1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "opcode/mips.h"
47 /* The sizes of floating point registers. */
51 MIPS_FPU_SINGLE_REGSIZE
= 4,
52 MIPS_FPU_DOUBLE_REGSIZE
= 8
55 /* All the possible MIPS ABIs. */
67 struct frame_extra_info
69 mips_extra_func_info_t proc_desc
;
73 /* Various MIPS ISA options (related to stack analysis) can be
74 overridden dynamically. Establish an enum/array for managing
77 static const char size_auto
[] = "auto";
78 static const char size_32
[] = "32";
79 static const char size_64
[] = "64";
81 static const char *size_enums
[] = {
88 /* Some MIPS boards don't support floating point while others only
89 support single-precision floating-point operations. See also
90 FP_REGISTER_DOUBLE. */
94 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
95 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
96 MIPS_FPU_NONE
/* No floating point. */
99 #ifndef MIPS_DEFAULT_FPU_TYPE
100 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
102 static int mips_fpu_type_auto
= 1;
103 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
104 #define MIPS_FPU_TYPE mips_fpu_type
106 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
107 #ifndef FP_REGISTER_DOUBLE
108 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
111 static int mips_debug
= 0;
113 /* MIPS specific per-architecture information */
116 /* from the elf header */
119 enum mips_abi mips_abi
;
120 const char *mips_abi_string
;
121 enum mips_fpu_type mips_fpu_type
;
122 int mips_last_arg_regnum
;
123 int mips_last_fp_arg_regnum
;
124 int mips_default_saved_regsize
;
125 int mips_fp_register_double
;
126 int mips_regs_have_home_p
;
127 int mips_default_stack_argsize
;
128 int gdb_target_is_mips64
;
129 int default_mask_address_p
;
134 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
135 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
139 #undef MIPS_LAST_FP_ARG_REGNUM
140 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
144 #undef MIPS_LAST_ARG_REGNUM
145 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
150 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
153 /* Return the currently configured (or set) saved register size. */
156 #undef MIPS_DEFAULT_SAVED_REGSIZE
157 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
158 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
159 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
162 static const char *mips_saved_regsize_string
= size_auto
;
164 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
167 mips_saved_regsize (void)
169 if (mips_saved_regsize_string
== size_auto
)
170 return MIPS_DEFAULT_SAVED_REGSIZE
;
171 else if (mips_saved_regsize_string
== size_64
)
173 else /* if (mips_saved_regsize_string == size_32) */
177 /* Indicate that the ABI makes use of double-precision registers
178 provided by the FPU (rather than combining pairs of registers to
179 form double-precision values). Do not use "TARGET_IS_MIPS64" to
180 determine if the ABI is using double-precision registers. See also
183 #undef FP_REGISTER_DOUBLE
184 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
187 /* Does the caller allocate a ``home'' for each register used in the
188 function call? The N32 ABI and MIPS_EABI do not, the others do. */
191 #undef MIPS_REGS_HAVE_HOME_P
192 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
193 #elif !defined (MIPS_REGS_HAVE_HOME_P)
194 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
197 /* The amount of space reserved on the stack for registers. This is
198 different to MIPS_SAVED_REGSIZE as it determines the alignment of
199 data allocated after the registers have run out. */
202 #undef MIPS_DEFAULT_STACK_ARGSIZE
203 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
204 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
205 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
208 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
210 static const char *mips_stack_argsize_string
= size_auto
;
213 mips_stack_argsize (void)
215 if (mips_stack_argsize_string
== size_auto
)
216 return MIPS_DEFAULT_STACK_ARGSIZE
;
217 else if (mips_stack_argsize_string
== size_64
)
219 else /* if (mips_stack_argsize_string == size_32) */
224 #undef GDB_TARGET_IS_MIPS64
225 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
229 #undef MIPS_DEFAULT_MASK_ADDRESS_P
230 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
231 #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P)
232 #define MIPS_DEFAULT_MASK_ADDRESS_P (0)
235 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
237 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
239 static void mips_print_register (int, int);
241 static mips_extra_func_info_t
242 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*);
244 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
246 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
248 int mips_set_processor_type (char *);
250 static void mips_show_processor_type_command (char *, int);
252 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
254 static mips_extra_func_info_t
255 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
);
257 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
258 mips_extra_func_info_t proc_desc
);
260 /* This value is the model of MIPS in use. It is derived from the value
261 of the PrID register. */
263 char *mips_processor_type
;
265 char *tmp_mips_processor_type
;
267 /* The list of available "set mips " and "show mips " commands */
269 static struct cmd_list_element
*setmipscmdlist
= NULL
;
270 static struct cmd_list_element
*showmipscmdlist
= NULL
;
272 /* A set of original names, to be used when restoring back to generic
273 registers from a specific set. */
275 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
276 char **mips_processor_reg_names
= mips_generic_reg_names
;
279 mips_register_name (int i
)
281 return mips_processor_reg_names
[i
];
284 /* Names of IDT R3041 registers. */
286 char *mips_r3041_reg_names
[] = {
287 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
288 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
289 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
290 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
291 "sr", "lo", "hi", "bad", "cause","pc",
292 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
293 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
294 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
295 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
296 "fsr", "fir", "fp", "",
297 "", "", "bus", "ccfg", "", "", "", "",
298 "", "", "port", "cmp", "", "", "epc", "prid",
301 /* Names of IDT R3051 registers. */
303 char *mips_r3051_reg_names
[] = {
304 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
305 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
306 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
307 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
308 "sr", "lo", "hi", "bad", "cause","pc",
309 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
310 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
311 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
312 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
313 "fsr", "fir", "fp", "",
314 "inx", "rand", "elo", "", "ctxt", "", "", "",
315 "", "", "ehi", "", "", "", "epc", "prid",
318 /* Names of IDT R3081 registers. */
320 char *mips_r3081_reg_names
[] = {
321 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
322 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
323 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
324 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
325 "sr", "lo", "hi", "bad", "cause","pc",
326 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
327 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
328 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
329 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
330 "fsr", "fir", "fp", "",
331 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
332 "", "", "ehi", "", "", "", "epc", "prid",
335 /* Names of LSI 33k registers. */
337 char *mips_lsi33k_reg_names
[] = {
338 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
339 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
340 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
341 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
342 "epc", "hi", "lo", "sr", "cause","badvaddr",
343 "dcic", "bpc", "bda", "", "", "", "", "",
344 "", "", "", "", "", "", "", "",
345 "", "", "", "", "", "", "", "",
346 "", "", "", "", "", "", "", "",
348 "", "", "", "", "", "", "", "",
349 "", "", "", "", "", "", "", "",
355 } mips_processor_type_table
[] = {
356 { "generic", mips_generic_reg_names
},
357 { "r3041", mips_r3041_reg_names
},
358 { "r3051", mips_r3051_reg_names
},
359 { "r3071", mips_r3081_reg_names
},
360 { "r3081", mips_r3081_reg_names
},
361 { "lsi33k", mips_lsi33k_reg_names
},
369 /* Table to translate MIPS16 register field to actual register number. */
370 static int mips16_to_32_reg
[8] =
371 {16, 17, 2, 3, 4, 5, 6, 7};
373 /* Heuristic_proc_start may hunt through the text section for a long
374 time across a 2400 baud serial line. Allows the user to limit this
377 static unsigned int heuristic_fence_post
= 0;
379 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
380 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
381 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
382 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
383 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
384 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
385 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
386 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
387 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
388 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
389 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
390 #define _PROC_MAGIC_ 0x0F0F0F0F
391 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
392 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
394 struct linked_proc_info
396 struct mips_extra_func_info info
;
397 struct linked_proc_info
*next
;
399 *linked_proc_desc_table
= NULL
;
402 mips_print_extra_frame_info (struct frame_info
*fi
)
406 && fi
->extra_info
->proc_desc
407 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
408 printf_filtered (" frame pointer is at %s+%s\n",
409 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
410 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
413 /* Convert between RAW and VIRTUAL registers. The RAW register size
414 defines the remote-gdb packet. */
416 static int mips64_transfers_32bit_regs_p
= 0;
419 mips_register_raw_size (int reg_nr
)
421 if (mips64_transfers_32bit_regs_p
)
422 return REGISTER_VIRTUAL_SIZE (reg_nr
);
423 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
424 && FP_REGISTER_DOUBLE
)
425 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
433 mips_register_convertible (int reg_nr
)
435 if (mips64_transfers_32bit_regs_p
)
438 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
442 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
443 char *raw_buf
, char *virt_buf
)
445 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
447 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
448 TYPE_LENGTH (virtual_type
));
452 TYPE_LENGTH (virtual_type
));
456 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
457 char *virt_buf
, char *raw_buf
)
459 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
460 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
461 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
463 TYPE_LENGTH (virtual_type
));
467 TYPE_LENGTH (virtual_type
));
470 /* Should the upper word of 64-bit addresses be zeroed? */
471 enum cmd_auto_boolean mask_address_var
= CMD_AUTO_BOOLEAN_AUTO
;
474 mips_mask_address_p (void)
476 switch (mask_address_var
)
478 case CMD_AUTO_BOOLEAN_TRUE
:
480 case CMD_AUTO_BOOLEAN_FALSE
:
483 case CMD_AUTO_BOOLEAN_AUTO
:
484 return MIPS_DEFAULT_MASK_ADDRESS_P
;
486 internal_error (__FILE__
, __LINE__
,
487 "mips_mask_address_p: bad switch");
493 show_mask_address (char *cmd
, int from_tty
)
495 switch (mask_address_var
)
497 case CMD_AUTO_BOOLEAN_TRUE
:
498 printf_filtered ("The 32 bit mips address mask is enabled\n");
500 case CMD_AUTO_BOOLEAN_FALSE
:
501 printf_filtered ("The 32 bit mips address mask is disabled\n");
503 case CMD_AUTO_BOOLEAN_AUTO
:
504 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
505 mips_mask_address_p () ? "enabled" : "disabled");
508 internal_error (__FILE__
, __LINE__
,
509 "show_mask_address: bad switch");
514 /* Should call_function allocate stack space for a struct return? */
516 mips_use_struct_convention (int gcc_p
, struct type
*type
)
519 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
521 return 1; /* Structures are returned by ref in extra arg0 */
524 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
527 pc_is_mips16 (bfd_vma memaddr
)
529 struct minimal_symbol
*sym
;
531 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
532 if (IS_MIPS16_ADDR (memaddr
))
535 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
536 the high bit of the info field. Use this to decide if the function is
537 MIPS16 or normal MIPS. */
538 sym
= lookup_minimal_symbol_by_pc (memaddr
);
540 return MSYMBOL_IS_SPECIAL (sym
);
545 /* MIPS believes that the PC has a sign extended value. Perhaphs the
546 all registers should be sign extended for simplicity? */
549 mips_read_pc (ptid_t ptid
)
551 return read_signed_register_pid (PC_REGNUM
, ptid
);
554 /* This returns the PC of the first inst after the prologue. If we can't
555 find the prologue, then return 0. */
558 after_prologue (CORE_ADDR pc
,
559 mips_extra_func_info_t proc_desc
)
561 struct symtab_and_line sal
;
562 CORE_ADDR func_addr
, func_end
;
565 proc_desc
= find_proc_desc (pc
, NULL
);
569 /* If function is frameless, then we need to do it the hard way. I
570 strongly suspect that frameless always means prologueless... */
571 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
572 && PROC_FRAME_OFFSET (proc_desc
) == 0)
576 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
577 return 0; /* Unknown */
579 sal
= find_pc_line (func_addr
, 0);
581 if (sal
.end
< func_end
)
584 /* The line after the prologue is after the end of the function. In this
585 case, tell the caller to find the prologue the hard way. */
590 /* Decode a MIPS32 instruction that saves a register in the stack, and
591 set the appropriate bit in the general register mask or float register mask
592 to indicate which register is saved. This is a helper function
593 for mips_find_saved_regs. */
596 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
597 unsigned long *float_mask
)
601 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
602 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
603 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
605 /* It might be possible to use the instruction to
606 find the offset, rather than the code below which
607 is based on things being in a certain order in the
608 frame, but figuring out what the instruction's offset
609 is relative to might be a little tricky. */
610 reg
= (inst
& 0x001f0000) >> 16;
611 *gen_mask
|= (1 << reg
);
613 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
614 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
615 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
618 reg
= ((inst
& 0x001f0000) >> 16);
619 *float_mask
|= (1 << reg
);
623 /* Decode a MIPS16 instruction that saves a register in the stack, and
624 set the appropriate bit in the general register or float register mask
625 to indicate which register is saved. This is a helper function
626 for mips_find_saved_regs. */
629 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
631 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
633 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
634 *gen_mask
|= (1 << reg
);
636 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
638 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
639 *gen_mask
|= (1 << reg
);
641 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
642 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
643 *gen_mask
|= (1 << RA_REGNUM
);
647 /* Fetch and return instruction from the specified location. If the PC
648 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
651 mips_fetch_instruction (CORE_ADDR addr
)
653 char buf
[MIPS_INSTLEN
];
657 if (pc_is_mips16 (addr
))
659 instlen
= MIPS16_INSTLEN
;
660 addr
= UNMAKE_MIPS16_ADDR (addr
);
663 instlen
= MIPS_INSTLEN
;
664 status
= read_memory_nobpt (addr
, buf
, instlen
);
666 memory_error (status
, addr
);
667 return extract_unsigned_integer (buf
, instlen
);
671 /* These the fields of 32 bit mips instructions */
672 #define mips32_op(x) (x >> 26)
673 #define itype_op(x) (x >> 26)
674 #define itype_rs(x) ((x >> 21) & 0x1f)
675 #define itype_rt(x) ((x >> 16) & 0x1f)
676 #define itype_immediate(x) (x & 0xffff)
678 #define jtype_op(x) (x >> 26)
679 #define jtype_target(x) (x & 0x03ffffff)
681 #define rtype_op(x) (x >> 26)
682 #define rtype_rs(x) ((x >> 21) & 0x1f)
683 #define rtype_rt(x) ((x >> 16) & 0x1f)
684 #define rtype_rd(x) ((x >> 11) & 0x1f)
685 #define rtype_shamt(x) ((x >> 6) & 0x1f)
686 #define rtype_funct(x) (x & 0x3f)
689 mips32_relative_offset (unsigned long inst
)
692 x
= itype_immediate (inst
);
693 if (x
& 0x8000) /* sign bit set */
695 x
|= 0xffff0000; /* sign extension */
701 /* Determine whate to set a single step breakpoint while considering
704 mips32_next_pc (CORE_ADDR pc
)
708 inst
= mips_fetch_instruction (pc
);
709 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
711 if (itype_op (inst
) >> 2 == 5)
712 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
714 op
= (itype_op (inst
) & 0x03);
729 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
730 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
732 int tf
= itype_rt (inst
) & 0x01;
733 int cnum
= itype_rt (inst
) >> 2;
734 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
735 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
737 if (((cond
>> cnum
) & 0x01) == tf
)
738 pc
+= mips32_relative_offset (inst
) + 4;
743 pc
+= 4; /* Not a branch, next instruction is easy */
746 { /* This gets way messy */
748 /* Further subdivide into SPECIAL, REGIMM and other */
749 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
751 case 0: /* SPECIAL */
752 op
= rtype_funct (inst
);
757 /* Set PC to that address */
758 pc
= read_signed_register (rtype_rs (inst
));
764 break; /* end SPECIAL */
767 op
= itype_rt (inst
); /* branch condition */
772 case 16: /* BLTZAL */
773 case 18: /* BLTZALL */
775 if (read_signed_register (itype_rs (inst
)) < 0)
776 pc
+= mips32_relative_offset (inst
) + 4;
778 pc
+= 8; /* after the delay slot */
782 case 17: /* BGEZAL */
783 case 19: /* BGEZALL */
784 greater_equal_branch
:
785 if (read_signed_register (itype_rs (inst
)) >= 0)
786 pc
+= mips32_relative_offset (inst
) + 4;
788 pc
+= 8; /* after the delay slot */
790 /* All of the other instructions in the REGIMM category */
795 break; /* end REGIMM */
800 reg
= jtype_target (inst
) << 2;
801 /* Upper four bits get never changed... */
802 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
805 /* FIXME case JALX : */
808 reg
= jtype_target (inst
) << 2;
809 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
810 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
812 break; /* The new PC will be alternate mode */
813 case 4: /* BEQ, BEQL */
815 if (read_signed_register (itype_rs (inst
)) ==
816 read_signed_register (itype_rt (inst
)))
817 pc
+= mips32_relative_offset (inst
) + 4;
821 case 5: /* BNE, BNEL */
823 if (read_signed_register (itype_rs (inst
)) !=
824 read_signed_register (itype_rt (inst
)))
825 pc
+= mips32_relative_offset (inst
) + 4;
829 case 6: /* BLEZ, BLEZL */
831 if (read_signed_register (itype_rs (inst
) <= 0))
832 pc
+= mips32_relative_offset (inst
) + 4;
838 greater_branch
: /* BGTZ, BGTZL */
839 if (read_signed_register (itype_rs (inst
) > 0))
840 pc
+= mips32_relative_offset (inst
) + 4;
847 } /* mips32_next_pc */
849 /* Decoding the next place to set a breakpoint is irregular for the
850 mips 16 variant, but fortunately, there fewer instructions. We have to cope
851 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
852 We dont want to set a single step instruction on the extend instruction
856 /* Lots of mips16 instruction formats */
857 /* Predicting jumps requires itype,ritype,i8type
858 and their extensions extItype,extritype,extI8type
860 enum mips16_inst_fmts
862 itype
, /* 0 immediate 5,10 */
863 ritype
, /* 1 5,3,8 */
864 rrtype
, /* 2 5,3,3,5 */
865 rritype
, /* 3 5,3,3,5 */
866 rrrtype
, /* 4 5,3,3,3,2 */
867 rriatype
, /* 5 5,3,3,1,4 */
868 shifttype
, /* 6 5,3,3,3,2 */
869 i8type
, /* 7 5,3,8 */
870 i8movtype
, /* 8 5,3,3,5 */
871 i8mov32rtype
, /* 9 5,3,5,3 */
872 i64type
, /* 10 5,3,8 */
873 ri64type
, /* 11 5,3,3,5 */
874 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
875 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
876 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
877 extRRItype
, /* 15 5,5,5,5,3,3,5 */
878 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
879 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
880 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
881 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
882 extRi64type
, /* 20 5,6,5,5,3,3,5 */
883 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
885 /* I am heaping all the fields of the formats into one structure and
886 then, only the fields which are involved in instruction extension */
890 unsigned int regx
; /* Function in i8 type */
895 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
896 for the bits which make up the immediatate extension. */
899 extended_offset (unsigned int extension
)
902 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
904 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
906 value
|= extension
& 0x01f; /* extract 4:0 */
910 /* Only call this function if you know that this is an extendable
911 instruction, It wont malfunction, but why make excess remote memory references?
912 If the immediate operands get sign extended or somthing, do it after
913 the extension is performed.
915 /* FIXME: Every one of these cases needs to worry about sign extension
916 when the offset is to be used in relative addressing */
920 fetch_mips_16 (CORE_ADDR pc
)
923 pc
&= 0xfffffffe; /* clear the low order bit */
924 target_read_memory (pc
, buf
, 2);
925 return extract_unsigned_integer (buf
, 2);
929 unpack_mips16 (CORE_ADDR pc
,
930 unsigned int extension
,
932 enum mips16_inst_fmts insn_format
,
933 struct upk_mips16
*upk
)
945 value
= extended_offset (extension
);
946 value
= value
<< 11; /* rom for the original value */
947 value
|= inst
& 0x7ff; /* eleven bits from instruction */
951 value
= inst
& 0x7ff;
952 /* FIXME : Consider sign extension */
961 { /* A register identifier and an offset */
962 /* Most of the fields are the same as I type but the
963 immediate value is of a different length */
967 value
= extended_offset (extension
);
968 value
= value
<< 8; /* from the original instruction */
969 value
|= inst
& 0xff; /* eleven bits from instruction */
970 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
971 if (value
& 0x4000) /* test the sign bit , bit 26 */
973 value
&= ~0x3fff; /* remove the sign bit */
979 value
= inst
& 0xff; /* 8 bits */
980 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
981 /* FIXME: Do sign extension , this format needs it */
982 if (value
& 0x80) /* THIS CONFUSES ME */
984 value
&= 0xef; /* remove the sign bit */
995 unsigned int nexthalf
;
996 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
998 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1006 internal_error (__FILE__
, __LINE__
,
1009 upk
->offset
= offset
;
1016 add_offset_16 (CORE_ADDR pc
, int offset
)
1018 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1023 extended_mips16_next_pc (CORE_ADDR pc
,
1024 unsigned int extension
,
1027 int op
= (insn
>> 11);
1030 case 2: /* Branch */
1033 struct upk_mips16 upk
;
1034 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1035 offset
= upk
.offset
;
1041 pc
+= (offset
<< 1) + 2;
1044 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1046 struct upk_mips16 upk
;
1047 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1048 pc
= add_offset_16 (pc
, upk
.offset
);
1049 if ((insn
>> 10) & 0x01) /* Exchange mode */
1050 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1057 struct upk_mips16 upk
;
1059 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1060 reg
= read_signed_register (upk
.regx
);
1062 pc
+= (upk
.offset
<< 1) + 2;
1069 struct upk_mips16 upk
;
1071 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1072 reg
= read_signed_register (upk
.regx
);
1074 pc
+= (upk
.offset
<< 1) + 2;
1079 case 12: /* I8 Formats btez btnez */
1081 struct upk_mips16 upk
;
1083 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1084 /* upk.regx contains the opcode */
1085 reg
= read_signed_register (24); /* Test register is 24 */
1086 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1087 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1088 /* pc = add_offset_16(pc,upk.offset) ; */
1089 pc
+= (upk
.offset
<< 1) + 2;
1094 case 29: /* RR Formats JR, JALR, JALR-RA */
1096 struct upk_mips16 upk
;
1097 /* upk.fmt = rrtype; */
1102 upk
.regx
= (insn
>> 8) & 0x07;
1103 upk
.regy
= (insn
>> 5) & 0x07;
1111 break; /* Function return instruction */
1117 break; /* BOGUS Guess */
1119 pc
= read_signed_register (reg
);
1126 /* This is an instruction extension. Fetch the real instruction
1127 (which follows the extension) and decode things based on
1131 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1144 mips16_next_pc (CORE_ADDR pc
)
1146 unsigned int insn
= fetch_mips_16 (pc
);
1147 return extended_mips16_next_pc (pc
, 0, insn
);
1150 /* The mips_next_pc function supports single_step when the remote
1151 target monitor or stub is not developed enough to do a single_step.
1152 It works by decoding the current instruction and predicting where a
1153 branch will go. This isnt hard because all the data is available.
1154 The MIPS32 and MIPS16 variants are quite different */
1156 mips_next_pc (CORE_ADDR pc
)
1159 return mips16_next_pc (pc
);
1161 return mips32_next_pc (pc
);
1164 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1168 mips_find_saved_regs (struct frame_info
*fci
)
1171 CORE_ADDR reg_position
;
1172 /* r0 bit means kernel trap */
1174 /* What registers have been saved? Bitmasks. */
1175 unsigned long gen_mask
, float_mask
;
1176 mips_extra_func_info_t proc_desc
;
1179 frame_saved_regs_zalloc (fci
);
1181 /* If it is the frame for sigtramp, the saved registers are located
1182 in a sigcontext structure somewhere on the stack.
1183 If the stack layout for sigtramp changes we might have to change these
1184 constants and the companion fixup_sigtramp in mdebugread.c */
1185 #ifndef SIGFRAME_BASE
1186 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1187 above the sigtramp frame. */
1188 #define SIGFRAME_BASE MIPS_REGSIZE
1189 /* FIXME! Are these correct?? */
1190 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1191 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1192 #define SIGFRAME_FPREGSAVE_OFF \
1193 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1195 #ifndef SIGFRAME_REG_SIZE
1196 /* FIXME! Is this correct?? */
1197 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1199 if (fci
->signal_handler_caller
)
1201 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1203 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1204 + ireg
* SIGFRAME_REG_SIZE
;
1205 fci
->saved_regs
[ireg
] = reg_position
;
1207 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1209 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1210 + ireg
* SIGFRAME_REG_SIZE
;
1211 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1213 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1217 proc_desc
= fci
->extra_info
->proc_desc
;
1218 if (proc_desc
== NULL
)
1219 /* I'm not sure how/whether this can happen. Normally when we can't
1220 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1221 and set the saved_regs right away. */
1224 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1225 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1226 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1228 if ( /* In any frame other than the innermost or a frame interrupted by
1229 a signal, we assume that all registers have been saved.
1230 This assumes that all register saves in a function happen before
1231 the first function call. */
1232 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1234 /* In a dummy frame we know exactly where things are saved. */
1235 && !PROC_DESC_IS_DUMMY (proc_desc
)
1237 /* Don't bother unless we are inside a function prologue. Outside the
1238 prologue, we know where everything is. */
1240 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1242 /* Not sure exactly what kernel_trap means, but if it means
1243 the kernel saves the registers without a prologue doing it,
1244 we better not examine the prologue to see whether registers
1245 have been saved yet. */
1248 /* We need to figure out whether the registers that the proc_desc
1249 claims are saved have been saved yet. */
1253 /* Bitmasks; set if we have found a save for the register. */
1254 unsigned long gen_save_found
= 0;
1255 unsigned long float_save_found
= 0;
1258 /* If the address is odd, assume this is MIPS16 code. */
1259 addr
= PROC_LOW_ADDR (proc_desc
);
1260 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1262 /* Scan through this function's instructions preceding the current
1263 PC, and look for those that save registers. */
1264 while (addr
< fci
->pc
)
1266 inst
= mips_fetch_instruction (addr
);
1267 if (pc_is_mips16 (addr
))
1268 mips16_decode_reg_save (inst
, &gen_save_found
);
1270 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1273 gen_mask
= gen_save_found
;
1274 float_mask
= float_save_found
;
1277 /* Fill in the offsets for the registers which gen_mask says
1279 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1280 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1281 if (gen_mask
& 0x80000000)
1283 fci
->saved_regs
[ireg
] = reg_position
;
1284 reg_position
-= MIPS_SAVED_REGSIZE
;
1287 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1288 of that normally used by gcc. Therefore, we have to fetch the first
1289 instruction of the function, and if it's an entry instruction that
1290 saves $s0 or $s1, correct their saved addresses. */
1291 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1293 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1294 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1297 int sreg_count
= (inst
>> 6) & 3;
1299 /* Check if the ra register was pushed on the stack. */
1300 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1302 reg_position
-= MIPS_SAVED_REGSIZE
;
1304 /* Check if the s0 and s1 registers were pushed on the stack. */
1305 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1307 fci
->saved_regs
[reg
] = reg_position
;
1308 reg_position
-= MIPS_SAVED_REGSIZE
;
1313 /* Fill in the offsets for the registers which float_mask says
1315 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1317 /* The freg_offset points to where the first *double* register
1318 is saved. So skip to the high-order word. */
1319 if (!GDB_TARGET_IS_MIPS64
)
1320 reg_position
+= MIPS_SAVED_REGSIZE
;
1322 /* Fill in the offsets for the float registers which float_mask says
1324 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1325 if (float_mask
& 0x80000000)
1327 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1328 reg_position
-= MIPS_SAVED_REGSIZE
;
1331 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1335 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1337 for (; fi
; fi
= fi
->next
)
1339 /* We have to get the saved sp from the sigcontext
1340 if it is a signal handler frame. */
1341 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1345 if (fi
->saved_regs
== NULL
)
1346 mips_find_saved_regs (fi
);
1347 if (fi
->saved_regs
[regno
])
1348 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1351 return read_signed_register (regno
);
1354 /* mips_addr_bits_remove - remove useless address bits */
1357 mips_addr_bits_remove (CORE_ADDR addr
)
1359 if (GDB_TARGET_IS_MIPS64
)
1361 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1363 /* This hack is a work-around for existing boards using
1364 PMON, the simulator, and any other 64-bit targets that
1365 doesn't have true 64-bit addressing. On these targets,
1366 the upper 32 bits of addresses are ignored by the
1367 hardware. Thus, the PC or SP are likely to have been
1368 sign extended to all 1s by instruction sequences that
1369 load 32-bit addresses. For example, a typical piece of
1370 code that loads an address is this:
1371 lui $r2, <upper 16 bits>
1372 ori $r2, <lower 16 bits>
1373 But the lui sign-extends the value such that the upper 32
1374 bits may be all 1s. The workaround is simply to mask off
1375 these bits. In the future, gcc may be changed to support
1376 true 64-bit addressing, and this masking will have to be
1378 addr
&= (CORE_ADDR
) 0xffffffff;
1381 else if (mips_mask_address_p ())
1383 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1384 masking off bits, instead, the actual target should be asking
1385 for the address to be converted to a valid pointer. */
1386 /* Even when GDB is configured for some 32-bit targets
1387 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1388 so CORE_ADDR is 64 bits. So we still have to mask off
1389 useless bits from addresses. */
1390 addr
&= (CORE_ADDR
) 0xffffffff;
1395 /* mips_software_single_step() is called just before we want to resume
1396 the inferior, if we want to single-step it but there is no hardware
1397 or kernel single-step support (MIPS on Linux for example). We find
1398 the target of the coming instruction and breakpoint it.
1400 single_step is also called just after the inferior stops. If we had
1401 set up a simulated single-step, we undo our damage. */
1404 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1406 static CORE_ADDR next_pc
;
1407 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1408 static binsn_quantum break_mem
;
1411 if (insert_breakpoints_p
)
1413 pc
= read_register (PC_REGNUM
);
1414 next_pc
= mips_next_pc (pc
);
1416 target_insert_breakpoint (next_pc
, break_mem
);
1419 target_remove_breakpoint (next_pc
, break_mem
);
1423 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1427 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1428 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1429 tmp
= mips_skip_stub (pc
);
1430 prev
->pc
= tmp
? tmp
: pc
;
1435 mips_frame_saved_pc (struct frame_info
*frame
)
1438 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1439 /* We have to get the saved pc from the sigcontext
1440 if it is a signal handler frame. */
1441 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1442 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1444 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1445 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1447 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1449 return ADDR_BITS_REMOVE (saved_pc
);
1452 static struct mips_extra_func_info temp_proc_desc
;
1453 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1455 /* Set a register's saved stack address in temp_saved_regs. If an address
1456 has already been set for this register, do nothing; this way we will
1457 only recognize the first save of a given register in a function prologue.
1458 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1461 set_reg_offset (int regno
, CORE_ADDR offset
)
1463 if (temp_saved_regs
[regno
] == 0)
1464 temp_saved_regs
[regno
] = offset
;
1468 /* Test whether the PC points to the return instruction at the
1469 end of a function. */
1472 mips_about_to_return (CORE_ADDR pc
)
1474 if (pc_is_mips16 (pc
))
1475 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1476 generates a "jr $ra"; other times it generates code to load
1477 the return address from the stack to an accessible register (such
1478 as $a3), then a "jr" using that register. This second case
1479 is almost impossible to distinguish from an indirect jump
1480 used for switch statements, so we don't even try. */
1481 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1483 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1487 /* This fencepost looks highly suspicious to me. Removing it also
1488 seems suspicious as it could affect remote debugging across serial
1492 heuristic_proc_start (CORE_ADDR pc
)
1499 pc
= ADDR_BITS_REMOVE (pc
);
1501 fence
= start_pc
- heuristic_fence_post
;
1505 if (heuristic_fence_post
== UINT_MAX
1506 || fence
< VM_MIN_ADDRESS
)
1507 fence
= VM_MIN_ADDRESS
;
1509 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1511 /* search back for previous return */
1512 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1513 if (start_pc
< fence
)
1515 /* It's not clear to me why we reach this point when
1516 stop_soon_quietly, but with this test, at least we
1517 don't print out warnings for every child forked (eg, on
1518 decstation). 22apr93 rich@cygnus.com. */
1519 if (!stop_soon_quietly
)
1521 static int blurb_printed
= 0;
1523 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1528 /* This actually happens frequently in embedded
1529 development, when you first connect to a board
1530 and your stack pointer and pc are nowhere in
1531 particular. This message needs to give people
1532 in that situation enough information to
1533 determine that it's no big deal. */
1534 printf_filtered ("\n\
1535 GDB is unable to find the start of the function at 0x%s\n\
1536 and thus can't determine the size of that function's stack frame.\n\
1537 This means that GDB may be unable to access that stack frame, or\n\
1538 the frames below it.\n\
1539 This problem is most likely caused by an invalid program counter or\n\
1541 However, if you think GDB should simply search farther back\n\
1542 from 0x%s for code which looks like the beginning of a\n\
1543 function, you can increase the range of the search using the `set\n\
1544 heuristic-fence-post' command.\n",
1545 paddr_nz (pc
), paddr_nz (pc
));
1552 else if (pc_is_mips16 (start_pc
))
1554 unsigned short inst
;
1556 /* On MIPS16, any one of the following is likely to be the
1557 start of a function:
1561 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1562 inst
= mips_fetch_instruction (start_pc
);
1563 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1564 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1565 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1566 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1568 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1569 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1574 else if (mips_about_to_return (start_pc
))
1576 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1583 /* Fetch the immediate value from a MIPS16 instruction.
1584 If the previous instruction was an EXTEND, use it to extend
1585 the upper bits of the immediate value. This is a helper function
1586 for mips16_heuristic_proc_desc. */
1589 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1590 unsigned short inst
, /* current instruction */
1591 int nbits
, /* number of bits in imm field */
1592 int scale
, /* scale factor to be applied to imm */
1593 int is_signed
) /* is the imm field signed? */
1597 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1599 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1600 if (offset
& 0x8000) /* check for negative extend */
1601 offset
= 0 - (0x10000 - (offset
& 0xffff));
1602 return offset
| (inst
& 0x1f);
1606 int max_imm
= 1 << nbits
;
1607 int mask
= max_imm
- 1;
1608 int sign_bit
= max_imm
>> 1;
1610 offset
= inst
& mask
;
1611 if (is_signed
&& (offset
& sign_bit
))
1612 offset
= 0 - (max_imm
- offset
);
1613 return offset
* scale
;
1618 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1619 stream from start_pc to limit_pc. */
1622 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1623 struct frame_info
*next_frame
, CORE_ADDR sp
)
1626 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1627 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1628 unsigned inst
= 0; /* current instruction */
1629 unsigned entry_inst
= 0; /* the entry instruction */
1632 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1633 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1635 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1637 /* Save the previous instruction. If it's an EXTEND, we'll extract
1638 the immediate offset extension from it in mips16_get_imm. */
1641 /* Fetch and decode the instruction. */
1642 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1643 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1644 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1646 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1647 if (offset
< 0) /* negative stack adjustment? */
1648 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1650 /* Exit loop if a positive stack adjustment is found, which
1651 usually means that the stack cleanup code in the function
1652 epilogue is reached. */
1655 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1657 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1658 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1659 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1660 set_reg_offset (reg
, sp
+ offset
);
1662 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1664 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1665 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1666 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1667 set_reg_offset (reg
, sp
+ offset
);
1669 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1671 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1672 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1673 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1675 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1677 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1678 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1679 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1681 else if (inst
== 0x673d) /* move $s1, $sp */
1684 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1686 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1688 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1689 frame_addr
= sp
+ offset
;
1690 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1691 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1693 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1695 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1696 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1697 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1698 set_reg_offset (reg
, frame_addr
+ offset
);
1700 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1702 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1703 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1704 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1705 set_reg_offset (reg
, frame_addr
+ offset
);
1707 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1708 entry_inst
= inst
; /* save for later processing */
1709 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1710 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1713 /* The entry instruction is typically the first instruction in a function,
1714 and it stores registers at offsets relative to the value of the old SP
1715 (before the prologue). But the value of the sp parameter to this
1716 function is the new SP (after the prologue has been executed). So we
1717 can't calculate those offsets until we've seen the entire prologue,
1718 and can calculate what the old SP must have been. */
1719 if (entry_inst
!= 0)
1721 int areg_count
= (entry_inst
>> 8) & 7;
1722 int sreg_count
= (entry_inst
>> 6) & 3;
1724 /* The entry instruction always subtracts 32 from the SP. */
1725 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1727 /* Now we can calculate what the SP must have been at the
1728 start of the function prologue. */
1729 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1731 /* Check if a0-a3 were saved in the caller's argument save area. */
1732 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1734 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1735 set_reg_offset (reg
, sp
+ offset
);
1736 offset
+= MIPS_SAVED_REGSIZE
;
1739 /* Check if the ra register was pushed on the stack. */
1741 if (entry_inst
& 0x20)
1743 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1744 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1745 offset
-= MIPS_SAVED_REGSIZE
;
1748 /* Check if the s0 and s1 registers were pushed on the stack. */
1749 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1751 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1752 set_reg_offset (reg
, sp
+ offset
);
1753 offset
-= MIPS_SAVED_REGSIZE
;
1759 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1760 struct frame_info
*next_frame
, CORE_ADDR sp
)
1763 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1765 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1766 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1767 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1768 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1770 unsigned long inst
, high_word
, low_word
;
1773 /* Fetch the instruction. */
1774 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1776 /* Save some code by pre-extracting some useful fields. */
1777 high_word
= (inst
>> 16) & 0xffff;
1778 low_word
= inst
& 0xffff;
1779 reg
= high_word
& 0x1f;
1781 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1782 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1783 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1785 if (low_word
& 0x8000) /* negative stack adjustment? */
1786 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1788 /* Exit loop if a positive stack adjustment is found, which
1789 usually means that the stack cleanup code in the function
1790 epilogue is reached. */
1793 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1795 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1796 set_reg_offset (reg
, sp
+ low_word
);
1798 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1800 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1801 but the register size used is only 32 bits. Make the address
1802 for the saved register point to the lower 32 bits. */
1803 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1804 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1806 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1808 /* Old gcc frame, r30 is virtual frame pointer. */
1809 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1810 frame_addr
= sp
+ low_word
;
1811 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1813 unsigned alloca_adjust
;
1814 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1815 frame_addr
= read_next_frame_reg (next_frame
, 30);
1816 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1817 if (alloca_adjust
> 0)
1819 /* FP > SP + frame_size. This may be because
1820 * of an alloca or somethings similar.
1821 * Fix sp to "pre-alloca" value, and try again.
1823 sp
+= alloca_adjust
;
1828 /* move $30,$sp. With different versions of gas this will be either
1829 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1830 Accept any one of these. */
1831 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1833 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1834 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1836 unsigned alloca_adjust
;
1837 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1838 frame_addr
= read_next_frame_reg (next_frame
, 30);
1839 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1840 if (alloca_adjust
> 0)
1842 /* FP > SP + frame_size. This may be because
1843 * of an alloca or somethings similar.
1844 * Fix sp to "pre-alloca" value, and try again.
1846 sp
+= alloca_adjust
;
1851 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1853 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1854 set_reg_offset (reg
, frame_addr
+ low_word
);
1859 static mips_extra_func_info_t
1860 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1861 struct frame_info
*next_frame
)
1863 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1867 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1868 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1869 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1870 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1871 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1873 if (start_pc
+ 200 < limit_pc
)
1874 limit_pc
= start_pc
+ 200;
1875 if (pc_is_mips16 (start_pc
))
1876 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1878 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1879 return &temp_proc_desc
;
1882 static mips_extra_func_info_t
1883 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1885 CORE_ADDR startaddr
;
1886 mips_extra_func_info_t proc_desc
;
1887 struct block
*b
= block_for_pc (pc
);
1890 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1892 *addrptr
= startaddr
;
1893 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1897 if (startaddr
> BLOCK_START (b
))
1898 /* This is the "pathological" case referred to in a comment in
1899 print_frame_info. It might be better to move this check into
1903 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1906 /* If we never found a PDR for this function in symbol reading, then
1907 examine prologues to find the information. */
1910 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1911 if (PROC_FRAME_REG (proc_desc
) == -1)
1921 static mips_extra_func_info_t
1922 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
)
1924 mips_extra_func_info_t proc_desc
;
1925 CORE_ADDR startaddr
;
1927 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1931 /* IF this is the topmost frame AND
1932 * (this proc does not have debugging information OR
1933 * the PC is in the procedure prologue)
1934 * THEN create a "heuristic" proc_desc (by analyzing
1935 * the actual code) to replace the "official" proc_desc.
1937 if (next_frame
== NULL
)
1939 struct symtab_and_line val
;
1940 struct symbol
*proc_symbol
=
1941 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1945 val
= find_pc_line (BLOCK_START
1946 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1948 val
.pc
= val
.end
? val
.end
: pc
;
1950 if (!proc_symbol
|| pc
< val
.pc
)
1952 mips_extra_func_info_t found_heuristic
=
1953 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1955 if (found_heuristic
)
1956 proc_desc
= found_heuristic
;
1962 /* Is linked_proc_desc_table really necessary? It only seems to be used
1963 by procedure call dummys. However, the procedures being called ought
1964 to have their own proc_descs, and even if they don't,
1965 heuristic_proc_desc knows how to create them! */
1967 register struct linked_proc_info
*link
;
1969 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1970 if (PROC_LOW_ADDR (&link
->info
) <= pc
1971 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1975 startaddr
= heuristic_proc_start (pc
);
1978 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1984 get_frame_pointer (struct frame_info
*frame
,
1985 mips_extra_func_info_t proc_desc
)
1987 return ADDR_BITS_REMOVE (
1988 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1989 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1992 mips_extra_func_info_t cached_proc_desc
;
1995 mips_frame_chain (struct frame_info
*frame
)
1997 mips_extra_func_info_t proc_desc
;
1999 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2001 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2004 /* Check if the PC is inside a call stub. If it is, fetch the
2005 PC of the caller of that stub. */
2006 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2009 /* Look up the procedure descriptor for this PC. */
2010 proc_desc
= find_proc_desc (saved_pc
, frame
);
2014 cached_proc_desc
= proc_desc
;
2016 /* If no frame pointer and frame size is zero, we must be at end
2017 of stack (or otherwise hosed). If we don't check frame size,
2018 we loop forever if we see a zero size frame. */
2019 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2020 && PROC_FRAME_OFFSET (proc_desc
) == 0
2021 /* The previous frame from a sigtramp frame might be frameless
2022 and have frame size zero. */
2023 && !frame
->signal_handler_caller
)
2026 return get_frame_pointer (frame
, proc_desc
);
2030 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2034 /* Use proc_desc calculated in frame_chain */
2035 mips_extra_func_info_t proc_desc
=
2036 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
2038 fci
->extra_info
= (struct frame_extra_info
*)
2039 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2041 fci
->saved_regs
= NULL
;
2042 fci
->extra_info
->proc_desc
=
2043 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2046 /* Fixup frame-pointer - only needed for top frame */
2047 /* This may not be quite right, if proc has a real frame register.
2048 Get the value of the frame relative sp, procedure might have been
2049 interrupted by a signal at it's very start. */
2050 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2051 && !PROC_DESC_IS_DUMMY (proc_desc
))
2052 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2054 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2056 if (proc_desc
== &temp_proc_desc
)
2060 /* Do not set the saved registers for a sigtramp frame,
2061 mips_find_saved_registers will do that for us.
2062 We can't use fci->signal_handler_caller, it is not yet set. */
2063 find_pc_partial_function (fci
->pc
, &name
,
2064 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2065 if (!IN_SIGTRAMP (fci
->pc
, name
))
2067 frame_saved_regs_zalloc (fci
);
2068 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2069 fci
->saved_regs
[PC_REGNUM
]
2070 = fci
->saved_regs
[RA_REGNUM
];
2074 /* hack: if argument regs are saved, guess these contain args */
2075 /* assume we can't tell how many args for now */
2076 fci
->extra_info
->num_args
= -1;
2077 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2079 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2081 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2088 /* MIPS stack frames are almost impenetrable. When execution stops,
2089 we basically have to look at symbol information for the function
2090 that we stopped in, which tells us *which* register (if any) is
2091 the base of the frame pointer, and what offset from that register
2092 the frame itself is at.
2094 This presents a problem when trying to examine a stack in memory
2095 (that isn't executing at the moment), using the "frame" command. We
2096 don't have a PC, nor do we have any registers except SP.
2098 This routine takes two arguments, SP and PC, and tries to make the
2099 cached frames look as if these two arguments defined a frame on the
2100 cache. This allows the rest of info frame to extract the important
2101 arguments without difficulty. */
2104 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2107 error ("MIPS frame specifications require two arguments: sp and pc");
2109 return create_new_frame (argv
[0], argv
[1]);
2112 /* According to the current ABI, should the type be passed in a
2113 floating-point register (assuming that there is space)? When there
2114 is no FPU, FP are not even considered as possibile candidates for
2115 FP registers and, consequently this returns false - forces FP
2116 arguments into integer registers. */
2119 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2121 return ((typecode
== TYPE_CODE_FLT
2123 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2124 && TYPE_NFIELDS (arg_type
) == 1
2125 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2126 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2130 mips_push_arguments (int nargs
,
2134 CORE_ADDR struct_addr
)
2140 int stack_offset
= 0;
2142 /* Macros to round N up or down to the next A boundary; A must be
2144 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2145 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2147 /* First ensure that the stack and structure return address (if any)
2148 are properly aligned. The stack has to be at least 64-bit aligned
2149 even on 32-bit machines, because doubles must be 64-bit aligned.
2150 On at least one MIPS variant, stack frames need to be 128-bit
2151 aligned, so we round to this widest known alignment. */
2152 sp
= ROUND_DOWN (sp
, 16);
2153 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2155 /* Now make space on the stack for the args. We allocate more
2156 than necessary for EABI, because the first few arguments are
2157 passed in registers, but that's OK. */
2158 for (argnum
= 0; argnum
< nargs
; argnum
++)
2159 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2160 sp
-= ROUND_UP (len
, 16);
2163 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2164 (long) sp
, ROUND_UP (len
, 16));
2166 /* Initialize the integer and float register pointers. */
2168 float_argreg
= FPA0_REGNUM
;
2170 /* the struct_return pointer occupies the first parameter-passing reg */
2174 fprintf_unfiltered (gdb_stdlog
,
2175 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2176 argreg
, (long) struct_addr
);
2177 write_register (argreg
++, struct_addr
);
2178 if (MIPS_REGS_HAVE_HOME_P
)
2179 stack_offset
+= MIPS_STACK_ARGSIZE
;
2182 /* Now load as many as possible of the first arguments into
2183 registers, and push the rest onto the stack. Loop thru args
2184 from first to last. */
2185 for (argnum
= 0; argnum
< nargs
; argnum
++)
2188 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2189 value_ptr arg
= args
[argnum
];
2190 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2191 int len
= TYPE_LENGTH (arg_type
);
2192 enum type_code typecode
= TYPE_CODE (arg_type
);
2195 fprintf_unfiltered (gdb_stdlog
,
2196 "mips_push_arguments: %d len=%d type=%d",
2197 argnum
+ 1, len
, (int) typecode
);
2199 /* The EABI passes structures that do not fit in a register by
2200 reference. In all other cases, pass the structure by value. */
2202 && len
> MIPS_SAVED_REGSIZE
2203 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2205 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2206 typecode
= TYPE_CODE_PTR
;
2207 len
= MIPS_SAVED_REGSIZE
;
2210 fprintf_unfiltered (gdb_stdlog
, " push");
2213 val
= (char *) VALUE_CONTENTS (arg
);
2215 /* 32-bit ABIs always start floating point arguments in an
2216 even-numbered floating point register. Round the FP register
2217 up before the check to see if there are any FP registers
2218 left. Non MIPS_EABI targets also pass the FP in the integer
2219 registers so also round up normal registers. */
2220 if (!FP_REGISTER_DOUBLE
2221 && fp_register_arg_p (typecode
, arg_type
))
2223 if ((float_argreg
& 1))
2227 /* Floating point arguments passed in registers have to be
2228 treated specially. On 32-bit architectures, doubles
2229 are passed in register pairs; the even register gets
2230 the low word, and the odd register gets the high word.
2231 On non-EABI processors, the first two floating point arguments are
2232 also copied to general registers, because MIPS16 functions
2233 don't use float registers for arguments. This duplication of
2234 arguments in general registers can't hurt non-MIPS16 functions
2235 because those registers are normally skipped. */
2236 /* MIPS_EABI squeezes a struct that contains a single floating
2237 point value into an FP register instead of pushing it onto the
2239 if (fp_register_arg_p (typecode
, arg_type
)
2240 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2242 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2244 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2245 unsigned long regval
;
2247 /* Write the low word of the double to the even register(s). */
2248 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2250 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2251 float_argreg
, phex (regval
, 4));
2252 write_register (float_argreg
++, regval
);
2256 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2257 argreg
, phex (regval
, 4));
2258 write_register (argreg
++, regval
);
2261 /* Write the high word of the double to the odd register(s). */
2262 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2264 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2265 float_argreg
, phex (regval
, 4));
2266 write_register (float_argreg
++, regval
);
2270 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2271 argreg
, phex (regval
, 4));
2272 write_register (argreg
++, regval
);
2278 /* This is a floating point value that fits entirely
2279 in a single register. */
2280 /* On 32 bit ABI's the float_argreg is further adjusted
2281 above to ensure that it is even register aligned. */
2282 LONGEST regval
= extract_unsigned_integer (val
, len
);
2284 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2285 float_argreg
, phex (regval
, len
));
2286 write_register (float_argreg
++, regval
);
2289 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2290 registers for each argument. The below is (my
2291 guess) to ensure that the corresponding integer
2292 register has reserved the same space. */
2294 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2295 argreg
, phex (regval
, len
));
2296 write_register (argreg
, regval
);
2297 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2300 /* Reserve space for the FP register. */
2301 if (MIPS_REGS_HAVE_HOME_P
)
2302 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2306 /* Copy the argument to general registers or the stack in
2307 register-sized pieces. Large arguments are split between
2308 registers and stack. */
2309 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2310 are treated specially: Irix cc passes them in registers
2311 where gcc sometimes puts them on the stack. For maximum
2312 compatibility, we will put them in both places. */
2313 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2314 (len
% MIPS_SAVED_REGSIZE
!= 0));
2315 /* Note: Floating-point values that didn't fit into an FP
2316 register are only written to memory. */
2319 /* Rememer if the argument was written to the stack. */
2320 int stack_used_p
= 0;
2321 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2324 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2327 /* Write this portion of the argument to the stack. */
2328 if (argreg
> MIPS_LAST_ARG_REGNUM
2330 || fp_register_arg_p (typecode
, arg_type
))
2332 /* Should shorter than int integer values be
2333 promoted to int before being stored? */
2334 int longword_offset
= 0;
2337 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2339 if (MIPS_STACK_ARGSIZE
== 8 &&
2340 (typecode
== TYPE_CODE_INT
||
2341 typecode
== TYPE_CODE_PTR
||
2342 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2343 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2344 else if ((typecode
== TYPE_CODE_STRUCT
||
2345 typecode
== TYPE_CODE_UNION
) &&
2346 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2347 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2352 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2353 (long) stack_offset
);
2354 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2355 (long) longword_offset
);
2358 addr
= sp
+ stack_offset
+ longword_offset
;
2363 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2364 for (i
= 0; i
< partial_len
; i
++)
2366 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2369 write_memory (addr
, val
, partial_len
);
2372 /* Note!!! This is NOT an else clause. Odd sized
2373 structs may go thru BOTH paths. Floating point
2374 arguments will not. */
2375 /* Write this portion of the argument to a general
2376 purpose register. */
2377 if (argreg
<= MIPS_LAST_ARG_REGNUM
2378 && !fp_register_arg_p (typecode
, arg_type
))
2380 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2382 /* A non-floating-point argument being passed in a
2383 general register. If a struct or union, and if
2384 the remaining length is smaller than the register
2385 size, we have to adjust the register value on
2388 It does not seem to be necessary to do the
2389 same for integral types.
2391 Also don't do this adjustment on EABI and O64
2395 && MIPS_SAVED_REGSIZE
< 8
2396 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2397 && partial_len
< MIPS_SAVED_REGSIZE
2398 && (typecode
== TYPE_CODE_STRUCT
||
2399 typecode
== TYPE_CODE_UNION
))
2400 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2404 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2406 phex (regval
, MIPS_SAVED_REGSIZE
));
2407 write_register (argreg
, regval
);
2410 /* If this is the old ABI, prevent subsequent floating
2411 point arguments from being passed in floating point
2414 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2420 /* Compute the the offset into the stack at which we
2421 will copy the next parameter.
2423 In older ABIs, the caller reserved space for
2424 registers that contained arguments. This was loosely
2425 refered to as their "home". Consequently, space is
2428 In the new EABI (and the NABI32), the stack_offset
2429 only needs to be adjusted when it has been used.. */
2431 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2432 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2436 fprintf_unfiltered (gdb_stdlog
, "\n");
2439 /* Return adjusted stack pointer. */
2444 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2446 /* Set the return address register to point to the entry
2447 point of the program, where a breakpoint lies in wait. */
2448 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2453 mips_push_register (CORE_ADDR
* sp
, int regno
)
2455 char buffer
[MAX_REGISTER_RAW_SIZE
];
2458 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2460 regsize
= MIPS_SAVED_REGSIZE
;
2461 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2462 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2467 regsize
= REGISTER_RAW_SIZE (regno
);
2471 read_register_gen (regno
, buffer
);
2472 write_memory (*sp
, buffer
+ offset
, regsize
);
2475 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2476 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2479 mips_push_dummy_frame (void)
2482 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2483 xmalloc (sizeof (struct linked_proc_info
));
2484 mips_extra_func_info_t proc_desc
= &link
->info
;
2485 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2486 CORE_ADDR old_sp
= sp
;
2487 link
->next
= linked_proc_desc_table
;
2488 linked_proc_desc_table
= link
;
2490 /* FIXME! are these correct ? */
2491 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2492 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2493 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2494 #define FLOAT_SINGLE_REG_SAVE_MASK \
2495 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2497 * The registers we must save are all those not preserved across
2498 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2499 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2500 * and FP Control/Status registers.
2503 * Dummy frame layout:
2506 * Saved MMHI, MMLO, FPC_CSR
2511 * Saved D18 (i.e. F19, F18)
2513 * Saved D0 (i.e. F1, F0)
2514 * Argument build area and stack arguments written via mips_push_arguments
2518 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2519 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2520 PROC_FRAME_OFFSET (proc_desc
) = 0;
2521 PROC_FRAME_ADJUST (proc_desc
) = 0;
2522 mips_push_register (&sp
, PC_REGNUM
);
2523 mips_push_register (&sp
, HI_REGNUM
);
2524 mips_push_register (&sp
, LO_REGNUM
);
2525 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2527 /* Save general CPU registers */
2528 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2529 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2530 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2531 for (ireg
= 32; --ireg
>= 0;)
2532 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2533 mips_push_register (&sp
, ireg
);
2535 /* Save floating point registers starting with high order word */
2536 PROC_FREG_MASK (proc_desc
) =
2537 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2538 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2539 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2541 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2542 for (ireg
= 32; --ireg
>= 0;)
2543 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2544 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2546 /* Update the frame pointer for the call dummy and the stack pointer.
2547 Set the procedure's starting and ending addresses to point to the
2548 call dummy address at the entry point. */
2549 write_register (PUSH_FP_REGNUM
, old_sp
);
2550 write_register (SP_REGNUM
, sp
);
2551 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2552 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2553 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2554 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2558 mips_pop_frame (void)
2560 register int regnum
;
2561 struct frame_info
*frame
= get_current_frame ();
2562 CORE_ADDR new_sp
= FRAME_FP (frame
);
2564 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2566 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2567 if (frame
->saved_regs
== NULL
)
2568 mips_find_saved_regs (frame
);
2569 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2571 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2572 && frame
->saved_regs
[regnum
])
2573 write_register (regnum
,
2574 read_memory_integer (frame
->saved_regs
[regnum
],
2575 MIPS_SAVED_REGSIZE
));
2577 write_register (SP_REGNUM
, new_sp
);
2578 flush_cached_frames ();
2580 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2582 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2584 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2586 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2588 if (&pi_ptr
->info
== proc_desc
)
2593 error ("Can't locate dummy extra frame info\n");
2595 if (prev_ptr
!= NULL
)
2596 prev_ptr
->next
= pi_ptr
->next
;
2598 linked_proc_desc_table
= pi_ptr
->next
;
2602 write_register (HI_REGNUM
,
2603 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2604 MIPS_SAVED_REGSIZE
));
2605 write_register (LO_REGNUM
,
2606 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2607 MIPS_SAVED_REGSIZE
));
2608 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2609 write_register (FCRCS_REGNUM
,
2610 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2611 MIPS_SAVED_REGSIZE
));
2616 mips_print_register (int regnum
, int all
)
2618 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2620 /* Get the data in raw format. */
2621 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2623 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2627 /* If an even floating point register, also print as double. */
2628 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2629 && !((regnum
- FP0_REGNUM
) & 1))
2630 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2632 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2634 read_relative_register_raw_bytes (regnum
, dbuffer
);
2635 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2636 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2638 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2639 val_print (builtin_type_double
, dbuffer
, 0, 0,
2640 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2641 printf_filtered ("); ");
2643 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2645 /* The problem with printing numeric register names (r26, etc.) is that
2646 the user can't use them on input. Probably the best solution is to
2647 fix it so that either the numeric or the funky (a2, etc.) names
2648 are accepted on input. */
2649 if (regnum
< MIPS_NUMREGS
)
2650 printf_filtered ("(r%d): ", regnum
);
2652 printf_filtered (": ");
2654 /* If virtual format is floating, print it that way. */
2655 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2656 if (FP_REGISTER_DOUBLE
)
2657 { /* show 8-byte floats as float AND double: */
2658 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2660 printf_filtered (" (float) ");
2661 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2662 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2663 printf_filtered (", (double) ");
2664 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2665 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2668 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2669 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2670 /* Else print as integer in hex. */
2675 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2676 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2680 print_scalar_formatted (raw_buffer
+ offset
,
2681 REGISTER_VIRTUAL_TYPE (regnum
),
2682 'x', 0, gdb_stdout
);
2686 /* Replacement for generic do_registers_info.
2687 Print regs in pretty columns. */
2690 do_fp_register_row (int regnum
)
2691 { /* do values for FP (float) regs */
2692 char *raw_buffer
[2];
2694 /* use HI and LO to control the order of combining two flt regs */
2695 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2696 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2697 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2698 int inv1
, inv2
, inv3
;
2700 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2701 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2702 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2704 /* Get the data in raw format. */
2705 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2706 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2707 if (REGISTER_RAW_SIZE (regnum
) == 4)
2709 /* 4-byte registers: we can fit two registers per row. */
2710 /* Also print every pair of 4-byte regs as an 8-byte double. */
2711 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2712 error ("can't read register %d (%s)",
2713 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2715 /* copy the two floats into one double, and unpack both */
2716 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2717 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2718 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2719 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2721 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
2723 printf_filtered (": <invalid float>");
2725 printf_filtered ("%-17.9g", flt1
);
2727 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
2729 printf_filtered (": <invalid float>");
2731 printf_filtered ("%-17.9g", flt2
);
2733 printf_filtered (" dbl: ");
2735 printf_filtered ("<invalid double>");
2737 printf_filtered ("%-24.17g", doub
);
2738 printf_filtered ("\n");
2740 /* may want to do hex display here (future enhancement) */
2744 { /* eight byte registers: print each one as float AND as double. */
2745 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2747 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2748 flt1
= unpack_double (builtin_type_float
,
2749 &raw_buffer
[HI
][offset
], &inv1
);
2750 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2752 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
2754 printf_filtered ("<invalid float>");
2756 printf_filtered ("flt: %-17.9g", flt1
);
2758 printf_filtered (" dbl: ");
2760 printf_filtered ("<invalid double>");
2762 printf_filtered ("%-24.17g", doub
);
2764 printf_filtered ("\n");
2765 /* may want to do hex display here (future enhancement) */
2771 /* Print a row's worth of GP (int) registers, with name labels above */
2774 do_gp_register_row (int regnum
)
2776 /* do values for GP (int) regs */
2777 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2778 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2780 int start_regnum
= regnum
;
2781 int numregs
= NUM_REGS
;
2784 /* For GP registers, we print a separate row of names above the vals */
2785 printf_filtered (" ");
2786 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2788 if (*REGISTER_NAME (regnum
) == '\0')
2789 continue; /* unused register */
2790 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2791 break; /* end the row: reached FP register */
2792 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2793 REGISTER_NAME (regnum
));
2796 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2797 start_regnum
); /* print the R0 to R31 names */
2799 regnum
= start_regnum
; /* go back to start of row */
2800 /* now print the values in hex, 4 or 8 to the row */
2801 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2803 if (*REGISTER_NAME (regnum
) == '\0')
2804 continue; /* unused register */
2805 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2806 break; /* end row: reached FP register */
2807 /* OK: get the data in raw format. */
2808 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2809 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2810 /* pad small registers */
2811 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2812 printf_filtered (" ");
2813 /* Now print the register value in hex, endian order. */
2814 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2815 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2816 byte
< REGISTER_RAW_SIZE (regnum
);
2818 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2820 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2823 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2824 printf_filtered (" ");
2827 if (col
> 0) /* ie. if we actually printed anything... */
2828 printf_filtered ("\n");
2833 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2836 mips_do_registers_info (int regnum
, int fpregs
)
2838 if (regnum
!= -1) /* do one specified register */
2840 if (*(REGISTER_NAME (regnum
)) == '\0')
2841 error ("Not a valid register for the current processor type");
2843 mips_print_register (regnum
, 0);
2844 printf_filtered ("\n");
2847 /* do all (or most) registers */
2850 while (regnum
< NUM_REGS
)
2852 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2853 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2854 regnum
= do_fp_register_row (regnum
); /* FP regs */
2856 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2858 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2863 /* Return number of args passed to a frame. described by FIP.
2864 Can return -1, meaning no way to tell. */
2867 mips_frame_num_args (struct frame_info
*frame
)
2872 /* Is this a branch with a delay slot? */
2874 static int is_delayed (unsigned long);
2877 is_delayed (unsigned long insn
)
2880 for (i
= 0; i
< NUMOPCODES
; ++i
)
2881 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2882 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2884 return (i
< NUMOPCODES
2885 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2886 | INSN_COND_BRANCH_DELAY
2887 | INSN_COND_BRANCH_LIKELY
)));
2891 mips_step_skips_delay (CORE_ADDR pc
)
2893 char buf
[MIPS_INSTLEN
];
2895 /* There is no branch delay slot on MIPS16. */
2896 if (pc_is_mips16 (pc
))
2899 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2900 /* If error reading memory, guess that it is not a delayed branch. */
2902 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2906 /* Skip the PC past function prologue instructions (32-bit version).
2907 This is a helper function for mips_skip_prologue. */
2910 mips32_skip_prologue (CORE_ADDR pc
)
2914 int seen_sp_adjust
= 0;
2915 int load_immediate_bytes
= 0;
2917 /* Skip the typical prologue instructions. These are the stack adjustment
2918 instruction and the instructions that save registers on the stack
2919 or in the gcc frame. */
2920 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2922 unsigned long high_word
;
2924 inst
= mips_fetch_instruction (pc
);
2925 high_word
= (inst
>> 16) & 0xffff;
2927 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2928 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2930 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2931 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2933 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2934 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2935 && (inst
& 0x001F0000)) /* reg != $zero */
2938 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2940 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2942 continue; /* reg != $zero */
2944 /* move $s8,$sp. With different versions of gas this will be either
2945 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2946 Accept any one of these. */
2947 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2950 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2952 else if (high_word
== 0x3c1c) /* lui $gp,n */
2954 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2956 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2957 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2959 /* The following instructions load $at or $t0 with an immediate
2960 value in preparation for a stack adjustment via
2961 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2962 a local variable, so we accept them only before a stack adjustment
2963 instruction was seen. */
2964 else if (!seen_sp_adjust
)
2966 if (high_word
== 0x3c01 || /* lui $at,n */
2967 high_word
== 0x3c08) /* lui $t0,n */
2969 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2972 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2973 high_word
== 0x3508 || /* ori $t0,$t0,n */
2974 high_word
== 0x3401 || /* ori $at,$zero,n */
2975 high_word
== 0x3408) /* ori $t0,$zero,n */
2977 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2987 /* In a frameless function, we might have incorrectly
2988 skipped some load immediate instructions. Undo the skipping
2989 if the load immediate was not followed by a stack adjustment. */
2990 if (load_immediate_bytes
&& !seen_sp_adjust
)
2991 pc
-= load_immediate_bytes
;
2995 /* Skip the PC past function prologue instructions (16-bit version).
2996 This is a helper function for mips_skip_prologue. */
2999 mips16_skip_prologue (CORE_ADDR pc
)
3002 int extend_bytes
= 0;
3003 int prev_extend_bytes
;
3005 /* Table of instructions likely to be found in a function prologue. */
3008 unsigned short inst
;
3009 unsigned short mask
;
3016 , /* addiu $sp,offset */
3020 , /* daddiu $sp,offset */
3024 , /* sw reg,n($sp) */
3028 , /* sd reg,n($sp) */
3032 , /* sw $ra,n($sp) */
3036 , /* sd $ra,n($sp) */
3044 , /* sw $a0-$a3,n($s1) */
3048 , /* move reg,$a0-$a3 */
3052 , /* entry pseudo-op */
3056 , /* addiu $s1,$sp,n */
3059 } /* end of table marker */
3062 /* Skip the typical prologue instructions. These are the stack adjustment
3063 instruction and the instructions that save registers on the stack
3064 or in the gcc frame. */
3065 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3067 unsigned short inst
;
3070 inst
= mips_fetch_instruction (pc
);
3072 /* Normally we ignore an extend instruction. However, if it is
3073 not followed by a valid prologue instruction, we must adjust
3074 the pc back over the extend so that it won't be considered
3075 part of the prologue. */
3076 if ((inst
& 0xf800) == 0xf000) /* extend */
3078 extend_bytes
= MIPS16_INSTLEN
;
3081 prev_extend_bytes
= extend_bytes
;
3084 /* Check for other valid prologue instructions besides extend. */
3085 for (i
= 0; table
[i
].mask
!= 0; i
++)
3086 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3088 if (table
[i
].mask
!= 0) /* it was in table? */
3089 continue; /* ignore it */
3093 /* Return the current pc, adjusted backwards by 2 if
3094 the previous instruction was an extend. */
3095 return pc
- prev_extend_bytes
;
3101 /* To skip prologues, I use this predicate. Returns either PC itself
3102 if the code at PC does not look like a function prologue; otherwise
3103 returns an address that (if we're lucky) follows the prologue. If
3104 LENIENT, then we must skip everything which is involved in setting
3105 up the frame (it's OK to skip more, just so long as we don't skip
3106 anything which might clobber the registers which are being saved.
3107 We must skip more in the case where part of the prologue is in the
3108 delay slot of a non-prologue instruction). */
3111 mips_skip_prologue (CORE_ADDR pc
)
3113 /* See if we can determine the end of the prologue via the symbol table.
3114 If so, then return either PC, or the PC after the prologue, whichever
3117 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3119 if (post_prologue_pc
!= 0)
3120 return max (pc
, post_prologue_pc
);
3122 /* Can't determine prologue from the symbol table, need to examine
3125 if (pc_is_mips16 (pc
))
3126 return mips16_skip_prologue (pc
);
3128 return mips32_skip_prologue (pc
);
3131 /* Determine how a return value is stored within the MIPS register
3132 file, given the return type `valtype'. */
3134 struct return_value_word
3143 return_value_location (struct type
*valtype
,
3144 struct return_value_word
*hi
,
3145 struct return_value_word
*lo
)
3147 int len
= TYPE_LENGTH (valtype
);
3149 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3150 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3151 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3153 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3155 /* We need to break a 64bit float in two 32 bit halves and
3156 spread them across a floating-point register pair. */
3157 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3158 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3159 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3160 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3162 hi
->reg_offset
= lo
->reg_offset
;
3163 lo
->reg
= FP0_REGNUM
+ 0;
3164 hi
->reg
= FP0_REGNUM
+ 1;
3170 /* The floating point value fits in a single floating-point
3172 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3173 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3176 lo
->reg
= FP0_REGNUM
;
3187 /* Locate a result possibly spread across two registers. */
3189 lo
->reg
= regnum
+ 0;
3190 hi
->reg
= regnum
+ 1;
3191 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3192 && len
< MIPS_SAVED_REGSIZE
)
3194 /* "un-left-justify" the value in the low register */
3195 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3200 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3201 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3202 && len
< MIPS_SAVED_REGSIZE
* 2
3203 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3204 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3206 /* "un-left-justify" the value spread across two registers. */
3207 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3208 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3210 hi
->len
= len
- lo
->len
;
3214 /* Only perform a partial copy of the second register. */
3217 if (len
> MIPS_SAVED_REGSIZE
)
3219 lo
->len
= MIPS_SAVED_REGSIZE
;
3220 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3228 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3229 && REGISTER_RAW_SIZE (regnum
) == 8
3230 && MIPS_SAVED_REGSIZE
== 4)
3232 /* Account for the fact that only the least-signficant part
3233 of the register is being used */
3234 lo
->reg_offset
+= 4;
3235 hi
->reg_offset
+= 4;
3238 hi
->buf_offset
= lo
->len
;
3242 /* Given a return value in `regbuf' with a type `valtype', extract and
3243 copy its value into `valbuf'. */
3246 mips_extract_return_value (struct type
*valtype
,
3247 char regbuf
[REGISTER_BYTES
],
3250 struct return_value_word lo
;
3251 struct return_value_word hi
;
3252 return_value_location (valtype
, &hi
, &lo
);
3254 memcpy (valbuf
+ lo
.buf_offset
,
3255 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3259 memcpy (valbuf
+ hi
.buf_offset
,
3260 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3264 /* Given a return value in `valbuf' with a type `valtype', write it's
3265 value into the appropriate register. */
3268 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3270 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3271 struct return_value_word lo
;
3272 struct return_value_word hi
;
3273 return_value_location (valtype
, &hi
, &lo
);
3275 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3276 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3277 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3279 REGISTER_RAW_SIZE (lo
.reg
));
3283 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3284 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3285 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3287 REGISTER_RAW_SIZE (hi
.reg
));
3291 /* Exported procedure: Is PC in the signal trampoline code */
3294 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3296 if (sigtramp_address
== 0)
3298 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3301 /* Root of all "set mips "/"show mips " commands. This will eventually be
3302 used for all MIPS-specific commands. */
3305 show_mips_command (char *args
, int from_tty
)
3307 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3311 set_mips_command (char *args
, int from_tty
)
3313 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3314 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3317 /* Commands to show/set the MIPS FPU type. */
3320 show_mipsfpu_command (char *args
, int from_tty
)
3323 switch (MIPS_FPU_TYPE
)
3325 case MIPS_FPU_SINGLE
:
3326 fpu
= "single-precision";
3328 case MIPS_FPU_DOUBLE
:
3329 fpu
= "double-precision";
3332 fpu
= "absent (none)";
3335 internal_error (__FILE__
, __LINE__
, "bad switch");
3337 if (mips_fpu_type_auto
)
3338 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3341 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3347 set_mipsfpu_command (char *args
, int from_tty
)
3349 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3350 show_mipsfpu_command (args
, from_tty
);
3354 set_mipsfpu_single_command (char *args
, int from_tty
)
3356 mips_fpu_type
= MIPS_FPU_SINGLE
;
3357 mips_fpu_type_auto
= 0;
3360 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3365 set_mipsfpu_double_command (char *args
, int from_tty
)
3367 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3368 mips_fpu_type_auto
= 0;
3371 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3376 set_mipsfpu_none_command (char *args
, int from_tty
)
3378 mips_fpu_type
= MIPS_FPU_NONE
;
3379 mips_fpu_type_auto
= 0;
3382 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3387 set_mipsfpu_auto_command (char *args
, int from_tty
)
3389 mips_fpu_type_auto
= 1;
3392 /* Command to set the processor type. */
3395 mips_set_processor_type_command (char *args
, int from_tty
)
3399 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3401 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3402 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3403 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3405 /* Restore the value. */
3406 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3411 if (!mips_set_processor_type (tmp_mips_processor_type
))
3413 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3414 /* Restore its value. */
3415 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3420 mips_show_processor_type_command (char *args
, int from_tty
)
3424 /* Modify the actual processor type. */
3427 mips_set_processor_type (char *str
)
3434 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3436 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3438 mips_processor_type
= str
;
3439 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3441 /* FIXME tweak fpu flag too */
3448 /* Attempt to identify the particular processor model by reading the
3452 mips_read_processor_type (void)
3456 prid
= read_register (PRID_REGNUM
);
3458 if ((prid
& ~0xf) == 0x700)
3459 return savestring ("r3041", strlen ("r3041"));
3464 /* Just like reinit_frame_cache, but with the right arguments to be
3465 callable as an sfunc. */
3468 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3469 struct cmd_list_element
*c
)
3471 reinit_frame_cache ();
3475 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3477 mips_extra_func_info_t proc_desc
;
3479 /* Search for the function containing this address. Set the low bit
3480 of the address when searching, in case we were given an even address
3481 that is the start of a 16-bit function. If we didn't do this,
3482 the search would fail because the symbol table says the function
3483 starts at an odd address, i.e. 1 byte past the given address. */
3484 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3485 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3487 /* Make an attempt to determine if this is a 16-bit function. If
3488 the procedure descriptor exists and the address therein is odd,
3489 it's definitely a 16-bit function. Otherwise, we have to just
3490 guess that if the address passed in is odd, it's 16-bits. */
3492 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3493 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3495 info
->mach
= pc_is_mips16 (memaddr
) ?
3496 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3498 /* Round down the instruction address to the appropriate boundary. */
3499 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3501 /* Call the appropriate disassembler based on the target endian-ness. */
3502 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3503 return print_insn_big_mips (memaddr
, info
);
3505 return print_insn_little_mips (memaddr
, info
);
3508 /* Old-style breakpoint macros.
3509 The IDT board uses an unusual breakpoint value, and sometimes gets
3510 confused when it sees the usual MIPS breakpoint instruction. */
3512 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3513 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3514 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3515 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3516 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3517 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3518 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3519 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3521 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3522 counter value to determine whether a 16- or 32-bit breakpoint should be
3523 used. It returns a pointer to a string of bytes that encode a breakpoint
3524 instruction, stores the length of the string to *lenptr, and adjusts pc
3525 (if necessary) to point to the actual memory location where the
3526 breakpoint should be inserted. */
3529 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3531 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3533 if (pc_is_mips16 (*pcptr
))
3535 static unsigned char mips16_big_breakpoint
[] =
3536 MIPS16_BIG_BREAKPOINT
;
3537 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3538 *lenptr
= sizeof (mips16_big_breakpoint
);
3539 return mips16_big_breakpoint
;
3543 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
3544 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3545 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3547 *lenptr
= sizeof (big_breakpoint
);
3549 if (strcmp (target_shortname
, "mips") == 0)
3550 return idt_big_breakpoint
;
3551 else if (strcmp (target_shortname
, "ddb") == 0
3552 || strcmp (target_shortname
, "pmon") == 0
3553 || strcmp (target_shortname
, "lsi") == 0)
3554 return pmon_big_breakpoint
;
3556 return big_breakpoint
;
3561 if (pc_is_mips16 (*pcptr
))
3563 static unsigned char mips16_little_breakpoint
[] =
3564 MIPS16_LITTLE_BREAKPOINT
;
3565 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3566 *lenptr
= sizeof (mips16_little_breakpoint
);
3567 return mips16_little_breakpoint
;
3571 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3572 static unsigned char pmon_little_breakpoint
[] =
3573 PMON_LITTLE_BREAKPOINT
;
3574 static unsigned char idt_little_breakpoint
[] =
3575 IDT_LITTLE_BREAKPOINT
;
3577 *lenptr
= sizeof (little_breakpoint
);
3579 if (strcmp (target_shortname
, "mips") == 0)
3580 return idt_little_breakpoint
;
3581 else if (strcmp (target_shortname
, "ddb") == 0
3582 || strcmp (target_shortname
, "pmon") == 0
3583 || strcmp (target_shortname
, "lsi") == 0)
3584 return pmon_little_breakpoint
;
3586 return little_breakpoint
;
3591 /* If PC is in a mips16 call or return stub, return the address of the target
3592 PC, which is either the callee or the caller. There are several
3593 cases which must be handled:
3595 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3596 target PC is in $31 ($ra).
3597 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3598 and the target PC is in $2.
3599 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3600 before the jal instruction, this is effectively a call stub
3601 and the the target PC is in $2. Otherwise this is effectively
3602 a return stub and the target PC is in $18.
3604 See the source code for the stubs in gcc/config/mips/mips16.S for
3607 This function implements the SKIP_TRAMPOLINE_CODE macro.
3611 mips_skip_stub (CORE_ADDR pc
)
3614 CORE_ADDR start_addr
;
3616 /* Find the starting address and name of the function containing the PC. */
3617 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3620 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3621 target PC is in $31 ($ra). */
3622 if (strcmp (name
, "__mips16_ret_sf") == 0
3623 || strcmp (name
, "__mips16_ret_df") == 0)
3624 return read_signed_register (RA_REGNUM
);
3626 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3628 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3629 and the target PC is in $2. */
3630 if (name
[19] >= '0' && name
[19] <= '9')
3631 return read_signed_register (2);
3633 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3634 before the jal instruction, this is effectively a call stub
3635 and the the target PC is in $2. Otherwise this is effectively
3636 a return stub and the target PC is in $18. */
3637 else if (name
[19] == 's' || name
[19] == 'd')
3639 if (pc
== start_addr
)
3641 /* Check if the target of the stub is a compiler-generated
3642 stub. Such a stub for a function bar might have a name
3643 like __fn_stub_bar, and might look like this:
3648 la $1,bar (becomes a lui/addiu pair)
3650 So scan down to the lui/addi and extract the target
3651 address from those two instructions. */
3653 CORE_ADDR target_pc
= read_signed_register (2);
3657 /* See if the name of the target function is __fn_stub_*. */
3658 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3660 if (strncmp (name
, "__fn_stub_", 10) != 0
3661 && strcmp (name
, "etext") != 0
3662 && strcmp (name
, "_etext") != 0)
3665 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3666 The limit on the search is arbitrarily set to 20
3667 instructions. FIXME. */
3668 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3670 inst
= mips_fetch_instruction (target_pc
);
3671 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3672 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3673 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3674 return pc
| (inst
& 0xffff); /* low word */
3677 /* Couldn't find the lui/addui pair, so return stub address. */
3681 /* This is the 'return' part of a call stub. The return
3682 address is in $r18. */
3683 return read_signed_register (18);
3686 return 0; /* not a stub */
3690 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3691 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3694 mips_in_call_stub (CORE_ADDR pc
, char *name
)
3696 CORE_ADDR start_addr
;
3698 /* Find the starting address of the function containing the PC. If the
3699 caller didn't give us a name, look it up at the same time. */
3700 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3703 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3705 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3706 if (name
[19] >= '0' && name
[19] <= '9')
3708 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3709 before the jal instruction, this is effectively a call stub. */
3710 else if (name
[19] == 's' || name
[19] == 'd')
3711 return pc
== start_addr
;
3714 return 0; /* not a stub */
3718 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3719 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3722 mips_in_return_stub (CORE_ADDR pc
, char *name
)
3724 CORE_ADDR start_addr
;
3726 /* Find the starting address of the function containing the PC. */
3727 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3730 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3731 if (strcmp (name
, "__mips16_ret_sf") == 0
3732 || strcmp (name
, "__mips16_ret_df") == 0)
3735 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3736 i.e. after the jal instruction, this is effectively a return stub. */
3737 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3738 && (name
[19] == 's' || name
[19] == 'd')
3739 && pc
!= start_addr
)
3742 return 0; /* not a stub */
3746 /* Return non-zero if the PC is in a library helper function that should
3747 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3750 mips_ignore_helper (CORE_ADDR pc
)
3754 /* Find the starting address and name of the function containing the PC. */
3755 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3758 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3759 that we want to ignore. */
3760 return (strcmp (name
, "__mips16_ret_sf") == 0
3761 || strcmp (name
, "__mips16_ret_df") == 0);
3765 /* Return a location where we can set a breakpoint that will be hit
3766 when an inferior function call returns. This is normally the
3767 program's entry point. Executables that don't have an entry
3768 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3769 whose address is the location where the breakpoint should be placed. */
3772 mips_call_dummy_address (void)
3774 struct minimal_symbol
*sym
;
3776 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3778 return SYMBOL_VALUE_ADDRESS (sym
);
3780 return entry_point_address ();
3784 /* If the current gcc for this target does not produce correct debugging
3785 information for float parameters, both prototyped and unprototyped, then
3786 define this macro. This forces gdb to always assume that floats are
3787 passed as doubles and then converted in the callee.
3789 For the mips chip, it appears that the debug info marks the parameters as
3790 floats regardless of whether the function is prototyped, but the actual
3791 values are passed as doubles for the non-prototyped case and floats for
3792 the prototyped case. Thus we choose to make the non-prototyped case work
3793 for C and break the prototyped case, since the non-prototyped case is
3794 probably much more common. (FIXME). */
3797 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3799 return current_language
->la_language
== language_c
;
3802 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3803 the register stored on the stack (32) is different to its real raw
3804 size (64). The below ensures that registers are fetched from the
3805 stack using their ABI size and then stored into the RAW_BUFFER
3806 using their raw size.
3808 The alternative to adding this function would be to add an ABI
3809 macro - REGISTER_STACK_SIZE(). */
3812 mips_get_saved_register (char *raw_buffer
,
3815 struct frame_info
*frame
,
3817 enum lval_type
*lval
)
3821 if (!target_has_registers
)
3822 error ("No registers.");
3824 /* Normal systems don't optimize out things with register numbers. */
3825 if (optimized
!= NULL
)
3827 addr
= find_saved_register (frame
, regnum
);
3831 *lval
= lval_memory
;
3832 if (regnum
== SP_REGNUM
)
3834 if (raw_buffer
!= NULL
)
3836 /* Put it back in target format. */
3837 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
3844 if (raw_buffer
!= NULL
)
3848 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
3850 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
3852 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
3853 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
3859 *lval
= lval_register
;
3860 addr
= REGISTER_BYTE (regnum
);
3861 if (raw_buffer
!= NULL
)
3862 read_register_gen (regnum
, raw_buffer
);
3868 /* Immediately after a function call, return the saved pc.
3869 Can't always go through the frames for this because on some machines
3870 the new frame is not set up until the new function executes
3871 some instructions. */
3874 mips_saved_pc_after_call (struct frame_info
*frame
)
3876 return read_signed_register (RA_REGNUM
);
3880 /* Convert a dbx stab register number (from `r' declaration) to a gdb
3884 mips_stab_reg_to_regnum (int num
)
3889 return num
+ FP0_REGNUM
- 38;
3892 /* Convert a ecoff register number to a gdb REGNUM */
3895 mips_ecoff_reg_to_regnum (int num
)
3900 return num
+ FP0_REGNUM
- 32;
3903 static struct gdbarch
*
3904 mips_gdbarch_init (struct gdbarch_info info
,
3905 struct gdbarch_list
*arches
)
3907 static LONGEST mips_call_dummy_words
[] =
3909 struct gdbarch
*gdbarch
;
3910 struct gdbarch_tdep
*tdep
;
3912 enum mips_abi mips_abi
;
3914 /* Reset the disassembly info, in case it was set to something
3916 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
3917 tm_print_insn_info
.arch
= bfd_arch_unknown
;
3918 tm_print_insn_info
.mach
= 0;
3920 /* Extract the elf_flags if available */
3921 if (info
.abfd
!= NULL
3922 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3923 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3927 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3928 switch ((elf_flags
& EF_MIPS_ABI
))
3930 case E_MIPS_ABI_O32
:
3931 mips_abi
= MIPS_ABI_O32
;
3933 case E_MIPS_ABI_O64
:
3934 mips_abi
= MIPS_ABI_O64
;
3936 case E_MIPS_ABI_EABI32
:
3937 mips_abi
= MIPS_ABI_EABI32
;
3939 case E_MIPS_ABI_EABI64
:
3940 mips_abi
= MIPS_ABI_EABI64
;
3943 if ((elf_flags
& EF_MIPS_ABI2
))
3944 mips_abi
= MIPS_ABI_N32
;
3946 mips_abi
= MIPS_ABI_UNKNOWN
;
3950 /* Try the architecture for any hint of the corect ABI */
3951 if (mips_abi
== MIPS_ABI_UNKNOWN
3952 && info
.bfd_arch_info
!= NULL
3953 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3955 switch (info
.bfd_arch_info
->mach
)
3957 case bfd_mach_mips3900
:
3958 mips_abi
= MIPS_ABI_EABI32
;
3960 case bfd_mach_mips4100
:
3961 case bfd_mach_mips5000
:
3962 mips_abi
= MIPS_ABI_EABI64
;
3964 case bfd_mach_mips8000
:
3965 case bfd_mach_mips10000
:
3966 mips_abi
= MIPS_ABI_N32
;
3970 #ifdef MIPS_DEFAULT_ABI
3971 if (mips_abi
== MIPS_ABI_UNKNOWN
)
3972 mips_abi
= MIPS_DEFAULT_ABI
;
3977 fprintf_unfiltered (gdb_stdlog
,
3978 "mips_gdbarch_init: elf_flags = 0x%08x\n",
3980 fprintf_unfiltered (gdb_stdlog
,
3981 "mips_gdbarch_init: mips_abi = %d\n",
3985 /* try to find a pre-existing architecture */
3986 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3988 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3990 /* MIPS needs to be pedantic about which ABI the object is
3992 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
3994 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
3996 return arches
->gdbarch
;
3999 /* Need a new architecture. Fill in a target specific vector. */
4000 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4001 gdbarch
= gdbarch_alloc (&info
, tdep
);
4002 tdep
->elf_flags
= elf_flags
;
4004 /* Initially set everything according to the ABI. */
4005 set_gdbarch_short_bit (gdbarch
, 16);
4006 set_gdbarch_int_bit (gdbarch
, 32);
4007 set_gdbarch_float_bit (gdbarch
, 32);
4008 set_gdbarch_double_bit (gdbarch
, 64);
4009 set_gdbarch_long_double_bit (gdbarch
, 64);
4010 tdep
->mips_abi
= mips_abi
;
4015 tdep
->mips_abi_string
= "o32";
4016 tdep
->mips_default_saved_regsize
= 4;
4017 tdep
->mips_default_stack_argsize
= 4;
4018 tdep
->mips_fp_register_double
= 0;
4019 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4020 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4021 tdep
->mips_regs_have_home_p
= 1;
4022 tdep
->gdb_target_is_mips64
= 0;
4023 tdep
->default_mask_address_p
= 0;
4024 set_gdbarch_long_bit (gdbarch
, 32);
4025 set_gdbarch_ptr_bit (gdbarch
, 32);
4026 set_gdbarch_long_long_bit (gdbarch
, 64);
4029 tdep
->mips_abi_string
= "o64";
4030 tdep
->mips_default_saved_regsize
= 8;
4031 tdep
->mips_default_stack_argsize
= 8;
4032 tdep
->mips_fp_register_double
= 1;
4033 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4034 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4035 tdep
->mips_regs_have_home_p
= 1;
4036 tdep
->gdb_target_is_mips64
= 1;
4037 tdep
->default_mask_address_p
= 0;
4038 set_gdbarch_long_bit (gdbarch
, 32);
4039 set_gdbarch_ptr_bit (gdbarch
, 32);
4040 set_gdbarch_long_long_bit (gdbarch
, 64);
4042 case MIPS_ABI_EABI32
:
4043 tdep
->mips_abi_string
= "eabi32";
4044 tdep
->mips_default_saved_regsize
= 4;
4045 tdep
->mips_default_stack_argsize
= 4;
4046 tdep
->mips_fp_register_double
= 0;
4047 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4048 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4049 tdep
->mips_regs_have_home_p
= 0;
4050 tdep
->gdb_target_is_mips64
= 0;
4051 tdep
->default_mask_address_p
= 0;
4052 set_gdbarch_long_bit (gdbarch
, 32);
4053 set_gdbarch_ptr_bit (gdbarch
, 32);
4054 set_gdbarch_long_long_bit (gdbarch
, 64);
4056 case MIPS_ABI_EABI64
:
4057 tdep
->mips_abi_string
= "eabi64";
4058 tdep
->mips_default_saved_regsize
= 8;
4059 tdep
->mips_default_stack_argsize
= 8;
4060 tdep
->mips_fp_register_double
= 1;
4061 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4062 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4063 tdep
->mips_regs_have_home_p
= 0;
4064 tdep
->gdb_target_is_mips64
= 1;
4065 tdep
->default_mask_address_p
= 0;
4066 set_gdbarch_long_bit (gdbarch
, 64);
4067 set_gdbarch_ptr_bit (gdbarch
, 64);
4068 set_gdbarch_long_long_bit (gdbarch
, 64);
4071 tdep
->mips_abi_string
= "n32";
4072 tdep
->mips_default_saved_regsize
= 4;
4073 tdep
->mips_default_stack_argsize
= 8;
4074 tdep
->mips_fp_register_double
= 1;
4075 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4076 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4077 tdep
->mips_regs_have_home_p
= 0;
4078 tdep
->gdb_target_is_mips64
= 0;
4079 tdep
->default_mask_address_p
= 0;
4080 set_gdbarch_long_bit (gdbarch
, 32);
4081 set_gdbarch_ptr_bit (gdbarch
, 32);
4082 set_gdbarch_long_long_bit (gdbarch
, 64);
4084 /* Set up the disassembler info, so that we get the right
4085 register names from libopcodes. */
4086 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4087 tm_print_insn_info
.arch
= bfd_arch_mips
;
4088 if (info
.bfd_arch_info
!= NULL
4089 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4090 && info
.bfd_arch_info
->mach
)
4091 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4093 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4096 tdep
->mips_abi_string
= "default";
4097 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
4098 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
4099 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
4100 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4101 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4102 tdep
->mips_regs_have_home_p
= 1;
4103 tdep
->gdb_target_is_mips64
= 0;
4104 tdep
->default_mask_address_p
= 0;
4105 set_gdbarch_long_bit (gdbarch
, 32);
4106 set_gdbarch_ptr_bit (gdbarch
, 32);
4107 set_gdbarch_long_long_bit (gdbarch
, 64);
4111 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4112 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4115 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4116 flag in object files because to do so would make it impossible to
4117 link with libraries compiled without "-gp32". This is
4118 unnecessarily restrictive.
4120 We could solve this problem by adding "-gp32" multilibs to gcc,
4121 but to set this flag before gcc is built with such multilibs will
4122 break too many systems.''
4124 But even more unhelpfully, the default linker output target for
4125 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4126 for 64-bit programs - you need to change the ABI to change this,
4127 and not all gcc targets support that currently. Therefore using
4128 this flag to detect 32-bit mode would do the wrong thing given
4129 the current gcc - it would make GDB treat these 64-bit programs
4130 as 32-bit programs by default. */
4132 /* enable/disable the MIPS FPU */
4133 if (!mips_fpu_type_auto
)
4134 tdep
->mips_fpu_type
= mips_fpu_type
;
4135 else if (info
.bfd_arch_info
!= NULL
4136 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4137 switch (info
.bfd_arch_info
->mach
)
4139 case bfd_mach_mips3900
:
4140 case bfd_mach_mips4100
:
4141 case bfd_mach_mips4111
:
4142 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4144 case bfd_mach_mips4650
:
4145 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4148 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4152 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4154 /* MIPS version of register names. NOTE: At present the MIPS
4155 register name management is part way between the old -
4156 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4157 Further work on it is required. */
4158 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4159 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4160 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4161 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4162 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
4163 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4164 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4166 /* Add/remove bits from an address. The MIPS needs be careful to
4167 ensure that all 32 bit addresses are sign extended to 64 bits. */
4168 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4170 /* There's a mess in stack frame creation. See comments in
4171 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4172 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
4173 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
4175 /* Map debug register numbers onto internal register numbers. */
4176 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4177 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4179 /* Initialize a frame */
4180 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4182 /* MIPS version of CALL_DUMMY */
4184 set_gdbarch_call_dummy_p (gdbarch
, 1);
4185 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4186 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4187 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4188 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4189 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4190 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4191 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4192 set_gdbarch_call_dummy_length (gdbarch
, 0);
4193 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4194 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4195 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4196 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4197 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4198 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4199 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4201 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4202 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4204 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4205 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4206 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4207 set_gdbarch_ieee_float (gdbarch
, 1);
4209 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4210 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4216 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4222 int ef_mips_32bitmode
;
4223 /* determine the ISA */
4224 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4242 /* determine the size of a pointer */
4243 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4244 fprintf_unfiltered (file
,
4245 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4247 fprintf_unfiltered (file
,
4248 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4250 fprintf_unfiltered (file
,
4251 "mips_dump_tdep: ef_mips_arch = %d\n",
4253 fprintf_unfiltered (file
,
4254 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4256 tdep
->mips_abi_string
);
4257 fprintf_unfiltered (file
,
4258 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4259 mips_mask_address_p (),
4260 tdep
->default_mask_address_p
);
4262 fprintf_unfiltered (file
,
4263 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4264 FP_REGISTER_DOUBLE
);
4265 fprintf_unfiltered (file
,
4266 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4267 MIPS_DEFAULT_FPU_TYPE
,
4268 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4269 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4270 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4272 fprintf_unfiltered (file
,
4273 "mips_dump_tdep: MIPS_EABI = %d\n",
4275 fprintf_unfiltered (file
,
4276 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4277 MIPS_LAST_FP_ARG_REGNUM
,
4278 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4279 fprintf_unfiltered (file
,
4280 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4282 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4283 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4284 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4286 fprintf_unfiltered (file
,
4287 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4288 MIPS_DEFAULT_SAVED_REGSIZE
);
4289 fprintf_unfiltered (file
,
4290 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4291 FP_REGISTER_DOUBLE
);
4292 fprintf_unfiltered (file
,
4293 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4294 MIPS_REGS_HAVE_HOME_P
);
4295 fprintf_unfiltered (file
,
4296 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4297 MIPS_DEFAULT_STACK_ARGSIZE
);
4298 fprintf_unfiltered (file
,
4299 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4300 MIPS_STACK_ARGSIZE
);
4301 fprintf_unfiltered (file
,
4302 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4304 fprintf_unfiltered (file
,
4305 "mips_dump_tdep: A0_REGNUM = %d\n",
4307 fprintf_unfiltered (file
,
4308 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4309 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4310 fprintf_unfiltered (file
,
4311 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4312 XSTRING (ATTACH_DETACH
));
4313 fprintf_unfiltered (file
,
4314 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4316 fprintf_unfiltered (file
,
4317 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4318 fprintf_unfiltered (file
,
4319 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4321 fprintf_unfiltered (file
,
4322 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4324 fprintf_unfiltered (file
,
4325 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4327 fprintf_unfiltered (file
,
4328 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4329 XSTRING (DO_REGISTERS_INFO
));
4330 fprintf_unfiltered (file
,
4331 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4332 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4333 fprintf_unfiltered (file
,
4334 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4335 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4336 fprintf_unfiltered (file
,
4337 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4338 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4339 fprintf_unfiltered (file
,
4340 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4342 fprintf_unfiltered (file
,
4343 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4345 fprintf_unfiltered (file
,
4346 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4347 FIRST_EMBED_REGNUM
);
4348 fprintf_unfiltered (file
,
4349 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4351 fprintf_unfiltered (file
,
4352 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4353 GDB_TARGET_IS_MIPS64
);
4354 fprintf_unfiltered (file
,
4355 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4356 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4357 fprintf_unfiltered (file
,
4358 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4359 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4360 fprintf_unfiltered (file
,
4361 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4363 fprintf_unfiltered (file
,
4364 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4365 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4366 fprintf_unfiltered (file
,
4367 "mips_dump_tdep: HI_REGNUM = %d\n",
4369 fprintf_unfiltered (file
,
4370 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4371 fprintf_unfiltered (file
,
4372 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4373 fprintf_unfiltered (file
,
4374 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4375 XSTRING (IGNORE_HELPER_CALL (PC
)));
4376 fprintf_unfiltered (file
,
4377 "mips_dump_tdep: IN_SIGTRAMP # %s\n",
4378 XSTRING (IN_SIGTRAMP (PC
, NAME
)));
4379 fprintf_unfiltered (file
,
4380 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4381 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4382 fprintf_unfiltered (file
,
4383 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4384 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4385 fprintf_unfiltered (file
,
4386 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4387 fprintf_unfiltered (file
,
4388 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4390 fprintf_unfiltered (file
,
4391 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4392 fprintf_unfiltered (file
,
4393 "mips_dump_tdep: LO_REGNUM = %d\n",
4395 #ifdef MACHINE_CPROC_FP_OFFSET
4396 fprintf_unfiltered (file
,
4397 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4398 MACHINE_CPROC_FP_OFFSET
);
4400 #ifdef MACHINE_CPROC_PC_OFFSET
4401 fprintf_unfiltered (file
,
4402 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4403 MACHINE_CPROC_PC_OFFSET
);
4405 #ifdef MACHINE_CPROC_SP_OFFSET
4406 fprintf_unfiltered (file
,
4407 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4408 MACHINE_CPROC_SP_OFFSET
);
4410 fprintf_unfiltered (file
,
4411 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4412 fprintf_unfiltered (file
,
4413 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4414 fprintf_unfiltered (file
,
4415 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4417 fprintf_unfiltered (file
,
4418 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4419 fprintf_unfiltered (file
,
4420 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4421 fprintf_unfiltered (file
,
4422 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4423 fprintf_unfiltered (file
,
4424 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4426 fprintf_unfiltered (file
,
4427 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4428 MIPS_LAST_ARG_REGNUM
,
4429 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4430 fprintf_unfiltered (file
,
4431 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4433 fprintf_unfiltered (file
,
4434 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4435 fprintf_unfiltered (file
,
4436 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4437 MIPS_SAVED_REGSIZE
);
4438 fprintf_unfiltered (file
,
4439 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4440 fprintf_unfiltered (file
,
4441 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4442 XSTRING (MSYMBOL_SIZE (MSYM
)));
4443 fprintf_unfiltered (file
,
4444 "mips_dump_tdep: OP_LDFPR = used?\n");
4445 fprintf_unfiltered (file
,
4446 "mips_dump_tdep: OP_LDGPR = used?\n");
4447 fprintf_unfiltered (file
,
4448 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4449 fprintf_unfiltered (file
,
4450 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4451 fprintf_unfiltered (file
,
4452 "mips_dump_tdep: PRID_REGNUM = %d\n",
4454 fprintf_unfiltered (file
,
4455 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4456 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4457 fprintf_unfiltered (file
,
4458 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4459 fprintf_unfiltered (file
,
4460 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4461 fprintf_unfiltered (file
,
4462 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4463 fprintf_unfiltered (file
,
4464 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4465 fprintf_unfiltered (file
,
4466 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4467 fprintf_unfiltered (file
,
4468 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4469 fprintf_unfiltered (file
,
4470 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4471 fprintf_unfiltered (file
,
4472 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4473 fprintf_unfiltered (file
,
4474 "mips_dump_tdep: PROC_PC_REG = function?\n");
4475 fprintf_unfiltered (file
,
4476 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4477 fprintf_unfiltered (file
,
4478 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4479 fprintf_unfiltered (file
,
4480 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4481 fprintf_unfiltered (file
,
4482 "mips_dump_tdep: PS_REGNUM = %d\n",
4484 fprintf_unfiltered (file
,
4485 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4487 fprintf_unfiltered (file
,
4488 "mips_dump_tdep: RA_REGNUM = %d\n",
4490 fprintf_unfiltered (file
,
4491 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4492 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4493 fprintf_unfiltered (file
,
4494 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4495 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4496 fprintf_unfiltered (file
,
4497 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4498 fprintf_unfiltered (file
,
4499 "mips_dump_tdep: ROUND_DOWN = function?\n");
4500 fprintf_unfiltered (file
,
4501 "mips_dump_tdep: ROUND_UP = function?\n");
4503 fprintf_unfiltered (file
,
4504 "mips_dump_tdep: SAVED_BYTES = %d\n",
4508 fprintf_unfiltered (file
,
4509 "mips_dump_tdep: SAVED_FP = %d\n",
4513 fprintf_unfiltered (file
,
4514 "mips_dump_tdep: SAVED_PC = %d\n",
4517 fprintf_unfiltered (file
,
4518 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4519 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4520 fprintf_unfiltered (file
,
4521 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4522 fprintf_unfiltered (file
,
4523 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4525 fprintf_unfiltered (file
,
4526 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4527 SIGFRAME_FPREGSAVE_OFF
);
4528 fprintf_unfiltered (file
,
4529 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4531 fprintf_unfiltered (file
,
4532 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4533 SIGFRAME_REGSAVE_OFF
);
4534 fprintf_unfiltered (file
,
4535 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4537 fprintf_unfiltered (file
,
4538 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4539 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4540 fprintf_unfiltered (file
,
4541 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4542 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4543 fprintf_unfiltered (file
,
4544 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
4545 SOFTWARE_SINGLE_STEP_P ());
4546 fprintf_unfiltered (file
,
4547 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4548 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4549 #ifdef STACK_END_ADDR
4550 fprintf_unfiltered (file
,
4551 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4554 fprintf_unfiltered (file
,
4555 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4556 XSTRING (STEP_SKIPS_DELAY (PC
)));
4557 fprintf_unfiltered (file
,
4558 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4559 STEP_SKIPS_DELAY_P
);
4560 fprintf_unfiltered (file
,
4561 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4562 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4563 fprintf_unfiltered (file
,
4564 "mips_dump_tdep: T9_REGNUM = %d\n",
4566 fprintf_unfiltered (file
,
4567 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4568 fprintf_unfiltered (file
,
4569 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4570 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4571 fprintf_unfiltered (file
,
4572 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4573 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4574 fprintf_unfiltered (file
,
4575 "mips_dump_tdep: TARGET_MIPS = used?\n");
4576 fprintf_unfiltered (file
,
4577 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4578 XSTRING (TM_PRINT_INSN_MACH
));
4580 fprintf_unfiltered (file
,
4581 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4582 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4585 fprintf_unfiltered (file
,
4586 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4589 #ifdef TRACE_FLAVOR_SIZE
4590 fprintf_unfiltered (file
,
4591 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4595 fprintf_unfiltered (file
,
4596 "mips_dump_tdep: TRACE_SET # %s\n",
4597 XSTRING (TRACE_SET (X
,STATE
)));
4599 fprintf_unfiltered (file
,
4600 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4601 #ifdef UNUSED_REGNUM
4602 fprintf_unfiltered (file
,
4603 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4606 fprintf_unfiltered (file
,
4607 "mips_dump_tdep: V0_REGNUM = %d\n",
4609 fprintf_unfiltered (file
,
4610 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4611 (long) VM_MIN_ADDRESS
);
4613 fprintf_unfiltered (file
,
4614 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4617 fprintf_unfiltered (file
,
4618 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4620 fprintf_unfiltered (file
,
4621 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4626 _initialize_mips_tdep (void)
4628 static struct cmd_list_element
*mipsfpulist
= NULL
;
4629 struct cmd_list_element
*c
;
4631 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4632 if (!tm_print_insn
) /* Someone may have already set it */
4633 tm_print_insn
= gdb_print_insn_mips
;
4635 /* Add root prefix command for all "set mips"/"show mips" commands */
4636 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4637 "Various MIPS specific commands.",
4638 &setmipscmdlist
, "set mips ", 0, &setlist
);
4640 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4641 "Various MIPS specific commands.",
4642 &showmipscmdlist
, "show mips ", 0, &showlist
);
4644 /* Allow the user to override the saved register size. */
4645 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4648 &mips_saved_regsize_string
, "\
4649 Set size of general purpose registers saved on the stack.\n\
4650 This option can be set to one of:\n\
4651 32 - Force GDB to treat saved GP registers as 32-bit\n\
4652 64 - Force GDB to treat saved GP registers as 64-bit\n\
4653 auto - Allow GDB to use the target's default setting or autodetect the\n\
4654 saved GP register size from information contained in the executable.\n\
4659 /* Allow the user to override the argument stack size. */
4660 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4663 &mips_stack_argsize_string
, "\
4664 Set the amount of stack space reserved for each argument.\n\
4665 This option can be set to one of:\n\
4666 32 - Force GDB to allocate 32-bit chunks per argument\n\
4667 64 - Force GDB to allocate 64-bit chunks per argument\n\
4668 auto - Allow GDB to determine the correct setting from the current\n\
4669 target and executable (default)",
4673 /* Let the user turn off floating point and set the fence post for
4674 heuristic_proc_start. */
4676 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4677 "Set use of MIPS floating-point coprocessor.",
4678 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4679 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4680 "Select single-precision MIPS floating-point coprocessor.",
4682 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4683 "Select double-precision MIPS floating-point coprocessor.",
4685 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4686 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4687 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4688 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4689 "Select no MIPS floating-point coprocessor.",
4691 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4692 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4693 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4694 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4695 "Select MIPS floating-point coprocessor automatically.",
4697 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4698 "Show current use of MIPS floating-point coprocessor target.",
4702 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4703 (char *) &tmp_mips_processor_type
,
4704 "Set the type of MIPS processor in use.\n\
4705 Set this to be able to access processor-type-specific registers.\n\
4708 c
->function
.cfunc
= mips_set_processor_type_command
;
4709 c
= add_show_from_set (c
, &showlist
);
4710 c
->function
.cfunc
= mips_show_processor_type_command
;
4712 tmp_mips_processor_type
= xstrdup (DEFAULT_MIPS_TYPE
);
4713 mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE
), 0);
4716 /* We really would like to have both "0" and "unlimited" work, but
4717 command.c doesn't deal with that. So make it a var_zinteger
4718 because the user can always use "999999" or some such for unlimited. */
4719 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4720 (char *) &heuristic_fence_post
,
4722 Set the distance searched for the start of a function.\n\
4723 If you are debugging a stripped executable, GDB needs to search through the\n\
4724 program for the start of a function. This command sets the distance of the\n\
4725 search. The only need to set it is when debugging a stripped executable.",
4727 /* We need to throw away the frame cache when we set this, since it
4728 might change our ability to get backtraces. */
4729 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4730 add_show_from_set (c
, &showlist
);
4732 /* Allow the user to control whether the upper bits of 64-bit
4733 addresses should be zeroed. */
4734 c
= add_set_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
,
4735 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4736 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
4737 the correct value.\n",
4739 add_cmd ("mask-address", no_class
, show_mask_address
,
4740 "Show current mask-address value", &showmipscmdlist
);
4742 /* Allow the user to control the size of 32 bit registers within the
4743 raw remote packet. */
4744 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4747 (char *)&mips64_transfers_32bit_regs_p
, "\
4748 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4749 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4750 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4751 64 bits for others. Use \"off\" to disable compatibility mode",
4755 /* Debug this files internals. */
4756 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
4757 &mips_debug
, "Set mips debugging.\n\
4758 When non-zero, mips specific debugging is enabled.", &setdebuglist
),