1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *const mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 const struct register_alias mips_numeric_register_aliases
[] = {
146 #define R(n) { #n, n }
147 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
148 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
149 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
150 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
154 #ifndef MIPS_DEFAULT_FPU_TYPE
155 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157 static int mips_fpu_type_auto
= 1;
158 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
160 static int mips_debug
= 0;
162 /* Properties (for struct target_desc) describing the g/G packet
164 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
165 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
167 struct target_desc
*mips_tdesc_gp32
;
168 struct target_desc
*mips_tdesc_gp64
;
170 const struct mips_regnum
*
171 mips_regnum (struct gdbarch
*gdbarch
)
173 return gdbarch_tdep (gdbarch
)->regnum
;
177 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
179 return mips_regnum (gdbarch
)->fp0
+ 12;
182 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
184 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
186 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
187 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
190 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
192 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
194 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
195 functions to test, set, or clear bit 0 of addresses. */
198 is_mips16_addr (CORE_ADDR addr
)
204 unmake_mips16_addr (CORE_ADDR addr
)
206 return ((addr
) & ~(CORE_ADDR
) 1);
210 make_mips16_addr (CORE_ADDR addr
)
212 return ((addr
) | (CORE_ADDR
) 1);
215 /* Return the MIPS ABI associated with GDBARCH. */
217 mips_abi (struct gdbarch
*gdbarch
)
219 return gdbarch_tdep (gdbarch
)->mips_abi
;
223 mips_isa_regsize (struct gdbarch
*gdbarch
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 /* If we know how big the registers are, use that size. */
228 if (tdep
->register_size_valid_p
)
229 return tdep
->register_size
;
231 /* Fall back to the previous behavior. */
232 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
233 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
236 /* Return the currently configured (or set) saved register size. */
239 mips_abi_regsize (struct gdbarch
*gdbarch
)
241 switch (mips_abi (gdbarch
))
243 case MIPS_ABI_EABI32
:
249 case MIPS_ABI_EABI64
:
251 case MIPS_ABI_UNKNOWN
:
254 internal_error (__FILE__
, __LINE__
, _("bad switch"));
258 /* Functions for setting and testing a bit in a minimal symbol that
259 marks it as 16-bit function. The MSB of the minimal symbol's
260 "info" field is used for this purpose.
262 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
263 i.e. refers to a 16-bit function, and sets a "special" bit in a
264 minimal symbol to mark it as a 16-bit function
266 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
269 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
271 if (ELF_ST_IS_MIPS16 (((elf_symbol_type
*)
272 (sym
))->internal_elf_sym
.st_other
))
274 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
279 msymbol_is_special (struct minimal_symbol
*msym
)
281 return MSYMBOL_TARGET_FLAG_1 (msym
);
284 /* XFER a value from the big/little/left end of the register.
285 Depending on the size of the value it might occupy the entire
286 register or just part of it. Make an allowance for this, aligning
287 things accordingly. */
290 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
291 int reg_num
, int length
,
292 enum bfd_endian endian
, gdb_byte
*in
,
293 const gdb_byte
*out
, int buf_offset
)
297 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
298 /* Need to transfer the left or right part of the register, based on
299 the targets byte order. */
303 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
305 case BFD_ENDIAN_LITTLE
:
308 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
312 internal_error (__FILE__
, __LINE__
, _("bad switch"));
315 fprintf_unfiltered (gdb_stderr
,
316 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
317 reg_num
, reg_offset
, buf_offset
, length
);
318 if (mips_debug
&& out
!= NULL
)
321 fprintf_unfiltered (gdb_stdlog
, "out ");
322 for (i
= 0; i
< length
; i
++)
323 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
326 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
329 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
331 if (mips_debug
&& in
!= NULL
)
334 fprintf_unfiltered (gdb_stdlog
, "in ");
335 for (i
= 0; i
< length
; i
++)
336 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
339 fprintf_unfiltered (gdb_stdlog
, "\n");
342 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
343 compatiblity mode. A return value of 1 means that we have
344 physical 64-bit registers, but should treat them as 32-bit registers. */
347 mips2_fp_compat (struct frame_info
*frame
)
349 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
350 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
352 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
356 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
357 in all the places we deal with FP registers. PR gdb/413. */
358 /* Otherwise check the FR bit in the status register - it controls
359 the FP compatiblity mode. If it is clear we are in compatibility
361 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
368 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
370 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
372 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
374 /* The list of available "set mips " and "show mips " commands. */
376 static struct cmd_list_element
*setmipscmdlist
= NULL
;
377 static struct cmd_list_element
*showmipscmdlist
= NULL
;
379 /* Integer registers 0 thru 31 are handled explicitly by
380 mips_register_name(). Processor specific registers 32 and above
381 are listed in the following tables. */
384 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
388 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
389 "sr", "lo", "hi", "bad", "cause", "pc",
390 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
391 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
392 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
393 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
397 /* Names of IDT R3041 registers. */
399 static const char *mips_r3041_reg_names
[] = {
400 "sr", "lo", "hi", "bad", "cause", "pc",
401 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
402 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
403 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
404 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
405 "fsr", "fir", "", /*"fp" */ "",
406 "", "", "bus", "ccfg", "", "", "", "",
407 "", "", "port", "cmp", "", "", "epc", "prid",
410 /* Names of tx39 registers. */
412 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
413 "sr", "lo", "hi", "bad", "cause", "pc",
414 "", "", "", "", "", "", "", "",
415 "", "", "", "", "", "", "", "",
416 "", "", "", "", "", "", "", "",
417 "", "", "", "", "", "", "", "",
419 "", "", "", "", "", "", "", "",
420 "", "", "config", "cache", "debug", "depc", "epc",
423 /* Names of IRIX registers. */
424 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
425 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
426 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
427 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
428 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
429 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
432 /* Names of registers with Linux kernels. */
433 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
434 "sr", "lo", "hi", "bad", "cause", "pc",
435 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
436 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
437 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
438 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
443 /* Return the name of the register corresponding to REGNO. */
445 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
447 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
448 /* GPR names for all ABIs other than n32/n64. */
449 static char *mips_gpr_names
[] = {
450 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
451 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
452 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
453 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
456 /* GPR names for n32 and n64 ABIs. */
457 static char *mips_n32_n64_gpr_names
[] = {
458 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
459 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
460 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
461 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
464 enum mips_abi abi
= mips_abi (gdbarch
);
466 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
467 but then don't make the raw register names visible. This (upper)
468 range of user visible register numbers are the pseudo-registers.
470 This approach was adopted accommodate the following scenario:
471 It is possible to debug a 64-bit device using a 32-bit
472 programming model. In such instances, the raw registers are
473 configured to be 64-bits wide, while the pseudo registers are
474 configured to be 32-bits wide. The registers that the user
475 sees - the pseudo registers - match the users expectations
476 given the programming model being used. */
477 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
478 if (regno
< gdbarch_num_regs (gdbarch
))
481 /* The MIPS integer registers are always mapped from 0 to 31. The
482 names of the registers (which reflects the conventions regarding
483 register use) vary depending on the ABI. */
484 if (0 <= rawnum
&& rawnum
< 32)
486 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
487 return mips_n32_n64_gpr_names
[rawnum
];
489 return mips_gpr_names
[rawnum
];
491 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
492 return tdesc_register_name (gdbarch
, rawnum
);
493 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
495 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
496 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
497 return tdep
->mips_processor_reg_names
[rawnum
- 32];
501 internal_error (__FILE__
, __LINE__
,
502 _("mips_register_name: bad register number %d"), rawnum
);
505 /* Return the groups that a MIPS register can be categorised into. */
508 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
509 struct reggroup
*reggroup
)
514 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
515 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
516 if (reggroup
== all_reggroup
)
518 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
519 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
520 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
521 (gdbarch), as not all architectures are multi-arch. */
522 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
523 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
524 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
526 if (reggroup
== float_reggroup
)
527 return float_p
&& pseudo
;
528 if (reggroup
== vector_reggroup
)
529 return vector_p
&& pseudo
;
530 if (reggroup
== general_reggroup
)
531 return (!vector_p
&& !float_p
) && pseudo
;
532 /* Save the pseudo registers. Need to make certain that any code
533 extracting register values from a saved register cache also uses
535 if (reggroup
== save_reggroup
)
536 return raw_p
&& pseudo
;
537 /* Restore the same pseudo register. */
538 if (reggroup
== restore_reggroup
)
539 return raw_p
&& pseudo
;
543 /* Return the groups that a MIPS register can be categorised into.
544 This version is only used if we have a target description which
545 describes real registers (and their groups). */
548 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
549 struct reggroup
*reggroup
)
551 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
552 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
555 /* Only save, restore, and display the pseudo registers. Need to
556 make certain that any code extracting register values from a
557 saved register cache also uses pseudo registers.
559 Note: saving and restoring the pseudo registers is slightly
560 strange; if we have 64 bits, we should save and restore all
561 64 bits. But this is hard and has little benefit. */
565 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
569 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
572 /* Map the symbol table registers which live in the range [1 *
573 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
574 registers. Take care of alignment and size problems. */
576 static enum register_status
577 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
578 int cookednum
, gdb_byte
*buf
)
580 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
581 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
582 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
583 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
584 return regcache_raw_read (regcache
, rawnum
, buf
);
585 else if (register_size (gdbarch
, rawnum
) >
586 register_size (gdbarch
, cookednum
))
588 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
589 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
592 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
594 enum register_status status
;
596 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
597 if (status
== REG_VALID
)
598 store_signed_integer (buf
, 4, byte_order
, regval
);
603 internal_error (__FILE__
, __LINE__
, _("bad register size"));
607 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
608 struct regcache
*regcache
, int cookednum
,
611 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
612 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
613 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
614 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
615 regcache_raw_write (regcache
, rawnum
, buf
);
616 else if (register_size (gdbarch
, rawnum
) >
617 register_size (gdbarch
, cookednum
))
619 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
620 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
623 /* Sign extend the shortened version of the register prior
624 to placing it in the raw register. This is required for
625 some mips64 parts in order to avoid unpredictable behavior. */
626 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
627 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
628 regcache_raw_write_signed (regcache
, rawnum
, regval
);
632 internal_error (__FILE__
, __LINE__
, _("bad register size"));
636 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
637 struct agent_expr
*ax
, int reg
)
639 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
640 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
641 && reg
< 2 * gdbarch_num_regs (gdbarch
));
643 ax_reg_mask (ax
, rawnum
);
649 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
650 struct agent_expr
*ax
, int reg
)
652 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
653 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
654 && reg
< 2 * gdbarch_num_regs (gdbarch
));
655 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
659 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
661 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
662 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
665 ax_simple (ax
, aop_lsh
);
668 ax_simple (ax
, aop_rsh_signed
);
672 internal_error (__FILE__
, __LINE__
, _("bad register size"));
677 /* Table to translate MIPS16 register field to actual register number. */
678 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
680 /* Heuristic_proc_start may hunt through the text section for a long
681 time across a 2400 baud serial line. Allows the user to limit this
684 static unsigned int heuristic_fence_post
= 0;
686 /* Number of bytes of storage in the actual machine representation for
687 register N. NOTE: This defines the pseudo register type so need to
688 rebuild the architecture vector. */
690 static int mips64_transfers_32bit_regs_p
= 0;
693 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
694 struct cmd_list_element
*c
)
696 struct gdbarch_info info
;
697 gdbarch_info_init (&info
);
698 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
699 instead of relying on globals. Doing that would let generic code
700 handle the search for this specific architecture. */
701 if (!gdbarch_update_p (info
))
703 mips64_transfers_32bit_regs_p
= 0;
704 error (_("32-bit compatibility mode not supported"));
708 /* Convert to/from a register and the corresponding memory value. */
710 /* This predicate tests for the case of an 8 byte floating point
711 value that is being transferred to or from a pair of floating point
712 registers each of which are (or are considered to be) only 4 bytes
715 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
718 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
719 && register_size (gdbarch
, regnum
) == 4
720 && (regnum
% gdbarch_num_regs (gdbarch
))
721 >= mips_regnum (gdbarch
)->fp0
722 && (regnum
% gdbarch_num_regs (gdbarch
))
723 < mips_regnum (gdbarch
)->fp0
+ 32
724 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
727 /* This predicate tests for the case of a value of less than 8
728 bytes in width that is being transfered to or from an 8 byte
729 general purpose register. */
731 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
734 int num_regs
= gdbarch_num_regs (gdbarch
);
736 return (register_size (gdbarch
, regnum
) == 8
737 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
738 && TYPE_LENGTH (type
) < 8);
742 mips_convert_register_p (struct gdbarch
*gdbarch
,
743 int regnum
, struct type
*type
)
745 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
746 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
750 mips_register_to_value (struct frame_info
*frame
, int regnum
,
751 struct type
*type
, gdb_byte
*to
,
752 int *optimizedp
, int *unavailablep
)
754 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
756 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
758 get_frame_register (frame
, regnum
+ 0, to
+ 4);
759 get_frame_register (frame
, regnum
+ 1, to
+ 0);
761 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
762 optimizedp
, unavailablep
))
765 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
766 optimizedp
, unavailablep
))
768 *optimizedp
= *unavailablep
= 0;
771 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
773 int len
= TYPE_LENGTH (type
);
776 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
777 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
778 optimizedp
, unavailablep
))
781 *optimizedp
= *unavailablep
= 0;
786 internal_error (__FILE__
, __LINE__
,
787 _("mips_register_to_value: unrecognized case"));
792 mips_value_to_register (struct frame_info
*frame
, int regnum
,
793 struct type
*type
, const gdb_byte
*from
)
795 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
797 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
799 put_frame_register (frame
, regnum
+ 0, from
+ 4);
800 put_frame_register (frame
, regnum
+ 1, from
+ 0);
802 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
805 int len
= TYPE_LENGTH (type
);
807 /* Sign extend values, irrespective of type, that are stored to
808 a 64-bit general purpose register. (32-bit unsigned values
809 are stored as signed quantities within a 64-bit register.
810 When performing an operation, in compiled code, that combines
811 a 32-bit unsigned value with a signed 64-bit value, a type
812 conversion is first performed that zeroes out the high 32 bits.) */
813 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
816 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
818 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
819 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
820 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
824 if (from
[len
-1] & 0x80)
825 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
827 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
828 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
829 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
834 internal_error (__FILE__
, __LINE__
,
835 _("mips_value_to_register: unrecognized case"));
839 /* Return the GDB type object for the "standard" data type of data in
843 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
845 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
846 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
847 && (regnum
% gdbarch_num_regs (gdbarch
))
848 < mips_regnum (gdbarch
)->fp0
+ 32)
850 /* The floating-point registers raw, or cooked, always match
851 mips_isa_regsize(), and also map 1:1, byte for byte. */
852 if (mips_isa_regsize (gdbarch
) == 4)
853 return builtin_type (gdbarch
)->builtin_float
;
855 return builtin_type (gdbarch
)->builtin_double
;
857 else if (regnum
< gdbarch_num_regs (gdbarch
))
859 /* The raw or ISA registers. These are all sized according to
861 if (mips_isa_regsize (gdbarch
) == 4)
862 return builtin_type (gdbarch
)->builtin_int32
;
864 return builtin_type (gdbarch
)->builtin_int64
;
868 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
870 /* The cooked or ABI registers. These are sized according to
871 the ABI (with a few complications). */
872 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
873 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
874 return builtin_type (gdbarch
)->builtin_int32
;
875 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
876 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
877 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
878 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
879 /* The pseudo/cooked view of the embedded registers is always
880 32-bit. The raw view is handled below. */
881 return builtin_type (gdbarch
)->builtin_int32
;
882 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
883 /* The target, while possibly using a 64-bit register buffer,
884 is only transfering 32-bits of each integer register.
885 Reflect this in the cooked/pseudo (ABI) register value. */
886 return builtin_type (gdbarch
)->builtin_int32
;
887 else if (mips_abi_regsize (gdbarch
) == 4)
888 /* The ABI is restricted to 32-bit registers (the ISA could be
890 return builtin_type (gdbarch
)->builtin_int32
;
893 return builtin_type (gdbarch
)->builtin_int64
;
897 /* Return the GDB type for the pseudo register REGNUM, which is the
898 ABI-level view. This function is only called if there is a target
899 description which includes registers, so we know precisely the
900 types of hardware registers. */
903 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
905 const int num_regs
= gdbarch_num_regs (gdbarch
);
906 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
907 int rawnum
= regnum
% num_regs
;
908 struct type
*rawtype
;
910 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
912 /* Absent registers are still absent. */
913 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
914 if (TYPE_LENGTH (rawtype
) == 0)
917 if (rawnum
>= mips_regnum (gdbarch
)->fp0
918 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32)
919 /* Present the floating point registers however the hardware did;
920 do not try to convert between FPU layouts. */
923 /* Use pointer types for registers if we can. For n32 we can not,
924 since we do not have a 64-bit pointer type. */
925 if (mips_abi_regsize (gdbarch
)
926 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
928 if (rawnum
== MIPS_SP_REGNUM
929 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
930 return builtin_type (gdbarch
)->builtin_data_ptr
;
931 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
932 return builtin_type (gdbarch
)->builtin_func_ptr
;
935 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
936 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
937 || rawnum
== mips_regnum (gdbarch
)->lo
938 || rawnum
== mips_regnum (gdbarch
)->hi
939 || rawnum
== mips_regnum (gdbarch
)->badvaddr
940 || rawnum
== mips_regnum (gdbarch
)->cause
941 || rawnum
== mips_regnum (gdbarch
)->pc
942 || (mips_regnum (gdbarch
)->dspacc
!= -1
943 && rawnum
>= mips_regnum (gdbarch
)->dspacc
944 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
945 return builtin_type (gdbarch
)->builtin_int32
;
947 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
948 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
949 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
950 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
952 /* The pseudo/cooked view of embedded registers is always
953 32-bit, even if the target transfers 64-bit values for them.
954 New targets relying on XML descriptions should only transfer
955 the necessary 32 bits, but older versions of GDB expected 64,
956 so allow the target to provide 64 bits without interfering
957 with the displayed type. */
958 return builtin_type (gdbarch
)->builtin_int32
;
961 /* For all other registers, pass through the hardware type. */
965 /* Should the upper word of 64-bit addresses be zeroed? */
966 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
969 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
971 switch (mask_address_var
)
973 case AUTO_BOOLEAN_TRUE
:
975 case AUTO_BOOLEAN_FALSE
:
978 case AUTO_BOOLEAN_AUTO
:
979 return tdep
->default_mask_address_p
;
981 internal_error (__FILE__
, __LINE__
,
982 _("mips_mask_address_p: bad switch"));
988 show_mask_address (struct ui_file
*file
, int from_tty
,
989 struct cmd_list_element
*c
, const char *value
)
991 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
993 deprecated_show_value_hack (file
, from_tty
, c
, value
);
994 switch (mask_address_var
)
996 case AUTO_BOOLEAN_TRUE
:
997 printf_filtered ("The 32 bit mips address mask is enabled\n");
999 case AUTO_BOOLEAN_FALSE
:
1000 printf_filtered ("The 32 bit mips address mask is disabled\n");
1002 case AUTO_BOOLEAN_AUTO
:
1004 ("The 32 bit address mask is set automatically. Currently %s\n",
1005 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1008 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1013 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1016 mips_pc_is_mips16 (CORE_ADDR memaddr
)
1018 struct minimal_symbol
*sym
;
1020 /* A flag indicating that this is a MIPS16 function is stored by
1021 elfread.c in the high bit of the info field. Use this to decide
1022 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
1023 the address is set, assume this is a MIPS16 address. */
1024 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1026 return msymbol_is_special (sym
);
1028 return is_mips16_addr (memaddr
);
1031 /* MIPS believes that the PC has a sign extended value. Perhaps the
1032 all registers should be sign extended for simplicity? */
1035 mips_read_pc (struct regcache
*regcache
)
1038 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1039 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1040 if (is_mips16_addr (pc
))
1041 pc
= unmake_mips16_addr (pc
);
1046 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1050 pc
= frame_unwind_register_signed
1051 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1052 if (is_mips16_addr (pc
))
1053 pc
= unmake_mips16_addr (pc
);
1058 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1060 return frame_unwind_register_signed
1061 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1064 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1065 dummy frame. The frame ID's base needs to match the TOS value
1066 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1069 static struct frame_id
1070 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1072 return frame_id_build
1073 (get_frame_register_signed (this_frame
,
1074 gdbarch_num_regs (gdbarch
)
1076 get_frame_pc (this_frame
));
1080 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1082 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1083 if (mips_pc_is_mips16 (pc
))
1084 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1086 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1089 /* Fetch and return instruction from the specified location. If the PC
1090 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1093 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1095 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1096 gdb_byte buf
[MIPS_INSN32_SIZE
];
1100 if (mips_pc_is_mips16 (addr
))
1102 instlen
= MIPS_INSN16_SIZE
;
1103 addr
= unmake_mips16_addr (addr
);
1106 instlen
= MIPS_INSN32_SIZE
;
1107 status
= target_read_memory (addr
, buf
, instlen
);
1109 memory_error (status
, addr
);
1110 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1113 /* These are the fields of 32 bit mips instructions. */
1114 #define mips32_op(x) (x >> 26)
1115 #define itype_op(x) (x >> 26)
1116 #define itype_rs(x) ((x >> 21) & 0x1f)
1117 #define itype_rt(x) ((x >> 16) & 0x1f)
1118 #define itype_immediate(x) (x & 0xffff)
1120 #define jtype_op(x) (x >> 26)
1121 #define jtype_target(x) (x & 0x03ffffff)
1123 #define rtype_op(x) (x >> 26)
1124 #define rtype_rs(x) ((x >> 21) & 0x1f)
1125 #define rtype_rt(x) ((x >> 16) & 0x1f)
1126 #define rtype_rd(x) ((x >> 11) & 0x1f)
1127 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1128 #define rtype_funct(x) (x & 0x3f)
1131 mips32_relative_offset (ULONGEST inst
)
1133 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1136 /* Determine the address of the next instruction executed after the INST
1137 floating condition branch instruction at PC. COUNT specifies the
1138 number of the floating condition bits tested by the branch. */
1141 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1142 ULONGEST inst
, CORE_ADDR pc
, int count
)
1144 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1145 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1146 int tf
= itype_rt (inst
) & 1;
1147 int mask
= (1 << count
) - 1;
1152 /* No way to handle; it'll most likely trap anyway. */
1155 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1156 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1158 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1159 pc
+= mips32_relative_offset (inst
);
1166 /* Determine where to set a single step breakpoint while considering
1167 branch prediction. */
1169 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1171 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1174 inst
= mips_fetch_instruction (gdbarch
, pc
);
1175 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1178 if (itype_op (inst
) >> 2 == 5)
1179 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1181 op
= (itype_op (inst
) & 0x03);
1191 goto greater_branch
;
1196 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1197 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1198 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1199 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 9
1200 && (itype_rt (inst
) & 2) == 0)
1201 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1202 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1203 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 10
1204 && (itype_rt (inst
) & 2) == 0)
1205 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1206 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1207 else if (itype_op (inst
) == 29)
1209 /* The new PC will be alternate mode. */
1213 reg
= jtype_target (inst
) << 2;
1214 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1215 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1218 pc
+= 4; /* Not a branch, next instruction is easy. */
1221 { /* This gets way messy. */
1223 /* Further subdivide into SPECIAL, REGIMM and other. */
1224 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1226 case 0: /* SPECIAL */
1227 op
= rtype_funct (inst
);
1232 /* Set PC to that address. */
1233 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1235 case 12: /* SYSCALL */
1237 struct gdbarch_tdep
*tdep
;
1239 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1240 if (tdep
->syscall_next_pc
!= NULL
)
1241 pc
= tdep
->syscall_next_pc (frame
);
1250 break; /* end SPECIAL */
1251 case 1: /* REGIMM */
1253 op
= itype_rt (inst
); /* branch condition */
1258 case 16: /* BLTZAL */
1259 case 18: /* BLTZALL */
1261 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1262 pc
+= mips32_relative_offset (inst
) + 4;
1264 pc
+= 8; /* after the delay slot */
1268 case 17: /* BGEZAL */
1269 case 19: /* BGEZALL */
1270 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1271 pc
+= mips32_relative_offset (inst
) + 4;
1273 pc
+= 8; /* after the delay slot */
1275 case 0x1c: /* BPOSGE32 */
1276 case 0x1e: /* BPOSGE64 */
1278 if (itype_rs (inst
) == 0)
1280 unsigned int pos
= (op
& 2) ? 64 : 32;
1281 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1284 /* No way to handle; it'll most likely trap anyway. */
1287 if ((get_frame_register_unsigned (frame
,
1288 dspctl
) & 0x7f) >= pos
)
1289 pc
+= mips32_relative_offset (inst
);
1294 /* All of the other instructions in the REGIMM category */
1299 break; /* end REGIMM */
1304 reg
= jtype_target (inst
) << 2;
1305 /* Upper four bits get never changed... */
1306 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1309 case 4: /* BEQ, BEQL */
1311 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1312 get_frame_register_signed (frame
, itype_rt (inst
)))
1313 pc
+= mips32_relative_offset (inst
) + 4;
1317 case 5: /* BNE, BNEL */
1319 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1320 get_frame_register_signed (frame
, itype_rt (inst
)))
1321 pc
+= mips32_relative_offset (inst
) + 4;
1325 case 6: /* BLEZ, BLEZL */
1326 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1327 pc
+= mips32_relative_offset (inst
) + 4;
1333 greater_branch
: /* BGTZ, BGTZL */
1334 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1335 pc
+= mips32_relative_offset (inst
) + 4;
1342 } /* mips32_next_pc */
1344 /* Decoding the next place to set a breakpoint is irregular for the
1345 mips 16 variant, but fortunately, there fewer instructions. We have
1346 to cope ith extensions for 16 bit instructions and a pair of actual
1347 32 bit instructions. We dont want to set a single step instruction
1348 on the extend instruction either. */
1350 /* Lots of mips16 instruction formats */
1351 /* Predicting jumps requires itype,ritype,i8type
1352 and their extensions extItype,extritype,extI8type. */
1353 enum mips16_inst_fmts
1355 itype
, /* 0 immediate 5,10 */
1356 ritype
, /* 1 5,3,8 */
1357 rrtype
, /* 2 5,3,3,5 */
1358 rritype
, /* 3 5,3,3,5 */
1359 rrrtype
, /* 4 5,3,3,3,2 */
1360 rriatype
, /* 5 5,3,3,1,4 */
1361 shifttype
, /* 6 5,3,3,3,2 */
1362 i8type
, /* 7 5,3,8 */
1363 i8movtype
, /* 8 5,3,3,5 */
1364 i8mov32rtype
, /* 9 5,3,5,3 */
1365 i64type
, /* 10 5,3,8 */
1366 ri64type
, /* 11 5,3,3,5 */
1367 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1368 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1369 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1370 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1371 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1372 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1373 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1374 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1375 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1376 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1378 /* I am heaping all the fields of the formats into one structure and
1379 then, only the fields which are involved in instruction extension. */
1383 unsigned int regx
; /* Function in i8 type. */
1388 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1389 for the bits which make up the immediate extension. */
1392 extended_offset (unsigned int extension
)
1396 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1398 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1400 value
|= extension
& 0x1f; /* Extract 4:0. */
1405 /* Only call this function if you know that this is an extendable
1406 instruction. It won't malfunction, but why make excess remote memory
1407 references? If the immediate operands get sign extended or something,
1408 do it after the extension is performed. */
1409 /* FIXME: Every one of these cases needs to worry about sign extension
1410 when the offset is to be used in relative addressing. */
1413 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1415 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1417 pc
&= 0xfffffffe; /* Clear the low order bit. */
1418 target_read_memory (pc
, buf
, 2);
1419 return extract_unsigned_integer (buf
, 2, byte_order
);
1423 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1424 unsigned int extension
,
1426 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1431 switch (insn_format
)
1438 value
= extended_offset ((extension
<< 16) | inst
);
1439 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1443 value
= inst
& 0x7ff;
1444 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
1453 { /* A register identifier and an offset. */
1454 /* Most of the fields are the same as I type but the
1455 immediate value is of a different length. */
1459 value
= extended_offset ((extension
<< 16) | inst
);
1460 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1464 value
= inst
& 0xff; /* 8 bits */
1465 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
1468 regx
= (inst
>> 8) & 0x07; /* i8 funct */
1474 unsigned long value
;
1475 unsigned int nexthalf
;
1476 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1477 value
= value
<< 16;
1478 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1487 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1489 upk
->offset
= offset
;
1496 add_offset_16 (CORE_ADDR pc
, int offset
)
1498 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1502 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1503 unsigned int extension
, unsigned int insn
)
1505 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1506 int op
= (insn
>> 11);
1509 case 2: /* Branch */
1512 struct upk_mips16 upk
;
1513 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1514 pc
+= (upk
.offset
<< 1) + 2;
1517 case 3: /* JAL , JALX - Watch out, these are 32 bit
1520 struct upk_mips16 upk
;
1521 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1522 pc
= add_offset_16 (pc
, upk
.offset
);
1523 if ((insn
>> 10) & 0x01) /* Exchange mode */
1524 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1531 struct upk_mips16 upk
;
1533 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1534 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1536 pc
+= (upk
.offset
<< 1) + 2;
1543 struct upk_mips16 upk
;
1545 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1546 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1548 pc
+= (upk
.offset
<< 1) + 2;
1553 case 12: /* I8 Formats btez btnez */
1555 struct upk_mips16 upk
;
1557 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1558 /* upk.regx contains the opcode */
1559 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1560 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1561 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1562 /* pc = add_offset_16(pc,upk.offset) ; */
1563 pc
+= (upk
.offset
<< 1) + 2;
1568 case 29: /* RR Formats JR, JALR, JALR-RA */
1570 struct upk_mips16 upk
;
1571 /* upk.fmt = rrtype; */
1576 upk
.regx
= (insn
>> 8) & 0x07;
1577 upk
.regy
= (insn
>> 5) & 0x07;
1578 if ((upk
.regy
& 1) == 0)
1579 reg
= mips16_to_32_reg
[upk
.regx
];
1581 reg
= 31; /* Function return instruction. */
1582 pc
= get_frame_register_signed (frame
, reg
);
1589 /* This is an instruction extension. Fetch the real instruction
1590 (which follows the extension) and decode things based on
1594 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1595 fetch_mips_16 (gdbarch
, pc
));
1608 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1610 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1611 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1612 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1615 /* The mips_next_pc function supports single_step when the remote
1616 target monitor or stub is not developed enough to do a single_step.
1617 It works by decoding the current instruction and predicting where a
1618 branch will go. This isnt hard because all the data is available.
1619 The MIPS32 and MIPS16 variants are quite different. */
1621 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1623 if (mips_pc_is_mips16 (pc
))
1624 return mips16_next_pc (frame
, pc
);
1626 return mips32_next_pc (frame
, pc
);
1629 struct mips_frame_cache
1632 struct trad_frame_saved_reg
*saved_regs
;
1635 /* Set a register's saved stack address in temp_saved_regs. If an
1636 address has already been set for this register, do nothing; this
1637 way we will only recognize the first save of a given register in a
1640 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1641 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1642 Strictly speaking, only the second range is used as it is only second
1643 range (the ABI instead of ISA registers) that comes into play when finding
1644 saved registers in a frame. */
1647 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1648 int regnum
, CORE_ADDR offset
)
1650 if (this_cache
!= NULL
1651 && this_cache
->saved_regs
[regnum
].addr
== -1)
1653 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1655 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1661 /* Fetch the immediate value from a MIPS16 instruction.
1662 If the previous instruction was an EXTEND, use it to extend
1663 the upper bits of the immediate value. This is a helper function
1664 for mips16_scan_prologue. */
1667 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1668 unsigned short inst
, /* current instruction */
1669 int nbits
, /* number of bits in imm field */
1670 int scale
, /* scale factor to be applied to imm */
1671 int is_signed
) /* is the imm field signed? */
1675 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1677 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1678 if (offset
& 0x8000) /* check for negative extend */
1679 offset
= 0 - (0x10000 - (offset
& 0xffff));
1680 return offset
| (inst
& 0x1f);
1684 int max_imm
= 1 << nbits
;
1685 int mask
= max_imm
- 1;
1686 int sign_bit
= max_imm
>> 1;
1688 offset
= inst
& mask
;
1689 if (is_signed
&& (offset
& sign_bit
))
1690 offset
= 0 - (max_imm
- offset
);
1691 return offset
* scale
;
1696 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1697 the associated FRAME_CACHE if not null.
1698 Return the address of the first instruction past the prologue. */
1701 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1702 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1703 struct frame_info
*this_frame
,
1704 struct mips_frame_cache
*this_cache
)
1707 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1709 long frame_offset
= 0; /* Size of stack frame. */
1710 long frame_adjust
= 0; /* Offset of FP from SP. */
1711 int frame_reg
= MIPS_SP_REGNUM
;
1712 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1713 unsigned inst
= 0; /* current instruction */
1714 unsigned entry_inst
= 0; /* the entry instruction */
1715 unsigned save_inst
= 0; /* the save instruction */
1718 int extend_bytes
= 0;
1719 int prev_extend_bytes
;
1720 CORE_ADDR end_prologue_addr
= 0;
1722 /* Can be called when there's no process, and hence when there's no
1724 if (this_frame
!= NULL
)
1725 sp
= get_frame_register_signed (this_frame
,
1726 gdbarch_num_regs (gdbarch
)
1731 if (limit_pc
> start_pc
+ 200)
1732 limit_pc
= start_pc
+ 200;
1734 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1736 /* Save the previous instruction. If it's an EXTEND, we'll extract
1737 the immediate offset extension from it in mips16_get_imm. */
1740 /* Fetch and decode the instruction. */
1741 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1743 /* Normally we ignore extend instructions. However, if it is
1744 not followed by a valid prologue instruction, then this
1745 instruction is not part of the prologue either. We must
1746 remember in this case to adjust the end_prologue_addr back
1748 if ((inst
& 0xf800) == 0xf000) /* extend */
1750 extend_bytes
= MIPS_INSN16_SIZE
;
1754 prev_extend_bytes
= extend_bytes
;
1757 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1758 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1760 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1761 if (offset
< 0) /* Negative stack adjustment? */
1762 frame_offset
-= offset
;
1764 /* Exit loop if a positive stack adjustment is found, which
1765 usually means that the stack cleanup code in the function
1766 epilogue is reached. */
1769 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1771 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1772 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1773 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1775 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1777 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1778 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1779 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1781 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1783 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1784 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1786 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1788 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1789 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1791 else if (inst
== 0x673d) /* move $s1, $sp */
1796 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1798 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1799 frame_addr
= sp
+ offset
;
1801 frame_adjust
= offset
;
1803 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1805 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1806 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1807 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1809 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1811 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1812 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1813 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1815 else if ((inst
& 0xf81f) == 0xe809
1816 && (inst
& 0x700) != 0x700) /* entry */
1817 entry_inst
= inst
; /* Save for later processing. */
1818 else if ((inst
& 0xff80) == 0x6480) /* save */
1820 save_inst
= inst
; /* Save for later processing. */
1821 if (prev_extend_bytes
) /* extend */
1822 save_inst
|= prev_inst
<< 16;
1824 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1825 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1826 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1828 /* This instruction is part of the prologue, but we don't
1829 need to do anything special to handle it. */
1833 /* This instruction is not an instruction typically found
1834 in a prologue, so we must have reached the end of the
1836 if (end_prologue_addr
== 0)
1837 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1841 /* The entry instruction is typically the first instruction in a function,
1842 and it stores registers at offsets relative to the value of the old SP
1843 (before the prologue). But the value of the sp parameter to this
1844 function is the new SP (after the prologue has been executed). So we
1845 can't calculate those offsets until we've seen the entire prologue,
1846 and can calculate what the old SP must have been. */
1847 if (entry_inst
!= 0)
1849 int areg_count
= (entry_inst
>> 8) & 7;
1850 int sreg_count
= (entry_inst
>> 6) & 3;
1852 /* The entry instruction always subtracts 32 from the SP. */
1855 /* Now we can calculate what the SP must have been at the
1856 start of the function prologue. */
1859 /* Check if a0-a3 were saved in the caller's argument save area. */
1860 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1862 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1863 offset
+= mips_abi_regsize (gdbarch
);
1866 /* Check if the ra register was pushed on the stack. */
1868 if (entry_inst
& 0x20)
1870 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1871 offset
-= mips_abi_regsize (gdbarch
);
1874 /* Check if the s0 and s1 registers were pushed on the stack. */
1875 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1877 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1878 offset
-= mips_abi_regsize (gdbarch
);
1882 /* The SAVE instruction is similar to ENTRY, except that defined by the
1883 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1884 size of the frame is specified as an immediate field of instruction
1885 and an extended variation exists which lets additional registers and
1886 frame space to be specified. The instruction always treats registers
1887 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1888 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1890 static int args_table
[16] = {
1891 0, 0, 0, 0, 1, 1, 1, 1,
1892 2, 2, 2, 0, 3, 3, 4, -1,
1894 static int astatic_table
[16] = {
1895 0, 1, 2, 3, 0, 1, 2, 3,
1896 0, 1, 2, 4, 0, 1, 0, -1,
1898 int aregs
= (save_inst
>> 16) & 0xf;
1899 int xsregs
= (save_inst
>> 24) & 0x7;
1900 int args
= args_table
[aregs
];
1901 int astatic
= astatic_table
[aregs
];
1906 warning (_("Invalid number of argument registers encoded in SAVE."));
1911 warning (_("Invalid number of static registers encoded in SAVE."));
1915 /* For standard SAVE the frame size of 0 means 128. */
1916 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1917 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1920 frame_offset
+= frame_size
;
1922 /* Now we can calculate what the SP must have been at the
1923 start of the function prologue. */
1926 /* Check if A0-A3 were saved in the caller's argument save area. */
1927 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1929 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1930 offset
+= mips_abi_regsize (gdbarch
);
1935 /* Check if the RA register was pushed on the stack. */
1936 if (save_inst
& 0x40)
1938 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1939 offset
-= mips_abi_regsize (gdbarch
);
1942 /* Check if the S8 register was pushed on the stack. */
1945 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1946 offset
-= mips_abi_regsize (gdbarch
);
1949 /* Check if S2-S7 were pushed on the stack. */
1950 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1952 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1953 offset
-= mips_abi_regsize (gdbarch
);
1956 /* Check if the S1 register was pushed on the stack. */
1957 if (save_inst
& 0x10)
1959 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1960 offset
-= mips_abi_regsize (gdbarch
);
1962 /* Check if the S0 register was pushed on the stack. */
1963 if (save_inst
& 0x20)
1965 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1966 offset
-= mips_abi_regsize (gdbarch
);
1969 /* Check if A0-A3 were pushed on the stack. */
1970 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1972 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1973 offset
-= mips_abi_regsize (gdbarch
);
1977 if (this_cache
!= NULL
)
1980 (get_frame_register_signed (this_frame
,
1981 gdbarch_num_regs (gdbarch
) + frame_reg
)
1982 + frame_offset
- frame_adjust
);
1983 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1984 be able to get rid of the assignment below, evetually. But it's
1985 still needed for now. */
1986 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1987 + mips_regnum (gdbarch
)->pc
]
1988 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1991 /* If we didn't reach the end of the prologue when scanning the function
1992 instructions, then set end_prologue_addr to the address of the
1993 instruction immediately after the last one we scanned. */
1994 if (end_prologue_addr
== 0)
1995 end_prologue_addr
= cur_pc
;
1997 return end_prologue_addr
;
2000 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2001 Procedures that use the 32-bit instruction set are handled by the
2002 mips_insn32 unwinder. */
2004 static struct mips_frame_cache
*
2005 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2007 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2008 struct mips_frame_cache
*cache
;
2010 if ((*this_cache
) != NULL
)
2011 return (*this_cache
);
2012 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2013 (*this_cache
) = cache
;
2014 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2016 /* Analyze the function prologue. */
2018 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2019 CORE_ADDR start_addr
;
2021 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2022 if (start_addr
== 0)
2023 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2024 /* We can't analyze the prologue if we couldn't find the begining
2026 if (start_addr
== 0)
2029 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2032 /* gdbarch_sp_regnum contains the value and not the address. */
2033 trad_frame_set_value (cache
->saved_regs
,
2034 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2037 return (*this_cache
);
2041 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2042 struct frame_id
*this_id
)
2044 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2046 /* This marks the outermost frame. */
2047 if (info
->base
== 0)
2049 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2052 static struct value
*
2053 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2054 void **this_cache
, int regnum
)
2056 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2058 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2062 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2063 struct frame_info
*this_frame
, void **this_cache
)
2065 CORE_ADDR pc
= get_frame_pc (this_frame
);
2066 if (mips_pc_is_mips16 (pc
))
2071 static const struct frame_unwind mips_insn16_frame_unwind
=
2074 default_frame_unwind_stop_reason
,
2075 mips_insn16_frame_this_id
,
2076 mips_insn16_frame_prev_register
,
2078 mips_insn16_frame_sniffer
2082 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2085 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2090 static const struct frame_base mips_insn16_frame_base
=
2092 &mips_insn16_frame_unwind
,
2093 mips_insn16_frame_base_address
,
2094 mips_insn16_frame_base_address
,
2095 mips_insn16_frame_base_address
2098 static const struct frame_base
*
2099 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2101 CORE_ADDR pc
= get_frame_pc (this_frame
);
2102 if (mips_pc_is_mips16 (pc
))
2103 return &mips_insn16_frame_base
;
2108 /* Mark all the registers as unset in the saved_regs array
2109 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2112 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2114 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2118 const int num_regs
= gdbarch_num_regs (gdbarch
);
2121 for (i
= 0; i
< num_regs
; i
++)
2123 this_cache
->saved_regs
[i
].addr
= -1;
2128 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2129 the associated FRAME_CACHE if not null.
2130 Return the address of the first instruction past the prologue. */
2133 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2134 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2135 struct frame_info
*this_frame
,
2136 struct mips_frame_cache
*this_cache
)
2139 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2143 int frame_reg
= MIPS_SP_REGNUM
;
2145 CORE_ADDR end_prologue_addr
= 0;
2146 int seen_sp_adjust
= 0;
2147 int load_immediate_bytes
= 0;
2148 int in_delay_slot
= 0;
2149 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2151 /* Can be called when there's no process, and hence when there's no
2153 if (this_frame
!= NULL
)
2154 sp
= get_frame_register_signed (this_frame
,
2155 gdbarch_num_regs (gdbarch
)
2160 if (limit_pc
> start_pc
+ 200)
2161 limit_pc
= start_pc
+ 200;
2166 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2168 unsigned long inst
, high_word
, low_word
;
2171 /* Fetch the instruction. */
2172 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2174 /* Save some code by pre-extracting some useful fields. */
2175 high_word
= (inst
>> 16) & 0xffff;
2176 low_word
= inst
& 0xffff;
2177 reg
= high_word
& 0x1f;
2179 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2180 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2181 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2183 if (low_word
& 0x8000) /* Negative stack adjustment? */
2184 frame_offset
+= 0x10000 - low_word
;
2186 /* Exit loop if a positive stack adjustment is found, which
2187 usually means that the stack cleanup code in the function
2188 epilogue is reached. */
2192 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2193 && !regsize_is_64_bits
)
2195 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2197 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2198 && regsize_is_64_bits
)
2200 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2201 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2203 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2205 /* Old gcc frame, r30 is virtual frame pointer. */
2206 if ((long) low_word
!= frame_offset
)
2207 frame_addr
= sp
+ low_word
;
2208 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2210 unsigned alloca_adjust
;
2213 frame_addr
= get_frame_register_signed
2214 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2216 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2217 if (alloca_adjust
> 0)
2219 /* FP > SP + frame_size. This may be because of
2220 an alloca or somethings similar. Fix sp to
2221 "pre-alloca" value, and try again. */
2222 sp
+= alloca_adjust
;
2223 /* Need to reset the status of all registers. Otherwise,
2224 we will hit a guard that prevents the new address
2225 for each register to be recomputed during the second
2227 reset_saved_regs (gdbarch
, this_cache
);
2232 /* move $30,$sp. With different versions of gas this will be either
2233 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2234 Accept any one of these. */
2235 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2237 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2238 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2240 unsigned alloca_adjust
;
2243 frame_addr
= get_frame_register_signed
2244 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2246 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2247 if (alloca_adjust
> 0)
2249 /* FP > SP + frame_size. This may be because of
2250 an alloca or somethings similar. Fix sp to
2251 "pre-alloca" value, and try again. */
2253 /* Need to reset the status of all registers. Otherwise,
2254 we will hit a guard that prevents the new address
2255 for each register to be recomputed during the second
2257 reset_saved_regs (gdbarch
, this_cache
);
2262 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2263 && !regsize_is_64_bits
)
2265 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2267 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2268 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2269 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2270 || high_word
== 0x3c1c /* lui $gp,n */
2271 || high_word
== 0x279c /* addiu $gp,$gp,n */
2272 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2273 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2276 /* These instructions are part of the prologue, but we don't
2277 need to do anything special to handle them. */
2279 /* The instructions below load $at or $t0 with an immediate
2280 value in preparation for a stack adjustment via
2281 subu $sp,$sp,[$at,$t0]. These instructions could also
2282 initialize a local variable, so we accept them only before
2283 a stack adjustment instruction was seen. */
2284 else if (!seen_sp_adjust
2285 && (high_word
== 0x3c01 /* lui $at,n */
2286 || high_word
== 0x3c08 /* lui $t0,n */
2287 || high_word
== 0x3421 /* ori $at,$at,n */
2288 || high_word
== 0x3508 /* ori $t0,$t0,n */
2289 || high_word
== 0x3401 /* ori $at,$zero,n */
2290 || high_word
== 0x3408 /* ori $t0,$zero,n */
2293 if (end_prologue_addr
== 0)
2294 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2298 /* This instruction is not an instruction typically found
2299 in a prologue, so we must have reached the end of the
2301 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2302 loop now? Why would we need to continue scanning the function
2304 if (end_prologue_addr
== 0)
2305 end_prologue_addr
= cur_pc
;
2307 /* Check for branches and jumps. For now, only jump to
2308 register are caught (i.e. returns). */
2309 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2313 /* If the previous instruction was a jump, we must have reached
2314 the end of the prologue by now. Stop scanning so that we do
2315 not go past the function return. */
2320 if (this_cache
!= NULL
)
2323 (get_frame_register_signed (this_frame
,
2324 gdbarch_num_regs (gdbarch
) + frame_reg
)
2326 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2327 this assignment below, eventually. But it's still needed
2329 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2330 + mips_regnum (gdbarch
)->pc
]
2331 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2335 /* If we didn't reach the end of the prologue when scanning the function
2336 instructions, then set end_prologue_addr to the address of the
2337 instruction immediately after the last one we scanned. */
2338 /* brobecker/2004-10-10: I don't think this would ever happen, but
2339 we may as well be careful and do our best if we have a null
2340 end_prologue_addr. */
2341 if (end_prologue_addr
== 0)
2342 end_prologue_addr
= cur_pc
;
2344 /* In a frameless function, we might have incorrectly
2345 skipped some load immediate instructions. Undo the skipping
2346 if the load immediate was not followed by a stack adjustment. */
2347 if (load_immediate_bytes
&& !seen_sp_adjust
)
2348 end_prologue_addr
-= load_immediate_bytes
;
2350 return end_prologue_addr
;
2353 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2354 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2355 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2358 static struct mips_frame_cache
*
2359 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2361 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2362 struct mips_frame_cache
*cache
;
2364 if ((*this_cache
) != NULL
)
2365 return (*this_cache
);
2367 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2368 (*this_cache
) = cache
;
2369 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2371 /* Analyze the function prologue. */
2373 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2374 CORE_ADDR start_addr
;
2376 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2377 if (start_addr
== 0)
2378 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2379 /* We can't analyze the prologue if we couldn't find the begining
2381 if (start_addr
== 0)
2384 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2387 /* gdbarch_sp_regnum contains the value and not the address. */
2388 trad_frame_set_value (cache
->saved_regs
,
2389 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2392 return (*this_cache
);
2396 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2397 struct frame_id
*this_id
)
2399 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2401 /* This marks the outermost frame. */
2402 if (info
->base
== 0)
2404 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2407 static struct value
*
2408 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2409 void **this_cache
, int regnum
)
2411 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2413 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2417 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2418 struct frame_info
*this_frame
, void **this_cache
)
2420 CORE_ADDR pc
= get_frame_pc (this_frame
);
2421 if (! mips_pc_is_mips16 (pc
))
2426 static const struct frame_unwind mips_insn32_frame_unwind
=
2429 default_frame_unwind_stop_reason
,
2430 mips_insn32_frame_this_id
,
2431 mips_insn32_frame_prev_register
,
2433 mips_insn32_frame_sniffer
2437 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2440 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2445 static const struct frame_base mips_insn32_frame_base
=
2447 &mips_insn32_frame_unwind
,
2448 mips_insn32_frame_base_address
,
2449 mips_insn32_frame_base_address
,
2450 mips_insn32_frame_base_address
2453 static const struct frame_base
*
2454 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2456 CORE_ADDR pc
= get_frame_pc (this_frame
);
2457 if (! mips_pc_is_mips16 (pc
))
2458 return &mips_insn32_frame_base
;
2463 static struct trad_frame_cache
*
2464 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2467 CORE_ADDR start_addr
;
2468 CORE_ADDR stack_addr
;
2469 struct trad_frame_cache
*this_trad_cache
;
2470 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2471 int num_regs
= gdbarch_num_regs (gdbarch
);
2473 if ((*this_cache
) != NULL
)
2474 return (*this_cache
);
2475 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2476 (*this_cache
) = this_trad_cache
;
2478 /* The return address is in the link register. */
2479 trad_frame_set_reg_realreg (this_trad_cache
,
2480 gdbarch_pc_regnum (gdbarch
),
2481 num_regs
+ MIPS_RA_REGNUM
);
2483 /* Frame ID, since it's a frameless / stackless function, no stack
2484 space is allocated and SP on entry is the current SP. */
2485 pc
= get_frame_pc (this_frame
);
2486 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2487 stack_addr
= get_frame_register_signed (this_frame
,
2488 num_regs
+ MIPS_SP_REGNUM
);
2489 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2491 /* Assume that the frame's base is the same as the
2493 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2495 return this_trad_cache
;
2499 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2500 struct frame_id
*this_id
)
2502 struct trad_frame_cache
*this_trad_cache
2503 = mips_stub_frame_cache (this_frame
, this_cache
);
2504 trad_frame_get_id (this_trad_cache
, this_id
);
2507 static struct value
*
2508 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2509 void **this_cache
, int regnum
)
2511 struct trad_frame_cache
*this_trad_cache
2512 = mips_stub_frame_cache (this_frame
, this_cache
);
2513 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2517 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2518 struct frame_info
*this_frame
, void **this_cache
)
2521 struct obj_section
*s
;
2522 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2523 struct minimal_symbol
*msym
;
2525 /* Use the stub unwinder for unreadable code. */
2526 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2529 if (in_plt_section (pc
, NULL
))
2532 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2533 s
= find_pc_section (pc
);
2536 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2537 ".MIPS.stubs") == 0)
2540 /* Calling a PIC function from a non-PIC function passes through a
2541 stub. The stub for foo is named ".pic.foo". */
2542 msym
= lookup_minimal_symbol_by_pc (pc
);
2544 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2545 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2551 static const struct frame_unwind mips_stub_frame_unwind
=
2554 default_frame_unwind_stop_reason
,
2555 mips_stub_frame_this_id
,
2556 mips_stub_frame_prev_register
,
2558 mips_stub_frame_sniffer
2562 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2565 struct trad_frame_cache
*this_trad_cache
2566 = mips_stub_frame_cache (this_frame
, this_cache
);
2567 return trad_frame_get_this_base (this_trad_cache
);
2570 static const struct frame_base mips_stub_frame_base
=
2572 &mips_stub_frame_unwind
,
2573 mips_stub_frame_base_address
,
2574 mips_stub_frame_base_address
,
2575 mips_stub_frame_base_address
2578 static const struct frame_base
*
2579 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2581 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2582 return &mips_stub_frame_base
;
2587 /* mips_addr_bits_remove - remove useless address bits */
2590 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2592 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2594 if (is_mips16_addr (addr
))
2595 addr
= unmake_mips16_addr (addr
);
2597 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2598 /* This hack is a work-around for existing boards using PMON, the
2599 simulator, and any other 64-bit targets that doesn't have true
2600 64-bit addressing. On these targets, the upper 32 bits of
2601 addresses are ignored by the hardware. Thus, the PC or SP are
2602 likely to have been sign extended to all 1s by instruction
2603 sequences that load 32-bit addresses. For example, a typical
2604 piece of code that loads an address is this:
2606 lui $r2, <upper 16 bits>
2607 ori $r2, <lower 16 bits>
2609 But the lui sign-extends the value such that the upper 32 bits
2610 may be all 1s. The workaround is simply to mask off these
2611 bits. In the future, gcc may be changed to support true 64-bit
2612 addressing, and this masking will have to be disabled. */
2613 return addr
&= 0xffffffffUL
;
2618 /* Instructions used during single-stepping of atomic sequences. */
2619 #define LL_OPCODE 0x30
2620 #define LLD_OPCODE 0x34
2621 #define SC_OPCODE 0x38
2622 #define SCD_OPCODE 0x3c
2624 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2625 instruction and ending with a SC/SCD instruction. If such a sequence
2626 is found, attempt to step through it. A breakpoint is placed at the end of
2630 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2631 struct address_space
*aspace
, CORE_ADDR pc
)
2633 CORE_ADDR breaks
[2] = {-1, -1};
2635 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2639 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2640 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2645 insn
= mips_fetch_instruction (gdbarch
, loc
);
2646 /* Assume all atomic sequences start with a ll/lld instruction. */
2647 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2650 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2652 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2655 loc
+= MIPS_INSN32_SIZE
;
2656 insn
= mips_fetch_instruction (gdbarch
, loc
);
2658 /* Assume that there is at most one branch in the atomic
2659 sequence. If a branch is found, put a breakpoint in its
2660 destination address. */
2661 switch (itype_op (insn
))
2663 case 0: /* SPECIAL */
2664 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2665 return 0; /* fallback to the standard single-step code. */
2667 case 1: /* REGIMM */
2668 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
2669 || ((itype_rt (insn
) & 0x1e) == 0
2670 && itype_rs (insn
) == 0)); /* BPOSGE* */
2674 return 0; /* fallback to the standard single-step code. */
2681 case 22: /* BLEZL */
2682 case 23: /* BGTTL */
2686 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
2687 && (itype_rt (insn
) & 0x2) == 0);
2688 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
2693 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2698 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2699 if (last_breakpoint
>= 1)
2700 return 0; /* More than one branch found, fallback to the
2701 standard single-step code. */
2702 breaks
[1] = branch_bp
;
2706 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2710 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2711 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2714 loc
+= MIPS_INSN32_SIZE
;
2716 /* Insert a breakpoint right after the end of the atomic sequence. */
2719 /* Check for duplicated breakpoints. Check also for a breakpoint
2720 placed (branch instruction's destination) in the atomic sequence. */
2721 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2722 last_breakpoint
= 0;
2724 /* Effectively inserts the breakpoints. */
2725 for (index
= 0; index
<= last_breakpoint
; index
++)
2726 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2731 /* mips_software_single_step() is called just before we want to resume
2732 the inferior, if we want to single-step it but there is no hardware
2733 or kernel single-step support (MIPS on GNU/Linux for example). We find
2734 the target of the coming instruction and breakpoint it. */
2737 mips_software_single_step (struct frame_info
*frame
)
2739 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2740 struct address_space
*aspace
= get_frame_address_space (frame
);
2741 CORE_ADDR pc
, next_pc
;
2743 pc
= get_frame_pc (frame
);
2744 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2747 next_pc
= mips_next_pc (frame
, pc
);
2749 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2753 /* Test whether the PC points to the return instruction at the
2754 end of a function. */
2757 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2759 if (mips_pc_is_mips16 (pc
))
2760 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2761 generates a "jr $ra"; other times it generates code to load
2762 the return address from the stack to an accessible register (such
2763 as $a3), then a "jr" using that register. This second case
2764 is almost impossible to distinguish from an indirect jump
2765 used for switch statements, so we don't even try. */
2766 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2768 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2772 /* This fencepost looks highly suspicious to me. Removing it also
2773 seems suspicious as it could affect remote debugging across serial
2777 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2783 struct inferior
*inf
;
2785 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2787 fence
= start_pc
- heuristic_fence_post
;
2791 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2792 fence
= VM_MIN_ADDRESS
;
2794 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2796 inf
= current_inferior ();
2798 /* Search back for previous return. */
2799 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2800 if (start_pc
< fence
)
2802 /* It's not clear to me why we reach this point when
2803 stop_soon, but with this test, at least we
2804 don't print out warnings for every child forked (eg, on
2805 decstation). 22apr93 rich@cygnus.com. */
2806 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2808 static int blurb_printed
= 0;
2810 warning (_("GDB can't find the start of the function at %s."),
2811 paddress (gdbarch
, pc
));
2815 /* This actually happens frequently in embedded
2816 development, when you first connect to a board
2817 and your stack pointer and pc are nowhere in
2818 particular. This message needs to give people
2819 in that situation enough information to
2820 determine that it's no big deal. */
2821 printf_filtered ("\n\
2822 GDB is unable to find the start of the function at %s\n\
2823 and thus can't determine the size of that function's stack frame.\n\
2824 This means that GDB may be unable to access that stack frame, or\n\
2825 the frames below it.\n\
2826 This problem is most likely caused by an invalid program counter or\n\
2828 However, if you think GDB should simply search farther back\n\
2829 from %s for code which looks like the beginning of a\n\
2830 function, you can increase the range of the search using the `set\n\
2831 heuristic-fence-post' command.\n",
2832 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2839 else if (mips_pc_is_mips16 (start_pc
))
2841 unsigned short inst
;
2843 /* On MIPS16, any one of the following is likely to be the
2844 start of a function:
2850 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2851 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2852 if ((inst
& 0xff80) == 0x6480) /* save */
2854 if (start_pc
- instlen
>= fence
)
2856 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2857 if ((inst
& 0xf800) == 0xf000) /* extend */
2858 start_pc
-= instlen
;
2862 else if (((inst
& 0xf81f) == 0xe809
2863 && (inst
& 0x700) != 0x700) /* entry */
2864 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2865 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2866 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2868 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2869 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2874 else if (mips_about_to_return (gdbarch
, start_pc
))
2876 /* Skip return and its delay slot. */
2877 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2884 struct mips_objfile_private
2890 /* According to the current ABI, should the type be passed in a
2891 floating-point register (assuming that there is space)? When there
2892 is no FPU, FP are not even considered as possible candidates for
2893 FP registers and, consequently this returns false - forces FP
2894 arguments into integer registers. */
2897 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2898 struct type
*arg_type
)
2900 return ((typecode
== TYPE_CODE_FLT
2901 || (MIPS_EABI (gdbarch
)
2902 && (typecode
== TYPE_CODE_STRUCT
2903 || typecode
== TYPE_CODE_UNION
)
2904 && TYPE_NFIELDS (arg_type
) == 1
2905 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2907 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2910 /* On o32, argument passing in GPRs depends on the alignment of the type being
2911 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2914 mips_type_needs_double_align (struct type
*type
)
2916 enum type_code typecode
= TYPE_CODE (type
);
2918 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2920 else if (typecode
== TYPE_CODE_STRUCT
)
2922 if (TYPE_NFIELDS (type
) < 1)
2924 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2926 else if (typecode
== TYPE_CODE_UNION
)
2930 n
= TYPE_NFIELDS (type
);
2931 for (i
= 0; i
< n
; i
++)
2932 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2939 /* Adjust the address downward (direction of stack growth) so that it
2940 is correctly aligned for a new stack frame. */
2942 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2944 return align_down (addr
, 16);
2948 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2949 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2950 int nargs
, struct value
**args
, CORE_ADDR sp
,
2951 int struct_return
, CORE_ADDR struct_addr
)
2957 int stack_offset
= 0;
2958 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2959 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2960 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2961 int regsize
= mips_abi_regsize (gdbarch
);
2963 /* For shared libraries, "t9" needs to point at the function
2965 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2967 /* Set the return address register to point to the entry point of
2968 the program, where a breakpoint lies in wait. */
2969 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2971 /* First ensure that the stack and structure return address (if any)
2972 are properly aligned. The stack has to be at least 64-bit
2973 aligned even on 32-bit machines, because doubles must be 64-bit
2974 aligned. For n32 and n64, stack frames need to be 128-bit
2975 aligned, so we round to this widest known alignment. */
2977 sp
= align_down (sp
, 16);
2978 struct_addr
= align_down (struct_addr
, 16);
2980 /* Now make space on the stack for the args. We allocate more
2981 than necessary for EABI, because the first few arguments are
2982 passed in registers, but that's OK. */
2983 for (argnum
= 0; argnum
< nargs
; argnum
++)
2984 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2985 sp
-= align_up (len
, 16);
2988 fprintf_unfiltered (gdb_stdlog
,
2989 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2990 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2992 /* Initialize the integer and float register pointers. */
2993 argreg
= MIPS_A0_REGNUM
;
2994 float_argreg
= mips_fpa0_regnum (gdbarch
);
2996 /* The struct_return pointer occupies the first parameter-passing reg. */
3000 fprintf_unfiltered (gdb_stdlog
,
3001 "mips_eabi_push_dummy_call: "
3002 "struct_return reg=%d %s\n",
3003 argreg
, paddress (gdbarch
, struct_addr
));
3004 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3007 /* Now load as many as possible of the first arguments into
3008 registers, and push the rest onto the stack. Loop thru args
3009 from first to last. */
3010 for (argnum
= 0; argnum
< nargs
; argnum
++)
3012 const gdb_byte
*val
;
3013 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
3014 struct value
*arg
= args
[argnum
];
3015 struct type
*arg_type
= check_typedef (value_type (arg
));
3016 int len
= TYPE_LENGTH (arg_type
);
3017 enum type_code typecode
= TYPE_CODE (arg_type
);
3020 fprintf_unfiltered (gdb_stdlog
,
3021 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3022 argnum
+ 1, len
, (int) typecode
);
3024 /* Function pointer arguments to mips16 code need to be made into
3026 if (typecode
== TYPE_CODE_PTR
3027 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
3029 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
3031 if (mips_pc_is_mips16 (addr
))
3033 store_signed_integer (valbuf
, len
, byte_order
,
3034 make_mips16_addr (addr
));
3038 val
= value_contents (arg
);
3040 /* The EABI passes structures that do not fit in a register by
3042 else if (len
> regsize
3043 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3045 store_unsigned_integer (valbuf
, regsize
, byte_order
,
3046 value_address (arg
));
3047 typecode
= TYPE_CODE_PTR
;
3051 fprintf_unfiltered (gdb_stdlog
, " push");
3054 val
= value_contents (arg
);
3056 /* 32-bit ABIs always start floating point arguments in an
3057 even-numbered floating point register. Round the FP register
3058 up before the check to see if there are any FP registers
3059 left. Non MIPS_EABI targets also pass the FP in the integer
3060 registers so also round up normal registers. */
3061 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3063 if ((float_argreg
& 1))
3067 /* Floating point arguments passed in registers have to be
3068 treated specially. On 32-bit architectures, doubles
3069 are passed in register pairs; the even register gets
3070 the low word, and the odd register gets the high word.
3071 On non-EABI processors, the first two floating point arguments are
3072 also copied to general registers, because MIPS16 functions
3073 don't use float registers for arguments. This duplication of
3074 arguments in general registers can't hurt non-MIPS16 functions
3075 because those registers are normally skipped. */
3076 /* MIPS_EABI squeezes a struct that contains a single floating
3077 point value into an FP register instead of pushing it onto the
3079 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3080 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3082 /* EABI32 will pass doubles in consecutive registers, even on
3083 64-bit cores. At one time, we used to check the size of
3084 `float_argreg' to determine whether or not to pass doubles
3085 in consecutive registers, but this is not sufficient for
3086 making the ABI determination. */
3087 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3089 int low_offset
= gdbarch_byte_order (gdbarch
)
3090 == BFD_ENDIAN_BIG
? 4 : 0;
3093 /* Write the low word of the double to the even register(s). */
3094 regval
= extract_signed_integer (val
+ low_offset
,
3097 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3098 float_argreg
, phex (regval
, 4));
3099 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3101 /* Write the high word of the double to the odd register(s). */
3102 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3105 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3106 float_argreg
, phex (regval
, 4));
3107 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3111 /* This is a floating point value that fits entirely
3112 in a single register. */
3113 /* On 32 bit ABI's the float_argreg is further adjusted
3114 above to ensure that it is even register aligned. */
3115 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3117 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3118 float_argreg
, phex (regval
, len
));
3119 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3124 /* Copy the argument to general registers or the stack in
3125 register-sized pieces. Large arguments are split between
3126 registers and stack. */
3127 /* Note: structs whose size is not a multiple of regsize
3128 are treated specially: Irix cc passes
3129 them in registers where gcc sometimes puts them on the
3130 stack. For maximum compatibility, we will put them in
3132 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3134 /* Note: Floating-point values that didn't fit into an FP
3135 register are only written to memory. */
3138 /* Remember if the argument was written to the stack. */
3139 int stack_used_p
= 0;
3140 int partial_len
= (len
< regsize
? len
: regsize
);
3143 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3146 /* Write this portion of the argument to the stack. */
3147 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3149 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3151 /* Should shorter than int integer values be
3152 promoted to int before being stored? */
3153 int longword_offset
= 0;
3156 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3159 && (typecode
== TYPE_CODE_INT
3160 || typecode
== TYPE_CODE_PTR
3161 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3162 longword_offset
= regsize
- len
;
3163 else if ((typecode
== TYPE_CODE_STRUCT
3164 || typecode
== TYPE_CODE_UNION
)
3165 && TYPE_LENGTH (arg_type
) < regsize
)
3166 longword_offset
= regsize
- len
;
3171 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3172 paddress (gdbarch
, stack_offset
));
3173 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3174 paddress (gdbarch
, longword_offset
));
3177 addr
= sp
+ stack_offset
+ longword_offset
;
3182 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3183 paddress (gdbarch
, addr
));
3184 for (i
= 0; i
< partial_len
; i
++)
3186 fprintf_unfiltered (gdb_stdlog
, "%02x",
3190 write_memory (addr
, val
, partial_len
);
3193 /* Note!!! This is NOT an else clause. Odd sized
3194 structs may go thru BOTH paths. Floating point
3195 arguments will not. */
3196 /* Write this portion of the argument to a general
3197 purpose register. */
3198 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3199 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3202 extract_signed_integer (val
, partial_len
, byte_order
);
3205 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3207 phex (regval
, regsize
));
3208 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3215 /* Compute the offset into the stack at which we will
3216 copy the next parameter.
3218 In the new EABI (and the NABI32), the stack_offset
3219 only needs to be adjusted when it has been used. */
3222 stack_offset
+= align_up (partial_len
, regsize
);
3226 fprintf_unfiltered (gdb_stdlog
, "\n");
3229 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3231 /* Return adjusted stack pointer. */
3235 /* Determine the return value convention being used. */
3237 static enum return_value_convention
3238 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3239 struct type
*type
, struct regcache
*regcache
,
3240 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3242 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3243 int fp_return_type
= 0;
3244 int offset
, regnum
, xfer
;
3246 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3247 return RETURN_VALUE_STRUCT_CONVENTION
;
3249 /* Floating point type? */
3250 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3252 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3254 /* Structs with a single field of float type
3255 are returned in a floating point register. */
3256 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3257 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3258 && TYPE_NFIELDS (type
) == 1)
3260 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3262 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3269 /* A floating-point value belongs in the least significant part
3272 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3273 regnum
= mips_regnum (gdbarch
)->fp0
;
3277 /* An integer value goes in V0/V1. */
3279 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3280 regnum
= MIPS_V0_REGNUM
;
3283 offset
< TYPE_LENGTH (type
);
3284 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3286 xfer
= mips_abi_regsize (gdbarch
);
3287 if (offset
+ xfer
> TYPE_LENGTH (type
))
3288 xfer
= TYPE_LENGTH (type
) - offset
;
3289 mips_xfer_register (gdbarch
, regcache
,
3290 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3291 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3295 return RETURN_VALUE_REGISTER_CONVENTION
;
3299 /* N32/N64 ABI stuff. */
3301 /* Search for a naturally aligned double at OFFSET inside a struct
3302 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3306 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3311 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3314 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3317 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3320 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3323 struct type
*field_type
;
3325 /* We're only looking at normal fields. */
3326 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3327 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3330 /* If we have gone past the offset, there is no double to pass. */
3331 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3335 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3337 /* If this field is entirely before the requested offset, go
3338 on to the next one. */
3339 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3342 /* If this is our special aligned double, we can stop. */
3343 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3344 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3347 /* This field starts at or before the requested offset, and
3348 overlaps it. If it is a structure, recurse inwards. */
3349 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3356 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3357 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3358 int nargs
, struct value
**args
, CORE_ADDR sp
,
3359 int struct_return
, CORE_ADDR struct_addr
)
3365 int stack_offset
= 0;
3366 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3367 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3368 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3370 /* For shared libraries, "t9" needs to point at the function
3372 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3374 /* Set the return address register to point to the entry point of
3375 the program, where a breakpoint lies in wait. */
3376 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3378 /* First ensure that the stack and structure return address (if any)
3379 are properly aligned. The stack has to be at least 64-bit
3380 aligned even on 32-bit machines, because doubles must be 64-bit
3381 aligned. For n32 and n64, stack frames need to be 128-bit
3382 aligned, so we round to this widest known alignment. */
3384 sp
= align_down (sp
, 16);
3385 struct_addr
= align_down (struct_addr
, 16);
3387 /* Now make space on the stack for the args. */
3388 for (argnum
= 0; argnum
< nargs
; argnum
++)
3389 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3390 sp
-= align_up (len
, 16);
3393 fprintf_unfiltered (gdb_stdlog
,
3394 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3395 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3397 /* Initialize the integer and float register pointers. */
3398 argreg
= MIPS_A0_REGNUM
;
3399 float_argreg
= mips_fpa0_regnum (gdbarch
);
3401 /* The struct_return pointer occupies the first parameter-passing reg. */
3405 fprintf_unfiltered (gdb_stdlog
,
3406 "mips_n32n64_push_dummy_call: "
3407 "struct_return reg=%d %s\n",
3408 argreg
, paddress (gdbarch
, struct_addr
));
3409 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3412 /* Now load as many as possible of the first arguments into
3413 registers, and push the rest onto the stack. Loop thru args
3414 from first to last. */
3415 for (argnum
= 0; argnum
< nargs
; argnum
++)
3417 const gdb_byte
*val
;
3418 struct value
*arg
= args
[argnum
];
3419 struct type
*arg_type
= check_typedef (value_type (arg
));
3420 int len
= TYPE_LENGTH (arg_type
);
3421 enum type_code typecode
= TYPE_CODE (arg_type
);
3424 fprintf_unfiltered (gdb_stdlog
,
3425 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3426 argnum
+ 1, len
, (int) typecode
);
3428 val
= value_contents (arg
);
3430 /* A 128-bit long double value requires an even-odd pair of
3431 floating-point registers. */
3433 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3434 && (float_argreg
& 1))
3440 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3441 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3443 /* This is a floating point value that fits entirely
3444 in a single register or a pair of registers. */
3445 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3446 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3448 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3449 float_argreg
, phex (regval
, reglen
));
3450 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3453 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3454 argreg
, phex (regval
, reglen
));
3455 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3460 regval
= extract_unsigned_integer (val
+ reglen
,
3461 reglen
, byte_order
);
3463 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3464 float_argreg
, phex (regval
, reglen
));
3465 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3468 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3469 argreg
, phex (regval
, reglen
));
3470 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3477 /* Copy the argument to general registers or the stack in
3478 register-sized pieces. Large arguments are split between
3479 registers and stack. */
3480 /* For N32/N64, structs, unions, or other composite types are
3481 treated as a sequence of doublewords, and are passed in integer
3482 or floating point registers as though they were simple scalar
3483 parameters to the extent that they fit, with any excess on the
3484 stack packed according to the normal memory layout of the
3486 The caller does not reserve space for the register arguments;
3487 the callee is responsible for reserving it if required. */
3488 /* Note: Floating-point values that didn't fit into an FP
3489 register are only written to memory. */
3492 /* Remember if the argument was written to the stack. */
3493 int stack_used_p
= 0;
3494 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3497 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3500 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3501 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3503 /* Write this portion of the argument to the stack. */
3504 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3506 /* Should shorter than int integer values be
3507 promoted to int before being stored? */
3508 int longword_offset
= 0;
3511 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3513 if ((typecode
== TYPE_CODE_INT
3514 || typecode
== TYPE_CODE_PTR
)
3516 longword_offset
= MIPS64_REGSIZE
- len
;
3521 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3522 paddress (gdbarch
, stack_offset
));
3523 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3524 paddress (gdbarch
, longword_offset
));
3527 addr
= sp
+ stack_offset
+ longword_offset
;
3532 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3533 paddress (gdbarch
, addr
));
3534 for (i
= 0; i
< partial_len
; i
++)
3536 fprintf_unfiltered (gdb_stdlog
, "%02x",
3540 write_memory (addr
, val
, partial_len
);
3543 /* Note!!! This is NOT an else clause. Odd sized
3544 structs may go thru BOTH paths. */
3545 /* Write this portion of the argument to a general
3546 purpose register. */
3547 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3551 /* Sign extend pointers, 32-bit integers and signed
3552 16-bit and 8-bit integers; everything else is taken
3555 if ((partial_len
== 4
3556 && (typecode
== TYPE_CODE_PTR
3557 || typecode
== TYPE_CODE_INT
))
3559 && typecode
== TYPE_CODE_INT
3560 && !TYPE_UNSIGNED (arg_type
)))
3561 regval
= extract_signed_integer (val
, partial_len
,
3564 regval
= extract_unsigned_integer (val
, partial_len
,
3567 /* A non-floating-point argument being passed in a
3568 general register. If a struct or union, and if
3569 the remaining length is smaller than the register
3570 size, we have to adjust the register value on
3573 It does not seem to be necessary to do the
3574 same for integral types. */
3576 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3577 && partial_len
< MIPS64_REGSIZE
3578 && (typecode
== TYPE_CODE_STRUCT
3579 || typecode
== TYPE_CODE_UNION
))
3580 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3584 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3586 phex (regval
, MIPS64_REGSIZE
));
3587 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3589 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3590 TYPE_LENGTH (arg_type
) - len
))
3593 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3595 phex (regval
, MIPS64_REGSIZE
));
3596 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3607 /* Compute the offset into the stack at which we will
3608 copy the next parameter.
3610 In N32 (N64?), the stack_offset only needs to be
3611 adjusted when it has been used. */
3614 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3618 fprintf_unfiltered (gdb_stdlog
, "\n");
3621 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3623 /* Return adjusted stack pointer. */
3627 static enum return_value_convention
3628 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3629 struct type
*type
, struct regcache
*regcache
,
3630 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3632 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3634 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3636 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3637 if needed), as appropriate for the type. Composite results (struct,
3638 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3641 * A struct with only one or two floating point fields is returned in $f0
3642 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3645 * Any other composite results of at most 128 bits are returned in
3646 $2 (first 64 bits) and $3 (remainder, if necessary).
3648 * Larger composite results are handled by converting the function to a
3649 procedure with an implicit first parameter, which is a pointer to an area
3650 reserved by the caller to receive the result. [The o32-bit ABI requires
3651 that all composite results be handled by conversion to implicit first
3652 parameters. The MIPS/SGI Fortran implementation has always made a
3653 specific exception to return COMPLEX results in the floating point
3656 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3657 return RETURN_VALUE_STRUCT_CONVENTION
;
3658 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3659 && TYPE_LENGTH (type
) == 16
3660 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3662 /* A 128-bit floating-point value fills both $f0 and $f2. The
3663 two registers are used in the same as memory order, so the
3664 eight bytes with the lower memory address are in $f0. */
3666 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3667 mips_xfer_register (gdbarch
, regcache
,
3668 gdbarch_num_regs (gdbarch
)
3669 + mips_regnum (gdbarch
)->fp0
,
3670 8, gdbarch_byte_order (gdbarch
),
3671 readbuf
, writebuf
, 0);
3672 mips_xfer_register (gdbarch
, regcache
,
3673 gdbarch_num_regs (gdbarch
)
3674 + mips_regnum (gdbarch
)->fp0
+ 2,
3675 8, gdbarch_byte_order (gdbarch
),
3676 readbuf
? readbuf
+ 8 : readbuf
,
3677 writebuf
? writebuf
+ 8 : writebuf
, 0);
3678 return RETURN_VALUE_REGISTER_CONVENTION
;
3680 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3681 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3683 /* A single or double floating-point value that fits in FP0. */
3685 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3686 mips_xfer_register (gdbarch
, regcache
,
3687 gdbarch_num_regs (gdbarch
)
3688 + mips_regnum (gdbarch
)->fp0
,
3690 gdbarch_byte_order (gdbarch
),
3691 readbuf
, writebuf
, 0);
3692 return RETURN_VALUE_REGISTER_CONVENTION
;
3694 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3695 && TYPE_NFIELDS (type
) <= 2
3696 && TYPE_NFIELDS (type
) >= 1
3697 && ((TYPE_NFIELDS (type
) == 1
3698 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3700 || (TYPE_NFIELDS (type
) == 2
3701 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3703 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3704 == TYPE_CODE_FLT
))))
3706 /* A struct that contains one or two floats. Each value is part
3707 in the least significant part of their floating point
3708 register (or GPR, for soft float). */
3711 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3712 ? mips_regnum (gdbarch
)->fp0
3714 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3716 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3719 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3721 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3723 /* A 16-byte long double field goes in two consecutive
3725 mips_xfer_register (gdbarch
, regcache
,
3726 gdbarch_num_regs (gdbarch
) + regnum
,
3728 gdbarch_byte_order (gdbarch
),
3729 readbuf
, writebuf
, offset
);
3730 mips_xfer_register (gdbarch
, regcache
,
3731 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3733 gdbarch_byte_order (gdbarch
),
3734 readbuf
, writebuf
, offset
+ 8);
3737 mips_xfer_register (gdbarch
, regcache
,
3738 gdbarch_num_regs (gdbarch
) + regnum
,
3739 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3740 gdbarch_byte_order (gdbarch
),
3741 readbuf
, writebuf
, offset
);
3743 return RETURN_VALUE_REGISTER_CONVENTION
;
3745 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3746 || TYPE_CODE (type
) == TYPE_CODE_UNION
3747 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3749 /* A composite type. Extract the left justified value,
3750 regardless of the byte order. I.e. DO NOT USE
3754 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3755 offset
< TYPE_LENGTH (type
);
3756 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3758 int xfer
= register_size (gdbarch
, regnum
);
3759 if (offset
+ xfer
> TYPE_LENGTH (type
))
3760 xfer
= TYPE_LENGTH (type
) - offset
;
3762 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3763 offset
, xfer
, regnum
);
3764 mips_xfer_register (gdbarch
, regcache
,
3765 gdbarch_num_regs (gdbarch
) + regnum
,
3766 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3769 return RETURN_VALUE_REGISTER_CONVENTION
;
3773 /* A scalar extract each part but least-significant-byte
3777 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3778 offset
< TYPE_LENGTH (type
);
3779 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3781 int xfer
= register_size (gdbarch
, regnum
);
3782 if (offset
+ xfer
> TYPE_LENGTH (type
))
3783 xfer
= TYPE_LENGTH (type
) - offset
;
3785 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3786 offset
, xfer
, regnum
);
3787 mips_xfer_register (gdbarch
, regcache
,
3788 gdbarch_num_regs (gdbarch
) + regnum
,
3789 xfer
, gdbarch_byte_order (gdbarch
),
3790 readbuf
, writebuf
, offset
);
3792 return RETURN_VALUE_REGISTER_CONVENTION
;
3796 /* O32 ABI stuff. */
3799 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3800 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3801 int nargs
, struct value
**args
, CORE_ADDR sp
,
3802 int struct_return
, CORE_ADDR struct_addr
)
3808 int stack_offset
= 0;
3809 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3810 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3811 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3813 /* For shared libraries, "t9" needs to point at the function
3815 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3817 /* Set the return address register to point to the entry point of
3818 the program, where a breakpoint lies in wait. */
3819 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3821 /* First ensure that the stack and structure return address (if any)
3822 are properly aligned. The stack has to be at least 64-bit
3823 aligned even on 32-bit machines, because doubles must be 64-bit
3824 aligned. For n32 and n64, stack frames need to be 128-bit
3825 aligned, so we round to this widest known alignment. */
3827 sp
= align_down (sp
, 16);
3828 struct_addr
= align_down (struct_addr
, 16);
3830 /* Now make space on the stack for the args. */
3831 for (argnum
= 0; argnum
< nargs
; argnum
++)
3833 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3834 int arglen
= TYPE_LENGTH (arg_type
);
3836 /* Align to double-word if necessary. */
3837 if (mips_type_needs_double_align (arg_type
))
3838 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3839 /* Allocate space on the stack. */
3840 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3842 sp
-= align_up (len
, 16);
3845 fprintf_unfiltered (gdb_stdlog
,
3846 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3847 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3849 /* Initialize the integer and float register pointers. */
3850 argreg
= MIPS_A0_REGNUM
;
3851 float_argreg
= mips_fpa0_regnum (gdbarch
);
3853 /* The struct_return pointer occupies the first parameter-passing reg. */
3857 fprintf_unfiltered (gdb_stdlog
,
3858 "mips_o32_push_dummy_call: "
3859 "struct_return reg=%d %s\n",
3860 argreg
, paddress (gdbarch
, struct_addr
));
3861 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3862 stack_offset
+= MIPS32_REGSIZE
;
3865 /* Now load as many as possible of the first arguments into
3866 registers, and push the rest onto the stack. Loop thru args
3867 from first to last. */
3868 for (argnum
= 0; argnum
< nargs
; argnum
++)
3870 const gdb_byte
*val
;
3871 struct value
*arg
= args
[argnum
];
3872 struct type
*arg_type
= check_typedef (value_type (arg
));
3873 int len
= TYPE_LENGTH (arg_type
);
3874 enum type_code typecode
= TYPE_CODE (arg_type
);
3877 fprintf_unfiltered (gdb_stdlog
,
3878 "mips_o32_push_dummy_call: %d len=%d type=%d",
3879 argnum
+ 1, len
, (int) typecode
);
3881 val
= value_contents (arg
);
3883 /* 32-bit ABIs always start floating point arguments in an
3884 even-numbered floating point register. Round the FP register
3885 up before the check to see if there are any FP registers
3886 left. O32/O64 targets also pass the FP in the integer
3887 registers so also round up normal registers. */
3888 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3890 if ((float_argreg
& 1))
3894 /* Floating point arguments passed in registers have to be
3895 treated specially. On 32-bit architectures, doubles
3896 are passed in register pairs; the even register gets
3897 the low word, and the odd register gets the high word.
3898 On O32/O64, the first two floating point arguments are
3899 also copied to general registers, because MIPS16 functions
3900 don't use float registers for arguments. This duplication of
3901 arguments in general registers can't hurt non-MIPS16 functions
3902 because those registers are normally skipped. */
3904 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3905 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3907 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3909 int low_offset
= gdbarch_byte_order (gdbarch
)
3910 == BFD_ENDIAN_BIG
? 4 : 0;
3911 unsigned long regval
;
3913 /* Write the low word of the double to the even register(s). */
3914 regval
= extract_unsigned_integer (val
+ low_offset
,
3917 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3918 float_argreg
, phex (regval
, 4));
3919 regcache_cooked_write_unsigned (regcache
,
3920 float_argreg
++, regval
);
3922 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3923 argreg
, phex (regval
, 4));
3924 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3926 /* Write the high word of the double to the odd register(s). */
3927 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3930 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3931 float_argreg
, phex (regval
, 4));
3932 regcache_cooked_write_unsigned (regcache
,
3933 float_argreg
++, regval
);
3936 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3937 argreg
, phex (regval
, 4));
3938 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3942 /* This is a floating point value that fits entirely
3943 in a single register. */
3944 /* On 32 bit ABI's the float_argreg is further adjusted
3945 above to ensure that it is even register aligned. */
3946 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3948 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3949 float_argreg
, phex (regval
, len
));
3950 regcache_cooked_write_unsigned (regcache
,
3951 float_argreg
++, regval
);
3952 /* Although two FP registers are reserved for each
3953 argument, only one corresponding integer register is
3956 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3957 argreg
, phex (regval
, len
));
3958 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3960 /* Reserve space for the FP register. */
3961 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3965 /* Copy the argument to general registers or the stack in
3966 register-sized pieces. Large arguments are split between
3967 registers and stack. */
3968 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3969 are treated specially: Irix cc passes
3970 them in registers where gcc sometimes puts them on the
3971 stack. For maximum compatibility, we will put them in
3973 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3974 && len
% MIPS32_REGSIZE
!= 0);
3975 /* Structures should be aligned to eight bytes (even arg registers)
3976 on MIPS_ABI_O32, if their first member has double precision. */
3977 if (mips_type_needs_double_align (arg_type
))
3982 stack_offset
+= MIPS32_REGSIZE
;
3987 /* Remember if the argument was written to the stack. */
3988 int stack_used_p
= 0;
3989 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3992 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3995 /* Write this portion of the argument to the stack. */
3996 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3997 || odd_sized_struct
)
3999 /* Should shorter than int integer values be
4000 promoted to int before being stored? */
4001 int longword_offset
= 0;
4007 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4008 paddress (gdbarch
, stack_offset
));
4009 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4010 paddress (gdbarch
, longword_offset
));
4013 addr
= sp
+ stack_offset
+ longword_offset
;
4018 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4019 paddress (gdbarch
, addr
));
4020 for (i
= 0; i
< partial_len
; i
++)
4022 fprintf_unfiltered (gdb_stdlog
, "%02x",
4026 write_memory (addr
, val
, partial_len
);
4029 /* Note!!! This is NOT an else clause. Odd sized
4030 structs may go thru BOTH paths. */
4031 /* Write this portion of the argument to a general
4032 purpose register. */
4033 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4035 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4037 /* Value may need to be sign extended, because
4038 mips_isa_regsize() != mips_abi_regsize(). */
4040 /* A non-floating-point argument being passed in a
4041 general register. If a struct or union, and if
4042 the remaining length is smaller than the register
4043 size, we have to adjust the register value on
4046 It does not seem to be necessary to do the
4047 same for integral types.
4049 Also don't do this adjustment on O64 binaries.
4051 cagney/2001-07-23: gdb/179: Also, GCC, when
4052 outputting LE O32 with sizeof (struct) <
4053 mips_abi_regsize(), generates a left shift
4054 as part of storing the argument in a register
4055 (the left shift isn't generated when
4056 sizeof (struct) >= mips_abi_regsize()). Since
4057 it is quite possible that this is GCC
4058 contradicting the LE/O32 ABI, GDB has not been
4059 adjusted to accommodate this. Either someone
4060 needs to demonstrate that the LE/O32 ABI
4061 specifies such a left shift OR this new ABI gets
4062 identified as such and GDB gets tweaked
4065 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4066 && partial_len
< MIPS32_REGSIZE
4067 && (typecode
== TYPE_CODE_STRUCT
4068 || typecode
== TYPE_CODE_UNION
))
4069 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4073 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4075 phex (regval
, MIPS32_REGSIZE
));
4076 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4079 /* Prevent subsequent floating point arguments from
4080 being passed in floating point registers. */
4081 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4087 /* Compute the offset into the stack at which we will
4088 copy the next parameter.
4090 In older ABIs, the caller reserved space for
4091 registers that contained arguments. This was loosely
4092 refered to as their "home". Consequently, space is
4093 always allocated. */
4095 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4099 fprintf_unfiltered (gdb_stdlog
, "\n");
4102 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4104 /* Return adjusted stack pointer. */
4108 static enum return_value_convention
4109 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4110 struct type
*type
, struct regcache
*regcache
,
4111 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4113 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4115 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4116 || TYPE_CODE (type
) == TYPE_CODE_UNION
4117 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4118 return RETURN_VALUE_STRUCT_CONVENTION
;
4119 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4120 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4122 /* A single-precision floating-point value. It fits in the
4123 least significant part of FP0. */
4125 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4126 mips_xfer_register (gdbarch
, regcache
,
4127 gdbarch_num_regs (gdbarch
)
4128 + mips_regnum (gdbarch
)->fp0
,
4130 gdbarch_byte_order (gdbarch
),
4131 readbuf
, writebuf
, 0);
4132 return RETURN_VALUE_REGISTER_CONVENTION
;
4134 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4135 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4137 /* A double-precision floating-point value. The most
4138 significant part goes in FP1, and the least significant in
4141 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4142 switch (gdbarch_byte_order (gdbarch
))
4144 case BFD_ENDIAN_LITTLE
:
4145 mips_xfer_register (gdbarch
, regcache
,
4146 gdbarch_num_regs (gdbarch
)
4147 + mips_regnum (gdbarch
)->fp0
+
4148 0, 4, gdbarch_byte_order (gdbarch
),
4149 readbuf
, writebuf
, 0);
4150 mips_xfer_register (gdbarch
, regcache
,
4151 gdbarch_num_regs (gdbarch
)
4152 + mips_regnum (gdbarch
)->fp0
+ 1,
4153 4, gdbarch_byte_order (gdbarch
),
4154 readbuf
, writebuf
, 4);
4156 case BFD_ENDIAN_BIG
:
4157 mips_xfer_register (gdbarch
, regcache
,
4158 gdbarch_num_regs (gdbarch
)
4159 + mips_regnum (gdbarch
)->fp0
+ 1,
4160 4, gdbarch_byte_order (gdbarch
),
4161 readbuf
, writebuf
, 0);
4162 mips_xfer_register (gdbarch
, regcache
,
4163 gdbarch_num_regs (gdbarch
)
4164 + mips_regnum (gdbarch
)->fp0
+ 0,
4165 4, gdbarch_byte_order (gdbarch
),
4166 readbuf
, writebuf
, 4);
4169 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4171 return RETURN_VALUE_REGISTER_CONVENTION
;
4174 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4175 && TYPE_NFIELDS (type
) <= 2
4176 && TYPE_NFIELDS (type
) >= 1
4177 && ((TYPE_NFIELDS (type
) == 1
4178 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4180 || (TYPE_NFIELDS (type
) == 2
4181 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4183 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4185 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4187 /* A struct that contains one or two floats. Each value is part
4188 in the least significant part of their floating point
4190 gdb_byte reg
[MAX_REGISTER_SIZE
];
4193 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4194 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4196 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4199 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4201 mips_xfer_register (gdbarch
, regcache
,
4202 gdbarch_num_regs (gdbarch
) + regnum
,
4203 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4204 gdbarch_byte_order (gdbarch
),
4205 readbuf
, writebuf
, offset
);
4207 return RETURN_VALUE_REGISTER_CONVENTION
;
4211 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4212 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4214 /* A structure or union. Extract the left justified value,
4215 regardless of the byte order. I.e. DO NOT USE
4219 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4220 offset
< TYPE_LENGTH (type
);
4221 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4223 int xfer
= register_size (gdbarch
, regnum
);
4224 if (offset
+ xfer
> TYPE_LENGTH (type
))
4225 xfer
= TYPE_LENGTH (type
) - offset
;
4227 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4228 offset
, xfer
, regnum
);
4229 mips_xfer_register (gdbarch
, regcache
,
4230 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4231 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4233 return RETURN_VALUE_REGISTER_CONVENTION
;
4238 /* A scalar extract each part but least-significant-byte
4239 justified. o32 thinks registers are 4 byte, regardless of
4243 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4244 offset
< TYPE_LENGTH (type
);
4245 offset
+= MIPS32_REGSIZE
, regnum
++)
4247 int xfer
= MIPS32_REGSIZE
;
4248 if (offset
+ xfer
> TYPE_LENGTH (type
))
4249 xfer
= TYPE_LENGTH (type
) - offset
;
4251 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4252 offset
, xfer
, regnum
);
4253 mips_xfer_register (gdbarch
, regcache
,
4254 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4255 gdbarch_byte_order (gdbarch
),
4256 readbuf
, writebuf
, offset
);
4258 return RETURN_VALUE_REGISTER_CONVENTION
;
4262 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4266 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4267 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4269 struct value
**args
, CORE_ADDR sp
,
4270 int struct_return
, CORE_ADDR struct_addr
)
4276 int stack_offset
= 0;
4277 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4278 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4279 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4281 /* For shared libraries, "t9" needs to point at the function
4283 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4285 /* Set the return address register to point to the entry point of
4286 the program, where a breakpoint lies in wait. */
4287 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4289 /* First ensure that the stack and structure return address (if any)
4290 are properly aligned. The stack has to be at least 64-bit
4291 aligned even on 32-bit machines, because doubles must be 64-bit
4292 aligned. For n32 and n64, stack frames need to be 128-bit
4293 aligned, so we round to this widest known alignment. */
4295 sp
= align_down (sp
, 16);
4296 struct_addr
= align_down (struct_addr
, 16);
4298 /* Now make space on the stack for the args. */
4299 for (argnum
= 0; argnum
< nargs
; argnum
++)
4301 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4302 int arglen
= TYPE_LENGTH (arg_type
);
4304 /* Allocate space on the stack. */
4305 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4307 sp
-= align_up (len
, 16);
4310 fprintf_unfiltered (gdb_stdlog
,
4311 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4312 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4314 /* Initialize the integer and float register pointers. */
4315 argreg
= MIPS_A0_REGNUM
;
4316 float_argreg
= mips_fpa0_regnum (gdbarch
);
4318 /* The struct_return pointer occupies the first parameter-passing reg. */
4322 fprintf_unfiltered (gdb_stdlog
,
4323 "mips_o64_push_dummy_call: "
4324 "struct_return reg=%d %s\n",
4325 argreg
, paddress (gdbarch
, struct_addr
));
4326 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4327 stack_offset
+= MIPS64_REGSIZE
;
4330 /* Now load as many as possible of the first arguments into
4331 registers, and push the rest onto the stack. Loop thru args
4332 from first to last. */
4333 for (argnum
= 0; argnum
< nargs
; argnum
++)
4335 const gdb_byte
*val
;
4336 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4337 struct value
*arg
= args
[argnum
];
4338 struct type
*arg_type
= check_typedef (value_type (arg
));
4339 int len
= TYPE_LENGTH (arg_type
);
4340 enum type_code typecode
= TYPE_CODE (arg_type
);
4343 fprintf_unfiltered (gdb_stdlog
,
4344 "mips_o64_push_dummy_call: %d len=%d type=%d",
4345 argnum
+ 1, len
, (int) typecode
);
4347 val
= value_contents (arg
);
4349 /* Function pointer arguments to mips16 code need to be made into
4351 if (typecode
== TYPE_CODE_PTR
4352 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4354 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4356 if (mips_pc_is_mips16 (addr
))
4358 store_signed_integer (valbuf
, len
, byte_order
,
4359 make_mips16_addr (addr
));
4364 /* Floating point arguments passed in registers have to be
4365 treated specially. On 32-bit architectures, doubles
4366 are passed in register pairs; the even register gets
4367 the low word, and the odd register gets the high word.
4368 On O32/O64, the first two floating point arguments are
4369 also copied to general registers, because MIPS16 functions
4370 don't use float registers for arguments. This duplication of
4371 arguments in general registers can't hurt non-MIPS16 functions
4372 because those registers are normally skipped. */
4374 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4375 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4377 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4379 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4380 float_argreg
, phex (regval
, len
));
4381 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4383 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4384 argreg
, phex (regval
, len
));
4385 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4387 /* Reserve space for the FP register. */
4388 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4392 /* Copy the argument to general registers or the stack in
4393 register-sized pieces. Large arguments are split between
4394 registers and stack. */
4395 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4396 are treated specially: Irix cc passes them in registers
4397 where gcc sometimes puts them on the stack. For maximum
4398 compatibility, we will put them in both places. */
4399 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4400 && len
% MIPS64_REGSIZE
!= 0);
4403 /* Remember if the argument was written to the stack. */
4404 int stack_used_p
= 0;
4405 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4408 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4411 /* Write this portion of the argument to the stack. */
4412 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4413 || odd_sized_struct
)
4415 /* Should shorter than int integer values be
4416 promoted to int before being stored? */
4417 int longword_offset
= 0;
4420 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4422 if ((typecode
== TYPE_CODE_INT
4423 || typecode
== TYPE_CODE_PTR
4424 || typecode
== TYPE_CODE_FLT
)
4426 longword_offset
= MIPS64_REGSIZE
- len
;
4431 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4432 paddress (gdbarch
, stack_offset
));
4433 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4434 paddress (gdbarch
, longword_offset
));
4437 addr
= sp
+ stack_offset
+ longword_offset
;
4442 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4443 paddress (gdbarch
, addr
));
4444 for (i
= 0; i
< partial_len
; i
++)
4446 fprintf_unfiltered (gdb_stdlog
, "%02x",
4450 write_memory (addr
, val
, partial_len
);
4453 /* Note!!! This is NOT an else clause. Odd sized
4454 structs may go thru BOTH paths. */
4455 /* Write this portion of the argument to a general
4456 purpose register. */
4457 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4459 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4461 /* Value may need to be sign extended, because
4462 mips_isa_regsize() != mips_abi_regsize(). */
4464 /* A non-floating-point argument being passed in a
4465 general register. If a struct or union, and if
4466 the remaining length is smaller than the register
4467 size, we have to adjust the register value on
4470 It does not seem to be necessary to do the
4471 same for integral types. */
4473 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4474 && partial_len
< MIPS64_REGSIZE
4475 && (typecode
== TYPE_CODE_STRUCT
4476 || typecode
== TYPE_CODE_UNION
))
4477 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4481 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4483 phex (regval
, MIPS64_REGSIZE
));
4484 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4487 /* Prevent subsequent floating point arguments from
4488 being passed in floating point registers. */
4489 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4495 /* Compute the offset into the stack at which we will
4496 copy the next parameter.
4498 In older ABIs, the caller reserved space for
4499 registers that contained arguments. This was loosely
4500 refered to as their "home". Consequently, space is
4501 always allocated. */
4503 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4507 fprintf_unfiltered (gdb_stdlog
, "\n");
4510 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4512 /* Return adjusted stack pointer. */
4516 static enum return_value_convention
4517 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4518 struct type
*type
, struct regcache
*regcache
,
4519 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4521 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4523 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4524 || TYPE_CODE (type
) == TYPE_CODE_UNION
4525 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4526 return RETURN_VALUE_STRUCT_CONVENTION
;
4527 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4529 /* A floating-point value. It fits in the least significant
4532 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4533 mips_xfer_register (gdbarch
, regcache
,
4534 gdbarch_num_regs (gdbarch
)
4535 + mips_regnum (gdbarch
)->fp0
,
4537 gdbarch_byte_order (gdbarch
),
4538 readbuf
, writebuf
, 0);
4539 return RETURN_VALUE_REGISTER_CONVENTION
;
4543 /* A scalar extract each part but least-significant-byte
4547 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4548 offset
< TYPE_LENGTH (type
);
4549 offset
+= MIPS64_REGSIZE
, regnum
++)
4551 int xfer
= MIPS64_REGSIZE
;
4552 if (offset
+ xfer
> TYPE_LENGTH (type
))
4553 xfer
= TYPE_LENGTH (type
) - offset
;
4555 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4556 offset
, xfer
, regnum
);
4557 mips_xfer_register (gdbarch
, regcache
,
4558 gdbarch_num_regs (gdbarch
) + regnum
,
4559 xfer
, gdbarch_byte_order (gdbarch
),
4560 readbuf
, writebuf
, offset
);
4562 return RETURN_VALUE_REGISTER_CONVENTION
;
4566 /* Floating point register management.
4568 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4569 64bit operations, these early MIPS cpus treat fp register pairs
4570 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4571 registers and offer a compatibility mode that emulates the MIPS2 fp
4572 model. When operating in MIPS2 fp compat mode, later cpu's split
4573 double precision floats into two 32-bit chunks and store them in
4574 consecutive fp regs. To display 64-bit floats stored in this
4575 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4576 Throw in user-configurable endianness and you have a real mess.
4578 The way this works is:
4579 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4580 double-precision value will be split across two logical registers.
4581 The lower-numbered logical register will hold the low-order bits,
4582 regardless of the processor's endianness.
4583 - If we are on a 64-bit processor, and we are looking for a
4584 single-precision value, it will be in the low ordered bits
4585 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4586 save slot in memory.
4587 - If we are in 64-bit mode, everything is straightforward.
4589 Note that this code only deals with "live" registers at the top of the
4590 stack. We will attempt to deal with saved registers later, when
4591 the raw/cooked register interface is in place. (We need a general
4592 interface that can deal with dynamic saved register sizes -- fp
4593 regs could be 32 bits wide in one frame and 64 on the frame above
4596 /* Copy a 32-bit single-precision value from the current frame
4597 into rare_buffer. */
4600 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4601 gdb_byte
*rare_buffer
)
4603 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4604 int raw_size
= register_size (gdbarch
, regno
);
4605 gdb_byte
*raw_buffer
= alloca (raw_size
);
4607 if (!frame_register_read (frame
, regno
, raw_buffer
))
4608 error (_("can't read register %d (%s)"),
4609 regno
, gdbarch_register_name (gdbarch
, regno
));
4612 /* We have a 64-bit value for this register. Find the low-order
4616 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4621 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4625 memcpy (rare_buffer
, raw_buffer
, 4);
4629 /* Copy a 64-bit double-precision value from the current frame into
4630 rare_buffer. This may include getting half of it from the next
4634 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4635 gdb_byte
*rare_buffer
)
4637 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4638 int raw_size
= register_size (gdbarch
, regno
);
4640 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4642 /* We have a 64-bit value for this register, and we should use
4644 if (!frame_register_read (frame
, regno
, rare_buffer
))
4645 error (_("can't read register %d (%s)"),
4646 regno
, gdbarch_register_name (gdbarch
, regno
));
4650 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4652 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4653 internal_error (__FILE__
, __LINE__
,
4654 _("mips_read_fp_register_double: bad access to "
4655 "odd-numbered FP register"));
4657 /* mips_read_fp_register_single will find the correct 32 bits from
4659 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4661 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4662 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4666 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4667 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4673 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4675 { /* Do values for FP (float) regs. */
4676 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4677 gdb_byte
*raw_buffer
;
4678 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4681 raw_buffer
= alloca (2 * register_size (gdbarch
,
4682 mips_regnum (gdbarch
)->fp0
));
4684 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4685 fprintf_filtered (file
, "%*s",
4686 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4689 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4691 struct value_print_options opts
;
4693 /* 4-byte registers: Print hex and floating. Also print even
4694 numbered registers as doubles. */
4695 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4696 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4699 get_formatted_print_options (&opts
, 'x');
4700 print_scalar_formatted (raw_buffer
,
4701 builtin_type (gdbarch
)->builtin_uint32
,
4704 fprintf_filtered (file
, " flt: ");
4706 fprintf_filtered (file
, " <invalid float> ");
4708 fprintf_filtered (file
, "%-17.9g", flt1
);
4710 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4712 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4713 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4716 fprintf_filtered (file
, " dbl: ");
4718 fprintf_filtered (file
, "<invalid double>");
4720 fprintf_filtered (file
, "%-24.17g", doub
);
4725 struct value_print_options opts
;
4727 /* Eight byte registers: print each one as hex, float and double. */
4728 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4729 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4732 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4733 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4736 get_formatted_print_options (&opts
, 'x');
4737 print_scalar_formatted (raw_buffer
,
4738 builtin_type (gdbarch
)->builtin_uint64
,
4741 fprintf_filtered (file
, " flt: ");
4743 fprintf_filtered (file
, "<invalid float>");
4745 fprintf_filtered (file
, "%-17.9g", flt1
);
4747 fprintf_filtered (file
, " dbl: ");
4749 fprintf_filtered (file
, "<invalid double>");
4751 fprintf_filtered (file
, "%-24.17g", doub
);
4756 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4759 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4761 struct value_print_options opts
;
4764 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4766 mips_print_fp_register (file
, frame
, regnum
);
4770 val
= get_frame_register_value (frame
, regnum
);
4771 if (value_optimized_out (val
))
4773 fprintf_filtered (file
, "%s: [Invalid]",
4774 gdbarch_register_name (gdbarch
, regnum
));
4778 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4780 /* The problem with printing numeric register names (r26, etc.) is that
4781 the user can't use them on input. Probably the best solution is to
4782 fix it so that either the numeric or the funky (a2, etc.) names
4783 are accepted on input. */
4784 if (regnum
< MIPS_NUMREGS
)
4785 fprintf_filtered (file
, "(r%d): ", regnum
);
4787 fprintf_filtered (file
, ": ");
4789 get_formatted_print_options (&opts
, 'x');
4790 val_print_scalar_formatted (value_type (val
),
4791 value_contents_for_printing (val
),
4792 value_embedded_offset (val
),
4797 /* Replacement for generic do_registers_info.
4798 Print regs in pretty columns. */
4801 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4804 fprintf_filtered (file
, " ");
4805 mips_print_fp_register (file
, frame
, regnum
);
4806 fprintf_filtered (file
, "\n");
4811 /* Print a row's worth of GP (int) registers, with name labels above. */
4814 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4817 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4818 /* Do values for GP (int) regs. */
4819 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4820 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4825 /* For GP registers, we print a separate row of names above the vals. */
4826 for (col
= 0, regnum
= start_regnum
;
4827 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4828 + gdbarch_num_pseudo_regs (gdbarch
);
4831 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4832 continue; /* unused register */
4833 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4835 break; /* End the row: reached FP register. */
4836 /* Large registers are handled separately. */
4837 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4840 break; /* End the row before this register. */
4842 /* Print this register on a row by itself. */
4843 mips_print_register (file
, frame
, regnum
);
4844 fprintf_filtered (file
, "\n");
4848 fprintf_filtered (file
, " ");
4849 fprintf_filtered (file
,
4850 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4851 gdbarch_register_name (gdbarch
, regnum
));
4858 /* Print the R0 to R31 names. */
4859 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4860 fprintf_filtered (file
, "\n R%-4d",
4861 start_regnum
% gdbarch_num_regs (gdbarch
));
4863 fprintf_filtered (file
, "\n ");
4865 /* Now print the values in hex, 4 or 8 to the row. */
4866 for (col
= 0, regnum
= start_regnum
;
4867 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4868 + gdbarch_num_pseudo_regs (gdbarch
);
4871 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4872 continue; /* unused register */
4873 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4875 break; /* End row: reached FP register. */
4876 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4877 break; /* End row: large register. */
4879 /* OK: get the data in raw format. */
4880 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4881 error (_("can't read register %d (%s)"),
4882 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4883 /* pad small registers */
4885 byte
< (mips_abi_regsize (gdbarch
)
4886 - register_size (gdbarch
, regnum
)); byte
++)
4887 printf_filtered (" ");
4888 /* Now print the register value in hex, endian order. */
4889 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4891 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4892 byte
< register_size (gdbarch
, regnum
); byte
++)
4893 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4895 for (byte
= register_size (gdbarch
, regnum
) - 1;
4897 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4898 fprintf_filtered (file
, " ");
4901 if (col
> 0) /* ie. if we actually printed anything... */
4902 fprintf_filtered (file
, "\n");
4907 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4910 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4911 struct frame_info
*frame
, int regnum
, int all
)
4913 if (regnum
!= -1) /* Do one specified register. */
4915 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4916 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4917 error (_("Not a valid register for the current processor type"));
4919 mips_print_register (file
, frame
, regnum
);
4920 fprintf_filtered (file
, "\n");
4923 /* Do all (or most) registers. */
4925 regnum
= gdbarch_num_regs (gdbarch
);
4926 while (regnum
< gdbarch_num_regs (gdbarch
)
4927 + gdbarch_num_pseudo_regs (gdbarch
))
4929 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4932 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4933 regnum
= print_fp_register_row (file
, frame
, regnum
);
4935 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4938 regnum
= print_gp_register_row (file
, frame
, regnum
);
4943 /* Is this a branch with a delay slot? */
4946 is_delayed (unsigned long insn
)
4949 for (i
= 0; i
< NUMOPCODES
; ++i
)
4950 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4951 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4953 return (i
< NUMOPCODES
4954 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4955 | INSN_COND_BRANCH_DELAY
4956 | INSN_COND_BRANCH_LIKELY
)));
4960 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4961 struct frame_info
*frame
)
4963 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4964 CORE_ADDR pc
= get_frame_pc (frame
);
4965 gdb_byte buf
[MIPS_INSN32_SIZE
];
4967 /* There is no branch delay slot on MIPS16. */
4968 if (mips_pc_is_mips16 (pc
))
4971 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4974 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4975 /* If error reading memory, guess that it is not a delayed
4978 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4981 /* To skip prologues, I use this predicate. Returns either PC itself
4982 if the code at PC does not look like a function prologue; otherwise
4983 returns an address that (if we're lucky) follows the prologue. If
4984 LENIENT, then we must skip everything which is involved in setting
4985 up the frame (it's OK to skip more, just so long as we don't skip
4986 anything which might clobber the registers which are being saved.
4987 We must skip more in the case where part of the prologue is in the
4988 delay slot of a non-prologue instruction). */
4991 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4994 CORE_ADDR func_addr
;
4996 /* See if we can determine the end of the prologue via the symbol table.
4997 If so, then return either PC, or the PC after the prologue, whichever
4999 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
5001 CORE_ADDR post_prologue_pc
5002 = skip_prologue_using_sal (gdbarch
, func_addr
);
5003 if (post_prologue_pc
!= 0)
5004 return max (pc
, post_prologue_pc
);
5007 /* Can't determine prologue from the symbol table, need to examine
5010 /* Find an upper limit on the function prologue using the debug
5011 information. If the debug information could not be used to provide
5012 that bound, then use an arbitrary large number as the upper bound. */
5013 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
5015 limit_pc
= pc
+ 100; /* Magic. */
5017 if (mips_pc_is_mips16 (pc
))
5018 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5020 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5023 /* Check whether the PC is in a function epilogue (32-bit version).
5024 This is a helper function for mips_in_function_epilogue_p. */
5026 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5028 CORE_ADDR func_addr
= 0, func_end
= 0;
5030 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5032 /* The MIPS epilogue is max. 12 bytes long. */
5033 CORE_ADDR addr
= func_end
- 12;
5035 if (addr
< func_addr
+ 4)
5036 addr
= func_addr
+ 4;
5040 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
5042 unsigned long high_word
;
5045 inst
= mips_fetch_instruction (gdbarch
, pc
);
5046 high_word
= (inst
>> 16) & 0xffff;
5048 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
5049 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
5050 && inst
!= 0x03e00008 /* jr $ra */
5051 && inst
!= 0x00000000) /* nop */
5061 /* Check whether the PC is in a function epilogue (16-bit version).
5062 This is a helper function for mips_in_function_epilogue_p. */
5064 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5066 CORE_ADDR func_addr
= 0, func_end
= 0;
5068 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5070 /* The MIPS epilogue is max. 12 bytes long. */
5071 CORE_ADDR addr
= func_end
- 12;
5073 if (addr
< func_addr
+ 4)
5074 addr
= func_addr
+ 4;
5078 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5080 unsigned short inst
;
5082 inst
= mips_fetch_instruction (gdbarch
, pc
);
5084 if ((inst
& 0xf800) == 0xf000) /* extend */
5087 if (inst
!= 0x6300 /* addiu $sp,offset */
5088 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5089 && inst
!= 0xe820 /* jr $ra */
5090 && inst
!= 0xe8a0 /* jrc $ra */
5091 && inst
!= 0x6500) /* nop */
5101 /* The epilogue is defined here as the area at the end of a function,
5102 after an instruction which destroys the function's stack frame. */
5104 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5106 if (mips_pc_is_mips16 (pc
))
5107 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5109 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5112 /* Root of all "set mips "/"show mips " commands. This will eventually be
5113 used for all MIPS-specific commands. */
5116 show_mips_command (char *args
, int from_tty
)
5118 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5122 set_mips_command (char *args
, int from_tty
)
5125 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5126 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5129 /* Commands to show/set the MIPS FPU type. */
5132 show_mipsfpu_command (char *args
, int from_tty
)
5136 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5139 ("The MIPS floating-point coprocessor is unknown "
5140 "because the current architecture is not MIPS.\n");
5144 switch (MIPS_FPU_TYPE (target_gdbarch
))
5146 case MIPS_FPU_SINGLE
:
5147 fpu
= "single-precision";
5149 case MIPS_FPU_DOUBLE
:
5150 fpu
= "double-precision";
5153 fpu
= "absent (none)";
5156 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5158 if (mips_fpu_type_auto
)
5159 printf_unfiltered ("The MIPS floating-point coprocessor "
5160 "is set automatically (currently %s)\n",
5164 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5169 set_mipsfpu_command (char *args
, int from_tty
)
5171 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5172 "\"single\",\"none\" or \"auto\".\n");
5173 show_mipsfpu_command (args
, from_tty
);
5177 set_mipsfpu_single_command (char *args
, int from_tty
)
5179 struct gdbarch_info info
;
5180 gdbarch_info_init (&info
);
5181 mips_fpu_type
= MIPS_FPU_SINGLE
;
5182 mips_fpu_type_auto
= 0;
5183 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5184 instead of relying on globals. Doing that would let generic code
5185 handle the search for this specific architecture. */
5186 if (!gdbarch_update_p (info
))
5187 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5191 set_mipsfpu_double_command (char *args
, int from_tty
)
5193 struct gdbarch_info info
;
5194 gdbarch_info_init (&info
);
5195 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5196 mips_fpu_type_auto
= 0;
5197 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5198 instead of relying on globals. Doing that would let generic code
5199 handle the search for this specific architecture. */
5200 if (!gdbarch_update_p (info
))
5201 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5205 set_mipsfpu_none_command (char *args
, int from_tty
)
5207 struct gdbarch_info info
;
5208 gdbarch_info_init (&info
);
5209 mips_fpu_type
= MIPS_FPU_NONE
;
5210 mips_fpu_type_auto
= 0;
5211 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5212 instead of relying on globals. Doing that would let generic code
5213 handle the search for this specific architecture. */
5214 if (!gdbarch_update_p (info
))
5215 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5219 set_mipsfpu_auto_command (char *args
, int from_tty
)
5221 mips_fpu_type_auto
= 1;
5224 /* Attempt to identify the particular processor model by reading the
5225 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5226 the relevant processor still exists (it dates back to '94) and
5227 secondly this is not the way to do this. The processor type should
5228 be set by forcing an architecture change. */
5231 deprecated_mips_set_processor_regs_hack (void)
5233 struct regcache
*regcache
= get_current_regcache ();
5234 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5238 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5239 if ((prid
& ~0xf) == 0x700)
5240 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5243 /* Just like reinit_frame_cache, but with the right arguments to be
5244 callable as an sfunc. */
5247 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5248 struct cmd_list_element
*c
)
5250 reinit_frame_cache ();
5254 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5256 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5257 disassembler needs to be able to locally determine the ISA, and
5258 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5260 if (mips_pc_is_mips16 (memaddr
))
5261 info
->mach
= bfd_mach_mips16
;
5263 /* Round down the instruction address to the appropriate boundary. */
5264 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5266 /* Set the disassembler options. */
5267 if (!info
->disassembler_options
)
5268 /* This string is not recognized explicitly by the disassembler,
5269 but it tells the disassembler to not try to guess the ABI from
5270 the bfd elf headers, such that, if the user overrides the ABI
5271 of a program linked as NewABI, the disassembly will follow the
5272 register naming conventions specified by the user. */
5273 info
->disassembler_options
= "gpr-names=32";
5275 /* Call the appropriate disassembler based on the target endian-ness. */
5276 if (info
->endian
== BFD_ENDIAN_BIG
)
5277 return print_insn_big_mips (memaddr
, info
);
5279 return print_insn_little_mips (memaddr
, info
);
5283 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5285 /* Set up the disassembler info, so that we get the right
5286 register names from libopcodes. */
5287 info
->disassembler_options
= "gpr-names=n32";
5288 info
->flavour
= bfd_target_elf_flavour
;
5290 return gdb_print_insn_mips (memaddr
, info
);
5294 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5296 /* Set up the disassembler info, so that we get the right
5297 register names from libopcodes. */
5298 info
->disassembler_options
= "gpr-names=64";
5299 info
->flavour
= bfd_target_elf_flavour
;
5301 return gdb_print_insn_mips (memaddr
, info
);
5304 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5305 program counter value to determine whether a 16- or 32-bit breakpoint
5306 should be used. It returns a pointer to a string of bytes that encode a
5307 breakpoint instruction, stores the length of the string to *lenptr, and
5308 adjusts pc (if necessary) to point to the actual memory location where
5309 the breakpoint should be inserted. */
5311 static const gdb_byte
*
5312 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5313 CORE_ADDR
*pcptr
, int *lenptr
)
5315 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5317 if (mips_pc_is_mips16 (*pcptr
))
5319 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5320 *pcptr
= unmake_mips16_addr (*pcptr
);
5321 *lenptr
= sizeof (mips16_big_breakpoint
);
5322 return mips16_big_breakpoint
;
5326 /* The IDT board uses an unusual breakpoint value, and
5327 sometimes gets confused when it sees the usual MIPS
5328 breakpoint instruction. */
5329 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5330 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5331 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5332 /* Likewise, IRIX appears to expect a different breakpoint,
5333 although this is not apparent until you try to use pthreads. */
5334 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5336 *lenptr
= sizeof (big_breakpoint
);
5338 if (strcmp (target_shortname
, "mips") == 0)
5339 return idt_big_breakpoint
;
5340 else if (strcmp (target_shortname
, "ddb") == 0
5341 || strcmp (target_shortname
, "pmon") == 0
5342 || strcmp (target_shortname
, "lsi") == 0)
5343 return pmon_big_breakpoint
;
5344 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5345 return irix_big_breakpoint
;
5347 return big_breakpoint
;
5352 if (mips_pc_is_mips16 (*pcptr
))
5354 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5355 *pcptr
= unmake_mips16_addr (*pcptr
);
5356 *lenptr
= sizeof (mips16_little_breakpoint
);
5357 return mips16_little_breakpoint
;
5361 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5362 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5363 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5365 *lenptr
= sizeof (little_breakpoint
);
5367 if (strcmp (target_shortname
, "mips") == 0)
5368 return idt_little_breakpoint
;
5369 else if (strcmp (target_shortname
, "ddb") == 0
5370 || strcmp (target_shortname
, "pmon") == 0
5371 || strcmp (target_shortname
, "lsi") == 0)
5372 return pmon_little_breakpoint
;
5374 return little_breakpoint
;
5379 /* Return non-zero if the ADDR instruction has a branch delay slot
5380 (i.e. it is a jump or branch instruction). This function is based
5381 on mips32_next_pc. */
5384 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
5386 gdb_byte buf
[MIPS_INSN32_SIZE
];
5393 status
= target_read_memory (addr
, buf
, MIPS_INSN32_SIZE
);
5397 inst
= mips_fetch_instruction (gdbarch
, addr
);
5398 op
= itype_op (inst
);
5399 if ((inst
& 0xe0000000) != 0)
5401 rs
= itype_rs (inst
);
5402 rt
= itype_rt (inst
);
5403 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
5404 || op
== 29 /* JALX: bits 011101 */
5407 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
5408 || (rs
== 9 && (rt
& 0x2) == 0)
5409 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
5410 || (rs
== 10 && (rt
& 0x2) == 0))));
5411 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
5414 switch (op
& 0x07) /* extract bits 28,27,26 */
5416 case 0: /* SPECIAL */
5417 op
= rtype_funct (inst
);
5418 return (op
== 8 /* JR */
5419 || op
== 9); /* JALR */
5420 break; /* end SPECIAL */
5421 case 1: /* REGIMM */
5422 rs
= itype_rs (inst
);
5423 rt
= itype_rt (inst
); /* branch condition */
5424 return ((rt
& 0xc) == 0
5425 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
5426 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
5427 || ((rt
& 0x1e) == 0x1c && rs
== 0));
5428 /* BPOSGE32, BPOSGE64: bits 1110x */
5429 break; /* end REGIMM */
5430 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
5436 /* Return non-zero if the ADDR instruction, which must be a 32-bit
5437 instruction if MUSTBE32 is set or can be any instruction otherwise,
5438 has a branch delay slot (i.e. it is a non-compact jump instruction). */
5441 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
5444 gdb_byte buf
[MIPS_INSN16_SIZE
];
5445 unsigned short inst
;
5448 status
= target_read_memory (addr
, buf
, MIPS_INSN16_SIZE
);
5452 inst
= mips_fetch_instruction (gdbarch
, addr
);
5454 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
5455 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
5458 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
5459 This assumes KSSEG exists. */
5462 mips_segment_boundary (CORE_ADDR bpaddr
)
5464 CORE_ADDR mask
= CORE_ADDR_MAX
;
5467 if (sizeof (CORE_ADDR
) == 8)
5468 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
5469 a compiler warning produced where CORE_ADDR is a 32-bit type even
5470 though in that case this is dead code). */
5471 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
5474 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
5475 segsize
= 29; /* 32-bit compatibility segment */
5477 segsize
= 62; /* xkseg */
5479 case 2: /* xkphys */
5482 default: /* xksseg (1), xkuseg/kuseg (0) */
5486 else if (bpaddr
& 0x80000000) /* kernel segment */
5489 segsize
= 31; /* user segment */
5491 return bpaddr
& mask
;
5494 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
5495 it backwards if necessary. Return the address of the new location. */
5498 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5500 CORE_ADDR prev_addr
, next_addr
;
5502 CORE_ADDR func_addr
;
5504 /* If a breakpoint is set on the instruction in a branch delay slot,
5505 GDB gets confused. When the breakpoint is hit, the PC isn't on
5506 the instruction in the branch delay slot, the PC will point to
5507 the branch instruction. Since the PC doesn't match any known
5508 breakpoints, GDB reports a trap exception.
5510 There are two possible fixes for this problem.
5512 1) When the breakpoint gets hit, see if the BD bit is set in the
5513 Cause register (which indicates the last exception occurred in a
5514 branch delay slot). If the BD bit is set, fix the PC to point to
5515 the instruction in the branch delay slot.
5517 2) When the user sets the breakpoint, don't allow him to set the
5518 breakpoint on the instruction in the branch delay slot. Instead
5519 move the breakpoint to the branch instruction (which will have
5522 The problem with the first solution is that if the user then
5523 single-steps the processor, the branch instruction will get
5524 skipped (since GDB thinks the PC is on the instruction in the
5527 So, we'll use the second solution. To do this we need to know if
5528 the instruction we're trying to set the breakpoint on is in the
5529 branch delay slot. */
5531 boundary
= mips_segment_boundary (bpaddr
);
5533 /* Make sure we don't scan back before the beginning of the current
5534 function, since we may fetch constant data or insns that look like
5535 a jump. Of course we might do that anyway if the compiler has
5536 moved constants inline. :-( */
5537 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
5538 && func_addr
> boundary
&& func_addr
<= bpaddr
)
5539 boundary
= func_addr
;
5541 if (!mips_pc_is_mips16 (bpaddr
))
5543 if (bpaddr
== boundary
)
5546 /* If the previous instruction has a branch delay slot, we have
5547 to move the breakpoint to the branch instruction. */
5548 prev_addr
= bpaddr
- 4;
5549 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
5554 struct minimal_symbol
*sym
;
5555 CORE_ADDR addr
, jmpaddr
;
5558 boundary
= unmake_mips16_addr (boundary
);
5560 /* The only MIPS16 instructions with delay slots are JAL, JALX,
5561 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
5562 so try for that first, then try the 2 byte JALR/JR.
5563 FIXME: We have to assume that bpaddr is not the second half
5564 of an extended instruction. */
5568 for (i
= 1; i
< 4; i
++)
5570 if (unmake_mips16_addr (addr
) == boundary
)
5573 if (i
== 1 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 0))
5574 /* Looks like a JR/JALR at [target-1], but it could be
5575 the second word of a previous JAL/JALX, so record it
5576 and check back one more. */
5579 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 1))
5582 /* Looks like a JAL/JALX at [target-2], but it could also
5583 be the second word of a previous JAL/JALX, record it,
5584 and check back one more. */
5587 /* Looks like a JAL/JALX at [target-3], so any previously
5588 recorded JAL/JALX or JR/JALR must be wrong, because:
5591 -2: JAL-ext (can't be JAL/JALX)
5592 -1: bdslot (can't be JR/JALR)
5595 Of course it could be another JAL-ext which looks
5596 like a JAL, but in that case we'd have broken out
5597 of this loop at [target-2]:
5601 -2: bdslot (can't be jmp)
5608 /* Not a jump instruction: if we're at [target-1] this
5609 could be the second word of a JAL/JALX, so continue;
5610 otherwise we're done. */
5623 /* If PC is in a mips16 call or return stub, return the address of the target
5624 PC, which is either the callee or the caller. There are several
5625 cases which must be handled:
5627 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5628 target PC is in $31 ($ra).
5629 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5630 and the target PC is in $2.
5631 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5632 before the jal instruction, this is effectively a call stub
5633 and the target PC is in $2. Otherwise this is effectively
5634 a return stub and the target PC is in $18.
5636 See the source code for the stubs in gcc/config/mips/mips16.S for
5640 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5642 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5644 CORE_ADDR start_addr
;
5646 /* Find the starting address and name of the function containing the PC. */
5647 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5650 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5651 target PC is in $31 ($ra). */
5652 if (strcmp (name
, "__mips16_ret_sf") == 0
5653 || strcmp (name
, "__mips16_ret_df") == 0)
5654 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5656 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5658 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5659 and the target PC is in $2. */
5660 if (name
[19] >= '0' && name
[19] <= '9')
5661 return get_frame_register_signed (frame
, 2);
5663 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5664 before the jal instruction, this is effectively a call stub
5665 and the target PC is in $2. Otherwise this is effectively
5666 a return stub and the target PC is in $18. */
5667 else if (name
[19] == 's' || name
[19] == 'd')
5669 if (pc
== start_addr
)
5671 /* Check if the target of the stub is a compiler-generated
5672 stub. Such a stub for a function bar might have a name
5673 like __fn_stub_bar, and might look like this:
5678 la $1,bar (becomes a lui/addiu pair)
5680 So scan down to the lui/addi and extract the target
5681 address from those two instructions. */
5683 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5686 /* See if the name of the target function is __fn_stub_*. */
5687 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5690 if (strncmp (name
, "__fn_stub_", 10) != 0
5691 && strcmp (name
, "etext") != 0
5692 && strcmp (name
, "_etext") != 0)
5695 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5696 The limit on the search is arbitrarily set to 20
5697 instructions. FIXME. */
5698 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5700 ULONGEST inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5701 CORE_ADDR addr
= inst
;
5703 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5704 pc
= (((addr
& 0xffff) ^ 0x8000) - 0x8000) << 16;
5706 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5707 return pc
+ ((addr
& 0xffff) ^ 0x8000) - 0x8000;
5711 /* Couldn't find the lui/addui pair, so return stub address. */
5715 /* This is the 'return' part of a call stub. The return
5716 address is in $r18. */
5717 return get_frame_register_signed (frame
, 18);
5720 return 0; /* not a stub */
5723 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5724 PC of the stub target. The stub just loads $t9 and jumps to it,
5725 so that $t9 has the correct value at function entry. */
5728 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5730 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5731 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5732 struct minimal_symbol
*msym
;
5734 gdb_byte stub_code
[16];
5735 int32_t stub_words
[4];
5737 /* The stub for foo is named ".pic.foo", and is either two
5738 instructions inserted before foo or a three instruction sequence
5739 which jumps to foo. */
5740 msym
= lookup_minimal_symbol_by_pc (pc
);
5742 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5743 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5744 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5747 /* A two-instruction header. */
5748 if (MSYMBOL_SIZE (msym
) == 8)
5751 /* A three-instruction (plus delay slot) trampoline. */
5752 if (MSYMBOL_SIZE (msym
) == 16)
5754 if (target_read_memory (pc
, stub_code
, 16) != 0)
5756 for (i
= 0; i
< 4; i
++)
5757 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5760 /* A stub contains these instructions:
5763 addiu t9, t9, %lo(target)
5766 This works even for N64, since stubs are only generated with
5768 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5769 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5770 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5771 && stub_words
[3] == 0x00000000)
5772 return ((((stub_words
[0] & 0x0000ffff) << 16)
5773 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
5776 /* Not a recognized stub. */
5781 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5783 CORE_ADDR target_pc
;
5785 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5789 target_pc
= find_solib_trampoline_target (frame
, pc
);
5793 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5800 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5801 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5804 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5807 if (num
>= 0 && num
< 32)
5809 else if (num
>= 38 && num
< 70)
5810 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5812 regnum
= mips_regnum (gdbarch
)->hi
;
5814 regnum
= mips_regnum (gdbarch
)->lo
;
5815 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
5816 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
5818 /* This will hopefully (eventually) provoke a warning. Should
5819 we be calling complaint() here? */
5820 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5821 return gdbarch_num_regs (gdbarch
) + regnum
;
5825 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5826 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5829 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5832 if (num
>= 0 && num
< 32)
5834 else if (num
>= 32 && num
< 64)
5835 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5837 regnum
= mips_regnum (gdbarch
)->hi
;
5839 regnum
= mips_regnum (gdbarch
)->lo
;
5840 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
5841 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
5843 /* This will hopefully (eventually) provoke a warning. Should we
5844 be calling complaint() here? */
5845 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5846 return gdbarch_num_regs (gdbarch
) + regnum
;
5850 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5852 /* Only makes sense to supply raw registers. */
5853 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5854 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5855 decide if it is valid. Should instead define a standard sim/gdb
5856 register numbering scheme. */
5857 if (gdbarch_register_name (gdbarch
,
5858 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5859 && gdbarch_register_name (gdbarch
,
5860 gdbarch_num_regs (gdbarch
)
5861 + regnum
)[0] != '\0')
5864 return LEGACY_SIM_REGNO_IGNORE
;
5868 /* Convert an integer into an address. Extracting the value signed
5869 guarantees a correctly sign extended address. */
5872 mips_integer_to_address (struct gdbarch
*gdbarch
,
5873 struct type
*type
, const gdb_byte
*buf
)
5875 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5876 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5879 /* Dummy virtual frame pointer method. This is no more or less accurate
5880 than most other architectures; we just need to be explicit about it,
5881 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5882 an assertion failure. */
5885 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5886 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5888 *reg
= MIPS_SP_REGNUM
;
5893 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5895 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5896 const char *name
= bfd_get_section_name (abfd
, sect
);
5898 if (*abip
!= MIPS_ABI_UNKNOWN
)
5901 if (strncmp (name
, ".mdebug.", 8) != 0)
5904 if (strcmp (name
, ".mdebug.abi32") == 0)
5905 *abip
= MIPS_ABI_O32
;
5906 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5907 *abip
= MIPS_ABI_N32
;
5908 else if (strcmp (name
, ".mdebug.abi64") == 0)
5909 *abip
= MIPS_ABI_N64
;
5910 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5911 *abip
= MIPS_ABI_O64
;
5912 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5913 *abip
= MIPS_ABI_EABI32
;
5914 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5915 *abip
= MIPS_ABI_EABI64
;
5917 warning (_("unsupported ABI %s."), name
+ 8);
5921 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5923 int *lbp
= (int *) obj
;
5924 const char *name
= bfd_get_section_name (abfd
, sect
);
5926 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5928 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5930 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5931 warning (_("unrecognized .gcc_compiled_longXX"));
5934 static enum mips_abi
5935 global_mips_abi (void)
5939 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5940 if (mips_abi_strings
[i
] == mips_abi_string
)
5941 return (enum mips_abi
) i
;
5943 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5947 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5949 /* If the size matches the set of 32-bit or 64-bit integer registers,
5950 assume that's what we've got. */
5951 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5952 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5954 /* If the size matches the full set of registers GDB traditionally
5955 knows about, including floating point, for either 32-bit or
5956 64-bit, assume that's what we've got. */
5957 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5958 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5960 /* Otherwise we don't have a useful guess. */
5963 static struct value
*
5964 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5966 const int *reg_p
= baton
;
5967 return value_of_register (*reg_p
, frame
);
5970 static struct gdbarch
*
5971 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5973 struct gdbarch
*gdbarch
;
5974 struct gdbarch_tdep
*tdep
;
5976 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5978 enum mips_fpu_type fpu_type
;
5979 struct tdesc_arch_data
*tdesc_data
= NULL
;
5980 int elf_fpu_type
= 0;
5981 const char **reg_names
;
5982 struct mips_regnum mips_regnum
, *regnum
;
5986 /* Fill in the OS dependent register numbers and names. */
5987 if (info
.osabi
== GDB_OSABI_IRIX
)
5989 mips_regnum
.fp0
= 32;
5990 mips_regnum
.pc
= 64;
5991 mips_regnum
.cause
= 65;
5992 mips_regnum
.badvaddr
= 66;
5993 mips_regnum
.hi
= 67;
5994 mips_regnum
.lo
= 68;
5995 mips_regnum
.fp_control_status
= 69;
5996 mips_regnum
.fp_implementation_revision
= 70;
5997 mips_regnum
.dspacc
= dspacc
= -1;
5998 mips_regnum
.dspctl
= dspctl
= -1;
6000 reg_names
= mips_irix_reg_names
;
6002 else if (info
.osabi
== GDB_OSABI_LINUX
)
6004 mips_regnum
.fp0
= 38;
6005 mips_regnum
.pc
= 37;
6006 mips_regnum
.cause
= 36;
6007 mips_regnum
.badvaddr
= 35;
6008 mips_regnum
.hi
= 34;
6009 mips_regnum
.lo
= 33;
6010 mips_regnum
.fp_control_status
= 70;
6011 mips_regnum
.fp_implementation_revision
= 71;
6012 mips_regnum
.dspacc
= -1;
6013 mips_regnum
.dspctl
= -1;
6017 reg_names
= mips_linux_reg_names
;
6021 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
6022 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
6023 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6024 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
6025 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
6026 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
6027 mips_regnum
.fp_control_status
= 70;
6028 mips_regnum
.fp_implementation_revision
= 71;
6029 mips_regnum
.dspacc
= dspacc
= -1;
6030 mips_regnum
.dspctl
= dspctl
= -1;
6031 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6032 if (info
.bfd_arch_info
!= NULL
6033 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6034 reg_names
= mips_tx39_reg_names
;
6036 reg_names
= mips_generic_reg_names
;
6039 /* Check any target description for validity. */
6040 if (tdesc_has_registers (info
.target_desc
))
6042 static const char *const mips_gprs
[] = {
6043 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6044 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6045 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6046 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6048 static const char *const mips_fprs
[] = {
6049 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6050 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6051 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6052 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
6055 const struct tdesc_feature
*feature
;
6058 feature
= tdesc_find_feature (info
.target_desc
,
6059 "org.gnu.gdb.mips.cpu");
6060 if (feature
== NULL
)
6063 tdesc_data
= tdesc_data_alloc ();
6066 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
6067 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6071 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6072 mips_regnum
.lo
, "lo");
6073 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6074 mips_regnum
.hi
, "hi");
6075 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6076 mips_regnum
.pc
, "pc");
6080 tdesc_data_cleanup (tdesc_data
);
6084 feature
= tdesc_find_feature (info
.target_desc
,
6085 "org.gnu.gdb.mips.cp0");
6086 if (feature
== NULL
)
6088 tdesc_data_cleanup (tdesc_data
);
6093 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6094 mips_regnum
.badvaddr
, "badvaddr");
6095 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6096 MIPS_PS_REGNUM
, "status");
6097 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6098 mips_regnum
.cause
, "cause");
6102 tdesc_data_cleanup (tdesc_data
);
6106 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
6107 backend is not prepared for that, though. */
6108 feature
= tdesc_find_feature (info
.target_desc
,
6109 "org.gnu.gdb.mips.fpu");
6110 if (feature
== NULL
)
6112 tdesc_data_cleanup (tdesc_data
);
6117 for (i
= 0; i
< 32; i
++)
6118 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6119 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
6121 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6122 mips_regnum
.fp_control_status
,
6125 &= tdesc_numbered_register (feature
, tdesc_data
,
6126 mips_regnum
.fp_implementation_revision
,
6131 tdesc_data_cleanup (tdesc_data
);
6137 feature
= tdesc_find_feature (info
.target_desc
,
6138 "org.gnu.gdb.mips.dsp");
6139 /* The DSP registers are optional; it's OK if they are absent. */
6140 if (feature
!= NULL
)
6144 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6145 dspacc
+ i
++, "hi1");
6146 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6147 dspacc
+ i
++, "lo1");
6148 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6149 dspacc
+ i
++, "hi2");
6150 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6151 dspacc
+ i
++, "lo2");
6152 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6153 dspacc
+ i
++, "hi3");
6154 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6155 dspacc
+ i
++, "lo3");
6157 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6162 tdesc_data_cleanup (tdesc_data
);
6166 mips_regnum
.dspacc
= dspacc
;
6167 mips_regnum
.dspctl
= dspctl
;
6171 /* It would be nice to detect an attempt to use a 64-bit ABI
6172 when only 32-bit registers are provided. */
6176 /* First of all, extract the elf_flags, if available. */
6177 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6178 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6179 else if (arches
!= NULL
)
6180 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6184 fprintf_unfiltered (gdb_stdlog
,
6185 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6187 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6188 switch ((elf_flags
& EF_MIPS_ABI
))
6190 case E_MIPS_ABI_O32
:
6191 found_abi
= MIPS_ABI_O32
;
6193 case E_MIPS_ABI_O64
:
6194 found_abi
= MIPS_ABI_O64
;
6196 case E_MIPS_ABI_EABI32
:
6197 found_abi
= MIPS_ABI_EABI32
;
6199 case E_MIPS_ABI_EABI64
:
6200 found_abi
= MIPS_ABI_EABI64
;
6203 if ((elf_flags
& EF_MIPS_ABI2
))
6204 found_abi
= MIPS_ABI_N32
;
6206 found_abi
= MIPS_ABI_UNKNOWN
;
6210 /* GCC creates a pseudo-section whose name describes the ABI. */
6211 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6212 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6214 /* If we have no useful BFD information, use the ABI from the last
6215 MIPS architecture (if there is one). */
6216 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6217 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6219 /* Try the architecture for any hint of the correct ABI. */
6220 if (found_abi
== MIPS_ABI_UNKNOWN
6221 && info
.bfd_arch_info
!= NULL
6222 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6224 switch (info
.bfd_arch_info
->mach
)
6226 case bfd_mach_mips3900
:
6227 found_abi
= MIPS_ABI_EABI32
;
6229 case bfd_mach_mips4100
:
6230 case bfd_mach_mips5000
:
6231 found_abi
= MIPS_ABI_EABI64
;
6233 case bfd_mach_mips8000
:
6234 case bfd_mach_mips10000
:
6235 /* On Irix, ELF64 executables use the N64 ABI. The
6236 pseudo-sections which describe the ABI aren't present
6237 on IRIX. (Even for executables created by gcc.) */
6238 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6239 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6240 found_abi
= MIPS_ABI_N64
;
6242 found_abi
= MIPS_ABI_N32
;
6247 /* Default 64-bit objects to N64 instead of O32. */
6248 if (found_abi
== MIPS_ABI_UNKNOWN
6249 && info
.abfd
!= NULL
6250 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6251 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6252 found_abi
= MIPS_ABI_N64
;
6255 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6258 /* What has the user specified from the command line? */
6259 wanted_abi
= global_mips_abi ();
6261 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6264 /* Now that we have found what the ABI for this binary would be,
6265 check whether the user is overriding it. */
6266 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6267 mips_abi
= wanted_abi
;
6268 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6269 mips_abi
= found_abi
;
6271 mips_abi
= MIPS_ABI_O32
;
6273 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6276 /* Also used when doing an architecture lookup. */
6278 fprintf_unfiltered (gdb_stdlog
,
6279 "mips_gdbarch_init: "
6280 "mips64_transfers_32bit_regs_p = %d\n",
6281 mips64_transfers_32bit_regs_p
);
6283 /* Determine the MIPS FPU type. */
6286 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6287 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6288 Tag_GNU_MIPS_ABI_FP
);
6289 #endif /* HAVE_ELF */
6291 if (!mips_fpu_type_auto
)
6292 fpu_type
= mips_fpu_type
;
6293 else if (elf_fpu_type
!= 0)
6295 switch (elf_fpu_type
)
6298 fpu_type
= MIPS_FPU_DOUBLE
;
6301 fpu_type
= MIPS_FPU_SINGLE
;
6305 /* Soft float or unknown. */
6306 fpu_type
= MIPS_FPU_NONE
;
6310 else if (info
.bfd_arch_info
!= NULL
6311 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6312 switch (info
.bfd_arch_info
->mach
)
6314 case bfd_mach_mips3900
:
6315 case bfd_mach_mips4100
:
6316 case bfd_mach_mips4111
:
6317 case bfd_mach_mips4120
:
6318 fpu_type
= MIPS_FPU_NONE
;
6320 case bfd_mach_mips4650
:
6321 fpu_type
= MIPS_FPU_SINGLE
;
6324 fpu_type
= MIPS_FPU_DOUBLE
;
6327 else if (arches
!= NULL
)
6328 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6330 fpu_type
= MIPS_FPU_DOUBLE
;
6332 fprintf_unfiltered (gdb_stdlog
,
6333 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6335 /* Check for blatant incompatibilities. */
6337 /* If we have only 32-bit registers, then we can't debug a 64-bit
6339 if (info
.target_desc
6340 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
6341 && mips_abi
!= MIPS_ABI_EABI32
6342 && mips_abi
!= MIPS_ABI_O32
)
6344 if (tdesc_data
!= NULL
)
6345 tdesc_data_cleanup (tdesc_data
);
6349 /* Try to find a pre-existing architecture. */
6350 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6352 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6354 /* MIPS needs to be pedantic about which ABI the object is
6356 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6358 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6360 /* Need to be pedantic about which register virtual size is
6362 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6363 != mips64_transfers_32bit_regs_p
)
6365 /* Be pedantic about which FPU is selected. */
6366 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6369 if (tdesc_data
!= NULL
)
6370 tdesc_data_cleanup (tdesc_data
);
6371 return arches
->gdbarch
;
6374 /* Need a new architecture. Fill in a target specific vector. */
6375 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6376 gdbarch
= gdbarch_alloc (&info
, tdep
);
6377 tdep
->elf_flags
= elf_flags
;
6378 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6379 tdep
->found_abi
= found_abi
;
6380 tdep
->mips_abi
= mips_abi
;
6381 tdep
->mips_fpu_type
= fpu_type
;
6382 tdep
->register_size_valid_p
= 0;
6383 tdep
->register_size
= 0;
6384 tdep
->gregset
= NULL
;
6385 tdep
->gregset64
= NULL
;
6386 tdep
->fpregset
= NULL
;
6387 tdep
->fpregset64
= NULL
;
6389 if (info
.target_desc
)
6391 /* Some useful properties can be inferred from the target. */
6392 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
6394 tdep
->register_size_valid_p
= 1;
6395 tdep
->register_size
= 4;
6397 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6399 tdep
->register_size_valid_p
= 1;
6400 tdep
->register_size
= 8;
6404 /* Initially set everything according to the default ABI/ISA. */
6405 set_gdbarch_short_bit (gdbarch
, 16);
6406 set_gdbarch_int_bit (gdbarch
, 32);
6407 set_gdbarch_float_bit (gdbarch
, 32);
6408 set_gdbarch_double_bit (gdbarch
, 64);
6409 set_gdbarch_long_double_bit (gdbarch
, 64);
6410 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6411 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6412 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6414 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6415 mips_ax_pseudo_register_collect
);
6416 set_gdbarch_ax_pseudo_register_push_stack
6417 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6419 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6420 mips_elf_make_msymbol_special
);
6422 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
6423 *regnum
= mips_regnum
;
6424 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6425 set_gdbarch_num_regs (gdbarch
, num_regs
);
6426 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6427 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6428 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6429 tdep
->mips_processor_reg_names
= reg_names
;
6430 tdep
->regnum
= regnum
;
6435 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6436 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6437 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6438 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6439 tdep
->default_mask_address_p
= 0;
6440 set_gdbarch_long_bit (gdbarch
, 32);
6441 set_gdbarch_ptr_bit (gdbarch
, 32);
6442 set_gdbarch_long_long_bit (gdbarch
, 64);
6445 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6446 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6447 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6448 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6449 tdep
->default_mask_address_p
= 0;
6450 set_gdbarch_long_bit (gdbarch
, 32);
6451 set_gdbarch_ptr_bit (gdbarch
, 32);
6452 set_gdbarch_long_long_bit (gdbarch
, 64);
6454 case MIPS_ABI_EABI32
:
6455 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6456 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6457 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6458 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6459 tdep
->default_mask_address_p
= 0;
6460 set_gdbarch_long_bit (gdbarch
, 32);
6461 set_gdbarch_ptr_bit (gdbarch
, 32);
6462 set_gdbarch_long_long_bit (gdbarch
, 64);
6464 case MIPS_ABI_EABI64
:
6465 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6466 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6467 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6468 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6469 tdep
->default_mask_address_p
= 0;
6470 set_gdbarch_long_bit (gdbarch
, 64);
6471 set_gdbarch_ptr_bit (gdbarch
, 64);
6472 set_gdbarch_long_long_bit (gdbarch
, 64);
6475 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6476 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6477 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6478 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6479 tdep
->default_mask_address_p
= 0;
6480 set_gdbarch_long_bit (gdbarch
, 32);
6481 set_gdbarch_ptr_bit (gdbarch
, 32);
6482 set_gdbarch_long_long_bit (gdbarch
, 64);
6483 set_gdbarch_long_double_bit (gdbarch
, 128);
6484 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6487 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6488 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6489 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6490 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6491 tdep
->default_mask_address_p
= 0;
6492 set_gdbarch_long_bit (gdbarch
, 64);
6493 set_gdbarch_ptr_bit (gdbarch
, 64);
6494 set_gdbarch_long_long_bit (gdbarch
, 64);
6495 set_gdbarch_long_double_bit (gdbarch
, 128);
6496 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6499 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6502 /* GCC creates a pseudo-section whose name specifies the size of
6503 longs, since -mlong32 or -mlong64 may be used independent of
6504 other options. How those options affect pointer sizes is ABI and
6505 architecture dependent, so use them to override the default sizes
6506 set by the ABI. This table shows the relationship between ABI,
6507 -mlongXX, and size of pointers:
6509 ABI -mlongXX ptr bits
6510 --- -------- --------
6524 Note that for o32 and eabi32, pointers are always 32 bits
6525 regardless of any -mlongXX option. For all others, pointers and
6526 longs are the same, as set by -mlongXX or set by defaults. */
6528 if (info
.abfd
!= NULL
)
6532 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6535 set_gdbarch_long_bit (gdbarch
, long_bit
);
6539 case MIPS_ABI_EABI32
:
6544 case MIPS_ABI_EABI64
:
6545 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6548 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6553 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6554 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6557 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6558 flag in object files because to do so would make it impossible to
6559 link with libraries compiled without "-gp32". This is
6560 unnecessarily restrictive.
6562 We could solve this problem by adding "-gp32" multilibs to gcc,
6563 but to set this flag before gcc is built with such multilibs will
6564 break too many systems.''
6566 But even more unhelpfully, the default linker output target for
6567 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6568 for 64-bit programs - you need to change the ABI to change this,
6569 and not all gcc targets support that currently. Therefore using
6570 this flag to detect 32-bit mode would do the wrong thing given
6571 the current gcc - it would make GDB treat these 64-bit programs
6572 as 32-bit programs by default. */
6574 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6575 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6577 /* Add/remove bits from an address. The MIPS needs be careful to
6578 ensure that all 32 bit addresses are sign extended to 64 bits. */
6579 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6581 /* Unwind the frame. */
6582 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6583 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6584 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6586 /* Map debug register numbers onto internal register numbers. */
6587 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6588 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6589 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6590 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6591 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6592 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6594 /* MIPS version of CALL_DUMMY. */
6596 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6597 replaced by a command, and all targets will default to on stack
6598 (regardless of the stack's execute status). */
6599 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6600 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6602 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6603 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6604 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6606 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6607 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6608 set_gdbarch_adjust_breakpoint_address (gdbarch
,
6609 mips_adjust_breakpoint_address
);
6611 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6613 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6615 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6616 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6617 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6619 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6621 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6623 if (mips_abi
== MIPS_ABI_N32
)
6624 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6625 else if (mips_abi
== MIPS_ABI_N64
)
6626 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6628 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6630 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6631 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6632 need to all be folded into the target vector. Since they are
6633 being used as guards for target_stopped_by_watchpoint, why not have
6634 target_stopped_by_watchpoint return the type of watchpoint that the code
6636 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6638 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6640 set_gdbarch_single_step_through_delay (gdbarch
,
6641 mips_single_step_through_delay
);
6643 /* Virtual tables. */
6644 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6646 mips_register_g_packet_guesses (gdbarch
);
6648 /* Hook in OS ABI-specific overrides, if they have been registered. */
6649 info
.tdep_info
= (void *) tdesc_data
;
6650 gdbarch_init_osabi (info
, gdbarch
);
6652 /* The hook may have adjusted num_regs, fetch the final value and
6653 set pc_regnum and sp_regnum now that it has been fixed. */
6654 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6655 replaced by gdbarch_read_pc? */
6656 num_regs
= gdbarch_num_regs (gdbarch
);
6657 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6658 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6660 /* Unwind the frame. */
6661 dwarf2_append_unwinders (gdbarch
);
6662 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6663 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6664 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6665 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6666 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6667 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6668 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6672 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6673 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6675 /* Override the normal target description methods to handle our
6676 dual real and pseudo registers. */
6677 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6678 set_gdbarch_register_reggroup_p (gdbarch
,
6679 mips_tdesc_register_reggroup_p
);
6681 num_regs
= gdbarch_num_regs (gdbarch
);
6682 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6683 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6684 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6687 /* Add ABI-specific aliases for the registers. */
6688 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6689 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6690 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6691 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6693 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6694 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6695 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6697 /* Add some other standard aliases. */
6698 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6699 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6700 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6702 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6703 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6704 value_of_mips_user_reg
,
6705 &mips_numeric_register_aliases
[i
].regnum
);
6711 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6713 struct gdbarch_info info
;
6715 /* Force the architecture to update, and (if it's a MIPS architecture)
6716 mips_gdbarch_init will take care of the rest. */
6717 gdbarch_info_init (&info
);
6718 gdbarch_update_p (info
);
6721 /* Print out which MIPS ABI is in use. */
6724 show_mips_abi (struct ui_file
*file
,
6726 struct cmd_list_element
*ignored_cmd
,
6727 const char *ignored_value
)
6729 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6732 "The MIPS ABI is unknown because the current architecture "
6736 enum mips_abi global_abi
= global_mips_abi ();
6737 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6738 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6740 if (global_abi
== MIPS_ABI_UNKNOWN
)
6743 "The MIPS ABI is set automatically (currently \"%s\").\n",
6745 else if (global_abi
== actual_abi
)
6748 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6752 /* Probably shouldn't happen... */
6753 fprintf_filtered (file
,
6754 "The (auto detected) MIPS ABI \"%s\" is in use "
6755 "even though the user setting was \"%s\".\n",
6756 actual_abi_str
, mips_abi_strings
[global_abi
]);
6762 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6764 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6768 int ef_mips_32bitmode
;
6769 /* Determine the ISA. */
6770 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6788 /* Determine the size of a pointer. */
6789 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6790 fprintf_unfiltered (file
,
6791 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6793 fprintf_unfiltered (file
,
6794 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6796 fprintf_unfiltered (file
,
6797 "mips_dump_tdep: ef_mips_arch = %d\n",
6799 fprintf_unfiltered (file
,
6800 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6801 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6802 fprintf_unfiltered (file
,
6804 "mips_mask_address_p() %d (default %d)\n",
6805 mips_mask_address_p (tdep
),
6806 tdep
->default_mask_address_p
);
6808 fprintf_unfiltered (file
,
6809 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6810 MIPS_DEFAULT_FPU_TYPE
,
6811 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6812 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6813 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6815 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6816 MIPS_EABI (gdbarch
));
6817 fprintf_unfiltered (file
,
6818 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6819 MIPS_FPU_TYPE (gdbarch
),
6820 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6821 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6822 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6826 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6829 _initialize_mips_tdep (void)
6831 static struct cmd_list_element
*mipsfpulist
= NULL
;
6832 struct cmd_list_element
*c
;
6834 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6835 if (MIPS_ABI_LAST
+ 1
6836 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6837 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6839 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6841 mips_pdr_data
= register_objfile_data ();
6843 /* Create feature sets with the appropriate properties. The values
6844 are not important. */
6845 mips_tdesc_gp32
= allocate_target_description ();
6846 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6848 mips_tdesc_gp64
= allocate_target_description ();
6849 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6851 /* Add root prefix command for all "set mips"/"show mips" commands. */
6852 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6853 _("Various MIPS specific commands."),
6854 &setmipscmdlist
, "set mips ", 0, &setlist
);
6856 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6857 _("Various MIPS specific commands."),
6858 &showmipscmdlist
, "show mips ", 0, &showlist
);
6860 /* Allow the user to override the ABI. */
6861 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6862 &mips_abi_string
, _("\
6863 Set the MIPS ABI used by this program."), _("\
6864 Show the MIPS ABI used by this program."), _("\
6865 This option can be set to one of:\n\
6866 auto - the default ABI associated with the current binary\n\
6875 &setmipscmdlist
, &showmipscmdlist
);
6877 /* Let the user turn off floating point and set the fence post for
6878 heuristic_proc_start. */
6880 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6881 _("Set use of MIPS floating-point coprocessor."),
6882 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6883 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6884 _("Select single-precision MIPS floating-point coprocessor."),
6886 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6887 _("Select double-precision MIPS floating-point coprocessor."),
6889 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6890 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6891 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6892 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6893 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6894 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6895 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6896 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6897 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6898 _("Select MIPS floating-point coprocessor automatically."),
6900 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6901 _("Show current use of MIPS floating-point coprocessor target."),
6904 /* We really would like to have both "0" and "unlimited" work, but
6905 command.c doesn't deal with that. So make it a var_zinteger
6906 because the user can always use "999999" or some such for unlimited. */
6907 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6908 &heuristic_fence_post
, _("\
6909 Set the distance searched for the start of a function."), _("\
6910 Show the distance searched for the start of a function."), _("\
6911 If you are debugging a stripped executable, GDB needs to search through the\n\
6912 program for the start of a function. This command sets the distance of the\n\
6913 search. The only need to set it is when debugging a stripped executable."),
6914 reinit_frame_cache_sfunc
,
6915 NULL
, /* FIXME: i18n: The distance searched for
6916 the start of a function is %s. */
6917 &setlist
, &showlist
);
6919 /* Allow the user to control whether the upper bits of 64-bit
6920 addresses should be zeroed. */
6921 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6922 &mask_address_var
, _("\
6923 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6924 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6925 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6926 allow GDB to determine the correct value."),
6927 NULL
, show_mask_address
,
6928 &setmipscmdlist
, &showmipscmdlist
);
6930 /* Allow the user to control the size of 32 bit registers within the
6931 raw remote packet. */
6932 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6933 &mips64_transfers_32bit_regs_p
, _("\
6934 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6936 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6938 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6939 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6940 64 bits for others. Use \"off\" to disable compatibility mode"),
6941 set_mips64_transfers_32bit_regs
,
6942 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6943 MIPS target that transfers 32-bit
6944 quantities is %s. */
6945 &setlist
, &showlist
);
6947 /* Debug this files internals. */
6948 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6950 Set mips debugging."), _("\
6951 Show mips debugging."), _("\
6952 When non-zero, mips specific debugging is enabled."),
6954 NULL
, /* FIXME: i18n: Mips debugging is
6956 &setdebuglist
, &showdebuglist
);