1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
73 static const char *mips_abi_string
;
75 static const char *mips_abi_strings
[] = {
85 struct frame_extra_info
87 mips_extra_func_info_t proc_desc
;
91 /* Various MIPS ISA options (related to stack analysis) can be
92 overridden dynamically. Establish an enum/array for managing
95 static const char size_auto
[] = "auto";
96 static const char size_32
[] = "32";
97 static const char size_64
[] = "64";
99 static const char *size_enums
[] = {
106 /* Some MIPS boards don't support floating point while others only
107 support single-precision floating-point operations. See also
108 FP_REGISTER_DOUBLE. */
112 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
113 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
114 MIPS_FPU_NONE
/* No floating point. */
117 #ifndef MIPS_DEFAULT_FPU_TYPE
118 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
120 static int mips_fpu_type_auto
= 1;
121 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
123 static int mips_debug
= 0;
125 /* MIPS specific per-architecture information */
128 /* from the elf header */
132 enum mips_abi mips_abi
;
133 enum mips_abi found_abi
;
134 enum mips_fpu_type mips_fpu_type
;
135 int mips_last_arg_regnum
;
136 int mips_last_fp_arg_regnum
;
137 int mips_default_saved_regsize
;
138 int mips_fp_register_double
;
139 int mips_regs_have_home_p
;
140 int mips_default_stack_argsize
;
141 int gdb_target_is_mips64
;
142 int default_mask_address_p
;
144 enum gdb_osabi osabi
;
147 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
148 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
150 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
152 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
154 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
156 /* Return the currently configured (or set) saved register size. */
158 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
160 static const char *mips_saved_regsize_string
= size_auto
;
162 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
165 mips_saved_regsize (void)
167 if (mips_saved_regsize_string
== size_auto
)
168 return MIPS_DEFAULT_SAVED_REGSIZE
;
169 else if (mips_saved_regsize_string
== size_64
)
171 else /* if (mips_saved_regsize_string == size_32) */
175 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
176 compatiblity mode. A return value of 1 means that we have
177 physical 64-bit registers, but should treat them as 32-bit registers. */
180 mips2_fp_compat (void)
182 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
184 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
188 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
189 in all the places we deal with FP registers. PR gdb/413. */
190 /* Otherwise check the FR bit in the status register - it controls
191 the FP compatiblity mode. If it is clear we are in compatibility
193 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
200 /* Indicate that the ABI makes use of double-precision registers
201 provided by the FPU (rather than combining pairs of registers to
202 form double-precision values). Do not use "TARGET_IS_MIPS64" to
203 determine if the ABI is using double-precision registers. See also
205 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
207 /* Does the caller allocate a ``home'' for each register used in the
208 function call? The N32 ABI and MIPS_EABI do not, the others do. */
210 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
212 /* The amount of space reserved on the stack for registers. This is
213 different to MIPS_SAVED_REGSIZE as it determines the alignment of
214 data allocated after the registers have run out. */
216 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
218 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
220 static const char *mips_stack_argsize_string
= size_auto
;
223 mips_stack_argsize (void)
225 if (mips_stack_argsize_string
== size_auto
)
226 return MIPS_DEFAULT_STACK_ARGSIZE
;
227 else if (mips_stack_argsize_string
== size_64
)
229 else /* if (mips_stack_argsize_string == size_32) */
233 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
235 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
237 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
239 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
241 static void mips_print_register (int, int);
243 static mips_extra_func_info_t
244 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
246 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
248 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
250 int mips_set_processor_type (char *);
252 static void mips_show_processor_type_command (char *, int);
254 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
256 static mips_extra_func_info_t
257 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
259 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
260 mips_extra_func_info_t proc_desc
);
262 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
263 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
265 static struct type
*mips_float_register_type (void);
266 static struct type
*mips_double_register_type (void);
268 /* This value is the model of MIPS in use. It is derived from the value
269 of the PrID register. */
271 char *mips_processor_type
;
273 char *tmp_mips_processor_type
;
275 /* The list of available "set mips " and "show mips " commands */
277 static struct cmd_list_element
*setmipscmdlist
= NULL
;
278 static struct cmd_list_element
*showmipscmdlist
= NULL
;
280 /* A set of original names, to be used when restoring back to generic
281 registers from a specific set. */
283 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
284 char **mips_processor_reg_names
= mips_generic_reg_names
;
287 mips_register_name (int i
)
289 return mips_processor_reg_names
[i
];
292 /* Names of IDT R3041 registers. */
294 char *mips_r3041_reg_names
[] = {
295 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
296 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
297 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
298 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
299 "sr", "lo", "hi", "bad", "cause","pc",
300 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
301 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
302 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
303 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
304 "fsr", "fir", "fp", "",
305 "", "", "bus", "ccfg", "", "", "", "",
306 "", "", "port", "cmp", "", "", "epc", "prid",
309 /* Names of IDT R3051 registers. */
311 char *mips_r3051_reg_names
[] = {
312 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
313 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
314 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
315 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
316 "sr", "lo", "hi", "bad", "cause","pc",
317 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
318 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
319 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
320 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
321 "fsr", "fir", "fp", "",
322 "inx", "rand", "elo", "", "ctxt", "", "", "",
323 "", "", "ehi", "", "", "", "epc", "prid",
326 /* Names of IDT R3081 registers. */
328 char *mips_r3081_reg_names
[] = {
329 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
330 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
331 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
332 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
333 "sr", "lo", "hi", "bad", "cause","pc",
334 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
335 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
336 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
337 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
338 "fsr", "fir", "fp", "",
339 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
340 "", "", "ehi", "", "", "", "epc", "prid",
343 /* Names of LSI 33k registers. */
345 char *mips_lsi33k_reg_names
[] = {
346 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
347 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
348 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
349 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
350 "epc", "hi", "lo", "sr", "cause","badvaddr",
351 "dcic", "bpc", "bda", "", "", "", "", "",
352 "", "", "", "", "", "", "", "",
353 "", "", "", "", "", "", "", "",
354 "", "", "", "", "", "", "", "",
356 "", "", "", "", "", "", "", "",
357 "", "", "", "", "", "", "", "",
363 } mips_processor_type_table
[] = {
364 { "generic", mips_generic_reg_names
},
365 { "r3041", mips_r3041_reg_names
},
366 { "r3051", mips_r3051_reg_names
},
367 { "r3071", mips_r3081_reg_names
},
368 { "r3081", mips_r3081_reg_names
},
369 { "lsi33k", mips_lsi33k_reg_names
},
377 /* Table to translate MIPS16 register field to actual register number. */
378 static int mips16_to_32_reg
[8] =
379 {16, 17, 2, 3, 4, 5, 6, 7};
381 /* Heuristic_proc_start may hunt through the text section for a long
382 time across a 2400 baud serial line. Allows the user to limit this
385 static unsigned int heuristic_fence_post
= 0;
387 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
388 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
389 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
390 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
391 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
392 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
393 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
394 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
395 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
396 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
397 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
398 this will corrupt pdr.iline. Fortunately we don't use it. */
399 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
400 #define _PROC_MAGIC_ 0x0F0F0F0F
401 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
402 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
404 struct linked_proc_info
406 struct mips_extra_func_info info
;
407 struct linked_proc_info
*next
;
409 *linked_proc_desc_table
= NULL
;
412 mips_print_extra_frame_info (struct frame_info
*fi
)
416 && fi
->extra_info
->proc_desc
417 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
418 printf_filtered (" frame pointer is at %s+%s\n",
419 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
420 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
423 /* Number of bytes of storage in the actual machine representation for
424 register N. NOTE: This indirectly defines the register size
425 transfered by the GDB protocol. */
427 static int mips64_transfers_32bit_regs_p
= 0;
430 mips_register_raw_size (int reg_nr
)
432 if (mips64_transfers_32bit_regs_p
)
433 return REGISTER_VIRTUAL_SIZE (reg_nr
);
434 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
435 && FP_REGISTER_DOUBLE
)
436 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
443 /* Convert between RAW and VIRTUAL registers. The RAW register size
444 defines the remote-gdb packet. */
447 mips_register_convertible (int reg_nr
)
449 if (mips64_transfers_32bit_regs_p
)
452 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
456 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
457 char *raw_buf
, char *virt_buf
)
459 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
461 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
462 TYPE_LENGTH (virtual_type
));
466 TYPE_LENGTH (virtual_type
));
470 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
471 char *virt_buf
, char *raw_buf
)
473 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
474 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
475 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
477 TYPE_LENGTH (virtual_type
));
481 TYPE_LENGTH (virtual_type
));
484 /* Should the upper word of 64-bit addresses be zeroed? */
485 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
488 mips_mask_address_p (void)
490 switch (mask_address_var
)
492 case AUTO_BOOLEAN_TRUE
:
494 case AUTO_BOOLEAN_FALSE
:
497 case AUTO_BOOLEAN_AUTO
:
498 return MIPS_DEFAULT_MASK_ADDRESS_P
;
500 internal_error (__FILE__
, __LINE__
,
501 "mips_mask_address_p: bad switch");
507 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
509 switch (mask_address_var
)
511 case AUTO_BOOLEAN_TRUE
:
512 printf_filtered ("The 32 bit mips address mask is enabled\n");
514 case AUTO_BOOLEAN_FALSE
:
515 printf_filtered ("The 32 bit mips address mask is disabled\n");
517 case AUTO_BOOLEAN_AUTO
:
518 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
519 mips_mask_address_p () ? "enabled" : "disabled");
522 internal_error (__FILE__
, __LINE__
,
523 "show_mask_address: bad switch");
528 /* Should call_function allocate stack space for a struct return? */
530 mips_use_struct_convention (int gcc_p
, struct type
*type
)
533 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
535 return 1; /* Structures are returned by ref in extra arg0 */
538 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
541 pc_is_mips16 (bfd_vma memaddr
)
543 struct minimal_symbol
*sym
;
545 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
546 if (IS_MIPS16_ADDR (memaddr
))
549 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
550 the high bit of the info field. Use this to decide if the function is
551 MIPS16 or normal MIPS. */
552 sym
= lookup_minimal_symbol_by_pc (memaddr
);
554 return MSYMBOL_IS_SPECIAL (sym
);
559 /* MIPS believes that the PC has a sign extended value. Perhaphs the
560 all registers should be sign extended for simplicity? */
563 mips_read_pc (ptid_t ptid
)
565 return read_signed_register_pid (PC_REGNUM
, ptid
);
568 /* This returns the PC of the first inst after the prologue. If we can't
569 find the prologue, then return 0. */
572 after_prologue (CORE_ADDR pc
,
573 mips_extra_func_info_t proc_desc
)
575 struct symtab_and_line sal
;
576 CORE_ADDR func_addr
, func_end
;
578 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
579 to read the stack pointer from the current machine state, because
580 the current machine state has nothing to do with the information
581 we need from the proc_desc; and the process may or may not exist
584 proc_desc
= find_proc_desc (pc
, NULL
, 0);
588 /* If function is frameless, then we need to do it the hard way. I
589 strongly suspect that frameless always means prologueless... */
590 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
591 && PROC_FRAME_OFFSET (proc_desc
) == 0)
595 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
596 return 0; /* Unknown */
598 sal
= find_pc_line (func_addr
, 0);
600 if (sal
.end
< func_end
)
603 /* The line after the prologue is after the end of the function. In this
604 case, tell the caller to find the prologue the hard way. */
609 /* Decode a MIPS32 instruction that saves a register in the stack, and
610 set the appropriate bit in the general register mask or float register mask
611 to indicate which register is saved. This is a helper function
612 for mips_find_saved_regs. */
615 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
616 unsigned long *float_mask
)
620 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
621 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
622 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
624 /* It might be possible to use the instruction to
625 find the offset, rather than the code below which
626 is based on things being in a certain order in the
627 frame, but figuring out what the instruction's offset
628 is relative to might be a little tricky. */
629 reg
= (inst
& 0x001f0000) >> 16;
630 *gen_mask
|= (1 << reg
);
632 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
633 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
634 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
637 reg
= ((inst
& 0x001f0000) >> 16);
638 *float_mask
|= (1 << reg
);
642 /* Decode a MIPS16 instruction that saves a register in the stack, and
643 set the appropriate bit in the general register or float register mask
644 to indicate which register is saved. This is a helper function
645 for mips_find_saved_regs. */
648 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
650 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
652 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
653 *gen_mask
|= (1 << reg
);
655 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
657 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
658 *gen_mask
|= (1 << reg
);
660 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
661 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
662 *gen_mask
|= (1 << RA_REGNUM
);
666 /* Fetch and return instruction from the specified location. If the PC
667 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
670 mips_fetch_instruction (CORE_ADDR addr
)
672 char buf
[MIPS_INSTLEN
];
676 if (pc_is_mips16 (addr
))
678 instlen
= MIPS16_INSTLEN
;
679 addr
= UNMAKE_MIPS16_ADDR (addr
);
682 instlen
= MIPS_INSTLEN
;
683 status
= read_memory_nobpt (addr
, buf
, instlen
);
685 memory_error (status
, addr
);
686 return extract_unsigned_integer (buf
, instlen
);
690 /* These the fields of 32 bit mips instructions */
691 #define mips32_op(x) (x >> 26)
692 #define itype_op(x) (x >> 26)
693 #define itype_rs(x) ((x >> 21) & 0x1f)
694 #define itype_rt(x) ((x >> 16) & 0x1f)
695 #define itype_immediate(x) (x & 0xffff)
697 #define jtype_op(x) (x >> 26)
698 #define jtype_target(x) (x & 0x03ffffff)
700 #define rtype_op(x) (x >> 26)
701 #define rtype_rs(x) ((x >> 21) & 0x1f)
702 #define rtype_rt(x) ((x >> 16) & 0x1f)
703 #define rtype_rd(x) ((x >> 11) & 0x1f)
704 #define rtype_shamt(x) ((x >> 6) & 0x1f)
705 #define rtype_funct(x) (x & 0x3f)
708 mips32_relative_offset (unsigned long inst
)
711 x
= itype_immediate (inst
);
712 if (x
& 0x8000) /* sign bit set */
714 x
|= 0xffff0000; /* sign extension */
720 /* Determine whate to set a single step breakpoint while considering
723 mips32_next_pc (CORE_ADDR pc
)
727 inst
= mips_fetch_instruction (pc
);
728 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
730 if (itype_op (inst
) >> 2 == 5)
731 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
733 op
= (itype_op (inst
) & 0x03);
748 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
749 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
751 int tf
= itype_rt (inst
) & 0x01;
752 int cnum
= itype_rt (inst
) >> 2;
753 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
754 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
756 if (((cond
>> cnum
) & 0x01) == tf
)
757 pc
+= mips32_relative_offset (inst
) + 4;
762 pc
+= 4; /* Not a branch, next instruction is easy */
765 { /* This gets way messy */
767 /* Further subdivide into SPECIAL, REGIMM and other */
768 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
770 case 0: /* SPECIAL */
771 op
= rtype_funct (inst
);
776 /* Set PC to that address */
777 pc
= read_signed_register (rtype_rs (inst
));
783 break; /* end SPECIAL */
786 op
= itype_rt (inst
); /* branch condition */
791 case 16: /* BLTZAL */
792 case 18: /* BLTZALL */
794 if (read_signed_register (itype_rs (inst
)) < 0)
795 pc
+= mips32_relative_offset (inst
) + 4;
797 pc
+= 8; /* after the delay slot */
801 case 17: /* BGEZAL */
802 case 19: /* BGEZALL */
803 greater_equal_branch
:
804 if (read_signed_register (itype_rs (inst
)) >= 0)
805 pc
+= mips32_relative_offset (inst
) + 4;
807 pc
+= 8; /* after the delay slot */
809 /* All of the other instructions in the REGIMM category */
814 break; /* end REGIMM */
819 reg
= jtype_target (inst
) << 2;
820 /* Upper four bits get never changed... */
821 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
824 /* FIXME case JALX : */
827 reg
= jtype_target (inst
) << 2;
828 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
829 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
831 break; /* The new PC will be alternate mode */
832 case 4: /* BEQ, BEQL */
834 if (read_signed_register (itype_rs (inst
)) ==
835 read_signed_register (itype_rt (inst
)))
836 pc
+= mips32_relative_offset (inst
) + 4;
840 case 5: /* BNE, BNEL */
842 if (read_signed_register (itype_rs (inst
)) !=
843 read_signed_register (itype_rt (inst
)))
844 pc
+= mips32_relative_offset (inst
) + 4;
848 case 6: /* BLEZ, BLEZL */
850 if (read_signed_register (itype_rs (inst
) <= 0))
851 pc
+= mips32_relative_offset (inst
) + 4;
857 greater_branch
: /* BGTZ, BGTZL */
858 if (read_signed_register (itype_rs (inst
) > 0))
859 pc
+= mips32_relative_offset (inst
) + 4;
866 } /* mips32_next_pc */
868 /* Decoding the next place to set a breakpoint is irregular for the
869 mips 16 variant, but fortunately, there fewer instructions. We have to cope
870 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
871 We dont want to set a single step instruction on the extend instruction
875 /* Lots of mips16 instruction formats */
876 /* Predicting jumps requires itype,ritype,i8type
877 and their extensions extItype,extritype,extI8type
879 enum mips16_inst_fmts
881 itype
, /* 0 immediate 5,10 */
882 ritype
, /* 1 5,3,8 */
883 rrtype
, /* 2 5,3,3,5 */
884 rritype
, /* 3 5,3,3,5 */
885 rrrtype
, /* 4 5,3,3,3,2 */
886 rriatype
, /* 5 5,3,3,1,4 */
887 shifttype
, /* 6 5,3,3,3,2 */
888 i8type
, /* 7 5,3,8 */
889 i8movtype
, /* 8 5,3,3,5 */
890 i8mov32rtype
, /* 9 5,3,5,3 */
891 i64type
, /* 10 5,3,8 */
892 ri64type
, /* 11 5,3,3,5 */
893 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
894 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
895 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
896 extRRItype
, /* 15 5,5,5,5,3,3,5 */
897 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
898 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
899 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
900 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
901 extRi64type
, /* 20 5,6,5,5,3,3,5 */
902 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
904 /* I am heaping all the fields of the formats into one structure and
905 then, only the fields which are involved in instruction extension */
909 unsigned int regx
; /* Function in i8 type */
914 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
915 for the bits which make up the immediatate extension. */
918 extended_offset (unsigned int extension
)
921 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
923 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
925 value
|= extension
& 0x01f; /* extract 4:0 */
929 /* Only call this function if you know that this is an extendable
930 instruction, It wont malfunction, but why make excess remote memory references?
931 If the immediate operands get sign extended or somthing, do it after
932 the extension is performed.
934 /* FIXME: Every one of these cases needs to worry about sign extension
935 when the offset is to be used in relative addressing */
939 fetch_mips_16 (CORE_ADDR pc
)
942 pc
&= 0xfffffffe; /* clear the low order bit */
943 target_read_memory (pc
, buf
, 2);
944 return extract_unsigned_integer (buf
, 2);
948 unpack_mips16 (CORE_ADDR pc
,
949 unsigned int extension
,
951 enum mips16_inst_fmts insn_format
,
952 struct upk_mips16
*upk
)
964 value
= extended_offset (extension
);
965 value
= value
<< 11; /* rom for the original value */
966 value
|= inst
& 0x7ff; /* eleven bits from instruction */
970 value
= inst
& 0x7ff;
971 /* FIXME : Consider sign extension */
980 { /* A register identifier and an offset */
981 /* Most of the fields are the same as I type but the
982 immediate value is of a different length */
986 value
= extended_offset (extension
);
987 value
= value
<< 8; /* from the original instruction */
988 value
|= inst
& 0xff; /* eleven bits from instruction */
989 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
990 if (value
& 0x4000) /* test the sign bit , bit 26 */
992 value
&= ~0x3fff; /* remove the sign bit */
998 value
= inst
& 0xff; /* 8 bits */
999 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1000 /* FIXME: Do sign extension , this format needs it */
1001 if (value
& 0x80) /* THIS CONFUSES ME */
1003 value
&= 0xef; /* remove the sign bit */
1013 unsigned long value
;
1014 unsigned int nexthalf
;
1015 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1016 value
= value
<< 16;
1017 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1025 internal_error (__FILE__
, __LINE__
,
1028 upk
->offset
= offset
;
1035 add_offset_16 (CORE_ADDR pc
, int offset
)
1037 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1042 extended_mips16_next_pc (CORE_ADDR pc
,
1043 unsigned int extension
,
1046 int op
= (insn
>> 11);
1049 case 2: /* Branch */
1052 struct upk_mips16 upk
;
1053 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1054 offset
= upk
.offset
;
1060 pc
+= (offset
<< 1) + 2;
1063 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1065 struct upk_mips16 upk
;
1066 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1067 pc
= add_offset_16 (pc
, upk
.offset
);
1068 if ((insn
>> 10) & 0x01) /* Exchange mode */
1069 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1076 struct upk_mips16 upk
;
1078 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1079 reg
= read_signed_register (upk
.regx
);
1081 pc
+= (upk
.offset
<< 1) + 2;
1088 struct upk_mips16 upk
;
1090 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1091 reg
= read_signed_register (upk
.regx
);
1093 pc
+= (upk
.offset
<< 1) + 2;
1098 case 12: /* I8 Formats btez btnez */
1100 struct upk_mips16 upk
;
1102 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1103 /* upk.regx contains the opcode */
1104 reg
= read_signed_register (24); /* Test register is 24 */
1105 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1106 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1107 /* pc = add_offset_16(pc,upk.offset) ; */
1108 pc
+= (upk
.offset
<< 1) + 2;
1113 case 29: /* RR Formats JR, JALR, JALR-RA */
1115 struct upk_mips16 upk
;
1116 /* upk.fmt = rrtype; */
1121 upk
.regx
= (insn
>> 8) & 0x07;
1122 upk
.regy
= (insn
>> 5) & 0x07;
1130 break; /* Function return instruction */
1136 break; /* BOGUS Guess */
1138 pc
= read_signed_register (reg
);
1145 /* This is an instruction extension. Fetch the real instruction
1146 (which follows the extension) and decode things based on
1150 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1163 mips16_next_pc (CORE_ADDR pc
)
1165 unsigned int insn
= fetch_mips_16 (pc
);
1166 return extended_mips16_next_pc (pc
, 0, insn
);
1169 /* The mips_next_pc function supports single_step when the remote
1170 target monitor or stub is not developed enough to do a single_step.
1171 It works by decoding the current instruction and predicting where a
1172 branch will go. This isnt hard because all the data is available.
1173 The MIPS32 and MIPS16 variants are quite different */
1175 mips_next_pc (CORE_ADDR pc
)
1178 return mips16_next_pc (pc
);
1180 return mips32_next_pc (pc
);
1183 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1187 mips_find_saved_regs (struct frame_info
*fci
)
1190 CORE_ADDR reg_position
;
1191 /* r0 bit means kernel trap */
1193 /* What registers have been saved? Bitmasks. */
1194 unsigned long gen_mask
, float_mask
;
1195 mips_extra_func_info_t proc_desc
;
1198 frame_saved_regs_zalloc (fci
);
1200 /* If it is the frame for sigtramp, the saved registers are located
1201 in a sigcontext structure somewhere on the stack.
1202 If the stack layout for sigtramp changes we might have to change these
1203 constants and the companion fixup_sigtramp in mdebugread.c */
1204 #ifndef SIGFRAME_BASE
1205 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1206 above the sigtramp frame. */
1207 #define SIGFRAME_BASE MIPS_REGSIZE
1208 /* FIXME! Are these correct?? */
1209 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1210 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1211 #define SIGFRAME_FPREGSAVE_OFF \
1212 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1214 #ifndef SIGFRAME_REG_SIZE
1215 /* FIXME! Is this correct?? */
1216 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1218 if (fci
->signal_handler_caller
)
1220 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1222 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1223 + ireg
* SIGFRAME_REG_SIZE
;
1224 fci
->saved_regs
[ireg
] = reg_position
;
1226 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1228 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1229 + ireg
* SIGFRAME_REG_SIZE
;
1230 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1232 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1236 proc_desc
= fci
->extra_info
->proc_desc
;
1237 if (proc_desc
== NULL
)
1238 /* I'm not sure how/whether this can happen. Normally when we can't
1239 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1240 and set the saved_regs right away. */
1243 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1244 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1245 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1247 if ( /* In any frame other than the innermost or a frame interrupted by
1248 a signal, we assume that all registers have been saved.
1249 This assumes that all register saves in a function happen before
1250 the first function call. */
1251 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1253 /* In a dummy frame we know exactly where things are saved. */
1254 && !PROC_DESC_IS_DUMMY (proc_desc
)
1256 /* Don't bother unless we are inside a function prologue. Outside the
1257 prologue, we know where everything is. */
1259 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1261 /* Not sure exactly what kernel_trap means, but if it means
1262 the kernel saves the registers without a prologue doing it,
1263 we better not examine the prologue to see whether registers
1264 have been saved yet. */
1267 /* We need to figure out whether the registers that the proc_desc
1268 claims are saved have been saved yet. */
1272 /* Bitmasks; set if we have found a save for the register. */
1273 unsigned long gen_save_found
= 0;
1274 unsigned long float_save_found
= 0;
1277 /* If the address is odd, assume this is MIPS16 code. */
1278 addr
= PROC_LOW_ADDR (proc_desc
);
1279 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1281 /* Scan through this function's instructions preceding the current
1282 PC, and look for those that save registers. */
1283 while (addr
< fci
->pc
)
1285 inst
= mips_fetch_instruction (addr
);
1286 if (pc_is_mips16 (addr
))
1287 mips16_decode_reg_save (inst
, &gen_save_found
);
1289 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1292 gen_mask
= gen_save_found
;
1293 float_mask
= float_save_found
;
1296 /* Fill in the offsets for the registers which gen_mask says
1298 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1299 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1300 if (gen_mask
& 0x80000000)
1302 fci
->saved_regs
[ireg
] = reg_position
;
1303 reg_position
-= MIPS_SAVED_REGSIZE
;
1306 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1307 of that normally used by gcc. Therefore, we have to fetch the first
1308 instruction of the function, and if it's an entry instruction that
1309 saves $s0 or $s1, correct their saved addresses. */
1310 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1312 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1313 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1316 int sreg_count
= (inst
>> 6) & 3;
1318 /* Check if the ra register was pushed on the stack. */
1319 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1321 reg_position
-= MIPS_SAVED_REGSIZE
;
1323 /* Check if the s0 and s1 registers were pushed on the stack. */
1324 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1326 fci
->saved_regs
[reg
] = reg_position
;
1327 reg_position
-= MIPS_SAVED_REGSIZE
;
1332 /* Fill in the offsets for the registers which float_mask says
1334 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1336 /* The freg_offset points to where the first *double* register
1337 is saved. So skip to the high-order word. */
1338 if (!GDB_TARGET_IS_MIPS64
)
1339 reg_position
+= MIPS_SAVED_REGSIZE
;
1341 /* Fill in the offsets for the float registers which float_mask says
1343 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1344 if (float_mask
& 0x80000000)
1346 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1347 reg_position
-= MIPS_SAVED_REGSIZE
;
1350 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1354 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1356 for (; fi
; fi
= fi
->next
)
1358 /* We have to get the saved sp from the sigcontext
1359 if it is a signal handler frame. */
1360 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1364 if (fi
->saved_regs
== NULL
)
1365 mips_find_saved_regs (fi
);
1366 if (fi
->saved_regs
[regno
])
1367 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1370 return read_signed_register (regno
);
1373 /* mips_addr_bits_remove - remove useless address bits */
1376 mips_addr_bits_remove (CORE_ADDR addr
)
1378 if (GDB_TARGET_IS_MIPS64
)
1380 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1382 /* This hack is a work-around for existing boards using
1383 PMON, the simulator, and any other 64-bit targets that
1384 doesn't have true 64-bit addressing. On these targets,
1385 the upper 32 bits of addresses are ignored by the
1386 hardware. Thus, the PC or SP are likely to have been
1387 sign extended to all 1s by instruction sequences that
1388 load 32-bit addresses. For example, a typical piece of
1389 code that loads an address is this:
1390 lui $r2, <upper 16 bits>
1391 ori $r2, <lower 16 bits>
1392 But the lui sign-extends the value such that the upper 32
1393 bits may be all 1s. The workaround is simply to mask off
1394 these bits. In the future, gcc may be changed to support
1395 true 64-bit addressing, and this masking will have to be
1397 addr
&= (CORE_ADDR
) 0xffffffff;
1400 else if (mips_mask_address_p ())
1402 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1403 masking off bits, instead, the actual target should be asking
1404 for the address to be converted to a valid pointer. */
1405 /* Even when GDB is configured for some 32-bit targets
1406 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1407 so CORE_ADDR is 64 bits. So we still have to mask off
1408 useless bits from addresses. */
1409 addr
&= (CORE_ADDR
) 0xffffffff;
1414 /* mips_software_single_step() is called just before we want to resume
1415 the inferior, if we want to single-step it but there is no hardware
1416 or kernel single-step support (MIPS on GNU/Linux for example). We find
1417 the target of the coming instruction and breakpoint it.
1419 single_step is also called just after the inferior stops. If we had
1420 set up a simulated single-step, we undo our damage. */
1423 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1425 static CORE_ADDR next_pc
;
1426 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1427 static binsn_quantum break_mem
;
1430 if (insert_breakpoints_p
)
1432 pc
= read_register (PC_REGNUM
);
1433 next_pc
= mips_next_pc (pc
);
1435 target_insert_breakpoint (next_pc
, break_mem
);
1438 target_remove_breakpoint (next_pc
, break_mem
);
1442 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1446 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1447 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1448 tmp
= mips_skip_stub (pc
);
1449 prev
->pc
= tmp
? tmp
: pc
;
1454 mips_frame_saved_pc (struct frame_info
*frame
)
1457 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1458 /* We have to get the saved pc from the sigcontext
1459 if it is a signal handler frame. */
1460 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1461 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1463 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1464 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1466 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1468 return ADDR_BITS_REMOVE (saved_pc
);
1471 static struct mips_extra_func_info temp_proc_desc
;
1472 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1474 /* Set a register's saved stack address in temp_saved_regs. If an address
1475 has already been set for this register, do nothing; this way we will
1476 only recognize the first save of a given register in a function prologue.
1477 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1480 set_reg_offset (int regno
, CORE_ADDR offset
)
1482 if (temp_saved_regs
[regno
] == 0)
1483 temp_saved_regs
[regno
] = offset
;
1487 /* Test whether the PC points to the return instruction at the
1488 end of a function. */
1491 mips_about_to_return (CORE_ADDR pc
)
1493 if (pc_is_mips16 (pc
))
1494 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1495 generates a "jr $ra"; other times it generates code to load
1496 the return address from the stack to an accessible register (such
1497 as $a3), then a "jr" using that register. This second case
1498 is almost impossible to distinguish from an indirect jump
1499 used for switch statements, so we don't even try. */
1500 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1502 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1506 /* This fencepost looks highly suspicious to me. Removing it also
1507 seems suspicious as it could affect remote debugging across serial
1511 heuristic_proc_start (CORE_ADDR pc
)
1518 pc
= ADDR_BITS_REMOVE (pc
);
1520 fence
= start_pc
- heuristic_fence_post
;
1524 if (heuristic_fence_post
== UINT_MAX
1525 || fence
< VM_MIN_ADDRESS
)
1526 fence
= VM_MIN_ADDRESS
;
1528 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1530 /* search back for previous return */
1531 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1532 if (start_pc
< fence
)
1534 /* It's not clear to me why we reach this point when
1535 stop_soon_quietly, but with this test, at least we
1536 don't print out warnings for every child forked (eg, on
1537 decstation). 22apr93 rich@cygnus.com. */
1538 if (!stop_soon_quietly
)
1540 static int blurb_printed
= 0;
1542 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1547 /* This actually happens frequently in embedded
1548 development, when you first connect to a board
1549 and your stack pointer and pc are nowhere in
1550 particular. This message needs to give people
1551 in that situation enough information to
1552 determine that it's no big deal. */
1553 printf_filtered ("\n\
1554 GDB is unable to find the start of the function at 0x%s\n\
1555 and thus can't determine the size of that function's stack frame.\n\
1556 This means that GDB may be unable to access that stack frame, or\n\
1557 the frames below it.\n\
1558 This problem is most likely caused by an invalid program counter or\n\
1560 However, if you think GDB should simply search farther back\n\
1561 from 0x%s for code which looks like the beginning of a\n\
1562 function, you can increase the range of the search using the `set\n\
1563 heuristic-fence-post' command.\n",
1564 paddr_nz (pc
), paddr_nz (pc
));
1571 else if (pc_is_mips16 (start_pc
))
1573 unsigned short inst
;
1575 /* On MIPS16, any one of the following is likely to be the
1576 start of a function:
1580 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1581 inst
= mips_fetch_instruction (start_pc
);
1582 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1583 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1584 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1585 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1587 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1588 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1593 else if (mips_about_to_return (start_pc
))
1595 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1602 /* Fetch the immediate value from a MIPS16 instruction.
1603 If the previous instruction was an EXTEND, use it to extend
1604 the upper bits of the immediate value. This is a helper function
1605 for mips16_heuristic_proc_desc. */
1608 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1609 unsigned short inst
, /* current instruction */
1610 int nbits
, /* number of bits in imm field */
1611 int scale
, /* scale factor to be applied to imm */
1612 int is_signed
) /* is the imm field signed? */
1616 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1618 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1619 if (offset
& 0x8000) /* check for negative extend */
1620 offset
= 0 - (0x10000 - (offset
& 0xffff));
1621 return offset
| (inst
& 0x1f);
1625 int max_imm
= 1 << nbits
;
1626 int mask
= max_imm
- 1;
1627 int sign_bit
= max_imm
>> 1;
1629 offset
= inst
& mask
;
1630 if (is_signed
&& (offset
& sign_bit
))
1631 offset
= 0 - (max_imm
- offset
);
1632 return offset
* scale
;
1637 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1638 stream from start_pc to limit_pc. */
1641 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1642 struct frame_info
*next_frame
, CORE_ADDR sp
)
1645 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1646 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1647 unsigned inst
= 0; /* current instruction */
1648 unsigned entry_inst
= 0; /* the entry instruction */
1651 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1652 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1654 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1656 /* Save the previous instruction. If it's an EXTEND, we'll extract
1657 the immediate offset extension from it in mips16_get_imm. */
1660 /* Fetch and decode the instruction. */
1661 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1662 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1663 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1665 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1666 if (offset
< 0) /* negative stack adjustment? */
1667 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1669 /* Exit loop if a positive stack adjustment is found, which
1670 usually means that the stack cleanup code in the function
1671 epilogue is reached. */
1674 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1676 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1677 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1678 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1679 set_reg_offset (reg
, sp
+ offset
);
1681 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1683 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1684 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1685 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1686 set_reg_offset (reg
, sp
+ offset
);
1688 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1690 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1691 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1692 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1694 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1696 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1697 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1698 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1700 else if (inst
== 0x673d) /* move $s1, $sp */
1703 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1705 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1707 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1708 frame_addr
= sp
+ offset
;
1709 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1710 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1712 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1714 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1715 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1716 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1717 set_reg_offset (reg
, frame_addr
+ offset
);
1719 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1721 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1722 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1723 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1724 set_reg_offset (reg
, frame_addr
+ offset
);
1726 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1727 entry_inst
= inst
; /* save for later processing */
1728 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1729 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1732 /* The entry instruction is typically the first instruction in a function,
1733 and it stores registers at offsets relative to the value of the old SP
1734 (before the prologue). But the value of the sp parameter to this
1735 function is the new SP (after the prologue has been executed). So we
1736 can't calculate those offsets until we've seen the entire prologue,
1737 and can calculate what the old SP must have been. */
1738 if (entry_inst
!= 0)
1740 int areg_count
= (entry_inst
>> 8) & 7;
1741 int sreg_count
= (entry_inst
>> 6) & 3;
1743 /* The entry instruction always subtracts 32 from the SP. */
1744 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1746 /* Now we can calculate what the SP must have been at the
1747 start of the function prologue. */
1748 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1750 /* Check if a0-a3 were saved in the caller's argument save area. */
1751 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1753 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1754 set_reg_offset (reg
, sp
+ offset
);
1755 offset
+= MIPS_SAVED_REGSIZE
;
1758 /* Check if the ra register was pushed on the stack. */
1760 if (entry_inst
& 0x20)
1762 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1763 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1764 offset
-= MIPS_SAVED_REGSIZE
;
1767 /* Check if the s0 and s1 registers were pushed on the stack. */
1768 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1770 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1771 set_reg_offset (reg
, sp
+ offset
);
1772 offset
-= MIPS_SAVED_REGSIZE
;
1778 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1779 struct frame_info
*next_frame
, CORE_ADDR sp
)
1782 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1784 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1785 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1786 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1787 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1789 unsigned long inst
, high_word
, low_word
;
1792 /* Fetch the instruction. */
1793 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1795 /* Save some code by pre-extracting some useful fields. */
1796 high_word
= (inst
>> 16) & 0xffff;
1797 low_word
= inst
& 0xffff;
1798 reg
= high_word
& 0x1f;
1800 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1801 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1802 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1804 if (low_word
& 0x8000) /* negative stack adjustment? */
1805 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1807 /* Exit loop if a positive stack adjustment is found, which
1808 usually means that the stack cleanup code in the function
1809 epilogue is reached. */
1812 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1814 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1815 set_reg_offset (reg
, sp
+ low_word
);
1817 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1819 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1820 but the register size used is only 32 bits. Make the address
1821 for the saved register point to the lower 32 bits. */
1822 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1823 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1825 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1827 /* Old gcc frame, r30 is virtual frame pointer. */
1828 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1829 frame_addr
= sp
+ low_word
;
1830 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1832 unsigned alloca_adjust
;
1833 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1834 frame_addr
= read_next_frame_reg (next_frame
, 30);
1835 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1836 if (alloca_adjust
> 0)
1838 /* FP > SP + frame_size. This may be because
1839 * of an alloca or somethings similar.
1840 * Fix sp to "pre-alloca" value, and try again.
1842 sp
+= alloca_adjust
;
1847 /* move $30,$sp. With different versions of gas this will be either
1848 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1849 Accept any one of these. */
1850 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1852 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1853 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1855 unsigned alloca_adjust
;
1856 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1857 frame_addr
= read_next_frame_reg (next_frame
, 30);
1858 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1859 if (alloca_adjust
> 0)
1861 /* FP > SP + frame_size. This may be because
1862 * of an alloca or somethings similar.
1863 * Fix sp to "pre-alloca" value, and try again.
1865 sp
+= alloca_adjust
;
1870 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1872 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1873 set_reg_offset (reg
, frame_addr
+ low_word
);
1878 static mips_extra_func_info_t
1879 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1880 struct frame_info
*next_frame
, int cur_frame
)
1885 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1891 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1892 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1893 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1894 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1895 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1897 if (start_pc
+ 200 < limit_pc
)
1898 limit_pc
= start_pc
+ 200;
1899 if (pc_is_mips16 (start_pc
))
1900 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1902 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1903 return &temp_proc_desc
;
1906 struct mips_objfile_private
1912 /* Global used to communicate between non_heuristic_proc_desc and
1913 compare_pdr_entries within qsort (). */
1914 static bfd
*the_bfd
;
1917 compare_pdr_entries (const void *a
, const void *b
)
1919 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
1920 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
1924 else if (lhs
== rhs
)
1930 static mips_extra_func_info_t
1931 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1933 CORE_ADDR startaddr
;
1934 mips_extra_func_info_t proc_desc
;
1935 struct block
*b
= block_for_pc (pc
);
1937 struct obj_section
*sec
;
1938 struct mips_objfile_private
*priv
;
1940 if (PC_IN_CALL_DUMMY (pc
, 0, 0))
1943 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1945 *addrptr
= startaddr
;
1949 sec
= find_pc_section (pc
);
1952 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
1954 /* Search the ".pdr" section generated by GAS. This includes most of
1955 the information normally found in ECOFF PDRs. */
1957 the_bfd
= sec
->objfile
->obfd
;
1959 && (the_bfd
->format
== bfd_object
1960 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
1961 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
1963 /* Right now GAS only outputs the address as a four-byte sequence.
1964 This means that we should not bother with this method on 64-bit
1965 targets (until that is fixed). */
1967 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
1968 sizeof (struct mips_objfile_private
));
1970 sec
->objfile
->obj_private
= priv
;
1972 else if (priv
== NULL
)
1976 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
1977 sizeof (struct mips_objfile_private
));
1979 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
1982 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
1983 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
1985 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
1986 priv
->contents
, 0, priv
->size
);
1988 /* In general, the .pdr section is sorted. However, in the
1989 presence of multiple code sections (and other corner cases)
1990 it can become unsorted. Sort it so that we can use a faster
1992 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
1997 sec
->objfile
->obj_private
= priv
;
2001 if (priv
->size
!= 0)
2007 high
= priv
->size
/ 32;
2013 mid
= (low
+ high
) / 2;
2015 ptr
= priv
->contents
+ mid
* 32;
2016 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2017 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2018 SECT_OFF_TEXT (sec
->objfile
));
2019 if (pdr_pc
== startaddr
)
2021 if (pdr_pc
> startaddr
)
2026 while (low
!= high
);
2030 struct symbol
*sym
= find_pc_function (pc
);
2032 /* Fill in what we need of the proc_desc. */
2033 proc_desc
= (mips_extra_func_info_t
)
2034 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2035 sizeof (struct mips_extra_func_info
));
2036 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2038 /* Only used for dummy frames. */
2039 PROC_HIGH_ADDR (proc_desc
) = 0;
2041 PROC_FRAME_OFFSET (proc_desc
)
2042 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2043 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2045 PROC_FRAME_ADJUST (proc_desc
) = 0;
2046 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2048 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2050 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2052 PROC_FREG_OFFSET (proc_desc
)
2053 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2054 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2056 proc_desc
->pdr
.isym
= (long) sym
;
2066 if (startaddr
> BLOCK_START (b
))
2068 /* This is the "pathological" case referred to in a comment in
2069 print_frame_info. It might be better to move this check into
2074 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
2076 /* If we never found a PDR for this function in symbol reading, then
2077 examine prologues to find the information. */
2080 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2081 if (PROC_FRAME_REG (proc_desc
) == -1)
2091 static mips_extra_func_info_t
2092 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2094 mips_extra_func_info_t proc_desc
;
2095 CORE_ADDR startaddr
;
2097 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2101 /* IF this is the topmost frame AND
2102 * (this proc does not have debugging information OR
2103 * the PC is in the procedure prologue)
2104 * THEN create a "heuristic" proc_desc (by analyzing
2105 * the actual code) to replace the "official" proc_desc.
2107 if (next_frame
== NULL
)
2109 struct symtab_and_line val
;
2110 struct symbol
*proc_symbol
=
2111 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2115 val
= find_pc_line (BLOCK_START
2116 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2118 val
.pc
= val
.end
? val
.end
: pc
;
2120 if (!proc_symbol
|| pc
< val
.pc
)
2122 mips_extra_func_info_t found_heuristic
=
2123 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2124 pc
, next_frame
, cur_frame
);
2125 if (found_heuristic
)
2126 proc_desc
= found_heuristic
;
2132 /* Is linked_proc_desc_table really necessary? It only seems to be used
2133 by procedure call dummys. However, the procedures being called ought
2134 to have their own proc_descs, and even if they don't,
2135 heuristic_proc_desc knows how to create them! */
2137 register struct linked_proc_info
*link
;
2139 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2140 if (PROC_LOW_ADDR (&link
->info
) <= pc
2141 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2145 startaddr
= heuristic_proc_start (pc
);
2148 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2154 get_frame_pointer (struct frame_info
*frame
,
2155 mips_extra_func_info_t proc_desc
)
2157 return ADDR_BITS_REMOVE (
2158 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
2159 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2162 mips_extra_func_info_t cached_proc_desc
;
2165 mips_frame_chain (struct frame_info
*frame
)
2167 mips_extra_func_info_t proc_desc
;
2169 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2171 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2174 /* Check if the PC is inside a call stub. If it is, fetch the
2175 PC of the caller of that stub. */
2176 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2179 /* Look up the procedure descriptor for this PC. */
2180 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2184 cached_proc_desc
= proc_desc
;
2186 /* If no frame pointer and frame size is zero, we must be at end
2187 of stack (or otherwise hosed). If we don't check frame size,
2188 we loop forever if we see a zero size frame. */
2189 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2190 && PROC_FRAME_OFFSET (proc_desc
) == 0
2191 /* The previous frame from a sigtramp frame might be frameless
2192 and have frame size zero. */
2193 && !frame
->signal_handler_caller
)
2196 return get_frame_pointer (frame
, proc_desc
);
2200 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2204 /* Use proc_desc calculated in frame_chain */
2205 mips_extra_func_info_t proc_desc
=
2206 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2208 fci
->extra_info
= (struct frame_extra_info
*)
2209 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2211 fci
->saved_regs
= NULL
;
2212 fci
->extra_info
->proc_desc
=
2213 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2216 /* Fixup frame-pointer - only needed for top frame */
2217 /* This may not be quite right, if proc has a real frame register.
2218 Get the value of the frame relative sp, procedure might have been
2219 interrupted by a signal at it's very start. */
2220 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2221 && !PROC_DESC_IS_DUMMY (proc_desc
))
2222 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2224 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2226 if (proc_desc
== &temp_proc_desc
)
2230 /* Do not set the saved registers for a sigtramp frame,
2231 mips_find_saved_registers will do that for us.
2232 We can't use fci->signal_handler_caller, it is not yet set. */
2233 find_pc_partial_function (fci
->pc
, &name
,
2234 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2235 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2237 frame_saved_regs_zalloc (fci
);
2238 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2239 fci
->saved_regs
[PC_REGNUM
]
2240 = fci
->saved_regs
[RA_REGNUM
];
2244 /* hack: if argument regs are saved, guess these contain args */
2245 /* assume we can't tell how many args for now */
2246 fci
->extra_info
->num_args
= -1;
2247 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2249 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2251 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2258 /* MIPS stack frames are almost impenetrable. When execution stops,
2259 we basically have to look at symbol information for the function
2260 that we stopped in, which tells us *which* register (if any) is
2261 the base of the frame pointer, and what offset from that register
2262 the frame itself is at.
2264 This presents a problem when trying to examine a stack in memory
2265 (that isn't executing at the moment), using the "frame" command. We
2266 don't have a PC, nor do we have any registers except SP.
2268 This routine takes two arguments, SP and PC, and tries to make the
2269 cached frames look as if these two arguments defined a frame on the
2270 cache. This allows the rest of info frame to extract the important
2271 arguments without difficulty. */
2274 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2277 error ("MIPS frame specifications require two arguments: sp and pc");
2279 return create_new_frame (argv
[0], argv
[1]);
2282 /* According to the current ABI, should the type be passed in a
2283 floating-point register (assuming that there is space)? When there
2284 is no FPU, FP are not even considered as possibile candidates for
2285 FP registers and, consequently this returns false - forces FP
2286 arguments into integer registers. */
2289 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2291 return ((typecode
== TYPE_CODE_FLT
2293 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2294 && TYPE_NFIELDS (arg_type
) == 1
2295 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2296 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2299 /* On o32, argument passing in GPRs depends on the alignment of the type being
2300 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2303 mips_type_needs_double_align (struct type
*type
)
2305 enum type_code typecode
= TYPE_CODE (type
);
2307 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2309 else if (typecode
== TYPE_CODE_STRUCT
)
2311 if (TYPE_NFIELDS (type
) < 1)
2313 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2315 else if (typecode
== TYPE_CODE_UNION
)
2319 n
= TYPE_NFIELDS (type
);
2320 for (i
= 0; i
< n
; i
++)
2321 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2329 mips_push_arguments (int nargs
,
2330 struct value
**args
,
2333 CORE_ADDR struct_addr
)
2339 int stack_offset
= 0;
2341 /* Macros to round N up or down to the next A boundary; A must be
2343 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2344 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2346 /* First ensure that the stack and structure return address (if any)
2347 are properly aligned. The stack has to be at least 64-bit aligned
2348 even on 32-bit machines, because doubles must be 64-bit aligned.
2349 On at least one MIPS variant, stack frames need to be 128-bit
2350 aligned, so we round to this widest known alignment. */
2351 sp
= ROUND_DOWN (sp
, 16);
2352 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2354 /* Now make space on the stack for the args. We allocate more
2355 than necessary for EABI, because the first few arguments are
2356 passed in registers, but that's OK. */
2357 for (argnum
= 0; argnum
< nargs
; argnum
++)
2358 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2359 sp
-= ROUND_UP (len
, 16);
2362 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2363 (long) sp
, ROUND_UP (len
, 16));
2365 /* Initialize the integer and float register pointers. */
2367 float_argreg
= FPA0_REGNUM
;
2369 /* the struct_return pointer occupies the first parameter-passing reg */
2373 fprintf_unfiltered (gdb_stdlog
,
2374 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2375 argreg
, (long) struct_addr
);
2376 write_register (argreg
++, struct_addr
);
2377 if (MIPS_REGS_HAVE_HOME_P
)
2378 stack_offset
+= MIPS_STACK_ARGSIZE
;
2381 /* Now load as many as possible of the first arguments into
2382 registers, and push the rest onto the stack. Loop thru args
2383 from first to last. */
2384 for (argnum
= 0; argnum
< nargs
; argnum
++)
2387 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2388 struct value
*arg
= args
[argnum
];
2389 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2390 int len
= TYPE_LENGTH (arg_type
);
2391 enum type_code typecode
= TYPE_CODE (arg_type
);
2394 fprintf_unfiltered (gdb_stdlog
,
2395 "mips_push_arguments: %d len=%d type=%d",
2396 argnum
+ 1, len
, (int) typecode
);
2398 /* The EABI passes structures that do not fit in a register by
2399 reference. In all other cases, pass the structure by value. */
2401 && len
> MIPS_SAVED_REGSIZE
2402 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2404 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2405 typecode
= TYPE_CODE_PTR
;
2406 len
= MIPS_SAVED_REGSIZE
;
2409 fprintf_unfiltered (gdb_stdlog
, " push");
2412 val
= (char *) VALUE_CONTENTS (arg
);
2414 /* 32-bit ABIs always start floating point arguments in an
2415 even-numbered floating point register. Round the FP register
2416 up before the check to see if there are any FP registers
2417 left. Non MIPS_EABI targets also pass the FP in the integer
2418 registers so also round up normal registers. */
2419 if (!FP_REGISTER_DOUBLE
2420 && fp_register_arg_p (typecode
, arg_type
))
2422 if ((float_argreg
& 1))
2426 /* Floating point arguments passed in registers have to be
2427 treated specially. On 32-bit architectures, doubles
2428 are passed in register pairs; the even register gets
2429 the low word, and the odd register gets the high word.
2430 On non-EABI processors, the first two floating point arguments are
2431 also copied to general registers, because MIPS16 functions
2432 don't use float registers for arguments. This duplication of
2433 arguments in general registers can't hurt non-MIPS16 functions
2434 because those registers are normally skipped. */
2435 /* MIPS_EABI squeezes a struct that contains a single floating
2436 point value into an FP register instead of pushing it onto the
2438 if (fp_register_arg_p (typecode
, arg_type
)
2439 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2441 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2443 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2444 unsigned long regval
;
2446 /* Write the low word of the double to the even register(s). */
2447 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2449 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2450 float_argreg
, phex (regval
, 4));
2451 write_register (float_argreg
++, regval
);
2455 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2456 argreg
, phex (regval
, 4));
2457 write_register (argreg
++, regval
);
2460 /* Write the high word of the double to the odd register(s). */
2461 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2463 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2464 float_argreg
, phex (regval
, 4));
2465 write_register (float_argreg
++, regval
);
2469 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2470 argreg
, phex (regval
, 4));
2471 write_register (argreg
++, regval
);
2477 /* This is a floating point value that fits entirely
2478 in a single register. */
2479 /* On 32 bit ABI's the float_argreg is further adjusted
2480 above to ensure that it is even register aligned. */
2481 LONGEST regval
= extract_unsigned_integer (val
, len
);
2483 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2484 float_argreg
, phex (regval
, len
));
2485 write_register (float_argreg
++, regval
);
2488 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2489 registers for each argument. The below is (my
2490 guess) to ensure that the corresponding integer
2491 register has reserved the same space. */
2493 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2494 argreg
, phex (regval
, len
));
2495 write_register (argreg
, regval
);
2496 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2499 /* Reserve space for the FP register. */
2500 if (MIPS_REGS_HAVE_HOME_P
)
2501 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2505 /* Copy the argument to general registers or the stack in
2506 register-sized pieces. Large arguments are split between
2507 registers and stack. */
2508 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2509 are treated specially: Irix cc passes them in registers
2510 where gcc sometimes puts them on the stack. For maximum
2511 compatibility, we will put them in both places. */
2512 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2513 (len
% MIPS_SAVED_REGSIZE
!= 0));
2514 /* Structures should be aligned to eight bytes (even arg registers)
2515 on MIPS_ABI_O32 if their first member has double precision. */
2516 if (gdbarch_tdep (current_gdbarch
)->mips_abi
== MIPS_ABI_O32
2517 && mips_type_needs_double_align (arg_type
))
2522 /* Note: Floating-point values that didn't fit into an FP
2523 register are only written to memory. */
2526 /* Rememer if the argument was written to the stack. */
2527 int stack_used_p
= 0;
2528 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2531 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2534 /* Write this portion of the argument to the stack. */
2535 if (argreg
> MIPS_LAST_ARG_REGNUM
2537 || fp_register_arg_p (typecode
, arg_type
))
2539 /* Should shorter than int integer values be
2540 promoted to int before being stored? */
2541 int longword_offset
= 0;
2544 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2546 if (MIPS_STACK_ARGSIZE
== 8 &&
2547 (typecode
== TYPE_CODE_INT
||
2548 typecode
== TYPE_CODE_PTR
||
2549 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2550 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2551 else if ((typecode
== TYPE_CODE_STRUCT
||
2552 typecode
== TYPE_CODE_UNION
) &&
2553 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2554 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2559 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2560 (long) stack_offset
);
2561 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2562 (long) longword_offset
);
2565 addr
= sp
+ stack_offset
+ longword_offset
;
2570 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2571 for (i
= 0; i
< partial_len
; i
++)
2573 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2576 write_memory (addr
, val
, partial_len
);
2579 /* Note!!! This is NOT an else clause. Odd sized
2580 structs may go thru BOTH paths. Floating point
2581 arguments will not. */
2582 /* Write this portion of the argument to a general
2583 purpose register. */
2584 if (argreg
<= MIPS_LAST_ARG_REGNUM
2585 && !fp_register_arg_p (typecode
, arg_type
))
2587 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2589 /* A non-floating-point argument being passed in a
2590 general register. If a struct or union, and if
2591 the remaining length is smaller than the register
2592 size, we have to adjust the register value on
2595 It does not seem to be necessary to do the
2596 same for integral types.
2598 Also don't do this adjustment on EABI and O64
2601 cagney/2001-07-23: gdb/179: Also, GCC, when
2602 outputting LE O32 with sizeof (struct) <
2603 MIPS_SAVED_REGSIZE, generates a left shift as
2604 part of storing the argument in a register a
2605 register (the left shift isn't generated when
2606 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2607 is quite possible that this is GCC contradicting
2608 the LE/O32 ABI, GDB has not been adjusted to
2609 accommodate this. Either someone needs to
2610 demonstrate that the LE/O32 ABI specifies such a
2611 left shift OR this new ABI gets identified as
2612 such and GDB gets tweaked accordingly. */
2615 && MIPS_SAVED_REGSIZE
< 8
2616 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2617 && partial_len
< MIPS_SAVED_REGSIZE
2618 && (typecode
== TYPE_CODE_STRUCT
||
2619 typecode
== TYPE_CODE_UNION
))
2620 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2624 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2626 phex (regval
, MIPS_SAVED_REGSIZE
));
2627 write_register (argreg
, regval
);
2630 /* If this is the old ABI, prevent subsequent floating
2631 point arguments from being passed in floating point
2634 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2640 /* Compute the the offset into the stack at which we
2641 will copy the next parameter.
2643 In older ABIs, the caller reserved space for
2644 registers that contained arguments. This was loosely
2645 refered to as their "home". Consequently, space is
2648 In the new EABI (and the NABI32), the stack_offset
2649 only needs to be adjusted when it has been used.. */
2651 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2652 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2656 fprintf_unfiltered (gdb_stdlog
, "\n");
2659 /* Return adjusted stack pointer. */
2664 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2666 /* Set the return address register to point to the entry
2667 point of the program, where a breakpoint lies in wait. */
2668 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2673 mips_push_register (CORE_ADDR
* sp
, int regno
)
2675 char buffer
[MAX_REGISTER_RAW_SIZE
];
2678 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2680 regsize
= MIPS_SAVED_REGSIZE
;
2681 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2682 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2687 regsize
= REGISTER_RAW_SIZE (regno
);
2691 read_register_gen (regno
, buffer
);
2692 write_memory (*sp
, buffer
+ offset
, regsize
);
2695 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2696 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2699 mips_push_dummy_frame (void)
2702 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2703 xmalloc (sizeof (struct linked_proc_info
));
2704 mips_extra_func_info_t proc_desc
= &link
->info
;
2705 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2706 CORE_ADDR old_sp
= sp
;
2707 link
->next
= linked_proc_desc_table
;
2708 linked_proc_desc_table
= link
;
2710 /* FIXME! are these correct ? */
2711 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2712 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2713 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2714 #define FLOAT_SINGLE_REG_SAVE_MASK \
2715 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2717 * The registers we must save are all those not preserved across
2718 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2719 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2720 * and FP Control/Status registers.
2723 * Dummy frame layout:
2726 * Saved MMHI, MMLO, FPC_CSR
2731 * Saved D18 (i.e. F19, F18)
2733 * Saved D0 (i.e. F1, F0)
2734 * Argument build area and stack arguments written via mips_push_arguments
2738 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2739 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2740 PROC_FRAME_OFFSET (proc_desc
) = 0;
2741 PROC_FRAME_ADJUST (proc_desc
) = 0;
2742 mips_push_register (&sp
, PC_REGNUM
);
2743 mips_push_register (&sp
, HI_REGNUM
);
2744 mips_push_register (&sp
, LO_REGNUM
);
2745 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2747 /* Save general CPU registers */
2748 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2749 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2750 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2751 for (ireg
= 32; --ireg
>= 0;)
2752 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2753 mips_push_register (&sp
, ireg
);
2755 /* Save floating point registers starting with high order word */
2756 PROC_FREG_MASK (proc_desc
) =
2757 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2758 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2759 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2761 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2762 for (ireg
= 32; --ireg
>= 0;)
2763 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2764 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2766 /* Update the frame pointer for the call dummy and the stack pointer.
2767 Set the procedure's starting and ending addresses to point to the
2768 call dummy address at the entry point. */
2769 write_register (PUSH_FP_REGNUM
, old_sp
);
2770 write_register (SP_REGNUM
, sp
);
2771 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2772 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2773 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2774 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2778 mips_pop_frame (void)
2780 register int regnum
;
2781 struct frame_info
*frame
= get_current_frame ();
2782 CORE_ADDR new_sp
= FRAME_FP (frame
);
2784 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2786 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2787 if (frame
->saved_regs
== NULL
)
2788 mips_find_saved_regs (frame
);
2789 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2791 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2792 && frame
->saved_regs
[regnum
])
2793 write_register (regnum
,
2794 read_memory_integer (frame
->saved_regs
[regnum
],
2795 MIPS_SAVED_REGSIZE
));
2797 write_register (SP_REGNUM
, new_sp
);
2798 flush_cached_frames ();
2800 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2802 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2804 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2806 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2808 if (&pi_ptr
->info
== proc_desc
)
2813 error ("Can't locate dummy extra frame info\n");
2815 if (prev_ptr
!= NULL
)
2816 prev_ptr
->next
= pi_ptr
->next
;
2818 linked_proc_desc_table
= pi_ptr
->next
;
2822 write_register (HI_REGNUM
,
2823 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2824 MIPS_SAVED_REGSIZE
));
2825 write_register (LO_REGNUM
,
2826 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2827 MIPS_SAVED_REGSIZE
));
2828 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2829 write_register (FCRCS_REGNUM
,
2830 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2831 MIPS_SAVED_REGSIZE
));
2835 /* Floating point register management.
2837 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2838 64bit operations, these early MIPS cpus treat fp register pairs
2839 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2840 registers and offer a compatibility mode that emulates the MIPS2 fp
2841 model. When operating in MIPS2 fp compat mode, later cpu's split
2842 double precision floats into two 32-bit chunks and store them in
2843 consecutive fp regs. To display 64-bit floats stored in this
2844 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2845 Throw in user-configurable endianness and you have a real mess.
2847 The way this works is:
2848 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2849 double-precision value will be split across two logical registers.
2850 The lower-numbered logical register will hold the low-order bits,
2851 regardless of the processor's endianness.
2852 - If we are on a 64-bit processor, and we are looking for a
2853 single-precision value, it will be in the low ordered bits
2854 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2855 save slot in memory.
2856 - If we are in 64-bit mode, everything is straightforward.
2858 Note that this code only deals with "live" registers at the top of the
2859 stack. We will attempt to deal with saved registers later, when
2860 the raw/cooked register interface is in place. (We need a general
2861 interface that can deal with dynamic saved register sizes -- fp
2862 regs could be 32 bits wide in one frame and 64 on the frame above
2865 static struct type
*
2866 mips_float_register_type (void)
2868 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2869 return builtin_type_ieee_single_big
;
2871 return builtin_type_ieee_single_little
;
2874 static struct type
*
2875 mips_double_register_type (void)
2877 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2878 return builtin_type_ieee_double_big
;
2880 return builtin_type_ieee_double_little
;
2883 /* Copy a 32-bit single-precision value from the current frame
2884 into rare_buffer. */
2887 mips_read_fp_register_single (int regno
, char *rare_buffer
)
2889 int raw_size
= REGISTER_RAW_SIZE (regno
);
2890 char *raw_buffer
= alloca (raw_size
);
2892 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
2893 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2896 /* We have a 64-bit value for this register. Find the low-order
2900 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2905 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
2909 memcpy (rare_buffer
, raw_buffer
, 4);
2913 /* Copy a 64-bit double-precision value from the current frame into
2914 rare_buffer. This may include getting half of it from the next
2918 mips_read_fp_register_double (int regno
, char *rare_buffer
)
2920 int raw_size
= REGISTER_RAW_SIZE (regno
);
2922 if (raw_size
== 8 && !mips2_fp_compat ())
2924 /* We have a 64-bit value for this register, and we should use
2926 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
2927 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2931 if ((regno
- FP0_REGNUM
) & 1)
2932 internal_error (__FILE__
, __LINE__
,
2933 "mips_read_fp_register_double: bad access to "
2934 "odd-numbered FP register");
2936 /* mips_read_fp_register_single will find the correct 32 bits from
2938 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2940 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
2941 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
2945 mips_read_fp_register_single (regno
, rare_buffer
);
2946 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
2952 mips_print_register (int regnum
, int all
)
2954 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2956 /* Get the data in raw format. */
2957 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
2959 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2963 /* If we have a actual 32-bit floating point register (or we are in
2964 32-bit compatibility mode), and the register is even-numbered,
2965 also print it as a double (spanning two registers). */
2966 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2967 && (REGISTER_RAW_SIZE (regnum
) == 4
2968 || mips2_fp_compat ())
2969 && !((regnum
- FP0_REGNUM
) & 1))
2971 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2973 mips_read_fp_register_double (regnum
, dbuffer
);
2975 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2976 val_print (mips_double_register_type (), dbuffer
, 0, 0,
2977 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2978 printf_filtered ("); ");
2980 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2982 /* The problem with printing numeric register names (r26, etc.) is that
2983 the user can't use them on input. Probably the best solution is to
2984 fix it so that either the numeric or the funky (a2, etc.) names
2985 are accepted on input. */
2986 if (regnum
< MIPS_NUMREGS
)
2987 printf_filtered ("(r%d): ", regnum
);
2989 printf_filtered (": ");
2991 /* If virtual format is floating, print it that way. */
2992 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2993 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
2995 /* We have a meaningful 64-bit value in this register. Show
2996 it as a 32-bit float and a 64-bit double. */
2997 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
2999 printf_filtered (" (float) ");
3000 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
3001 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3002 printf_filtered (", (double) ");
3003 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
3004 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3007 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
3008 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3009 /* Else print as integer in hex. */
3014 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3015 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3019 print_scalar_formatted (raw_buffer
+ offset
,
3020 REGISTER_VIRTUAL_TYPE (regnum
),
3021 'x', 0, gdb_stdout
);
3025 /* Replacement for generic do_registers_info.
3026 Print regs in pretty columns. */
3029 do_fp_register_row (int regnum
)
3030 { /* do values for FP (float) regs */
3032 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
3033 int inv1
, inv2
, inv3
;
3035 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
3037 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
3039 /* 4-byte registers: we can fit two registers per row. */
3040 /* Also print every pair of 4-byte regs as an 8-byte double. */
3041 mips_read_fp_register_single (regnum
, raw_buffer
);
3042 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3044 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
3045 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
3047 mips_read_fp_register_double (regnum
, raw_buffer
);
3048 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3050 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
3052 printf_filtered (": <invalid float>");
3054 printf_filtered ("%-17.9g", flt1
);
3056 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
3058 printf_filtered (": <invalid float>");
3060 printf_filtered ("%-17.9g", flt2
);
3062 printf_filtered (" dbl: ");
3064 printf_filtered ("<invalid double>");
3066 printf_filtered ("%-24.17g", doub
);
3067 printf_filtered ("\n");
3069 /* may want to do hex display here (future enhancement) */
3074 /* Eight byte registers: print each one as float AND as double. */
3075 mips_read_fp_register_single (regnum
, raw_buffer
);
3076 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
3078 mips_read_fp_register_double (regnum
, raw_buffer
);
3079 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3081 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
3083 printf_filtered ("<invalid float>");
3085 printf_filtered ("flt: %-17.9g", flt1
);
3087 printf_filtered (" dbl: ");
3089 printf_filtered ("<invalid double>");
3091 printf_filtered ("%-24.17g", doub
);
3093 printf_filtered ("\n");
3094 /* may want to do hex display here (future enhancement) */
3100 /* Print a row's worth of GP (int) registers, with name labels above */
3103 do_gp_register_row (int regnum
)
3105 /* do values for GP (int) regs */
3106 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3107 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
3109 int start_regnum
= regnum
;
3110 int numregs
= NUM_REGS
;
3113 /* For GP registers, we print a separate row of names above the vals */
3114 printf_filtered (" ");
3115 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3117 if (*REGISTER_NAME (regnum
) == '\0')
3118 continue; /* unused register */
3119 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3120 break; /* end the row: reached FP register */
3121 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
3122 REGISTER_NAME (regnum
));
3125 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
3126 start_regnum
); /* print the R0 to R31 names */
3128 regnum
= start_regnum
; /* go back to start of row */
3129 /* now print the values in hex, 4 or 8 to the row */
3130 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3132 if (*REGISTER_NAME (regnum
) == '\0')
3133 continue; /* unused register */
3134 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3135 break; /* end row: reached FP register */
3136 /* OK: get the data in raw format. */
3137 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3138 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3139 /* pad small registers */
3140 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
3141 printf_filtered (" ");
3142 /* Now print the register value in hex, endian order. */
3143 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3144 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3145 byte
< REGISTER_RAW_SIZE (regnum
);
3147 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3149 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
3152 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3153 printf_filtered (" ");
3156 if (col
> 0) /* ie. if we actually printed anything... */
3157 printf_filtered ("\n");
3162 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3165 mips_do_registers_info (int regnum
, int fpregs
)
3167 if (regnum
!= -1) /* do one specified register */
3169 if (*(REGISTER_NAME (regnum
)) == '\0')
3170 error ("Not a valid register for the current processor type");
3172 mips_print_register (regnum
, 0);
3173 printf_filtered ("\n");
3176 /* do all (or most) registers */
3179 while (regnum
< NUM_REGS
)
3181 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3182 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
3183 regnum
= do_fp_register_row (regnum
); /* FP regs */
3185 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
3187 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
3192 /* Return number of args passed to a frame. described by FIP.
3193 Can return -1, meaning no way to tell. */
3196 mips_frame_num_args (struct frame_info
*frame
)
3201 /* Is this a branch with a delay slot? */
3203 static int is_delayed (unsigned long);
3206 is_delayed (unsigned long insn
)
3209 for (i
= 0; i
< NUMOPCODES
; ++i
)
3210 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
3211 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
3213 return (i
< NUMOPCODES
3214 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
3215 | INSN_COND_BRANCH_DELAY
3216 | INSN_COND_BRANCH_LIKELY
)));
3220 mips_step_skips_delay (CORE_ADDR pc
)
3222 char buf
[MIPS_INSTLEN
];
3224 /* There is no branch delay slot on MIPS16. */
3225 if (pc_is_mips16 (pc
))
3228 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
3229 /* If error reading memory, guess that it is not a delayed branch. */
3231 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
3235 /* Skip the PC past function prologue instructions (32-bit version).
3236 This is a helper function for mips_skip_prologue. */
3239 mips32_skip_prologue (CORE_ADDR pc
)
3243 int seen_sp_adjust
= 0;
3244 int load_immediate_bytes
= 0;
3246 /* Skip the typical prologue instructions. These are the stack adjustment
3247 instruction and the instructions that save registers on the stack
3248 or in the gcc frame. */
3249 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
3251 unsigned long high_word
;
3253 inst
= mips_fetch_instruction (pc
);
3254 high_word
= (inst
>> 16) & 0xffff;
3256 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
3257 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
3259 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
3260 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
3262 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3263 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3264 && (inst
& 0x001F0000)) /* reg != $zero */
3267 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3269 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
3271 continue; /* reg != $zero */
3273 /* move $s8,$sp. With different versions of gas this will be either
3274 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3275 Accept any one of these. */
3276 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3279 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3281 else if (high_word
== 0x3c1c) /* lui $gp,n */
3283 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
3285 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3286 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
3288 /* The following instructions load $at or $t0 with an immediate
3289 value in preparation for a stack adjustment via
3290 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3291 a local variable, so we accept them only before a stack adjustment
3292 instruction was seen. */
3293 else if (!seen_sp_adjust
)
3295 if (high_word
== 0x3c01 || /* lui $at,n */
3296 high_word
== 0x3c08) /* lui $t0,n */
3298 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3301 else if (high_word
== 0x3421 || /* ori $at,$at,n */
3302 high_word
== 0x3508 || /* ori $t0,$t0,n */
3303 high_word
== 0x3401 || /* ori $at,$zero,n */
3304 high_word
== 0x3408) /* ori $t0,$zero,n */
3306 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3316 /* In a frameless function, we might have incorrectly
3317 skipped some load immediate instructions. Undo the skipping
3318 if the load immediate was not followed by a stack adjustment. */
3319 if (load_immediate_bytes
&& !seen_sp_adjust
)
3320 pc
-= load_immediate_bytes
;
3324 /* Skip the PC past function prologue instructions (16-bit version).
3325 This is a helper function for mips_skip_prologue. */
3328 mips16_skip_prologue (CORE_ADDR pc
)
3331 int extend_bytes
= 0;
3332 int prev_extend_bytes
;
3334 /* Table of instructions likely to be found in a function prologue. */
3337 unsigned short inst
;
3338 unsigned short mask
;
3345 , /* addiu $sp,offset */
3349 , /* daddiu $sp,offset */
3353 , /* sw reg,n($sp) */
3357 , /* sd reg,n($sp) */
3361 , /* sw $ra,n($sp) */
3365 , /* sd $ra,n($sp) */
3373 , /* sw $a0-$a3,n($s1) */
3377 , /* move reg,$a0-$a3 */
3381 , /* entry pseudo-op */
3385 , /* addiu $s1,$sp,n */
3388 } /* end of table marker */
3391 /* Skip the typical prologue instructions. These are the stack adjustment
3392 instruction and the instructions that save registers on the stack
3393 or in the gcc frame. */
3394 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3396 unsigned short inst
;
3399 inst
= mips_fetch_instruction (pc
);
3401 /* Normally we ignore an extend instruction. However, if it is
3402 not followed by a valid prologue instruction, we must adjust
3403 the pc back over the extend so that it won't be considered
3404 part of the prologue. */
3405 if ((inst
& 0xf800) == 0xf000) /* extend */
3407 extend_bytes
= MIPS16_INSTLEN
;
3410 prev_extend_bytes
= extend_bytes
;
3413 /* Check for other valid prologue instructions besides extend. */
3414 for (i
= 0; table
[i
].mask
!= 0; i
++)
3415 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3417 if (table
[i
].mask
!= 0) /* it was in table? */
3418 continue; /* ignore it */
3422 /* Return the current pc, adjusted backwards by 2 if
3423 the previous instruction was an extend. */
3424 return pc
- prev_extend_bytes
;
3430 /* To skip prologues, I use this predicate. Returns either PC itself
3431 if the code at PC does not look like a function prologue; otherwise
3432 returns an address that (if we're lucky) follows the prologue. If
3433 LENIENT, then we must skip everything which is involved in setting
3434 up the frame (it's OK to skip more, just so long as we don't skip
3435 anything which might clobber the registers which are being saved.
3436 We must skip more in the case where part of the prologue is in the
3437 delay slot of a non-prologue instruction). */
3440 mips_skip_prologue (CORE_ADDR pc
)
3442 /* See if we can determine the end of the prologue via the symbol table.
3443 If so, then return either PC, or the PC after the prologue, whichever
3446 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3448 if (post_prologue_pc
!= 0)
3449 return max (pc
, post_prologue_pc
);
3451 /* Can't determine prologue from the symbol table, need to examine
3454 if (pc_is_mips16 (pc
))
3455 return mips16_skip_prologue (pc
);
3457 return mips32_skip_prologue (pc
);
3460 /* Determine how a return value is stored within the MIPS register
3461 file, given the return type `valtype'. */
3463 struct return_value_word
3472 return_value_location (struct type
*valtype
,
3473 struct return_value_word
*hi
,
3474 struct return_value_word
*lo
)
3476 int len
= TYPE_LENGTH (valtype
);
3478 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3479 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3480 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3482 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3484 /* We need to break a 64bit float in two 32 bit halves and
3485 spread them across a floating-point register pair. */
3486 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3487 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3488 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3489 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3491 hi
->reg_offset
= lo
->reg_offset
;
3492 lo
->reg
= FP0_REGNUM
+ 0;
3493 hi
->reg
= FP0_REGNUM
+ 1;
3499 /* The floating point value fits in a single floating-point
3501 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3502 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3505 lo
->reg
= FP0_REGNUM
;
3516 /* Locate a result possibly spread across two registers. */
3518 lo
->reg
= regnum
+ 0;
3519 hi
->reg
= regnum
+ 1;
3520 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3521 && len
< MIPS_SAVED_REGSIZE
)
3523 /* "un-left-justify" the value in the low register */
3524 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3529 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3530 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3531 && len
< MIPS_SAVED_REGSIZE
* 2
3532 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3533 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3535 /* "un-left-justify" the value spread across two registers. */
3536 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3537 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3539 hi
->len
= len
- lo
->len
;
3543 /* Only perform a partial copy of the second register. */
3546 if (len
> MIPS_SAVED_REGSIZE
)
3548 lo
->len
= MIPS_SAVED_REGSIZE
;
3549 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3557 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3558 && REGISTER_RAW_SIZE (regnum
) == 8
3559 && MIPS_SAVED_REGSIZE
== 4)
3561 /* Account for the fact that only the least-signficant part
3562 of the register is being used */
3563 lo
->reg_offset
+= 4;
3564 hi
->reg_offset
+= 4;
3567 hi
->buf_offset
= lo
->len
;
3571 /* Given a return value in `regbuf' with a type `valtype', extract and
3572 copy its value into `valbuf'. */
3575 mips_extract_return_value (struct type
*valtype
,
3576 char regbuf
[REGISTER_BYTES
],
3579 struct return_value_word lo
;
3580 struct return_value_word hi
;
3581 return_value_location (valtype
, &hi
, &lo
);
3583 memcpy (valbuf
+ lo
.buf_offset
,
3584 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3588 memcpy (valbuf
+ hi
.buf_offset
,
3589 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3593 /* Given a return value in `valbuf' with a type `valtype', write it's
3594 value into the appropriate register. */
3597 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3599 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3600 struct return_value_word lo
;
3601 struct return_value_word hi
;
3602 return_value_location (valtype
, &hi
, &lo
);
3604 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3605 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3606 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3608 REGISTER_RAW_SIZE (lo
.reg
));
3612 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3613 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3614 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3616 REGISTER_RAW_SIZE (hi
.reg
));
3620 /* Exported procedure: Is PC in the signal trampoline code */
3623 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3625 if (sigtramp_address
== 0)
3627 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3630 /* Root of all "set mips "/"show mips " commands. This will eventually be
3631 used for all MIPS-specific commands. */
3634 show_mips_command (char *args
, int from_tty
)
3636 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3640 set_mips_command (char *args
, int from_tty
)
3642 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3643 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3646 /* Commands to show/set the MIPS FPU type. */
3649 show_mipsfpu_command (char *args
, int from_tty
)
3652 switch (MIPS_FPU_TYPE
)
3654 case MIPS_FPU_SINGLE
:
3655 fpu
= "single-precision";
3657 case MIPS_FPU_DOUBLE
:
3658 fpu
= "double-precision";
3661 fpu
= "absent (none)";
3664 internal_error (__FILE__
, __LINE__
, "bad switch");
3666 if (mips_fpu_type_auto
)
3667 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3670 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3676 set_mipsfpu_command (char *args
, int from_tty
)
3678 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3679 show_mipsfpu_command (args
, from_tty
);
3683 set_mipsfpu_single_command (char *args
, int from_tty
)
3685 mips_fpu_type
= MIPS_FPU_SINGLE
;
3686 mips_fpu_type_auto
= 0;
3687 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3691 set_mipsfpu_double_command (char *args
, int from_tty
)
3693 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3694 mips_fpu_type_auto
= 0;
3695 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3699 set_mipsfpu_none_command (char *args
, int from_tty
)
3701 mips_fpu_type
= MIPS_FPU_NONE
;
3702 mips_fpu_type_auto
= 0;
3703 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3707 set_mipsfpu_auto_command (char *args
, int from_tty
)
3709 mips_fpu_type_auto
= 1;
3712 /* Command to set the processor type. */
3715 mips_set_processor_type_command (char *args
, int from_tty
)
3719 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3721 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3722 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3723 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3725 /* Restore the value. */
3726 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3731 if (!mips_set_processor_type (tmp_mips_processor_type
))
3733 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3734 /* Restore its value. */
3735 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3740 mips_show_processor_type_command (char *args
, int from_tty
)
3744 /* Modify the actual processor type. */
3747 mips_set_processor_type (char *str
)
3754 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3756 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3758 mips_processor_type
= str
;
3759 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3761 /* FIXME tweak fpu flag too */
3768 /* Attempt to identify the particular processor model by reading the
3772 mips_read_processor_type (void)
3776 prid
= read_register (PRID_REGNUM
);
3778 if ((prid
& ~0xf) == 0x700)
3779 return savestring ("r3041", strlen ("r3041"));
3784 /* Just like reinit_frame_cache, but with the right arguments to be
3785 callable as an sfunc. */
3788 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3789 struct cmd_list_element
*c
)
3791 reinit_frame_cache ();
3795 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3797 mips_extra_func_info_t proc_desc
;
3799 /* Search for the function containing this address. Set the low bit
3800 of the address when searching, in case we were given an even address
3801 that is the start of a 16-bit function. If we didn't do this,
3802 the search would fail because the symbol table says the function
3803 starts at an odd address, i.e. 1 byte past the given address. */
3804 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3805 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3807 /* Make an attempt to determine if this is a 16-bit function. If
3808 the procedure descriptor exists and the address therein is odd,
3809 it's definitely a 16-bit function. Otherwise, we have to just
3810 guess that if the address passed in is odd, it's 16-bits. */
3812 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3813 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3815 info
->mach
= pc_is_mips16 (memaddr
) ?
3816 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3818 /* Round down the instruction address to the appropriate boundary. */
3819 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3821 /* Call the appropriate disassembler based on the target endian-ness. */
3822 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3823 return print_insn_big_mips (memaddr
, info
);
3825 return print_insn_little_mips (memaddr
, info
);
3828 /* Old-style breakpoint macros.
3829 The IDT board uses an unusual breakpoint value, and sometimes gets
3830 confused when it sees the usual MIPS breakpoint instruction. */
3832 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3833 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3834 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3835 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3836 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3837 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3838 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3839 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3841 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3842 counter value to determine whether a 16- or 32-bit breakpoint should be
3843 used. It returns a pointer to a string of bytes that encode a breakpoint
3844 instruction, stores the length of the string to *lenptr, and adjusts pc
3845 (if necessary) to point to the actual memory location where the
3846 breakpoint should be inserted. */
3848 const unsigned char *
3849 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3851 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3853 if (pc_is_mips16 (*pcptr
))
3855 static unsigned char mips16_big_breakpoint
[] =
3856 MIPS16_BIG_BREAKPOINT
;
3857 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3858 *lenptr
= sizeof (mips16_big_breakpoint
);
3859 return mips16_big_breakpoint
;
3863 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
3864 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3865 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3867 *lenptr
= sizeof (big_breakpoint
);
3869 if (strcmp (target_shortname
, "mips") == 0)
3870 return idt_big_breakpoint
;
3871 else if (strcmp (target_shortname
, "ddb") == 0
3872 || strcmp (target_shortname
, "pmon") == 0
3873 || strcmp (target_shortname
, "lsi") == 0)
3874 return pmon_big_breakpoint
;
3876 return big_breakpoint
;
3881 if (pc_is_mips16 (*pcptr
))
3883 static unsigned char mips16_little_breakpoint
[] =
3884 MIPS16_LITTLE_BREAKPOINT
;
3885 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3886 *lenptr
= sizeof (mips16_little_breakpoint
);
3887 return mips16_little_breakpoint
;
3891 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3892 static unsigned char pmon_little_breakpoint
[] =
3893 PMON_LITTLE_BREAKPOINT
;
3894 static unsigned char idt_little_breakpoint
[] =
3895 IDT_LITTLE_BREAKPOINT
;
3897 *lenptr
= sizeof (little_breakpoint
);
3899 if (strcmp (target_shortname
, "mips") == 0)
3900 return idt_little_breakpoint
;
3901 else if (strcmp (target_shortname
, "ddb") == 0
3902 || strcmp (target_shortname
, "pmon") == 0
3903 || strcmp (target_shortname
, "lsi") == 0)
3904 return pmon_little_breakpoint
;
3906 return little_breakpoint
;
3911 /* If PC is in a mips16 call or return stub, return the address of the target
3912 PC, which is either the callee or the caller. There are several
3913 cases which must be handled:
3915 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3916 target PC is in $31 ($ra).
3917 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3918 and the target PC is in $2.
3919 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3920 before the jal instruction, this is effectively a call stub
3921 and the the target PC is in $2. Otherwise this is effectively
3922 a return stub and the target PC is in $18.
3924 See the source code for the stubs in gcc/config/mips/mips16.S for
3927 This function implements the SKIP_TRAMPOLINE_CODE macro.
3931 mips_skip_stub (CORE_ADDR pc
)
3934 CORE_ADDR start_addr
;
3936 /* Find the starting address and name of the function containing the PC. */
3937 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3940 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3941 target PC is in $31 ($ra). */
3942 if (strcmp (name
, "__mips16_ret_sf") == 0
3943 || strcmp (name
, "__mips16_ret_df") == 0)
3944 return read_signed_register (RA_REGNUM
);
3946 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3948 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3949 and the target PC is in $2. */
3950 if (name
[19] >= '0' && name
[19] <= '9')
3951 return read_signed_register (2);
3953 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3954 before the jal instruction, this is effectively a call stub
3955 and the the target PC is in $2. Otherwise this is effectively
3956 a return stub and the target PC is in $18. */
3957 else if (name
[19] == 's' || name
[19] == 'd')
3959 if (pc
== start_addr
)
3961 /* Check if the target of the stub is a compiler-generated
3962 stub. Such a stub for a function bar might have a name
3963 like __fn_stub_bar, and might look like this:
3968 la $1,bar (becomes a lui/addiu pair)
3970 So scan down to the lui/addi and extract the target
3971 address from those two instructions. */
3973 CORE_ADDR target_pc
= read_signed_register (2);
3977 /* See if the name of the target function is __fn_stub_*. */
3978 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3980 if (strncmp (name
, "__fn_stub_", 10) != 0
3981 && strcmp (name
, "etext") != 0
3982 && strcmp (name
, "_etext") != 0)
3985 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3986 The limit on the search is arbitrarily set to 20
3987 instructions. FIXME. */
3988 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3990 inst
= mips_fetch_instruction (target_pc
);
3991 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3992 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3993 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3994 return pc
| (inst
& 0xffff); /* low word */
3997 /* Couldn't find the lui/addui pair, so return stub address. */
4001 /* This is the 'return' part of a call stub. The return
4002 address is in $r18. */
4003 return read_signed_register (18);
4006 return 0; /* not a stub */
4010 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
4011 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4014 mips_in_call_stub (CORE_ADDR pc
, char *name
)
4016 CORE_ADDR start_addr
;
4018 /* Find the starting address of the function containing the PC. If the
4019 caller didn't give us a name, look it up at the same time. */
4020 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
4023 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4025 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4026 if (name
[19] >= '0' && name
[19] <= '9')
4028 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4029 before the jal instruction, this is effectively a call stub. */
4030 else if (name
[19] == 's' || name
[19] == 'd')
4031 return pc
== start_addr
;
4034 return 0; /* not a stub */
4038 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
4039 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
4042 mips_in_return_stub (CORE_ADDR pc
, char *name
)
4044 CORE_ADDR start_addr
;
4046 /* Find the starting address of the function containing the PC. */
4047 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
4050 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4051 if (strcmp (name
, "__mips16_ret_sf") == 0
4052 || strcmp (name
, "__mips16_ret_df") == 0)
4055 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4056 i.e. after the jal instruction, this is effectively a return stub. */
4057 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
4058 && (name
[19] == 's' || name
[19] == 'd')
4059 && pc
!= start_addr
)
4062 return 0; /* not a stub */
4066 /* Return non-zero if the PC is in a library helper function that should
4067 be ignored. This implements the IGNORE_HELPER_CALL macro. */
4070 mips_ignore_helper (CORE_ADDR pc
)
4074 /* Find the starting address and name of the function containing the PC. */
4075 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
4078 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4079 that we want to ignore. */
4080 return (strcmp (name
, "__mips16_ret_sf") == 0
4081 || strcmp (name
, "__mips16_ret_df") == 0);
4085 /* Return a location where we can set a breakpoint that will be hit
4086 when an inferior function call returns. This is normally the
4087 program's entry point. Executables that don't have an entry
4088 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
4089 whose address is the location where the breakpoint should be placed. */
4092 mips_call_dummy_address (void)
4094 struct minimal_symbol
*sym
;
4096 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
4098 return SYMBOL_VALUE_ADDRESS (sym
);
4100 return entry_point_address ();
4104 /* If the current gcc for this target does not produce correct debugging
4105 information for float parameters, both prototyped and unprototyped, then
4106 define this macro. This forces gdb to always assume that floats are
4107 passed as doubles and then converted in the callee.
4109 For the mips chip, it appears that the debug info marks the parameters as
4110 floats regardless of whether the function is prototyped, but the actual
4111 values are passed as doubles for the non-prototyped case and floats for
4112 the prototyped case. Thus we choose to make the non-prototyped case work
4113 for C and break the prototyped case, since the non-prototyped case is
4114 probably much more common. (FIXME). */
4117 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
4119 return current_language
->la_language
== language_c
;
4122 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4123 the register stored on the stack (32) is different to its real raw
4124 size (64). The below ensures that registers are fetched from the
4125 stack using their ABI size and then stored into the RAW_BUFFER
4126 using their raw size.
4128 The alternative to adding this function would be to add an ABI
4129 macro - REGISTER_STACK_SIZE(). */
4132 mips_get_saved_register (char *raw_buffer
,
4135 struct frame_info
*frame
,
4137 enum lval_type
*lval
)
4141 if (!target_has_registers
)
4142 error ("No registers.");
4144 /* Normal systems don't optimize out things with register numbers. */
4145 if (optimized
!= NULL
)
4147 addr
= find_saved_register (frame
, regnum
);
4151 *lval
= lval_memory
;
4152 if (regnum
== SP_REGNUM
)
4154 if (raw_buffer
!= NULL
)
4156 /* Put it back in target format. */
4157 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
4164 if (raw_buffer
!= NULL
)
4168 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4170 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
4172 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
4173 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
4179 *lval
= lval_register
;
4180 addr
= REGISTER_BYTE (regnum
);
4181 if (raw_buffer
!= NULL
)
4182 read_register_gen (regnum
, raw_buffer
);
4188 /* Immediately after a function call, return the saved pc.
4189 Can't always go through the frames for this because on some machines
4190 the new frame is not set up until the new function executes
4191 some instructions. */
4194 mips_saved_pc_after_call (struct frame_info
*frame
)
4196 return read_signed_register (RA_REGNUM
);
4200 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4204 mips_stab_reg_to_regnum (int num
)
4209 return num
+ FP0_REGNUM
- 38;
4212 /* Convert a ecoff register number to a gdb REGNUM */
4215 mips_ecoff_reg_to_regnum (int num
)
4220 return num
+ FP0_REGNUM
- 32;
4223 /* Convert an integer into an address. By first converting the value
4224 into a pointer and then extracting it signed, the address is
4225 guarenteed to be correctly sign extended. */
4228 mips_integer_to_address (struct type
*type
, void *buf
)
4230 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4231 LONGEST val
= unpack_long (type
, buf
);
4232 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4233 return extract_signed_integer (tmp
,
4234 TYPE_LENGTH (builtin_type_void_data_ptr
));
4238 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4240 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4241 const char *name
= bfd_get_section_name (abfd
, sect
);
4243 if (*abip
!= MIPS_ABI_UNKNOWN
)
4246 if (strncmp (name
, ".mdebug.", 8) != 0)
4249 if (strcmp (name
, ".mdebug.abi32") == 0)
4250 *abip
= MIPS_ABI_O32
;
4251 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4252 *abip
= MIPS_ABI_N32
;
4253 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4254 *abip
= MIPS_ABI_O64
;
4255 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4256 *abip
= MIPS_ABI_EABI32
;
4257 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4258 *abip
= MIPS_ABI_EABI64
;
4260 warning ("unsupported ABI %s.", name
+ 8);
4263 static enum mips_abi
4264 global_mips_abi (void)
4268 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4269 if (mips_abi_strings
[i
] == mips_abi_string
)
4270 return (enum mips_abi
) i
;
4272 internal_error (__FILE__
, __LINE__
,
4273 "unknown ABI string");
4276 static struct gdbarch
*
4277 mips_gdbarch_init (struct gdbarch_info info
,
4278 struct gdbarch_list
*arches
)
4280 static LONGEST mips_call_dummy_words
[] =
4282 struct gdbarch
*gdbarch
;
4283 struct gdbarch_tdep
*tdep
;
4285 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4286 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
4288 /* Reset the disassembly info, in case it was set to something
4290 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
4291 tm_print_insn_info
.arch
= bfd_arch_unknown
;
4292 tm_print_insn_info
.mach
= 0;
4298 /* First of all, extract the elf_flags, if available. */
4299 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4300 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4302 /* Try to determine the OS ABI of the object we are loading. If
4303 we end up with `unknown', just leave it that way. */
4304 osabi
= gdbarch_lookup_osabi (info
.abfd
);
4307 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4308 switch ((elf_flags
& EF_MIPS_ABI
))
4310 case E_MIPS_ABI_O32
:
4311 mips_abi
= MIPS_ABI_O32
;
4313 case E_MIPS_ABI_O64
:
4314 mips_abi
= MIPS_ABI_O64
;
4316 case E_MIPS_ABI_EABI32
:
4317 mips_abi
= MIPS_ABI_EABI32
;
4319 case E_MIPS_ABI_EABI64
:
4320 mips_abi
= MIPS_ABI_EABI64
;
4323 if ((elf_flags
& EF_MIPS_ABI2
))
4324 mips_abi
= MIPS_ABI_N32
;
4326 mips_abi
= MIPS_ABI_UNKNOWN
;
4330 /* GCC creates a pseudo-section whose name describes the ABI. */
4331 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4332 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
4334 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
4335 Use the ABI from the last architecture if there is one. */
4336 if (info
.abfd
== NULL
&& arches
!= NULL
)
4337 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4339 /* Try the architecture for any hint of the corect ABI */
4340 if (mips_abi
== MIPS_ABI_UNKNOWN
4341 && info
.bfd_arch_info
!= NULL
4342 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4344 switch (info
.bfd_arch_info
->mach
)
4346 case bfd_mach_mips3900
:
4347 mips_abi
= MIPS_ABI_EABI32
;
4349 case bfd_mach_mips4100
:
4350 case bfd_mach_mips5000
:
4351 mips_abi
= MIPS_ABI_EABI64
;
4353 case bfd_mach_mips8000
:
4354 case bfd_mach_mips10000
:
4355 mips_abi
= MIPS_ABI_N32
;
4360 #ifdef MIPS_DEFAULT_ABI
4361 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4362 mips_abi
= MIPS_DEFAULT_ABI
;
4365 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4366 mips_abi
= MIPS_ABI_O32
;
4368 /* Now that we have found what the ABI for this binary would be,
4369 check whether the user is overriding it. */
4370 found_abi
= mips_abi
;
4371 wanted_abi
= global_mips_abi ();
4372 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4373 mips_abi
= wanted_abi
;
4377 fprintf_unfiltered (gdb_stdlog
,
4378 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4380 fprintf_unfiltered (gdb_stdlog
,
4381 "mips_gdbarch_init: mips_abi = %d\n",
4383 fprintf_unfiltered (gdb_stdlog
,
4384 "mips_gdbarch_init: found_mips_abi = %d\n",
4388 /* try to find a pre-existing architecture */
4389 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4391 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4393 /* MIPS needs to be pedantic about which ABI the object is
4395 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4397 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4399 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
4400 return arches
->gdbarch
;
4403 /* Need a new architecture. Fill in a target specific vector. */
4404 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4405 gdbarch
= gdbarch_alloc (&info
, tdep
);
4406 tdep
->elf_flags
= elf_flags
;
4407 tdep
->osabi
= osabi
;
4409 /* Initially set everything according to the default ABI/ISA. */
4410 set_gdbarch_short_bit (gdbarch
, 16);
4411 set_gdbarch_int_bit (gdbarch
, 32);
4412 set_gdbarch_float_bit (gdbarch
, 32);
4413 set_gdbarch_double_bit (gdbarch
, 64);
4414 set_gdbarch_long_double_bit (gdbarch
, 64);
4415 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
4416 tdep
->found_abi
= found_abi
;
4417 tdep
->mips_abi
= mips_abi
;
4422 tdep
->mips_default_saved_regsize
= 4;
4423 tdep
->mips_default_stack_argsize
= 4;
4424 tdep
->mips_fp_register_double
= 0;
4425 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4426 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4427 tdep
->mips_regs_have_home_p
= 1;
4428 tdep
->gdb_target_is_mips64
= 0;
4429 tdep
->default_mask_address_p
= 0;
4430 set_gdbarch_long_bit (gdbarch
, 32);
4431 set_gdbarch_ptr_bit (gdbarch
, 32);
4432 set_gdbarch_long_long_bit (gdbarch
, 64);
4435 tdep
->mips_default_saved_regsize
= 8;
4436 tdep
->mips_default_stack_argsize
= 8;
4437 tdep
->mips_fp_register_double
= 1;
4438 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4439 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4440 tdep
->mips_regs_have_home_p
= 1;
4441 tdep
->gdb_target_is_mips64
= 1;
4442 tdep
->default_mask_address_p
= 0;
4443 set_gdbarch_long_bit (gdbarch
, 32);
4444 set_gdbarch_ptr_bit (gdbarch
, 32);
4445 set_gdbarch_long_long_bit (gdbarch
, 64);
4447 case MIPS_ABI_EABI32
:
4448 tdep
->mips_default_saved_regsize
= 4;
4449 tdep
->mips_default_stack_argsize
= 4;
4450 tdep
->mips_fp_register_double
= 0;
4451 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4452 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4453 tdep
->mips_regs_have_home_p
= 0;
4454 tdep
->gdb_target_is_mips64
= 0;
4455 tdep
->default_mask_address_p
= 0;
4456 set_gdbarch_long_bit (gdbarch
, 32);
4457 set_gdbarch_ptr_bit (gdbarch
, 32);
4458 set_gdbarch_long_long_bit (gdbarch
, 64);
4460 case MIPS_ABI_EABI64
:
4461 tdep
->mips_default_saved_regsize
= 8;
4462 tdep
->mips_default_stack_argsize
= 8;
4463 tdep
->mips_fp_register_double
= 1;
4464 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4465 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4466 tdep
->mips_regs_have_home_p
= 0;
4467 tdep
->gdb_target_is_mips64
= 1;
4468 tdep
->default_mask_address_p
= 0;
4469 set_gdbarch_long_bit (gdbarch
, 64);
4470 set_gdbarch_ptr_bit (gdbarch
, 64);
4471 set_gdbarch_long_long_bit (gdbarch
, 64);
4474 tdep
->mips_default_saved_regsize
= 4;
4475 tdep
->mips_default_stack_argsize
= 8;
4476 tdep
->mips_fp_register_double
= 1;
4477 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4478 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4479 tdep
->mips_regs_have_home_p
= 0;
4480 tdep
->gdb_target_is_mips64
= 0;
4481 tdep
->default_mask_address_p
= 0;
4482 set_gdbarch_long_bit (gdbarch
, 32);
4483 set_gdbarch_ptr_bit (gdbarch
, 32);
4484 set_gdbarch_long_long_bit (gdbarch
, 64);
4486 /* Set up the disassembler info, so that we get the right
4487 register names from libopcodes. */
4488 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4489 tm_print_insn_info
.arch
= bfd_arch_mips
;
4490 if (info
.bfd_arch_info
!= NULL
4491 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4492 && info
.bfd_arch_info
->mach
)
4493 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4495 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4498 internal_error (__FILE__
, __LINE__
,
4499 "unknown ABI in switch");
4502 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4503 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4506 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4507 flag in object files because to do so would make it impossible to
4508 link with libraries compiled without "-gp32". This is
4509 unnecessarily restrictive.
4511 We could solve this problem by adding "-gp32" multilibs to gcc,
4512 but to set this flag before gcc is built with such multilibs will
4513 break too many systems.''
4515 But even more unhelpfully, the default linker output target for
4516 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4517 for 64-bit programs - you need to change the ABI to change this,
4518 and not all gcc targets support that currently. Therefore using
4519 this flag to detect 32-bit mode would do the wrong thing given
4520 the current gcc - it would make GDB treat these 64-bit programs
4521 as 32-bit programs by default. */
4523 /* enable/disable the MIPS FPU */
4524 if (!mips_fpu_type_auto
)
4525 tdep
->mips_fpu_type
= mips_fpu_type
;
4526 else if (info
.bfd_arch_info
!= NULL
4527 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4528 switch (info
.bfd_arch_info
->mach
)
4530 case bfd_mach_mips3900
:
4531 case bfd_mach_mips4100
:
4532 case bfd_mach_mips4111
:
4533 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4535 case bfd_mach_mips4650
:
4536 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4539 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4543 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4545 /* MIPS version of register names. NOTE: At present the MIPS
4546 register name management is part way between the old -
4547 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4548 Further work on it is required. */
4549 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4550 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4551 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4552 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4553 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4554 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4556 /* Add/remove bits from an address. The MIPS needs be careful to
4557 ensure that all 32 bit addresses are sign extended to 64 bits. */
4558 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4560 /* There's a mess in stack frame creation. See comments in
4561 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4562 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
4563 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
4565 /* Map debug register numbers onto internal register numbers. */
4566 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4567 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4569 /* Initialize a frame */
4570 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4572 /* MIPS version of CALL_DUMMY */
4574 set_gdbarch_call_dummy_p (gdbarch
, 1);
4575 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4576 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4577 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4578 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4579 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4580 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4581 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4582 set_gdbarch_call_dummy_length (gdbarch
, 0);
4583 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4584 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4585 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4586 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4587 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4588 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4589 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4591 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4592 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4594 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4595 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4596 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4598 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4599 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4601 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
4602 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
4603 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
4605 /* Hook in OS ABI-specific overrides, if they have been registered. */
4606 gdbarch_init_osabi (info
, gdbarch
, osabi
);
4612 mips_abi_update (char *ignore_args
, int from_tty
,
4613 struct cmd_list_element
*c
)
4615 struct gdbarch_info info
;
4617 /* Force the architecture to update, and (if it's a MIPS architecture)
4618 mips_gdbarch_init will take care of the rest. */
4619 gdbarch_info_init (&info
);
4620 gdbarch_update_p (info
);
4624 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4626 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4630 int ef_mips_32bitmode
;
4631 /* determine the ISA */
4632 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4650 /* determine the size of a pointer */
4651 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4652 fprintf_unfiltered (file
,
4653 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4655 fprintf_unfiltered (file
,
4656 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4658 fprintf_unfiltered (file
,
4659 "mips_dump_tdep: ef_mips_arch = %d\n",
4661 fprintf_unfiltered (file
,
4662 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4664 mips_abi_strings
[tdep
->mips_abi
]);
4665 fprintf_unfiltered (file
,
4666 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4667 mips_mask_address_p (),
4668 tdep
->default_mask_address_p
);
4670 fprintf_unfiltered (file
,
4671 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4672 FP_REGISTER_DOUBLE
);
4673 fprintf_unfiltered (file
,
4674 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4675 MIPS_DEFAULT_FPU_TYPE
,
4676 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4677 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4678 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4680 fprintf_unfiltered (file
,
4681 "mips_dump_tdep: MIPS_EABI = %d\n",
4683 fprintf_unfiltered (file
,
4684 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4685 MIPS_LAST_FP_ARG_REGNUM
,
4686 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4687 fprintf_unfiltered (file
,
4688 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4690 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4691 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4692 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4694 fprintf_unfiltered (file
,
4695 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4696 MIPS_DEFAULT_SAVED_REGSIZE
);
4697 fprintf_unfiltered (file
,
4698 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4699 FP_REGISTER_DOUBLE
);
4700 fprintf_unfiltered (file
,
4701 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4702 MIPS_REGS_HAVE_HOME_P
);
4703 fprintf_unfiltered (file
,
4704 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4705 MIPS_DEFAULT_STACK_ARGSIZE
);
4706 fprintf_unfiltered (file
,
4707 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4708 MIPS_STACK_ARGSIZE
);
4709 fprintf_unfiltered (file
,
4710 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4712 fprintf_unfiltered (file
,
4713 "mips_dump_tdep: A0_REGNUM = %d\n",
4715 fprintf_unfiltered (file
,
4716 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4717 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4718 fprintf_unfiltered (file
,
4719 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4720 XSTRING (ATTACH_DETACH
));
4721 fprintf_unfiltered (file
,
4722 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4724 fprintf_unfiltered (file
,
4725 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4726 fprintf_unfiltered (file
,
4727 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4729 fprintf_unfiltered (file
,
4730 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4732 fprintf_unfiltered (file
,
4733 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4735 fprintf_unfiltered (file
,
4736 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4737 XSTRING (DO_REGISTERS_INFO
));
4738 fprintf_unfiltered (file
,
4739 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4740 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4741 fprintf_unfiltered (file
,
4742 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4743 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4744 fprintf_unfiltered (file
,
4745 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4746 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4747 fprintf_unfiltered (file
,
4748 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4750 fprintf_unfiltered (file
,
4751 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4753 fprintf_unfiltered (file
,
4754 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4755 FIRST_EMBED_REGNUM
);
4756 fprintf_unfiltered (file
,
4757 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4759 fprintf_unfiltered (file
,
4760 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4761 GDB_TARGET_IS_MIPS64
);
4762 fprintf_unfiltered (file
,
4763 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4764 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4765 fprintf_unfiltered (file
,
4766 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4767 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4768 fprintf_unfiltered (file
,
4769 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4771 fprintf_unfiltered (file
,
4772 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4773 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4774 fprintf_unfiltered (file
,
4775 "mips_dump_tdep: HI_REGNUM = %d\n",
4777 fprintf_unfiltered (file
,
4778 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4779 fprintf_unfiltered (file
,
4780 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4781 fprintf_unfiltered (file
,
4782 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4783 XSTRING (IGNORE_HELPER_CALL (PC
)));
4784 fprintf_unfiltered (file
,
4785 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4786 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4787 fprintf_unfiltered (file
,
4788 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4789 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4790 fprintf_unfiltered (file
,
4791 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4792 fprintf_unfiltered (file
,
4793 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4795 fprintf_unfiltered (file
,
4796 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4797 fprintf_unfiltered (file
,
4798 "mips_dump_tdep: LO_REGNUM = %d\n",
4800 #ifdef MACHINE_CPROC_FP_OFFSET
4801 fprintf_unfiltered (file
,
4802 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4803 MACHINE_CPROC_FP_OFFSET
);
4805 #ifdef MACHINE_CPROC_PC_OFFSET
4806 fprintf_unfiltered (file
,
4807 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4808 MACHINE_CPROC_PC_OFFSET
);
4810 #ifdef MACHINE_CPROC_SP_OFFSET
4811 fprintf_unfiltered (file
,
4812 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4813 MACHINE_CPROC_SP_OFFSET
);
4815 fprintf_unfiltered (file
,
4816 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4817 fprintf_unfiltered (file
,
4818 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4819 fprintf_unfiltered (file
,
4820 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4822 fprintf_unfiltered (file
,
4823 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4824 fprintf_unfiltered (file
,
4825 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4826 fprintf_unfiltered (file
,
4827 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4828 fprintf_unfiltered (file
,
4829 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4831 fprintf_unfiltered (file
,
4832 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4833 MIPS_LAST_ARG_REGNUM
,
4834 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4835 fprintf_unfiltered (file
,
4836 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4838 fprintf_unfiltered (file
,
4839 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4840 fprintf_unfiltered (file
,
4841 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4842 MIPS_SAVED_REGSIZE
);
4843 fprintf_unfiltered (file
,
4844 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4845 fprintf_unfiltered (file
,
4846 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4847 XSTRING (MSYMBOL_SIZE (MSYM
)));
4848 fprintf_unfiltered (file
,
4849 "mips_dump_tdep: OP_LDFPR = used?\n");
4850 fprintf_unfiltered (file
,
4851 "mips_dump_tdep: OP_LDGPR = used?\n");
4852 fprintf_unfiltered (file
,
4853 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4854 fprintf_unfiltered (file
,
4855 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4856 fprintf_unfiltered (file
,
4857 "mips_dump_tdep: PRID_REGNUM = %d\n",
4859 fprintf_unfiltered (file
,
4860 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4861 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4862 fprintf_unfiltered (file
,
4863 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4864 fprintf_unfiltered (file
,
4865 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4866 fprintf_unfiltered (file
,
4867 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4868 fprintf_unfiltered (file
,
4869 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4870 fprintf_unfiltered (file
,
4871 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4872 fprintf_unfiltered (file
,
4873 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4874 fprintf_unfiltered (file
,
4875 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4876 fprintf_unfiltered (file
,
4877 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4878 fprintf_unfiltered (file
,
4879 "mips_dump_tdep: PROC_PC_REG = function?\n");
4880 fprintf_unfiltered (file
,
4881 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4882 fprintf_unfiltered (file
,
4883 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4884 fprintf_unfiltered (file
,
4885 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4886 fprintf_unfiltered (file
,
4887 "mips_dump_tdep: PS_REGNUM = %d\n",
4889 fprintf_unfiltered (file
,
4890 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4892 fprintf_unfiltered (file
,
4893 "mips_dump_tdep: RA_REGNUM = %d\n",
4895 fprintf_unfiltered (file
,
4896 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4897 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4898 fprintf_unfiltered (file
,
4899 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4900 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4901 fprintf_unfiltered (file
,
4902 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4903 fprintf_unfiltered (file
,
4904 "mips_dump_tdep: ROUND_DOWN = function?\n");
4905 fprintf_unfiltered (file
,
4906 "mips_dump_tdep: ROUND_UP = function?\n");
4908 fprintf_unfiltered (file
,
4909 "mips_dump_tdep: SAVED_BYTES = %d\n",
4913 fprintf_unfiltered (file
,
4914 "mips_dump_tdep: SAVED_FP = %d\n",
4918 fprintf_unfiltered (file
,
4919 "mips_dump_tdep: SAVED_PC = %d\n",
4922 fprintf_unfiltered (file
,
4923 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4924 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4925 fprintf_unfiltered (file
,
4926 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4927 fprintf_unfiltered (file
,
4928 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4930 fprintf_unfiltered (file
,
4931 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4932 SIGFRAME_FPREGSAVE_OFF
);
4933 fprintf_unfiltered (file
,
4934 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4936 fprintf_unfiltered (file
,
4937 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4938 SIGFRAME_REGSAVE_OFF
);
4939 fprintf_unfiltered (file
,
4940 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4942 fprintf_unfiltered (file
,
4943 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4944 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4945 fprintf_unfiltered (file
,
4946 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4947 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4948 fprintf_unfiltered (file
,
4949 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
4950 SOFTWARE_SINGLE_STEP_P ());
4951 fprintf_unfiltered (file
,
4952 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4953 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4954 #ifdef STACK_END_ADDR
4955 fprintf_unfiltered (file
,
4956 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4959 fprintf_unfiltered (file
,
4960 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4961 XSTRING (STEP_SKIPS_DELAY (PC
)));
4962 fprintf_unfiltered (file
,
4963 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4964 STEP_SKIPS_DELAY_P
);
4965 fprintf_unfiltered (file
,
4966 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4967 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4968 fprintf_unfiltered (file
,
4969 "mips_dump_tdep: T9_REGNUM = %d\n",
4971 fprintf_unfiltered (file
,
4972 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4973 fprintf_unfiltered (file
,
4974 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4975 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4976 fprintf_unfiltered (file
,
4977 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4978 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4979 fprintf_unfiltered (file
,
4980 "mips_dump_tdep: TARGET_MIPS = used?\n");
4981 fprintf_unfiltered (file
,
4982 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4983 XSTRING (TM_PRINT_INSN_MACH
));
4985 fprintf_unfiltered (file
,
4986 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4987 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4990 fprintf_unfiltered (file
,
4991 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4994 #ifdef TRACE_FLAVOR_SIZE
4995 fprintf_unfiltered (file
,
4996 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5000 fprintf_unfiltered (file
,
5001 "mips_dump_tdep: TRACE_SET # %s\n",
5002 XSTRING (TRACE_SET (X
,STATE
)));
5004 fprintf_unfiltered (file
,
5005 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
5006 #ifdef UNUSED_REGNUM
5007 fprintf_unfiltered (file
,
5008 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
5011 fprintf_unfiltered (file
,
5012 "mips_dump_tdep: V0_REGNUM = %d\n",
5014 fprintf_unfiltered (file
,
5015 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5016 (long) VM_MIN_ADDRESS
);
5018 fprintf_unfiltered (file
,
5019 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
5022 fprintf_unfiltered (file
,
5023 "mips_dump_tdep: ZERO_REGNUM = %d\n",
5025 fprintf_unfiltered (file
,
5026 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
5029 fprintf_unfiltered (file
,
5030 "mips_dump_tdep: OS ABI = %s\n",
5031 gdbarch_osabi_name (tdep
->osabi
));
5035 _initialize_mips_tdep (void)
5037 static struct cmd_list_element
*mipsfpulist
= NULL
;
5038 struct cmd_list_element
*c
;
5040 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5041 if (MIPS_ABI_LAST
+ 1
5042 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5043 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
5045 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5046 if (!tm_print_insn
) /* Someone may have already set it */
5047 tm_print_insn
= gdb_print_insn_mips
;
5049 /* Add root prefix command for all "set mips"/"show mips" commands */
5050 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5051 "Various MIPS specific commands.",
5052 &setmipscmdlist
, "set mips ", 0, &setlist
);
5054 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5055 "Various MIPS specific commands.",
5056 &showmipscmdlist
, "show mips ", 0, &showlist
);
5058 /* Allow the user to override the saved register size. */
5059 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
5062 &mips_saved_regsize_string
, "\
5063 Set size of general purpose registers saved on the stack.\n\
5064 This option can be set to one of:\n\
5065 32 - Force GDB to treat saved GP registers as 32-bit\n\
5066 64 - Force GDB to treat saved GP registers as 64-bit\n\
5067 auto - Allow GDB to use the target's default setting or autodetect the\n\
5068 saved GP register size from information contained in the executable.\n\
5073 /* Allow the user to override the argument stack size. */
5074 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
5077 &mips_stack_argsize_string
, "\
5078 Set the amount of stack space reserved for each argument.\n\
5079 This option can be set to one of:\n\
5080 32 - Force GDB to allocate 32-bit chunks per argument\n\
5081 64 - Force GDB to allocate 64-bit chunks per argument\n\
5082 auto - Allow GDB to determine the correct setting from the current\n\
5083 target and executable (default)",
5087 /* Allow the user to override the ABI. */
5088 c
= add_set_enum_cmd
5089 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
5090 "Set the ABI used by this program.\n"
5091 "This option can be set to one of:\n"
5092 " auto - the default ABI associated with the current binary\n"
5099 add_show_from_set (c
, &showmipscmdlist
);
5100 set_cmd_sfunc (c
, mips_abi_update
);
5102 /* Let the user turn off floating point and set the fence post for
5103 heuristic_proc_start. */
5105 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5106 "Set use of MIPS floating-point coprocessor.",
5107 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5108 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5109 "Select single-precision MIPS floating-point coprocessor.",
5111 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5112 "Select double-precision MIPS floating-point coprocessor.",
5114 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5115 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5116 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5117 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5118 "Select no MIPS floating-point coprocessor.",
5120 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5121 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5122 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5123 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5124 "Select MIPS floating-point coprocessor automatically.",
5126 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5127 "Show current use of MIPS floating-point coprocessor target.",
5130 /* We really would like to have both "0" and "unlimited" work, but
5131 command.c doesn't deal with that. So make it a var_zinteger
5132 because the user can always use "999999" or some such for unlimited. */
5133 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
5134 (char *) &heuristic_fence_post
,
5136 Set the distance searched for the start of a function.\n\
5137 If you are debugging a stripped executable, GDB needs to search through the\n\
5138 program for the start of a function. This command sets the distance of the\n\
5139 search. The only need to set it is when debugging a stripped executable.",
5141 /* We need to throw away the frame cache when we set this, since it
5142 might change our ability to get backtraces. */
5143 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
5144 add_show_from_set (c
, &showlist
);
5146 /* Allow the user to control whether the upper bits of 64-bit
5147 addresses should be zeroed. */
5148 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
5149 Set zeroing of upper 32 bits of 64-bit addresses.\n\
5150 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5151 allow GDB to determine the correct value.\n", "\
5152 Show zeroing of upper 32 bits of 64-bit addresses.",
5153 NULL
, show_mask_address
,
5154 &setmipscmdlist
, &showmipscmdlist
);
5156 /* Allow the user to control the size of 32 bit registers within the
5157 raw remote packet. */
5158 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5161 (char *)&mips64_transfers_32bit_regs_p
, "\
5162 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5163 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5164 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5165 64 bits for others. Use \"off\" to disable compatibility mode",
5169 /* Debug this files internals. */
5170 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
5171 &mips_debug
, "Set mips debugging.\n\
5172 When non-zero, mips specific debugging is enabled.", &setdebuglist
),