1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
58 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
60 /* A useful bit in the CP0 status register (PS_REGNUM). */
61 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
62 #define ST0_FR (1 << 26)
64 /* The sizes of floating point registers. */
68 MIPS_FPU_SINGLE_REGSIZE
= 4,
69 MIPS_FPU_DOUBLE_REGSIZE
= 8
73 static const char *mips_abi_string
;
75 static const char *mips_abi_strings
[] = {
86 struct frame_extra_info
88 mips_extra_func_info_t proc_desc
;
92 /* Various MIPS ISA options (related to stack analysis) can be
93 overridden dynamically. Establish an enum/array for managing
96 static const char size_auto
[] = "auto";
97 static const char size_32
[] = "32";
98 static const char size_64
[] = "64";
100 static const char *size_enums
[] = {
107 /* Some MIPS boards don't support floating point while others only
108 support single-precision floating-point operations. See also
109 FP_REGISTER_DOUBLE. */
113 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
114 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
115 MIPS_FPU_NONE
/* No floating point. */
118 #ifndef MIPS_DEFAULT_FPU_TYPE
119 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
121 static int mips_fpu_type_auto
= 1;
122 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
124 static int mips_debug
= 0;
126 /* MIPS specific per-architecture information */
129 /* from the elf header */
133 enum mips_abi mips_abi
;
134 enum mips_abi found_abi
;
135 enum mips_fpu_type mips_fpu_type
;
136 int mips_last_arg_regnum
;
137 int mips_last_fp_arg_regnum
;
138 int mips_default_saved_regsize
;
139 int mips_fp_register_double
;
140 int mips_default_stack_argsize
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
153 const struct mips_regnum
*
154 mips_regnum (struct gdbarch
*gdbarch
)
156 return gdbarch_tdep (gdbarch
)->regnum
;
160 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
162 return mips_regnum (gdbarch
)->fp0
+ 12;
165 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
166 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
168 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
170 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
172 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
174 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
175 functions to test, set, or clear bit 0 of addresses. */
178 is_mips16_addr (CORE_ADDR addr
)
184 make_mips16_addr (CORE_ADDR addr
)
190 unmake_mips16_addr (CORE_ADDR addr
)
192 return ((addr
) & ~1);
195 /* Return the contents of register REGNUM as a signed integer. */
198 read_signed_register (int regnum
)
200 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
201 deprecated_read_register_gen (regnum
, buf
);
202 return (extract_signed_integer
203 (buf
, register_size (current_gdbarch
, regnum
)));
207 read_signed_register_pid (int regnum
, ptid_t ptid
)
212 if (ptid_equal (ptid
, inferior_ptid
))
213 return read_signed_register (regnum
);
215 save_ptid
= inferior_ptid
;
217 inferior_ptid
= ptid
;
219 retval
= read_signed_register (regnum
);
221 inferior_ptid
= save_ptid
;
226 /* Return the MIPS ABI associated with GDBARCH. */
228 mips_abi (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->mips_abi
;
234 mips_regsize (struct gdbarch
*gdbarch
)
236 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
237 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
240 /* Return the currently configured (or set) saved register size. */
242 static const char *mips_saved_regsize_string
= size_auto
;
245 mips_saved_regsize (struct gdbarch_tdep
*tdep
)
247 if (mips_saved_regsize_string
== size_auto
)
248 return tdep
->mips_default_saved_regsize
;
249 else if (mips_saved_regsize_string
== size_64
)
251 else /* if (mips_saved_regsize_string == size_32) */
255 /* Functions for setting and testing a bit in a minimal symbol that
256 marks it as 16-bit function. The MSB of the minimal symbol's
257 "info" field is used for this purpose.
259 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
260 i.e. refers to a 16-bit function, and sets a "special" bit in a
261 minimal symbol to mark it as a 16-bit function
263 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
266 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
268 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
270 MSYMBOL_INFO (msym
) = (char *)
271 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
272 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
277 msymbol_is_special (struct minimal_symbol
*msym
)
279 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
282 /* XFER a value from the big/little/left end of the register.
283 Depending on the size of the value it might occupy the entire
284 register or just part of it. Make an allowance for this, aligning
285 things accordingly. */
288 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
289 enum bfd_endian endian
, bfd_byte
* in
,
290 const bfd_byte
* out
, int buf_offset
)
293 gdb_assert (reg_num
>= NUM_REGS
);
294 /* Need to transfer the left or right part of the register, based on
295 the targets byte order. */
299 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
301 case BFD_ENDIAN_LITTLE
:
304 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
308 internal_error (__FILE__
, __LINE__
, "bad switch");
311 fprintf_unfiltered (gdb_stderr
,
312 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
313 reg_num
, reg_offset
, buf_offset
, length
);
314 if (mips_debug
&& out
!= NULL
)
317 fprintf_unfiltered (gdb_stdlog
, "out ");
318 for (i
= 0; i
< length
; i
++)
319 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
322 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
325 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
327 if (mips_debug
&& in
!= NULL
)
330 fprintf_unfiltered (gdb_stdlog
, "in ");
331 for (i
= 0; i
< length
; i
++)
332 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
335 fprintf_unfiltered (gdb_stdlog
, "\n");
338 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
339 compatiblity mode. A return value of 1 means that we have
340 physical 64-bit registers, but should treat them as 32-bit registers. */
343 mips2_fp_compat (void)
345 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
347 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
352 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
353 in all the places we deal with FP registers. PR gdb/413. */
354 /* Otherwise check the FR bit in the status register - it controls
355 the FP compatiblity mode. If it is clear we are in compatibility
357 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
364 /* Indicate that the ABI makes use of double-precision registers
365 provided by the FPU (rather than combining pairs of registers to
366 form double-precision values). See also MIPS_FPU_TYPE. */
367 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
369 /* The amount of space reserved on the stack for registers. This is
370 different to MIPS_SAVED_REGSIZE as it determines the alignment of
371 data allocated after the registers have run out. */
373 static const char *mips_stack_argsize_string
= size_auto
;
376 mips_stack_argsize (struct gdbarch_tdep
*tdep
)
378 if (mips_stack_argsize_string
== size_auto
)
379 return tdep
->mips_default_stack_argsize
;
380 else if (mips_stack_argsize_string
== size_64
)
382 else /* if (mips_stack_argsize_string == size_32) */
386 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
388 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
389 struct frame_info
*, int);
391 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
393 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
395 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
397 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
398 struct frame_info
*next_frame
,
401 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
402 mips_extra_func_info_t proc_desc
);
404 static struct type
*mips_float_register_type (void);
405 static struct type
*mips_double_register_type (void);
407 /* The list of available "set mips " and "show mips " commands */
409 static struct cmd_list_element
*setmipscmdlist
= NULL
;
410 static struct cmd_list_element
*showmipscmdlist
= NULL
;
412 /* Integer registers 0 thru 31 are handled explicitly by
413 mips_register_name(). Processor specific registers 32 and above
414 are listed in the followign tables. */
417 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
421 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
422 "sr", "lo", "hi", "bad", "cause", "pc",
423 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
424 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
425 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
426 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
427 "fsr", "fir", "" /*"fp" */ , "",
428 "", "", "", "", "", "", "", "",
429 "", "", "", "", "", "", "", "",
432 /* Names of IDT R3041 registers. */
434 static const char *mips_r3041_reg_names
[] = {
435 "sr", "lo", "hi", "bad", "cause", "pc",
436 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
437 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
438 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
439 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
440 "fsr", "fir", "", /*"fp" */ "",
441 "", "", "bus", "ccfg", "", "", "", "",
442 "", "", "port", "cmp", "", "", "epc", "prid",
445 /* Names of tx39 registers. */
447 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
448 "sr", "lo", "hi", "bad", "cause", "pc",
449 "", "", "", "", "", "", "", "",
450 "", "", "", "", "", "", "", "",
451 "", "", "", "", "", "", "", "",
452 "", "", "", "", "", "", "", "",
454 "", "", "", "", "", "", "", "",
455 "", "", "config", "cache", "debug", "depc", "epc", ""
458 /* Names of IRIX registers. */
459 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
460 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
461 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
462 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
463 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
464 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
468 /* Return the name of the register corresponding to REGNO. */
470 mips_register_name (int regno
)
472 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
473 /* GPR names for all ABIs other than n32/n64. */
474 static char *mips_gpr_names
[] = {
475 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
476 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
477 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
478 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
481 /* GPR names for n32 and n64 ABIs. */
482 static char *mips_n32_n64_gpr_names
[] = {
483 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
484 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
485 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
486 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
489 enum mips_abi abi
= mips_abi (current_gdbarch
);
491 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
492 don't make the raw register names visible. */
493 int rawnum
= regno
% NUM_REGS
;
494 if (regno
< NUM_REGS
)
497 /* The MIPS integer registers are always mapped from 0 to 31. The
498 names of the registers (which reflects the conventions regarding
499 register use) vary depending on the ABI. */
500 if (0 <= rawnum
&& rawnum
< 32)
502 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
503 return mips_n32_n64_gpr_names
[rawnum
];
505 return mips_gpr_names
[rawnum
];
507 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
509 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
510 return tdep
->mips_processor_reg_names
[rawnum
- 32];
513 internal_error (__FILE__
, __LINE__
,
514 "mips_register_name: bad register number %d", rawnum
);
517 /* Return the groups that a MIPS register can be categorised into. */
520 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
521 struct reggroup
*reggroup
)
526 int rawnum
= regnum
% NUM_REGS
;
527 int pseudo
= regnum
/ NUM_REGS
;
528 if (reggroup
== all_reggroup
)
530 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
531 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
532 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
533 (gdbarch), as not all architectures are multi-arch. */
534 raw_p
= rawnum
< NUM_REGS
;
535 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
537 if (reggroup
== float_reggroup
)
538 return float_p
&& pseudo
;
539 if (reggroup
== vector_reggroup
)
540 return vector_p
&& pseudo
;
541 if (reggroup
== general_reggroup
)
542 return (!vector_p
&& !float_p
) && pseudo
;
543 /* Save the pseudo registers. Need to make certain that any code
544 extracting register values from a saved register cache also uses
546 if (reggroup
== save_reggroup
)
547 return raw_p
&& pseudo
;
548 /* Restore the same pseudo register. */
549 if (reggroup
== restore_reggroup
)
550 return raw_p
&& pseudo
;
554 /* Map the symbol table registers which live in the range [1 *
555 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
556 registers. Take care of alignment and size problems. */
559 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
560 int cookednum
, void *buf
)
562 int rawnum
= cookednum
% NUM_REGS
;
563 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
564 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
565 regcache_raw_read (regcache
, rawnum
, buf
);
566 else if (register_size (gdbarch
, rawnum
) >
567 register_size (gdbarch
, cookednum
))
569 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
570 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
571 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
573 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
576 internal_error (__FILE__
, __LINE__
, "bad register size");
580 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
581 struct regcache
*regcache
, int cookednum
,
584 int rawnum
= cookednum
% NUM_REGS
;
585 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
586 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
587 regcache_raw_write (regcache
, rawnum
, buf
);
588 else if (register_size (gdbarch
, rawnum
) >
589 register_size (gdbarch
, cookednum
))
591 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
592 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
593 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
595 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
598 internal_error (__FILE__
, __LINE__
, "bad register size");
601 /* Table to translate MIPS16 register field to actual register number. */
602 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
604 /* Heuristic_proc_start may hunt through the text section for a long
605 time across a 2400 baud serial line. Allows the user to limit this
608 static unsigned int heuristic_fence_post
= 0;
610 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
611 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
612 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
613 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
614 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
615 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
616 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
617 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
618 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
619 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
620 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
621 this will corrupt pdr.iline. Fortunately we don't use it. */
622 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
623 #define _PROC_MAGIC_ 0x0F0F0F0F
624 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
625 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
627 struct linked_proc_info
629 struct mips_extra_func_info info
;
630 struct linked_proc_info
*next
;
632 *linked_proc_desc_table
= NULL
;
634 /* Number of bytes of storage in the actual machine representation for
635 register N. NOTE: This defines the pseudo register type so need to
636 rebuild the architecture vector. */
638 static int mips64_transfers_32bit_regs_p
= 0;
641 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
642 struct cmd_list_element
*c
)
644 struct gdbarch_info info
;
645 gdbarch_info_init (&info
);
646 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
647 instead of relying on globals. Doing that would let generic code
648 handle the search for this specific architecture. */
649 if (!gdbarch_update_p (info
))
651 mips64_transfers_32bit_regs_p
= 0;
652 error ("32-bit compatibility mode not supported");
656 /* Convert to/from a register and the corresponding memory value. */
659 mips_convert_register_p (int regnum
, struct type
*type
)
661 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
662 && register_size (current_gdbarch
, regnum
) == 4
663 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
664 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
665 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
669 mips_register_to_value (struct frame_info
*frame
, int regnum
,
670 struct type
*type
, void *to
)
672 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
673 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
677 mips_value_to_register (struct frame_info
*frame
, int regnum
,
678 struct type
*type
, const void *from
)
680 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
681 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
684 /* Return the GDB type object for the "standard" data type of data in
688 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
690 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
691 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
692 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
694 /* The floating-point registers raw, or cooked, always match
695 mips_regsize(), and also map 1:1, byte for byte. */
696 switch (gdbarch_byte_order (gdbarch
))
699 if (mips_regsize (gdbarch
) == 4)
700 return builtin_type_ieee_single_big
;
702 return builtin_type_ieee_double_big
;
703 case BFD_ENDIAN_LITTLE
:
704 if (mips_regsize (gdbarch
) == 4)
705 return builtin_type_ieee_single_little
;
707 return builtin_type_ieee_double_little
;
708 case BFD_ENDIAN_UNKNOWN
:
710 internal_error (__FILE__
, __LINE__
, "bad switch");
714 (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
715 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
716 /* The pseudo/cooked view of the embedded registers is always
717 32-bit. The raw view is handled below. */
718 return builtin_type_int32
;
719 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
720 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
721 /* The target, while using a 64-bit register buffer, is only
722 transfering 32-bits of each integer register. Reflect this in
723 the cooked/pseudo register value. */
724 return builtin_type_int32
;
725 else if (mips_regsize (gdbarch
) == 8)
727 return builtin_type_int64
;
730 return builtin_type_int32
;
733 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
738 return read_signed_register (SP_REGNUM
);
741 /* Should the upper word of 64-bit addresses be zeroed? */
742 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
745 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
747 switch (mask_address_var
)
749 case AUTO_BOOLEAN_TRUE
:
751 case AUTO_BOOLEAN_FALSE
:
754 case AUTO_BOOLEAN_AUTO
:
755 return tdep
->default_mask_address_p
;
757 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
763 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
765 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
766 switch (mask_address_var
)
768 case AUTO_BOOLEAN_TRUE
:
769 printf_filtered ("The 32 bit mips address mask is enabled\n");
771 case AUTO_BOOLEAN_FALSE
:
772 printf_filtered ("The 32 bit mips address mask is disabled\n");
774 case AUTO_BOOLEAN_AUTO
:
776 ("The 32 bit address mask is set automatically. Currently %s\n",
777 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
780 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
785 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
788 pc_is_mips16 (bfd_vma memaddr
)
790 struct minimal_symbol
*sym
;
792 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
793 if (is_mips16_addr (memaddr
))
796 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
797 the high bit of the info field. Use this to decide if the function is
798 MIPS16 or normal MIPS. */
799 sym
= lookup_minimal_symbol_by_pc (memaddr
);
801 return msymbol_is_special (sym
);
806 /* MIPS believes that the PC has a sign extended value. Perhaphs the
807 all registers should be sign extended for simplicity? */
810 mips_read_pc (ptid_t ptid
)
812 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
816 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
818 return frame_unwind_register_signed (next_frame
,
819 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
822 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
823 dummy frame. The frame ID's base needs to match the TOS value
824 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
827 static struct frame_id
828 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
830 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ SP_REGNUM
),
831 frame_pc_unwind (next_frame
));
835 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
837 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
840 /* This returns the PC of the first inst after the prologue. If we can't
841 find the prologue, then return 0. */
844 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
846 struct symtab_and_line sal
;
847 CORE_ADDR func_addr
, func_end
;
849 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
850 to read the stack pointer from the current machine state, because
851 the current machine state has nothing to do with the information
852 we need from the proc_desc; and the process may or may not exist
855 proc_desc
= find_proc_desc (pc
, NULL
, 0);
859 /* If function is frameless, then we need to do it the hard way. I
860 strongly suspect that frameless always means prologueless... */
861 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
862 && PROC_FRAME_OFFSET (proc_desc
) == 0)
866 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
867 return 0; /* Unknown */
869 sal
= find_pc_line (func_addr
, 0);
871 if (sal
.end
< func_end
)
874 /* The line after the prologue is after the end of the function. In this
875 case, tell the caller to find the prologue the hard way. */
880 /* Decode a MIPS32 instruction that saves a register in the stack, and
881 set the appropriate bit in the general register mask or float register mask
882 to indicate which register is saved. This is a helper function
883 for mips_find_saved_regs. */
886 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
887 unsigned long *float_mask
)
891 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
892 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
893 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
895 /* It might be possible to use the instruction to
896 find the offset, rather than the code below which
897 is based on things being in a certain order in the
898 frame, but figuring out what the instruction's offset
899 is relative to might be a little tricky. */
900 reg
= (inst
& 0x001f0000) >> 16;
901 *gen_mask
|= (1 << reg
);
903 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
904 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
905 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
908 reg
= ((inst
& 0x001f0000) >> 16);
909 *float_mask
|= (1 << reg
);
913 /* Decode a MIPS16 instruction that saves a register in the stack, and
914 set the appropriate bit in the general register or float register mask
915 to indicate which register is saved. This is a helper function
916 for mips_find_saved_regs. */
919 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
921 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
923 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
924 *gen_mask
|= (1 << reg
);
926 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
928 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
929 *gen_mask
|= (1 << reg
);
931 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
932 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
933 *gen_mask
|= (1 << RA_REGNUM
);
937 /* Fetch and return instruction from the specified location. If the PC
938 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
941 mips_fetch_instruction (CORE_ADDR addr
)
943 char buf
[MIPS_INSTLEN
];
947 if (pc_is_mips16 (addr
))
949 instlen
= MIPS16_INSTLEN
;
950 addr
= unmake_mips16_addr (addr
);
953 instlen
= MIPS_INSTLEN
;
954 status
= read_memory_nobpt (addr
, buf
, instlen
);
956 memory_error (status
, addr
);
957 return extract_unsigned_integer (buf
, instlen
);
961 mips16_fetch_instruction (CORE_ADDR addr
)
963 char buf
[MIPS_INSTLEN
];
967 instlen
= MIPS16_INSTLEN
;
968 addr
= unmake_mips16_addr (addr
);
969 status
= read_memory_nobpt (addr
, buf
, instlen
);
971 memory_error (status
, addr
);
972 return extract_unsigned_integer (buf
, instlen
);
976 mips32_fetch_instruction (CORE_ADDR addr
)
978 char buf
[MIPS_INSTLEN
];
981 instlen
= MIPS_INSTLEN
;
982 status
= read_memory_nobpt (addr
, buf
, instlen
);
984 memory_error (status
, addr
);
985 return extract_unsigned_integer (buf
, instlen
);
989 /* These the fields of 32 bit mips instructions */
990 #define mips32_op(x) (x >> 26)
991 #define itype_op(x) (x >> 26)
992 #define itype_rs(x) ((x >> 21) & 0x1f)
993 #define itype_rt(x) ((x >> 16) & 0x1f)
994 #define itype_immediate(x) (x & 0xffff)
996 #define jtype_op(x) (x >> 26)
997 #define jtype_target(x) (x & 0x03ffffff)
999 #define rtype_op(x) (x >> 26)
1000 #define rtype_rs(x) ((x >> 21) & 0x1f)
1001 #define rtype_rt(x) ((x >> 16) & 0x1f)
1002 #define rtype_rd(x) ((x >> 11) & 0x1f)
1003 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1004 #define rtype_funct(x) (x & 0x3f)
1007 mips32_relative_offset (unsigned long inst
)
1010 x
= itype_immediate (inst
);
1011 if (x
& 0x8000) /* sign bit set */
1013 x
|= 0xffff0000; /* sign extension */
1019 /* Determine whate to set a single step breakpoint while considering
1020 branch prediction */
1022 mips32_next_pc (CORE_ADDR pc
)
1026 inst
= mips_fetch_instruction (pc
);
1027 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1029 if (itype_op (inst
) >> 2 == 5)
1030 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1032 op
= (itype_op (inst
) & 0x03);
1042 goto greater_branch
;
1047 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1048 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1050 int tf
= itype_rt (inst
) & 0x01;
1051 int cnum
= itype_rt (inst
) >> 2;
1053 read_signed_register (mips_regnum (current_gdbarch
)->
1055 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1057 if (((cond
>> cnum
) & 0x01) == tf
)
1058 pc
+= mips32_relative_offset (inst
) + 4;
1063 pc
+= 4; /* Not a branch, next instruction is easy */
1066 { /* This gets way messy */
1068 /* Further subdivide into SPECIAL, REGIMM and other */
1069 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1071 case 0: /* SPECIAL */
1072 op
= rtype_funct (inst
);
1077 /* Set PC to that address */
1078 pc
= read_signed_register (rtype_rs (inst
));
1084 break; /* end SPECIAL */
1085 case 1: /* REGIMM */
1087 op
= itype_rt (inst
); /* branch condition */
1092 case 16: /* BLTZAL */
1093 case 18: /* BLTZALL */
1095 if (read_signed_register (itype_rs (inst
)) < 0)
1096 pc
+= mips32_relative_offset (inst
) + 4;
1098 pc
+= 8; /* after the delay slot */
1102 case 17: /* BGEZAL */
1103 case 19: /* BGEZALL */
1104 if (read_signed_register (itype_rs (inst
)) >= 0)
1105 pc
+= mips32_relative_offset (inst
) + 4;
1107 pc
+= 8; /* after the delay slot */
1109 /* All of the other instructions in the REGIMM category */
1114 break; /* end REGIMM */
1119 reg
= jtype_target (inst
) << 2;
1120 /* Upper four bits get never changed... */
1121 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1124 /* FIXME case JALX : */
1127 reg
= jtype_target (inst
) << 2;
1128 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1129 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1131 break; /* The new PC will be alternate mode */
1132 case 4: /* BEQ, BEQL */
1134 if (read_signed_register (itype_rs (inst
)) ==
1135 read_signed_register (itype_rt (inst
)))
1136 pc
+= mips32_relative_offset (inst
) + 4;
1140 case 5: /* BNE, BNEL */
1142 if (read_signed_register (itype_rs (inst
)) !=
1143 read_signed_register (itype_rt (inst
)))
1144 pc
+= mips32_relative_offset (inst
) + 4;
1148 case 6: /* BLEZ, BLEZL */
1149 if (read_signed_register (itype_rs (inst
) <= 0))
1150 pc
+= mips32_relative_offset (inst
) + 4;
1156 greater_branch
: /* BGTZ, BGTZL */
1157 if (read_signed_register (itype_rs (inst
) > 0))
1158 pc
+= mips32_relative_offset (inst
) + 4;
1165 } /* mips32_next_pc */
1167 /* Decoding the next place to set a breakpoint is irregular for the
1168 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1169 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1170 We dont want to set a single step instruction on the extend instruction
1174 /* Lots of mips16 instruction formats */
1175 /* Predicting jumps requires itype,ritype,i8type
1176 and their extensions extItype,extritype,extI8type
1178 enum mips16_inst_fmts
1180 itype
, /* 0 immediate 5,10 */
1181 ritype
, /* 1 5,3,8 */
1182 rrtype
, /* 2 5,3,3,5 */
1183 rritype
, /* 3 5,3,3,5 */
1184 rrrtype
, /* 4 5,3,3,3,2 */
1185 rriatype
, /* 5 5,3,3,1,4 */
1186 shifttype
, /* 6 5,3,3,3,2 */
1187 i8type
, /* 7 5,3,8 */
1188 i8movtype
, /* 8 5,3,3,5 */
1189 i8mov32rtype
, /* 9 5,3,5,3 */
1190 i64type
, /* 10 5,3,8 */
1191 ri64type
, /* 11 5,3,3,5 */
1192 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1193 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1194 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1195 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1196 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1197 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1198 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1199 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1200 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1201 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1203 /* I am heaping all the fields of the formats into one structure and
1204 then, only the fields which are involved in instruction extension */
1208 unsigned int regx
; /* Function in i8 type */
1213 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1214 for the bits which make up the immediatate extension. */
1217 extended_offset (unsigned int extension
)
1220 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1222 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1224 value
|= extension
& 0x01f; /* extract 4:0 */
1228 /* Only call this function if you know that this is an extendable
1229 instruction, It wont malfunction, but why make excess remote memory references?
1230 If the immediate operands get sign extended or somthing, do it after
1231 the extension is performed.
1233 /* FIXME: Every one of these cases needs to worry about sign extension
1234 when the offset is to be used in relative addressing */
1238 fetch_mips_16 (CORE_ADDR pc
)
1241 pc
&= 0xfffffffe; /* clear the low order bit */
1242 target_read_memory (pc
, buf
, 2);
1243 return extract_unsigned_integer (buf
, 2);
1247 unpack_mips16 (CORE_ADDR pc
,
1248 unsigned int extension
,
1250 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1255 switch (insn_format
)
1262 value
= extended_offset (extension
);
1263 value
= value
<< 11; /* rom for the original value */
1264 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1268 value
= inst
& 0x7ff;
1269 /* FIXME : Consider sign extension */
1278 { /* A register identifier and an offset */
1279 /* Most of the fields are the same as I type but the
1280 immediate value is of a different length */
1284 value
= extended_offset (extension
);
1285 value
= value
<< 8; /* from the original instruction */
1286 value
|= inst
& 0xff; /* eleven bits from instruction */
1287 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1288 if (value
& 0x4000) /* test the sign bit , bit 26 */
1290 value
&= ~0x3fff; /* remove the sign bit */
1296 value
= inst
& 0xff; /* 8 bits */
1297 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1298 /* FIXME: Do sign extension , this format needs it */
1299 if (value
& 0x80) /* THIS CONFUSES ME */
1301 value
&= 0xef; /* remove the sign bit */
1311 unsigned long value
;
1312 unsigned int nexthalf
;
1313 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1314 value
= value
<< 16;
1315 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1323 internal_error (__FILE__
, __LINE__
, "bad switch");
1325 upk
->offset
= offset
;
1332 add_offset_16 (CORE_ADDR pc
, int offset
)
1334 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1338 extended_mips16_next_pc (CORE_ADDR pc
,
1339 unsigned int extension
, unsigned int insn
)
1341 int op
= (insn
>> 11);
1344 case 2: /* Branch */
1347 struct upk_mips16 upk
;
1348 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1349 offset
= upk
.offset
;
1355 pc
+= (offset
<< 1) + 2;
1358 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1360 struct upk_mips16 upk
;
1361 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1362 pc
= add_offset_16 (pc
, upk
.offset
);
1363 if ((insn
>> 10) & 0x01) /* Exchange mode */
1364 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1371 struct upk_mips16 upk
;
1373 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1374 reg
= read_signed_register (upk
.regx
);
1376 pc
+= (upk
.offset
<< 1) + 2;
1383 struct upk_mips16 upk
;
1385 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1386 reg
= read_signed_register (upk
.regx
);
1388 pc
+= (upk
.offset
<< 1) + 2;
1393 case 12: /* I8 Formats btez btnez */
1395 struct upk_mips16 upk
;
1397 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1398 /* upk.regx contains the opcode */
1399 reg
= read_signed_register (24); /* Test register is 24 */
1400 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1401 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1402 /* pc = add_offset_16(pc,upk.offset) ; */
1403 pc
+= (upk
.offset
<< 1) + 2;
1408 case 29: /* RR Formats JR, JALR, JALR-RA */
1410 struct upk_mips16 upk
;
1411 /* upk.fmt = rrtype; */
1416 upk
.regx
= (insn
>> 8) & 0x07;
1417 upk
.regy
= (insn
>> 5) & 0x07;
1425 break; /* Function return instruction */
1431 break; /* BOGUS Guess */
1433 pc
= read_signed_register (reg
);
1440 /* This is an instruction extension. Fetch the real instruction
1441 (which follows the extension) and decode things based on
1445 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1458 mips16_next_pc (CORE_ADDR pc
)
1460 unsigned int insn
= fetch_mips_16 (pc
);
1461 return extended_mips16_next_pc (pc
, 0, insn
);
1464 /* The mips_next_pc function supports single_step when the remote
1465 target monitor or stub is not developed enough to do a single_step.
1466 It works by decoding the current instruction and predicting where a
1467 branch will go. This isnt hard because all the data is available.
1468 The MIPS32 and MIPS16 variants are quite different */
1470 mips_next_pc (CORE_ADDR pc
)
1473 return mips16_next_pc (pc
);
1475 return mips32_next_pc (pc
);
1478 struct mips_frame_cache
1481 struct trad_frame_saved_reg
*saved_regs
;
1485 static struct mips_frame_cache
*
1486 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1488 mips_extra_func_info_t proc_desc
;
1489 struct mips_frame_cache
*cache
;
1490 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1491 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1492 /* r0 bit means kernel trap */
1494 /* What registers have been saved? Bitmasks. */
1495 unsigned long gen_mask
, float_mask
;
1497 if ((*this_cache
) != NULL
)
1498 return (*this_cache
);
1499 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1500 (*this_cache
) = cache
;
1501 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1503 /* Get the mdebug proc descriptor. */
1504 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1505 if (proc_desc
== NULL
)
1506 /* I'm not sure how/whether this can happen. Normally when we
1507 can't find a proc_desc, we "synthesize" one using
1508 heuristic_proc_desc and set the saved_regs right away. */
1511 /* Extract the frame's base. */
1512 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1513 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1515 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1516 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1517 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1519 /* In any frame other than the innermost or a frame interrupted by a
1520 signal, we assume that all registers have been saved. This
1521 assumes that all register saves in a function happen before the
1522 first function call. */
1523 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1524 /* Not sure exactly what kernel_trap means, but if it means the
1525 kernel saves the registers without a prologue doing it, we
1526 better not examine the prologue to see whether registers
1527 have been saved yet. */
1530 /* We need to figure out whether the registers that the
1531 proc_desc claims are saved have been saved yet. */
1535 /* Bitmasks; set if we have found a save for the register. */
1536 unsigned long gen_save_found
= 0;
1537 unsigned long float_save_found
= 0;
1540 /* If the address is odd, assume this is MIPS16 code. */
1541 addr
= PROC_LOW_ADDR (proc_desc
);
1542 mips16
= pc_is_mips16 (addr
);
1544 /* Scan through this function's instructions preceding the
1545 current PC, and look for those that save registers. */
1546 while (addr
< frame_pc_unwind (next_frame
))
1550 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1552 addr
+= MIPS16_INSTLEN
;
1556 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1557 &gen_save_found
, &float_save_found
);
1558 addr
+= MIPS_INSTLEN
;
1561 gen_mask
= gen_save_found
;
1562 float_mask
= float_save_found
;
1565 /* Fill in the offsets for the registers which gen_mask says were
1568 CORE_ADDR reg_position
= (cache
->base
1569 + PROC_REG_OFFSET (proc_desc
));
1571 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1572 if (gen_mask
& 0x80000000)
1574 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1575 reg_position
-= mips_saved_regsize (tdep
);
1579 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1580 order of that normally used by gcc. Therefore, we have to fetch
1581 the first instruction of the function, and if it's an entry
1582 instruction that saves $s0 or $s1, correct their saved addresses. */
1583 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1585 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1586 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1590 int sreg_count
= (inst
>> 6) & 3;
1592 /* Check if the ra register was pushed on the stack. */
1593 CORE_ADDR reg_position
= (cache
->base
1594 + PROC_REG_OFFSET (proc_desc
));
1596 reg_position
-= mips_saved_regsize (tdep
);
1598 /* Check if the s0 and s1 registers were pushed on the
1600 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1602 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1604 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1605 reg_position
-= mips_saved_regsize (tdep
);
1610 /* Fill in the offsets for the registers which float_mask says were
1613 CORE_ADDR reg_position
= (cache
->base
1614 + PROC_FREG_OFFSET (proc_desc
));
1616 /* Fill in the offsets for the float registers which float_mask
1618 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1619 if (float_mask
& 0x80000000)
1621 if (mips_saved_regsize (tdep
) == 4
1622 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1624 /* On a big endian 32 bit ABI, floating point registers
1625 are paired to form doubles such that the most
1626 significant part is in $f[N+1] and the least
1627 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1628 registers are also spilled as a pair and stored as a
1631 When little-endian the least significant part is
1632 stored first leading to the memory order $f[N] and
1635 Unfortunately, when big-endian the most significant
1636 part of the double is stored first, and the least
1637 significant is stored second. This leads to the
1638 registers being ordered in memory as firt $f[N+1] and
1641 For the big-endian case make certain that the
1642 addresses point at the correct (swapped) locations
1643 $f[N] and $f[N+1] pair (keep in mind that
1644 reg_position is decremented each time through the
1647 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1648 .addr
= reg_position
- mips_saved_regsize (tdep
);
1650 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1651 .addr
= reg_position
+ mips_saved_regsize (tdep
);
1654 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1655 .addr
= reg_position
;
1656 reg_position
-= mips_saved_regsize (tdep
);
1659 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1660 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1663 /* SP_REGNUM, contains the value and not the address. */
1664 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ SP_REGNUM
, cache
->base
);
1666 return (*this_cache
);
1670 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1671 struct frame_id
*this_id
)
1673 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1675 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1679 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1681 int regnum
, int *optimizedp
,
1682 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1683 int *realnump
, void *valuep
)
1685 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1687 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
1688 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1691 static const struct frame_unwind mips_mdebug_frame_unwind
=
1694 mips_mdebug_frame_this_id
,
1695 mips_mdebug_frame_prev_register
1698 static const struct frame_unwind
*
1699 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1701 return &mips_mdebug_frame_unwind
;
1705 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1708 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1713 static const struct frame_base mips_mdebug_frame_base
= {
1714 &mips_mdebug_frame_unwind
,
1715 mips_mdebug_frame_base_address
,
1716 mips_mdebug_frame_base_address
,
1717 mips_mdebug_frame_base_address
1720 static const struct frame_base
*
1721 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1723 return &mips_mdebug_frame_base
;
1727 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1729 /* Always a pseudo. */
1730 gdb_assert (regno
>= NUM_REGS
);
1734 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1737 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1738 /* The SP_REGNUM is special, its value is stored in saved_regs.
1739 In fact, it is so special that it can even only be fetched
1740 using a raw register number! Once this code as been converted
1741 to frame-unwind the problem goes away. */
1742 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1744 return frame_unwind_register_signed (fi
, regno
);
1748 /* mips_addr_bits_remove - remove useless address bits */
1751 mips_addr_bits_remove (CORE_ADDR addr
)
1753 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1754 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1755 /* This hack is a work-around for existing boards using PMON, the
1756 simulator, and any other 64-bit targets that doesn't have true
1757 64-bit addressing. On these targets, the upper 32 bits of
1758 addresses are ignored by the hardware. Thus, the PC or SP are
1759 likely to have been sign extended to all 1s by instruction
1760 sequences that load 32-bit addresses. For example, a typical
1761 piece of code that loads an address is this:
1763 lui $r2, <upper 16 bits>
1764 ori $r2, <lower 16 bits>
1766 But the lui sign-extends the value such that the upper 32 bits
1767 may be all 1s. The workaround is simply to mask off these
1768 bits. In the future, gcc may be changed to support true 64-bit
1769 addressing, and this masking will have to be disabled. */
1770 return addr
&= 0xffffffffUL
;
1775 /* mips_software_single_step() is called just before we want to resume
1776 the inferior, if we want to single-step it but there is no hardware
1777 or kernel single-step support (MIPS on GNU/Linux for example). We find
1778 the target of the coming instruction and breakpoint it.
1780 single_step is also called just after the inferior stops. If we had
1781 set up a simulated single-step, we undo our damage. */
1784 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1786 static CORE_ADDR next_pc
;
1787 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1788 static binsn_quantum break_mem
;
1791 if (insert_breakpoints_p
)
1793 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
1794 next_pc
= mips_next_pc (pc
);
1796 target_insert_breakpoint (next_pc
, break_mem
);
1799 target_remove_breakpoint (next_pc
, break_mem
);
1802 static struct mips_extra_func_info temp_proc_desc
;
1804 /* This hack will go away once the get_prev_frame() code has been
1805 modified to set the frame's type first. That is BEFORE init extra
1806 frame info et.al. is called. This is because it will become
1807 possible to skip the init extra info call for sigtramp and dummy
1809 static CORE_ADDR
*temp_saved_regs
;
1811 /* Set a register's saved stack address in temp_saved_regs. If an
1812 address has already been set for this register, do nothing; this
1813 way we will only recognize the first save of a given register in a
1816 For simplicity, save the address in both [0 .. NUM_REGS) and
1817 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1818 is used as it is only second range (the ABI instead of ISA
1819 registers) that comes into play when finding saved registers in a
1823 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1825 if (saved_regs
[regno
] == 0)
1827 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1828 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1833 /* Test whether the PC points to the return instruction at the
1834 end of a function. */
1837 mips_about_to_return (CORE_ADDR pc
)
1839 if (pc_is_mips16 (pc
))
1840 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1841 generates a "jr $ra"; other times it generates code to load
1842 the return address from the stack to an accessible register (such
1843 as $a3), then a "jr" using that register. This second case
1844 is almost impossible to distinguish from an indirect jump
1845 used for switch statements, so we don't even try. */
1846 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1848 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1852 /* This fencepost looks highly suspicious to me. Removing it also
1853 seems suspicious as it could affect remote debugging across serial
1857 heuristic_proc_start (CORE_ADDR pc
)
1864 pc
= ADDR_BITS_REMOVE (pc
);
1866 fence
= start_pc
- heuristic_fence_post
;
1870 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
1871 fence
= VM_MIN_ADDRESS
;
1873 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1875 /* search back for previous return */
1876 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1877 if (start_pc
< fence
)
1879 /* It's not clear to me why we reach this point when
1880 stop_soon, but with this test, at least we
1881 don't print out warnings for every child forked (eg, on
1882 decstation). 22apr93 rich@cygnus.com. */
1883 if (stop_soon
== NO_STOP_QUIETLY
)
1885 static int blurb_printed
= 0;
1888 ("Warning: GDB can't find the start of the function at 0x%s.",
1893 /* This actually happens frequently in embedded
1894 development, when you first connect to a board
1895 and your stack pointer and pc are nowhere in
1896 particular. This message needs to give people
1897 in that situation enough information to
1898 determine that it's no big deal. */
1899 printf_filtered ("\n\
1900 GDB is unable to find the start of the function at 0x%s\n\
1901 and thus can't determine the size of that function's stack frame.\n\
1902 This means that GDB may be unable to access that stack frame, or\n\
1903 the frames below it.\n\
1904 This problem is most likely caused by an invalid program counter or\n\
1906 However, if you think GDB should simply search farther back\n\
1907 from 0x%s for code which looks like the beginning of a\n\
1908 function, you can increase the range of the search using the `set\n\
1909 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
1916 else if (pc_is_mips16 (start_pc
))
1918 unsigned short inst
;
1920 /* On MIPS16, any one of the following is likely to be the
1921 start of a function:
1925 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1926 inst
= mips_fetch_instruction (start_pc
);
1927 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1928 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1929 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1930 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1932 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1933 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1938 else if (mips_about_to_return (start_pc
))
1940 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1947 /* Fetch the immediate value from a MIPS16 instruction.
1948 If the previous instruction was an EXTEND, use it to extend
1949 the upper bits of the immediate value. This is a helper function
1950 for mips16_heuristic_proc_desc. */
1953 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1954 unsigned short inst
, /* current instruction */
1955 int nbits
, /* number of bits in imm field */
1956 int scale
, /* scale factor to be applied to imm */
1957 int is_signed
) /* is the imm field signed? */
1961 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1963 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1964 if (offset
& 0x8000) /* check for negative extend */
1965 offset
= 0 - (0x10000 - (offset
& 0xffff));
1966 return offset
| (inst
& 0x1f);
1970 int max_imm
= 1 << nbits
;
1971 int mask
= max_imm
- 1;
1972 int sign_bit
= max_imm
>> 1;
1974 offset
= inst
& mask
;
1975 if (is_signed
&& (offset
& sign_bit
))
1976 offset
= 0 - (max_imm
- offset
);
1977 return offset
* scale
;
1982 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1983 stream from start_pc to limit_pc. */
1986 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1987 struct frame_info
*next_frame
, CORE_ADDR sp
)
1990 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1991 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1992 unsigned inst
= 0; /* current instruction */
1993 unsigned entry_inst
= 0; /* the entry instruction */
1995 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1997 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1998 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2000 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2002 /* Save the previous instruction. If it's an EXTEND, we'll extract
2003 the immediate offset extension from it in mips16_get_imm. */
2006 /* Fetch and decode the instruction. */
2007 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2008 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2009 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2011 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2012 if (offset
< 0) /* negative stack adjustment? */
2013 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2015 /* Exit loop if a positive stack adjustment is found, which
2016 usually means that the stack cleanup code in the function
2017 epilogue is reached. */
2020 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2022 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2023 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2024 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2025 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2027 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2029 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2030 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2031 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2032 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2034 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2036 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2037 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2038 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2040 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2042 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2043 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2044 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2046 else if (inst
== 0x673d) /* move $s1, $sp */
2049 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2051 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2053 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2054 frame_addr
= sp
+ offset
;
2055 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2056 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2058 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2060 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2061 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2062 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2063 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2065 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2067 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2068 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2069 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2070 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2072 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2073 entry_inst
= inst
; /* save for later processing */
2074 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2075 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2078 /* The entry instruction is typically the first instruction in a function,
2079 and it stores registers at offsets relative to the value of the old SP
2080 (before the prologue). But the value of the sp parameter to this
2081 function is the new SP (after the prologue has been executed). So we
2082 can't calculate those offsets until we've seen the entire prologue,
2083 and can calculate what the old SP must have been. */
2084 if (entry_inst
!= 0)
2086 int areg_count
= (entry_inst
>> 8) & 7;
2087 int sreg_count
= (entry_inst
>> 6) & 3;
2089 /* The entry instruction always subtracts 32 from the SP. */
2090 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2092 /* Now we can calculate what the SP must have been at the
2093 start of the function prologue. */
2094 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2096 /* Check if a0-a3 were saved in the caller's argument save area. */
2097 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2099 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2100 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2101 offset
+= mips_saved_regsize (tdep
);
2104 /* Check if the ra register was pushed on the stack. */
2106 if (entry_inst
& 0x20)
2108 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2109 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2110 offset
-= mips_saved_regsize (tdep
);
2113 /* Check if the s0 and s1 registers were pushed on the stack. */
2114 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2116 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2117 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2118 offset
-= mips_saved_regsize (tdep
);
2124 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2125 struct frame_info
*next_frame
, CORE_ADDR sp
)
2128 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2130 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2131 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2132 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2133 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2134 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2136 unsigned long inst
, high_word
, low_word
;
2139 /* Fetch the instruction. */
2140 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2142 /* Save some code by pre-extracting some useful fields. */
2143 high_word
= (inst
>> 16) & 0xffff;
2144 low_word
= inst
& 0xffff;
2145 reg
= high_word
& 0x1f;
2147 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2148 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2149 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2151 if (low_word
& 0x8000) /* negative stack adjustment? */
2152 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2154 /* Exit loop if a positive stack adjustment is found, which
2155 usually means that the stack cleanup code in the function
2156 epilogue is reached. */
2159 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2161 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2162 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2164 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2166 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2167 but the register size used is only 32 bits. Make the address
2168 for the saved register point to the lower 32 bits. */
2169 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2170 set_reg_offset (temp_saved_regs
, reg
,
2171 sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2173 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2175 /* Old gcc frame, r30 is virtual frame pointer. */
2176 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2177 frame_addr
= sp
+ low_word
;
2178 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2180 unsigned alloca_adjust
;
2181 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2182 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2183 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2184 if (alloca_adjust
> 0)
2186 /* FP > SP + frame_size. This may be because
2187 * of an alloca or somethings similar.
2188 * Fix sp to "pre-alloca" value, and try again.
2190 sp
+= alloca_adjust
;
2195 /* move $30,$sp. With different versions of gas this will be either
2196 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2197 Accept any one of these. */
2198 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2200 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2201 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2203 unsigned alloca_adjust
;
2204 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2205 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2206 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2207 if (alloca_adjust
> 0)
2209 /* FP > SP + frame_size. This may be because
2210 * of an alloca or somethings similar.
2211 * Fix sp to "pre-alloca" value, and try again.
2213 sp
+= alloca_adjust
;
2218 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2220 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2221 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2226 static mips_extra_func_info_t
2227 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2228 struct frame_info
*next_frame
, int cur_frame
)
2233 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2239 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2240 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2241 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2242 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2243 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2244 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2246 if (start_pc
+ 200 < limit_pc
)
2247 limit_pc
= start_pc
+ 200;
2248 if (pc_is_mips16 (start_pc
))
2249 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2251 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2252 return &temp_proc_desc
;
2255 struct mips_objfile_private
2261 /* Global used to communicate between non_heuristic_proc_desc and
2262 compare_pdr_entries within qsort (). */
2263 static bfd
*the_bfd
;
2266 compare_pdr_entries (const void *a
, const void *b
)
2268 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2269 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2273 else if (lhs
== rhs
)
2279 static mips_extra_func_info_t
2280 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2282 CORE_ADDR startaddr
;
2283 mips_extra_func_info_t proc_desc
;
2284 struct block
*b
= block_for_pc (pc
);
2286 struct obj_section
*sec
;
2287 struct mips_objfile_private
*priv
;
2289 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2292 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2294 *addrptr
= startaddr
;
2298 sec
= find_pc_section (pc
);
2301 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2303 /* Search the ".pdr" section generated by GAS. This includes most of
2304 the information normally found in ECOFF PDRs. */
2306 the_bfd
= sec
->objfile
->obfd
;
2308 && (the_bfd
->format
== bfd_object
2309 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2310 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2312 /* Right now GAS only outputs the address as a four-byte sequence.
2313 This means that we should not bother with this method on 64-bit
2314 targets (until that is fixed). */
2316 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2317 sizeof (struct mips_objfile_private
));
2319 sec
->objfile
->obj_private
= priv
;
2321 else if (priv
== NULL
)
2325 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2326 sizeof (struct mips_objfile_private
));
2328 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2331 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2332 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2334 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2335 priv
->contents
, 0, priv
->size
);
2337 /* In general, the .pdr section is sorted. However, in the
2338 presence of multiple code sections (and other corner cases)
2339 it can become unsorted. Sort it so that we can use a faster
2341 qsort (priv
->contents
, priv
->size
/ 32, 32,
2342 compare_pdr_entries
);
2347 sec
->objfile
->obj_private
= priv
;
2351 if (priv
->size
!= 0)
2357 high
= priv
->size
/ 32;
2363 mid
= (low
+ high
) / 2;
2365 ptr
= priv
->contents
+ mid
* 32;
2366 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2367 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2368 SECT_OFF_TEXT (sec
->objfile
));
2369 if (pdr_pc
== startaddr
)
2371 if (pdr_pc
> startaddr
)
2376 while (low
!= high
);
2380 struct symbol
*sym
= find_pc_function (pc
);
2382 /* Fill in what we need of the proc_desc. */
2383 proc_desc
= (mips_extra_func_info_t
)
2384 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2385 sizeof (struct mips_extra_func_info
));
2386 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2388 /* Only used for dummy frames. */
2389 PROC_HIGH_ADDR (proc_desc
) = 0;
2391 PROC_FRAME_OFFSET (proc_desc
)
2392 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2393 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2395 PROC_FRAME_ADJUST (proc_desc
) = 0;
2396 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2398 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2400 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2402 PROC_FREG_OFFSET (proc_desc
)
2403 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2404 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2406 proc_desc
->pdr
.isym
= (long) sym
;
2416 if (startaddr
> BLOCK_START (b
))
2418 /* This is the "pathological" case referred to in a comment in
2419 print_frame_info. It might be better to move this check into
2424 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2426 /* If we never found a PDR for this function in symbol reading, then
2427 examine prologues to find the information. */
2430 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2431 if (PROC_FRAME_REG (proc_desc
) == -1)
2441 static mips_extra_func_info_t
2442 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2444 mips_extra_func_info_t proc_desc
;
2445 CORE_ADDR startaddr
= 0;
2447 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2451 /* IF this is the topmost frame AND
2452 * (this proc does not have debugging information OR
2453 * the PC is in the procedure prologue)
2454 * THEN create a "heuristic" proc_desc (by analyzing
2455 * the actual code) to replace the "official" proc_desc.
2457 if (next_frame
== NULL
)
2459 struct symtab_and_line val
;
2460 struct symbol
*proc_symbol
=
2461 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2465 val
= find_pc_line (BLOCK_START
2466 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
2467 val
.pc
= val
.end
? val
.end
: pc
;
2469 if (!proc_symbol
|| pc
< val
.pc
)
2471 mips_extra_func_info_t found_heuristic
=
2472 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2473 pc
, next_frame
, cur_frame
);
2474 if (found_heuristic
)
2475 proc_desc
= found_heuristic
;
2481 /* Is linked_proc_desc_table really necessary? It only seems to be used
2482 by procedure call dummys. However, the procedures being called ought
2483 to have their own proc_descs, and even if they don't,
2484 heuristic_proc_desc knows how to create them! */
2486 struct linked_proc_info
*link
;
2488 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2489 if (PROC_LOW_ADDR (&link
->info
) <= pc
2490 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2494 startaddr
= heuristic_proc_start (pc
);
2496 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2501 /* MIPS stack frames are almost impenetrable. When execution stops,
2502 we basically have to look at symbol information for the function
2503 that we stopped in, which tells us *which* register (if any) is
2504 the base of the frame pointer, and what offset from that register
2505 the frame itself is at.
2507 This presents a problem when trying to examine a stack in memory
2508 (that isn't executing at the moment), using the "frame" command. We
2509 don't have a PC, nor do we have any registers except SP.
2511 This routine takes two arguments, SP and PC, and tries to make the
2512 cached frames look as if these two arguments defined a frame on the
2513 cache. This allows the rest of info frame to extract the important
2514 arguments without difficulty. */
2517 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2520 error ("MIPS frame specifications require two arguments: sp and pc");
2522 return create_new_frame (argv
[0], argv
[1]);
2525 /* According to the current ABI, should the type be passed in a
2526 floating-point register (assuming that there is space)? When there
2527 is no FPU, FP are not even considered as possibile candidates for
2528 FP registers and, consequently this returns false - forces FP
2529 arguments into integer registers. */
2532 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2534 return ((typecode
== TYPE_CODE_FLT
2536 && (typecode
== TYPE_CODE_STRUCT
2537 || typecode
== TYPE_CODE_UNION
)
2538 && TYPE_NFIELDS (arg_type
) == 1
2539 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2540 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2543 /* On o32, argument passing in GPRs depends on the alignment of the type being
2544 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2547 mips_type_needs_double_align (struct type
*type
)
2549 enum type_code typecode
= TYPE_CODE (type
);
2551 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2553 else if (typecode
== TYPE_CODE_STRUCT
)
2555 if (TYPE_NFIELDS (type
) < 1)
2557 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2559 else if (typecode
== TYPE_CODE_UNION
)
2563 n
= TYPE_NFIELDS (type
);
2564 for (i
= 0; i
< n
; i
++)
2565 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2572 /* Adjust the address downward (direction of stack growth) so that it
2573 is correctly aligned for a new stack frame. */
2575 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2577 return align_down (addr
, 16);
2580 /* Determine how a return value is stored within the MIPS register
2581 file, given the return type `valtype'. */
2583 struct return_value_word
2592 return_value_location (struct type
*valtype
,
2593 struct return_value_word
*hi
,
2594 struct return_value_word
*lo
)
2596 int len
= TYPE_LENGTH (valtype
);
2597 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2599 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2600 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2601 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2603 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2605 /* We need to break a 64bit float in two 32 bit halves and
2606 spread them across a floating-point register pair. */
2607 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2608 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
2609 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2610 && register_size (current_gdbarch
,
2611 mips_regnum (current_gdbarch
)->
2612 fp0
) == 8) ? 4 : 0);
2613 hi
->reg_offset
= lo
->reg_offset
;
2614 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
2615 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
2621 /* The floating point value fits in a single floating-point
2623 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2624 && register_size (current_gdbarch
,
2625 mips_regnum (current_gdbarch
)->
2627 && len
== 4) ? 4 : 0);
2628 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
2639 /* Locate a result possibly spread across two registers. */
2641 lo
->reg
= regnum
+ 0;
2642 hi
->reg
= regnum
+ 1;
2643 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2644 && len
< mips_saved_regsize (tdep
))
2646 /* "un-left-justify" the value in the low register */
2647 lo
->reg_offset
= mips_saved_regsize (tdep
) - len
;
2652 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_saved_regsize (tdep
) /* odd-size structs */
2653 && len
< mips_saved_regsize (tdep
) * 2
2654 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2655 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2657 /* "un-left-justify" the value spread across two registers. */
2658 lo
->reg_offset
= 2 * mips_saved_regsize (tdep
) - len
;
2659 lo
->len
= mips_saved_regsize (tdep
) - lo
->reg_offset
;
2661 hi
->len
= len
- lo
->len
;
2665 /* Only perform a partial copy of the second register. */
2668 if (len
> mips_saved_regsize (tdep
))
2670 lo
->len
= mips_saved_regsize (tdep
);
2671 hi
->len
= len
- mips_saved_regsize (tdep
);
2679 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2680 && register_size (current_gdbarch
, regnum
) == 8
2681 && mips_saved_regsize (tdep
) == 4)
2683 /* Account for the fact that only the least-signficant part
2684 of the register is being used */
2685 lo
->reg_offset
+= 4;
2686 hi
->reg_offset
+= 4;
2689 hi
->buf_offset
= lo
->len
;
2693 /* Should call_function allocate stack space for a struct return? */
2696 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
2698 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2699 return (TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
));
2702 /* Should call_function pass struct by reference?
2703 For each architecture, structs are passed either by
2704 value or by reference, depending on their size. */
2707 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2709 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
2710 int len
= TYPE_LENGTH (check_typedef (type
));
2711 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2713 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2714 return (len
> mips_saved_regsize (tdep
));
2720 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2721 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2722 int nargs
, struct value
**args
, CORE_ADDR sp
,
2723 int struct_return
, CORE_ADDR struct_addr
)
2729 int stack_offset
= 0;
2730 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2732 /* For shared libraries, "t9" needs to point at the function
2734 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2736 /* Set the return address register to point to the entry point of
2737 the program, where a breakpoint lies in wait. */
2738 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2740 /* First ensure that the stack and structure return address (if any)
2741 are properly aligned. The stack has to be at least 64-bit
2742 aligned even on 32-bit machines, because doubles must be 64-bit
2743 aligned. For n32 and n64, stack frames need to be 128-bit
2744 aligned, so we round to this widest known alignment. */
2746 sp
= align_down (sp
, 16);
2747 struct_addr
= align_down (struct_addr
, 16);
2749 /* Now make space on the stack for the args. We allocate more
2750 than necessary for EABI, because the first few arguments are
2751 passed in registers, but that's OK. */
2752 for (argnum
= 0; argnum
< nargs
; argnum
++)
2753 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2754 mips_stack_argsize (tdep
));
2755 sp
-= align_up (len
, 16);
2758 fprintf_unfiltered (gdb_stdlog
,
2759 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2760 paddr_nz (sp
), (long) align_up (len
, 16));
2762 /* Initialize the integer and float register pointers. */
2764 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2766 /* The struct_return pointer occupies the first parameter-passing reg. */
2770 fprintf_unfiltered (gdb_stdlog
,
2771 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2772 argreg
, paddr_nz (struct_addr
));
2773 write_register (argreg
++, struct_addr
);
2776 /* Now load as many as possible of the first arguments into
2777 registers, and push the rest onto the stack. Loop thru args
2778 from first to last. */
2779 for (argnum
= 0; argnum
< nargs
; argnum
++)
2782 char valbuf
[MAX_REGISTER_SIZE
];
2783 struct value
*arg
= args
[argnum
];
2784 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2785 int len
= TYPE_LENGTH (arg_type
);
2786 enum type_code typecode
= TYPE_CODE (arg_type
);
2789 fprintf_unfiltered (gdb_stdlog
,
2790 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2791 argnum
+ 1, len
, (int) typecode
);
2793 /* The EABI passes structures that do not fit in a register by
2795 if (len
> mips_saved_regsize (tdep
)
2796 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2798 store_unsigned_integer (valbuf
, mips_saved_regsize (tdep
),
2799 VALUE_ADDRESS (arg
));
2800 typecode
= TYPE_CODE_PTR
;
2801 len
= mips_saved_regsize (tdep
);
2804 fprintf_unfiltered (gdb_stdlog
, " push");
2807 val
= (char *) VALUE_CONTENTS (arg
);
2809 /* 32-bit ABIs always start floating point arguments in an
2810 even-numbered floating point register. Round the FP register
2811 up before the check to see if there are any FP registers
2812 left. Non MIPS_EABI targets also pass the FP in the integer
2813 registers so also round up normal registers. */
2814 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
2816 if ((float_argreg
& 1))
2820 /* Floating point arguments passed in registers have to be
2821 treated specially. On 32-bit architectures, doubles
2822 are passed in register pairs; the even register gets
2823 the low word, and the odd register gets the high word.
2824 On non-EABI processors, the first two floating point arguments are
2825 also copied to general registers, because MIPS16 functions
2826 don't use float registers for arguments. This duplication of
2827 arguments in general registers can't hurt non-MIPS16 functions
2828 because those registers are normally skipped. */
2829 /* MIPS_EABI squeezes a struct that contains a single floating
2830 point value into an FP register instead of pushing it onto the
2832 if (fp_register_arg_p (typecode
, arg_type
)
2833 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2835 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2837 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2838 unsigned long regval
;
2840 /* Write the low word of the double to the even register(s). */
2841 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2843 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2844 float_argreg
, phex (regval
, 4));
2845 write_register (float_argreg
++, regval
);
2847 /* Write the high word of the double to the odd register(s). */
2848 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2850 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2851 float_argreg
, phex (regval
, 4));
2852 write_register (float_argreg
++, regval
);
2856 /* This is a floating point value that fits entirely
2857 in a single register. */
2858 /* On 32 bit ABI's the float_argreg is further adjusted
2859 above to ensure that it is even register aligned. */
2860 LONGEST regval
= extract_unsigned_integer (val
, len
);
2862 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2863 float_argreg
, phex (regval
, len
));
2864 write_register (float_argreg
++, regval
);
2869 /* Copy the argument to general registers or the stack in
2870 register-sized pieces. Large arguments are split between
2871 registers and stack. */
2872 /* Note: structs whose size is not a multiple of
2873 mips_regsize() are treated specially: Irix cc passes them
2874 in registers where gcc sometimes puts them on the stack.
2875 For maximum compatibility, we will put them in both
2877 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
2878 && (len
% mips_saved_regsize (tdep
) != 0));
2880 /* Note: Floating-point values that didn't fit into an FP
2881 register are only written to memory. */
2884 /* Remember if the argument was written to the stack. */
2885 int stack_used_p
= 0;
2886 int partial_len
= (len
< mips_saved_regsize (tdep
)
2887 ? len
: mips_saved_regsize (tdep
));
2890 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2893 /* Write this portion of the argument to the stack. */
2894 if (argreg
> MIPS_LAST_ARG_REGNUM
2896 || fp_register_arg_p (typecode
, arg_type
))
2898 /* Should shorter than int integer values be
2899 promoted to int before being stored? */
2900 int longword_offset
= 0;
2903 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2905 if (mips_stack_argsize (tdep
) == 8
2906 && (typecode
== TYPE_CODE_INT
2907 || typecode
== TYPE_CODE_PTR
2908 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2909 longword_offset
= mips_stack_argsize (tdep
) - len
;
2910 else if ((typecode
== TYPE_CODE_STRUCT
2911 || typecode
== TYPE_CODE_UNION
)
2912 && (TYPE_LENGTH (arg_type
)
2913 < mips_stack_argsize (tdep
)))
2914 longword_offset
= mips_stack_argsize (tdep
) - len
;
2919 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2920 paddr_nz (stack_offset
));
2921 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2922 paddr_nz (longword_offset
));
2925 addr
= sp
+ stack_offset
+ longword_offset
;
2930 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2932 for (i
= 0; i
< partial_len
; i
++)
2934 fprintf_unfiltered (gdb_stdlog
, "%02x",
2938 write_memory (addr
, val
, partial_len
);
2941 /* Note!!! This is NOT an else clause. Odd sized
2942 structs may go thru BOTH paths. Floating point
2943 arguments will not. */
2944 /* Write this portion of the argument to a general
2945 purpose register. */
2946 if (argreg
<= MIPS_LAST_ARG_REGNUM
2947 && !fp_register_arg_p (typecode
, arg_type
))
2950 extract_unsigned_integer (val
, partial_len
);
2953 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2956 mips_saved_regsize (tdep
)));
2957 write_register (argreg
, regval
);
2964 /* Compute the the offset into the stack at which we
2965 will copy the next parameter.
2967 In the new EABI (and the NABI32), the stack_offset
2968 only needs to be adjusted when it has been used. */
2971 stack_offset
+= align_up (partial_len
,
2972 mips_stack_argsize (tdep
));
2976 fprintf_unfiltered (gdb_stdlog
, "\n");
2979 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
2981 /* Return adjusted stack pointer. */
2985 /* Given a return value in `regbuf' with a type `valtype', extract and
2986 copy its value into `valbuf'. */
2989 mips_eabi_extract_return_value (struct type
*valtype
,
2990 char regbuf
[], char *valbuf
)
2992 struct return_value_word lo
;
2993 struct return_value_word hi
;
2994 return_value_location (valtype
, &hi
, &lo
);
2996 memcpy (valbuf
+ lo
.buf_offset
,
2997 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
2998 lo
.reg_offset
, lo
.len
);
3001 memcpy (valbuf
+ hi
.buf_offset
,
3002 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3003 hi
.reg_offset
, hi
.len
);
3006 /* Given a return value in `valbuf' with a type `valtype', write it's
3007 value into the appropriate register. */
3010 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3012 char raw_buffer
[MAX_REGISTER_SIZE
];
3013 struct return_value_word lo
;
3014 struct return_value_word hi
;
3015 return_value_location (valtype
, &hi
, &lo
);
3017 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3018 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3019 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3020 raw_buffer
, register_size (current_gdbarch
,
3025 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3026 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3027 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3029 register_size (current_gdbarch
,
3034 /* N32/N64 ABI stuff. */
3037 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3038 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3039 int nargs
, struct value
**args
, CORE_ADDR sp
,
3040 int struct_return
, CORE_ADDR struct_addr
)
3046 int stack_offset
= 0;
3047 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3049 /* For shared libraries, "t9" needs to point at the function
3051 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3053 /* Set the return address register to point to the entry point of
3054 the program, where a breakpoint lies in wait. */
3055 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3057 /* First ensure that the stack and structure return address (if any)
3058 are properly aligned. The stack has to be at least 64-bit
3059 aligned even on 32-bit machines, because doubles must be 64-bit
3060 aligned. For n32 and n64, stack frames need to be 128-bit
3061 aligned, so we round to this widest known alignment. */
3063 sp
= align_down (sp
, 16);
3064 struct_addr
= align_down (struct_addr
, 16);
3066 /* Now make space on the stack for the args. */
3067 for (argnum
= 0; argnum
< nargs
; argnum
++)
3068 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3069 mips_stack_argsize (tdep
));
3070 sp
-= align_up (len
, 16);
3073 fprintf_unfiltered (gdb_stdlog
,
3074 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3075 paddr_nz (sp
), (long) align_up (len
, 16));
3077 /* Initialize the integer and float register pointers. */
3079 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3081 /* The struct_return pointer occupies the first parameter-passing reg. */
3085 fprintf_unfiltered (gdb_stdlog
,
3086 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3087 argreg
, paddr_nz (struct_addr
));
3088 write_register (argreg
++, struct_addr
);
3091 /* Now load as many as possible of the first arguments into
3092 registers, and push the rest onto the stack. Loop thru args
3093 from first to last. */
3094 for (argnum
= 0; argnum
< nargs
; argnum
++)
3097 struct value
*arg
= args
[argnum
];
3098 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3099 int len
= TYPE_LENGTH (arg_type
);
3100 enum type_code typecode
= TYPE_CODE (arg_type
);
3103 fprintf_unfiltered (gdb_stdlog
,
3104 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3105 argnum
+ 1, len
, (int) typecode
);
3107 val
= (char *) VALUE_CONTENTS (arg
);
3109 if (fp_register_arg_p (typecode
, arg_type
)
3110 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3112 /* This is a floating point value that fits entirely
3113 in a single register. */
3114 /* On 32 bit ABI's the float_argreg is further adjusted
3115 above to ensure that it is even register aligned. */
3116 LONGEST regval
= extract_unsigned_integer (val
, len
);
3118 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3119 float_argreg
, phex (regval
, len
));
3120 write_register (float_argreg
++, regval
);
3123 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3124 argreg
, phex (regval
, len
));
3125 write_register (argreg
, regval
);
3130 /* Copy the argument to general registers or the stack in
3131 register-sized pieces. Large arguments are split between
3132 registers and stack. */
3133 /* Note: structs whose size is not a multiple of
3134 mips_regsize() are treated specially: Irix cc passes them
3135 in registers where gcc sometimes puts them on the stack.
3136 For maximum compatibility, we will put them in both
3138 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3139 && (len
% mips_saved_regsize (tdep
) != 0));
3140 /* Note: Floating-point values that didn't fit into an FP
3141 register are only written to memory. */
3144 /* Rememer if the argument was written to the stack. */
3145 int stack_used_p
= 0;
3146 int partial_len
= (len
< mips_saved_regsize (tdep
)
3147 ? len
: mips_saved_regsize (tdep
));
3150 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3153 /* Write this portion of the argument to the stack. */
3154 if (argreg
> MIPS_LAST_ARG_REGNUM
3156 || fp_register_arg_p (typecode
, arg_type
))
3158 /* Should shorter than int integer values be
3159 promoted to int before being stored? */
3160 int longword_offset
= 0;
3163 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3165 if (mips_stack_argsize (tdep
) == 8
3166 && (typecode
== TYPE_CODE_INT
3167 || typecode
== TYPE_CODE_PTR
3168 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3169 longword_offset
= mips_stack_argsize (tdep
) - len
;
3174 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3175 paddr_nz (stack_offset
));
3176 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3177 paddr_nz (longword_offset
));
3180 addr
= sp
+ stack_offset
+ longword_offset
;
3185 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3187 for (i
= 0; i
< partial_len
; i
++)
3189 fprintf_unfiltered (gdb_stdlog
, "%02x",
3193 write_memory (addr
, val
, partial_len
);
3196 /* Note!!! This is NOT an else clause. Odd sized
3197 structs may go thru BOTH paths. Floating point
3198 arguments will not. */
3199 /* Write this portion of the argument to a general
3200 purpose register. */
3201 if (argreg
<= MIPS_LAST_ARG_REGNUM
3202 && !fp_register_arg_p (typecode
, arg_type
))
3205 extract_unsigned_integer (val
, partial_len
);
3207 /* A non-floating-point argument being passed in a
3208 general register. If a struct or union, and if
3209 the remaining length is smaller than the register
3210 size, we have to adjust the register value on
3213 It does not seem to be necessary to do the
3214 same for integral types.
3216 cagney/2001-07-23: gdb/179: Also, GCC, when
3217 outputting LE O32 with sizeof (struct) <
3218 mips_saved_regsize(), generates a left shift as
3219 part of storing the argument in a register a
3220 register (the left shift isn't generated when
3221 sizeof (struct) >= mips_saved_regsize()). Since
3222 it is quite possible that this is GCC
3223 contradicting the LE/O32 ABI, GDB has not been
3224 adjusted to accommodate this. Either someone
3225 needs to demonstrate that the LE/O32 ABI
3226 specifies such a left shift OR this new ABI gets
3227 identified as such and GDB gets tweaked
3230 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3231 && partial_len
< mips_saved_regsize (tdep
)
3232 && (typecode
== TYPE_CODE_STRUCT
||
3233 typecode
== TYPE_CODE_UNION
))
3234 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3238 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3241 mips_saved_regsize (tdep
)));
3242 write_register (argreg
, regval
);
3249 /* Compute the the offset into the stack at which we
3250 will copy the next parameter.
3252 In N32 (N64?), the stack_offset only needs to be
3253 adjusted when it has been used. */
3256 stack_offset
+= align_up (partial_len
,
3257 mips_stack_argsize (tdep
));
3261 fprintf_unfiltered (gdb_stdlog
, "\n");
3264 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3266 /* Return adjusted stack pointer. */
3270 static enum return_value_convention
3271 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3272 struct type
*type
, struct regcache
*regcache
,
3273 void *readbuf
, const void *writebuf
)
3275 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3276 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3277 || TYPE_CODE (type
) == TYPE_CODE_UNION
3278 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3279 || TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
))
3280 return RETURN_VALUE_STRUCT_CONVENTION
;
3281 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3282 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3284 /* A floating-point value belongs in the least significant part
3287 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3288 mips_xfer_register (regcache
,
3289 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3291 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3292 return RETURN_VALUE_REGISTER_CONVENTION
;
3294 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3295 && TYPE_NFIELDS (type
) <= 2
3296 && TYPE_NFIELDS (type
) >= 1
3297 && ((TYPE_NFIELDS (type
) == 1
3298 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3300 || (TYPE_NFIELDS (type
) == 2
3301 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3303 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3305 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3307 /* A struct that contains one or two floats. Each value is part
3308 in the least significant part of their floating point
3312 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3313 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3315 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3318 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3320 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3321 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3322 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3324 return RETURN_VALUE_REGISTER_CONVENTION
;
3326 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3327 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3329 /* A structure or union. Extract the left justified value,
3330 regardless of the byte order. I.e. DO NOT USE
3334 for (offset
= 0, regnum
= V0_REGNUM
;
3335 offset
< TYPE_LENGTH (type
);
3336 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3338 int xfer
= register_size (current_gdbarch
, regnum
);
3339 if (offset
+ xfer
> TYPE_LENGTH (type
))
3340 xfer
= TYPE_LENGTH (type
) - offset
;
3342 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3343 offset
, xfer
, regnum
);
3344 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3345 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3347 return RETURN_VALUE_REGISTER_CONVENTION
;
3351 /* A scalar extract each part but least-significant-byte
3355 for (offset
= 0, regnum
= V0_REGNUM
;
3356 offset
< TYPE_LENGTH (type
);
3357 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3359 int xfer
= register_size (current_gdbarch
, regnum
);
3360 if (offset
+ xfer
> TYPE_LENGTH (type
))
3361 xfer
= TYPE_LENGTH (type
) - offset
;
3363 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3364 offset
, xfer
, regnum
);
3365 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3366 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3368 return RETURN_VALUE_REGISTER_CONVENTION
;
3372 /* O32 ABI stuff. */
3375 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3376 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3377 int nargs
, struct value
**args
, CORE_ADDR sp
,
3378 int struct_return
, CORE_ADDR struct_addr
)
3384 int stack_offset
= 0;
3385 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3387 /* For shared libraries, "t9" needs to point at the function
3389 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3391 /* Set the return address register to point to the entry point of
3392 the program, where a breakpoint lies in wait. */
3393 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3395 /* First ensure that the stack and structure return address (if any)
3396 are properly aligned. The stack has to be at least 64-bit
3397 aligned even on 32-bit machines, because doubles must be 64-bit
3398 aligned. For n32 and n64, stack frames need to be 128-bit
3399 aligned, so we round to this widest known alignment. */
3401 sp
= align_down (sp
, 16);
3402 struct_addr
= align_down (struct_addr
, 16);
3404 /* Now make space on the stack for the args. */
3405 for (argnum
= 0; argnum
< nargs
; argnum
++)
3406 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3407 mips_stack_argsize (tdep
));
3408 sp
-= align_up (len
, 16);
3411 fprintf_unfiltered (gdb_stdlog
,
3412 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3413 paddr_nz (sp
), (long) align_up (len
, 16));
3415 /* Initialize the integer and float register pointers. */
3417 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3419 /* The struct_return pointer occupies the first parameter-passing reg. */
3423 fprintf_unfiltered (gdb_stdlog
,
3424 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3425 argreg
, paddr_nz (struct_addr
));
3426 write_register (argreg
++, struct_addr
);
3427 stack_offset
+= mips_stack_argsize (tdep
);
3430 /* Now load as many as possible of the first arguments into
3431 registers, and push the rest onto the stack. Loop thru args
3432 from first to last. */
3433 for (argnum
= 0; argnum
< nargs
; argnum
++)
3436 struct value
*arg
= args
[argnum
];
3437 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3438 int len
= TYPE_LENGTH (arg_type
);
3439 enum type_code typecode
= TYPE_CODE (arg_type
);
3442 fprintf_unfiltered (gdb_stdlog
,
3443 "mips_o32_push_dummy_call: %d len=%d type=%d",
3444 argnum
+ 1, len
, (int) typecode
);
3446 val
= (char *) VALUE_CONTENTS (arg
);
3448 /* 32-bit ABIs always start floating point arguments in an
3449 even-numbered floating point register. Round the FP register
3450 up before the check to see if there are any FP registers
3451 left. O32/O64 targets also pass the FP in the integer
3452 registers so also round up normal registers. */
3453 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3455 if ((float_argreg
& 1))
3459 /* Floating point arguments passed in registers have to be
3460 treated specially. On 32-bit architectures, doubles
3461 are passed in register pairs; the even register gets
3462 the low word, and the odd register gets the high word.
3463 On O32/O64, the first two floating point arguments are
3464 also copied to general registers, because MIPS16 functions
3465 don't use float registers for arguments. This duplication of
3466 arguments in general registers can't hurt non-MIPS16 functions
3467 because those registers are normally skipped. */
3469 if (fp_register_arg_p (typecode
, arg_type
)
3470 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3472 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3474 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3475 unsigned long regval
;
3477 /* Write the low word of the double to the even register(s). */
3478 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3480 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3481 float_argreg
, phex (regval
, 4));
3482 write_register (float_argreg
++, regval
);
3484 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3485 argreg
, phex (regval
, 4));
3486 write_register (argreg
++, regval
);
3488 /* Write the high word of the double to the odd register(s). */
3489 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3491 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3492 float_argreg
, phex (regval
, 4));
3493 write_register (float_argreg
++, regval
);
3496 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3497 argreg
, phex (regval
, 4));
3498 write_register (argreg
++, regval
);
3502 /* This is a floating point value that fits entirely
3503 in a single register. */
3504 /* On 32 bit ABI's the float_argreg is further adjusted
3505 above to ensure that it is even register aligned. */
3506 LONGEST regval
= extract_unsigned_integer (val
, len
);
3508 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3509 float_argreg
, phex (regval
, len
));
3510 write_register (float_argreg
++, regval
);
3511 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3512 registers for each argument. The below is (my
3513 guess) to ensure that the corresponding integer
3514 register has reserved the same space. */
3516 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3517 argreg
, phex (regval
, len
));
3518 write_register (argreg
, regval
);
3519 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3521 /* Reserve space for the FP register. */
3522 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3526 /* Copy the argument to general registers or the stack in
3527 register-sized pieces. Large arguments are split between
3528 registers and stack. */
3529 /* Note: structs whose size is not a multiple of
3530 mips_regsize() are treated specially: Irix cc passes them
3531 in registers where gcc sometimes puts them on the stack.
3532 For maximum compatibility, we will put them in both
3534 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3535 && (len
% mips_saved_regsize (tdep
) != 0));
3536 /* Structures should be aligned to eight bytes (even arg registers)
3537 on MIPS_ABI_O32, if their first member has double precision. */
3538 if (mips_saved_regsize (tdep
) < 8
3539 && mips_type_needs_double_align (arg_type
))
3544 /* Note: Floating-point values that didn't fit into an FP
3545 register are only written to memory. */
3548 /* Remember if the argument was written to the stack. */
3549 int stack_used_p
= 0;
3550 int partial_len
= (len
< mips_saved_regsize (tdep
)
3551 ? len
: mips_saved_regsize (tdep
));
3554 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3557 /* Write this portion of the argument to the stack. */
3558 if (argreg
> MIPS_LAST_ARG_REGNUM
3560 || fp_register_arg_p (typecode
, arg_type
))
3562 /* Should shorter than int integer values be
3563 promoted to int before being stored? */
3564 int longword_offset
= 0;
3567 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3569 if (mips_stack_argsize (tdep
) == 8
3570 && (typecode
== TYPE_CODE_INT
3571 || typecode
== TYPE_CODE_PTR
3572 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3573 longword_offset
= mips_stack_argsize (tdep
) - len
;
3578 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3579 paddr_nz (stack_offset
));
3580 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3581 paddr_nz (longword_offset
));
3584 addr
= sp
+ stack_offset
+ longword_offset
;
3589 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3591 for (i
= 0; i
< partial_len
; i
++)
3593 fprintf_unfiltered (gdb_stdlog
, "%02x",
3597 write_memory (addr
, val
, partial_len
);
3600 /* Note!!! This is NOT an else clause. Odd sized
3601 structs may go thru BOTH paths. Floating point
3602 arguments will not. */
3603 /* Write this portion of the argument to a general
3604 purpose register. */
3605 if (argreg
<= MIPS_LAST_ARG_REGNUM
3606 && !fp_register_arg_p (typecode
, arg_type
))
3608 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3609 /* Value may need to be sign extended, because
3610 mips_regsize() != mips_saved_regsize(). */
3612 /* A non-floating-point argument being passed in a
3613 general register. If a struct or union, and if
3614 the remaining length is smaller than the register
3615 size, we have to adjust the register value on
3618 It does not seem to be necessary to do the
3619 same for integral types.
3621 Also don't do this adjustment on O64 binaries.
3623 cagney/2001-07-23: gdb/179: Also, GCC, when
3624 outputting LE O32 with sizeof (struct) <
3625 mips_saved_regsize(), generates a left shift as
3626 part of storing the argument in a register a
3627 register (the left shift isn't generated when
3628 sizeof (struct) >= mips_saved_regsize()). Since
3629 it is quite possible that this is GCC
3630 contradicting the LE/O32 ABI, GDB has not been
3631 adjusted to accommodate this. Either someone
3632 needs to demonstrate that the LE/O32 ABI
3633 specifies such a left shift OR this new ABI gets
3634 identified as such and GDB gets tweaked
3637 if (mips_saved_regsize (tdep
) < 8
3638 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3639 && partial_len
< mips_saved_regsize (tdep
)
3640 && (typecode
== TYPE_CODE_STRUCT
||
3641 typecode
== TYPE_CODE_UNION
))
3642 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3646 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3649 mips_saved_regsize (tdep
)));
3650 write_register (argreg
, regval
);
3653 /* Prevent subsequent floating point arguments from
3654 being passed in floating point registers. */
3655 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3661 /* Compute the the offset into the stack at which we
3662 will copy the next parameter.
3664 In older ABIs, the caller reserved space for
3665 registers that contained arguments. This was loosely
3666 refered to as their "home". Consequently, space is
3667 always allocated. */
3669 stack_offset
+= align_up (partial_len
,
3670 mips_stack_argsize (tdep
));
3674 fprintf_unfiltered (gdb_stdlog
, "\n");
3677 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3679 /* Return adjusted stack pointer. */
3683 static enum return_value_convention
3684 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3685 struct regcache
*regcache
,
3686 void *readbuf
, const void *writebuf
)
3688 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3690 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3691 || TYPE_CODE (type
) == TYPE_CODE_UNION
3692 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3693 return RETURN_VALUE_STRUCT_CONVENTION
;
3694 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3695 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3697 /* A single-precision floating-point value. It fits in the
3698 least significant part of FP0. */
3700 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3701 mips_xfer_register (regcache
,
3702 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3704 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3705 return RETURN_VALUE_REGISTER_CONVENTION
;
3707 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3708 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3710 /* A double-precision floating-point value. The most
3711 significant part goes in FP1, and the least significant in
3714 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3715 switch (TARGET_BYTE_ORDER
)
3717 case BFD_ENDIAN_LITTLE
:
3718 mips_xfer_register (regcache
,
3719 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3720 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3721 mips_xfer_register (regcache
,
3722 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3723 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3725 case BFD_ENDIAN_BIG
:
3726 mips_xfer_register (regcache
,
3727 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3728 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3729 mips_xfer_register (regcache
,
3730 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3731 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3734 internal_error (__FILE__
, __LINE__
, "bad switch");
3736 return RETURN_VALUE_REGISTER_CONVENTION
;
3739 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3740 && TYPE_NFIELDS (type
) <= 2
3741 && TYPE_NFIELDS (type
) >= 1
3742 && ((TYPE_NFIELDS (type
) == 1
3743 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3745 || (TYPE_NFIELDS (type
) == 2
3746 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3748 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3750 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3752 /* A struct that contains one or two floats. Each value is part
3753 in the least significant part of their floating point
3755 bfd_byte reg
[MAX_REGISTER_SIZE
];
3758 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3759 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3761 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3764 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3766 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3767 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3768 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3770 return RETURN_VALUE_REGISTER_CONVENTION
;
3774 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3775 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3777 /* A structure or union. Extract the left justified value,
3778 regardless of the byte order. I.e. DO NOT USE
3782 for (offset
= 0, regnum
= V0_REGNUM
;
3783 offset
< TYPE_LENGTH (type
);
3784 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3786 int xfer
= register_size (current_gdbarch
, regnum
);
3787 if (offset
+ xfer
> TYPE_LENGTH (type
))
3788 xfer
= TYPE_LENGTH (type
) - offset
;
3790 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3791 offset
, xfer
, regnum
);
3792 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3793 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3795 return RETURN_VALUE_REGISTER_CONVENTION
;
3800 /* A scalar extract each part but least-significant-byte
3801 justified. o32 thinks registers are 4 byte, regardless of
3802 the ISA. mips_stack_argsize controls this. */
3805 for (offset
= 0, regnum
= V0_REGNUM
;
3806 offset
< TYPE_LENGTH (type
);
3807 offset
+= mips_stack_argsize (tdep
), regnum
++)
3809 int xfer
= mips_stack_argsize (tdep
);
3810 if (offset
+ xfer
> TYPE_LENGTH (type
))
3811 xfer
= TYPE_LENGTH (type
) - offset
;
3813 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3814 offset
, xfer
, regnum
);
3815 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3816 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3818 return RETURN_VALUE_REGISTER_CONVENTION
;
3822 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3826 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3827 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3829 struct value
**args
, CORE_ADDR sp
,
3830 int struct_return
, CORE_ADDR struct_addr
)
3836 int stack_offset
= 0;
3837 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3839 /* For shared libraries, "t9" needs to point at the function
3841 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3843 /* Set the return address register to point to the entry point of
3844 the program, where a breakpoint lies in wait. */
3845 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3847 /* First ensure that the stack and structure return address (if any)
3848 are properly aligned. The stack has to be at least 64-bit
3849 aligned even on 32-bit machines, because doubles must be 64-bit
3850 aligned. For n32 and n64, stack frames need to be 128-bit
3851 aligned, so we round to this widest known alignment. */
3853 sp
= align_down (sp
, 16);
3854 struct_addr
= align_down (struct_addr
, 16);
3856 /* Now make space on the stack for the args. */
3857 for (argnum
= 0; argnum
< nargs
; argnum
++)
3858 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3859 mips_stack_argsize (tdep
));
3860 sp
-= align_up (len
, 16);
3863 fprintf_unfiltered (gdb_stdlog
,
3864 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3865 paddr_nz (sp
), (long) align_up (len
, 16));
3867 /* Initialize the integer and float register pointers. */
3869 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3871 /* The struct_return pointer occupies the first parameter-passing reg. */
3875 fprintf_unfiltered (gdb_stdlog
,
3876 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3877 argreg
, paddr_nz (struct_addr
));
3878 write_register (argreg
++, struct_addr
);
3879 stack_offset
+= mips_stack_argsize (tdep
);
3882 /* Now load as many as possible of the first arguments into
3883 registers, and push the rest onto the stack. Loop thru args
3884 from first to last. */
3885 for (argnum
= 0; argnum
< nargs
; argnum
++)
3888 struct value
*arg
= args
[argnum
];
3889 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3890 int len
= TYPE_LENGTH (arg_type
);
3891 enum type_code typecode
= TYPE_CODE (arg_type
);
3894 fprintf_unfiltered (gdb_stdlog
,
3895 "mips_o64_push_dummy_call: %d len=%d type=%d",
3896 argnum
+ 1, len
, (int) typecode
);
3898 val
= (char *) VALUE_CONTENTS (arg
);
3900 /* 32-bit ABIs always start floating point arguments in an
3901 even-numbered floating point register. Round the FP register
3902 up before the check to see if there are any FP registers
3903 left. O32/O64 targets also pass the FP in the integer
3904 registers so also round up normal registers. */
3905 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3907 if ((float_argreg
& 1))
3911 /* Floating point arguments passed in registers have to be
3912 treated specially. On 32-bit architectures, doubles
3913 are passed in register pairs; the even register gets
3914 the low word, and the odd register gets the high word.
3915 On O32/O64, the first two floating point arguments are
3916 also copied to general registers, because MIPS16 functions
3917 don't use float registers for arguments. This duplication of
3918 arguments in general registers can't hurt non-MIPS16 functions
3919 because those registers are normally skipped. */
3921 if (fp_register_arg_p (typecode
, arg_type
)
3922 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3924 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3926 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3927 unsigned long regval
;
3929 /* Write the low word of the double to the even register(s). */
3930 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3932 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3933 float_argreg
, phex (regval
, 4));
3934 write_register (float_argreg
++, regval
);
3936 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3937 argreg
, phex (regval
, 4));
3938 write_register (argreg
++, regval
);
3940 /* Write the high word of the double to the odd register(s). */
3941 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3943 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3944 float_argreg
, phex (regval
, 4));
3945 write_register (float_argreg
++, regval
);
3948 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3949 argreg
, phex (regval
, 4));
3950 write_register (argreg
++, regval
);
3954 /* This is a floating point value that fits entirely
3955 in a single register. */
3956 /* On 32 bit ABI's the float_argreg is further adjusted
3957 above to ensure that it is even register aligned. */
3958 LONGEST regval
= extract_unsigned_integer (val
, len
);
3960 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3961 float_argreg
, phex (regval
, len
));
3962 write_register (float_argreg
++, regval
);
3963 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3964 registers for each argument. The below is (my
3965 guess) to ensure that the corresponding integer
3966 register has reserved the same space. */
3968 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3969 argreg
, phex (regval
, len
));
3970 write_register (argreg
, regval
);
3971 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3973 /* Reserve space for the FP register. */
3974 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3978 /* Copy the argument to general registers or the stack in
3979 register-sized pieces. Large arguments are split between
3980 registers and stack. */
3981 /* Note: structs whose size is not a multiple of
3982 mips_regsize() are treated specially: Irix cc passes them
3983 in registers where gcc sometimes puts them on the stack.
3984 For maximum compatibility, we will put them in both
3986 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3987 && (len
% mips_saved_regsize (tdep
) != 0));
3988 /* Structures should be aligned to eight bytes (even arg registers)
3989 on MIPS_ABI_O32, if their first member has double precision. */
3990 if (mips_saved_regsize (tdep
) < 8
3991 && mips_type_needs_double_align (arg_type
))
3996 /* Note: Floating-point values that didn't fit into an FP
3997 register are only written to memory. */
4000 /* Remember if the argument was written to the stack. */
4001 int stack_used_p
= 0;
4002 int partial_len
= (len
< mips_saved_regsize (tdep
)
4003 ? len
: mips_saved_regsize (tdep
));
4006 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4009 /* Write this portion of the argument to the stack. */
4010 if (argreg
> MIPS_LAST_ARG_REGNUM
4012 || fp_register_arg_p (typecode
, arg_type
))
4014 /* Should shorter than int integer values be
4015 promoted to int before being stored? */
4016 int longword_offset
= 0;
4019 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4021 if (mips_stack_argsize (tdep
) == 8
4022 && (typecode
== TYPE_CODE_INT
4023 || typecode
== TYPE_CODE_PTR
4024 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4025 longword_offset
= mips_stack_argsize (tdep
) - len
;
4030 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4031 paddr_nz (stack_offset
));
4032 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4033 paddr_nz (longword_offset
));
4036 addr
= sp
+ stack_offset
+ longword_offset
;
4041 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4043 for (i
= 0; i
< partial_len
; i
++)
4045 fprintf_unfiltered (gdb_stdlog
, "%02x",
4049 write_memory (addr
, val
, partial_len
);
4052 /* Note!!! This is NOT an else clause. Odd sized
4053 structs may go thru BOTH paths. Floating point
4054 arguments will not. */
4055 /* Write this portion of the argument to a general
4056 purpose register. */
4057 if (argreg
<= MIPS_LAST_ARG_REGNUM
4058 && !fp_register_arg_p (typecode
, arg_type
))
4060 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4061 /* Value may need to be sign extended, because
4062 mips_regsize() != mips_saved_regsize(). */
4064 /* A non-floating-point argument being passed in a
4065 general register. If a struct or union, and if
4066 the remaining length is smaller than the register
4067 size, we have to adjust the register value on
4070 It does not seem to be necessary to do the
4071 same for integral types.
4073 Also don't do this adjustment on O64 binaries.
4075 cagney/2001-07-23: gdb/179: Also, GCC, when
4076 outputting LE O32 with sizeof (struct) <
4077 mips_saved_regsize(), generates a left shift as
4078 part of storing the argument in a register a
4079 register (the left shift isn't generated when
4080 sizeof (struct) >= mips_saved_regsize()). Since
4081 it is quite possible that this is GCC
4082 contradicting the LE/O32 ABI, GDB has not been
4083 adjusted to accommodate this. Either someone
4084 needs to demonstrate that the LE/O32 ABI
4085 specifies such a left shift OR this new ABI gets
4086 identified as such and GDB gets tweaked
4089 if (mips_saved_regsize (tdep
) < 8
4090 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4091 && partial_len
< mips_saved_regsize (tdep
)
4092 && (typecode
== TYPE_CODE_STRUCT
||
4093 typecode
== TYPE_CODE_UNION
))
4094 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
4098 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4101 mips_saved_regsize (tdep
)));
4102 write_register (argreg
, regval
);
4105 /* Prevent subsequent floating point arguments from
4106 being passed in floating point registers. */
4107 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4113 /* Compute the the offset into the stack at which we
4114 will copy the next parameter.
4116 In older ABIs, the caller reserved space for
4117 registers that contained arguments. This was loosely
4118 refered to as their "home". Consequently, space is
4119 always allocated. */
4121 stack_offset
+= align_up (partial_len
,
4122 mips_stack_argsize (tdep
));
4126 fprintf_unfiltered (gdb_stdlog
, "\n");
4129 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
4131 /* Return adjusted stack pointer. */
4136 mips_o64_extract_return_value (struct type
*valtype
,
4137 char regbuf
[], char *valbuf
)
4139 struct return_value_word lo
;
4140 struct return_value_word hi
;
4141 return_value_location (valtype
, &hi
, &lo
);
4143 memcpy (valbuf
+ lo
.buf_offset
,
4144 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4145 lo
.reg_offset
, lo
.len
);
4148 memcpy (valbuf
+ hi
.buf_offset
,
4149 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4150 hi
.reg_offset
, hi
.len
);
4154 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4156 char raw_buffer
[MAX_REGISTER_SIZE
];
4157 struct return_value_word lo
;
4158 struct return_value_word hi
;
4159 return_value_location (valtype
, &hi
, &lo
);
4161 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4162 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4163 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4164 raw_buffer
, register_size (current_gdbarch
,
4169 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4170 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4171 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4173 register_size (current_gdbarch
,
4178 /* Floating point register management.
4180 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4181 64bit operations, these early MIPS cpus treat fp register pairs
4182 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4183 registers and offer a compatibility mode that emulates the MIPS2 fp
4184 model. When operating in MIPS2 fp compat mode, later cpu's split
4185 double precision floats into two 32-bit chunks and store them in
4186 consecutive fp regs. To display 64-bit floats stored in this
4187 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4188 Throw in user-configurable endianness and you have a real mess.
4190 The way this works is:
4191 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4192 double-precision value will be split across two logical registers.
4193 The lower-numbered logical register will hold the low-order bits,
4194 regardless of the processor's endianness.
4195 - If we are on a 64-bit processor, and we are looking for a
4196 single-precision value, it will be in the low ordered bits
4197 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4198 save slot in memory.
4199 - If we are in 64-bit mode, everything is straightforward.
4201 Note that this code only deals with "live" registers at the top of the
4202 stack. We will attempt to deal with saved registers later, when
4203 the raw/cooked register interface is in place. (We need a general
4204 interface that can deal with dynamic saved register sizes -- fp
4205 regs could be 32 bits wide in one frame and 64 on the frame above
4208 static struct type
*
4209 mips_float_register_type (void)
4211 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4212 return builtin_type_ieee_single_big
;
4214 return builtin_type_ieee_single_little
;
4217 static struct type
*
4218 mips_double_register_type (void)
4220 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4221 return builtin_type_ieee_double_big
;
4223 return builtin_type_ieee_double_little
;
4226 /* Copy a 32-bit single-precision value from the current frame
4227 into rare_buffer. */
4230 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4233 int raw_size
= register_size (current_gdbarch
, regno
);
4234 char *raw_buffer
= alloca (raw_size
);
4236 if (!frame_register_read (frame
, regno
, raw_buffer
))
4237 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4240 /* We have a 64-bit value for this register. Find the low-order
4244 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4249 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4253 memcpy (rare_buffer
, raw_buffer
, 4);
4257 /* Copy a 64-bit double-precision value from the current frame into
4258 rare_buffer. This may include getting half of it from the next
4262 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4265 int raw_size
= register_size (current_gdbarch
, regno
);
4267 if (raw_size
== 8 && !mips2_fp_compat ())
4269 /* We have a 64-bit value for this register, and we should use
4271 if (!frame_register_read (frame
, regno
, rare_buffer
))
4272 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4276 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4277 internal_error (__FILE__
, __LINE__
,
4278 "mips_read_fp_register_double: bad access to "
4279 "odd-numbered FP register");
4281 /* mips_read_fp_register_single will find the correct 32 bits from
4283 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4285 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4286 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4290 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4291 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4297 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4299 { /* do values for FP (float) regs */
4301 double doub
, flt1
; /* doubles extracted from raw hex data */
4305 (char *) alloca (2 *
4306 register_size (current_gdbarch
,
4307 mips_regnum (current_gdbarch
)->fp0
));
4309 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4310 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4313 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4315 /* 4-byte registers: Print hex and floating. Also print even
4316 numbered registers as doubles. */
4317 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4318 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4320 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4323 fprintf_filtered (file
, " flt: ");
4325 fprintf_filtered (file
, " <invalid float> ");
4327 fprintf_filtered (file
, "%-17.9g", flt1
);
4329 if (regnum
% 2 == 0)
4331 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4332 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4335 fprintf_filtered (file
, " dbl: ");
4337 fprintf_filtered (file
, "<invalid double>");
4339 fprintf_filtered (file
, "%-24.17g", doub
);
4344 /* Eight byte registers: print each one as hex, float and double. */
4345 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4346 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4348 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4349 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4352 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4355 fprintf_filtered (file
, " flt: ");
4357 fprintf_filtered (file
, "<invalid float>");
4359 fprintf_filtered (file
, "%-17.9g", flt1
);
4361 fprintf_filtered (file
, " dbl: ");
4363 fprintf_filtered (file
, "<invalid double>");
4365 fprintf_filtered (file
, "%-24.17g", doub
);
4370 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4371 int regnum
, int all
)
4373 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4374 char raw_buffer
[MAX_REGISTER_SIZE
];
4377 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4379 mips_print_fp_register (file
, frame
, regnum
);
4383 /* Get the data in raw format. */
4384 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4386 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4390 fputs_filtered (REGISTER_NAME (regnum
), file
);
4392 /* The problem with printing numeric register names (r26, etc.) is that
4393 the user can't use them on input. Probably the best solution is to
4394 fix it so that either the numeric or the funky (a2, etc.) names
4395 are accepted on input. */
4396 if (regnum
< MIPS_NUMREGS
)
4397 fprintf_filtered (file
, "(r%d): ", regnum
);
4399 fprintf_filtered (file
, ": ");
4401 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4403 register_size (current_gdbarch
,
4404 regnum
) - register_size (current_gdbarch
, regnum
);
4408 print_scalar_formatted (raw_buffer
+ offset
,
4409 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4413 /* Replacement for generic do_registers_info.
4414 Print regs in pretty columns. */
4417 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4420 fprintf_filtered (file
, " ");
4421 mips_print_fp_register (file
, frame
, regnum
);
4422 fprintf_filtered (file
, "\n");
4427 /* Print a row's worth of GP (int) registers, with name labels above */
4430 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4433 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4434 /* do values for GP (int) regs */
4435 char raw_buffer
[MAX_REGISTER_SIZE
];
4436 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4440 /* For GP registers, we print a separate row of names above the vals */
4441 fprintf_filtered (file
, " ");
4442 for (col
= 0, regnum
= start_regnum
;
4443 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4445 if (*REGISTER_NAME (regnum
) == '\0')
4446 continue; /* unused register */
4447 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4449 break; /* end the row: reached FP register */
4450 fprintf_filtered (file
,
4451 mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4452 REGISTER_NAME (regnum
));
4455 /* print the R0 to R31 names */
4456 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4457 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4459 fprintf_filtered (file
, "\n ");
4461 /* now print the values in hex, 4 or 8 to the row */
4462 for (col
= 0, regnum
= start_regnum
;
4463 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4465 if (*REGISTER_NAME (regnum
) == '\0')
4466 continue; /* unused register */
4467 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4469 break; /* end row: reached FP register */
4470 /* OK: get the data in raw format. */
4471 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4472 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4473 /* pad small registers */
4475 byte
< (mips_regsize (current_gdbarch
)
4476 - register_size (current_gdbarch
, regnum
)); byte
++)
4477 printf_filtered (" ");
4478 /* Now print the register value in hex, endian order. */
4479 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4481 register_size (current_gdbarch
,
4482 regnum
) - register_size (current_gdbarch
, regnum
);
4483 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4484 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4486 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4488 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4489 fprintf_filtered (file
, " ");
4492 if (col
> 0) /* ie. if we actually printed anything... */
4493 fprintf_filtered (file
, "\n");
4498 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4501 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4502 struct frame_info
*frame
, int regnum
, int all
)
4504 if (regnum
!= -1) /* do one specified register */
4506 gdb_assert (regnum
>= NUM_REGS
);
4507 if (*(REGISTER_NAME (regnum
)) == '\0')
4508 error ("Not a valid register for the current processor type");
4510 mips_print_register (file
, frame
, regnum
, 0);
4511 fprintf_filtered (file
, "\n");
4514 /* do all (or most) registers */
4517 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4519 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4522 if (all
) /* true for "INFO ALL-REGISTERS" command */
4523 regnum
= print_fp_register_row (file
, frame
, regnum
);
4525 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4528 regnum
= print_gp_register_row (file
, frame
, regnum
);
4533 /* Is this a branch with a delay slot? */
4535 static int is_delayed (unsigned long);
4538 is_delayed (unsigned long insn
)
4541 for (i
= 0; i
< NUMOPCODES
; ++i
)
4542 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4543 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4545 return (i
< NUMOPCODES
4546 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4547 | INSN_COND_BRANCH_DELAY
4548 | INSN_COND_BRANCH_LIKELY
)));
4552 mips_step_skips_delay (CORE_ADDR pc
)
4554 char buf
[MIPS_INSTLEN
];
4556 /* There is no branch delay slot on MIPS16. */
4557 if (pc_is_mips16 (pc
))
4560 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4561 /* If error reading memory, guess that it is not a delayed branch. */
4563 return is_delayed ((unsigned long)
4564 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4568 /* Given PC at the function's start address, attempt to find the
4569 prologue end using SAL information. Return zero if the skip fails.
4571 A non-optimized prologue traditionally has one SAL for the function
4572 and a second for the function body. A single line function has
4573 them both pointing at the same line.
4575 An optimized prologue is similar but the prologue may contain
4576 instructions (SALs) from the instruction body. Need to skip those
4577 while not getting into the function body.
4579 The functions end point and an increasing SAL line are used as
4580 indicators of the prologue's endpoint.
4582 This code is based on the function refine_prologue_limit (versions
4583 found in both ia64 and ppc). */
4586 skip_prologue_using_sal (CORE_ADDR func_addr
)
4588 struct symtab_and_line prologue_sal
;
4592 /* Get an initial range for the function. */
4593 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
4594 start_pc
+= FUNCTION_START_OFFSET
;
4596 prologue_sal
= find_pc_line (start_pc
, 0);
4597 if (prologue_sal
.line
!= 0)
4599 while (prologue_sal
.end
< end_pc
)
4601 struct symtab_and_line sal
;
4603 sal
= find_pc_line (prologue_sal
.end
, 0);
4606 /* Assume that a consecutive SAL for the same (or larger)
4607 line mark the prologue -> body transition. */
4608 if (sal
.line
>= prologue_sal
.line
)
4610 /* The case in which compiler's optimizer/scheduler has
4611 moved instructions into the prologue. We look ahead in
4612 the function looking for address ranges whose
4613 corresponding line number is less the first one that we
4614 found for the function. This is more conservative then
4615 refine_prologue_limit which scans a large number of SALs
4616 looking for any in the prologue */
4620 return prologue_sal
.end
;
4623 /* Skip the PC past function prologue instructions (32-bit version).
4624 This is a helper function for mips_skip_prologue. */
4627 mips32_skip_prologue (CORE_ADDR pc
)
4631 int seen_sp_adjust
= 0;
4632 int load_immediate_bytes
= 0;
4634 /* Find an upper bound on the prologue. */
4635 end_pc
= skip_prologue_using_sal (pc
);
4637 end_pc
= pc
+ 100; /* Magic. */
4639 /* Skip the typical prologue instructions. These are the stack adjustment
4640 instruction and the instructions that save registers on the stack
4641 or in the gcc frame. */
4642 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4644 unsigned long high_word
;
4646 inst
= mips_fetch_instruction (pc
);
4647 high_word
= (inst
>> 16) & 0xffff;
4649 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4650 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4652 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4653 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4655 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4656 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4657 && (inst
& 0x001F0000)) /* reg != $zero */
4660 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4662 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4664 continue; /* reg != $zero */
4666 /* move $s8,$sp. With different versions of gas this will be either
4667 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4668 Accept any one of these. */
4669 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4672 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4674 else if (high_word
== 0x3c1c) /* lui $gp,n */
4676 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4678 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4679 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4681 /* The following instructions load $at or $t0 with an immediate
4682 value in preparation for a stack adjustment via
4683 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4684 a local variable, so we accept them only before a stack adjustment
4685 instruction was seen. */
4686 else if (!seen_sp_adjust
)
4688 if (high_word
== 0x3c01 || /* lui $at,n */
4689 high_word
== 0x3c08) /* lui $t0,n */
4691 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4694 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4695 high_word
== 0x3508 || /* ori $t0,$t0,n */
4696 high_word
== 0x3401 || /* ori $at,$zero,n */
4697 high_word
== 0x3408) /* ori $t0,$zero,n */
4699 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4709 /* In a frameless function, we might have incorrectly
4710 skipped some load immediate instructions. Undo the skipping
4711 if the load immediate was not followed by a stack adjustment. */
4712 if (load_immediate_bytes
&& !seen_sp_adjust
)
4713 pc
-= load_immediate_bytes
;
4717 /* Skip the PC past function prologue instructions (16-bit version).
4718 This is a helper function for mips_skip_prologue. */
4721 mips16_skip_prologue (CORE_ADDR pc
)
4724 int extend_bytes
= 0;
4725 int prev_extend_bytes
;
4727 /* Table of instructions likely to be found in a function prologue. */
4730 unsigned short inst
;
4731 unsigned short mask
;
4737 , /* addiu $sp,offset */
4740 , /* daddiu $sp,offset */
4743 , /* sw reg,n($sp) */
4746 , /* sd reg,n($sp) */
4749 , /* sw $ra,n($sp) */
4752 , /* sd $ra,n($sp) */
4758 , /* sw $a0-$a3,n($s1) */
4761 , /* move reg,$a0-$a3 */
4764 , /* entry pseudo-op */
4767 , /* addiu $s1,$sp,n */
4769 0, 0} /* end of table marker */
4772 /* Find an upper bound on the prologue. */
4773 end_pc
= skip_prologue_using_sal (pc
);
4775 end_pc
= pc
+ 100; /* Magic. */
4777 /* Skip the typical prologue instructions. These are the stack adjustment
4778 instruction and the instructions that save registers on the stack
4779 or in the gcc frame. */
4780 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4782 unsigned short inst
;
4785 inst
= mips_fetch_instruction (pc
);
4787 /* Normally we ignore an extend instruction. However, if it is
4788 not followed by a valid prologue instruction, we must adjust
4789 the pc back over the extend so that it won't be considered
4790 part of the prologue. */
4791 if ((inst
& 0xf800) == 0xf000) /* extend */
4793 extend_bytes
= MIPS16_INSTLEN
;
4796 prev_extend_bytes
= extend_bytes
;
4799 /* Check for other valid prologue instructions besides extend. */
4800 for (i
= 0; table
[i
].mask
!= 0; i
++)
4801 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4803 if (table
[i
].mask
!= 0) /* it was in table? */
4804 continue; /* ignore it */
4808 /* Return the current pc, adjusted backwards by 2 if
4809 the previous instruction was an extend. */
4810 return pc
- prev_extend_bytes
;
4816 /* To skip prologues, I use this predicate. Returns either PC itself
4817 if the code at PC does not look like a function prologue; otherwise
4818 returns an address that (if we're lucky) follows the prologue. If
4819 LENIENT, then we must skip everything which is involved in setting
4820 up the frame (it's OK to skip more, just so long as we don't skip
4821 anything which might clobber the registers which are being saved.
4822 We must skip more in the case where part of the prologue is in the
4823 delay slot of a non-prologue instruction). */
4826 mips_skip_prologue (CORE_ADDR pc
)
4828 /* See if we can determine the end of the prologue via the symbol table.
4829 If so, then return either PC, or the PC after the prologue, whichever
4832 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4834 if (post_prologue_pc
!= 0)
4835 return max (pc
, post_prologue_pc
);
4837 /* Can't determine prologue from the symbol table, need to examine
4840 if (pc_is_mips16 (pc
))
4841 return mips16_skip_prologue (pc
);
4843 return mips32_skip_prologue (pc
);
4846 /* Exported procedure: Is PC in the signal trampoline code */
4849 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
4851 if (sigtramp_address
== 0)
4853 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
4856 /* Root of all "set mips "/"show mips " commands. This will eventually be
4857 used for all MIPS-specific commands. */
4860 show_mips_command (char *args
, int from_tty
)
4862 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4866 set_mips_command (char *args
, int from_tty
)
4869 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4870 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4873 /* Commands to show/set the MIPS FPU type. */
4876 show_mipsfpu_command (char *args
, int from_tty
)
4879 switch (MIPS_FPU_TYPE
)
4881 case MIPS_FPU_SINGLE
:
4882 fpu
= "single-precision";
4884 case MIPS_FPU_DOUBLE
:
4885 fpu
= "double-precision";
4888 fpu
= "absent (none)";
4891 internal_error (__FILE__
, __LINE__
, "bad switch");
4893 if (mips_fpu_type_auto
)
4895 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4899 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4904 set_mipsfpu_command (char *args
, int from_tty
)
4907 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4908 show_mipsfpu_command (args
, from_tty
);
4912 set_mipsfpu_single_command (char *args
, int from_tty
)
4914 struct gdbarch_info info
;
4915 gdbarch_info_init (&info
);
4916 mips_fpu_type
= MIPS_FPU_SINGLE
;
4917 mips_fpu_type_auto
= 0;
4918 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4919 instead of relying on globals. Doing that would let generic code
4920 handle the search for this specific architecture. */
4921 if (!gdbarch_update_p (info
))
4922 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4926 set_mipsfpu_double_command (char *args
, int from_tty
)
4928 struct gdbarch_info info
;
4929 gdbarch_info_init (&info
);
4930 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4931 mips_fpu_type_auto
= 0;
4932 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4933 instead of relying on globals. Doing that would let generic code
4934 handle the search for this specific architecture. */
4935 if (!gdbarch_update_p (info
))
4936 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4940 set_mipsfpu_none_command (char *args
, int from_tty
)
4942 struct gdbarch_info info
;
4943 gdbarch_info_init (&info
);
4944 mips_fpu_type
= MIPS_FPU_NONE
;
4945 mips_fpu_type_auto
= 0;
4946 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4947 instead of relying on globals. Doing that would let generic code
4948 handle the search for this specific architecture. */
4949 if (!gdbarch_update_p (info
))
4950 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4954 set_mipsfpu_auto_command (char *args
, int from_tty
)
4956 mips_fpu_type_auto
= 1;
4959 /* Attempt to identify the particular processor model by reading the
4960 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4961 the relevant processor still exists (it dates back to '94) and
4962 secondly this is not the way to do this. The processor type should
4963 be set by forcing an architecture change. */
4966 deprecated_mips_set_processor_regs_hack (void)
4968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4971 prid
= read_register (PRID_REGNUM
);
4973 if ((prid
& ~0xf) == 0x700)
4974 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4977 /* Just like reinit_frame_cache, but with the right arguments to be
4978 callable as an sfunc. */
4981 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4982 struct cmd_list_element
*c
)
4984 reinit_frame_cache ();
4988 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4990 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4991 mips_extra_func_info_t proc_desc
;
4993 /* Search for the function containing this address. Set the low bit
4994 of the address when searching, in case we were given an even address
4995 that is the start of a 16-bit function. If we didn't do this,
4996 the search would fail because the symbol table says the function
4997 starts at an odd address, i.e. 1 byte past the given address. */
4998 memaddr
= ADDR_BITS_REMOVE (memaddr
);
4999 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5001 /* Make an attempt to determine if this is a 16-bit function. If
5002 the procedure descriptor exists and the address therein is odd,
5003 it's definitely a 16-bit function. Otherwise, we have to just
5004 guess that if the address passed in is odd, it's 16-bits. */
5005 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5006 disassembler needs to be able to locally determine the ISA, and
5007 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5011 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5012 info
->mach
= bfd_mach_mips16
;
5016 if (pc_is_mips16 (memaddr
))
5017 info
->mach
= bfd_mach_mips16
;
5020 /* Round down the instruction address to the appropriate boundary. */
5021 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5023 /* Set the disassembler options. */
5024 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5026 /* Set up the disassembler info, so that we get the right
5027 register names from libopcodes. */
5028 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5029 info
->disassembler_options
= "gpr-names=n32";
5031 info
->disassembler_options
= "gpr-names=64";
5032 info
->flavour
= bfd_target_elf_flavour
;
5035 /* This string is not recognized explicitly by the disassembler,
5036 but it tells the disassembler to not try to guess the ABI from
5037 the bfd elf headers, such that, if the user overrides the ABI
5038 of a program linked as NewABI, the disassembly will follow the
5039 register naming conventions specified by the user. */
5040 info
->disassembler_options
= "gpr-names=32";
5042 /* Call the appropriate disassembler based on the target endian-ness. */
5043 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5044 return print_insn_big_mips (memaddr
, info
);
5046 return print_insn_little_mips (memaddr
, info
);
5049 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5050 counter value to determine whether a 16- or 32-bit breakpoint should be
5051 used. It returns a pointer to a string of bytes that encode a breakpoint
5052 instruction, stores the length of the string to *lenptr, and adjusts pc
5053 (if necessary) to point to the actual memory location where the
5054 breakpoint should be inserted. */
5056 static const unsigned char *
5057 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5059 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5061 if (pc_is_mips16 (*pcptr
))
5063 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5064 *pcptr
= unmake_mips16_addr (*pcptr
);
5065 *lenptr
= sizeof (mips16_big_breakpoint
);
5066 return mips16_big_breakpoint
;
5070 /* The IDT board uses an unusual breakpoint value, and
5071 sometimes gets confused when it sees the usual MIPS
5072 breakpoint instruction. */
5073 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5074 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5075 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5077 *lenptr
= sizeof (big_breakpoint
);
5079 if (strcmp (target_shortname
, "mips") == 0)
5080 return idt_big_breakpoint
;
5081 else if (strcmp (target_shortname
, "ddb") == 0
5082 || strcmp (target_shortname
, "pmon") == 0
5083 || strcmp (target_shortname
, "lsi") == 0)
5084 return pmon_big_breakpoint
;
5086 return big_breakpoint
;
5091 if (pc_is_mips16 (*pcptr
))
5093 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5094 *pcptr
= unmake_mips16_addr (*pcptr
);
5095 *lenptr
= sizeof (mips16_little_breakpoint
);
5096 return mips16_little_breakpoint
;
5100 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5101 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5102 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5104 *lenptr
= sizeof (little_breakpoint
);
5106 if (strcmp (target_shortname
, "mips") == 0)
5107 return idt_little_breakpoint
;
5108 else if (strcmp (target_shortname
, "ddb") == 0
5109 || strcmp (target_shortname
, "pmon") == 0
5110 || strcmp (target_shortname
, "lsi") == 0)
5111 return pmon_little_breakpoint
;
5113 return little_breakpoint
;
5118 /* If PC is in a mips16 call or return stub, return the address of the target
5119 PC, which is either the callee or the caller. There are several
5120 cases which must be handled:
5122 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5123 target PC is in $31 ($ra).
5124 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5125 and the target PC is in $2.
5126 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5127 before the jal instruction, this is effectively a call stub
5128 and the the target PC is in $2. Otherwise this is effectively
5129 a return stub and the target PC is in $18.
5131 See the source code for the stubs in gcc/config/mips/mips16.S for
5134 This function implements the SKIP_TRAMPOLINE_CODE macro.
5138 mips_skip_stub (CORE_ADDR pc
)
5141 CORE_ADDR start_addr
;
5143 /* Find the starting address and name of the function containing the PC. */
5144 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5147 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5148 target PC is in $31 ($ra). */
5149 if (strcmp (name
, "__mips16_ret_sf") == 0
5150 || strcmp (name
, "__mips16_ret_df") == 0)
5151 return read_signed_register (RA_REGNUM
);
5153 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5155 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5156 and the target PC is in $2. */
5157 if (name
[19] >= '0' && name
[19] <= '9')
5158 return read_signed_register (2);
5160 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5161 before the jal instruction, this is effectively a call stub
5162 and the the target PC is in $2. Otherwise this is effectively
5163 a return stub and the target PC is in $18. */
5164 else if (name
[19] == 's' || name
[19] == 'd')
5166 if (pc
== start_addr
)
5168 /* Check if the target of the stub is a compiler-generated
5169 stub. Such a stub for a function bar might have a name
5170 like __fn_stub_bar, and might look like this:
5175 la $1,bar (becomes a lui/addiu pair)
5177 So scan down to the lui/addi and extract the target
5178 address from those two instructions. */
5180 CORE_ADDR target_pc
= read_signed_register (2);
5184 /* See if the name of the target function is __fn_stub_*. */
5185 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5188 if (strncmp (name
, "__fn_stub_", 10) != 0
5189 && strcmp (name
, "etext") != 0
5190 && strcmp (name
, "_etext") != 0)
5193 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5194 The limit on the search is arbitrarily set to 20
5195 instructions. FIXME. */
5196 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5198 inst
= mips_fetch_instruction (target_pc
);
5199 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5200 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5201 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5202 return pc
| (inst
& 0xffff); /* low word */
5205 /* Couldn't find the lui/addui pair, so return stub address. */
5209 /* This is the 'return' part of a call stub. The return
5210 address is in $r18. */
5211 return read_signed_register (18);
5214 return 0; /* not a stub */
5218 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5219 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5222 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5224 CORE_ADDR start_addr
;
5226 /* Find the starting address of the function containing the PC. If the
5227 caller didn't give us a name, look it up at the same time. */
5228 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5232 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5234 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5235 if (name
[19] >= '0' && name
[19] <= '9')
5237 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5238 before the jal instruction, this is effectively a call stub. */
5239 else if (name
[19] == 's' || name
[19] == 'd')
5240 return pc
== start_addr
;
5243 return 0; /* not a stub */
5247 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5248 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5251 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5253 CORE_ADDR start_addr
;
5255 /* Find the starting address of the function containing the PC. */
5256 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5259 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5260 if (strcmp (name
, "__mips16_ret_sf") == 0
5261 || strcmp (name
, "__mips16_ret_df") == 0)
5264 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5265 i.e. after the jal instruction, this is effectively a return stub. */
5266 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5267 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5270 return 0; /* not a stub */
5274 /* Return non-zero if the PC is in a library helper function that should
5275 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5278 mips_ignore_helper (CORE_ADDR pc
)
5282 /* Find the starting address and name of the function containing the PC. */
5283 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5286 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5287 that we want to ignore. */
5288 return (strcmp (name
, "__mips16_ret_sf") == 0
5289 || strcmp (name
, "__mips16_ret_df") == 0);
5293 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5294 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5297 mips_stab_reg_to_regnum (int num
)
5300 if (num
>= 0 && num
< 32)
5302 else if (num
>= 38 && num
< 70)
5303 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5305 regnum
= mips_regnum (current_gdbarch
)->hi
;
5307 regnum
= mips_regnum (current_gdbarch
)->lo
;
5309 /* This will hopefully (eventually) provoke a warning. Should
5310 we be calling complaint() here? */
5311 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5312 return NUM_REGS
+ regnum
;
5316 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5317 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5320 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5323 if (num
>= 0 && num
< 32)
5325 else if (num
>= 32 && num
< 64)
5326 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5328 regnum
= mips_regnum (current_gdbarch
)->hi
;
5330 regnum
= mips_regnum (current_gdbarch
)->lo
;
5332 /* This will hopefully (eventually) provoke a warning. Should we
5333 be calling complaint() here? */
5334 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5335 return NUM_REGS
+ regnum
;
5339 mips_register_sim_regno (int regnum
)
5341 /* Only makes sense to supply raw registers. */
5342 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5343 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5344 decide if it is valid. Should instead define a standard sim/gdb
5345 register numbering scheme. */
5346 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5347 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5350 return LEGACY_SIM_REGNO_IGNORE
;
5354 /* Convert an integer into an address. By first converting the value
5355 into a pointer and then extracting it signed, the address is
5356 guarenteed to be correctly sign extended. */
5359 mips_integer_to_address (struct type
*type
, void *buf
)
5361 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5362 LONGEST val
= unpack_long (type
, buf
);
5363 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5364 return extract_signed_integer (tmp
,
5365 TYPE_LENGTH (builtin_type_void_data_ptr
));
5369 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5371 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5372 const char *name
= bfd_get_section_name (abfd
, sect
);
5374 if (*abip
!= MIPS_ABI_UNKNOWN
)
5377 if (strncmp (name
, ".mdebug.", 8) != 0)
5380 if (strcmp (name
, ".mdebug.abi32") == 0)
5381 *abip
= MIPS_ABI_O32
;
5382 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5383 *abip
= MIPS_ABI_N32
;
5384 else if (strcmp (name
, ".mdebug.abi64") == 0)
5385 *abip
= MIPS_ABI_N64
;
5386 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5387 *abip
= MIPS_ABI_O64
;
5388 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5389 *abip
= MIPS_ABI_EABI32
;
5390 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5391 *abip
= MIPS_ABI_EABI64
;
5393 warning ("unsupported ABI %s.", name
+ 8);
5396 static enum mips_abi
5397 global_mips_abi (void)
5401 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5402 if (mips_abi_strings
[i
] == mips_abi_string
)
5403 return (enum mips_abi
) i
;
5405 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5408 static struct gdbarch
*
5409 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5411 struct gdbarch
*gdbarch
;
5412 struct gdbarch_tdep
*tdep
;
5414 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5416 enum mips_fpu_type fpu_type
;
5418 /* First of all, extract the elf_flags, if available. */
5419 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5420 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5421 else if (arches
!= NULL
)
5422 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5426 fprintf_unfiltered (gdb_stdlog
,
5427 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5429 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5430 switch ((elf_flags
& EF_MIPS_ABI
))
5432 case E_MIPS_ABI_O32
:
5433 found_abi
= MIPS_ABI_O32
;
5435 case E_MIPS_ABI_O64
:
5436 found_abi
= MIPS_ABI_O64
;
5438 case E_MIPS_ABI_EABI32
:
5439 found_abi
= MIPS_ABI_EABI32
;
5441 case E_MIPS_ABI_EABI64
:
5442 found_abi
= MIPS_ABI_EABI64
;
5445 if ((elf_flags
& EF_MIPS_ABI2
))
5446 found_abi
= MIPS_ABI_N32
;
5448 found_abi
= MIPS_ABI_UNKNOWN
;
5452 /* GCC creates a pseudo-section whose name describes the ABI. */
5453 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5454 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5456 /* If we have no usefu BFD information, use the ABI from the last
5457 MIPS architecture (if there is one). */
5458 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5459 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5461 /* Try the architecture for any hint of the correct ABI. */
5462 if (found_abi
== MIPS_ABI_UNKNOWN
5463 && info
.bfd_arch_info
!= NULL
5464 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5466 switch (info
.bfd_arch_info
->mach
)
5468 case bfd_mach_mips3900
:
5469 found_abi
= MIPS_ABI_EABI32
;
5471 case bfd_mach_mips4100
:
5472 case bfd_mach_mips5000
:
5473 found_abi
= MIPS_ABI_EABI64
;
5475 case bfd_mach_mips8000
:
5476 case bfd_mach_mips10000
:
5477 /* On Irix, ELF64 executables use the N64 ABI. The
5478 pseudo-sections which describe the ABI aren't present
5479 on IRIX. (Even for executables created by gcc.) */
5480 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5481 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5482 found_abi
= MIPS_ABI_N64
;
5484 found_abi
= MIPS_ABI_N32
;
5490 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5493 /* What has the user specified from the command line? */
5494 wanted_abi
= global_mips_abi ();
5496 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5499 /* Now that we have found what the ABI for this binary would be,
5500 check whether the user is overriding it. */
5501 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5502 mips_abi
= wanted_abi
;
5503 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5504 mips_abi
= found_abi
;
5506 mips_abi
= MIPS_ABI_O32
;
5508 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5511 /* Also used when doing an architecture lookup. */
5513 fprintf_unfiltered (gdb_stdlog
,
5514 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5515 mips64_transfers_32bit_regs_p
);
5517 /* Determine the MIPS FPU type. */
5518 if (!mips_fpu_type_auto
)
5519 fpu_type
= mips_fpu_type
;
5520 else if (info
.bfd_arch_info
!= NULL
5521 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5522 switch (info
.bfd_arch_info
->mach
)
5524 case bfd_mach_mips3900
:
5525 case bfd_mach_mips4100
:
5526 case bfd_mach_mips4111
:
5527 fpu_type
= MIPS_FPU_NONE
;
5529 case bfd_mach_mips4650
:
5530 fpu_type
= MIPS_FPU_SINGLE
;
5533 fpu_type
= MIPS_FPU_DOUBLE
;
5536 else if (arches
!= NULL
)
5537 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5539 fpu_type
= MIPS_FPU_DOUBLE
;
5541 fprintf_unfiltered (gdb_stdlog
,
5542 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5544 /* try to find a pre-existing architecture */
5545 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5547 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5549 /* MIPS needs to be pedantic about which ABI the object is
5551 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5553 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5555 /* Need to be pedantic about which register virtual size is
5557 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5558 != mips64_transfers_32bit_regs_p
)
5560 /* Be pedantic about which FPU is selected. */
5561 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5563 return arches
->gdbarch
;
5566 /* Need a new architecture. Fill in a target specific vector. */
5567 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5568 gdbarch
= gdbarch_alloc (&info
, tdep
);
5569 tdep
->elf_flags
= elf_flags
;
5570 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5571 tdep
->found_abi
= found_abi
;
5572 tdep
->mips_abi
= mips_abi
;
5573 tdep
->mips_fpu_type
= fpu_type
;
5575 /* Initially set everything according to the default ABI/ISA. */
5576 set_gdbarch_short_bit (gdbarch
, 16);
5577 set_gdbarch_int_bit (gdbarch
, 32);
5578 set_gdbarch_float_bit (gdbarch
, 32);
5579 set_gdbarch_double_bit (gdbarch
, 64);
5580 set_gdbarch_long_double_bit (gdbarch
, 64);
5581 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5582 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5583 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5585 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5586 mips_elf_make_msymbol_special
);
5588 /* Fill in the OS dependant register numbers and names. */
5590 const char **reg_names
;
5591 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5592 struct mips_regnum
);
5593 if (info
.osabi
== GDB_OSABI_IRIX
)
5598 regnum
->badvaddr
= 66;
5601 regnum
->fp_control_status
= 69;
5602 regnum
->fp_implementation_revision
= 70;
5604 reg_names
= mips_irix_reg_names
;
5608 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5609 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5610 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5611 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5612 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5613 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5614 regnum
->fp_control_status
= 70;
5615 regnum
->fp_implementation_revision
= 71;
5617 if (info
.bfd_arch_info
!= NULL
5618 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5619 reg_names
= mips_tx39_reg_names
;
5621 reg_names
= mips_generic_reg_names
;
5623 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5624 replaced by read_pc? */
5625 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5626 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5627 set_gdbarch_num_regs (gdbarch
, num_regs
);
5628 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5629 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5630 tdep
->mips_processor_reg_names
= reg_names
;
5631 tdep
->regnum
= regnum
;
5637 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5638 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5639 tdep
->mips_default_saved_regsize
= 4;
5640 tdep
->mips_default_stack_argsize
= 4;
5641 tdep
->mips_fp_register_double
= 0;
5642 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5643 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5644 tdep
->default_mask_address_p
= 0;
5645 set_gdbarch_long_bit (gdbarch
, 32);
5646 set_gdbarch_ptr_bit (gdbarch
, 32);
5647 set_gdbarch_long_long_bit (gdbarch
, 64);
5650 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5651 set_gdbarch_deprecated_store_return_value (gdbarch
,
5652 mips_o64_store_return_value
);
5653 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5654 mips_o64_extract_return_value
);
5655 tdep
->mips_default_saved_regsize
= 8;
5656 tdep
->mips_default_stack_argsize
= 8;
5657 tdep
->mips_fp_register_double
= 1;
5658 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5659 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5660 tdep
->default_mask_address_p
= 0;
5661 set_gdbarch_long_bit (gdbarch
, 32);
5662 set_gdbarch_ptr_bit (gdbarch
, 32);
5663 set_gdbarch_long_long_bit (gdbarch
, 64);
5664 set_gdbarch_use_struct_convention (gdbarch
,
5665 always_use_struct_convention
);
5667 case MIPS_ABI_EABI32
:
5668 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5669 set_gdbarch_deprecated_store_return_value (gdbarch
,
5670 mips_eabi_store_return_value
);
5671 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5672 mips_eabi_extract_return_value
);
5673 tdep
->mips_default_saved_regsize
= 4;
5674 tdep
->mips_default_stack_argsize
= 4;
5675 tdep
->mips_fp_register_double
= 0;
5676 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5677 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5678 tdep
->default_mask_address_p
= 0;
5679 set_gdbarch_long_bit (gdbarch
, 32);
5680 set_gdbarch_ptr_bit (gdbarch
, 32);
5681 set_gdbarch_long_long_bit (gdbarch
, 64);
5682 set_gdbarch_deprecated_reg_struct_has_addr
5683 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5684 set_gdbarch_use_struct_convention (gdbarch
,
5685 mips_eabi_use_struct_convention
);
5687 case MIPS_ABI_EABI64
:
5688 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5689 set_gdbarch_deprecated_store_return_value (gdbarch
,
5690 mips_eabi_store_return_value
);
5691 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5692 mips_eabi_extract_return_value
);
5693 tdep
->mips_default_saved_regsize
= 8;
5694 tdep
->mips_default_stack_argsize
= 8;
5695 tdep
->mips_fp_register_double
= 1;
5696 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5697 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5698 tdep
->default_mask_address_p
= 0;
5699 set_gdbarch_long_bit (gdbarch
, 64);
5700 set_gdbarch_ptr_bit (gdbarch
, 64);
5701 set_gdbarch_long_long_bit (gdbarch
, 64);
5702 set_gdbarch_deprecated_reg_struct_has_addr
5703 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5704 set_gdbarch_use_struct_convention (gdbarch
,
5705 mips_eabi_use_struct_convention
);
5708 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5709 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5710 tdep
->mips_default_saved_regsize
= 8;
5711 tdep
->mips_default_stack_argsize
= 8;
5712 tdep
->mips_fp_register_double
= 1;
5713 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5714 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5715 tdep
->default_mask_address_p
= 0;
5716 set_gdbarch_long_bit (gdbarch
, 32);
5717 set_gdbarch_ptr_bit (gdbarch
, 32);
5718 set_gdbarch_long_long_bit (gdbarch
, 64);
5721 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5722 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5723 tdep
->mips_default_saved_regsize
= 8;
5724 tdep
->mips_default_stack_argsize
= 8;
5725 tdep
->mips_fp_register_double
= 1;
5726 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5727 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5728 tdep
->default_mask_address_p
= 0;
5729 set_gdbarch_long_bit (gdbarch
, 64);
5730 set_gdbarch_ptr_bit (gdbarch
, 64);
5731 set_gdbarch_long_long_bit (gdbarch
, 64);
5734 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5737 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5738 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5741 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5742 flag in object files because to do so would make it impossible to
5743 link with libraries compiled without "-gp32". This is
5744 unnecessarily restrictive.
5746 We could solve this problem by adding "-gp32" multilibs to gcc,
5747 but to set this flag before gcc is built with such multilibs will
5748 break too many systems.''
5750 But even more unhelpfully, the default linker output target for
5751 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5752 for 64-bit programs - you need to change the ABI to change this,
5753 and not all gcc targets support that currently. Therefore using
5754 this flag to detect 32-bit mode would do the wrong thing given
5755 the current gcc - it would make GDB treat these 64-bit programs
5756 as 32-bit programs by default. */
5758 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5759 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5760 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5762 /* Add/remove bits from an address. The MIPS needs be careful to
5763 ensure that all 32 bit addresses are sign extended to 64 bits. */
5764 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5766 /* Unwind the frame. */
5767 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5768 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
5769 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5770 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
5772 /* Map debug register numbers onto internal register numbers. */
5773 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5774 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5775 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5776 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5777 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5778 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5779 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5780 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5782 /* MIPS version of CALL_DUMMY */
5784 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5785 replaced by a command, and all targets will default to on stack
5786 (regardless of the stack's execute status). */
5787 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5788 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5790 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5791 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5792 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5794 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5795 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5797 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5799 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5800 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5801 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5803 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5805 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5806 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
5808 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5810 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5811 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5812 need to all be folded into the target vector. Since they are
5813 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5814 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5816 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5818 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
5820 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5821 to support MIPS16. This is a bad thing. Make sure not to do it
5822 if we have an OS ABI that actually supports shared libraries, since
5823 shared library support is more important. If we have an OS someday
5824 that supports both shared libraries and MIPS16, we'll have to find
5825 a better place for these. */
5826 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5828 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5829 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
5832 /* Hook in OS ABI-specific overrides, if they have been registered. */
5833 gdbarch_init_osabi (info
, gdbarch
);
5839 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5841 struct gdbarch_info info
;
5843 /* Force the architecture to update, and (if it's a MIPS architecture)
5844 mips_gdbarch_init will take care of the rest. */
5845 gdbarch_info_init (&info
);
5846 gdbarch_update_p (info
);
5849 /* Print out which MIPS ABI is in use. */
5852 show_mips_abi (char *ignore_args
, int from_tty
)
5854 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5856 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5859 enum mips_abi global_abi
= global_mips_abi ();
5860 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5861 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5863 if (global_abi
== MIPS_ABI_UNKNOWN
)
5865 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5867 else if (global_abi
== actual_abi
)
5869 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5873 /* Probably shouldn't happen... */
5875 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5876 actual_abi_str
, mips_abi_strings
[global_abi
]);
5882 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5884 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5888 int ef_mips_32bitmode
;
5889 /* determine the ISA */
5890 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5908 /* determine the size of a pointer */
5909 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5910 fprintf_unfiltered (file
,
5911 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5913 fprintf_unfiltered (file
,
5914 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5916 fprintf_unfiltered (file
,
5917 "mips_dump_tdep: ef_mips_arch = %d\n",
5919 fprintf_unfiltered (file
,
5920 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5921 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5922 fprintf_unfiltered (file
,
5923 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5924 mips_mask_address_p (tdep
),
5925 tdep
->default_mask_address_p
);
5927 fprintf_unfiltered (file
,
5928 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5929 FP_REGISTER_DOUBLE
);
5930 fprintf_unfiltered (file
,
5931 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5932 MIPS_DEFAULT_FPU_TYPE
,
5933 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5934 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5935 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5937 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5938 fprintf_unfiltered (file
,
5939 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5941 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5942 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5943 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5945 fprintf_unfiltered (file
,
5946 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5947 FP_REGISTER_DOUBLE
);
5948 fprintf_unfiltered (file
,
5949 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5950 mips_stack_argsize (tdep
));
5951 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
5952 fprintf_unfiltered (file
,
5953 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5954 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
5955 fprintf_unfiltered (file
,
5956 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5957 XSTRING (ATTACH_DETACH
));
5958 fprintf_unfiltered (file
,
5959 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5960 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5961 fprintf_unfiltered (file
,
5962 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5963 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5964 fprintf_unfiltered (file
,
5965 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5966 FIRST_EMBED_REGNUM
);
5967 fprintf_unfiltered (file
,
5968 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
5969 XSTRING (IGNORE_HELPER_CALL (PC
)));
5970 fprintf_unfiltered (file
,
5971 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5972 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
5973 fprintf_unfiltered (file
,
5974 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
5975 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
5976 fprintf_unfiltered (file
,
5977 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5979 #ifdef MACHINE_CPROC_FP_OFFSET
5980 fprintf_unfiltered (file
,
5981 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5982 MACHINE_CPROC_FP_OFFSET
);
5984 #ifdef MACHINE_CPROC_PC_OFFSET
5985 fprintf_unfiltered (file
,
5986 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5987 MACHINE_CPROC_PC_OFFSET
);
5989 #ifdef MACHINE_CPROC_SP_OFFSET
5990 fprintf_unfiltered (file
,
5991 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5992 MACHINE_CPROC_SP_OFFSET
);
5994 fprintf_unfiltered (file
,
5995 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5997 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5998 fprintf_unfiltered (file
,
5999 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6000 fprintf_unfiltered (file
,
6001 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6002 fprintf_unfiltered (file
,
6003 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6004 MIPS_LAST_ARG_REGNUM
,
6005 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6006 fprintf_unfiltered (file
,
6007 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6008 fprintf_unfiltered (file
,
6009 "mips_dump_tdep: mips_saved_regsize() = %d\n",
6010 mips_saved_regsize (tdep
));
6011 fprintf_unfiltered (file
,
6012 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6013 fprintf_unfiltered (file
,
6014 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6015 fprintf_unfiltered (file
,
6016 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6017 fprintf_unfiltered (file
,
6018 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6019 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6020 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6021 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6022 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6023 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6024 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6025 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6026 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6027 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6028 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6029 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6031 fprintf_unfiltered (file
,
6032 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6035 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6038 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6040 fprintf_unfiltered (file
,
6041 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6042 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6043 fprintf_unfiltered (file
,
6044 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6045 fprintf_unfiltered (file
,
6046 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6047 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6048 fprintf_unfiltered (file
,
6049 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6050 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6051 fprintf_unfiltered (file
,
6052 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6053 SOFTWARE_SINGLE_STEP_P ());
6054 fprintf_unfiltered (file
,
6055 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6056 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6057 #ifdef STACK_END_ADDR
6058 fprintf_unfiltered (file
,
6059 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6062 fprintf_unfiltered (file
,
6063 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6064 XSTRING (STEP_SKIPS_DELAY (PC
)));
6065 fprintf_unfiltered (file
,
6066 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6067 STEP_SKIPS_DELAY_P
);
6068 fprintf_unfiltered (file
,
6069 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6070 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6071 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6072 fprintf_unfiltered (file
,
6073 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6074 fprintf_unfiltered (file
,
6075 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6076 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6077 (TYPE
, CNT
, OTHERTYPE
)));
6078 fprintf_unfiltered (file
,
6079 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6080 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6082 fprintf_unfiltered (file
,
6083 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6084 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6087 fprintf_unfiltered (file
,
6088 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6090 #ifdef TRACE_FLAVOR_SIZE
6091 fprintf_unfiltered (file
,
6092 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6096 fprintf_unfiltered (file
,
6097 "mips_dump_tdep: TRACE_SET # %s\n",
6098 XSTRING (TRACE_SET (X
, STATE
)));
6100 #ifdef UNUSED_REGNUM
6101 fprintf_unfiltered (file
,
6102 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6104 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6105 fprintf_unfiltered (file
,
6106 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6107 (long) VM_MIN_ADDRESS
);
6108 fprintf_unfiltered (file
,
6109 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6110 fprintf_unfiltered (file
,
6111 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6114 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6117 _initialize_mips_tdep (void)
6119 static struct cmd_list_element
*mipsfpulist
= NULL
;
6120 struct cmd_list_element
*c
;
6122 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6123 if (MIPS_ABI_LAST
+ 1
6124 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6125 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6127 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6129 /* Add root prefix command for all "set mips"/"show mips" commands */
6130 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6131 "Various MIPS specific commands.",
6132 &setmipscmdlist
, "set mips ", 0, &setlist
);
6134 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6135 "Various MIPS specific commands.",
6136 &showmipscmdlist
, "show mips ", 0, &showlist
);
6138 /* Allow the user to override the saved register size. */
6139 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6142 &mips_saved_regsize_string
, "\
6143 Set size of general purpose registers saved on the stack.\n\
6144 This option can be set to one of:\n\
6145 32 - Force GDB to treat saved GP registers as 32-bit\n\
6146 64 - Force GDB to treat saved GP registers as 64-bit\n\
6147 auto - Allow GDB to use the target's default setting or autodetect the\n\
6148 saved GP register size from information contained in the executable.\n\
6149 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6151 /* Allow the user to override the argument stack size. */
6152 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6155 &mips_stack_argsize_string
, "\
6156 Set the amount of stack space reserved for each argument.\n\
6157 This option can be set to one of:\n\
6158 32 - Force GDB to allocate 32-bit chunks per argument\n\
6159 64 - Force GDB to allocate 64-bit chunks per argument\n\
6160 auto - Allow GDB to determine the correct setting from the current\n\
6161 target and executable (default)", &setmipscmdlist
), &showmipscmdlist
);
6163 /* Allow the user to override the ABI. */
6164 c
= add_set_enum_cmd
6165 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6166 "Set the ABI used by this program.\n"
6167 "This option can be set to one of:\n"
6168 " auto - the default ABI associated with the current binary\n"
6170 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6171 set_cmd_sfunc (c
, mips_abi_update
);
6172 add_cmd ("abi", class_obscure
, show_mips_abi
,
6173 "Show ABI in use by MIPS target", &showmipscmdlist
);
6175 /* Let the user turn off floating point and set the fence post for
6176 heuristic_proc_start. */
6178 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6179 "Set use of MIPS floating-point coprocessor.",
6180 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6181 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6182 "Select single-precision MIPS floating-point coprocessor.",
6184 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6185 "Select double-precision MIPS floating-point coprocessor.",
6187 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6188 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6189 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6190 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6191 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6192 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6193 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6194 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6195 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6196 "Select MIPS floating-point coprocessor automatically.",
6198 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6199 "Show current use of MIPS floating-point coprocessor target.",
6202 /* We really would like to have both "0" and "unlimited" work, but
6203 command.c doesn't deal with that. So make it a var_zinteger
6204 because the user can always use "999999" or some such for unlimited. */
6205 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6206 (char *) &heuristic_fence_post
, "\
6207 Set the distance searched for the start of a function.\n\
6208 If you are debugging a stripped executable, GDB needs to search through the\n\
6209 program for the start of a function. This command sets the distance of the\n\
6210 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6211 /* We need to throw away the frame cache when we set this, since it
6212 might change our ability to get backtraces. */
6213 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6214 add_show_from_set (c
, &showlist
);
6216 /* Allow the user to control whether the upper bits of 64-bit
6217 addresses should be zeroed. */
6218 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6219 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6220 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6221 allow GDB to determine the correct value.\n", "\
6222 Show zeroing of upper 32 bits of 64-bit addresses.",
6223 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6225 /* Allow the user to control the size of 32 bit registers within the
6226 raw remote packet. */
6227 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6228 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6229 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6230 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6231 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6232 64 bits for others. Use \"off\" to disable compatibility mode", "\
6233 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6234 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6235 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6236 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6238 /* Debug this files internals. */
6239 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6240 &mips_debug
, "Set mips debugging.\n\
6241 When non-zero, mips specific debugging is enabled.", &setdebuglist
), &showdebuglist
);