1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 const struct register_alias mips_numeric_register_aliases
[] = {
146 #define R(n) { #n, n }
147 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
148 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
149 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
150 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
154 #ifndef MIPS_DEFAULT_FPU_TYPE
155 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157 static int mips_fpu_type_auto
= 1;
158 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
160 static int mips_debug
= 0;
162 /* Properties (for struct target_desc) describing the g/G packet
164 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
165 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
167 struct target_desc
*mips_tdesc_gp32
;
168 struct target_desc
*mips_tdesc_gp64
;
170 const struct mips_regnum
*
171 mips_regnum (struct gdbarch
*gdbarch
)
173 return gdbarch_tdep (gdbarch
)->regnum
;
177 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
179 return mips_regnum (gdbarch
)->fp0
+ 12;
182 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
184 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
186 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
187 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
190 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
192 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
194 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
195 functions to test, set, or clear bit 0 of addresses. */
198 is_mips16_addr (CORE_ADDR addr
)
204 unmake_mips16_addr (CORE_ADDR addr
)
206 return ((addr
) & ~(CORE_ADDR
) 1);
210 make_mips16_addr (CORE_ADDR addr
)
212 return ((addr
) | (CORE_ADDR
) 1);
215 /* Return the MIPS ABI associated with GDBARCH. */
217 mips_abi (struct gdbarch
*gdbarch
)
219 return gdbarch_tdep (gdbarch
)->mips_abi
;
223 mips_isa_regsize (struct gdbarch
*gdbarch
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 /* If we know how big the registers are, use that size. */
228 if (tdep
->register_size_valid_p
)
229 return tdep
->register_size
;
231 /* Fall back to the previous behavior. */
232 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
233 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
236 /* Return the currently configured (or set) saved register size. */
239 mips_abi_regsize (struct gdbarch
*gdbarch
)
241 switch (mips_abi (gdbarch
))
243 case MIPS_ABI_EABI32
:
249 case MIPS_ABI_EABI64
:
251 case MIPS_ABI_UNKNOWN
:
254 internal_error (__FILE__
, __LINE__
, _("bad switch"));
258 /* Functions for setting and testing a bit in a minimal symbol that
259 marks it as 16-bit function. The MSB of the minimal symbol's
260 "info" field is used for this purpose.
262 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
263 i.e. refers to a 16-bit function, and sets a "special" bit in a
264 minimal symbol to mark it as a 16-bit function
266 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
269 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
271 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
273 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
278 msymbol_is_special (struct minimal_symbol
*msym
)
280 return MSYMBOL_TARGET_FLAG_1 (msym
);
283 /* XFER a value from the big/little/left end of the register.
284 Depending on the size of the value it might occupy the entire
285 register or just part of it. Make an allowance for this, aligning
286 things accordingly. */
289 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
290 int reg_num
, int length
,
291 enum bfd_endian endian
, gdb_byte
*in
,
292 const gdb_byte
*out
, int buf_offset
)
296 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
297 /* Need to transfer the left or right part of the register, based on
298 the targets byte order. */
302 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
304 case BFD_ENDIAN_LITTLE
:
307 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
311 internal_error (__FILE__
, __LINE__
, _("bad switch"));
314 fprintf_unfiltered (gdb_stderr
,
315 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
316 reg_num
, reg_offset
, buf_offset
, length
);
317 if (mips_debug
&& out
!= NULL
)
320 fprintf_unfiltered (gdb_stdlog
, "out ");
321 for (i
= 0; i
< length
; i
++)
322 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
325 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
328 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
330 if (mips_debug
&& in
!= NULL
)
333 fprintf_unfiltered (gdb_stdlog
, "in ");
334 for (i
= 0; i
< length
; i
++)
335 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
338 fprintf_unfiltered (gdb_stdlog
, "\n");
341 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
342 compatiblity mode. A return value of 1 means that we have
343 physical 64-bit registers, but should treat them as 32-bit registers. */
346 mips2_fp_compat (struct frame_info
*frame
)
348 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
349 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
351 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
355 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
356 in all the places we deal with FP registers. PR gdb/413. */
357 /* Otherwise check the FR bit in the status register - it controls
358 the FP compatiblity mode. If it is clear we are in compatibility
360 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
367 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
369 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
371 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
373 /* The list of available "set mips " and "show mips " commands. */
375 static struct cmd_list_element
*setmipscmdlist
= NULL
;
376 static struct cmd_list_element
*showmipscmdlist
= NULL
;
378 /* Integer registers 0 thru 31 are handled explicitly by
379 mips_register_name(). Processor specific registers 32 and above
380 are listed in the following tables. */
383 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
387 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
388 "sr", "lo", "hi", "bad", "cause", "pc",
389 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
390 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
391 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
392 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
393 "fsr", "fir", "" /*"fp" */ , "",
394 "", "", "", "", "", "", "", "",
395 "", "", "", "", "", "", "", "",
398 /* Names of IDT R3041 registers. */
400 static const char *mips_r3041_reg_names
[] = {
401 "sr", "lo", "hi", "bad", "cause", "pc",
402 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
403 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
404 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
405 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
406 "fsr", "fir", "", /*"fp" */ "",
407 "", "", "bus", "ccfg", "", "", "", "",
408 "", "", "port", "cmp", "", "", "epc", "prid",
411 /* Names of tx39 registers. */
413 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
414 "sr", "lo", "hi", "bad", "cause", "pc",
415 "", "", "", "", "", "", "", "",
416 "", "", "", "", "", "", "", "",
417 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
420 "", "", "", "", "", "", "", "",
421 "", "", "config", "cache", "debug", "depc", "epc", ""
424 /* Names of IRIX registers. */
425 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
426 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
427 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
428 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
429 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
430 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
434 /* Return the name of the register corresponding to REGNO. */
436 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
438 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
439 /* GPR names for all ABIs other than n32/n64. */
440 static char *mips_gpr_names
[] = {
441 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
442 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
443 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
444 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
447 /* GPR names for n32 and n64 ABIs. */
448 static char *mips_n32_n64_gpr_names
[] = {
449 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
450 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
451 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
452 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
455 enum mips_abi abi
= mips_abi (gdbarch
);
457 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
458 but then don't make the raw register names visible. This (upper)
459 range of user visible register numbers are the pseudo-registers.
461 This approach was adopted accommodate the following scenario:
462 It is possible to debug a 64-bit device using a 32-bit
463 programming model. In such instances, the raw registers are
464 configured to be 64-bits wide, while the pseudo registers are
465 configured to be 32-bits wide. The registers that the user
466 sees - the pseudo registers - match the users expectations
467 given the programming model being used. */
468 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
469 if (regno
< gdbarch_num_regs (gdbarch
))
472 /* The MIPS integer registers are always mapped from 0 to 31. The
473 names of the registers (which reflects the conventions regarding
474 register use) vary depending on the ABI. */
475 if (0 <= rawnum
&& rawnum
< 32)
477 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
478 return mips_n32_n64_gpr_names
[rawnum
];
480 return mips_gpr_names
[rawnum
];
482 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
483 return tdesc_register_name (gdbarch
, rawnum
);
484 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
486 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
487 return tdep
->mips_processor_reg_names
[rawnum
- 32];
490 internal_error (__FILE__
, __LINE__
,
491 _("mips_register_name: bad register number %d"), rawnum
);
494 /* Return the groups that a MIPS register can be categorised into. */
497 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
498 struct reggroup
*reggroup
)
503 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
504 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
505 if (reggroup
== all_reggroup
)
507 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
508 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
509 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
510 (gdbarch), as not all architectures are multi-arch. */
511 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
512 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
513 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
515 if (reggroup
== float_reggroup
)
516 return float_p
&& pseudo
;
517 if (reggroup
== vector_reggroup
)
518 return vector_p
&& pseudo
;
519 if (reggroup
== general_reggroup
)
520 return (!vector_p
&& !float_p
) && pseudo
;
521 /* Save the pseudo registers. Need to make certain that any code
522 extracting register values from a saved register cache also uses
524 if (reggroup
== save_reggroup
)
525 return raw_p
&& pseudo
;
526 /* Restore the same pseudo register. */
527 if (reggroup
== restore_reggroup
)
528 return raw_p
&& pseudo
;
532 /* Return the groups that a MIPS register can be categorised into.
533 This version is only used if we have a target description which
534 describes real registers (and their groups). */
537 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
538 struct reggroup
*reggroup
)
540 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
541 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
544 /* Only save, restore, and display the pseudo registers. Need to
545 make certain that any code extracting register values from a
546 saved register cache also uses pseudo registers.
548 Note: saving and restoring the pseudo registers is slightly
549 strange; if we have 64 bits, we should save and restore all
550 64 bits. But this is hard and has little benefit. */
554 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
558 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
561 /* Map the symbol table registers which live in the range [1 *
562 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
563 registers. Take care of alignment and size problems. */
565 static enum register_status
566 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
567 int cookednum
, gdb_byte
*buf
)
569 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
570 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
571 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
572 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
573 return regcache_raw_read (regcache
, rawnum
, buf
);
574 else if (register_size (gdbarch
, rawnum
) >
575 register_size (gdbarch
, cookednum
))
577 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
578 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
581 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
583 enum register_status status
;
585 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
586 if (status
== REG_VALID
)
587 store_signed_integer (buf
, 4, byte_order
, regval
);
592 internal_error (__FILE__
, __LINE__
, _("bad register size"));
596 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
597 struct regcache
*regcache
, int cookednum
,
600 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
601 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
602 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
603 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
604 regcache_raw_write (regcache
, rawnum
, buf
);
605 else if (register_size (gdbarch
, rawnum
) >
606 register_size (gdbarch
, cookednum
))
608 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
609 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
612 /* Sign extend the shortened version of the register prior
613 to placing it in the raw register. This is required for
614 some mips64 parts in order to avoid unpredictable behavior. */
615 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
616 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
617 regcache_raw_write_signed (regcache
, rawnum
, regval
);
621 internal_error (__FILE__
, __LINE__
, _("bad register size"));
625 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
626 struct agent_expr
*ax
, int reg
)
628 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
629 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
630 && reg
< 2 * gdbarch_num_regs (gdbarch
));
632 ax_reg_mask (ax
, rawnum
);
638 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
639 struct agent_expr
*ax
, int reg
)
641 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
642 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
643 && reg
< 2 * gdbarch_num_regs (gdbarch
));
644 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
648 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
650 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
651 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
654 ax_simple (ax
, aop_lsh
);
657 ax_simple (ax
, aop_rsh_signed
);
661 internal_error (__FILE__
, __LINE__
, _("bad register size"));
666 /* Table to translate MIPS16 register field to actual register number. */
667 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
669 /* Heuristic_proc_start may hunt through the text section for a long
670 time across a 2400 baud serial line. Allows the user to limit this
673 static unsigned int heuristic_fence_post
= 0;
675 /* Number of bytes of storage in the actual machine representation for
676 register N. NOTE: This defines the pseudo register type so need to
677 rebuild the architecture vector. */
679 static int mips64_transfers_32bit_regs_p
= 0;
682 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
683 struct cmd_list_element
*c
)
685 struct gdbarch_info info
;
686 gdbarch_info_init (&info
);
687 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
688 instead of relying on globals. Doing that would let generic code
689 handle the search for this specific architecture. */
690 if (!gdbarch_update_p (info
))
692 mips64_transfers_32bit_regs_p
= 0;
693 error (_("32-bit compatibility mode not supported"));
697 /* Convert to/from a register and the corresponding memory value. */
699 /* This predicate tests for the case of an 8 byte floating point
700 value that is being transferred to or from a pair of floating point
701 registers each of which are (or are considered to be) only 4 bytes
704 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
707 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
708 && register_size (gdbarch
, regnum
) == 4
709 && (regnum
% gdbarch_num_regs (gdbarch
))
710 >= mips_regnum (gdbarch
)->fp0
711 && (regnum
% gdbarch_num_regs (gdbarch
))
712 < mips_regnum (gdbarch
)->fp0
+ 32
713 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
716 /* This predicate tests for the case of a value of less than 8
717 bytes in width that is being transfered to or from an 8 byte
718 general purpose register. */
720 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
723 int num_regs
= gdbarch_num_regs (gdbarch
);
725 return (register_size (gdbarch
, regnum
) == 8
726 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
727 && TYPE_LENGTH (type
) < 8);
731 mips_convert_register_p (struct gdbarch
*gdbarch
,
732 int regnum
, struct type
*type
)
734 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
735 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
739 mips_register_to_value (struct frame_info
*frame
, int regnum
,
740 struct type
*type
, gdb_byte
*to
,
741 int *optimizedp
, int *unavailablep
)
743 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
745 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
747 get_frame_register (frame
, regnum
+ 0, to
+ 4);
748 get_frame_register (frame
, regnum
+ 1, to
+ 0);
750 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
751 optimizedp
, unavailablep
))
754 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
755 optimizedp
, unavailablep
))
757 *optimizedp
= *unavailablep
= 0;
760 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
762 int len
= TYPE_LENGTH (type
);
765 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
766 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
767 optimizedp
, unavailablep
))
770 *optimizedp
= *unavailablep
= 0;
775 internal_error (__FILE__
, __LINE__
,
776 _("mips_register_to_value: unrecognized case"));
781 mips_value_to_register (struct frame_info
*frame
, int regnum
,
782 struct type
*type
, const gdb_byte
*from
)
784 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
786 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
788 put_frame_register (frame
, regnum
+ 0, from
+ 4);
789 put_frame_register (frame
, regnum
+ 1, from
+ 0);
791 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
794 int len
= TYPE_LENGTH (type
);
796 /* Sign extend values, irrespective of type, that are stored to
797 a 64-bit general purpose register. (32-bit unsigned values
798 are stored as signed quantities within a 64-bit register.
799 When performing an operation, in compiled code, that combines
800 a 32-bit unsigned value with a signed 64-bit value, a type
801 conversion is first performed that zeroes out the high 32 bits.) */
802 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
805 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
807 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
808 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
809 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
813 if (from
[len
-1] & 0x80)
814 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
816 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
817 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
818 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
823 internal_error (__FILE__
, __LINE__
,
824 _("mips_value_to_register: unrecognized case"));
828 /* Return the GDB type object for the "standard" data type of data in
832 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
834 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
835 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
836 && (regnum
% gdbarch_num_regs (gdbarch
))
837 < mips_regnum (gdbarch
)->fp0
+ 32)
839 /* The floating-point registers raw, or cooked, always match
840 mips_isa_regsize(), and also map 1:1, byte for byte. */
841 if (mips_isa_regsize (gdbarch
) == 4)
842 return builtin_type (gdbarch
)->builtin_float
;
844 return builtin_type (gdbarch
)->builtin_double
;
846 else if (regnum
< gdbarch_num_regs (gdbarch
))
848 /* The raw or ISA registers. These are all sized according to
850 if (mips_isa_regsize (gdbarch
) == 4)
851 return builtin_type (gdbarch
)->builtin_int32
;
853 return builtin_type (gdbarch
)->builtin_int64
;
857 /* The cooked or ABI registers. These are sized according to
858 the ABI (with a few complications). */
859 if (regnum
>= (gdbarch_num_regs (gdbarch
)
860 + mips_regnum (gdbarch
)->fp_control_status
)
861 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
862 /* The pseudo/cooked view of the embedded registers is always
863 32-bit. The raw view is handled below. */
864 return builtin_type (gdbarch
)->builtin_int32
;
865 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
866 /* The target, while possibly using a 64-bit register buffer,
867 is only transfering 32-bits of each integer register.
868 Reflect this in the cooked/pseudo (ABI) register value. */
869 return builtin_type (gdbarch
)->builtin_int32
;
870 else if (mips_abi_regsize (gdbarch
) == 4)
871 /* The ABI is restricted to 32-bit registers (the ISA could be
873 return builtin_type (gdbarch
)->builtin_int32
;
876 return builtin_type (gdbarch
)->builtin_int64
;
880 /* Return the GDB type for the pseudo register REGNUM, which is the
881 ABI-level view. This function is only called if there is a target
882 description which includes registers, so we know precisely the
883 types of hardware registers. */
886 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
888 const int num_regs
= gdbarch_num_regs (gdbarch
);
889 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
890 int rawnum
= regnum
% num_regs
;
891 struct type
*rawtype
;
893 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
895 /* Absent registers are still absent. */
896 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
897 if (TYPE_LENGTH (rawtype
) == 0)
900 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
901 /* Present the floating point registers however the hardware did;
902 do not try to convert between FPU layouts. */
905 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
907 /* The pseudo/cooked view of embedded registers is always
908 32-bit, even if the target transfers 64-bit values for them.
909 New targets relying on XML descriptions should only transfer
910 the necessary 32 bits, but older versions of GDB expected 64,
911 so allow the target to provide 64 bits without interfering
912 with the displayed type. */
913 return builtin_type (gdbarch
)->builtin_int32
;
916 /* Use pointer types for registers if we can. For n32 we can not,
917 since we do not have a 64-bit pointer type. */
918 if (mips_abi_regsize (gdbarch
)
919 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
921 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
922 return builtin_type (gdbarch
)->builtin_data_ptr
;
923 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
924 return builtin_type (gdbarch
)->builtin_func_ptr
;
927 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
928 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
929 return builtin_type (gdbarch
)->builtin_int32
;
931 /* For all other registers, pass through the hardware type. */
935 /* Should the upper word of 64-bit addresses be zeroed? */
936 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
939 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
941 switch (mask_address_var
)
943 case AUTO_BOOLEAN_TRUE
:
945 case AUTO_BOOLEAN_FALSE
:
948 case AUTO_BOOLEAN_AUTO
:
949 return tdep
->default_mask_address_p
;
951 internal_error (__FILE__
, __LINE__
,
952 _("mips_mask_address_p: bad switch"));
958 show_mask_address (struct ui_file
*file
, int from_tty
,
959 struct cmd_list_element
*c
, const char *value
)
961 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
963 deprecated_show_value_hack (file
, from_tty
, c
, value
);
964 switch (mask_address_var
)
966 case AUTO_BOOLEAN_TRUE
:
967 printf_filtered ("The 32 bit mips address mask is enabled\n");
969 case AUTO_BOOLEAN_FALSE
:
970 printf_filtered ("The 32 bit mips address mask is disabled\n");
972 case AUTO_BOOLEAN_AUTO
:
974 ("The 32 bit address mask is set automatically. Currently %s\n",
975 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
978 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
983 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
986 mips_pc_is_mips16 (CORE_ADDR memaddr
)
988 struct minimal_symbol
*sym
;
990 /* A flag indicating that this is a MIPS16 function is stored by
991 elfread.c in the high bit of the info field. Use this to decide
992 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
993 the address is set, assume this is a MIPS16 address. */
994 sym
= lookup_minimal_symbol_by_pc (memaddr
);
996 return msymbol_is_special (sym
);
998 return is_mips16_addr (memaddr
);
1001 /* MIPS believes that the PC has a sign extended value. Perhaps the
1002 all registers should be sign extended for simplicity? */
1005 mips_read_pc (struct regcache
*regcache
)
1008 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1009 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1010 if (is_mips16_addr (pc
))
1011 pc
= unmake_mips16_addr (pc
);
1016 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1020 pc
= frame_unwind_register_signed
1021 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1022 if (is_mips16_addr (pc
))
1023 pc
= unmake_mips16_addr (pc
);
1028 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1030 return frame_unwind_register_signed
1031 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1034 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1035 dummy frame. The frame ID's base needs to match the TOS value
1036 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1039 static struct frame_id
1040 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1042 return frame_id_build
1043 (get_frame_register_signed (this_frame
,
1044 gdbarch_num_regs (gdbarch
)
1046 get_frame_pc (this_frame
));
1050 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1052 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1053 if (mips_pc_is_mips16 (pc
))
1054 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1056 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1059 /* Fetch and return instruction from the specified location. If the PC
1060 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1063 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1065 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1066 gdb_byte buf
[MIPS_INSN32_SIZE
];
1070 if (mips_pc_is_mips16 (addr
))
1072 instlen
= MIPS_INSN16_SIZE
;
1073 addr
= unmake_mips16_addr (addr
);
1076 instlen
= MIPS_INSN32_SIZE
;
1077 status
= target_read_memory (addr
, buf
, instlen
);
1079 memory_error (status
, addr
);
1080 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1083 /* These are the fields of 32 bit mips instructions. */
1084 #define mips32_op(x) (x >> 26)
1085 #define itype_op(x) (x >> 26)
1086 #define itype_rs(x) ((x >> 21) & 0x1f)
1087 #define itype_rt(x) ((x >> 16) & 0x1f)
1088 #define itype_immediate(x) (x & 0xffff)
1090 #define jtype_op(x) (x >> 26)
1091 #define jtype_target(x) (x & 0x03ffffff)
1093 #define rtype_op(x) (x >> 26)
1094 #define rtype_rs(x) ((x >> 21) & 0x1f)
1095 #define rtype_rt(x) ((x >> 16) & 0x1f)
1096 #define rtype_rd(x) ((x >> 11) & 0x1f)
1097 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1098 #define rtype_funct(x) (x & 0x3f)
1101 mips32_relative_offset (ULONGEST inst
)
1103 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1106 /* Determine where to set a single step breakpoint while considering
1107 branch prediction. */
1109 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1111 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1114 inst
= mips_fetch_instruction (gdbarch
, pc
);
1115 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1118 if (itype_op (inst
) >> 2 == 5)
1119 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1121 op
= (itype_op (inst
) & 0x03);
1131 goto greater_branch
;
1136 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1137 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1139 int tf
= itype_rt (inst
) & 0x01;
1140 int cnum
= itype_rt (inst
) >> 2;
1142 get_frame_register_signed (frame
,
1143 mips_regnum (get_frame_arch (frame
))->
1145 int cond
= ((fcrcs
>> 24) & 0xfe) | ((fcrcs
>> 23) & 0x01);
1147 if (((cond
>> cnum
) & 0x01) == tf
)
1148 pc
+= mips32_relative_offset (inst
) + 4;
1153 pc
+= 4; /* Not a branch, next instruction is easy. */
1156 { /* This gets way messy. */
1158 /* Further subdivide into SPECIAL, REGIMM and other. */
1159 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1161 case 0: /* SPECIAL */
1162 op
= rtype_funct (inst
);
1167 /* Set PC to that address. */
1168 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1170 case 12: /* SYSCALL */
1172 struct gdbarch_tdep
*tdep
;
1174 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1175 if (tdep
->syscall_next_pc
!= NULL
)
1176 pc
= tdep
->syscall_next_pc (frame
);
1185 break; /* end SPECIAL */
1186 case 1: /* REGIMM */
1188 op
= itype_rt (inst
); /* branch condition */
1193 case 16: /* BLTZAL */
1194 case 18: /* BLTZALL */
1196 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1197 pc
+= mips32_relative_offset (inst
) + 4;
1199 pc
+= 8; /* after the delay slot */
1203 case 17: /* BGEZAL */
1204 case 19: /* BGEZALL */
1205 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1206 pc
+= mips32_relative_offset (inst
) + 4;
1208 pc
+= 8; /* after the delay slot */
1210 /* All of the other instructions in the REGIMM category */
1215 break; /* end REGIMM */
1220 reg
= jtype_target (inst
) << 2;
1221 /* Upper four bits get never changed... */
1222 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1225 /* FIXME case JALX : */
1228 reg
= jtype_target (inst
) << 2;
1229 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1230 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1232 break; /* The new PC will be alternate mode */
1233 case 4: /* BEQ, BEQL */
1235 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1236 get_frame_register_signed (frame
, itype_rt (inst
)))
1237 pc
+= mips32_relative_offset (inst
) + 4;
1241 case 5: /* BNE, BNEL */
1243 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1244 get_frame_register_signed (frame
, itype_rt (inst
)))
1245 pc
+= mips32_relative_offset (inst
) + 4;
1249 case 6: /* BLEZ, BLEZL */
1250 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1251 pc
+= mips32_relative_offset (inst
) + 4;
1257 greater_branch
: /* BGTZ, BGTZL */
1258 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1259 pc
+= mips32_relative_offset (inst
) + 4;
1266 } /* mips32_next_pc */
1268 /* Decoding the next place to set a breakpoint is irregular for the
1269 mips 16 variant, but fortunately, there fewer instructions. We have
1270 to cope ith extensions for 16 bit instructions and a pair of actual
1271 32 bit instructions. We dont want to set a single step instruction
1272 on the extend instruction either. */
1274 /* Lots of mips16 instruction formats */
1275 /* Predicting jumps requires itype,ritype,i8type
1276 and their extensions extItype,extritype,extI8type. */
1277 enum mips16_inst_fmts
1279 itype
, /* 0 immediate 5,10 */
1280 ritype
, /* 1 5,3,8 */
1281 rrtype
, /* 2 5,3,3,5 */
1282 rritype
, /* 3 5,3,3,5 */
1283 rrrtype
, /* 4 5,3,3,3,2 */
1284 rriatype
, /* 5 5,3,3,1,4 */
1285 shifttype
, /* 6 5,3,3,3,2 */
1286 i8type
, /* 7 5,3,8 */
1287 i8movtype
, /* 8 5,3,3,5 */
1288 i8mov32rtype
, /* 9 5,3,5,3 */
1289 i64type
, /* 10 5,3,8 */
1290 ri64type
, /* 11 5,3,3,5 */
1291 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1292 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1293 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1294 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1295 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1296 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1297 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1298 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1299 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1300 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1302 /* I am heaping all the fields of the formats into one structure and
1303 then, only the fields which are involved in instruction extension. */
1307 unsigned int regx
; /* Function in i8 type. */
1312 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1313 for the bits which make up the immediate extension. */
1316 extended_offset (unsigned int extension
)
1320 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1322 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1324 value
|= extension
& 0x1f; /* Extract 4:0. */
1329 /* Only call this function if you know that this is an extendable
1330 instruction. It won't malfunction, but why make excess remote memory
1331 references? If the immediate operands get sign extended or something,
1332 do it after the extension is performed. */
1333 /* FIXME: Every one of these cases needs to worry about sign extension
1334 when the offset is to be used in relative addressing. */
1337 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1339 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1341 pc
&= 0xfffffffe; /* Clear the low order bit. */
1342 target_read_memory (pc
, buf
, 2);
1343 return extract_unsigned_integer (buf
, 2, byte_order
);
1347 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1348 unsigned int extension
,
1350 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1355 switch (insn_format
)
1362 value
= extended_offset ((extension
<< 16) | inst
);
1363 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1367 value
= inst
& 0x7ff;
1368 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
1377 { /* A register identifier and an offset. */
1378 /* Most of the fields are the same as I type but the
1379 immediate value is of a different length. */
1383 value
= extended_offset ((extension
<< 16) | inst
);
1384 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1388 value
= inst
& 0xff; /* 8 bits */
1389 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
1392 regx
= (inst
>> 8) & 0x07; /* i8 funct */
1398 unsigned long value
;
1399 unsigned int nexthalf
;
1400 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1401 value
= value
<< 16;
1402 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1411 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1413 upk
->offset
= offset
;
1420 add_offset_16 (CORE_ADDR pc
, int offset
)
1422 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1426 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1427 unsigned int extension
, unsigned int insn
)
1429 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1430 int op
= (insn
>> 11);
1433 case 2: /* Branch */
1436 struct upk_mips16 upk
;
1437 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1438 pc
+= (upk
.offset
<< 1) + 2;
1441 case 3: /* JAL , JALX - Watch out, these are 32 bit
1444 struct upk_mips16 upk
;
1445 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1446 pc
= add_offset_16 (pc
, upk
.offset
);
1447 if ((insn
>> 10) & 0x01) /* Exchange mode */
1448 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1455 struct upk_mips16 upk
;
1457 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1458 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1460 pc
+= (upk
.offset
<< 1) + 2;
1467 struct upk_mips16 upk
;
1469 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1470 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1472 pc
+= (upk
.offset
<< 1) + 2;
1477 case 12: /* I8 Formats btez btnez */
1479 struct upk_mips16 upk
;
1481 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1482 /* upk.regx contains the opcode */
1483 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1484 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1485 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1486 /* pc = add_offset_16(pc,upk.offset) ; */
1487 pc
+= (upk
.offset
<< 1) + 2;
1492 case 29: /* RR Formats JR, JALR, JALR-RA */
1494 struct upk_mips16 upk
;
1495 /* upk.fmt = rrtype; */
1500 upk
.regx
= (insn
>> 8) & 0x07;
1501 upk
.regy
= (insn
>> 5) & 0x07;
1502 if ((upk
.regy
& 1) == 0)
1503 reg
= mips16_to_32_reg
[upk
.regx
];
1505 reg
= 31; /* Function return instruction. */
1506 pc
= get_frame_register_signed (frame
, reg
);
1513 /* This is an instruction extension. Fetch the real instruction
1514 (which follows the extension) and decode things based on
1518 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1519 fetch_mips_16 (gdbarch
, pc
));
1532 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1534 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1535 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1536 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1539 /* The mips_next_pc function supports single_step when the remote
1540 target monitor or stub is not developed enough to do a single_step.
1541 It works by decoding the current instruction and predicting where a
1542 branch will go. This isnt hard because all the data is available.
1543 The MIPS32 and MIPS16 variants are quite different. */
1545 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1547 if (mips_pc_is_mips16 (pc
))
1548 return mips16_next_pc (frame
, pc
);
1550 return mips32_next_pc (frame
, pc
);
1553 struct mips_frame_cache
1556 struct trad_frame_saved_reg
*saved_regs
;
1559 /* Set a register's saved stack address in temp_saved_regs. If an
1560 address has already been set for this register, do nothing; this
1561 way we will only recognize the first save of a given register in a
1564 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1565 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1566 Strictly speaking, only the second range is used as it is only second
1567 range (the ABI instead of ISA registers) that comes into play when finding
1568 saved registers in a frame. */
1571 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1572 int regnum
, CORE_ADDR offset
)
1574 if (this_cache
!= NULL
1575 && this_cache
->saved_regs
[regnum
].addr
== -1)
1577 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1579 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1585 /* Fetch the immediate value from a MIPS16 instruction.
1586 If the previous instruction was an EXTEND, use it to extend
1587 the upper bits of the immediate value. This is a helper function
1588 for mips16_scan_prologue. */
1591 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1592 unsigned short inst
, /* current instruction */
1593 int nbits
, /* number of bits in imm field */
1594 int scale
, /* scale factor to be applied to imm */
1595 int is_signed
) /* is the imm field signed? */
1599 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1601 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1602 if (offset
& 0x8000) /* check for negative extend */
1603 offset
= 0 - (0x10000 - (offset
& 0xffff));
1604 return offset
| (inst
& 0x1f);
1608 int max_imm
= 1 << nbits
;
1609 int mask
= max_imm
- 1;
1610 int sign_bit
= max_imm
>> 1;
1612 offset
= inst
& mask
;
1613 if (is_signed
&& (offset
& sign_bit
))
1614 offset
= 0 - (max_imm
- offset
);
1615 return offset
* scale
;
1620 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1621 the associated FRAME_CACHE if not null.
1622 Return the address of the first instruction past the prologue. */
1625 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1626 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1627 struct frame_info
*this_frame
,
1628 struct mips_frame_cache
*this_cache
)
1631 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1633 long frame_offset
= 0; /* Size of stack frame. */
1634 long frame_adjust
= 0; /* Offset of FP from SP. */
1635 int frame_reg
= MIPS_SP_REGNUM
;
1636 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1637 unsigned inst
= 0; /* current instruction */
1638 unsigned entry_inst
= 0; /* the entry instruction */
1639 unsigned save_inst
= 0; /* the save instruction */
1642 int extend_bytes
= 0;
1643 int prev_extend_bytes
;
1644 CORE_ADDR end_prologue_addr
= 0;
1646 /* Can be called when there's no process, and hence when there's no
1648 if (this_frame
!= NULL
)
1649 sp
= get_frame_register_signed (this_frame
,
1650 gdbarch_num_regs (gdbarch
)
1655 if (limit_pc
> start_pc
+ 200)
1656 limit_pc
= start_pc
+ 200;
1658 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1660 /* Save the previous instruction. If it's an EXTEND, we'll extract
1661 the immediate offset extension from it in mips16_get_imm. */
1664 /* Fetch and decode the instruction. */
1665 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1667 /* Normally we ignore extend instructions. However, if it is
1668 not followed by a valid prologue instruction, then this
1669 instruction is not part of the prologue either. We must
1670 remember in this case to adjust the end_prologue_addr back
1672 if ((inst
& 0xf800) == 0xf000) /* extend */
1674 extend_bytes
= MIPS_INSN16_SIZE
;
1678 prev_extend_bytes
= extend_bytes
;
1681 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1682 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1684 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1685 if (offset
< 0) /* Negative stack adjustment? */
1686 frame_offset
-= offset
;
1688 /* Exit loop if a positive stack adjustment is found, which
1689 usually means that the stack cleanup code in the function
1690 epilogue is reached. */
1693 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1695 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1696 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1697 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1699 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1701 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1702 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1703 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1705 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1707 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1708 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1710 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1712 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1713 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1715 else if (inst
== 0x673d) /* move $s1, $sp */
1720 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1722 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1723 frame_addr
= sp
+ offset
;
1725 frame_adjust
= offset
;
1727 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1729 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1730 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1731 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1733 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1735 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1736 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1737 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1739 else if ((inst
& 0xf81f) == 0xe809
1740 && (inst
& 0x700) != 0x700) /* entry */
1741 entry_inst
= inst
; /* Save for later processing. */
1742 else if ((inst
& 0xff80) == 0x6480) /* save */
1744 save_inst
= inst
; /* Save for later processing. */
1745 if (prev_extend_bytes
) /* extend */
1746 save_inst
|= prev_inst
<< 16;
1748 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1749 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1750 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1752 /* This instruction is part of the prologue, but we don't
1753 need to do anything special to handle it. */
1757 /* This instruction is not an instruction typically found
1758 in a prologue, so we must have reached the end of the
1760 if (end_prologue_addr
== 0)
1761 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1765 /* The entry instruction is typically the first instruction in a function,
1766 and it stores registers at offsets relative to the value of the old SP
1767 (before the prologue). But the value of the sp parameter to this
1768 function is the new SP (after the prologue has been executed). So we
1769 can't calculate those offsets until we've seen the entire prologue,
1770 and can calculate what the old SP must have been. */
1771 if (entry_inst
!= 0)
1773 int areg_count
= (entry_inst
>> 8) & 7;
1774 int sreg_count
= (entry_inst
>> 6) & 3;
1776 /* The entry instruction always subtracts 32 from the SP. */
1779 /* Now we can calculate what the SP must have been at the
1780 start of the function prologue. */
1783 /* Check if a0-a3 were saved in the caller's argument save area. */
1784 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1786 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1787 offset
+= mips_abi_regsize (gdbarch
);
1790 /* Check if the ra register was pushed on the stack. */
1792 if (entry_inst
& 0x20)
1794 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1795 offset
-= mips_abi_regsize (gdbarch
);
1798 /* Check if the s0 and s1 registers were pushed on the stack. */
1799 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1801 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1802 offset
-= mips_abi_regsize (gdbarch
);
1806 /* The SAVE instruction is similar to ENTRY, except that defined by the
1807 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1808 size of the frame is specified as an immediate field of instruction
1809 and an extended variation exists which lets additional registers and
1810 frame space to be specified. The instruction always treats registers
1811 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1812 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1814 static int args_table
[16] = {
1815 0, 0, 0, 0, 1, 1, 1, 1,
1816 2, 2, 2, 0, 3, 3, 4, -1,
1818 static int astatic_table
[16] = {
1819 0, 1, 2, 3, 0, 1, 2, 3,
1820 0, 1, 2, 4, 0, 1, 0, -1,
1822 int aregs
= (save_inst
>> 16) & 0xf;
1823 int xsregs
= (save_inst
>> 24) & 0x7;
1824 int args
= args_table
[aregs
];
1825 int astatic
= astatic_table
[aregs
];
1830 warning (_("Invalid number of argument registers encoded in SAVE."));
1835 warning (_("Invalid number of static registers encoded in SAVE."));
1839 /* For standard SAVE the frame size of 0 means 128. */
1840 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1841 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1844 frame_offset
+= frame_size
;
1846 /* Now we can calculate what the SP must have been at the
1847 start of the function prologue. */
1850 /* Check if A0-A3 were saved in the caller's argument save area. */
1851 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1853 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1854 offset
+= mips_abi_regsize (gdbarch
);
1859 /* Check if the RA register was pushed on the stack. */
1860 if (save_inst
& 0x40)
1862 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1863 offset
-= mips_abi_regsize (gdbarch
);
1866 /* Check if the S8 register was pushed on the stack. */
1869 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1870 offset
-= mips_abi_regsize (gdbarch
);
1873 /* Check if S2-S7 were pushed on the stack. */
1874 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1876 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1877 offset
-= mips_abi_regsize (gdbarch
);
1880 /* Check if the S1 register was pushed on the stack. */
1881 if (save_inst
& 0x10)
1883 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1884 offset
-= mips_abi_regsize (gdbarch
);
1886 /* Check if the S0 register was pushed on the stack. */
1887 if (save_inst
& 0x20)
1889 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1890 offset
-= mips_abi_regsize (gdbarch
);
1893 /* Check if A0-A3 were pushed on the stack. */
1894 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1896 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1897 offset
-= mips_abi_regsize (gdbarch
);
1901 if (this_cache
!= NULL
)
1904 (get_frame_register_signed (this_frame
,
1905 gdbarch_num_regs (gdbarch
) + frame_reg
)
1906 + frame_offset
- frame_adjust
);
1907 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1908 be able to get rid of the assignment below, evetually. But it's
1909 still needed for now. */
1910 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1911 + mips_regnum (gdbarch
)->pc
]
1912 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1915 /* If we didn't reach the end of the prologue when scanning the function
1916 instructions, then set end_prologue_addr to the address of the
1917 instruction immediately after the last one we scanned. */
1918 if (end_prologue_addr
== 0)
1919 end_prologue_addr
= cur_pc
;
1921 return end_prologue_addr
;
1924 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1925 Procedures that use the 32-bit instruction set are handled by the
1926 mips_insn32 unwinder. */
1928 static struct mips_frame_cache
*
1929 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1931 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1932 struct mips_frame_cache
*cache
;
1934 if ((*this_cache
) != NULL
)
1935 return (*this_cache
);
1936 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1937 (*this_cache
) = cache
;
1938 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1940 /* Analyze the function prologue. */
1942 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1943 CORE_ADDR start_addr
;
1945 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1946 if (start_addr
== 0)
1947 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1948 /* We can't analyze the prologue if we couldn't find the begining
1950 if (start_addr
== 0)
1953 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1956 /* gdbarch_sp_regnum contains the value and not the address. */
1957 trad_frame_set_value (cache
->saved_regs
,
1958 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1961 return (*this_cache
);
1965 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1966 struct frame_id
*this_id
)
1968 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1970 /* This marks the outermost frame. */
1971 if (info
->base
== 0)
1973 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1976 static struct value
*
1977 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1978 void **this_cache
, int regnum
)
1980 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1982 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1986 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1987 struct frame_info
*this_frame
, void **this_cache
)
1989 CORE_ADDR pc
= get_frame_pc (this_frame
);
1990 if (mips_pc_is_mips16 (pc
))
1995 static const struct frame_unwind mips_insn16_frame_unwind
=
1998 default_frame_unwind_stop_reason
,
1999 mips_insn16_frame_this_id
,
2000 mips_insn16_frame_prev_register
,
2002 mips_insn16_frame_sniffer
2006 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2009 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2014 static const struct frame_base mips_insn16_frame_base
=
2016 &mips_insn16_frame_unwind
,
2017 mips_insn16_frame_base_address
,
2018 mips_insn16_frame_base_address
,
2019 mips_insn16_frame_base_address
2022 static const struct frame_base
*
2023 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2025 CORE_ADDR pc
= get_frame_pc (this_frame
);
2026 if (mips_pc_is_mips16 (pc
))
2027 return &mips_insn16_frame_base
;
2032 /* Mark all the registers as unset in the saved_regs array
2033 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2036 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2038 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2042 const int num_regs
= gdbarch_num_regs (gdbarch
);
2045 for (i
= 0; i
< num_regs
; i
++)
2047 this_cache
->saved_regs
[i
].addr
= -1;
2052 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2053 the associated FRAME_CACHE if not null.
2054 Return the address of the first instruction past the prologue. */
2057 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2058 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2059 struct frame_info
*this_frame
,
2060 struct mips_frame_cache
*this_cache
)
2063 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2067 int frame_reg
= MIPS_SP_REGNUM
;
2069 CORE_ADDR end_prologue_addr
= 0;
2070 int seen_sp_adjust
= 0;
2071 int load_immediate_bytes
= 0;
2072 int in_delay_slot
= 0;
2073 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2075 /* Can be called when there's no process, and hence when there's no
2077 if (this_frame
!= NULL
)
2078 sp
= get_frame_register_signed (this_frame
,
2079 gdbarch_num_regs (gdbarch
)
2084 if (limit_pc
> start_pc
+ 200)
2085 limit_pc
= start_pc
+ 200;
2090 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2092 unsigned long inst
, high_word
, low_word
;
2095 /* Fetch the instruction. */
2096 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2098 /* Save some code by pre-extracting some useful fields. */
2099 high_word
= (inst
>> 16) & 0xffff;
2100 low_word
= inst
& 0xffff;
2101 reg
= high_word
& 0x1f;
2103 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2104 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2105 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2107 if (low_word
& 0x8000) /* Negative stack adjustment? */
2108 frame_offset
+= 0x10000 - low_word
;
2110 /* Exit loop if a positive stack adjustment is found, which
2111 usually means that the stack cleanup code in the function
2112 epilogue is reached. */
2116 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2117 && !regsize_is_64_bits
)
2119 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2121 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2122 && regsize_is_64_bits
)
2124 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2125 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2127 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2129 /* Old gcc frame, r30 is virtual frame pointer. */
2130 if ((long) low_word
!= frame_offset
)
2131 frame_addr
= sp
+ low_word
;
2132 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2134 unsigned alloca_adjust
;
2137 frame_addr
= get_frame_register_signed
2138 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2140 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2141 if (alloca_adjust
> 0)
2143 /* FP > SP + frame_size. This may be because of
2144 an alloca or somethings similar. Fix sp to
2145 "pre-alloca" value, and try again. */
2146 sp
+= alloca_adjust
;
2147 /* Need to reset the status of all registers. Otherwise,
2148 we will hit a guard that prevents the new address
2149 for each register to be recomputed during the second
2151 reset_saved_regs (gdbarch
, this_cache
);
2156 /* move $30,$sp. With different versions of gas this will be either
2157 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2158 Accept any one of these. */
2159 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2161 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2162 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2164 unsigned alloca_adjust
;
2167 frame_addr
= get_frame_register_signed
2168 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2170 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2171 if (alloca_adjust
> 0)
2173 /* FP > SP + frame_size. This may be because of
2174 an alloca or somethings similar. Fix sp to
2175 "pre-alloca" value, and try again. */
2177 /* Need to reset the status of all registers. Otherwise,
2178 we will hit a guard that prevents the new address
2179 for each register to be recomputed during the second
2181 reset_saved_regs (gdbarch
, this_cache
);
2186 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2187 && !regsize_is_64_bits
)
2189 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2191 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2192 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2193 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2194 || high_word
== 0x3c1c /* lui $gp,n */
2195 || high_word
== 0x279c /* addiu $gp,$gp,n */
2196 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2197 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2200 /* These instructions are part of the prologue, but we don't
2201 need to do anything special to handle them. */
2203 /* The instructions below load $at or $t0 with an immediate
2204 value in preparation for a stack adjustment via
2205 subu $sp,$sp,[$at,$t0]. These instructions could also
2206 initialize a local variable, so we accept them only before
2207 a stack adjustment instruction was seen. */
2208 else if (!seen_sp_adjust
2209 && (high_word
== 0x3c01 /* lui $at,n */
2210 || high_word
== 0x3c08 /* lui $t0,n */
2211 || high_word
== 0x3421 /* ori $at,$at,n */
2212 || high_word
== 0x3508 /* ori $t0,$t0,n */
2213 || high_word
== 0x3401 /* ori $at,$zero,n */
2214 || high_word
== 0x3408 /* ori $t0,$zero,n */
2217 if (end_prologue_addr
== 0)
2218 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2222 /* This instruction is not an instruction typically found
2223 in a prologue, so we must have reached the end of the
2225 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2226 loop now? Why would we need to continue scanning the function
2228 if (end_prologue_addr
== 0)
2229 end_prologue_addr
= cur_pc
;
2231 /* Check for branches and jumps. For now, only jump to
2232 register are caught (i.e. returns). */
2233 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2237 /* If the previous instruction was a jump, we must have reached
2238 the end of the prologue by now. Stop scanning so that we do
2239 not go past the function return. */
2244 if (this_cache
!= NULL
)
2247 (get_frame_register_signed (this_frame
,
2248 gdbarch_num_regs (gdbarch
) + frame_reg
)
2250 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2251 this assignment below, eventually. But it's still needed
2253 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2254 + mips_regnum (gdbarch
)->pc
]
2255 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2259 /* If we didn't reach the end of the prologue when scanning the function
2260 instructions, then set end_prologue_addr to the address of the
2261 instruction immediately after the last one we scanned. */
2262 /* brobecker/2004-10-10: I don't think this would ever happen, but
2263 we may as well be careful and do our best if we have a null
2264 end_prologue_addr. */
2265 if (end_prologue_addr
== 0)
2266 end_prologue_addr
= cur_pc
;
2268 /* In a frameless function, we might have incorrectly
2269 skipped some load immediate instructions. Undo the skipping
2270 if the load immediate was not followed by a stack adjustment. */
2271 if (load_immediate_bytes
&& !seen_sp_adjust
)
2272 end_prologue_addr
-= load_immediate_bytes
;
2274 return end_prologue_addr
;
2277 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2278 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2279 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2282 static struct mips_frame_cache
*
2283 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2285 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2286 struct mips_frame_cache
*cache
;
2288 if ((*this_cache
) != NULL
)
2289 return (*this_cache
);
2291 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2292 (*this_cache
) = cache
;
2293 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2295 /* Analyze the function prologue. */
2297 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2298 CORE_ADDR start_addr
;
2300 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2301 if (start_addr
== 0)
2302 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2303 /* We can't analyze the prologue if we couldn't find the begining
2305 if (start_addr
== 0)
2308 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2311 /* gdbarch_sp_regnum contains the value and not the address. */
2312 trad_frame_set_value (cache
->saved_regs
,
2313 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2316 return (*this_cache
);
2320 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2321 struct frame_id
*this_id
)
2323 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2325 /* This marks the outermost frame. */
2326 if (info
->base
== 0)
2328 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2331 static struct value
*
2332 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2333 void **this_cache
, int regnum
)
2335 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2337 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2341 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2342 struct frame_info
*this_frame
, void **this_cache
)
2344 CORE_ADDR pc
= get_frame_pc (this_frame
);
2345 if (! mips_pc_is_mips16 (pc
))
2350 static const struct frame_unwind mips_insn32_frame_unwind
=
2353 default_frame_unwind_stop_reason
,
2354 mips_insn32_frame_this_id
,
2355 mips_insn32_frame_prev_register
,
2357 mips_insn32_frame_sniffer
2361 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2364 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2369 static const struct frame_base mips_insn32_frame_base
=
2371 &mips_insn32_frame_unwind
,
2372 mips_insn32_frame_base_address
,
2373 mips_insn32_frame_base_address
,
2374 mips_insn32_frame_base_address
2377 static const struct frame_base
*
2378 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2380 CORE_ADDR pc
= get_frame_pc (this_frame
);
2381 if (! mips_pc_is_mips16 (pc
))
2382 return &mips_insn32_frame_base
;
2387 static struct trad_frame_cache
*
2388 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2391 CORE_ADDR start_addr
;
2392 CORE_ADDR stack_addr
;
2393 struct trad_frame_cache
*this_trad_cache
;
2394 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2395 int num_regs
= gdbarch_num_regs (gdbarch
);
2397 if ((*this_cache
) != NULL
)
2398 return (*this_cache
);
2399 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2400 (*this_cache
) = this_trad_cache
;
2402 /* The return address is in the link register. */
2403 trad_frame_set_reg_realreg (this_trad_cache
,
2404 gdbarch_pc_regnum (gdbarch
),
2405 num_regs
+ MIPS_RA_REGNUM
);
2407 /* Frame ID, since it's a frameless / stackless function, no stack
2408 space is allocated and SP on entry is the current SP. */
2409 pc
= get_frame_pc (this_frame
);
2410 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2411 stack_addr
= get_frame_register_signed (this_frame
,
2412 num_regs
+ MIPS_SP_REGNUM
);
2413 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2415 /* Assume that the frame's base is the same as the
2417 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2419 return this_trad_cache
;
2423 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2424 struct frame_id
*this_id
)
2426 struct trad_frame_cache
*this_trad_cache
2427 = mips_stub_frame_cache (this_frame
, this_cache
);
2428 trad_frame_get_id (this_trad_cache
, this_id
);
2431 static struct value
*
2432 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2433 void **this_cache
, int regnum
)
2435 struct trad_frame_cache
*this_trad_cache
2436 = mips_stub_frame_cache (this_frame
, this_cache
);
2437 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2441 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2442 struct frame_info
*this_frame
, void **this_cache
)
2445 struct obj_section
*s
;
2446 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2447 struct minimal_symbol
*msym
;
2449 /* Use the stub unwinder for unreadable code. */
2450 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2453 if (in_plt_section (pc
, NULL
))
2456 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2457 s
= find_pc_section (pc
);
2460 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2461 ".MIPS.stubs") == 0)
2464 /* Calling a PIC function from a non-PIC function passes through a
2465 stub. The stub for foo is named ".pic.foo". */
2466 msym
= lookup_minimal_symbol_by_pc (pc
);
2468 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2469 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2475 static const struct frame_unwind mips_stub_frame_unwind
=
2478 default_frame_unwind_stop_reason
,
2479 mips_stub_frame_this_id
,
2480 mips_stub_frame_prev_register
,
2482 mips_stub_frame_sniffer
2486 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2489 struct trad_frame_cache
*this_trad_cache
2490 = mips_stub_frame_cache (this_frame
, this_cache
);
2491 return trad_frame_get_this_base (this_trad_cache
);
2494 static const struct frame_base mips_stub_frame_base
=
2496 &mips_stub_frame_unwind
,
2497 mips_stub_frame_base_address
,
2498 mips_stub_frame_base_address
,
2499 mips_stub_frame_base_address
2502 static const struct frame_base
*
2503 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2505 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2506 return &mips_stub_frame_base
;
2511 /* mips_addr_bits_remove - remove useless address bits */
2514 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2516 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2518 if (is_mips16_addr (addr
))
2519 addr
= unmake_mips16_addr (addr
);
2521 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2522 /* This hack is a work-around for existing boards using PMON, the
2523 simulator, and any other 64-bit targets that doesn't have true
2524 64-bit addressing. On these targets, the upper 32 bits of
2525 addresses are ignored by the hardware. Thus, the PC or SP are
2526 likely to have been sign extended to all 1s by instruction
2527 sequences that load 32-bit addresses. For example, a typical
2528 piece of code that loads an address is this:
2530 lui $r2, <upper 16 bits>
2531 ori $r2, <lower 16 bits>
2533 But the lui sign-extends the value such that the upper 32 bits
2534 may be all 1s. The workaround is simply to mask off these
2535 bits. In the future, gcc may be changed to support true 64-bit
2536 addressing, and this masking will have to be disabled. */
2537 return addr
&= 0xffffffffUL
;
2542 /* Instructions used during single-stepping of atomic sequences. */
2543 #define LL_OPCODE 0x30
2544 #define LLD_OPCODE 0x34
2545 #define SC_OPCODE 0x38
2546 #define SCD_OPCODE 0x3c
2548 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2549 instruction and ending with a SC/SCD instruction. If such a sequence
2550 is found, attempt to step through it. A breakpoint is placed at the end of
2554 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2555 struct address_space
*aspace
, CORE_ADDR pc
)
2557 CORE_ADDR breaks
[2] = {-1, -1};
2559 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2563 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2564 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2569 insn
= mips_fetch_instruction (gdbarch
, loc
);
2570 /* Assume all atomic sequences start with a ll/lld instruction. */
2571 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2574 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2576 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2579 loc
+= MIPS_INSN32_SIZE
;
2580 insn
= mips_fetch_instruction (gdbarch
, loc
);
2582 /* Assume that there is at most one branch in the atomic
2583 sequence. If a branch is found, put a breakpoint in its
2584 destination address. */
2585 switch (itype_op (insn
))
2587 case 0: /* SPECIAL */
2588 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2589 return 0; /* fallback to the standard single-step code. */
2591 case 1: /* REGIMM */
2592 is_branch
= ((itype_rt (insn
) & 0xc) == 0); /* B{LT,GE}Z* */
2596 return 0; /* fallback to the standard single-step code. */
2603 case 22: /* BLEZL */
2604 case 23: /* BGTTL */
2610 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2615 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2616 if (last_breakpoint
>= 1)
2617 return 0; /* More than one branch found, fallback to the
2618 standard single-step code. */
2619 breaks
[1] = branch_bp
;
2623 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2627 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2628 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2631 loc
+= MIPS_INSN32_SIZE
;
2633 /* Insert a breakpoint right after the end of the atomic sequence. */
2636 /* Check for duplicated breakpoints. Check also for a breakpoint
2637 placed (branch instruction's destination) in the atomic sequence. */
2638 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2639 last_breakpoint
= 0;
2641 /* Effectively inserts the breakpoints. */
2642 for (index
= 0; index
<= last_breakpoint
; index
++)
2643 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2648 /* mips_software_single_step() is called just before we want to resume
2649 the inferior, if we want to single-step it but there is no hardware
2650 or kernel single-step support (MIPS on GNU/Linux for example). We find
2651 the target of the coming instruction and breakpoint it. */
2654 mips_software_single_step (struct frame_info
*frame
)
2656 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2657 struct address_space
*aspace
= get_frame_address_space (frame
);
2658 CORE_ADDR pc
, next_pc
;
2660 pc
= get_frame_pc (frame
);
2661 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2664 next_pc
= mips_next_pc (frame
, pc
);
2666 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2670 /* Test whether the PC points to the return instruction at the
2671 end of a function. */
2674 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2676 if (mips_pc_is_mips16 (pc
))
2677 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2678 generates a "jr $ra"; other times it generates code to load
2679 the return address from the stack to an accessible register (such
2680 as $a3), then a "jr" using that register. This second case
2681 is almost impossible to distinguish from an indirect jump
2682 used for switch statements, so we don't even try. */
2683 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2685 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2689 /* This fencepost looks highly suspicious to me. Removing it also
2690 seems suspicious as it could affect remote debugging across serial
2694 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2700 struct inferior
*inf
;
2702 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2704 fence
= start_pc
- heuristic_fence_post
;
2708 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2709 fence
= VM_MIN_ADDRESS
;
2711 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2713 inf
= current_inferior ();
2715 /* Search back for previous return. */
2716 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2717 if (start_pc
< fence
)
2719 /* It's not clear to me why we reach this point when
2720 stop_soon, but with this test, at least we
2721 don't print out warnings for every child forked (eg, on
2722 decstation). 22apr93 rich@cygnus.com. */
2723 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2725 static int blurb_printed
= 0;
2727 warning (_("GDB can't find the start of the function at %s."),
2728 paddress (gdbarch
, pc
));
2732 /* This actually happens frequently in embedded
2733 development, when you first connect to a board
2734 and your stack pointer and pc are nowhere in
2735 particular. This message needs to give people
2736 in that situation enough information to
2737 determine that it's no big deal. */
2738 printf_filtered ("\n\
2739 GDB is unable to find the start of the function at %s\n\
2740 and thus can't determine the size of that function's stack frame.\n\
2741 This means that GDB may be unable to access that stack frame, or\n\
2742 the frames below it.\n\
2743 This problem is most likely caused by an invalid program counter or\n\
2745 However, if you think GDB should simply search farther back\n\
2746 from %s for code which looks like the beginning of a\n\
2747 function, you can increase the range of the search using the `set\n\
2748 heuristic-fence-post' command.\n",
2749 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2756 else if (mips_pc_is_mips16 (start_pc
))
2758 unsigned short inst
;
2760 /* On MIPS16, any one of the following is likely to be the
2761 start of a function:
2767 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2768 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2769 if ((inst
& 0xff80) == 0x6480) /* save */
2771 if (start_pc
- instlen
>= fence
)
2773 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2774 if ((inst
& 0xf800) == 0xf000) /* extend */
2775 start_pc
-= instlen
;
2779 else if (((inst
& 0xf81f) == 0xe809
2780 && (inst
& 0x700) != 0x700) /* entry */
2781 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2782 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2783 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2785 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2786 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2791 else if (mips_about_to_return (gdbarch
, start_pc
))
2793 /* Skip return and its delay slot. */
2794 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2801 struct mips_objfile_private
2807 /* According to the current ABI, should the type be passed in a
2808 floating-point register (assuming that there is space)? When there
2809 is no FPU, FP are not even considered as possible candidates for
2810 FP registers and, consequently this returns false - forces FP
2811 arguments into integer registers. */
2814 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2815 struct type
*arg_type
)
2817 return ((typecode
== TYPE_CODE_FLT
2818 || (MIPS_EABI (gdbarch
)
2819 && (typecode
== TYPE_CODE_STRUCT
2820 || typecode
== TYPE_CODE_UNION
)
2821 && TYPE_NFIELDS (arg_type
) == 1
2822 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2824 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2827 /* On o32, argument passing in GPRs depends on the alignment of the type being
2828 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2831 mips_type_needs_double_align (struct type
*type
)
2833 enum type_code typecode
= TYPE_CODE (type
);
2835 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2837 else if (typecode
== TYPE_CODE_STRUCT
)
2839 if (TYPE_NFIELDS (type
) < 1)
2841 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2843 else if (typecode
== TYPE_CODE_UNION
)
2847 n
= TYPE_NFIELDS (type
);
2848 for (i
= 0; i
< n
; i
++)
2849 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2856 /* Adjust the address downward (direction of stack growth) so that it
2857 is correctly aligned for a new stack frame. */
2859 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2861 return align_down (addr
, 16);
2865 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2866 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2867 int nargs
, struct value
**args
, CORE_ADDR sp
,
2868 int struct_return
, CORE_ADDR struct_addr
)
2874 int stack_offset
= 0;
2875 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2876 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2877 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2878 int regsize
= mips_abi_regsize (gdbarch
);
2880 /* For shared libraries, "t9" needs to point at the function
2882 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2884 /* Set the return address register to point to the entry point of
2885 the program, where a breakpoint lies in wait. */
2886 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2888 /* First ensure that the stack and structure return address (if any)
2889 are properly aligned. The stack has to be at least 64-bit
2890 aligned even on 32-bit machines, because doubles must be 64-bit
2891 aligned. For n32 and n64, stack frames need to be 128-bit
2892 aligned, so we round to this widest known alignment. */
2894 sp
= align_down (sp
, 16);
2895 struct_addr
= align_down (struct_addr
, 16);
2897 /* Now make space on the stack for the args. We allocate more
2898 than necessary for EABI, because the first few arguments are
2899 passed in registers, but that's OK. */
2900 for (argnum
= 0; argnum
< nargs
; argnum
++)
2901 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2902 sp
-= align_up (len
, 16);
2905 fprintf_unfiltered (gdb_stdlog
,
2906 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2907 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2909 /* Initialize the integer and float register pointers. */
2910 argreg
= MIPS_A0_REGNUM
;
2911 float_argreg
= mips_fpa0_regnum (gdbarch
);
2913 /* The struct_return pointer occupies the first parameter-passing reg. */
2917 fprintf_unfiltered (gdb_stdlog
,
2918 "mips_eabi_push_dummy_call: "
2919 "struct_return reg=%d %s\n",
2920 argreg
, paddress (gdbarch
, struct_addr
));
2921 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2924 /* Now load as many as possible of the first arguments into
2925 registers, and push the rest onto the stack. Loop thru args
2926 from first to last. */
2927 for (argnum
= 0; argnum
< nargs
; argnum
++)
2929 const gdb_byte
*val
;
2930 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2931 struct value
*arg
= args
[argnum
];
2932 struct type
*arg_type
= check_typedef (value_type (arg
));
2933 int len
= TYPE_LENGTH (arg_type
);
2934 enum type_code typecode
= TYPE_CODE (arg_type
);
2937 fprintf_unfiltered (gdb_stdlog
,
2938 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2939 argnum
+ 1, len
, (int) typecode
);
2941 /* Function pointer arguments to mips16 code need to be made into
2943 if (typecode
== TYPE_CODE_PTR
2944 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
2946 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
2948 if (mips_pc_is_mips16 (addr
))
2950 store_signed_integer (valbuf
, len
, byte_order
,
2951 make_mips16_addr (addr
));
2955 val
= value_contents (arg
);
2957 /* The EABI passes structures that do not fit in a register by
2959 else if (len
> regsize
2960 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2962 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2963 value_address (arg
));
2964 typecode
= TYPE_CODE_PTR
;
2968 fprintf_unfiltered (gdb_stdlog
, " push");
2971 val
= value_contents (arg
);
2973 /* 32-bit ABIs always start floating point arguments in an
2974 even-numbered floating point register. Round the FP register
2975 up before the check to see if there are any FP registers
2976 left. Non MIPS_EABI targets also pass the FP in the integer
2977 registers so also round up normal registers. */
2978 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2980 if ((float_argreg
& 1))
2984 /* Floating point arguments passed in registers have to be
2985 treated specially. On 32-bit architectures, doubles
2986 are passed in register pairs; the even register gets
2987 the low word, and the odd register gets the high word.
2988 On non-EABI processors, the first two floating point arguments are
2989 also copied to general registers, because MIPS16 functions
2990 don't use float registers for arguments. This duplication of
2991 arguments in general registers can't hurt non-MIPS16 functions
2992 because those registers are normally skipped. */
2993 /* MIPS_EABI squeezes a struct that contains a single floating
2994 point value into an FP register instead of pushing it onto the
2996 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2997 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
2999 /* EABI32 will pass doubles in consecutive registers, even on
3000 64-bit cores. At one time, we used to check the size of
3001 `float_argreg' to determine whether or not to pass doubles
3002 in consecutive registers, but this is not sufficient for
3003 making the ABI determination. */
3004 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3006 int low_offset
= gdbarch_byte_order (gdbarch
)
3007 == BFD_ENDIAN_BIG
? 4 : 0;
3010 /* Write the low word of the double to the even register(s). */
3011 regval
= extract_signed_integer (val
+ low_offset
,
3014 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3015 float_argreg
, phex (regval
, 4));
3016 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3018 /* Write the high word of the double to the odd register(s). */
3019 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3022 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3023 float_argreg
, phex (regval
, 4));
3024 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3028 /* This is a floating point value that fits entirely
3029 in a single register. */
3030 /* On 32 bit ABI's the float_argreg is further adjusted
3031 above to ensure that it is even register aligned. */
3032 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3034 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3035 float_argreg
, phex (regval
, len
));
3036 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3041 /* Copy the argument to general registers or the stack in
3042 register-sized pieces. Large arguments are split between
3043 registers and stack. */
3044 /* Note: structs whose size is not a multiple of regsize
3045 are treated specially: Irix cc passes
3046 them in registers where gcc sometimes puts them on the
3047 stack. For maximum compatibility, we will put them in
3049 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3051 /* Note: Floating-point values that didn't fit into an FP
3052 register are only written to memory. */
3055 /* Remember if the argument was written to the stack. */
3056 int stack_used_p
= 0;
3057 int partial_len
= (len
< regsize
? len
: regsize
);
3060 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3063 /* Write this portion of the argument to the stack. */
3064 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3066 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3068 /* Should shorter than int integer values be
3069 promoted to int before being stored? */
3070 int longword_offset
= 0;
3073 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3076 && (typecode
== TYPE_CODE_INT
3077 || typecode
== TYPE_CODE_PTR
3078 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3079 longword_offset
= regsize
- len
;
3080 else if ((typecode
== TYPE_CODE_STRUCT
3081 || typecode
== TYPE_CODE_UNION
)
3082 && TYPE_LENGTH (arg_type
) < regsize
)
3083 longword_offset
= regsize
- len
;
3088 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3089 paddress (gdbarch
, stack_offset
));
3090 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3091 paddress (gdbarch
, longword_offset
));
3094 addr
= sp
+ stack_offset
+ longword_offset
;
3099 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3100 paddress (gdbarch
, addr
));
3101 for (i
= 0; i
< partial_len
; i
++)
3103 fprintf_unfiltered (gdb_stdlog
, "%02x",
3107 write_memory (addr
, val
, partial_len
);
3110 /* Note!!! This is NOT an else clause. Odd sized
3111 structs may go thru BOTH paths. Floating point
3112 arguments will not. */
3113 /* Write this portion of the argument to a general
3114 purpose register. */
3115 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3116 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3119 extract_signed_integer (val
, partial_len
, byte_order
);
3122 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3124 phex (regval
, regsize
));
3125 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3132 /* Compute the offset into the stack at which we will
3133 copy the next parameter.
3135 In the new EABI (and the NABI32), the stack_offset
3136 only needs to be adjusted when it has been used. */
3139 stack_offset
+= align_up (partial_len
, regsize
);
3143 fprintf_unfiltered (gdb_stdlog
, "\n");
3146 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3148 /* Return adjusted stack pointer. */
3152 /* Determine the return value convention being used. */
3154 static enum return_value_convention
3155 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3156 struct type
*type
, struct regcache
*regcache
,
3157 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3159 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3160 int fp_return_type
= 0;
3161 int offset
, regnum
, xfer
;
3163 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3164 return RETURN_VALUE_STRUCT_CONVENTION
;
3166 /* Floating point type? */
3167 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3169 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3171 /* Structs with a single field of float type
3172 are returned in a floating point register. */
3173 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3174 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3175 && TYPE_NFIELDS (type
) == 1)
3177 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3179 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3186 /* A floating-point value belongs in the least significant part
3189 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3190 regnum
= mips_regnum (gdbarch
)->fp0
;
3194 /* An integer value goes in V0/V1. */
3196 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3197 regnum
= MIPS_V0_REGNUM
;
3200 offset
< TYPE_LENGTH (type
);
3201 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3203 xfer
= mips_abi_regsize (gdbarch
);
3204 if (offset
+ xfer
> TYPE_LENGTH (type
))
3205 xfer
= TYPE_LENGTH (type
) - offset
;
3206 mips_xfer_register (gdbarch
, regcache
,
3207 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3208 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3212 return RETURN_VALUE_REGISTER_CONVENTION
;
3216 /* N32/N64 ABI stuff. */
3218 /* Search for a naturally aligned double at OFFSET inside a struct
3219 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3223 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3228 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3231 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3234 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3237 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3240 struct type
*field_type
;
3242 /* We're only looking at normal fields. */
3243 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3244 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3247 /* If we have gone past the offset, there is no double to pass. */
3248 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3252 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3254 /* If this field is entirely before the requested offset, go
3255 on to the next one. */
3256 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3259 /* If this is our special aligned double, we can stop. */
3260 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3261 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3264 /* This field starts at or before the requested offset, and
3265 overlaps it. If it is a structure, recurse inwards. */
3266 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3273 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3274 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3275 int nargs
, struct value
**args
, CORE_ADDR sp
,
3276 int struct_return
, CORE_ADDR struct_addr
)
3282 int stack_offset
= 0;
3283 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3284 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3285 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3287 /* For shared libraries, "t9" needs to point at the function
3289 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3291 /* Set the return address register to point to the entry point of
3292 the program, where a breakpoint lies in wait. */
3293 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3295 /* First ensure that the stack and structure return address (if any)
3296 are properly aligned. The stack has to be at least 64-bit
3297 aligned even on 32-bit machines, because doubles must be 64-bit
3298 aligned. For n32 and n64, stack frames need to be 128-bit
3299 aligned, so we round to this widest known alignment. */
3301 sp
= align_down (sp
, 16);
3302 struct_addr
= align_down (struct_addr
, 16);
3304 /* Now make space on the stack for the args. */
3305 for (argnum
= 0; argnum
< nargs
; argnum
++)
3306 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3307 sp
-= align_up (len
, 16);
3310 fprintf_unfiltered (gdb_stdlog
,
3311 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3312 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3314 /* Initialize the integer and float register pointers. */
3315 argreg
= MIPS_A0_REGNUM
;
3316 float_argreg
= mips_fpa0_regnum (gdbarch
);
3318 /* The struct_return pointer occupies the first parameter-passing reg. */
3322 fprintf_unfiltered (gdb_stdlog
,
3323 "mips_n32n64_push_dummy_call: "
3324 "struct_return reg=%d %s\n",
3325 argreg
, paddress (gdbarch
, struct_addr
));
3326 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3329 /* Now load as many as possible of the first arguments into
3330 registers, and push the rest onto the stack. Loop thru args
3331 from first to last. */
3332 for (argnum
= 0; argnum
< nargs
; argnum
++)
3334 const gdb_byte
*val
;
3335 struct value
*arg
= args
[argnum
];
3336 struct type
*arg_type
= check_typedef (value_type (arg
));
3337 int len
= TYPE_LENGTH (arg_type
);
3338 enum type_code typecode
= TYPE_CODE (arg_type
);
3341 fprintf_unfiltered (gdb_stdlog
,
3342 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3343 argnum
+ 1, len
, (int) typecode
);
3345 val
= value_contents (arg
);
3347 /* A 128-bit long double value requires an even-odd pair of
3348 floating-point registers. */
3350 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3351 && (float_argreg
& 1))
3357 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3358 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3360 /* This is a floating point value that fits entirely
3361 in a single register or a pair of registers. */
3362 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3363 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3365 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3366 float_argreg
, phex (regval
, reglen
));
3367 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3370 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3371 argreg
, phex (regval
, reglen
));
3372 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3377 regval
= extract_unsigned_integer (val
+ reglen
,
3378 reglen
, byte_order
);
3380 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3381 float_argreg
, phex (regval
, reglen
));
3382 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3385 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3386 argreg
, phex (regval
, reglen
));
3387 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3394 /* Copy the argument to general registers or the stack in
3395 register-sized pieces. Large arguments are split between
3396 registers and stack. */
3397 /* For N32/N64, structs, unions, or other composite types are
3398 treated as a sequence of doublewords, and are passed in integer
3399 or floating point registers as though they were simple scalar
3400 parameters to the extent that they fit, with any excess on the
3401 stack packed according to the normal memory layout of the
3403 The caller does not reserve space for the register arguments;
3404 the callee is responsible for reserving it if required. */
3405 /* Note: Floating-point values that didn't fit into an FP
3406 register are only written to memory. */
3409 /* Remember if the argument was written to the stack. */
3410 int stack_used_p
= 0;
3411 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3414 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3417 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3418 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3420 /* Write this portion of the argument to the stack. */
3421 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3423 /* Should shorter than int integer values be
3424 promoted to int before being stored? */
3425 int longword_offset
= 0;
3428 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3430 if ((typecode
== TYPE_CODE_INT
3431 || typecode
== TYPE_CODE_PTR
)
3433 longword_offset
= MIPS64_REGSIZE
- len
;
3438 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3439 paddress (gdbarch
, stack_offset
));
3440 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3441 paddress (gdbarch
, longword_offset
));
3444 addr
= sp
+ stack_offset
+ longword_offset
;
3449 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3450 paddress (gdbarch
, addr
));
3451 for (i
= 0; i
< partial_len
; i
++)
3453 fprintf_unfiltered (gdb_stdlog
, "%02x",
3457 write_memory (addr
, val
, partial_len
);
3460 /* Note!!! This is NOT an else clause. Odd sized
3461 structs may go thru BOTH paths. */
3462 /* Write this portion of the argument to a general
3463 purpose register. */
3464 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3468 /* Sign extend pointers, 32-bit integers and signed
3469 16-bit and 8-bit integers; everything else is taken
3472 if ((partial_len
== 4
3473 && (typecode
== TYPE_CODE_PTR
3474 || typecode
== TYPE_CODE_INT
))
3476 && typecode
== TYPE_CODE_INT
3477 && !TYPE_UNSIGNED (arg_type
)))
3478 regval
= extract_signed_integer (val
, partial_len
,
3481 regval
= extract_unsigned_integer (val
, partial_len
,
3484 /* A non-floating-point argument being passed in a
3485 general register. If a struct or union, and if
3486 the remaining length is smaller than the register
3487 size, we have to adjust the register value on
3490 It does not seem to be necessary to do the
3491 same for integral types. */
3493 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3494 && partial_len
< MIPS64_REGSIZE
3495 && (typecode
== TYPE_CODE_STRUCT
3496 || typecode
== TYPE_CODE_UNION
))
3497 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3501 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3503 phex (regval
, MIPS64_REGSIZE
));
3504 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3506 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3507 TYPE_LENGTH (arg_type
) - len
))
3510 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3512 phex (regval
, MIPS64_REGSIZE
));
3513 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3524 /* Compute the offset into the stack at which we will
3525 copy the next parameter.
3527 In N32 (N64?), the stack_offset only needs to be
3528 adjusted when it has been used. */
3531 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3535 fprintf_unfiltered (gdb_stdlog
, "\n");
3538 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3540 /* Return adjusted stack pointer. */
3544 static enum return_value_convention
3545 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3546 struct type
*type
, struct regcache
*regcache
,
3547 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3549 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3551 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3553 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3554 if needed), as appropriate for the type. Composite results (struct,
3555 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3558 * A struct with only one or two floating point fields is returned in $f0
3559 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3562 * Any other composite results of at most 128 bits are returned in
3563 $2 (first 64 bits) and $3 (remainder, if necessary).
3565 * Larger composite results are handled by converting the function to a
3566 procedure with an implicit first parameter, which is a pointer to an area
3567 reserved by the caller to receive the result. [The o32-bit ABI requires
3568 that all composite results be handled by conversion to implicit first
3569 parameters. The MIPS/SGI Fortran implementation has always made a
3570 specific exception to return COMPLEX results in the floating point
3573 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3574 return RETURN_VALUE_STRUCT_CONVENTION
;
3575 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3576 && TYPE_LENGTH (type
) == 16
3577 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3579 /* A 128-bit floating-point value fills both $f0 and $f2. The
3580 two registers are used in the same as memory order, so the
3581 eight bytes with the lower memory address are in $f0. */
3583 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3584 mips_xfer_register (gdbarch
, regcache
,
3585 gdbarch_num_regs (gdbarch
)
3586 + mips_regnum (gdbarch
)->fp0
,
3587 8, gdbarch_byte_order (gdbarch
),
3588 readbuf
, writebuf
, 0);
3589 mips_xfer_register (gdbarch
, regcache
,
3590 gdbarch_num_regs (gdbarch
)
3591 + mips_regnum (gdbarch
)->fp0
+ 2,
3592 8, gdbarch_byte_order (gdbarch
),
3593 readbuf
? readbuf
+ 8 : readbuf
,
3594 writebuf
? writebuf
+ 8 : writebuf
, 0);
3595 return RETURN_VALUE_REGISTER_CONVENTION
;
3597 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3598 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3600 /* A single or double floating-point value that fits in FP0. */
3602 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3603 mips_xfer_register (gdbarch
, regcache
,
3604 gdbarch_num_regs (gdbarch
)
3605 + mips_regnum (gdbarch
)->fp0
,
3607 gdbarch_byte_order (gdbarch
),
3608 readbuf
, writebuf
, 0);
3609 return RETURN_VALUE_REGISTER_CONVENTION
;
3611 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3612 && TYPE_NFIELDS (type
) <= 2
3613 && TYPE_NFIELDS (type
) >= 1
3614 && ((TYPE_NFIELDS (type
) == 1
3615 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3617 || (TYPE_NFIELDS (type
) == 2
3618 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3620 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3621 == TYPE_CODE_FLT
))))
3623 /* A struct that contains one or two floats. Each value is part
3624 in the least significant part of their floating point
3625 register (or GPR, for soft float). */
3628 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3629 ? mips_regnum (gdbarch
)->fp0
3631 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3633 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3636 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3638 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3640 /* A 16-byte long double field goes in two consecutive
3642 mips_xfer_register (gdbarch
, regcache
,
3643 gdbarch_num_regs (gdbarch
) + regnum
,
3645 gdbarch_byte_order (gdbarch
),
3646 readbuf
, writebuf
, offset
);
3647 mips_xfer_register (gdbarch
, regcache
,
3648 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3650 gdbarch_byte_order (gdbarch
),
3651 readbuf
, writebuf
, offset
+ 8);
3654 mips_xfer_register (gdbarch
, regcache
,
3655 gdbarch_num_regs (gdbarch
) + regnum
,
3656 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3657 gdbarch_byte_order (gdbarch
),
3658 readbuf
, writebuf
, offset
);
3660 return RETURN_VALUE_REGISTER_CONVENTION
;
3662 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3663 || TYPE_CODE (type
) == TYPE_CODE_UNION
3664 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3666 /* A composite type. Extract the left justified value,
3667 regardless of the byte order. I.e. DO NOT USE
3671 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3672 offset
< TYPE_LENGTH (type
);
3673 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3675 int xfer
= register_size (gdbarch
, regnum
);
3676 if (offset
+ xfer
> TYPE_LENGTH (type
))
3677 xfer
= TYPE_LENGTH (type
) - offset
;
3679 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3680 offset
, xfer
, regnum
);
3681 mips_xfer_register (gdbarch
, regcache
,
3682 gdbarch_num_regs (gdbarch
) + regnum
,
3683 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3686 return RETURN_VALUE_REGISTER_CONVENTION
;
3690 /* A scalar extract each part but least-significant-byte
3694 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3695 offset
< TYPE_LENGTH (type
);
3696 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3698 int xfer
= register_size (gdbarch
, regnum
);
3699 if (offset
+ xfer
> TYPE_LENGTH (type
))
3700 xfer
= TYPE_LENGTH (type
) - offset
;
3702 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3703 offset
, xfer
, regnum
);
3704 mips_xfer_register (gdbarch
, regcache
,
3705 gdbarch_num_regs (gdbarch
) + regnum
,
3706 xfer
, gdbarch_byte_order (gdbarch
),
3707 readbuf
, writebuf
, offset
);
3709 return RETURN_VALUE_REGISTER_CONVENTION
;
3713 /* O32 ABI stuff. */
3716 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3717 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3718 int nargs
, struct value
**args
, CORE_ADDR sp
,
3719 int struct_return
, CORE_ADDR struct_addr
)
3725 int stack_offset
= 0;
3726 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3727 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3728 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3730 /* For shared libraries, "t9" needs to point at the function
3732 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3734 /* Set the return address register to point to the entry point of
3735 the program, where a breakpoint lies in wait. */
3736 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3738 /* First ensure that the stack and structure return address (if any)
3739 are properly aligned. The stack has to be at least 64-bit
3740 aligned even on 32-bit machines, because doubles must be 64-bit
3741 aligned. For n32 and n64, stack frames need to be 128-bit
3742 aligned, so we round to this widest known alignment. */
3744 sp
= align_down (sp
, 16);
3745 struct_addr
= align_down (struct_addr
, 16);
3747 /* Now make space on the stack for the args. */
3748 for (argnum
= 0; argnum
< nargs
; argnum
++)
3750 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3751 int arglen
= TYPE_LENGTH (arg_type
);
3753 /* Align to double-word if necessary. */
3754 if (mips_type_needs_double_align (arg_type
))
3755 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3756 /* Allocate space on the stack. */
3757 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3759 sp
-= align_up (len
, 16);
3762 fprintf_unfiltered (gdb_stdlog
,
3763 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3764 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3766 /* Initialize the integer and float register pointers. */
3767 argreg
= MIPS_A0_REGNUM
;
3768 float_argreg
= mips_fpa0_regnum (gdbarch
);
3770 /* The struct_return pointer occupies the first parameter-passing reg. */
3774 fprintf_unfiltered (gdb_stdlog
,
3775 "mips_o32_push_dummy_call: "
3776 "struct_return reg=%d %s\n",
3777 argreg
, paddress (gdbarch
, struct_addr
));
3778 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3779 stack_offset
+= MIPS32_REGSIZE
;
3782 /* Now load as many as possible of the first arguments into
3783 registers, and push the rest onto the stack. Loop thru args
3784 from first to last. */
3785 for (argnum
= 0; argnum
< nargs
; argnum
++)
3787 const gdb_byte
*val
;
3788 struct value
*arg
= args
[argnum
];
3789 struct type
*arg_type
= check_typedef (value_type (arg
));
3790 int len
= TYPE_LENGTH (arg_type
);
3791 enum type_code typecode
= TYPE_CODE (arg_type
);
3794 fprintf_unfiltered (gdb_stdlog
,
3795 "mips_o32_push_dummy_call: %d len=%d type=%d",
3796 argnum
+ 1, len
, (int) typecode
);
3798 val
= value_contents (arg
);
3800 /* 32-bit ABIs always start floating point arguments in an
3801 even-numbered floating point register. Round the FP register
3802 up before the check to see if there are any FP registers
3803 left. O32/O64 targets also pass the FP in the integer
3804 registers so also round up normal registers. */
3805 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3807 if ((float_argreg
& 1))
3811 /* Floating point arguments passed in registers have to be
3812 treated specially. On 32-bit architectures, doubles
3813 are passed in register pairs; the even register gets
3814 the low word, and the odd register gets the high word.
3815 On O32/O64, the first two floating point arguments are
3816 also copied to general registers, because MIPS16 functions
3817 don't use float registers for arguments. This duplication of
3818 arguments in general registers can't hurt non-MIPS16 functions
3819 because those registers are normally skipped. */
3821 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3822 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3824 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3826 int low_offset
= gdbarch_byte_order (gdbarch
)
3827 == BFD_ENDIAN_BIG
? 4 : 0;
3828 unsigned long regval
;
3830 /* Write the low word of the double to the even register(s). */
3831 regval
= extract_unsigned_integer (val
+ low_offset
,
3834 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3835 float_argreg
, phex (regval
, 4));
3836 regcache_cooked_write_unsigned (regcache
,
3837 float_argreg
++, regval
);
3839 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3840 argreg
, phex (regval
, 4));
3841 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3843 /* Write the high word of the double to the odd register(s). */
3844 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3847 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3848 float_argreg
, phex (regval
, 4));
3849 regcache_cooked_write_unsigned (regcache
,
3850 float_argreg
++, regval
);
3853 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3854 argreg
, phex (regval
, 4));
3855 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3859 /* This is a floating point value that fits entirely
3860 in a single register. */
3861 /* On 32 bit ABI's the float_argreg is further adjusted
3862 above to ensure that it is even register aligned. */
3863 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3865 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3866 float_argreg
, phex (regval
, len
));
3867 regcache_cooked_write_unsigned (regcache
,
3868 float_argreg
++, regval
);
3869 /* Although two FP registers are reserved for each
3870 argument, only one corresponding integer register is
3873 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3874 argreg
, phex (regval
, len
));
3875 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3877 /* Reserve space for the FP register. */
3878 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3882 /* Copy the argument to general registers or the stack in
3883 register-sized pieces. Large arguments are split between
3884 registers and stack. */
3885 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3886 are treated specially: Irix cc passes
3887 them in registers where gcc sometimes puts them on the
3888 stack. For maximum compatibility, we will put them in
3890 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3891 && len
% MIPS32_REGSIZE
!= 0);
3892 /* Structures should be aligned to eight bytes (even arg registers)
3893 on MIPS_ABI_O32, if their first member has double precision. */
3894 if (mips_type_needs_double_align (arg_type
))
3899 stack_offset
+= MIPS32_REGSIZE
;
3904 /* Remember if the argument was written to the stack. */
3905 int stack_used_p
= 0;
3906 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3909 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3912 /* Write this portion of the argument to the stack. */
3913 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3914 || odd_sized_struct
)
3916 /* Should shorter than int integer values be
3917 promoted to int before being stored? */
3918 int longword_offset
= 0;
3924 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3925 paddress (gdbarch
, stack_offset
));
3926 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3927 paddress (gdbarch
, longword_offset
));
3930 addr
= sp
+ stack_offset
+ longword_offset
;
3935 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3936 paddress (gdbarch
, addr
));
3937 for (i
= 0; i
< partial_len
; i
++)
3939 fprintf_unfiltered (gdb_stdlog
, "%02x",
3943 write_memory (addr
, val
, partial_len
);
3946 /* Note!!! This is NOT an else clause. Odd sized
3947 structs may go thru BOTH paths. */
3948 /* Write this portion of the argument to a general
3949 purpose register. */
3950 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3952 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3954 /* Value may need to be sign extended, because
3955 mips_isa_regsize() != mips_abi_regsize(). */
3957 /* A non-floating-point argument being passed in a
3958 general register. If a struct or union, and if
3959 the remaining length is smaller than the register
3960 size, we have to adjust the register value on
3963 It does not seem to be necessary to do the
3964 same for integral types.
3966 Also don't do this adjustment on O64 binaries.
3968 cagney/2001-07-23: gdb/179: Also, GCC, when
3969 outputting LE O32 with sizeof (struct) <
3970 mips_abi_regsize(), generates a left shift
3971 as part of storing the argument in a register
3972 (the left shift isn't generated when
3973 sizeof (struct) >= mips_abi_regsize()). Since
3974 it is quite possible that this is GCC
3975 contradicting the LE/O32 ABI, GDB has not been
3976 adjusted to accommodate this. Either someone
3977 needs to demonstrate that the LE/O32 ABI
3978 specifies such a left shift OR this new ABI gets
3979 identified as such and GDB gets tweaked
3982 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3983 && partial_len
< MIPS32_REGSIZE
3984 && (typecode
== TYPE_CODE_STRUCT
3985 || typecode
== TYPE_CODE_UNION
))
3986 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3990 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3992 phex (regval
, MIPS32_REGSIZE
));
3993 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3996 /* Prevent subsequent floating point arguments from
3997 being passed in floating point registers. */
3998 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4004 /* Compute the offset into the stack at which we will
4005 copy the next parameter.
4007 In older ABIs, the caller reserved space for
4008 registers that contained arguments. This was loosely
4009 refered to as their "home". Consequently, space is
4010 always allocated. */
4012 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4016 fprintf_unfiltered (gdb_stdlog
, "\n");
4019 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4021 /* Return adjusted stack pointer. */
4025 static enum return_value_convention
4026 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4027 struct type
*type
, struct regcache
*regcache
,
4028 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4030 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4032 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4033 || TYPE_CODE (type
) == TYPE_CODE_UNION
4034 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4035 return RETURN_VALUE_STRUCT_CONVENTION
;
4036 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4037 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4039 /* A single-precision floating-point value. It fits in the
4040 least significant part of FP0. */
4042 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4043 mips_xfer_register (gdbarch
, regcache
,
4044 gdbarch_num_regs (gdbarch
)
4045 + mips_regnum (gdbarch
)->fp0
,
4047 gdbarch_byte_order (gdbarch
),
4048 readbuf
, writebuf
, 0);
4049 return RETURN_VALUE_REGISTER_CONVENTION
;
4051 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4052 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4054 /* A double-precision floating-point value. The most
4055 significant part goes in FP1, and the least significant in
4058 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4059 switch (gdbarch_byte_order (gdbarch
))
4061 case BFD_ENDIAN_LITTLE
:
4062 mips_xfer_register (gdbarch
, regcache
,
4063 gdbarch_num_regs (gdbarch
)
4064 + mips_regnum (gdbarch
)->fp0
+
4065 0, 4, gdbarch_byte_order (gdbarch
),
4066 readbuf
, writebuf
, 0);
4067 mips_xfer_register (gdbarch
, regcache
,
4068 gdbarch_num_regs (gdbarch
)
4069 + mips_regnum (gdbarch
)->fp0
+ 1,
4070 4, gdbarch_byte_order (gdbarch
),
4071 readbuf
, writebuf
, 4);
4073 case BFD_ENDIAN_BIG
:
4074 mips_xfer_register (gdbarch
, regcache
,
4075 gdbarch_num_regs (gdbarch
)
4076 + mips_regnum (gdbarch
)->fp0
+ 1,
4077 4, gdbarch_byte_order (gdbarch
),
4078 readbuf
, writebuf
, 0);
4079 mips_xfer_register (gdbarch
, regcache
,
4080 gdbarch_num_regs (gdbarch
)
4081 + mips_regnum (gdbarch
)->fp0
+ 0,
4082 4, gdbarch_byte_order (gdbarch
),
4083 readbuf
, writebuf
, 4);
4086 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4088 return RETURN_VALUE_REGISTER_CONVENTION
;
4091 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4092 && TYPE_NFIELDS (type
) <= 2
4093 && TYPE_NFIELDS (type
) >= 1
4094 && ((TYPE_NFIELDS (type
) == 1
4095 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4097 || (TYPE_NFIELDS (type
) == 2
4098 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4100 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4102 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4104 /* A struct that contains one or two floats. Each value is part
4105 in the least significant part of their floating point
4107 gdb_byte reg
[MAX_REGISTER_SIZE
];
4110 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4111 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4113 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4116 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4118 mips_xfer_register (gdbarch
, regcache
,
4119 gdbarch_num_regs (gdbarch
) + regnum
,
4120 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4121 gdbarch_byte_order (gdbarch
),
4122 readbuf
, writebuf
, offset
);
4124 return RETURN_VALUE_REGISTER_CONVENTION
;
4128 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4129 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4131 /* A structure or union. Extract the left justified value,
4132 regardless of the byte order. I.e. DO NOT USE
4136 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4137 offset
< TYPE_LENGTH (type
);
4138 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4140 int xfer
= register_size (gdbarch
, regnum
);
4141 if (offset
+ xfer
> TYPE_LENGTH (type
))
4142 xfer
= TYPE_LENGTH (type
) - offset
;
4144 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4145 offset
, xfer
, regnum
);
4146 mips_xfer_register (gdbarch
, regcache
,
4147 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4148 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4150 return RETURN_VALUE_REGISTER_CONVENTION
;
4155 /* A scalar extract each part but least-significant-byte
4156 justified. o32 thinks registers are 4 byte, regardless of
4160 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4161 offset
< TYPE_LENGTH (type
);
4162 offset
+= MIPS32_REGSIZE
, regnum
++)
4164 int xfer
= MIPS32_REGSIZE
;
4165 if (offset
+ xfer
> TYPE_LENGTH (type
))
4166 xfer
= TYPE_LENGTH (type
) - offset
;
4168 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4169 offset
, xfer
, regnum
);
4170 mips_xfer_register (gdbarch
, regcache
,
4171 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4172 gdbarch_byte_order (gdbarch
),
4173 readbuf
, writebuf
, offset
);
4175 return RETURN_VALUE_REGISTER_CONVENTION
;
4179 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4183 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4184 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4186 struct value
**args
, CORE_ADDR sp
,
4187 int struct_return
, CORE_ADDR struct_addr
)
4193 int stack_offset
= 0;
4194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4195 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4196 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4198 /* For shared libraries, "t9" needs to point at the function
4200 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4202 /* Set the return address register to point to the entry point of
4203 the program, where a breakpoint lies in wait. */
4204 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4206 /* First ensure that the stack and structure return address (if any)
4207 are properly aligned. The stack has to be at least 64-bit
4208 aligned even on 32-bit machines, because doubles must be 64-bit
4209 aligned. For n32 and n64, stack frames need to be 128-bit
4210 aligned, so we round to this widest known alignment. */
4212 sp
= align_down (sp
, 16);
4213 struct_addr
= align_down (struct_addr
, 16);
4215 /* Now make space on the stack for the args. */
4216 for (argnum
= 0; argnum
< nargs
; argnum
++)
4218 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4219 int arglen
= TYPE_LENGTH (arg_type
);
4221 /* Allocate space on the stack. */
4222 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4224 sp
-= align_up (len
, 16);
4227 fprintf_unfiltered (gdb_stdlog
,
4228 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4229 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4231 /* Initialize the integer and float register pointers. */
4232 argreg
= MIPS_A0_REGNUM
;
4233 float_argreg
= mips_fpa0_regnum (gdbarch
);
4235 /* The struct_return pointer occupies the first parameter-passing reg. */
4239 fprintf_unfiltered (gdb_stdlog
,
4240 "mips_o64_push_dummy_call: "
4241 "struct_return reg=%d %s\n",
4242 argreg
, paddress (gdbarch
, struct_addr
));
4243 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4244 stack_offset
+= MIPS64_REGSIZE
;
4247 /* Now load as many as possible of the first arguments into
4248 registers, and push the rest onto the stack. Loop thru args
4249 from first to last. */
4250 for (argnum
= 0; argnum
< nargs
; argnum
++)
4252 const gdb_byte
*val
;
4253 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4254 struct value
*arg
= args
[argnum
];
4255 struct type
*arg_type
= check_typedef (value_type (arg
));
4256 int len
= TYPE_LENGTH (arg_type
);
4257 enum type_code typecode
= TYPE_CODE (arg_type
);
4260 fprintf_unfiltered (gdb_stdlog
,
4261 "mips_o64_push_dummy_call: %d len=%d type=%d",
4262 argnum
+ 1, len
, (int) typecode
);
4264 val
= value_contents (arg
);
4266 /* Function pointer arguments to mips16 code need to be made into
4268 if (typecode
== TYPE_CODE_PTR
4269 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4271 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4273 if (mips_pc_is_mips16 (addr
))
4275 store_signed_integer (valbuf
, len
, byte_order
,
4276 make_mips16_addr (addr
));
4281 /* Floating point arguments passed in registers have to be
4282 treated specially. On 32-bit architectures, doubles
4283 are passed in register pairs; the even register gets
4284 the low word, and the odd register gets the high word.
4285 On O32/O64, the first two floating point arguments are
4286 also copied to general registers, because MIPS16 functions
4287 don't use float registers for arguments. This duplication of
4288 arguments in general registers can't hurt non-MIPS16 functions
4289 because those registers are normally skipped. */
4291 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4292 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4294 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4296 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4297 float_argreg
, phex (regval
, len
));
4298 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4300 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4301 argreg
, phex (regval
, len
));
4302 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4304 /* Reserve space for the FP register. */
4305 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4309 /* Copy the argument to general registers or the stack in
4310 register-sized pieces. Large arguments are split between
4311 registers and stack. */
4312 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4313 are treated specially: Irix cc passes them in registers
4314 where gcc sometimes puts them on the stack. For maximum
4315 compatibility, we will put them in both places. */
4316 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4317 && len
% MIPS64_REGSIZE
!= 0);
4320 /* Remember if the argument was written to the stack. */
4321 int stack_used_p
= 0;
4322 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4325 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4328 /* Write this portion of the argument to the stack. */
4329 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4330 || odd_sized_struct
)
4332 /* Should shorter than int integer values be
4333 promoted to int before being stored? */
4334 int longword_offset
= 0;
4337 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4339 if ((typecode
== TYPE_CODE_INT
4340 || typecode
== TYPE_CODE_PTR
4341 || typecode
== TYPE_CODE_FLT
)
4343 longword_offset
= MIPS64_REGSIZE
- len
;
4348 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4349 paddress (gdbarch
, stack_offset
));
4350 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4351 paddress (gdbarch
, longword_offset
));
4354 addr
= sp
+ stack_offset
+ longword_offset
;
4359 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4360 paddress (gdbarch
, addr
));
4361 for (i
= 0; i
< partial_len
; i
++)
4363 fprintf_unfiltered (gdb_stdlog
, "%02x",
4367 write_memory (addr
, val
, partial_len
);
4370 /* Note!!! This is NOT an else clause. Odd sized
4371 structs may go thru BOTH paths. */
4372 /* Write this portion of the argument to a general
4373 purpose register. */
4374 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4376 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4378 /* Value may need to be sign extended, because
4379 mips_isa_regsize() != mips_abi_regsize(). */
4381 /* A non-floating-point argument being passed in a
4382 general register. If a struct or union, and if
4383 the remaining length is smaller than the register
4384 size, we have to adjust the register value on
4387 It does not seem to be necessary to do the
4388 same for integral types. */
4390 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4391 && partial_len
< MIPS64_REGSIZE
4392 && (typecode
== TYPE_CODE_STRUCT
4393 || typecode
== TYPE_CODE_UNION
))
4394 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4398 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4400 phex (regval
, MIPS64_REGSIZE
));
4401 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4404 /* Prevent subsequent floating point arguments from
4405 being passed in floating point registers. */
4406 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4412 /* Compute the offset into the stack at which we will
4413 copy the next parameter.
4415 In older ABIs, the caller reserved space for
4416 registers that contained arguments. This was loosely
4417 refered to as their "home". Consequently, space is
4418 always allocated. */
4420 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4424 fprintf_unfiltered (gdb_stdlog
, "\n");
4427 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4429 /* Return adjusted stack pointer. */
4433 static enum return_value_convention
4434 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4435 struct type
*type
, struct regcache
*regcache
,
4436 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4438 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4440 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4441 || TYPE_CODE (type
) == TYPE_CODE_UNION
4442 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4443 return RETURN_VALUE_STRUCT_CONVENTION
;
4444 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4446 /* A floating-point value. It fits in the least significant
4449 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4450 mips_xfer_register (gdbarch
, regcache
,
4451 gdbarch_num_regs (gdbarch
)
4452 + mips_regnum (gdbarch
)->fp0
,
4454 gdbarch_byte_order (gdbarch
),
4455 readbuf
, writebuf
, 0);
4456 return RETURN_VALUE_REGISTER_CONVENTION
;
4460 /* A scalar extract each part but least-significant-byte
4464 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4465 offset
< TYPE_LENGTH (type
);
4466 offset
+= MIPS64_REGSIZE
, regnum
++)
4468 int xfer
= MIPS64_REGSIZE
;
4469 if (offset
+ xfer
> TYPE_LENGTH (type
))
4470 xfer
= TYPE_LENGTH (type
) - offset
;
4472 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4473 offset
, xfer
, regnum
);
4474 mips_xfer_register (gdbarch
, regcache
,
4475 gdbarch_num_regs (gdbarch
) + regnum
,
4476 xfer
, gdbarch_byte_order (gdbarch
),
4477 readbuf
, writebuf
, offset
);
4479 return RETURN_VALUE_REGISTER_CONVENTION
;
4483 /* Floating point register management.
4485 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4486 64bit operations, these early MIPS cpus treat fp register pairs
4487 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4488 registers and offer a compatibility mode that emulates the MIPS2 fp
4489 model. When operating in MIPS2 fp compat mode, later cpu's split
4490 double precision floats into two 32-bit chunks and store them in
4491 consecutive fp regs. To display 64-bit floats stored in this
4492 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4493 Throw in user-configurable endianness and you have a real mess.
4495 The way this works is:
4496 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4497 double-precision value will be split across two logical registers.
4498 The lower-numbered logical register will hold the low-order bits,
4499 regardless of the processor's endianness.
4500 - If we are on a 64-bit processor, and we are looking for a
4501 single-precision value, it will be in the low ordered bits
4502 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4503 save slot in memory.
4504 - If we are in 64-bit mode, everything is straightforward.
4506 Note that this code only deals with "live" registers at the top of the
4507 stack. We will attempt to deal with saved registers later, when
4508 the raw/cooked register interface is in place. (We need a general
4509 interface that can deal with dynamic saved register sizes -- fp
4510 regs could be 32 bits wide in one frame and 64 on the frame above
4513 /* Copy a 32-bit single-precision value from the current frame
4514 into rare_buffer. */
4517 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4518 gdb_byte
*rare_buffer
)
4520 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4521 int raw_size
= register_size (gdbarch
, regno
);
4522 gdb_byte
*raw_buffer
= alloca (raw_size
);
4524 if (!frame_register_read (frame
, regno
, raw_buffer
))
4525 error (_("can't read register %d (%s)"),
4526 regno
, gdbarch_register_name (gdbarch
, regno
));
4529 /* We have a 64-bit value for this register. Find the low-order
4533 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4538 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4542 memcpy (rare_buffer
, raw_buffer
, 4);
4546 /* Copy a 64-bit double-precision value from the current frame into
4547 rare_buffer. This may include getting half of it from the next
4551 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4552 gdb_byte
*rare_buffer
)
4554 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4555 int raw_size
= register_size (gdbarch
, regno
);
4557 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4559 /* We have a 64-bit value for this register, and we should use
4561 if (!frame_register_read (frame
, regno
, rare_buffer
))
4562 error (_("can't read register %d (%s)"),
4563 regno
, gdbarch_register_name (gdbarch
, regno
));
4567 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4569 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4570 internal_error (__FILE__
, __LINE__
,
4571 _("mips_read_fp_register_double: bad access to "
4572 "odd-numbered FP register"));
4574 /* mips_read_fp_register_single will find the correct 32 bits from
4576 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4578 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4579 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4583 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4584 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4590 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4592 { /* Do values for FP (float) regs. */
4593 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4594 gdb_byte
*raw_buffer
;
4595 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4598 raw_buffer
= alloca (2 * register_size (gdbarch
,
4599 mips_regnum (gdbarch
)->fp0
));
4601 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4602 fprintf_filtered (file
, "%*s",
4603 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4606 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4608 struct value_print_options opts
;
4610 /* 4-byte registers: Print hex and floating. Also print even
4611 numbered registers as doubles. */
4612 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4613 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4616 get_formatted_print_options (&opts
, 'x');
4617 print_scalar_formatted (raw_buffer
,
4618 builtin_type (gdbarch
)->builtin_uint32
,
4621 fprintf_filtered (file
, " flt: ");
4623 fprintf_filtered (file
, " <invalid float> ");
4625 fprintf_filtered (file
, "%-17.9g", flt1
);
4627 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4629 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4630 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4633 fprintf_filtered (file
, " dbl: ");
4635 fprintf_filtered (file
, "<invalid double>");
4637 fprintf_filtered (file
, "%-24.17g", doub
);
4642 struct value_print_options opts
;
4644 /* Eight byte registers: print each one as hex, float and double. */
4645 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4646 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4649 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4650 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4653 get_formatted_print_options (&opts
, 'x');
4654 print_scalar_formatted (raw_buffer
,
4655 builtin_type (gdbarch
)->builtin_uint64
,
4658 fprintf_filtered (file
, " flt: ");
4660 fprintf_filtered (file
, "<invalid float>");
4662 fprintf_filtered (file
, "%-17.9g", flt1
);
4664 fprintf_filtered (file
, " dbl: ");
4666 fprintf_filtered (file
, "<invalid double>");
4668 fprintf_filtered (file
, "%-24.17g", doub
);
4673 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4676 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4678 struct value_print_options opts
;
4681 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4683 mips_print_fp_register (file
, frame
, regnum
);
4687 val
= get_frame_register_value (frame
, regnum
);
4688 if (value_optimized_out (val
))
4690 fprintf_filtered (file
, "%s: [Invalid]",
4691 gdbarch_register_name (gdbarch
, regnum
));
4695 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4697 /* The problem with printing numeric register names (r26, etc.) is that
4698 the user can't use them on input. Probably the best solution is to
4699 fix it so that either the numeric or the funky (a2, etc.) names
4700 are accepted on input. */
4701 if (regnum
< MIPS_NUMREGS
)
4702 fprintf_filtered (file
, "(r%d): ", regnum
);
4704 fprintf_filtered (file
, ": ");
4706 get_formatted_print_options (&opts
, 'x');
4707 val_print_scalar_formatted (value_type (val
),
4708 value_contents_for_printing (val
),
4709 value_embedded_offset (val
),
4714 /* Replacement for generic do_registers_info.
4715 Print regs in pretty columns. */
4718 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4721 fprintf_filtered (file
, " ");
4722 mips_print_fp_register (file
, frame
, regnum
);
4723 fprintf_filtered (file
, "\n");
4728 /* Print a row's worth of GP (int) registers, with name labels above. */
4731 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4734 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4735 /* Do values for GP (int) regs. */
4736 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4737 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4742 /* For GP registers, we print a separate row of names above the vals. */
4743 for (col
= 0, regnum
= start_regnum
;
4744 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4745 + gdbarch_num_pseudo_regs (gdbarch
);
4748 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4749 continue; /* unused register */
4750 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4752 break; /* End the row: reached FP register. */
4753 /* Large registers are handled separately. */
4754 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4757 break; /* End the row before this register. */
4759 /* Print this register on a row by itself. */
4760 mips_print_register (file
, frame
, regnum
);
4761 fprintf_filtered (file
, "\n");
4765 fprintf_filtered (file
, " ");
4766 fprintf_filtered (file
,
4767 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4768 gdbarch_register_name (gdbarch
, regnum
));
4775 /* Print the R0 to R31 names. */
4776 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4777 fprintf_filtered (file
, "\n R%-4d",
4778 start_regnum
% gdbarch_num_regs (gdbarch
));
4780 fprintf_filtered (file
, "\n ");
4782 /* Now print the values in hex, 4 or 8 to the row. */
4783 for (col
= 0, regnum
= start_regnum
;
4784 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4785 + gdbarch_num_pseudo_regs (gdbarch
);
4788 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4789 continue; /* unused register */
4790 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4792 break; /* End row: reached FP register. */
4793 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4794 break; /* End row: large register. */
4796 /* OK: get the data in raw format. */
4797 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4798 error (_("can't read register %d (%s)"),
4799 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4800 /* pad small registers */
4802 byte
< (mips_abi_regsize (gdbarch
)
4803 - register_size (gdbarch
, regnum
)); byte
++)
4804 printf_filtered (" ");
4805 /* Now print the register value in hex, endian order. */
4806 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4808 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4809 byte
< register_size (gdbarch
, regnum
); byte
++)
4810 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4812 for (byte
= register_size (gdbarch
, regnum
) - 1;
4814 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4815 fprintf_filtered (file
, " ");
4818 if (col
> 0) /* ie. if we actually printed anything... */
4819 fprintf_filtered (file
, "\n");
4824 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4827 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4828 struct frame_info
*frame
, int regnum
, int all
)
4830 if (regnum
!= -1) /* Do one specified register. */
4832 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4833 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4834 error (_("Not a valid register for the current processor type"));
4836 mips_print_register (file
, frame
, regnum
);
4837 fprintf_filtered (file
, "\n");
4840 /* Do all (or most) registers. */
4842 regnum
= gdbarch_num_regs (gdbarch
);
4843 while (regnum
< gdbarch_num_regs (gdbarch
)
4844 + gdbarch_num_pseudo_regs (gdbarch
))
4846 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4849 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4850 regnum
= print_fp_register_row (file
, frame
, regnum
);
4852 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4855 regnum
= print_gp_register_row (file
, frame
, regnum
);
4860 /* Is this a branch with a delay slot? */
4863 is_delayed (unsigned long insn
)
4866 for (i
= 0; i
< NUMOPCODES
; ++i
)
4867 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4868 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4870 return (i
< NUMOPCODES
4871 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4872 | INSN_COND_BRANCH_DELAY
4873 | INSN_COND_BRANCH_LIKELY
)));
4877 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4878 struct frame_info
*frame
)
4880 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4881 CORE_ADDR pc
= get_frame_pc (frame
);
4882 gdb_byte buf
[MIPS_INSN32_SIZE
];
4884 /* There is no branch delay slot on MIPS16. */
4885 if (mips_pc_is_mips16 (pc
))
4888 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4891 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4892 /* If error reading memory, guess that it is not a delayed
4895 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4898 /* To skip prologues, I use this predicate. Returns either PC itself
4899 if the code at PC does not look like a function prologue; otherwise
4900 returns an address that (if we're lucky) follows the prologue. If
4901 LENIENT, then we must skip everything which is involved in setting
4902 up the frame (it's OK to skip more, just so long as we don't skip
4903 anything which might clobber the registers which are being saved.
4904 We must skip more in the case where part of the prologue is in the
4905 delay slot of a non-prologue instruction). */
4908 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4911 CORE_ADDR func_addr
;
4913 /* See if we can determine the end of the prologue via the symbol table.
4914 If so, then return either PC, or the PC after the prologue, whichever
4916 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4918 CORE_ADDR post_prologue_pc
4919 = skip_prologue_using_sal (gdbarch
, func_addr
);
4920 if (post_prologue_pc
!= 0)
4921 return max (pc
, post_prologue_pc
);
4924 /* Can't determine prologue from the symbol table, need to examine
4927 /* Find an upper limit on the function prologue using the debug
4928 information. If the debug information could not be used to provide
4929 that bound, then use an arbitrary large number as the upper bound. */
4930 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4932 limit_pc
= pc
+ 100; /* Magic. */
4934 if (mips_pc_is_mips16 (pc
))
4935 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4937 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4940 /* Check whether the PC is in a function epilogue (32-bit version).
4941 This is a helper function for mips_in_function_epilogue_p. */
4943 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4945 CORE_ADDR func_addr
= 0, func_end
= 0;
4947 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4949 /* The MIPS epilogue is max. 12 bytes long. */
4950 CORE_ADDR addr
= func_end
- 12;
4952 if (addr
< func_addr
+ 4)
4953 addr
= func_addr
+ 4;
4957 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4959 unsigned long high_word
;
4962 inst
= mips_fetch_instruction (gdbarch
, pc
);
4963 high_word
= (inst
>> 16) & 0xffff;
4965 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4966 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4967 && inst
!= 0x03e00008 /* jr $ra */
4968 && inst
!= 0x00000000) /* nop */
4978 /* Check whether the PC is in a function epilogue (16-bit version).
4979 This is a helper function for mips_in_function_epilogue_p. */
4981 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4983 CORE_ADDR func_addr
= 0, func_end
= 0;
4985 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4987 /* The MIPS epilogue is max. 12 bytes long. */
4988 CORE_ADDR addr
= func_end
- 12;
4990 if (addr
< func_addr
+ 4)
4991 addr
= func_addr
+ 4;
4995 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4997 unsigned short inst
;
4999 inst
= mips_fetch_instruction (gdbarch
, pc
);
5001 if ((inst
& 0xf800) == 0xf000) /* extend */
5004 if (inst
!= 0x6300 /* addiu $sp,offset */
5005 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5006 && inst
!= 0xe820 /* jr $ra */
5007 && inst
!= 0xe8a0 /* jrc $ra */
5008 && inst
!= 0x6500) /* nop */
5018 /* The epilogue is defined here as the area at the end of a function,
5019 after an instruction which destroys the function's stack frame. */
5021 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5023 if (mips_pc_is_mips16 (pc
))
5024 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5026 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5029 /* Root of all "set mips "/"show mips " commands. This will eventually be
5030 used for all MIPS-specific commands. */
5033 show_mips_command (char *args
, int from_tty
)
5035 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5039 set_mips_command (char *args
, int from_tty
)
5042 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5043 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5046 /* Commands to show/set the MIPS FPU type. */
5049 show_mipsfpu_command (char *args
, int from_tty
)
5053 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5056 ("The MIPS floating-point coprocessor is unknown "
5057 "because the current architecture is not MIPS.\n");
5061 switch (MIPS_FPU_TYPE (target_gdbarch
))
5063 case MIPS_FPU_SINGLE
:
5064 fpu
= "single-precision";
5066 case MIPS_FPU_DOUBLE
:
5067 fpu
= "double-precision";
5070 fpu
= "absent (none)";
5073 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5075 if (mips_fpu_type_auto
)
5076 printf_unfiltered ("The MIPS floating-point coprocessor "
5077 "is set automatically (currently %s)\n",
5081 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5086 set_mipsfpu_command (char *args
, int from_tty
)
5088 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5089 "\"single\",\"none\" or \"auto\".\n");
5090 show_mipsfpu_command (args
, from_tty
);
5094 set_mipsfpu_single_command (char *args
, int from_tty
)
5096 struct gdbarch_info info
;
5097 gdbarch_info_init (&info
);
5098 mips_fpu_type
= MIPS_FPU_SINGLE
;
5099 mips_fpu_type_auto
= 0;
5100 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5101 instead of relying on globals. Doing that would let generic code
5102 handle the search for this specific architecture. */
5103 if (!gdbarch_update_p (info
))
5104 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5108 set_mipsfpu_double_command (char *args
, int from_tty
)
5110 struct gdbarch_info info
;
5111 gdbarch_info_init (&info
);
5112 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5113 mips_fpu_type_auto
= 0;
5114 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5115 instead of relying on globals. Doing that would let generic code
5116 handle the search for this specific architecture. */
5117 if (!gdbarch_update_p (info
))
5118 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5122 set_mipsfpu_none_command (char *args
, int from_tty
)
5124 struct gdbarch_info info
;
5125 gdbarch_info_init (&info
);
5126 mips_fpu_type
= MIPS_FPU_NONE
;
5127 mips_fpu_type_auto
= 0;
5128 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5129 instead of relying on globals. Doing that would let generic code
5130 handle the search for this specific architecture. */
5131 if (!gdbarch_update_p (info
))
5132 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5136 set_mipsfpu_auto_command (char *args
, int from_tty
)
5138 mips_fpu_type_auto
= 1;
5141 /* Attempt to identify the particular processor model by reading the
5142 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5143 the relevant processor still exists (it dates back to '94) and
5144 secondly this is not the way to do this. The processor type should
5145 be set by forcing an architecture change. */
5148 deprecated_mips_set_processor_regs_hack (void)
5150 struct regcache
*regcache
= get_current_regcache ();
5151 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5155 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5156 if ((prid
& ~0xf) == 0x700)
5157 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5160 /* Just like reinit_frame_cache, but with the right arguments to be
5161 callable as an sfunc. */
5164 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5165 struct cmd_list_element
*c
)
5167 reinit_frame_cache ();
5171 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5173 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5174 disassembler needs to be able to locally determine the ISA, and
5175 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5177 if (mips_pc_is_mips16 (memaddr
))
5178 info
->mach
= bfd_mach_mips16
;
5180 /* Round down the instruction address to the appropriate boundary. */
5181 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5183 /* Set the disassembler options. */
5184 if (!info
->disassembler_options
)
5185 /* This string is not recognized explicitly by the disassembler,
5186 but it tells the disassembler to not try to guess the ABI from
5187 the bfd elf headers, such that, if the user overrides the ABI
5188 of a program linked as NewABI, the disassembly will follow the
5189 register naming conventions specified by the user. */
5190 info
->disassembler_options
= "gpr-names=32";
5192 /* Call the appropriate disassembler based on the target endian-ness. */
5193 if (info
->endian
== BFD_ENDIAN_BIG
)
5194 return print_insn_big_mips (memaddr
, info
);
5196 return print_insn_little_mips (memaddr
, info
);
5200 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5202 /* Set up the disassembler info, so that we get the right
5203 register names from libopcodes. */
5204 info
->disassembler_options
= "gpr-names=n32";
5205 info
->flavour
= bfd_target_elf_flavour
;
5207 return gdb_print_insn_mips (memaddr
, info
);
5211 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5213 /* Set up the disassembler info, so that we get the right
5214 register names from libopcodes. */
5215 info
->disassembler_options
= "gpr-names=64";
5216 info
->flavour
= bfd_target_elf_flavour
;
5218 return gdb_print_insn_mips (memaddr
, info
);
5221 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5222 program counter value to determine whether a 16- or 32-bit breakpoint
5223 should be used. It returns a pointer to a string of bytes that encode a
5224 breakpoint instruction, stores the length of the string to *lenptr, and
5225 adjusts pc (if necessary) to point to the actual memory location where
5226 the breakpoint should be inserted. */
5228 static const gdb_byte
*
5229 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5230 CORE_ADDR
*pcptr
, int *lenptr
)
5232 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5234 if (mips_pc_is_mips16 (*pcptr
))
5236 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5237 *pcptr
= unmake_mips16_addr (*pcptr
);
5238 *lenptr
= sizeof (mips16_big_breakpoint
);
5239 return mips16_big_breakpoint
;
5243 /* The IDT board uses an unusual breakpoint value, and
5244 sometimes gets confused when it sees the usual MIPS
5245 breakpoint instruction. */
5246 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5247 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5248 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5249 /* Likewise, IRIX appears to expect a different breakpoint,
5250 although this is not apparent until you try to use pthreads. */
5251 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5253 *lenptr
= sizeof (big_breakpoint
);
5255 if (strcmp (target_shortname
, "mips") == 0)
5256 return idt_big_breakpoint
;
5257 else if (strcmp (target_shortname
, "ddb") == 0
5258 || strcmp (target_shortname
, "pmon") == 0
5259 || strcmp (target_shortname
, "lsi") == 0)
5260 return pmon_big_breakpoint
;
5261 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5262 return irix_big_breakpoint
;
5264 return big_breakpoint
;
5269 if (mips_pc_is_mips16 (*pcptr
))
5271 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5272 *pcptr
= unmake_mips16_addr (*pcptr
);
5273 *lenptr
= sizeof (mips16_little_breakpoint
);
5274 return mips16_little_breakpoint
;
5278 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5279 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5280 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5282 *lenptr
= sizeof (little_breakpoint
);
5284 if (strcmp (target_shortname
, "mips") == 0)
5285 return idt_little_breakpoint
;
5286 else if (strcmp (target_shortname
, "ddb") == 0
5287 || strcmp (target_shortname
, "pmon") == 0
5288 || strcmp (target_shortname
, "lsi") == 0)
5289 return pmon_little_breakpoint
;
5291 return little_breakpoint
;
5296 /* If PC is in a mips16 call or return stub, return the address of the target
5297 PC, which is either the callee or the caller. There are several
5298 cases which must be handled:
5300 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5301 target PC is in $31 ($ra).
5302 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5303 and the target PC is in $2.
5304 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5305 before the jal instruction, this is effectively a call stub
5306 and the target PC is in $2. Otherwise this is effectively
5307 a return stub and the target PC is in $18.
5309 See the source code for the stubs in gcc/config/mips/mips16.S for
5313 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5315 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5317 CORE_ADDR start_addr
;
5319 /* Find the starting address and name of the function containing the PC. */
5320 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5323 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5324 target PC is in $31 ($ra). */
5325 if (strcmp (name
, "__mips16_ret_sf") == 0
5326 || strcmp (name
, "__mips16_ret_df") == 0)
5327 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5329 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5331 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5332 and the target PC is in $2. */
5333 if (name
[19] >= '0' && name
[19] <= '9')
5334 return get_frame_register_signed (frame
, 2);
5336 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5337 before the jal instruction, this is effectively a call stub
5338 and the target PC is in $2. Otherwise this is effectively
5339 a return stub and the target PC is in $18. */
5340 else if (name
[19] == 's' || name
[19] == 'd')
5342 if (pc
== start_addr
)
5344 /* Check if the target of the stub is a compiler-generated
5345 stub. Such a stub for a function bar might have a name
5346 like __fn_stub_bar, and might look like this:
5351 la $1,bar (becomes a lui/addiu pair)
5353 So scan down to the lui/addi and extract the target
5354 address from those two instructions. */
5356 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5359 /* See if the name of the target function is __fn_stub_*. */
5360 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5363 if (strncmp (name
, "__fn_stub_", 10) != 0
5364 && strcmp (name
, "etext") != 0
5365 && strcmp (name
, "_etext") != 0)
5368 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5369 The limit on the search is arbitrarily set to 20
5370 instructions. FIXME. */
5371 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5373 ULONGEST inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5374 CORE_ADDR addr
= inst
;
5376 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5377 pc
= (((addr
& 0xffff) ^ 0x8000) - 0x8000) << 16;
5379 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5380 return pc
+ ((addr
& 0xffff) ^ 0x8000) - 0x8000;
5384 /* Couldn't find the lui/addui pair, so return stub address. */
5388 /* This is the 'return' part of a call stub. The return
5389 address is in $r18. */
5390 return get_frame_register_signed (frame
, 18);
5393 return 0; /* not a stub */
5396 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5397 PC of the stub target. The stub just loads $t9 and jumps to it,
5398 so that $t9 has the correct value at function entry. */
5401 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5403 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5404 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5405 struct minimal_symbol
*msym
;
5407 gdb_byte stub_code
[16];
5408 int32_t stub_words
[4];
5410 /* The stub for foo is named ".pic.foo", and is either two
5411 instructions inserted before foo or a three instruction sequence
5412 which jumps to foo. */
5413 msym
= lookup_minimal_symbol_by_pc (pc
);
5415 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5416 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5417 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5420 /* A two-instruction header. */
5421 if (MSYMBOL_SIZE (msym
) == 8)
5424 /* A three-instruction (plus delay slot) trampoline. */
5425 if (MSYMBOL_SIZE (msym
) == 16)
5427 if (target_read_memory (pc
, stub_code
, 16) != 0)
5429 for (i
= 0; i
< 4; i
++)
5430 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5433 /* A stub contains these instructions:
5436 addiu t9, t9, %lo(target)
5439 This works even for N64, since stubs are only generated with
5441 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5442 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5443 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5444 && stub_words
[3] == 0x00000000)
5445 return (((stub_words
[0] & 0x0000ffff) << 16)
5446 + (stub_words
[2] & 0x0000ffff));
5449 /* Not a recognized stub. */
5454 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5456 CORE_ADDR target_pc
;
5458 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5462 target_pc
= find_solib_trampoline_target (frame
, pc
);
5466 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5473 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5474 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5477 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5480 if (num
>= 0 && num
< 32)
5482 else if (num
>= 38 && num
< 70)
5483 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5485 regnum
= mips_regnum (gdbarch
)->hi
;
5487 regnum
= mips_regnum (gdbarch
)->lo
;
5489 /* This will hopefully (eventually) provoke a warning. Should
5490 we be calling complaint() here? */
5491 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5492 return gdbarch_num_regs (gdbarch
) + regnum
;
5496 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5497 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5500 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5503 if (num
>= 0 && num
< 32)
5505 else if (num
>= 32 && num
< 64)
5506 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5508 regnum
= mips_regnum (gdbarch
)->hi
;
5510 regnum
= mips_regnum (gdbarch
)->lo
;
5512 /* This will hopefully (eventually) provoke a warning. Should we
5513 be calling complaint() here? */
5514 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5515 return gdbarch_num_regs (gdbarch
) + regnum
;
5519 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5521 /* Only makes sense to supply raw registers. */
5522 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5523 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5524 decide if it is valid. Should instead define a standard sim/gdb
5525 register numbering scheme. */
5526 if (gdbarch_register_name (gdbarch
,
5527 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5528 && gdbarch_register_name (gdbarch
,
5529 gdbarch_num_regs (gdbarch
)
5530 + regnum
)[0] != '\0')
5533 return LEGACY_SIM_REGNO_IGNORE
;
5537 /* Convert an integer into an address. Extracting the value signed
5538 guarantees a correctly sign extended address. */
5541 mips_integer_to_address (struct gdbarch
*gdbarch
,
5542 struct type
*type
, const gdb_byte
*buf
)
5544 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5545 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5548 /* Dummy virtual frame pointer method. This is no more or less accurate
5549 than most other architectures; we just need to be explicit about it,
5550 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5551 an assertion failure. */
5554 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5555 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5557 *reg
= MIPS_SP_REGNUM
;
5562 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5564 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5565 const char *name
= bfd_get_section_name (abfd
, sect
);
5567 if (*abip
!= MIPS_ABI_UNKNOWN
)
5570 if (strncmp (name
, ".mdebug.", 8) != 0)
5573 if (strcmp (name
, ".mdebug.abi32") == 0)
5574 *abip
= MIPS_ABI_O32
;
5575 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5576 *abip
= MIPS_ABI_N32
;
5577 else if (strcmp (name
, ".mdebug.abi64") == 0)
5578 *abip
= MIPS_ABI_N64
;
5579 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5580 *abip
= MIPS_ABI_O64
;
5581 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5582 *abip
= MIPS_ABI_EABI32
;
5583 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5584 *abip
= MIPS_ABI_EABI64
;
5586 warning (_("unsupported ABI %s."), name
+ 8);
5590 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5592 int *lbp
= (int *) obj
;
5593 const char *name
= bfd_get_section_name (abfd
, sect
);
5595 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5597 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5599 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5600 warning (_("unrecognized .gcc_compiled_longXX"));
5603 static enum mips_abi
5604 global_mips_abi (void)
5608 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5609 if (mips_abi_strings
[i
] == mips_abi_string
)
5610 return (enum mips_abi
) i
;
5612 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5616 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5618 /* If the size matches the set of 32-bit or 64-bit integer registers,
5619 assume that's what we've got. */
5620 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5621 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5623 /* If the size matches the full set of registers GDB traditionally
5624 knows about, including floating point, for either 32-bit or
5625 64-bit, assume that's what we've got. */
5626 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5627 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5629 /* Otherwise we don't have a useful guess. */
5632 static struct value
*
5633 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5635 const int *reg_p
= baton
;
5636 return value_of_register (*reg_p
, frame
);
5639 static struct gdbarch
*
5640 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5642 struct gdbarch
*gdbarch
;
5643 struct gdbarch_tdep
*tdep
;
5645 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5647 enum mips_fpu_type fpu_type
;
5648 struct tdesc_arch_data
*tdesc_data
= NULL
;
5649 int elf_fpu_type
= 0;
5651 /* Check any target description for validity. */
5652 if (tdesc_has_registers (info
.target_desc
))
5654 static const char *const mips_gprs
[] = {
5655 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5656 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5657 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5658 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5660 static const char *const mips_fprs
[] = {
5661 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5662 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5663 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5664 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5667 const struct tdesc_feature
*feature
;
5670 feature
= tdesc_find_feature (info
.target_desc
,
5671 "org.gnu.gdb.mips.cpu");
5672 if (feature
== NULL
)
5675 tdesc_data
= tdesc_data_alloc ();
5678 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5679 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5683 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5684 MIPS_EMBED_LO_REGNUM
, "lo");
5685 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5686 MIPS_EMBED_HI_REGNUM
, "hi");
5687 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5688 MIPS_EMBED_PC_REGNUM
, "pc");
5692 tdesc_data_cleanup (tdesc_data
);
5696 feature
= tdesc_find_feature (info
.target_desc
,
5697 "org.gnu.gdb.mips.cp0");
5698 if (feature
== NULL
)
5700 tdesc_data_cleanup (tdesc_data
);
5705 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5706 MIPS_EMBED_BADVADDR_REGNUM
,
5708 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5709 MIPS_PS_REGNUM
, "status");
5710 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5711 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5715 tdesc_data_cleanup (tdesc_data
);
5719 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5720 backend is not prepared for that, though. */
5721 feature
= tdesc_find_feature (info
.target_desc
,
5722 "org.gnu.gdb.mips.fpu");
5723 if (feature
== NULL
)
5725 tdesc_data_cleanup (tdesc_data
);
5730 for (i
= 0; i
< 32; i
++)
5731 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5732 i
+ MIPS_EMBED_FP0_REGNUM
,
5735 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5736 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5737 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5738 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5742 tdesc_data_cleanup (tdesc_data
);
5746 /* It would be nice to detect an attempt to use a 64-bit ABI
5747 when only 32-bit registers are provided. */
5750 /* First of all, extract the elf_flags, if available. */
5751 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5752 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5753 else if (arches
!= NULL
)
5754 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5758 fprintf_unfiltered (gdb_stdlog
,
5759 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5761 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5762 switch ((elf_flags
& EF_MIPS_ABI
))
5764 case E_MIPS_ABI_O32
:
5765 found_abi
= MIPS_ABI_O32
;
5767 case E_MIPS_ABI_O64
:
5768 found_abi
= MIPS_ABI_O64
;
5770 case E_MIPS_ABI_EABI32
:
5771 found_abi
= MIPS_ABI_EABI32
;
5773 case E_MIPS_ABI_EABI64
:
5774 found_abi
= MIPS_ABI_EABI64
;
5777 if ((elf_flags
& EF_MIPS_ABI2
))
5778 found_abi
= MIPS_ABI_N32
;
5780 found_abi
= MIPS_ABI_UNKNOWN
;
5784 /* GCC creates a pseudo-section whose name describes the ABI. */
5785 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5786 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5788 /* If we have no useful BFD information, use the ABI from the last
5789 MIPS architecture (if there is one). */
5790 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5791 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5793 /* Try the architecture for any hint of the correct ABI. */
5794 if (found_abi
== MIPS_ABI_UNKNOWN
5795 && info
.bfd_arch_info
!= NULL
5796 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5798 switch (info
.bfd_arch_info
->mach
)
5800 case bfd_mach_mips3900
:
5801 found_abi
= MIPS_ABI_EABI32
;
5803 case bfd_mach_mips4100
:
5804 case bfd_mach_mips5000
:
5805 found_abi
= MIPS_ABI_EABI64
;
5807 case bfd_mach_mips8000
:
5808 case bfd_mach_mips10000
:
5809 /* On Irix, ELF64 executables use the N64 ABI. The
5810 pseudo-sections which describe the ABI aren't present
5811 on IRIX. (Even for executables created by gcc.) */
5812 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5813 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5814 found_abi
= MIPS_ABI_N64
;
5816 found_abi
= MIPS_ABI_N32
;
5821 /* Default 64-bit objects to N64 instead of O32. */
5822 if (found_abi
== MIPS_ABI_UNKNOWN
5823 && info
.abfd
!= NULL
5824 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5825 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5826 found_abi
= MIPS_ABI_N64
;
5829 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5832 /* What has the user specified from the command line? */
5833 wanted_abi
= global_mips_abi ();
5835 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5838 /* Now that we have found what the ABI for this binary would be,
5839 check whether the user is overriding it. */
5840 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5841 mips_abi
= wanted_abi
;
5842 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5843 mips_abi
= found_abi
;
5845 mips_abi
= MIPS_ABI_O32
;
5847 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5850 /* Also used when doing an architecture lookup. */
5852 fprintf_unfiltered (gdb_stdlog
,
5853 "mips_gdbarch_init: "
5854 "mips64_transfers_32bit_regs_p = %d\n",
5855 mips64_transfers_32bit_regs_p
);
5857 /* Determine the MIPS FPU type. */
5860 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5861 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5862 Tag_GNU_MIPS_ABI_FP
);
5863 #endif /* HAVE_ELF */
5865 if (!mips_fpu_type_auto
)
5866 fpu_type
= mips_fpu_type
;
5867 else if (elf_fpu_type
!= 0)
5869 switch (elf_fpu_type
)
5872 fpu_type
= MIPS_FPU_DOUBLE
;
5875 fpu_type
= MIPS_FPU_SINGLE
;
5879 /* Soft float or unknown. */
5880 fpu_type
= MIPS_FPU_NONE
;
5884 else if (info
.bfd_arch_info
!= NULL
5885 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5886 switch (info
.bfd_arch_info
->mach
)
5888 case bfd_mach_mips3900
:
5889 case bfd_mach_mips4100
:
5890 case bfd_mach_mips4111
:
5891 case bfd_mach_mips4120
:
5892 fpu_type
= MIPS_FPU_NONE
;
5894 case bfd_mach_mips4650
:
5895 fpu_type
= MIPS_FPU_SINGLE
;
5898 fpu_type
= MIPS_FPU_DOUBLE
;
5901 else if (arches
!= NULL
)
5902 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5904 fpu_type
= MIPS_FPU_DOUBLE
;
5906 fprintf_unfiltered (gdb_stdlog
,
5907 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5909 /* Check for blatant incompatibilities. */
5911 /* If we have only 32-bit registers, then we can't debug a 64-bit
5913 if (info
.target_desc
5914 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5915 && mips_abi
!= MIPS_ABI_EABI32
5916 && mips_abi
!= MIPS_ABI_O32
)
5918 if (tdesc_data
!= NULL
)
5919 tdesc_data_cleanup (tdesc_data
);
5923 /* Try to find a pre-existing architecture. */
5924 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5926 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5928 /* MIPS needs to be pedantic about which ABI the object is
5930 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5932 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5934 /* Need to be pedantic about which register virtual size is
5936 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5937 != mips64_transfers_32bit_regs_p
)
5939 /* Be pedantic about which FPU is selected. */
5940 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5943 if (tdesc_data
!= NULL
)
5944 tdesc_data_cleanup (tdesc_data
);
5945 return arches
->gdbarch
;
5948 /* Need a new architecture. Fill in a target specific vector. */
5949 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5950 gdbarch
= gdbarch_alloc (&info
, tdep
);
5951 tdep
->elf_flags
= elf_flags
;
5952 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5953 tdep
->found_abi
= found_abi
;
5954 tdep
->mips_abi
= mips_abi
;
5955 tdep
->mips_fpu_type
= fpu_type
;
5956 tdep
->register_size_valid_p
= 0;
5957 tdep
->register_size
= 0;
5958 tdep
->gregset
= NULL
;
5959 tdep
->gregset64
= NULL
;
5960 tdep
->fpregset
= NULL
;
5961 tdep
->fpregset64
= NULL
;
5963 if (info
.target_desc
)
5965 /* Some useful properties can be inferred from the target. */
5966 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5968 tdep
->register_size_valid_p
= 1;
5969 tdep
->register_size
= 4;
5971 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5973 tdep
->register_size_valid_p
= 1;
5974 tdep
->register_size
= 8;
5978 /* Initially set everything according to the default ABI/ISA. */
5979 set_gdbarch_short_bit (gdbarch
, 16);
5980 set_gdbarch_int_bit (gdbarch
, 32);
5981 set_gdbarch_float_bit (gdbarch
, 32);
5982 set_gdbarch_double_bit (gdbarch
, 64);
5983 set_gdbarch_long_double_bit (gdbarch
, 64);
5984 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5985 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5986 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5988 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
5989 mips_ax_pseudo_register_collect
);
5990 set_gdbarch_ax_pseudo_register_push_stack
5991 (gdbarch
, mips_ax_pseudo_register_push_stack
);
5993 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5994 mips_elf_make_msymbol_special
);
5996 /* Fill in the OS dependant register numbers and names. */
5998 const char **reg_names
;
5999 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6000 struct mips_regnum
);
6001 if (tdesc_has_registers (info
.target_desc
))
6003 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6004 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6005 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6006 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6007 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6008 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6009 regnum
->fp_control_status
= 70;
6010 regnum
->fp_implementation_revision
= 71;
6011 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6014 else if (info
.osabi
== GDB_OSABI_IRIX
)
6019 regnum
->badvaddr
= 66;
6022 regnum
->fp_control_status
= 69;
6023 regnum
->fp_implementation_revision
= 70;
6025 reg_names
= mips_irix_reg_names
;
6029 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6030 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6031 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6032 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6033 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6034 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6035 regnum
->fp_control_status
= 70;
6036 regnum
->fp_implementation_revision
= 71;
6038 if (info
.bfd_arch_info
!= NULL
6039 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6040 reg_names
= mips_tx39_reg_names
;
6042 reg_names
= mips_generic_reg_names
;
6044 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6045 replaced by gdbarch_read_pc? */
6046 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6047 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6048 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6049 set_gdbarch_num_regs (gdbarch
, num_regs
);
6050 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6051 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6052 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6053 tdep
->mips_processor_reg_names
= reg_names
;
6054 tdep
->regnum
= regnum
;
6060 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6061 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6062 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6063 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6064 tdep
->default_mask_address_p
= 0;
6065 set_gdbarch_long_bit (gdbarch
, 32);
6066 set_gdbarch_ptr_bit (gdbarch
, 32);
6067 set_gdbarch_long_long_bit (gdbarch
, 64);
6070 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6071 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6072 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6073 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6074 tdep
->default_mask_address_p
= 0;
6075 set_gdbarch_long_bit (gdbarch
, 32);
6076 set_gdbarch_ptr_bit (gdbarch
, 32);
6077 set_gdbarch_long_long_bit (gdbarch
, 64);
6079 case MIPS_ABI_EABI32
:
6080 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6081 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6082 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6083 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6084 tdep
->default_mask_address_p
= 0;
6085 set_gdbarch_long_bit (gdbarch
, 32);
6086 set_gdbarch_ptr_bit (gdbarch
, 32);
6087 set_gdbarch_long_long_bit (gdbarch
, 64);
6089 case MIPS_ABI_EABI64
:
6090 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6091 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6092 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6093 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6094 tdep
->default_mask_address_p
= 0;
6095 set_gdbarch_long_bit (gdbarch
, 64);
6096 set_gdbarch_ptr_bit (gdbarch
, 64);
6097 set_gdbarch_long_long_bit (gdbarch
, 64);
6100 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6101 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6102 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6103 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6104 tdep
->default_mask_address_p
= 0;
6105 set_gdbarch_long_bit (gdbarch
, 32);
6106 set_gdbarch_ptr_bit (gdbarch
, 32);
6107 set_gdbarch_long_long_bit (gdbarch
, 64);
6108 set_gdbarch_long_double_bit (gdbarch
, 128);
6109 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6112 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6113 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6114 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6115 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6116 tdep
->default_mask_address_p
= 0;
6117 set_gdbarch_long_bit (gdbarch
, 64);
6118 set_gdbarch_ptr_bit (gdbarch
, 64);
6119 set_gdbarch_long_long_bit (gdbarch
, 64);
6120 set_gdbarch_long_double_bit (gdbarch
, 128);
6121 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6124 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6127 /* GCC creates a pseudo-section whose name specifies the size of
6128 longs, since -mlong32 or -mlong64 may be used independent of
6129 other options. How those options affect pointer sizes is ABI and
6130 architecture dependent, so use them to override the default sizes
6131 set by the ABI. This table shows the relationship between ABI,
6132 -mlongXX, and size of pointers:
6134 ABI -mlongXX ptr bits
6135 --- -------- --------
6149 Note that for o32 and eabi32, pointers are always 32 bits
6150 regardless of any -mlongXX option. For all others, pointers and
6151 longs are the same, as set by -mlongXX or set by defaults. */
6153 if (info
.abfd
!= NULL
)
6157 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6160 set_gdbarch_long_bit (gdbarch
, long_bit
);
6164 case MIPS_ABI_EABI32
:
6169 case MIPS_ABI_EABI64
:
6170 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6173 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6178 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6179 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6182 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6183 flag in object files because to do so would make it impossible to
6184 link with libraries compiled without "-gp32". This is
6185 unnecessarily restrictive.
6187 We could solve this problem by adding "-gp32" multilibs to gcc,
6188 but to set this flag before gcc is built with such multilibs will
6189 break too many systems.''
6191 But even more unhelpfully, the default linker output target for
6192 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6193 for 64-bit programs - you need to change the ABI to change this,
6194 and not all gcc targets support that currently. Therefore using
6195 this flag to detect 32-bit mode would do the wrong thing given
6196 the current gcc - it would make GDB treat these 64-bit programs
6197 as 32-bit programs by default. */
6199 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6200 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6202 /* Add/remove bits from an address. The MIPS needs be careful to
6203 ensure that all 32 bit addresses are sign extended to 64 bits. */
6204 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6206 /* Unwind the frame. */
6207 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6208 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6209 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6211 /* Map debug register numbers onto internal register numbers. */
6212 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6213 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6214 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6215 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6216 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6217 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6219 /* MIPS version of CALL_DUMMY. */
6221 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6222 replaced by a command, and all targets will default to on stack
6223 (regardless of the stack's execute status). */
6224 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6225 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6227 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6228 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6229 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6231 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6232 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6234 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6236 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6238 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6239 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6240 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6242 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6244 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6246 if (mips_abi
== MIPS_ABI_N32
)
6247 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6248 else if (mips_abi
== MIPS_ABI_N64
)
6249 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6251 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6253 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6254 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6255 need to all be folded into the target vector. Since they are
6256 being used as guards for target_stopped_by_watchpoint, why not have
6257 target_stopped_by_watchpoint return the type of watchpoint that the code
6259 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6261 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6263 set_gdbarch_single_step_through_delay (gdbarch
,
6264 mips_single_step_through_delay
);
6266 /* Virtual tables. */
6267 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6269 mips_register_g_packet_guesses (gdbarch
);
6271 /* Hook in OS ABI-specific overrides, if they have been registered. */
6272 info
.tdep_info
= (void *) tdesc_data
;
6273 gdbarch_init_osabi (info
, gdbarch
);
6275 /* Unwind the frame. */
6276 dwarf2_append_unwinders (gdbarch
);
6277 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6278 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6279 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6280 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6281 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6282 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6283 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6287 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6288 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6290 /* Override the normal target description methods to handle our
6291 dual real and pseudo registers. */
6292 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6293 set_gdbarch_register_reggroup_p (gdbarch
,
6294 mips_tdesc_register_reggroup_p
);
6296 num_regs
= gdbarch_num_regs (gdbarch
);
6297 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6298 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6299 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6302 /* Add ABI-specific aliases for the registers. */
6303 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6304 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6305 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6306 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6308 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6309 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6310 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6312 /* Add some other standard aliases. */
6313 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6314 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6315 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6317 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6318 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6319 value_of_mips_user_reg
,
6320 &mips_numeric_register_aliases
[i
].regnum
);
6326 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6328 struct gdbarch_info info
;
6330 /* Force the architecture to update, and (if it's a MIPS architecture)
6331 mips_gdbarch_init will take care of the rest. */
6332 gdbarch_info_init (&info
);
6333 gdbarch_update_p (info
);
6336 /* Print out which MIPS ABI is in use. */
6339 show_mips_abi (struct ui_file
*file
,
6341 struct cmd_list_element
*ignored_cmd
,
6342 const char *ignored_value
)
6344 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6347 "The MIPS ABI is unknown because the current architecture "
6351 enum mips_abi global_abi
= global_mips_abi ();
6352 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6353 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6355 if (global_abi
== MIPS_ABI_UNKNOWN
)
6358 "The MIPS ABI is set automatically (currently \"%s\").\n",
6360 else if (global_abi
== actual_abi
)
6363 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6367 /* Probably shouldn't happen... */
6368 fprintf_filtered (file
,
6369 "The (auto detected) MIPS ABI \"%s\" is in use "
6370 "even though the user setting was \"%s\".\n",
6371 actual_abi_str
, mips_abi_strings
[global_abi
]);
6377 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6379 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6383 int ef_mips_32bitmode
;
6384 /* Determine the ISA. */
6385 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6403 /* Determine the size of a pointer. */
6404 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6405 fprintf_unfiltered (file
,
6406 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6408 fprintf_unfiltered (file
,
6409 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6411 fprintf_unfiltered (file
,
6412 "mips_dump_tdep: ef_mips_arch = %d\n",
6414 fprintf_unfiltered (file
,
6415 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6416 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6417 fprintf_unfiltered (file
,
6419 "mips_mask_address_p() %d (default %d)\n",
6420 mips_mask_address_p (tdep
),
6421 tdep
->default_mask_address_p
);
6423 fprintf_unfiltered (file
,
6424 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6425 MIPS_DEFAULT_FPU_TYPE
,
6426 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6427 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6428 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6430 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6431 MIPS_EABI (gdbarch
));
6432 fprintf_unfiltered (file
,
6433 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6434 MIPS_FPU_TYPE (gdbarch
),
6435 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6436 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6437 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6441 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6444 _initialize_mips_tdep (void)
6446 static struct cmd_list_element
*mipsfpulist
= NULL
;
6447 struct cmd_list_element
*c
;
6449 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6450 if (MIPS_ABI_LAST
+ 1
6451 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6452 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6454 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6456 mips_pdr_data
= register_objfile_data ();
6458 /* Create feature sets with the appropriate properties. The values
6459 are not important. */
6460 mips_tdesc_gp32
= allocate_target_description ();
6461 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6463 mips_tdesc_gp64
= allocate_target_description ();
6464 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6466 /* Add root prefix command for all "set mips"/"show mips" commands. */
6467 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6468 _("Various MIPS specific commands."),
6469 &setmipscmdlist
, "set mips ", 0, &setlist
);
6471 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6472 _("Various MIPS specific commands."),
6473 &showmipscmdlist
, "show mips ", 0, &showlist
);
6475 /* Allow the user to override the ABI. */
6476 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6477 &mips_abi_string
, _("\
6478 Set the MIPS ABI used by this program."), _("\
6479 Show the MIPS ABI used by this program."), _("\
6480 This option can be set to one of:\n\
6481 auto - the default ABI associated with the current binary\n\
6490 &setmipscmdlist
, &showmipscmdlist
);
6492 /* Let the user turn off floating point and set the fence post for
6493 heuristic_proc_start. */
6495 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6496 _("Set use of MIPS floating-point coprocessor."),
6497 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6498 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6499 _("Select single-precision MIPS floating-point coprocessor."),
6501 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6502 _("Select double-precision MIPS floating-point coprocessor."),
6504 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6505 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6506 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6507 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6508 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6509 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6510 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6511 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6512 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6513 _("Select MIPS floating-point coprocessor automatically."),
6515 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6516 _("Show current use of MIPS floating-point coprocessor target."),
6519 /* We really would like to have both "0" and "unlimited" work, but
6520 command.c doesn't deal with that. So make it a var_zinteger
6521 because the user can always use "999999" or some such for unlimited. */
6522 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6523 &heuristic_fence_post
, _("\
6524 Set the distance searched for the start of a function."), _("\
6525 Show the distance searched for the start of a function."), _("\
6526 If you are debugging a stripped executable, GDB needs to search through the\n\
6527 program for the start of a function. This command sets the distance of the\n\
6528 search. The only need to set it is when debugging a stripped executable."),
6529 reinit_frame_cache_sfunc
,
6530 NULL
, /* FIXME: i18n: The distance searched for
6531 the start of a function is %s. */
6532 &setlist
, &showlist
);
6534 /* Allow the user to control whether the upper bits of 64-bit
6535 addresses should be zeroed. */
6536 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6537 &mask_address_var
, _("\
6538 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6539 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6540 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6541 allow GDB to determine the correct value."),
6542 NULL
, show_mask_address
,
6543 &setmipscmdlist
, &showmipscmdlist
);
6545 /* Allow the user to control the size of 32 bit registers within the
6546 raw remote packet. */
6547 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6548 &mips64_transfers_32bit_regs_p
, _("\
6549 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6551 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6553 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6554 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6555 64 bits for others. Use \"off\" to disable compatibility mode"),
6556 set_mips64_transfers_32bit_regs
,
6557 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6558 MIPS target that transfers 32-bit
6559 quantities is %s. */
6560 &setlist
, &showlist
);
6562 /* Debug this files internals. */
6563 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6565 Set mips debugging."), _("\
6566 Show mips debugging."), _("\
6567 When non-zero, mips specific debugging is enabled."),
6569 NULL
, /* FIXME: i18n: Mips debugging is
6571 &setdebuglist
, &showdebuglist
);