1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
62 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
64 /* A useful bit in the CP0 status register (PS_REGNUM). */
65 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
66 #define ST0_FR (1 << 26)
68 /* The sizes of floating point registers. */
72 MIPS_FPU_SINGLE_REGSIZE
= 4,
73 MIPS_FPU_DOUBLE_REGSIZE
= 8
77 static const char *mips_abi_string
;
79 static const char *mips_abi_strings
[] = {
90 struct frame_extra_info
92 mips_extra_func_info_t proc_desc
;
96 /* Various MIPS ISA options (related to stack analysis) can be
97 overridden dynamically. Establish an enum/array for managing
100 static const char size_auto
[] = "auto";
101 static const char size_32
[] = "32";
102 static const char size_64
[] = "64";
104 static const char *size_enums
[] = {
111 /* Some MIPS boards don't support floating point while others only
112 support single-precision floating-point operations. */
116 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
117 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
118 MIPS_FPU_NONE
/* No floating point. */
121 #ifndef MIPS_DEFAULT_FPU_TYPE
122 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
124 static int mips_fpu_type_auto
= 1;
125 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
127 static int mips_debug
= 0;
129 /* MIPS specific per-architecture information */
132 /* from the elf header */
136 enum mips_abi mips_abi
;
137 enum mips_abi found_abi
;
138 enum mips_fpu_type mips_fpu_type
;
139 int mips_last_arg_regnum
;
140 int mips_last_fp_arg_regnum
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
154 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
160 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
161 They are implemented as a pair of 64bit doubles where the high
162 part holds the result of the operation rounded to double, and
163 the low double holds the difference between the exact result and
164 the rounded result. So "high" + "low" contains the result with
165 added precision. Unfortunately, the floatformat structure used
166 by GDB is not powerful enough to describe this format. As a temporary
167 measure, we define a 128bit floatformat that only uses the high part.
168 We lose a bit of precision but that's probably the best we can do
169 for now with the current infrastructure. */
171 static const struct floatformat floatformat_n32n64_long_double_big
=
173 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
174 floatformat_intbit_no
,
175 "floatformat_ieee_double_big",
176 n32n64_floatformat_always_valid
179 const struct mips_regnum
*
180 mips_regnum (struct gdbarch
*gdbarch
)
182 return gdbarch_tdep (gdbarch
)->regnum
;
186 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
188 return mips_regnum (gdbarch
)->fp0
+ 12;
191 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
192 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
194 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
196 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
198 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
200 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
201 functions to test, set, or clear bit 0 of addresses. */
204 is_mips16_addr (CORE_ADDR addr
)
210 make_mips16_addr (CORE_ADDR addr
)
216 unmake_mips16_addr (CORE_ADDR addr
)
218 return ((addr
) & ~1);
221 /* Return the contents of register REGNUM as a signed integer. */
224 read_signed_register (int regnum
)
226 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
227 deprecated_read_register_gen (regnum
, buf
);
228 return (extract_signed_integer
229 (buf
, register_size (current_gdbarch
, regnum
)));
233 read_signed_register_pid (int regnum
, ptid_t ptid
)
238 if (ptid_equal (ptid
, inferior_ptid
))
239 return read_signed_register (regnum
);
241 save_ptid
= inferior_ptid
;
243 inferior_ptid
= ptid
;
245 retval
= read_signed_register (regnum
);
247 inferior_ptid
= save_ptid
;
252 /* Return the MIPS ABI associated with GDBARCH. */
254 mips_abi (struct gdbarch
*gdbarch
)
256 return gdbarch_tdep (gdbarch
)->mips_abi
;
260 mips_isa_regsize (struct gdbarch
*gdbarch
)
262 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
263 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
266 /* Return the currently configured (or set) saved register size. */
268 static const char *mips_abi_regsize_string
= size_auto
;
271 mips_abi_regsize (struct gdbarch
*gdbarch
)
273 if (mips_abi_regsize_string
== size_auto
)
274 switch (mips_abi (gdbarch
))
276 case MIPS_ABI_EABI32
:
282 case MIPS_ABI_EABI64
:
284 case MIPS_ABI_UNKNOWN
:
287 internal_error (__FILE__
, __LINE__
, "bad switch");
289 else if (mips_abi_regsize_string
== size_64
)
291 else /* if (mips_abi_regsize_string == size_32) */
295 /* Functions for setting and testing a bit in a minimal symbol that
296 marks it as 16-bit function. The MSB of the minimal symbol's
297 "info" field is used for this purpose.
299 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
300 i.e. refers to a 16-bit function, and sets a "special" bit in a
301 minimal symbol to mark it as a 16-bit function
303 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
306 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
308 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
310 MSYMBOL_INFO (msym
) = (char *)
311 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
312 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
317 msymbol_is_special (struct minimal_symbol
*msym
)
319 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
322 /* XFER a value from the big/little/left end of the register.
323 Depending on the size of the value it might occupy the entire
324 register or just part of it. Make an allowance for this, aligning
325 things accordingly. */
328 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
329 enum bfd_endian endian
, bfd_byte
* in
,
330 const bfd_byte
* out
, int buf_offset
)
333 gdb_assert (reg_num
>= NUM_REGS
);
334 /* Need to transfer the left or right part of the register, based on
335 the targets byte order. */
339 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
341 case BFD_ENDIAN_LITTLE
:
344 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
348 internal_error (__FILE__
, __LINE__
, "bad switch");
351 fprintf_unfiltered (gdb_stderr
,
352 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
353 reg_num
, reg_offset
, buf_offset
, length
);
354 if (mips_debug
&& out
!= NULL
)
357 fprintf_unfiltered (gdb_stdlog
, "out ");
358 for (i
= 0; i
< length
; i
++)
359 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
362 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
365 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
367 if (mips_debug
&& in
!= NULL
)
370 fprintf_unfiltered (gdb_stdlog
, "in ");
371 for (i
= 0; i
< length
; i
++)
372 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
375 fprintf_unfiltered (gdb_stdlog
, "\n");
378 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
379 compatiblity mode. A return value of 1 means that we have
380 physical 64-bit registers, but should treat them as 32-bit registers. */
383 mips2_fp_compat (void)
385 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
387 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
392 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
393 in all the places we deal with FP registers. PR gdb/413. */
394 /* Otherwise check the FR bit in the status register - it controls
395 the FP compatiblity mode. If it is clear we are in compatibility
397 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
404 /* The amount of space reserved on the stack for registers. This is
405 different to MIPS_ABI_REGSIZE as it determines the alignment of
406 data allocated after the registers have run out. */
408 static const char *mips_stack_argsize_string
= size_auto
;
411 mips_stack_argsize (struct gdbarch
*gdbarch
)
413 if (mips_stack_argsize_string
== size_auto
)
414 return mips_abi_regsize (gdbarch
);
415 else if (mips_stack_argsize_string
== size_64
)
417 else /* if (mips_stack_argsize_string == size_32) */
421 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
424 struct frame_info
*);
425 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
428 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
430 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
432 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
434 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
436 static struct type
*mips_float_register_type (void);
437 static struct type
*mips_double_register_type (void);
439 /* The list of available "set mips " and "show mips " commands */
441 static struct cmd_list_element
*setmipscmdlist
= NULL
;
442 static struct cmd_list_element
*showmipscmdlist
= NULL
;
444 /* Integer registers 0 thru 31 are handled explicitly by
445 mips_register_name(). Processor specific registers 32 and above
446 are listed in the followign tables. */
449 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
453 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
454 "sr", "lo", "hi", "bad", "cause", "pc",
455 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
456 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
457 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
458 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
459 "fsr", "fir", "" /*"fp" */ , "",
460 "", "", "", "", "", "", "", "",
461 "", "", "", "", "", "", "", "",
464 /* Names of IDT R3041 registers. */
466 static const char *mips_r3041_reg_names
[] = {
467 "sr", "lo", "hi", "bad", "cause", "pc",
468 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
469 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
470 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
471 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
472 "fsr", "fir", "", /*"fp" */ "",
473 "", "", "bus", "ccfg", "", "", "", "",
474 "", "", "port", "cmp", "", "", "epc", "prid",
477 /* Names of tx39 registers. */
479 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
480 "sr", "lo", "hi", "bad", "cause", "pc",
481 "", "", "", "", "", "", "", "",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
486 "", "", "", "", "", "", "", "",
487 "", "", "config", "cache", "debug", "depc", "epc", ""
490 /* Names of IRIX registers. */
491 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
492 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
493 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
494 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
495 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
496 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
500 /* Return the name of the register corresponding to REGNO. */
502 mips_register_name (int regno
)
504 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
505 /* GPR names for all ABIs other than n32/n64. */
506 static char *mips_gpr_names
[] = {
507 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
508 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
509 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
510 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
513 /* GPR names for n32 and n64 ABIs. */
514 static char *mips_n32_n64_gpr_names
[] = {
515 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
516 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
517 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
518 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
521 enum mips_abi abi
= mips_abi (current_gdbarch
);
523 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
524 don't make the raw register names visible. */
525 int rawnum
= regno
% NUM_REGS
;
526 if (regno
< NUM_REGS
)
529 /* The MIPS integer registers are always mapped from 0 to 31. The
530 names of the registers (which reflects the conventions regarding
531 register use) vary depending on the ABI. */
532 if (0 <= rawnum
&& rawnum
< 32)
534 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
535 return mips_n32_n64_gpr_names
[rawnum
];
537 return mips_gpr_names
[rawnum
];
539 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
541 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
542 return tdep
->mips_processor_reg_names
[rawnum
- 32];
545 internal_error (__FILE__
, __LINE__
,
546 "mips_register_name: bad register number %d", rawnum
);
549 /* Return the groups that a MIPS register can be categorised into. */
552 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
553 struct reggroup
*reggroup
)
558 int rawnum
= regnum
% NUM_REGS
;
559 int pseudo
= regnum
/ NUM_REGS
;
560 if (reggroup
== all_reggroup
)
562 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
563 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
564 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
565 (gdbarch), as not all architectures are multi-arch. */
566 raw_p
= rawnum
< NUM_REGS
;
567 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
569 if (reggroup
== float_reggroup
)
570 return float_p
&& pseudo
;
571 if (reggroup
== vector_reggroup
)
572 return vector_p
&& pseudo
;
573 if (reggroup
== general_reggroup
)
574 return (!vector_p
&& !float_p
) && pseudo
;
575 /* Save the pseudo registers. Need to make certain that any code
576 extracting register values from a saved register cache also uses
578 if (reggroup
== save_reggroup
)
579 return raw_p
&& pseudo
;
580 /* Restore the same pseudo register. */
581 if (reggroup
== restore_reggroup
)
582 return raw_p
&& pseudo
;
586 /* Map the symbol table registers which live in the range [1 *
587 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
588 registers. Take care of alignment and size problems. */
591 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
592 int cookednum
, void *buf
)
594 int rawnum
= cookednum
% NUM_REGS
;
595 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
596 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
597 regcache_raw_read (regcache
, rawnum
, buf
);
598 else if (register_size (gdbarch
, rawnum
) >
599 register_size (gdbarch
, cookednum
))
601 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
602 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
603 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
605 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
608 internal_error (__FILE__
, __LINE__
, "bad register size");
612 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
613 struct regcache
*regcache
, int cookednum
,
616 int rawnum
= cookednum
% NUM_REGS
;
617 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
618 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
619 regcache_raw_write (regcache
, rawnum
, buf
);
620 else if (register_size (gdbarch
, rawnum
) >
621 register_size (gdbarch
, cookednum
))
623 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
624 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
625 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
627 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
630 internal_error (__FILE__
, __LINE__
, "bad register size");
633 /* Table to translate MIPS16 register field to actual register number. */
634 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
636 /* Heuristic_proc_start may hunt through the text section for a long
637 time across a 2400 baud serial line. Allows the user to limit this
640 static unsigned int heuristic_fence_post
= 0;
642 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
643 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
644 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
645 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
646 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
647 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
648 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
649 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
650 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
651 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
652 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
653 this will corrupt pdr.iline. Fortunately we don't use it. */
654 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
655 #define _PROC_MAGIC_ 0x0F0F0F0F
656 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
657 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
659 /* Number of bytes of storage in the actual machine representation for
660 register N. NOTE: This defines the pseudo register type so need to
661 rebuild the architecture vector. */
663 static int mips64_transfers_32bit_regs_p
= 0;
666 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
667 struct cmd_list_element
*c
)
669 struct gdbarch_info info
;
670 gdbarch_info_init (&info
);
671 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
672 instead of relying on globals. Doing that would let generic code
673 handle the search for this specific architecture. */
674 if (!gdbarch_update_p (info
))
676 mips64_transfers_32bit_regs_p
= 0;
677 error ("32-bit compatibility mode not supported");
681 /* Convert to/from a register and the corresponding memory value. */
684 mips_convert_register_p (int regnum
, struct type
*type
)
686 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
687 && register_size (current_gdbarch
, regnum
) == 4
688 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
689 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
690 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
694 mips_register_to_value (struct frame_info
*frame
, int regnum
,
695 struct type
*type
, void *to
)
697 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
698 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
702 mips_value_to_register (struct frame_info
*frame
, int regnum
,
703 struct type
*type
, const void *from
)
705 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
706 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
709 /* Return the GDB type object for the "standard" data type of data in
713 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
715 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
716 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
717 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
719 /* The floating-point registers raw, or cooked, always match
720 mips_isa_regsize(), and also map 1:1, byte for byte. */
721 switch (gdbarch_byte_order (gdbarch
))
724 if (mips_isa_regsize (gdbarch
) == 4)
725 return builtin_type_ieee_single_big
;
727 return builtin_type_ieee_double_big
;
728 case BFD_ENDIAN_LITTLE
:
729 if (mips_isa_regsize (gdbarch
) == 4)
730 return builtin_type_ieee_single_little
;
732 return builtin_type_ieee_double_little
;
733 case BFD_ENDIAN_UNKNOWN
:
735 internal_error (__FILE__
, __LINE__
, "bad switch");
738 else if (regnum
< NUM_REGS
)
740 /* The raw or ISA registers. These are all sized according to
742 if (mips_isa_regsize (gdbarch
) == 4)
743 return builtin_type_int32
;
745 return builtin_type_int64
;
749 /* The cooked or ABI registers. These are sized according to
750 the ABI (with a few complications). */
751 if (regnum
>= (NUM_REGS
752 + mips_regnum (current_gdbarch
)->fp_control_status
)
753 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
754 /* The pseudo/cooked view of the embedded registers is always
755 32-bit. The raw view is handled below. */
756 return builtin_type_int32
;
757 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
758 /* The target, while possibly using a 64-bit register buffer,
759 is only transfering 32-bits of each integer register.
760 Reflect this in the cooked/pseudo (ABI) register value. */
761 return builtin_type_int32
;
762 else if (mips_abi_regsize (gdbarch
) == 4)
763 /* The ABI is restricted to 32-bit registers (the ISA could be
765 return builtin_type_int32
;
768 return builtin_type_int64
;
772 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
777 return read_signed_register (MIPS_SP_REGNUM
);
780 /* Should the upper word of 64-bit addresses be zeroed? */
781 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
784 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
786 switch (mask_address_var
)
788 case AUTO_BOOLEAN_TRUE
:
790 case AUTO_BOOLEAN_FALSE
:
793 case AUTO_BOOLEAN_AUTO
:
794 return tdep
->default_mask_address_p
;
796 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
802 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
804 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
805 switch (mask_address_var
)
807 case AUTO_BOOLEAN_TRUE
:
808 printf_filtered ("The 32 bit mips address mask is enabled\n");
810 case AUTO_BOOLEAN_FALSE
:
811 printf_filtered ("The 32 bit mips address mask is disabled\n");
813 case AUTO_BOOLEAN_AUTO
:
815 ("The 32 bit address mask is set automatically. Currently %s\n",
816 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
819 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
824 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
827 pc_is_mips16 (bfd_vma memaddr
)
829 struct minimal_symbol
*sym
;
831 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
832 if (is_mips16_addr (memaddr
))
835 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
836 the high bit of the info field. Use this to decide if the function is
837 MIPS16 or normal MIPS. */
838 sym
= lookup_minimal_symbol_by_pc (memaddr
);
840 return msymbol_is_special (sym
);
845 /* MIPS believes that the PC has a sign extended value. Perhaps the
846 all registers should be sign extended for simplicity? */
849 mips_read_pc (ptid_t ptid
)
851 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
855 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
857 return frame_unwind_register_signed (next_frame
,
858 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
861 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
862 dummy frame. The frame ID's base needs to match the TOS value
863 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
866 static struct frame_id
867 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
869 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
870 frame_pc_unwind (next_frame
));
874 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
876 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
879 /* This returns the PC of the first inst after the prologue. If we can't
880 find the prologue, then return 0. */
883 after_prologue (CORE_ADDR pc
)
885 mips_extra_func_info_t proc_desc
;
886 struct symtab_and_line sal
;
887 CORE_ADDR func_addr
, func_end
;
888 CORE_ADDR startaddr
= 0;
890 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
891 attempt to read the stack pointer from the current machine state,
892 because the current machine state has nothing to do with the
893 information we need from the proc_desc; and the process may or
894 may not exist right now. */
895 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
898 /* IF this is the topmost frame AND (this proc does not have
899 debugging information OR the PC is in the procedure prologue)
900 THEN create a "heuristic" proc_desc (by analyzing the actual
901 code) to replace the "official" proc_desc. */
902 struct symtab_and_line val
;
903 struct symbol
*proc_symbol
=
904 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
908 val
= find_pc_line (BLOCK_START
909 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
910 val
.pc
= val
.end
? val
.end
: pc
;
912 if (!proc_symbol
|| pc
< val
.pc
)
914 mips_extra_func_info_t found_heuristic
=
915 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
);
917 proc_desc
= found_heuristic
;
923 startaddr
= heuristic_proc_start (pc
);
925 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
);
930 /* If function is frameless, then we need to do it the hard way. I
931 strongly suspect that frameless always means prologueless... */
932 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
933 && PROC_FRAME_OFFSET (proc_desc
) == 0)
937 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
938 return 0; /* Unknown */
940 sal
= find_pc_line (func_addr
, 0);
942 if (sal
.end
< func_end
)
945 /* The line after the prologue is after the end of the function. In this
946 case, tell the caller to find the prologue the hard way. */
951 /* Decode a MIPS32 instruction that saves a register in the stack, and
952 set the appropriate bit in the general register mask or float register mask
953 to indicate which register is saved. This is a helper function
954 for mips_find_saved_regs. */
957 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
958 unsigned long *float_mask
)
962 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
963 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
964 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
966 /* It might be possible to use the instruction to
967 find the offset, rather than the code below which
968 is based on things being in a certain order in the
969 frame, but figuring out what the instruction's offset
970 is relative to might be a little tricky. */
971 reg
= (inst
& 0x001f0000) >> 16;
972 *gen_mask
|= (1 << reg
);
974 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
975 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
976 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
979 reg
= ((inst
& 0x001f0000) >> 16);
980 *float_mask
|= (1 << reg
);
984 /* Decode a MIPS16 instruction that saves a register in the stack, and
985 set the appropriate bit in the general register or float register mask
986 to indicate which register is saved. This is a helper function
987 for mips_find_saved_regs. */
990 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
992 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
994 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
995 *gen_mask
|= (1 << reg
);
997 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
999 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1000 *gen_mask
|= (1 << reg
);
1002 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
1003 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1004 *gen_mask
|= (1 << RA_REGNUM
);
1008 /* Fetch and return instruction from the specified location. If the PC
1009 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1012 mips_fetch_instruction (CORE_ADDR addr
)
1014 char buf
[MIPS_INSTLEN
];
1018 if (pc_is_mips16 (addr
))
1020 instlen
= MIPS16_INSTLEN
;
1021 addr
= unmake_mips16_addr (addr
);
1024 instlen
= MIPS_INSTLEN
;
1025 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1027 memory_error (status
, addr
);
1028 return extract_unsigned_integer (buf
, instlen
);
1032 mips16_fetch_instruction (CORE_ADDR addr
)
1034 char buf
[MIPS_INSTLEN
];
1038 instlen
= MIPS16_INSTLEN
;
1039 addr
= unmake_mips16_addr (addr
);
1040 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1042 memory_error (status
, addr
);
1043 return extract_unsigned_integer (buf
, instlen
);
1047 mips32_fetch_instruction (CORE_ADDR addr
)
1049 char buf
[MIPS_INSTLEN
];
1052 instlen
= MIPS_INSTLEN
;
1053 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1055 memory_error (status
, addr
);
1056 return extract_unsigned_integer (buf
, instlen
);
1060 /* These the fields of 32 bit mips instructions */
1061 #define mips32_op(x) (x >> 26)
1062 #define itype_op(x) (x >> 26)
1063 #define itype_rs(x) ((x >> 21) & 0x1f)
1064 #define itype_rt(x) ((x >> 16) & 0x1f)
1065 #define itype_immediate(x) (x & 0xffff)
1067 #define jtype_op(x) (x >> 26)
1068 #define jtype_target(x) (x & 0x03ffffff)
1070 #define rtype_op(x) (x >> 26)
1071 #define rtype_rs(x) ((x >> 21) & 0x1f)
1072 #define rtype_rt(x) ((x >> 16) & 0x1f)
1073 #define rtype_rd(x) ((x >> 11) & 0x1f)
1074 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1075 #define rtype_funct(x) (x & 0x3f)
1078 mips32_relative_offset (unsigned long inst
)
1081 x
= itype_immediate (inst
);
1082 if (x
& 0x8000) /* sign bit set */
1084 x
|= 0xffff0000; /* sign extension */
1090 /* Determine whate to set a single step breakpoint while considering
1091 branch prediction */
1093 mips32_next_pc (CORE_ADDR pc
)
1097 inst
= mips_fetch_instruction (pc
);
1098 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1100 if (itype_op (inst
) >> 2 == 5)
1101 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1103 op
= (itype_op (inst
) & 0x03);
1113 goto greater_branch
;
1118 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1119 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1121 int tf
= itype_rt (inst
) & 0x01;
1122 int cnum
= itype_rt (inst
) >> 2;
1124 read_signed_register (mips_regnum (current_gdbarch
)->
1126 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1128 if (((cond
>> cnum
) & 0x01) == tf
)
1129 pc
+= mips32_relative_offset (inst
) + 4;
1134 pc
+= 4; /* Not a branch, next instruction is easy */
1137 { /* This gets way messy */
1139 /* Further subdivide into SPECIAL, REGIMM and other */
1140 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1142 case 0: /* SPECIAL */
1143 op
= rtype_funct (inst
);
1148 /* Set PC to that address */
1149 pc
= read_signed_register (rtype_rs (inst
));
1155 break; /* end SPECIAL */
1156 case 1: /* REGIMM */
1158 op
= itype_rt (inst
); /* branch condition */
1163 case 16: /* BLTZAL */
1164 case 18: /* BLTZALL */
1166 if (read_signed_register (itype_rs (inst
)) < 0)
1167 pc
+= mips32_relative_offset (inst
) + 4;
1169 pc
+= 8; /* after the delay slot */
1173 case 17: /* BGEZAL */
1174 case 19: /* BGEZALL */
1175 if (read_signed_register (itype_rs (inst
)) >= 0)
1176 pc
+= mips32_relative_offset (inst
) + 4;
1178 pc
+= 8; /* after the delay slot */
1180 /* All of the other instructions in the REGIMM category */
1185 break; /* end REGIMM */
1190 reg
= jtype_target (inst
) << 2;
1191 /* Upper four bits get never changed... */
1192 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1195 /* FIXME case JALX : */
1198 reg
= jtype_target (inst
) << 2;
1199 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1200 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1202 break; /* The new PC will be alternate mode */
1203 case 4: /* BEQ, BEQL */
1205 if (read_signed_register (itype_rs (inst
)) ==
1206 read_signed_register (itype_rt (inst
)))
1207 pc
+= mips32_relative_offset (inst
) + 4;
1211 case 5: /* BNE, BNEL */
1213 if (read_signed_register (itype_rs (inst
)) !=
1214 read_signed_register (itype_rt (inst
)))
1215 pc
+= mips32_relative_offset (inst
) + 4;
1219 case 6: /* BLEZ, BLEZL */
1220 if (read_signed_register (itype_rs (inst
) <= 0))
1221 pc
+= mips32_relative_offset (inst
) + 4;
1227 greater_branch
: /* BGTZ, BGTZL */
1228 if (read_signed_register (itype_rs (inst
) > 0))
1229 pc
+= mips32_relative_offset (inst
) + 4;
1236 } /* mips32_next_pc */
1238 /* Decoding the next place to set a breakpoint is irregular for the
1239 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1240 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1241 We dont want to set a single step instruction on the extend instruction
1245 /* Lots of mips16 instruction formats */
1246 /* Predicting jumps requires itype,ritype,i8type
1247 and their extensions extItype,extritype,extI8type
1249 enum mips16_inst_fmts
1251 itype
, /* 0 immediate 5,10 */
1252 ritype
, /* 1 5,3,8 */
1253 rrtype
, /* 2 5,3,3,5 */
1254 rritype
, /* 3 5,3,3,5 */
1255 rrrtype
, /* 4 5,3,3,3,2 */
1256 rriatype
, /* 5 5,3,3,1,4 */
1257 shifttype
, /* 6 5,3,3,3,2 */
1258 i8type
, /* 7 5,3,8 */
1259 i8movtype
, /* 8 5,3,3,5 */
1260 i8mov32rtype
, /* 9 5,3,5,3 */
1261 i64type
, /* 10 5,3,8 */
1262 ri64type
, /* 11 5,3,3,5 */
1263 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1264 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1265 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1266 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1267 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1268 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1269 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1270 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1271 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1272 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1274 /* I am heaping all the fields of the formats into one structure and
1275 then, only the fields which are involved in instruction extension */
1279 unsigned int regx
; /* Function in i8 type */
1284 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1285 for the bits which make up the immediatate extension. */
1288 extended_offset (unsigned int extension
)
1291 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1293 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1295 value
|= extension
& 0x01f; /* extract 4:0 */
1299 /* Only call this function if you know that this is an extendable
1300 instruction, It wont malfunction, but why make excess remote memory references?
1301 If the immediate operands get sign extended or somthing, do it after
1302 the extension is performed.
1304 /* FIXME: Every one of these cases needs to worry about sign extension
1305 when the offset is to be used in relative addressing */
1309 fetch_mips_16 (CORE_ADDR pc
)
1312 pc
&= 0xfffffffe; /* clear the low order bit */
1313 target_read_memory (pc
, buf
, 2);
1314 return extract_unsigned_integer (buf
, 2);
1318 unpack_mips16 (CORE_ADDR pc
,
1319 unsigned int extension
,
1321 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1326 switch (insn_format
)
1333 value
= extended_offset (extension
);
1334 value
= value
<< 11; /* rom for the original value */
1335 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1339 value
= inst
& 0x7ff;
1340 /* FIXME : Consider sign extension */
1349 { /* A register identifier and an offset */
1350 /* Most of the fields are the same as I type but the
1351 immediate value is of a different length */
1355 value
= extended_offset (extension
);
1356 value
= value
<< 8; /* from the original instruction */
1357 value
|= inst
& 0xff; /* eleven bits from instruction */
1358 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1359 if (value
& 0x4000) /* test the sign bit , bit 26 */
1361 value
&= ~0x3fff; /* remove the sign bit */
1367 value
= inst
& 0xff; /* 8 bits */
1368 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1369 /* FIXME: Do sign extension , this format needs it */
1370 if (value
& 0x80) /* THIS CONFUSES ME */
1372 value
&= 0xef; /* remove the sign bit */
1382 unsigned long value
;
1383 unsigned int nexthalf
;
1384 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1385 value
= value
<< 16;
1386 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1394 internal_error (__FILE__
, __LINE__
, "bad switch");
1396 upk
->offset
= offset
;
1403 add_offset_16 (CORE_ADDR pc
, int offset
)
1405 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1409 extended_mips16_next_pc (CORE_ADDR pc
,
1410 unsigned int extension
, unsigned int insn
)
1412 int op
= (insn
>> 11);
1415 case 2: /* Branch */
1418 struct upk_mips16 upk
;
1419 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1420 offset
= upk
.offset
;
1426 pc
+= (offset
<< 1) + 2;
1429 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1431 struct upk_mips16 upk
;
1432 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1433 pc
= add_offset_16 (pc
, upk
.offset
);
1434 if ((insn
>> 10) & 0x01) /* Exchange mode */
1435 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1442 struct upk_mips16 upk
;
1444 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1445 reg
= read_signed_register (upk
.regx
);
1447 pc
+= (upk
.offset
<< 1) + 2;
1454 struct upk_mips16 upk
;
1456 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1457 reg
= read_signed_register (upk
.regx
);
1459 pc
+= (upk
.offset
<< 1) + 2;
1464 case 12: /* I8 Formats btez btnez */
1466 struct upk_mips16 upk
;
1468 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1469 /* upk.regx contains the opcode */
1470 reg
= read_signed_register (24); /* Test register is 24 */
1471 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1472 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1473 /* pc = add_offset_16(pc,upk.offset) ; */
1474 pc
+= (upk
.offset
<< 1) + 2;
1479 case 29: /* RR Formats JR, JALR, JALR-RA */
1481 struct upk_mips16 upk
;
1482 /* upk.fmt = rrtype; */
1487 upk
.regx
= (insn
>> 8) & 0x07;
1488 upk
.regy
= (insn
>> 5) & 0x07;
1496 break; /* Function return instruction */
1502 break; /* BOGUS Guess */
1504 pc
= read_signed_register (reg
);
1511 /* This is an instruction extension. Fetch the real instruction
1512 (which follows the extension) and decode things based on
1516 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1529 mips16_next_pc (CORE_ADDR pc
)
1531 unsigned int insn
= fetch_mips_16 (pc
);
1532 return extended_mips16_next_pc (pc
, 0, insn
);
1535 /* The mips_next_pc function supports single_step when the remote
1536 target monitor or stub is not developed enough to do a single_step.
1537 It works by decoding the current instruction and predicting where a
1538 branch will go. This isnt hard because all the data is available.
1539 The MIPS32 and MIPS16 variants are quite different */
1541 mips_next_pc (CORE_ADDR pc
)
1544 return mips16_next_pc (pc
);
1546 return mips32_next_pc (pc
);
1549 struct mips_frame_cache
1552 struct trad_frame_saved_reg
*saved_regs
;
1556 static struct mips_frame_cache
*
1557 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1559 CORE_ADDR startaddr
= 0;
1560 mips_extra_func_info_t proc_desc
;
1561 struct mips_frame_cache
*cache
;
1562 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1563 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1564 /* r0 bit means kernel trap */
1566 /* What registers have been saved? Bitmasks. */
1567 unsigned long gen_mask
, float_mask
;
1569 if ((*this_cache
) != NULL
)
1570 return (*this_cache
);
1571 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1572 (*this_cache
) = cache
;
1573 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1575 /* Get the mdebug proc descriptor. */
1576 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1578 /* Must be true. This is only called when the sniffer detected a
1580 gdb_assert (proc_desc
!= NULL
);
1582 /* Extract the frame's base. */
1583 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1584 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1586 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1587 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1588 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1590 /* In any frame other than the innermost or a frame interrupted by a
1591 signal, we assume that all registers have been saved. This
1592 assumes that all register saves in a function happen before the
1593 first function call. */
1594 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1595 /* Not sure exactly what kernel_trap means, but if it means the
1596 kernel saves the registers without a prologue doing it, we
1597 better not examine the prologue to see whether registers
1598 have been saved yet. */
1601 /* We need to figure out whether the registers that the
1602 proc_desc claims are saved have been saved yet. */
1606 /* Bitmasks; set if we have found a save for the register. */
1607 unsigned long gen_save_found
= 0;
1608 unsigned long float_save_found
= 0;
1611 /* If the address is odd, assume this is MIPS16 code. */
1612 addr
= PROC_LOW_ADDR (proc_desc
);
1613 mips16
= pc_is_mips16 (addr
);
1615 /* Scan through this function's instructions preceding the
1616 current PC, and look for those that save registers. */
1617 while (addr
< frame_pc_unwind (next_frame
))
1621 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1623 addr
+= MIPS16_INSTLEN
;
1627 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1628 &gen_save_found
, &float_save_found
);
1629 addr
+= MIPS_INSTLEN
;
1632 gen_mask
= gen_save_found
;
1633 float_mask
= float_save_found
;
1636 /* Fill in the offsets for the registers which gen_mask says were
1639 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1642 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1643 if (gen_mask
& 0x80000000)
1645 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1646 reg_position
-= mips_abi_regsize (gdbarch
);
1650 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1651 order of that normally used by gcc. Therefore, we have to fetch
1652 the first instruction of the function, and if it's an entry
1653 instruction that saves $s0 or $s1, correct their saved addresses. */
1654 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1656 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1657 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1661 int sreg_count
= (inst
>> 6) & 3;
1663 /* Check if the ra register was pushed on the stack. */
1664 CORE_ADDR reg_position
= (cache
->base
1665 + PROC_REG_OFFSET (proc_desc
));
1667 reg_position
-= mips_abi_regsize (gdbarch
);
1669 /* Check if the s0 and s1 registers were pushed on the
1671 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1673 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1675 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1676 reg_position
-= mips_abi_regsize (gdbarch
);
1681 /* Fill in the offsets for the registers which float_mask says were
1684 CORE_ADDR reg_position
= (cache
->base
1685 + PROC_FREG_OFFSET (proc_desc
));
1687 /* Fill in the offsets for the float registers which float_mask
1689 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1690 if (float_mask
& 0x80000000)
1692 if (mips_abi_regsize (gdbarch
) == 4
1693 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1695 /* On a big endian 32 bit ABI, floating point registers
1696 are paired to form doubles such that the most
1697 significant part is in $f[N+1] and the least
1698 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1699 registers are also spilled as a pair and stored as a
1702 When little-endian the least significant part is
1703 stored first leading to the memory order $f[N] and
1706 Unfortunately, when big-endian the most significant
1707 part of the double is stored first, and the least
1708 significant is stored second. This leads to the
1709 registers being ordered in memory as firt $f[N+1] and
1712 For the big-endian case make certain that the
1713 addresses point at the correct (swapped) locations
1714 $f[N] and $f[N+1] pair (keep in mind that
1715 reg_position is decremented each time through the
1718 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1719 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1721 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1722 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1725 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1726 .addr
= reg_position
;
1727 reg_position
-= mips_abi_regsize (gdbarch
);
1730 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1731 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1734 /* SP_REGNUM, contains the value and not the address. */
1735 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1737 return (*this_cache
);
1741 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1742 struct frame_id
*this_id
)
1744 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1746 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1750 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1752 int regnum
, int *optimizedp
,
1753 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1754 int *realnump
, void *valuep
)
1756 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1758 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1759 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1762 static const struct frame_unwind mips_mdebug_frame_unwind
=
1765 mips_mdebug_frame_this_id
,
1766 mips_mdebug_frame_prev_register
1769 static const struct frame_unwind
*
1770 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1772 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1773 CORE_ADDR startaddr
= 0;
1774 mips_extra_func_info_t proc_desc
;
1777 /* Only use the mdebug frame unwinder on mdebug frames where all the
1778 registers have been saved. Leave hard cases such as no mdebug or
1779 in prologue for the heuristic unwinders. */
1781 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1782 if (proc_desc
== NULL
)
1785 /* Not sure exactly what kernel_trap means, but if it means the
1786 kernel saves the registers without a prologue doing it, we better
1787 not examine the prologue to see whether registers have been saved
1789 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1791 return &mips_mdebug_frame_unwind
;
1793 /* In any frame other than the innermost or a frame interrupted by a
1794 signal, we assume that all registers have been saved. This
1795 assumes that all register saves in a function happen before the
1796 first function call. */
1797 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1798 return &mips_mdebug_frame_unwind
;
1804 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1807 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1812 static const struct frame_base mips_mdebug_frame_base
= {
1813 &mips_mdebug_frame_unwind
,
1814 mips_mdebug_frame_base_address
,
1815 mips_mdebug_frame_base_address
,
1816 mips_mdebug_frame_base_address
1819 static const struct frame_base
*
1820 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1822 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1823 return &mips_mdebug_frame_base
;
1828 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1829 Procedures that use the 32-bit instruction set are handled by the
1830 mips_insn32 unwinder. */
1832 static struct mips_frame_cache
*
1833 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1835 mips_extra_func_info_t proc_desc
;
1836 struct mips_frame_cache
*cache
;
1837 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1838 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1839 /* r0 bit means kernel trap */
1841 /* What registers have been saved? Bitmasks. */
1842 unsigned long gen_mask
, float_mask
;
1844 if ((*this_cache
) != NULL
)
1845 return (*this_cache
);
1846 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1847 (*this_cache
) = cache
;
1848 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1850 /* Synthesize a proc descriptor. */
1852 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1853 CORE_ADDR start_addr
;
1855 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1856 if (start_addr
== 0)
1857 start_addr
= heuristic_proc_start (pc
);
1859 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
);
1862 /* Extract the frame's base. */
1863 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1864 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1866 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1867 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1868 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1870 /* In any frame other than the innermost or a frame interrupted by a
1871 signal, we assume that all registers have been saved. This
1872 assumes that all register saves in a function happen before the
1873 first function call. */
1874 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1875 /* Not sure exactly what kernel_trap means, but if it means the
1876 kernel saves the registers without a prologue doing it, we
1877 better not examine the prologue to see whether registers
1878 have been saved yet. */
1881 /* We need to figure out whether the registers that the
1882 proc_desc claims are saved have been saved yet. */
1886 /* Bitmasks; set if we have found a save for the register. */
1887 unsigned long gen_save_found
= 0;
1888 unsigned long float_save_found
= 0;
1891 /* If the address is odd, assume this is MIPS16 code. */
1892 addr
= PROC_LOW_ADDR (proc_desc
);
1893 mips16
= pc_is_mips16 (addr
);
1895 /* Scan through this function's instructions preceding the
1896 current PC, and look for those that save registers. */
1897 while (addr
< frame_pc_unwind (next_frame
))
1901 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1903 addr
+= MIPS16_INSTLEN
;
1907 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1908 &gen_save_found
, &float_save_found
);
1909 addr
+= MIPS_INSTLEN
;
1912 gen_mask
= gen_save_found
;
1913 float_mask
= float_save_found
;
1916 /* Fill in the offsets for the registers which gen_mask says were
1919 CORE_ADDR reg_position
= (cache
->base
1920 + PROC_REG_OFFSET (proc_desc
));
1922 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1923 if (gen_mask
& 0x80000000)
1925 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1926 reg_position
-= mips_abi_regsize (gdbarch
);
1930 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1931 order of that normally used by gcc. Therefore, we have to fetch
1932 the first instruction of the function, and if it's an entry
1933 instruction that saves $s0 or $s1, correct their saved addresses. */
1934 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1936 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1937 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1941 int sreg_count
= (inst
>> 6) & 3;
1943 /* Check if the ra register was pushed on the stack. */
1944 CORE_ADDR reg_position
= (cache
->base
1945 + PROC_REG_OFFSET (proc_desc
));
1947 reg_position
-= mips_abi_regsize (gdbarch
);
1949 /* Check if the s0 and s1 registers were pushed on the
1951 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1953 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1955 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1956 reg_position
-= mips_abi_regsize (gdbarch
);
1961 /* Fill in the offsets for the registers which float_mask says were
1964 CORE_ADDR reg_position
= (cache
->base
1965 + PROC_FREG_OFFSET (proc_desc
));
1967 /* Fill in the offsets for the float registers which float_mask
1969 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1970 if (float_mask
& 0x80000000)
1972 if (mips_abi_regsize (gdbarch
) == 4
1973 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1975 /* On a big endian 32 bit ABI, floating point registers
1976 are paired to form doubles such that the most
1977 significant part is in $f[N+1] and the least
1978 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1979 registers are also spilled as a pair and stored as a
1982 When little-endian the least significant part is
1983 stored first leading to the memory order $f[N] and
1986 Unfortunately, when big-endian the most significant
1987 part of the double is stored first, and the least
1988 significant is stored second. This leads to the
1989 registers being ordered in memory as firt $f[N+1] and
1992 For the big-endian case make certain that the
1993 addresses point at the correct (swapped) locations
1994 $f[N] and $f[N+1] pair (keep in mind that
1995 reg_position is decremented each time through the
1998 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1999 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
2001 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2002 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
2005 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2006 .addr
= reg_position
;
2007 reg_position
-= mips_abi_regsize (gdbarch
);
2010 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2011 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2014 /* SP_REGNUM, contains the value and not the address. */
2015 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2017 return (*this_cache
);
2021 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2022 struct frame_id
*this_id
)
2024 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2026 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2030 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
2032 int regnum
, int *optimizedp
,
2033 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2034 int *realnump
, void *valuep
)
2036 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2038 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2039 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2042 static const struct frame_unwind mips_insn16_frame_unwind
=
2045 mips_insn16_frame_this_id
,
2046 mips_insn16_frame_prev_register
2049 static const struct frame_unwind
*
2050 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
2052 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2053 if (pc_is_mips16 (pc
))
2054 return &mips_insn16_frame_unwind
;
2059 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
2062 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2067 static const struct frame_base mips_insn16_frame_base
=
2069 &mips_insn16_frame_unwind
,
2070 mips_insn16_frame_base_address
,
2071 mips_insn16_frame_base_address
,
2072 mips_insn16_frame_base_address
2075 static const struct frame_base
*
2076 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
2078 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
2079 return &mips_insn16_frame_base
;
2084 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2085 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2086 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2089 static struct mips_frame_cache
*
2090 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2092 mips_extra_func_info_t proc_desc
;
2093 struct mips_frame_cache
*cache
;
2094 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2095 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2096 /* r0 bit means kernel trap */
2098 /* What registers have been saved? Bitmasks. */
2099 unsigned long gen_mask
, float_mask
;
2101 if ((*this_cache
) != NULL
)
2102 return (*this_cache
);
2103 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2104 (*this_cache
) = cache
;
2105 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2107 /* Synthesize a proc descriptor. */
2109 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2110 CORE_ADDR start_addr
;
2112 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2113 if (start_addr
== 0)
2114 start_addr
= heuristic_proc_start (pc
);
2116 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
);
2119 if (proc_desc
== NULL
)
2120 /* I'm not sure how/whether this can happen. Normally when we
2121 can't find a proc_desc, we "synthesize" one using
2122 heuristic_proc_desc and set the saved_regs right away. */
2125 /* Extract the frame's base. */
2126 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2127 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2129 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
2130 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
2131 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
2133 /* In any frame other than the innermost or a frame interrupted by a
2134 signal, we assume that all registers have been saved. This
2135 assumes that all register saves in a function happen before the
2136 first function call. */
2137 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
2138 /* Not sure exactly what kernel_trap means, but if it means the
2139 kernel saves the registers without a prologue doing it, we
2140 better not examine the prologue to see whether registers
2141 have been saved yet. */
2144 /* We need to figure out whether the registers that the
2145 proc_desc claims are saved have been saved yet. */
2149 /* Bitmasks; set if we have found a save for the register. */
2150 unsigned long gen_save_found
= 0;
2151 unsigned long float_save_found
= 0;
2153 addr
= PROC_LOW_ADDR (proc_desc
);
2155 /* Scan through this function's instructions preceding the
2156 current PC, and look for those that save registers. */
2157 while (addr
< frame_pc_unwind (next_frame
))
2159 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
2160 &gen_save_found
, &float_save_found
);
2161 addr
+= MIPS_INSTLEN
;
2163 gen_mask
= gen_save_found
;
2164 float_mask
= float_save_found
;
2167 /* Fill in the offsets for the registers which gen_mask says were
2170 CORE_ADDR reg_position
= (cache
->base
2171 + PROC_REG_OFFSET (proc_desc
));
2173 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
2174 if (gen_mask
& 0x80000000)
2176 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
2177 reg_position
-= mips_abi_regsize (gdbarch
);
2181 /* Fill in the offsets for the registers which float_mask says were
2184 CORE_ADDR reg_position
= (cache
->base
+ PROC_FREG_OFFSET (proc_desc
));
2187 /* Fill in the offsets for the float registers which float_mask
2189 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
2190 if (float_mask
& 0x80000000)
2193 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
;
2195 if (mips_abi_regsize (gdbarch
) == 4
2196 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2198 /* On a big endian 32 bit ABI, floating point registers
2199 are paired to form doubles such that the most
2200 significant part is in $f[N+1] and the least
2201 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
2202 registers are also spilled as a pair and stored as a
2205 When little-endian the least significant part is
2206 stored first leading to the memory order $f[N] and
2209 Unfortunately, when big-endian the most significant
2210 part of the double is stored first, and the least
2211 significant is stored second. This leads to the
2212 registers being ordered in memory as firt $f[N+1] and
2215 For the big-endian case make certain that the
2216 addresses point at the correct (swapped) locations
2217 $f[N] and $f[N+1] pair (keep in mind that
2218 reg_position is decremented each time through the
2221 cache
->saved_regs
[regno
].addr
=
2222 reg_position
- mips_abi_regsize (gdbarch
);
2224 cache
->saved_regs
[regno
].addr
=
2225 reg_position
+ mips_abi_regsize (gdbarch
);
2228 cache
->saved_regs
[regno
].addr
= reg_position
;
2229 reg_position
-= mips_abi_regsize (gdbarch
);
2232 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2233 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2236 /* SP_REGNUM, contains the value and not the address. */
2237 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2239 return (*this_cache
);
2243 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2244 struct frame_id
*this_id
)
2246 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2248 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2252 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2254 int regnum
, int *optimizedp
,
2255 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2256 int *realnump
, void *valuep
)
2258 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2260 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2261 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2264 static const struct frame_unwind mips_insn32_frame_unwind
=
2267 mips_insn32_frame_this_id
,
2268 mips_insn32_frame_prev_register
2271 static const struct frame_unwind
*
2272 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2274 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2275 if (! pc_is_mips16 (pc
))
2276 return &mips_insn32_frame_unwind
;
2281 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2284 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2289 static const struct frame_base mips_insn32_frame_base
=
2291 &mips_insn32_frame_unwind
,
2292 mips_insn32_frame_base_address
,
2293 mips_insn32_frame_base_address
,
2294 mips_insn32_frame_base_address
2297 static const struct frame_base
*
2298 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2300 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2301 return &mips_insn32_frame_base
;
2306 static struct trad_frame_cache
*
2307 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2310 CORE_ADDR start_addr
;
2311 CORE_ADDR stack_addr
;
2312 struct trad_frame_cache
*this_trad_cache
;
2314 if ((*this_cache
) != NULL
)
2315 return (*this_cache
);
2316 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2317 (*this_cache
) = this_trad_cache
;
2319 /* The return address is in the link register. */
2320 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2322 /* Frame ID, since it's a frameless / stackless function, no stack
2323 space is allocated and SP on entry is the current SP. */
2324 pc
= frame_pc_unwind (next_frame
);
2325 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2326 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2327 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2329 /* Assume that the frame's base is the same as the
2331 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2333 return this_trad_cache
;
2337 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2338 struct frame_id
*this_id
)
2340 struct trad_frame_cache
*this_trad_cache
2341 = mips_stub_frame_cache (next_frame
, this_cache
);
2342 trad_frame_get_id (this_trad_cache
, this_id
);
2346 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2348 int regnum
, int *optimizedp
,
2349 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2350 int *realnump
, void *valuep
)
2352 struct trad_frame_cache
*this_trad_cache
2353 = mips_stub_frame_cache (next_frame
, this_cache
);
2354 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2355 lvalp
, addrp
, realnump
, valuep
);
2358 static const struct frame_unwind mips_stub_frame_unwind
=
2361 mips_stub_frame_this_id
,
2362 mips_stub_frame_prev_register
2365 static const struct frame_unwind
*
2366 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2368 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2369 if (in_plt_section (pc
, NULL
))
2370 return &mips_stub_frame_unwind
;
2376 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2379 struct trad_frame_cache
*this_trad_cache
2380 = mips_stub_frame_cache (next_frame
, this_cache
);
2381 return trad_frame_get_this_base (this_trad_cache
);
2384 static const struct frame_base mips_stub_frame_base
=
2386 &mips_stub_frame_unwind
,
2387 mips_stub_frame_base_address
,
2388 mips_stub_frame_base_address
,
2389 mips_stub_frame_base_address
2392 static const struct frame_base
*
2393 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2395 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2396 return &mips_stub_frame_base
;
2402 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2404 /* Always a pseudo. */
2405 gdb_assert (regno
>= NUM_REGS
);
2409 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2412 else if ((regno
% NUM_REGS
) == MIPS_SP_REGNUM
)
2413 /* MIPS_SP_REGNUM is special, its value is stored in saved_regs.
2414 In fact, it is so special that it can even only be fetched
2415 using a raw register number! Once this code as been converted
2416 to frame-unwind the problem goes away. */
2417 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
2419 return frame_unwind_register_signed (fi
, regno
);
2423 /* mips_addr_bits_remove - remove useless address bits */
2426 mips_addr_bits_remove (CORE_ADDR addr
)
2428 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2429 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2430 /* This hack is a work-around for existing boards using PMON, the
2431 simulator, and any other 64-bit targets that doesn't have true
2432 64-bit addressing. On these targets, the upper 32 bits of
2433 addresses are ignored by the hardware. Thus, the PC or SP are
2434 likely to have been sign extended to all 1s by instruction
2435 sequences that load 32-bit addresses. For example, a typical
2436 piece of code that loads an address is this:
2438 lui $r2, <upper 16 bits>
2439 ori $r2, <lower 16 bits>
2441 But the lui sign-extends the value such that the upper 32 bits
2442 may be all 1s. The workaround is simply to mask off these
2443 bits. In the future, gcc may be changed to support true 64-bit
2444 addressing, and this masking will have to be disabled. */
2445 return addr
&= 0xffffffffUL
;
2450 /* mips_software_single_step() is called just before we want to resume
2451 the inferior, if we want to single-step it but there is no hardware
2452 or kernel single-step support (MIPS on GNU/Linux for example). We find
2453 the target of the coming instruction and breakpoint it.
2455 single_step is also called just after the inferior stops. If we had
2456 set up a simulated single-step, we undo our damage. */
2459 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2461 static CORE_ADDR next_pc
;
2462 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2463 static binsn_quantum break_mem
;
2466 if (insert_breakpoints_p
)
2468 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2469 next_pc
= mips_next_pc (pc
);
2471 target_insert_breakpoint (next_pc
, break_mem
);
2474 target_remove_breakpoint (next_pc
, break_mem
);
2477 static struct mips_extra_func_info temp_proc_desc
;
2479 /* This hack will go away once the get_prev_frame() code has been
2480 modified to set the frame's type first. That is BEFORE init extra
2481 frame info et.al. is called. This is because it will become
2482 possible to skip the init extra info call for sigtramp and dummy
2484 static CORE_ADDR
*temp_saved_regs
;
2486 /* Set a register's saved stack address in temp_saved_regs. If an
2487 address has already been set for this register, do nothing; this
2488 way we will only recognize the first save of a given register in a
2491 For simplicity, save the address in both [0 .. NUM_REGS) and
2492 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2493 is used as it is only second range (the ABI instead of ISA
2494 registers) that comes into play when finding saved registers in a
2498 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
2500 if (saved_regs
[regno
] == 0)
2502 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
2503 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
2508 /* Test whether the PC points to the return instruction at the
2509 end of a function. */
2512 mips_about_to_return (CORE_ADDR pc
)
2514 if (pc_is_mips16 (pc
))
2515 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2516 generates a "jr $ra"; other times it generates code to load
2517 the return address from the stack to an accessible register (such
2518 as $a3), then a "jr" using that register. This second case
2519 is almost impossible to distinguish from an indirect jump
2520 used for switch statements, so we don't even try. */
2521 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2523 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2527 /* This fencepost looks highly suspicious to me. Removing it also
2528 seems suspicious as it could affect remote debugging across serial
2532 heuristic_proc_start (CORE_ADDR pc
)
2539 pc
= ADDR_BITS_REMOVE (pc
);
2541 fence
= start_pc
- heuristic_fence_post
;
2545 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2546 fence
= VM_MIN_ADDRESS
;
2548 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2550 /* search back for previous return */
2551 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2552 if (start_pc
< fence
)
2554 /* It's not clear to me why we reach this point when
2555 stop_soon, but with this test, at least we
2556 don't print out warnings for every child forked (eg, on
2557 decstation). 22apr93 rich@cygnus.com. */
2558 if (stop_soon
== NO_STOP_QUIETLY
)
2560 static int blurb_printed
= 0;
2562 warning ("GDB can't find the start of the function at 0x%s.",
2567 /* This actually happens frequently in embedded
2568 development, when you first connect to a board
2569 and your stack pointer and pc are nowhere in
2570 particular. This message needs to give people
2571 in that situation enough information to
2572 determine that it's no big deal. */
2573 printf_filtered ("\n\
2574 GDB is unable to find the start of the function at 0x%s\n\
2575 and thus can't determine the size of that function's stack frame.\n\
2576 This means that GDB may be unable to access that stack frame, or\n\
2577 the frames below it.\n\
2578 This problem is most likely caused by an invalid program counter or\n\
2580 However, if you think GDB should simply search farther back\n\
2581 from 0x%s for code which looks like the beginning of a\n\
2582 function, you can increase the range of the search using the `set\n\
2583 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2590 else if (pc_is_mips16 (start_pc
))
2592 unsigned short inst
;
2594 /* On MIPS16, any one of the following is likely to be the
2595 start of a function:
2599 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2600 inst
= mips_fetch_instruction (start_pc
);
2601 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2602 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2603 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2604 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2606 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2607 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2612 else if (mips_about_to_return (start_pc
))
2614 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2621 /* Fetch the immediate value from a MIPS16 instruction.
2622 If the previous instruction was an EXTEND, use it to extend
2623 the upper bits of the immediate value. This is a helper function
2624 for mips16_heuristic_proc_desc. */
2627 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2628 unsigned short inst
, /* current instruction */
2629 int nbits
, /* number of bits in imm field */
2630 int scale
, /* scale factor to be applied to imm */
2631 int is_signed
) /* is the imm field signed? */
2635 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2637 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2638 if (offset
& 0x8000) /* check for negative extend */
2639 offset
= 0 - (0x10000 - (offset
& 0xffff));
2640 return offset
| (inst
& 0x1f);
2644 int max_imm
= 1 << nbits
;
2645 int mask
= max_imm
- 1;
2646 int sign_bit
= max_imm
>> 1;
2648 offset
= inst
& mask
;
2649 if (is_signed
&& (offset
& sign_bit
))
2650 offset
= 0 - (max_imm
- offset
);
2651 return offset
* scale
;
2656 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2657 stream from start_pc to limit_pc. */
2660 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2661 struct frame_info
*next_frame
, CORE_ADDR sp
)
2664 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2665 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2666 unsigned inst
= 0; /* current instruction */
2667 unsigned entry_inst
= 0; /* the entry instruction */
2669 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2671 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2672 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2674 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2676 /* Save the previous instruction. If it's an EXTEND, we'll extract
2677 the immediate offset extension from it in mips16_get_imm. */
2680 /* Fetch and decode the instruction. */
2681 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2682 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2683 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2685 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2686 if (offset
< 0) /* negative stack adjustment? */
2687 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2689 /* Exit loop if a positive stack adjustment is found, which
2690 usually means that the stack cleanup code in the function
2691 epilogue is reached. */
2694 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2696 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2697 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2698 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2699 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2701 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2703 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2704 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2705 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2706 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2708 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2710 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2711 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2712 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2714 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2716 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2717 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2718 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2720 else if (inst
== 0x673d) /* move $s1, $sp */
2723 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2725 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2727 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2728 frame_addr
= sp
+ offset
;
2729 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2730 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2732 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2734 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2735 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2736 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2737 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2739 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2741 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2742 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2743 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2744 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2746 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2747 entry_inst
= inst
; /* save for later processing */
2748 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2749 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2752 /* The entry instruction is typically the first instruction in a function,
2753 and it stores registers at offsets relative to the value of the old SP
2754 (before the prologue). But the value of the sp parameter to this
2755 function is the new SP (after the prologue has been executed). So we
2756 can't calculate those offsets until we've seen the entire prologue,
2757 and can calculate what the old SP must have been. */
2758 if (entry_inst
!= 0)
2760 int areg_count
= (entry_inst
>> 8) & 7;
2761 int sreg_count
= (entry_inst
>> 6) & 3;
2763 /* The entry instruction always subtracts 32 from the SP. */
2764 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2766 /* Now we can calculate what the SP must have been at the
2767 start of the function prologue. */
2768 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2770 /* Check if a0-a3 were saved in the caller's argument save area. */
2771 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2773 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2774 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2775 offset
+= mips_abi_regsize (current_gdbarch
);
2778 /* Check if the ra register was pushed on the stack. */
2780 if (entry_inst
& 0x20)
2782 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2783 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2784 offset
-= mips_abi_regsize (current_gdbarch
);
2787 /* Check if the s0 and s1 registers were pushed on the stack. */
2788 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2790 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2791 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2792 offset
-= mips_abi_regsize (current_gdbarch
);
2798 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2799 struct frame_info
*next_frame
, CORE_ADDR sp
)
2802 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2804 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2805 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2806 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2807 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2808 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2810 unsigned long inst
, high_word
, low_word
;
2813 /* Fetch the instruction. */
2814 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2816 /* Save some code by pre-extracting some useful fields. */
2817 high_word
= (inst
>> 16) & 0xffff;
2818 low_word
= inst
& 0xffff;
2819 reg
= high_word
& 0x1f;
2821 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2822 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2823 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2825 if (low_word
& 0x8000) /* negative stack adjustment? */
2826 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2828 /* Exit loop if a positive stack adjustment is found, which
2829 usually means that the stack cleanup code in the function
2830 epilogue is reached. */
2833 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2835 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2836 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2838 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2840 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2842 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2843 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2845 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2847 /* Old gcc frame, r30 is virtual frame pointer. */
2848 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2849 frame_addr
= sp
+ low_word
;
2850 else if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2852 unsigned alloca_adjust
;
2853 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2854 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2855 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2856 if (alloca_adjust
> 0)
2858 /* FP > SP + frame_size. This may be because
2859 * of an alloca or somethings similar.
2860 * Fix sp to "pre-alloca" value, and try again.
2862 sp
+= alloca_adjust
;
2867 /* move $30,$sp. With different versions of gas this will be either
2868 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2869 Accept any one of these. */
2870 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2872 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2873 if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2875 unsigned alloca_adjust
;
2876 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2877 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2878 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2879 if (alloca_adjust
> 0)
2881 /* FP > SP + frame_size. This may be because
2882 * of an alloca or somethings similar.
2883 * Fix sp to "pre-alloca" value, and try again.
2885 sp
+= alloca_adjust
;
2890 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2892 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2893 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2898 static mips_extra_func_info_t
2899 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2900 struct frame_info
*next_frame
)
2904 /* Can be called when there's no process, and hence when there's no
2906 if (next_frame
!= NULL
)
2907 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2913 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2914 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2915 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2916 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2917 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2918 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2920 if (start_pc
+ 200 < limit_pc
)
2921 limit_pc
= start_pc
+ 200;
2922 if (pc_is_mips16 (start_pc
))
2923 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2925 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2926 return &temp_proc_desc
;
2929 struct mips_objfile_private
2935 /* Global used to communicate between non_heuristic_proc_desc and
2936 compare_pdr_entries within qsort (). */
2937 static bfd
*the_bfd
;
2940 compare_pdr_entries (const void *a
, const void *b
)
2942 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2943 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2947 else if (lhs
== rhs
)
2953 static mips_extra_func_info_t
2954 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2956 CORE_ADDR startaddr
;
2957 mips_extra_func_info_t proc_desc
;
2958 struct block
*b
= block_for_pc (pc
);
2960 struct obj_section
*sec
;
2961 struct mips_objfile_private
*priv
;
2963 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2965 *addrptr
= startaddr
;
2969 sec
= find_pc_section (pc
);
2972 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2974 /* Search the ".pdr" section generated by GAS. This includes most of
2975 the information normally found in ECOFF PDRs. */
2977 the_bfd
= sec
->objfile
->obfd
;
2979 && (the_bfd
->format
== bfd_object
2980 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2981 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2983 /* Right now GAS only outputs the address as a four-byte sequence.
2984 This means that we should not bother with this method on 64-bit
2985 targets (until that is fixed). */
2987 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2988 sizeof (struct mips_objfile_private
));
2990 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2992 else if (priv
== NULL
)
2996 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2997 sizeof (struct mips_objfile_private
));
2999 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
3002 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
3003 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
3005 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
3006 priv
->contents
, 0, priv
->size
);
3008 /* In general, the .pdr section is sorted. However, in the
3009 presence of multiple code sections (and other corner cases)
3010 it can become unsorted. Sort it so that we can use a faster
3012 qsort (priv
->contents
, priv
->size
/ 32, 32,
3013 compare_pdr_entries
);
3018 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
3022 if (priv
->size
!= 0)
3029 high
= priv
->size
/ 32;
3031 /* We've found a .pdr section describing this objfile. We want to
3032 find the entry which describes this code address. The .pdr
3033 information is not very descriptive; we have only a function
3034 start address. We have to look for the closest entry, because
3035 the local symbol at the beginning of this function may have
3036 been stripped - so if we ask the symbol table for the start
3037 address we may get a preceding global function. */
3039 /* First, find the last .pdr entry starting at or before PC. */
3042 mid
= (low
+ high
) / 2;
3044 ptr
= priv
->contents
+ mid
* 32;
3045 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3046 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3047 SECT_OFF_TEXT (sec
->objfile
));
3054 while (low
!= high
);
3056 /* Both low and high point one past the PDR of interest. If
3057 both are zero, that means this PC is before any region
3058 covered by a PDR, i.e. pdr_pc for the first PDR entry is
3062 ptr
= priv
->contents
+ (low
- 1) * 32;
3063 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3064 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3065 SECT_OFF_TEXT (sec
->objfile
));
3068 /* We don't have a range, so we have no way to know for sure
3069 whether we're in the correct PDR or a PDR for a preceding
3070 function and the current function was a stripped local
3071 symbol. But if the PDR's PC is at least as great as the
3072 best guess from the symbol table, assume that it does cover
3073 the right area; if a .pdr section is present at all then
3074 nearly every function will have an entry. The biggest exception
3075 will be the dynamic linker stubs; conveniently these are
3076 placed before .text instead of after. */
3078 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
3080 struct symbol
*sym
= find_pc_function (pc
);
3085 /* Fill in what we need of the proc_desc. */
3086 proc_desc
= (mips_extra_func_info_t
)
3087 obstack_alloc (&sec
->objfile
->objfile_obstack
,
3088 sizeof (struct mips_extra_func_info
));
3089 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
3091 /* Only used for dummy frames. */
3092 PROC_HIGH_ADDR (proc_desc
) = 0;
3094 PROC_FRAME_OFFSET (proc_desc
)
3095 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
3096 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3098 PROC_FRAME_ADJUST (proc_desc
) = 0;
3099 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3101 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3103 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3105 PROC_FREG_OFFSET (proc_desc
)
3106 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
3107 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3109 proc_desc
->pdr
.isym
= (long) sym
;
3119 if (startaddr
> BLOCK_START (b
))
3121 /* This is the "pathological" case referred to in a comment in
3122 print_frame_info. It might be better to move this check into
3127 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
3129 /* If we never found a PDR for this function in symbol reading, then
3130 examine prologues to find the information. */
3133 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
3134 if (PROC_FRAME_REG (proc_desc
) == -1)
3143 /* MIPS stack frames are almost impenetrable. When execution stops,
3144 we basically have to look at symbol information for the function
3145 that we stopped in, which tells us *which* register (if any) is
3146 the base of the frame pointer, and what offset from that register
3147 the frame itself is at.
3149 This presents a problem when trying to examine a stack in memory
3150 (that isn't executing at the moment), using the "frame" command. We
3151 don't have a PC, nor do we have any registers except SP.
3153 This routine takes two arguments, SP and PC, and tries to make the
3154 cached frames look as if these two arguments defined a frame on the
3155 cache. This allows the rest of info frame to extract the important
3156 arguments without difficulty. */
3159 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
3162 error ("MIPS frame specifications require two arguments: sp and pc");
3164 return create_new_frame (argv
[0], argv
[1]);
3167 /* According to the current ABI, should the type be passed in a
3168 floating-point register (assuming that there is space)? When there
3169 is no FPU, FP are not even considered as possibile candidates for
3170 FP registers and, consequently this returns false - forces FP
3171 arguments into integer registers. */
3174 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
3176 return ((typecode
== TYPE_CODE_FLT
3178 && (typecode
== TYPE_CODE_STRUCT
3179 || typecode
== TYPE_CODE_UNION
)
3180 && TYPE_NFIELDS (arg_type
) == 1
3181 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
3182 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
3185 /* On o32, argument passing in GPRs depends on the alignment of the type being
3186 passed. Return 1 if this type must be aligned to a doubleword boundary. */
3189 mips_type_needs_double_align (struct type
*type
)
3191 enum type_code typecode
= TYPE_CODE (type
);
3193 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
3195 else if (typecode
== TYPE_CODE_STRUCT
)
3197 if (TYPE_NFIELDS (type
) < 1)
3199 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
3201 else if (typecode
== TYPE_CODE_UNION
)
3205 n
= TYPE_NFIELDS (type
);
3206 for (i
= 0; i
< n
; i
++)
3207 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3214 /* Adjust the address downward (direction of stack growth) so that it
3215 is correctly aligned for a new stack frame. */
3217 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3219 return align_down (addr
, 16);
3222 /* Determine how a return value is stored within the MIPS register
3223 file, given the return type `valtype'. */
3225 struct return_value_word
3234 return_value_location (struct type
*valtype
,
3235 struct return_value_word
*hi
,
3236 struct return_value_word
*lo
)
3238 int len
= TYPE_LENGTH (valtype
);
3239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3241 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3242 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3243 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3245 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3247 /* We need to break a 64bit float in two 32 bit halves and
3248 spread them across a floating-point register pair. */
3249 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3250 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3251 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3252 && register_size (current_gdbarch
,
3253 mips_regnum (current_gdbarch
)->
3254 fp0
) == 8) ? 4 : 0);
3255 hi
->reg_offset
= lo
->reg_offset
;
3256 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3257 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3263 /* The floating point value fits in a single floating-point
3265 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3266 && register_size (current_gdbarch
,
3267 mips_regnum (current_gdbarch
)->
3269 && len
== 4) ? 4 : 0);
3270 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3281 /* Locate a result possibly spread across two registers. */
3283 lo
->reg
= regnum
+ 0;
3284 hi
->reg
= regnum
+ 1;
3285 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3286 && len
< mips_abi_regsize (current_gdbarch
))
3288 /* "un-left-justify" the value in the low register */
3289 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3294 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3295 && len
< mips_abi_regsize (current_gdbarch
) * 2
3296 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3297 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3299 /* "un-left-justify" the value spread across two registers. */
3300 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3301 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3303 hi
->len
= len
- lo
->len
;
3307 /* Only perform a partial copy of the second register. */
3310 if (len
> mips_abi_regsize (current_gdbarch
))
3312 lo
->len
= mips_abi_regsize (current_gdbarch
);
3313 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3321 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3322 && register_size (current_gdbarch
, regnum
) == 8
3323 && mips_abi_regsize (current_gdbarch
) == 4)
3325 /* Account for the fact that only the least-signficant part
3326 of the register is being used */
3327 lo
->reg_offset
+= 4;
3328 hi
->reg_offset
+= 4;
3331 hi
->buf_offset
= lo
->len
;
3335 /* Should call_function allocate stack space for a struct return? */
3338 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3341 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3344 /* Should call_function pass struct by reference?
3345 For each architecture, structs are passed either by
3346 value or by reference, depending on their size. */
3349 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3351 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3352 int len
= TYPE_LENGTH (check_typedef (type
));
3353 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3355 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3356 return (len
> mips_abi_regsize (current_gdbarch
));
3362 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3363 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3364 int nargs
, struct value
**args
, CORE_ADDR sp
,
3365 int struct_return
, CORE_ADDR struct_addr
)
3371 int stack_offset
= 0;
3372 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3373 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3375 /* For shared libraries, "t9" needs to point at the function
3377 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3379 /* Set the return address register to point to the entry point of
3380 the program, where a breakpoint lies in wait. */
3381 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3383 /* First ensure that the stack and structure return address (if any)
3384 are properly aligned. The stack has to be at least 64-bit
3385 aligned even on 32-bit machines, because doubles must be 64-bit
3386 aligned. For n32 and n64, stack frames need to be 128-bit
3387 aligned, so we round to this widest known alignment. */
3389 sp
= align_down (sp
, 16);
3390 struct_addr
= align_down (struct_addr
, 16);
3392 /* Now make space on the stack for the args. We allocate more
3393 than necessary for EABI, because the first few arguments are
3394 passed in registers, but that's OK. */
3395 for (argnum
= 0; argnum
< nargs
; argnum
++)
3396 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3397 mips_stack_argsize (gdbarch
));
3398 sp
-= align_up (len
, 16);
3401 fprintf_unfiltered (gdb_stdlog
,
3402 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3403 paddr_nz (sp
), (long) align_up (len
, 16));
3405 /* Initialize the integer and float register pointers. */
3407 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3409 /* The struct_return pointer occupies the first parameter-passing reg. */
3413 fprintf_unfiltered (gdb_stdlog
,
3414 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3415 argreg
, paddr_nz (struct_addr
));
3416 write_register (argreg
++, struct_addr
);
3419 /* Now load as many as possible of the first arguments into
3420 registers, and push the rest onto the stack. Loop thru args
3421 from first to last. */
3422 for (argnum
= 0; argnum
< nargs
; argnum
++)
3425 char valbuf
[MAX_REGISTER_SIZE
];
3426 struct value
*arg
= args
[argnum
];
3427 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3428 int len
= TYPE_LENGTH (arg_type
);
3429 enum type_code typecode
= TYPE_CODE (arg_type
);
3432 fprintf_unfiltered (gdb_stdlog
,
3433 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3434 argnum
+ 1, len
, (int) typecode
);
3436 /* The EABI passes structures that do not fit in a register by
3438 if (len
> mips_abi_regsize (gdbarch
)
3439 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3441 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3442 VALUE_ADDRESS (arg
));
3443 typecode
= TYPE_CODE_PTR
;
3444 len
= mips_abi_regsize (gdbarch
);
3447 fprintf_unfiltered (gdb_stdlog
, " push");
3450 val
= (char *) VALUE_CONTENTS (arg
);
3452 /* 32-bit ABIs always start floating point arguments in an
3453 even-numbered floating point register. Round the FP register
3454 up before the check to see if there are any FP registers
3455 left. Non MIPS_EABI targets also pass the FP in the integer
3456 registers so also round up normal registers. */
3457 if (mips_abi_regsize (gdbarch
) < 8
3458 && fp_register_arg_p (typecode
, arg_type
))
3460 if ((float_argreg
& 1))
3464 /* Floating point arguments passed in registers have to be
3465 treated specially. On 32-bit architectures, doubles
3466 are passed in register pairs; the even register gets
3467 the low word, and the odd register gets the high word.
3468 On non-EABI processors, the first two floating point arguments are
3469 also copied to general registers, because MIPS16 functions
3470 don't use float registers for arguments. This duplication of
3471 arguments in general registers can't hurt non-MIPS16 functions
3472 because those registers are normally skipped. */
3473 /* MIPS_EABI squeezes a struct that contains a single floating
3474 point value into an FP register instead of pushing it onto the
3476 if (fp_register_arg_p (typecode
, arg_type
)
3477 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3479 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3481 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3482 unsigned long regval
;
3484 /* Write the low word of the double to the even register(s). */
3485 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3487 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3488 float_argreg
, phex (regval
, 4));
3489 write_register (float_argreg
++, regval
);
3491 /* Write the high word of the double to the odd register(s). */
3492 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3494 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3495 float_argreg
, phex (regval
, 4));
3496 write_register (float_argreg
++, regval
);
3500 /* This is a floating point value that fits entirely
3501 in a single register. */
3502 /* On 32 bit ABI's the float_argreg is further adjusted
3503 above to ensure that it is even register aligned. */
3504 LONGEST regval
= extract_unsigned_integer (val
, len
);
3506 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3507 float_argreg
, phex (regval
, len
));
3508 write_register (float_argreg
++, regval
);
3513 /* Copy the argument to general registers or the stack in
3514 register-sized pieces. Large arguments are split between
3515 registers and stack. */
3516 /* Note: structs whose size is not a multiple of
3517 mips_abi_regsize() are treated specially: Irix cc passes
3518 them in registers where gcc sometimes puts them on the
3519 stack. For maximum compatibility, we will put them in
3521 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3522 && (len
% mips_abi_regsize (gdbarch
) != 0));
3524 /* Note: Floating-point values that didn't fit into an FP
3525 register are only written to memory. */
3528 /* Remember if the argument was written to the stack. */
3529 int stack_used_p
= 0;
3530 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3531 ? len
: mips_abi_regsize (gdbarch
));
3534 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3537 /* Write this portion of the argument to the stack. */
3538 if (argreg
> MIPS_LAST_ARG_REGNUM
3540 || fp_register_arg_p (typecode
, arg_type
))
3542 /* Should shorter than int integer values be
3543 promoted to int before being stored? */
3544 int longword_offset
= 0;
3547 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3549 if (mips_stack_argsize (gdbarch
) == 8
3550 && (typecode
== TYPE_CODE_INT
3551 || typecode
== TYPE_CODE_PTR
3552 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3553 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3554 else if ((typecode
== TYPE_CODE_STRUCT
3555 || typecode
== TYPE_CODE_UNION
)
3556 && (TYPE_LENGTH (arg_type
)
3557 < mips_stack_argsize (gdbarch
)))
3558 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3563 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3564 paddr_nz (stack_offset
));
3565 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3566 paddr_nz (longword_offset
));
3569 addr
= sp
+ stack_offset
+ longword_offset
;
3574 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3576 for (i
= 0; i
< partial_len
; i
++)
3578 fprintf_unfiltered (gdb_stdlog
, "%02x",
3582 write_memory (addr
, val
, partial_len
);
3585 /* Note!!! This is NOT an else clause. Odd sized
3586 structs may go thru BOTH paths. Floating point
3587 arguments will not. */
3588 /* Write this portion of the argument to a general
3589 purpose register. */
3590 if (argreg
<= MIPS_LAST_ARG_REGNUM
3591 && !fp_register_arg_p (typecode
, arg_type
))
3594 extract_unsigned_integer (val
, partial_len
);
3597 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3600 mips_abi_regsize (gdbarch
)));
3601 write_register (argreg
, regval
);
3608 /* Compute the the offset into the stack at which we
3609 will copy the next parameter.
3611 In the new EABI (and the NABI32), the stack_offset
3612 only needs to be adjusted when it has been used. */
3615 stack_offset
+= align_up (partial_len
,
3616 mips_stack_argsize (gdbarch
));
3620 fprintf_unfiltered (gdb_stdlog
, "\n");
3623 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3625 /* Return adjusted stack pointer. */
3629 /* Given a return value in `regbuf' with a type `valtype', extract and
3630 copy its value into `valbuf'. */
3633 mips_eabi_extract_return_value (struct type
*valtype
,
3634 char regbuf
[], char *valbuf
)
3636 struct return_value_word lo
;
3637 struct return_value_word hi
;
3638 return_value_location (valtype
, &hi
, &lo
);
3640 memcpy (valbuf
+ lo
.buf_offset
,
3641 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3642 lo
.reg_offset
, lo
.len
);
3645 memcpy (valbuf
+ hi
.buf_offset
,
3646 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3647 hi
.reg_offset
, hi
.len
);
3650 /* Given a return value in `valbuf' with a type `valtype', write it's
3651 value into the appropriate register. */
3654 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3656 char raw_buffer
[MAX_REGISTER_SIZE
];
3657 struct return_value_word lo
;
3658 struct return_value_word hi
;
3659 return_value_location (valtype
, &hi
, &lo
);
3661 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3662 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3663 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3664 raw_buffer
, register_size (current_gdbarch
,
3669 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3670 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3671 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3673 register_size (current_gdbarch
,
3678 /* N32/N64 ABI stuff. */
3681 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3682 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3683 int nargs
, struct value
**args
, CORE_ADDR sp
,
3684 int struct_return
, CORE_ADDR struct_addr
)
3690 int stack_offset
= 0;
3691 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3692 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3694 /* For shared libraries, "t9" needs to point at the function
3696 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3698 /* Set the return address register to point to the entry point of
3699 the program, where a breakpoint lies in wait. */
3700 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3702 /* First ensure that the stack and structure return address (if any)
3703 are properly aligned. The stack has to be at least 64-bit
3704 aligned even on 32-bit machines, because doubles must be 64-bit
3705 aligned. For n32 and n64, stack frames need to be 128-bit
3706 aligned, so we round to this widest known alignment. */
3708 sp
= align_down (sp
, 16);
3709 struct_addr
= align_down (struct_addr
, 16);
3711 /* Now make space on the stack for the args. */
3712 for (argnum
= 0; argnum
< nargs
; argnum
++)
3713 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3714 mips_stack_argsize (gdbarch
));
3715 sp
-= align_up (len
, 16);
3718 fprintf_unfiltered (gdb_stdlog
,
3719 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3720 paddr_nz (sp
), (long) align_up (len
, 16));
3722 /* Initialize the integer and float register pointers. */
3724 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3726 /* The struct_return pointer occupies the first parameter-passing reg. */
3730 fprintf_unfiltered (gdb_stdlog
,
3731 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3732 argreg
, paddr_nz (struct_addr
));
3733 write_register (argreg
++, struct_addr
);
3736 /* Now load as many as possible of the first arguments into
3737 registers, and push the rest onto the stack. Loop thru args
3738 from first to last. */
3739 for (argnum
= 0; argnum
< nargs
; argnum
++)
3742 struct value
*arg
= args
[argnum
];
3743 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3744 int len
= TYPE_LENGTH (arg_type
);
3745 enum type_code typecode
= TYPE_CODE (arg_type
);
3748 fprintf_unfiltered (gdb_stdlog
,
3749 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3750 argnum
+ 1, len
, (int) typecode
);
3752 val
= (char *) VALUE_CONTENTS (arg
);
3754 if (fp_register_arg_p (typecode
, arg_type
)
3755 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3757 /* This is a floating point value that fits entirely
3758 in a single register. */
3759 /* On 32 bit ABI's the float_argreg is further adjusted
3760 above to ensure that it is even register aligned. */
3761 LONGEST regval
= extract_unsigned_integer (val
, len
);
3763 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3764 float_argreg
, phex (regval
, len
));
3765 write_register (float_argreg
++, regval
);
3768 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3769 argreg
, phex (regval
, len
));
3770 write_register (argreg
, regval
);
3775 /* Copy the argument to general registers or the stack in
3776 register-sized pieces. Large arguments are split between
3777 registers and stack. */
3778 /* Note: structs whose size is not a multiple of
3779 mips_abi_regsize() are treated specially: Irix cc passes
3780 them in registers where gcc sometimes puts them on the
3781 stack. For maximum compatibility, we will put them in
3783 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3784 && (len
% mips_abi_regsize (gdbarch
) != 0));
3785 /* Note: Floating-point values that didn't fit into an FP
3786 register are only written to memory. */
3789 /* Rememer if the argument was written to the stack. */
3790 int stack_used_p
= 0;
3791 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3792 ? len
: mips_abi_regsize (gdbarch
));
3795 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3798 /* Write this portion of the argument to the stack. */
3799 if (argreg
> MIPS_LAST_ARG_REGNUM
3801 || fp_register_arg_p (typecode
, arg_type
))
3803 /* Should shorter than int integer values be
3804 promoted to int before being stored? */
3805 int longword_offset
= 0;
3808 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3810 if (mips_stack_argsize (gdbarch
) == 8
3811 && (typecode
== TYPE_CODE_INT
3812 || typecode
== TYPE_CODE_PTR
3813 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3814 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3819 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3820 paddr_nz (stack_offset
));
3821 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3822 paddr_nz (longword_offset
));
3825 addr
= sp
+ stack_offset
+ longword_offset
;
3830 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3832 for (i
= 0; i
< partial_len
; i
++)
3834 fprintf_unfiltered (gdb_stdlog
, "%02x",
3838 write_memory (addr
, val
, partial_len
);
3841 /* Note!!! This is NOT an else clause. Odd sized
3842 structs may go thru BOTH paths. Floating point
3843 arguments will not. */
3844 /* Write this portion of the argument to a general
3845 purpose register. */
3846 if (argreg
<= MIPS_LAST_ARG_REGNUM
3847 && !fp_register_arg_p (typecode
, arg_type
))
3850 extract_unsigned_integer (val
, partial_len
);
3852 /* A non-floating-point argument being passed in a
3853 general register. If a struct or union, and if
3854 the remaining length is smaller than the register
3855 size, we have to adjust the register value on
3858 It does not seem to be necessary to do the
3859 same for integral types.
3861 cagney/2001-07-23: gdb/179: Also, GCC, when
3862 outputting LE O32 with sizeof (struct) <
3863 mips_abi_regsize(), generates a left shift as
3864 part of storing the argument in a register a
3865 register (the left shift isn't generated when
3866 sizeof (struct) >= mips_abi_regsize()). Since
3867 it is quite possible that this is GCC
3868 contradicting the LE/O32 ABI, GDB has not been
3869 adjusted to accommodate this. Either someone
3870 needs to demonstrate that the LE/O32 ABI
3871 specifies such a left shift OR this new ABI gets
3872 identified as such and GDB gets tweaked
3875 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3876 && partial_len
< mips_abi_regsize (gdbarch
)
3877 && (typecode
== TYPE_CODE_STRUCT
||
3878 typecode
== TYPE_CODE_UNION
))
3879 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3883 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3886 mips_abi_regsize (gdbarch
)));
3887 write_register (argreg
, regval
);
3894 /* Compute the the offset into the stack at which we
3895 will copy the next parameter.
3897 In N32 (N64?), the stack_offset only needs to be
3898 adjusted when it has been used. */
3901 stack_offset
+= align_up (partial_len
,
3902 mips_stack_argsize (gdbarch
));
3906 fprintf_unfiltered (gdb_stdlog
, "\n");
3909 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3911 /* Return adjusted stack pointer. */
3915 static enum return_value_convention
3916 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3917 struct type
*type
, struct regcache
*regcache
,
3918 void *readbuf
, const void *writebuf
)
3920 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3921 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3922 || TYPE_CODE (type
) == TYPE_CODE_UNION
3923 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3924 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3925 return RETURN_VALUE_STRUCT_CONVENTION
;
3926 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3927 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3929 /* A floating-point value belongs in the least significant part
3932 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3933 mips_xfer_register (regcache
,
3934 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3936 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3937 return RETURN_VALUE_REGISTER_CONVENTION
;
3939 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3940 && TYPE_NFIELDS (type
) <= 2
3941 && TYPE_NFIELDS (type
) >= 1
3942 && ((TYPE_NFIELDS (type
) == 1
3943 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3945 || (TYPE_NFIELDS (type
) == 2
3946 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3948 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3950 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3952 /* A struct that contains one or two floats. Each value is part
3953 in the least significant part of their floating point
3957 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3958 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3960 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3963 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3965 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3966 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3967 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3969 return RETURN_VALUE_REGISTER_CONVENTION
;
3971 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3972 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3974 /* A structure or union. Extract the left justified value,
3975 regardless of the byte order. I.e. DO NOT USE
3979 for (offset
= 0, regnum
= V0_REGNUM
;
3980 offset
< TYPE_LENGTH (type
);
3981 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3983 int xfer
= register_size (current_gdbarch
, regnum
);
3984 if (offset
+ xfer
> TYPE_LENGTH (type
))
3985 xfer
= TYPE_LENGTH (type
) - offset
;
3987 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3988 offset
, xfer
, regnum
);
3989 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3990 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3992 return RETURN_VALUE_REGISTER_CONVENTION
;
3996 /* A scalar extract each part but least-significant-byte
4000 for (offset
= 0, regnum
= V0_REGNUM
;
4001 offset
< TYPE_LENGTH (type
);
4002 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4004 int xfer
= register_size (current_gdbarch
, regnum
);
4005 if (offset
+ xfer
> TYPE_LENGTH (type
))
4006 xfer
= TYPE_LENGTH (type
) - offset
;
4008 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4009 offset
, xfer
, regnum
);
4010 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4011 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4013 return RETURN_VALUE_REGISTER_CONVENTION
;
4017 /* O32 ABI stuff. */
4020 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4021 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4022 int nargs
, struct value
**args
, CORE_ADDR sp
,
4023 int struct_return
, CORE_ADDR struct_addr
)
4029 int stack_offset
= 0;
4030 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4031 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4033 /* For shared libraries, "t9" needs to point at the function
4035 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4037 /* Set the return address register to point to the entry point of
4038 the program, where a breakpoint lies in wait. */
4039 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4041 /* First ensure that the stack and structure return address (if any)
4042 are properly aligned. The stack has to be at least 64-bit
4043 aligned even on 32-bit machines, because doubles must be 64-bit
4044 aligned. For n32 and n64, stack frames need to be 128-bit
4045 aligned, so we round to this widest known alignment. */
4047 sp
= align_down (sp
, 16);
4048 struct_addr
= align_down (struct_addr
, 16);
4050 /* Now make space on the stack for the args. */
4051 for (argnum
= 0; argnum
< nargs
; argnum
++)
4052 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4053 mips_stack_argsize (gdbarch
));
4054 sp
-= align_up (len
, 16);
4057 fprintf_unfiltered (gdb_stdlog
,
4058 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
4059 paddr_nz (sp
), (long) align_up (len
, 16));
4061 /* Initialize the integer and float register pointers. */
4063 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4065 /* The struct_return pointer occupies the first parameter-passing reg. */
4069 fprintf_unfiltered (gdb_stdlog
,
4070 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
4071 argreg
, paddr_nz (struct_addr
));
4072 write_register (argreg
++, struct_addr
);
4073 stack_offset
+= mips_stack_argsize (gdbarch
);
4076 /* Now load as many as possible of the first arguments into
4077 registers, and push the rest onto the stack. Loop thru args
4078 from first to last. */
4079 for (argnum
= 0; argnum
< nargs
; argnum
++)
4082 struct value
*arg
= args
[argnum
];
4083 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4084 int len
= TYPE_LENGTH (arg_type
);
4085 enum type_code typecode
= TYPE_CODE (arg_type
);
4088 fprintf_unfiltered (gdb_stdlog
,
4089 "mips_o32_push_dummy_call: %d len=%d type=%d",
4090 argnum
+ 1, len
, (int) typecode
);
4092 val
= (char *) VALUE_CONTENTS (arg
);
4094 /* 32-bit ABIs always start floating point arguments in an
4095 even-numbered floating point register. Round the FP register
4096 up before the check to see if there are any FP registers
4097 left. O32/O64 targets also pass the FP in the integer
4098 registers so also round up normal registers. */
4099 if (mips_abi_regsize (gdbarch
) < 8
4100 && fp_register_arg_p (typecode
, arg_type
))
4102 if ((float_argreg
& 1))
4106 /* Floating point arguments passed in registers have to be
4107 treated specially. On 32-bit architectures, doubles
4108 are passed in register pairs; the even register gets
4109 the low word, and the odd register gets the high word.
4110 On O32/O64, the first two floating point arguments are
4111 also copied to general registers, because MIPS16 functions
4112 don't use float registers for arguments. This duplication of
4113 arguments in general registers can't hurt non-MIPS16 functions
4114 because those registers are normally skipped. */
4116 if (fp_register_arg_p (typecode
, arg_type
)
4117 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4119 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4121 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4122 unsigned long regval
;
4124 /* Write the low word of the double to the even register(s). */
4125 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4127 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4128 float_argreg
, phex (regval
, 4));
4129 write_register (float_argreg
++, regval
);
4131 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4132 argreg
, phex (regval
, 4));
4133 write_register (argreg
++, regval
);
4135 /* Write the high word of the double to the odd register(s). */
4136 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4138 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4139 float_argreg
, phex (regval
, 4));
4140 write_register (float_argreg
++, regval
);
4143 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4144 argreg
, phex (regval
, 4));
4145 write_register (argreg
++, regval
);
4149 /* This is a floating point value that fits entirely
4150 in a single register. */
4151 /* On 32 bit ABI's the float_argreg is further adjusted
4152 above to ensure that it is even register aligned. */
4153 LONGEST regval
= extract_unsigned_integer (val
, len
);
4155 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4156 float_argreg
, phex (regval
, len
));
4157 write_register (float_argreg
++, regval
);
4158 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4159 registers for each argument. The below is (my
4160 guess) to ensure that the corresponding integer
4161 register has reserved the same space. */
4163 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4164 argreg
, phex (regval
, len
));
4165 write_register (argreg
, regval
);
4166 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4168 /* Reserve space for the FP register. */
4169 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4173 /* Copy the argument to general registers or the stack in
4174 register-sized pieces. Large arguments are split between
4175 registers and stack. */
4176 /* Note: structs whose size is not a multiple of
4177 mips_abi_regsize() are treated specially: Irix cc passes
4178 them in registers where gcc sometimes puts them on the
4179 stack. For maximum compatibility, we will put them in
4181 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4182 && (len
% mips_abi_regsize (gdbarch
) != 0));
4183 /* Structures should be aligned to eight bytes (even arg registers)
4184 on MIPS_ABI_O32, if their first member has double precision. */
4185 if (mips_abi_regsize (gdbarch
) < 8
4186 && mips_type_needs_double_align (arg_type
))
4191 /* Note: Floating-point values that didn't fit into an FP
4192 register are only written to memory. */
4195 /* Remember if the argument was written to the stack. */
4196 int stack_used_p
= 0;
4197 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4198 ? len
: mips_abi_regsize (gdbarch
));
4201 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4204 /* Write this portion of the argument to the stack. */
4205 if (argreg
> MIPS_LAST_ARG_REGNUM
4207 || fp_register_arg_p (typecode
, arg_type
))
4209 /* Should shorter than int integer values be
4210 promoted to int before being stored? */
4211 int longword_offset
= 0;
4214 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4216 if (mips_stack_argsize (gdbarch
) == 8
4217 && (typecode
== TYPE_CODE_INT
4218 || typecode
== TYPE_CODE_PTR
4219 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4220 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4225 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4226 paddr_nz (stack_offset
));
4227 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4228 paddr_nz (longword_offset
));
4231 addr
= sp
+ stack_offset
+ longword_offset
;
4236 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4238 for (i
= 0; i
< partial_len
; i
++)
4240 fprintf_unfiltered (gdb_stdlog
, "%02x",
4244 write_memory (addr
, val
, partial_len
);
4247 /* Note!!! This is NOT an else clause. Odd sized
4248 structs may go thru BOTH paths. Floating point
4249 arguments will not. */
4250 /* Write this portion of the argument to a general
4251 purpose register. */
4252 if (argreg
<= MIPS_LAST_ARG_REGNUM
4253 && !fp_register_arg_p (typecode
, arg_type
))
4255 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4256 /* Value may need to be sign extended, because
4257 mips_isa_regsize() != mips_abi_regsize(). */
4259 /* A non-floating-point argument being passed in a
4260 general register. If a struct or union, and if
4261 the remaining length is smaller than the register
4262 size, we have to adjust the register value on
4265 It does not seem to be necessary to do the
4266 same for integral types.
4268 Also don't do this adjustment on O64 binaries.
4270 cagney/2001-07-23: gdb/179: Also, GCC, when
4271 outputting LE O32 with sizeof (struct) <
4272 mips_abi_regsize(), generates a left shift as
4273 part of storing the argument in a register a
4274 register (the left shift isn't generated when
4275 sizeof (struct) >= mips_abi_regsize()). Since
4276 it is quite possible that this is GCC
4277 contradicting the LE/O32 ABI, GDB has not been
4278 adjusted to accommodate this. Either someone
4279 needs to demonstrate that the LE/O32 ABI
4280 specifies such a left shift OR this new ABI gets
4281 identified as such and GDB gets tweaked
4284 if (mips_abi_regsize (gdbarch
) < 8
4285 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4286 && partial_len
< mips_abi_regsize (gdbarch
)
4287 && (typecode
== TYPE_CODE_STRUCT
||
4288 typecode
== TYPE_CODE_UNION
))
4289 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4293 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4296 mips_abi_regsize (gdbarch
)));
4297 write_register (argreg
, regval
);
4300 /* Prevent subsequent floating point arguments from
4301 being passed in floating point registers. */
4302 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4308 /* Compute the the offset into the stack at which we
4309 will copy the next parameter.
4311 In older ABIs, the caller reserved space for
4312 registers that contained arguments. This was loosely
4313 refered to as their "home". Consequently, space is
4314 always allocated. */
4316 stack_offset
+= align_up (partial_len
,
4317 mips_stack_argsize (gdbarch
));
4321 fprintf_unfiltered (gdb_stdlog
, "\n");
4324 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4326 /* Return adjusted stack pointer. */
4330 static enum return_value_convention
4331 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4332 struct regcache
*regcache
,
4333 void *readbuf
, const void *writebuf
)
4335 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4337 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4338 || TYPE_CODE (type
) == TYPE_CODE_UNION
4339 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4340 return RETURN_VALUE_STRUCT_CONVENTION
;
4341 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4342 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4344 /* A single-precision floating-point value. It fits in the
4345 least significant part of FP0. */
4347 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4348 mips_xfer_register (regcache
,
4349 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4351 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4352 return RETURN_VALUE_REGISTER_CONVENTION
;
4354 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4355 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4357 /* A double-precision floating-point value. The most
4358 significant part goes in FP1, and the least significant in
4361 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4362 switch (TARGET_BYTE_ORDER
)
4364 case BFD_ENDIAN_LITTLE
:
4365 mips_xfer_register (regcache
,
4366 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4367 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4368 mips_xfer_register (regcache
,
4369 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4370 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4372 case BFD_ENDIAN_BIG
:
4373 mips_xfer_register (regcache
,
4374 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4375 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4376 mips_xfer_register (regcache
,
4377 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4378 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4381 internal_error (__FILE__
, __LINE__
, "bad switch");
4383 return RETURN_VALUE_REGISTER_CONVENTION
;
4386 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4387 && TYPE_NFIELDS (type
) <= 2
4388 && TYPE_NFIELDS (type
) >= 1
4389 && ((TYPE_NFIELDS (type
) == 1
4390 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4392 || (TYPE_NFIELDS (type
) == 2
4393 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4395 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4397 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4399 /* A struct that contains one or two floats. Each value is part
4400 in the least significant part of their floating point
4402 bfd_byte reg
[MAX_REGISTER_SIZE
];
4405 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4406 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4408 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4411 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4413 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4414 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4415 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4417 return RETURN_VALUE_REGISTER_CONVENTION
;
4421 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4422 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4424 /* A structure or union. Extract the left justified value,
4425 regardless of the byte order. I.e. DO NOT USE
4429 for (offset
= 0, regnum
= V0_REGNUM
;
4430 offset
< TYPE_LENGTH (type
);
4431 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4433 int xfer
= register_size (current_gdbarch
, regnum
);
4434 if (offset
+ xfer
> TYPE_LENGTH (type
))
4435 xfer
= TYPE_LENGTH (type
) - offset
;
4437 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4438 offset
, xfer
, regnum
);
4439 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4440 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4442 return RETURN_VALUE_REGISTER_CONVENTION
;
4447 /* A scalar extract each part but least-significant-byte
4448 justified. o32 thinks registers are 4 byte, regardless of
4449 the ISA. mips_stack_argsize controls this. */
4452 for (offset
= 0, regnum
= V0_REGNUM
;
4453 offset
< TYPE_LENGTH (type
);
4454 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4456 int xfer
= mips_stack_argsize (gdbarch
);
4457 if (offset
+ xfer
> TYPE_LENGTH (type
))
4458 xfer
= TYPE_LENGTH (type
) - offset
;
4460 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4461 offset
, xfer
, regnum
);
4462 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4463 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4465 return RETURN_VALUE_REGISTER_CONVENTION
;
4469 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4473 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4474 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4476 struct value
**args
, CORE_ADDR sp
,
4477 int struct_return
, CORE_ADDR struct_addr
)
4483 int stack_offset
= 0;
4484 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4485 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4487 /* For shared libraries, "t9" needs to point at the function
4489 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4491 /* Set the return address register to point to the entry point of
4492 the program, where a breakpoint lies in wait. */
4493 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4495 /* First ensure that the stack and structure return address (if any)
4496 are properly aligned. The stack has to be at least 64-bit
4497 aligned even on 32-bit machines, because doubles must be 64-bit
4498 aligned. For n32 and n64, stack frames need to be 128-bit
4499 aligned, so we round to this widest known alignment. */
4501 sp
= align_down (sp
, 16);
4502 struct_addr
= align_down (struct_addr
, 16);
4504 /* Now make space on the stack for the args. */
4505 for (argnum
= 0; argnum
< nargs
; argnum
++)
4506 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4507 mips_stack_argsize (gdbarch
));
4508 sp
-= align_up (len
, 16);
4511 fprintf_unfiltered (gdb_stdlog
,
4512 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4513 paddr_nz (sp
), (long) align_up (len
, 16));
4515 /* Initialize the integer and float register pointers. */
4517 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4519 /* The struct_return pointer occupies the first parameter-passing reg. */
4523 fprintf_unfiltered (gdb_stdlog
,
4524 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4525 argreg
, paddr_nz (struct_addr
));
4526 write_register (argreg
++, struct_addr
);
4527 stack_offset
+= mips_stack_argsize (gdbarch
);
4530 /* Now load as many as possible of the first arguments into
4531 registers, and push the rest onto the stack. Loop thru args
4532 from first to last. */
4533 for (argnum
= 0; argnum
< nargs
; argnum
++)
4536 struct value
*arg
= args
[argnum
];
4537 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4538 int len
= TYPE_LENGTH (arg_type
);
4539 enum type_code typecode
= TYPE_CODE (arg_type
);
4542 fprintf_unfiltered (gdb_stdlog
,
4543 "mips_o64_push_dummy_call: %d len=%d type=%d",
4544 argnum
+ 1, len
, (int) typecode
);
4546 val
= (char *) VALUE_CONTENTS (arg
);
4548 /* 32-bit ABIs always start floating point arguments in an
4549 even-numbered floating point register. Round the FP register
4550 up before the check to see if there are any FP registers
4551 left. O32/O64 targets also pass the FP in the integer
4552 registers so also round up normal registers. */
4553 if (mips_abi_regsize (gdbarch
) < 8
4554 && fp_register_arg_p (typecode
, arg_type
))
4556 if ((float_argreg
& 1))
4560 /* Floating point arguments passed in registers have to be
4561 treated specially. On 32-bit architectures, doubles
4562 are passed in register pairs; the even register gets
4563 the low word, and the odd register gets the high word.
4564 On O32/O64, the first two floating point arguments are
4565 also copied to general registers, because MIPS16 functions
4566 don't use float registers for arguments. This duplication of
4567 arguments in general registers can't hurt non-MIPS16 functions
4568 because those registers are normally skipped. */
4570 if (fp_register_arg_p (typecode
, arg_type
)
4571 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4573 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4575 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4576 unsigned long regval
;
4578 /* Write the low word of the double to the even register(s). */
4579 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4581 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4582 float_argreg
, phex (regval
, 4));
4583 write_register (float_argreg
++, regval
);
4585 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4586 argreg
, phex (regval
, 4));
4587 write_register (argreg
++, regval
);
4589 /* Write the high word of the double to the odd register(s). */
4590 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4592 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4593 float_argreg
, phex (regval
, 4));
4594 write_register (float_argreg
++, regval
);
4597 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4598 argreg
, phex (regval
, 4));
4599 write_register (argreg
++, regval
);
4603 /* This is a floating point value that fits entirely
4604 in a single register. */
4605 /* On 32 bit ABI's the float_argreg is further adjusted
4606 above to ensure that it is even register aligned. */
4607 LONGEST regval
= extract_unsigned_integer (val
, len
);
4609 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4610 float_argreg
, phex (regval
, len
));
4611 write_register (float_argreg
++, regval
);
4612 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4613 registers for each argument. The below is (my
4614 guess) to ensure that the corresponding integer
4615 register has reserved the same space. */
4617 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4618 argreg
, phex (regval
, len
));
4619 write_register (argreg
, regval
);
4620 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4622 /* Reserve space for the FP register. */
4623 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4627 /* Copy the argument to general registers or the stack in
4628 register-sized pieces. Large arguments are split between
4629 registers and stack. */
4630 /* Note: structs whose size is not a multiple of
4631 mips_abi_regsize() are treated specially: Irix cc passes
4632 them in registers where gcc sometimes puts them on the
4633 stack. For maximum compatibility, we will put them in
4635 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4636 && (len
% mips_abi_regsize (gdbarch
) != 0));
4637 /* Structures should be aligned to eight bytes (even arg registers)
4638 on MIPS_ABI_O32, if their first member has double precision. */
4639 if (mips_abi_regsize (gdbarch
) < 8
4640 && mips_type_needs_double_align (arg_type
))
4645 /* Note: Floating-point values that didn't fit into an FP
4646 register are only written to memory. */
4649 /* Remember if the argument was written to the stack. */
4650 int stack_used_p
= 0;
4651 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4652 ? len
: mips_abi_regsize (gdbarch
));
4655 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4658 /* Write this portion of the argument to the stack. */
4659 if (argreg
> MIPS_LAST_ARG_REGNUM
4661 || fp_register_arg_p (typecode
, arg_type
))
4663 /* Should shorter than int integer values be
4664 promoted to int before being stored? */
4665 int longword_offset
= 0;
4668 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4670 if (mips_stack_argsize (gdbarch
) == 8
4671 && (typecode
== TYPE_CODE_INT
4672 || typecode
== TYPE_CODE_PTR
4673 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4674 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4679 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4680 paddr_nz (stack_offset
));
4681 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4682 paddr_nz (longword_offset
));
4685 addr
= sp
+ stack_offset
+ longword_offset
;
4690 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4692 for (i
= 0; i
< partial_len
; i
++)
4694 fprintf_unfiltered (gdb_stdlog
, "%02x",
4698 write_memory (addr
, val
, partial_len
);
4701 /* Note!!! This is NOT an else clause. Odd sized
4702 structs may go thru BOTH paths. Floating point
4703 arguments will not. */
4704 /* Write this portion of the argument to a general
4705 purpose register. */
4706 if (argreg
<= MIPS_LAST_ARG_REGNUM
4707 && !fp_register_arg_p (typecode
, arg_type
))
4709 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4710 /* Value may need to be sign extended, because
4711 mips_isa_regsize() != mips_abi_regsize(). */
4713 /* A non-floating-point argument being passed in a
4714 general register. If a struct or union, and if
4715 the remaining length is smaller than the register
4716 size, we have to adjust the register value on
4719 It does not seem to be necessary to do the
4720 same for integral types.
4722 Also don't do this adjustment on O64 binaries.
4724 cagney/2001-07-23: gdb/179: Also, GCC, when
4725 outputting LE O32 with sizeof (struct) <
4726 mips_abi_regsize(), generates a left shift as
4727 part of storing the argument in a register a
4728 register (the left shift isn't generated when
4729 sizeof (struct) >= mips_abi_regsize()). Since
4730 it is quite possible that this is GCC
4731 contradicting the LE/O32 ABI, GDB has not been
4732 adjusted to accommodate this. Either someone
4733 needs to demonstrate that the LE/O32 ABI
4734 specifies such a left shift OR this new ABI gets
4735 identified as such and GDB gets tweaked
4738 if (mips_abi_regsize (gdbarch
) < 8
4739 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4740 && partial_len
< mips_abi_regsize (gdbarch
)
4741 && (typecode
== TYPE_CODE_STRUCT
||
4742 typecode
== TYPE_CODE_UNION
))
4743 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4747 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4750 mips_abi_regsize (gdbarch
)));
4751 write_register (argreg
, regval
);
4754 /* Prevent subsequent floating point arguments from
4755 being passed in floating point registers. */
4756 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4762 /* Compute the the offset into the stack at which we
4763 will copy the next parameter.
4765 In older ABIs, the caller reserved space for
4766 registers that contained arguments. This was loosely
4767 refered to as their "home". Consequently, space is
4768 always allocated. */
4770 stack_offset
+= align_up (partial_len
,
4771 mips_stack_argsize (gdbarch
));
4775 fprintf_unfiltered (gdb_stdlog
, "\n");
4778 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4780 /* Return adjusted stack pointer. */
4785 mips_o64_extract_return_value (struct type
*valtype
,
4786 char regbuf
[], char *valbuf
)
4788 struct return_value_word lo
;
4789 struct return_value_word hi
;
4790 return_value_location (valtype
, &hi
, &lo
);
4792 memcpy (valbuf
+ lo
.buf_offset
,
4793 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4794 lo
.reg_offset
, lo
.len
);
4797 memcpy (valbuf
+ hi
.buf_offset
,
4798 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4799 hi
.reg_offset
, hi
.len
);
4803 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4805 char raw_buffer
[MAX_REGISTER_SIZE
];
4806 struct return_value_word lo
;
4807 struct return_value_word hi
;
4808 return_value_location (valtype
, &hi
, &lo
);
4810 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4811 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4812 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4813 raw_buffer
, register_size (current_gdbarch
,
4818 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4819 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4820 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4822 register_size (current_gdbarch
,
4827 /* Floating point register management.
4829 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4830 64bit operations, these early MIPS cpus treat fp register pairs
4831 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4832 registers and offer a compatibility mode that emulates the MIPS2 fp
4833 model. When operating in MIPS2 fp compat mode, later cpu's split
4834 double precision floats into two 32-bit chunks and store them in
4835 consecutive fp regs. To display 64-bit floats stored in this
4836 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4837 Throw in user-configurable endianness and you have a real mess.
4839 The way this works is:
4840 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4841 double-precision value will be split across two logical registers.
4842 The lower-numbered logical register will hold the low-order bits,
4843 regardless of the processor's endianness.
4844 - If we are on a 64-bit processor, and we are looking for a
4845 single-precision value, it will be in the low ordered bits
4846 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4847 save slot in memory.
4848 - If we are in 64-bit mode, everything is straightforward.
4850 Note that this code only deals with "live" registers at the top of the
4851 stack. We will attempt to deal with saved registers later, when
4852 the raw/cooked register interface is in place. (We need a general
4853 interface that can deal with dynamic saved register sizes -- fp
4854 regs could be 32 bits wide in one frame and 64 on the frame above
4857 static struct type
*
4858 mips_float_register_type (void)
4860 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4861 return builtin_type_ieee_single_big
;
4863 return builtin_type_ieee_single_little
;
4866 static struct type
*
4867 mips_double_register_type (void)
4869 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4870 return builtin_type_ieee_double_big
;
4872 return builtin_type_ieee_double_little
;
4875 /* Copy a 32-bit single-precision value from the current frame
4876 into rare_buffer. */
4879 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4882 int raw_size
= register_size (current_gdbarch
, regno
);
4883 char *raw_buffer
= alloca (raw_size
);
4885 if (!frame_register_read (frame
, regno
, raw_buffer
))
4886 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4889 /* We have a 64-bit value for this register. Find the low-order
4893 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4898 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4902 memcpy (rare_buffer
, raw_buffer
, 4);
4906 /* Copy a 64-bit double-precision value from the current frame into
4907 rare_buffer. This may include getting half of it from the next
4911 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4914 int raw_size
= register_size (current_gdbarch
, regno
);
4916 if (raw_size
== 8 && !mips2_fp_compat ())
4918 /* We have a 64-bit value for this register, and we should use
4920 if (!frame_register_read (frame
, regno
, rare_buffer
))
4921 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4925 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4926 internal_error (__FILE__
, __LINE__
,
4927 "mips_read_fp_register_double: bad access to "
4928 "odd-numbered FP register");
4930 /* mips_read_fp_register_single will find the correct 32 bits from
4932 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4934 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4935 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4939 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4940 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4946 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4948 { /* do values for FP (float) regs */
4950 double doub
, flt1
; /* doubles extracted from raw hex data */
4954 (char *) alloca (2 *
4955 register_size (current_gdbarch
,
4956 mips_regnum (current_gdbarch
)->fp0
));
4958 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4959 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4962 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4964 /* 4-byte registers: Print hex and floating. Also print even
4965 numbered registers as doubles. */
4966 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4967 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4969 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4972 fprintf_filtered (file
, " flt: ");
4974 fprintf_filtered (file
, " <invalid float> ");
4976 fprintf_filtered (file
, "%-17.9g", flt1
);
4978 if (regnum
% 2 == 0)
4980 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4981 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4984 fprintf_filtered (file
, " dbl: ");
4986 fprintf_filtered (file
, "<invalid double>");
4988 fprintf_filtered (file
, "%-24.17g", doub
);
4993 /* Eight byte registers: print each one as hex, float and double. */
4994 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4995 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4997 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4998 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
5001 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
5004 fprintf_filtered (file
, " flt: ");
5006 fprintf_filtered (file
, "<invalid float>");
5008 fprintf_filtered (file
, "%-17.9g", flt1
);
5010 fprintf_filtered (file
, " dbl: ");
5012 fprintf_filtered (file
, "<invalid double>");
5014 fprintf_filtered (file
, "%-24.17g", doub
);
5019 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
5020 int regnum
, int all
)
5022 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5023 char raw_buffer
[MAX_REGISTER_SIZE
];
5026 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
5028 mips_print_fp_register (file
, frame
, regnum
);
5032 /* Get the data in raw format. */
5033 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5035 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
5039 fputs_filtered (REGISTER_NAME (regnum
), file
);
5041 /* The problem with printing numeric register names (r26, etc.) is that
5042 the user can't use them on input. Probably the best solution is to
5043 fix it so that either the numeric or the funky (a2, etc.) names
5044 are accepted on input. */
5045 if (regnum
< MIPS_NUMREGS
)
5046 fprintf_filtered (file
, "(r%d): ", regnum
);
5048 fprintf_filtered (file
, ": ");
5050 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5052 register_size (current_gdbarch
,
5053 regnum
) - register_size (current_gdbarch
, regnum
);
5057 print_scalar_formatted (raw_buffer
+ offset
,
5058 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
5062 /* Replacement for generic do_registers_info.
5063 Print regs in pretty columns. */
5066 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5069 fprintf_filtered (file
, " ");
5070 mips_print_fp_register (file
, frame
, regnum
);
5071 fprintf_filtered (file
, "\n");
5076 /* Print a row's worth of GP (int) registers, with name labels above */
5079 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5082 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5083 /* do values for GP (int) regs */
5084 char raw_buffer
[MAX_REGISTER_SIZE
];
5085 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
5089 /* For GP registers, we print a separate row of names above the vals */
5090 fprintf_filtered (file
, " ");
5091 for (col
= 0, regnum
= start_regnum
;
5092 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5094 if (*REGISTER_NAME (regnum
) == '\0')
5095 continue; /* unused register */
5096 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5098 break; /* end the row: reached FP register */
5099 fprintf_filtered (file
,
5100 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
5101 REGISTER_NAME (regnum
));
5104 /* print the R0 to R31 names */
5105 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
5106 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
5108 fprintf_filtered (file
, "\n ");
5110 /* now print the values in hex, 4 or 8 to the row */
5111 for (col
= 0, regnum
= start_regnum
;
5112 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5114 if (*REGISTER_NAME (regnum
) == '\0')
5115 continue; /* unused register */
5116 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5118 break; /* end row: reached FP register */
5119 /* OK: get the data in raw format. */
5120 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5121 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
5122 /* pad small registers */
5124 byte
< (mips_abi_regsize (current_gdbarch
)
5125 - register_size (current_gdbarch
, regnum
)); byte
++)
5126 printf_filtered (" ");
5127 /* Now print the register value in hex, endian order. */
5128 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5130 register_size (current_gdbarch
,
5131 regnum
) - register_size (current_gdbarch
, regnum
);
5132 byte
< register_size (current_gdbarch
, regnum
); byte
++)
5133 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5135 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
5137 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5138 fprintf_filtered (file
, " ");
5141 if (col
> 0) /* ie. if we actually printed anything... */
5142 fprintf_filtered (file
, "\n");
5147 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
5150 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5151 struct frame_info
*frame
, int regnum
, int all
)
5153 if (regnum
!= -1) /* do one specified register */
5155 gdb_assert (regnum
>= NUM_REGS
);
5156 if (*(REGISTER_NAME (regnum
)) == '\0')
5157 error ("Not a valid register for the current processor type");
5159 mips_print_register (file
, frame
, regnum
, 0);
5160 fprintf_filtered (file
, "\n");
5163 /* do all (or most) registers */
5166 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
5168 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5171 if (all
) /* true for "INFO ALL-REGISTERS" command */
5172 regnum
= print_fp_register_row (file
, frame
, regnum
);
5174 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5177 regnum
= print_gp_register_row (file
, frame
, regnum
);
5182 /* Is this a branch with a delay slot? */
5184 static int is_delayed (unsigned long);
5187 is_delayed (unsigned long insn
)
5190 for (i
= 0; i
< NUMOPCODES
; ++i
)
5191 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5192 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5194 return (i
< NUMOPCODES
5195 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5196 | INSN_COND_BRANCH_DELAY
5197 | INSN_COND_BRANCH_LIKELY
)));
5201 mips_step_skips_delay (CORE_ADDR pc
)
5203 char buf
[MIPS_INSTLEN
];
5205 /* There is no branch delay slot on MIPS16. */
5206 if (pc_is_mips16 (pc
))
5209 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5210 /* If error reading memory, guess that it is not a delayed branch. */
5212 return is_delayed ((unsigned long)
5213 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5216 /* Skip the PC past function prologue instructions (32-bit version).
5217 This is a helper function for mips_skip_prologue. */
5220 mips32_skip_prologue (CORE_ADDR pc
)
5224 int seen_sp_adjust
= 0;
5225 int load_immediate_bytes
= 0;
5227 /* Find an upper bound on the prologue. */
5228 end_pc
= skip_prologue_using_sal (pc
);
5230 end_pc
= pc
+ 100; /* Magic. */
5232 /* Skip the typical prologue instructions. These are the stack adjustment
5233 instruction and the instructions that save registers on the stack
5234 or in the gcc frame. */
5235 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5237 unsigned long high_word
;
5239 inst
= mips_fetch_instruction (pc
);
5240 high_word
= (inst
>> 16) & 0xffff;
5242 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5243 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5245 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5246 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5248 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5249 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5250 && (inst
& 0x001F0000)) /* reg != $zero */
5253 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5255 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5257 continue; /* reg != $zero */
5259 /* move $s8,$sp. With different versions of gas this will be either
5260 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5261 Accept any one of these. */
5262 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5265 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5267 else if (high_word
== 0x3c1c) /* lui $gp,n */
5269 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5271 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5272 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5274 /* The following instructions load $at or $t0 with an immediate
5275 value in preparation for a stack adjustment via
5276 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5277 a local variable, so we accept them only before a stack adjustment
5278 instruction was seen. */
5279 else if (!seen_sp_adjust
)
5281 if (high_word
== 0x3c01 || /* lui $at,n */
5282 high_word
== 0x3c08) /* lui $t0,n */
5284 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5287 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5288 high_word
== 0x3508 || /* ori $t0,$t0,n */
5289 high_word
== 0x3401 || /* ori $at,$zero,n */
5290 high_word
== 0x3408) /* ori $t0,$zero,n */
5292 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5302 /* In a frameless function, we might have incorrectly
5303 skipped some load immediate instructions. Undo the skipping
5304 if the load immediate was not followed by a stack adjustment. */
5305 if (load_immediate_bytes
&& !seen_sp_adjust
)
5306 pc
-= load_immediate_bytes
;
5310 /* Skip the PC past function prologue instructions (16-bit version).
5311 This is a helper function for mips_skip_prologue. */
5314 mips16_skip_prologue (CORE_ADDR pc
)
5317 int extend_bytes
= 0;
5318 int prev_extend_bytes
;
5320 /* Table of instructions likely to be found in a function prologue. */
5323 unsigned short inst
;
5324 unsigned short mask
;
5330 , /* addiu $sp,offset */
5333 , /* daddiu $sp,offset */
5336 , /* sw reg,n($sp) */
5339 , /* sd reg,n($sp) */
5342 , /* sw $ra,n($sp) */
5345 , /* sd $ra,n($sp) */
5351 , /* sw $a0-$a3,n($s1) */
5354 , /* move reg,$a0-$a3 */
5357 , /* entry pseudo-op */
5360 , /* addiu $s1,$sp,n */
5362 0, 0} /* end of table marker */
5365 /* Find an upper bound on the prologue. */
5366 end_pc
= skip_prologue_using_sal (pc
);
5368 end_pc
= pc
+ 100; /* Magic. */
5370 /* Skip the typical prologue instructions. These are the stack adjustment
5371 instruction and the instructions that save registers on the stack
5372 or in the gcc frame. */
5373 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5375 unsigned short inst
;
5378 inst
= mips_fetch_instruction (pc
);
5380 /* Normally we ignore an extend instruction. However, if it is
5381 not followed by a valid prologue instruction, we must adjust
5382 the pc back over the extend so that it won't be considered
5383 part of the prologue. */
5384 if ((inst
& 0xf800) == 0xf000) /* extend */
5386 extend_bytes
= MIPS16_INSTLEN
;
5389 prev_extend_bytes
= extend_bytes
;
5392 /* Check for other valid prologue instructions besides extend. */
5393 for (i
= 0; table
[i
].mask
!= 0; i
++)
5394 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5396 if (table
[i
].mask
!= 0) /* it was in table? */
5397 continue; /* ignore it */
5401 /* Return the current pc, adjusted backwards by 2 if
5402 the previous instruction was an extend. */
5403 return pc
- prev_extend_bytes
;
5409 /* To skip prologues, I use this predicate. Returns either PC itself
5410 if the code at PC does not look like a function prologue; otherwise
5411 returns an address that (if we're lucky) follows the prologue. If
5412 LENIENT, then we must skip everything which is involved in setting
5413 up the frame (it's OK to skip more, just so long as we don't skip
5414 anything which might clobber the registers which are being saved.
5415 We must skip more in the case where part of the prologue is in the
5416 delay slot of a non-prologue instruction). */
5419 mips_skip_prologue (CORE_ADDR pc
)
5421 /* See if we can determine the end of the prologue via the symbol table.
5422 If so, then return either PC, or the PC after the prologue, whichever
5425 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
5427 if (post_prologue_pc
!= 0)
5428 return max (pc
, post_prologue_pc
);
5430 /* Can't determine prologue from the symbol table, need to examine
5433 if (pc_is_mips16 (pc
))
5434 return mips16_skip_prologue (pc
);
5436 return mips32_skip_prologue (pc
);
5439 /* Root of all "set mips "/"show mips " commands. This will eventually be
5440 used for all MIPS-specific commands. */
5443 show_mips_command (char *args
, int from_tty
)
5445 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5449 set_mips_command (char *args
, int from_tty
)
5452 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5453 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5456 /* Commands to show/set the MIPS FPU type. */
5459 show_mipsfpu_command (char *args
, int from_tty
)
5462 switch (MIPS_FPU_TYPE
)
5464 case MIPS_FPU_SINGLE
:
5465 fpu
= "single-precision";
5467 case MIPS_FPU_DOUBLE
:
5468 fpu
= "double-precision";
5471 fpu
= "absent (none)";
5474 internal_error (__FILE__
, __LINE__
, "bad switch");
5476 if (mips_fpu_type_auto
)
5478 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5482 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5487 set_mipsfpu_command (char *args
, int from_tty
)
5490 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5491 show_mipsfpu_command (args
, from_tty
);
5495 set_mipsfpu_single_command (char *args
, int from_tty
)
5497 struct gdbarch_info info
;
5498 gdbarch_info_init (&info
);
5499 mips_fpu_type
= MIPS_FPU_SINGLE
;
5500 mips_fpu_type_auto
= 0;
5501 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5502 instead of relying on globals. Doing that would let generic code
5503 handle the search for this specific architecture. */
5504 if (!gdbarch_update_p (info
))
5505 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5509 set_mipsfpu_double_command (char *args
, int from_tty
)
5511 struct gdbarch_info info
;
5512 gdbarch_info_init (&info
);
5513 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5514 mips_fpu_type_auto
= 0;
5515 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5516 instead of relying on globals. Doing that would let generic code
5517 handle the search for this specific architecture. */
5518 if (!gdbarch_update_p (info
))
5519 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5523 set_mipsfpu_none_command (char *args
, int from_tty
)
5525 struct gdbarch_info info
;
5526 gdbarch_info_init (&info
);
5527 mips_fpu_type
= MIPS_FPU_NONE
;
5528 mips_fpu_type_auto
= 0;
5529 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5530 instead of relying on globals. Doing that would let generic code
5531 handle the search for this specific architecture. */
5532 if (!gdbarch_update_p (info
))
5533 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5537 set_mipsfpu_auto_command (char *args
, int from_tty
)
5539 mips_fpu_type_auto
= 1;
5542 /* Attempt to identify the particular processor model by reading the
5543 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5544 the relevant processor still exists (it dates back to '94) and
5545 secondly this is not the way to do this. The processor type should
5546 be set by forcing an architecture change. */
5549 deprecated_mips_set_processor_regs_hack (void)
5551 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5554 prid
= read_register (PRID_REGNUM
);
5556 if ((prid
& ~0xf) == 0x700)
5557 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5560 /* Just like reinit_frame_cache, but with the right arguments to be
5561 callable as an sfunc. */
5564 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5565 struct cmd_list_element
*c
)
5567 reinit_frame_cache ();
5571 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5573 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5574 mips_extra_func_info_t proc_desc
;
5576 /* Search for the function containing this address. Set the low bit
5577 of the address when searching, in case we were given an even address
5578 that is the start of a 16-bit function. If we didn't do this,
5579 the search would fail because the symbol table says the function
5580 starts at an odd address, i.e. 1 byte past the given address. */
5581 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5582 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5584 /* Make an attempt to determine if this is a 16-bit function. If
5585 the procedure descriptor exists and the address therein is odd,
5586 it's definitely a 16-bit function. Otherwise, we have to just
5587 guess that if the address passed in is odd, it's 16-bits. */
5588 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5589 disassembler needs to be able to locally determine the ISA, and
5590 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5594 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5595 info
->mach
= bfd_mach_mips16
;
5599 if (pc_is_mips16 (memaddr
))
5600 info
->mach
= bfd_mach_mips16
;
5603 /* Round down the instruction address to the appropriate boundary. */
5604 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5606 /* Set the disassembler options. */
5607 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5609 /* Set up the disassembler info, so that we get the right
5610 register names from libopcodes. */
5611 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5612 info
->disassembler_options
= "gpr-names=n32";
5614 info
->disassembler_options
= "gpr-names=64";
5615 info
->flavour
= bfd_target_elf_flavour
;
5618 /* This string is not recognized explicitly by the disassembler,
5619 but it tells the disassembler to not try to guess the ABI from
5620 the bfd elf headers, such that, if the user overrides the ABI
5621 of a program linked as NewABI, the disassembly will follow the
5622 register naming conventions specified by the user. */
5623 info
->disassembler_options
= "gpr-names=32";
5625 /* Call the appropriate disassembler based on the target endian-ness. */
5626 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5627 return print_insn_big_mips (memaddr
, info
);
5629 return print_insn_little_mips (memaddr
, info
);
5632 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5633 counter value to determine whether a 16- or 32-bit breakpoint should be
5634 used. It returns a pointer to a string of bytes that encode a breakpoint
5635 instruction, stores the length of the string to *lenptr, and adjusts pc
5636 (if necessary) to point to the actual memory location where the
5637 breakpoint should be inserted. */
5639 static const unsigned char *
5640 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5642 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5644 if (pc_is_mips16 (*pcptr
))
5646 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5647 *pcptr
= unmake_mips16_addr (*pcptr
);
5648 *lenptr
= sizeof (mips16_big_breakpoint
);
5649 return mips16_big_breakpoint
;
5653 /* The IDT board uses an unusual breakpoint value, and
5654 sometimes gets confused when it sees the usual MIPS
5655 breakpoint instruction. */
5656 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5657 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5658 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5660 *lenptr
= sizeof (big_breakpoint
);
5662 if (strcmp (target_shortname
, "mips") == 0)
5663 return idt_big_breakpoint
;
5664 else if (strcmp (target_shortname
, "ddb") == 0
5665 || strcmp (target_shortname
, "pmon") == 0
5666 || strcmp (target_shortname
, "lsi") == 0)
5667 return pmon_big_breakpoint
;
5669 return big_breakpoint
;
5674 if (pc_is_mips16 (*pcptr
))
5676 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5677 *pcptr
= unmake_mips16_addr (*pcptr
);
5678 *lenptr
= sizeof (mips16_little_breakpoint
);
5679 return mips16_little_breakpoint
;
5683 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5684 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5685 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5687 *lenptr
= sizeof (little_breakpoint
);
5689 if (strcmp (target_shortname
, "mips") == 0)
5690 return idt_little_breakpoint
;
5691 else if (strcmp (target_shortname
, "ddb") == 0
5692 || strcmp (target_shortname
, "pmon") == 0
5693 || strcmp (target_shortname
, "lsi") == 0)
5694 return pmon_little_breakpoint
;
5696 return little_breakpoint
;
5701 /* If PC is in a mips16 call or return stub, return the address of the target
5702 PC, which is either the callee or the caller. There are several
5703 cases which must be handled:
5705 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5706 target PC is in $31 ($ra).
5707 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5708 and the target PC is in $2.
5709 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5710 before the jal instruction, this is effectively a call stub
5711 and the the target PC is in $2. Otherwise this is effectively
5712 a return stub and the target PC is in $18.
5714 See the source code for the stubs in gcc/config/mips/mips16.S for
5717 This function implements the SKIP_TRAMPOLINE_CODE macro.
5721 mips_skip_stub (CORE_ADDR pc
)
5724 CORE_ADDR start_addr
;
5726 /* Find the starting address and name of the function containing the PC. */
5727 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5730 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5731 target PC is in $31 ($ra). */
5732 if (strcmp (name
, "__mips16_ret_sf") == 0
5733 || strcmp (name
, "__mips16_ret_df") == 0)
5734 return read_signed_register (RA_REGNUM
);
5736 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5738 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5739 and the target PC is in $2. */
5740 if (name
[19] >= '0' && name
[19] <= '9')
5741 return read_signed_register (2);
5743 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5744 before the jal instruction, this is effectively a call stub
5745 and the the target PC is in $2. Otherwise this is effectively
5746 a return stub and the target PC is in $18. */
5747 else if (name
[19] == 's' || name
[19] == 'd')
5749 if (pc
== start_addr
)
5751 /* Check if the target of the stub is a compiler-generated
5752 stub. Such a stub for a function bar might have a name
5753 like __fn_stub_bar, and might look like this:
5758 la $1,bar (becomes a lui/addiu pair)
5760 So scan down to the lui/addi and extract the target
5761 address from those two instructions. */
5763 CORE_ADDR target_pc
= read_signed_register (2);
5767 /* See if the name of the target function is __fn_stub_*. */
5768 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5771 if (strncmp (name
, "__fn_stub_", 10) != 0
5772 && strcmp (name
, "etext") != 0
5773 && strcmp (name
, "_etext") != 0)
5776 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5777 The limit on the search is arbitrarily set to 20
5778 instructions. FIXME. */
5779 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5781 inst
= mips_fetch_instruction (target_pc
);
5782 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5783 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5784 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5785 return pc
| (inst
& 0xffff); /* low word */
5788 /* Couldn't find the lui/addui pair, so return stub address. */
5792 /* This is the 'return' part of a call stub. The return
5793 address is in $r18. */
5794 return read_signed_register (18);
5797 return 0; /* not a stub */
5801 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5802 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5805 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5807 CORE_ADDR start_addr
;
5809 /* Find the starting address of the function containing the PC. If the
5810 caller didn't give us a name, look it up at the same time. */
5811 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5815 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5817 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5818 if (name
[19] >= '0' && name
[19] <= '9')
5820 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5821 before the jal instruction, this is effectively a call stub. */
5822 else if (name
[19] == 's' || name
[19] == 'd')
5823 return pc
== start_addr
;
5826 return 0; /* not a stub */
5830 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5831 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5834 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5836 CORE_ADDR start_addr
;
5838 /* Find the starting address of the function containing the PC. */
5839 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5842 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5843 if (strcmp (name
, "__mips16_ret_sf") == 0
5844 || strcmp (name
, "__mips16_ret_df") == 0)
5847 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5848 i.e. after the jal instruction, this is effectively a return stub. */
5849 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5850 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5853 return 0; /* not a stub */
5857 /* Return non-zero if the PC is in a library helper function that
5858 should be ignored. This implements the
5859 DEPRECATED_IGNORE_HELPER_CALL macro. */
5862 mips_ignore_helper (CORE_ADDR pc
)
5866 /* Find the starting address and name of the function containing the PC. */
5867 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5870 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5871 that we want to ignore. */
5872 return (strcmp (name
, "__mips16_ret_sf") == 0
5873 || strcmp (name
, "__mips16_ret_df") == 0);
5877 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5878 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5881 mips_stab_reg_to_regnum (int num
)
5884 if (num
>= 0 && num
< 32)
5886 else if (num
>= 38 && num
< 70)
5887 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5889 regnum
= mips_regnum (current_gdbarch
)->hi
;
5891 regnum
= mips_regnum (current_gdbarch
)->lo
;
5893 /* This will hopefully (eventually) provoke a warning. Should
5894 we be calling complaint() here? */
5895 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5896 return NUM_REGS
+ regnum
;
5900 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5901 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5904 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5907 if (num
>= 0 && num
< 32)
5909 else if (num
>= 32 && num
< 64)
5910 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5912 regnum
= mips_regnum (current_gdbarch
)->hi
;
5914 regnum
= mips_regnum (current_gdbarch
)->lo
;
5916 /* This will hopefully (eventually) provoke a warning. Should we
5917 be calling complaint() here? */
5918 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5919 return NUM_REGS
+ regnum
;
5923 mips_register_sim_regno (int regnum
)
5925 /* Only makes sense to supply raw registers. */
5926 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5927 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5928 decide if it is valid. Should instead define a standard sim/gdb
5929 register numbering scheme. */
5930 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5931 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5934 return LEGACY_SIM_REGNO_IGNORE
;
5938 /* Convert an integer into an address. By first converting the value
5939 into a pointer and then extracting it signed, the address is
5940 guarenteed to be correctly sign extended. */
5943 mips_integer_to_address (struct type
*type
, void *buf
)
5945 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5946 LONGEST val
= unpack_long (type
, buf
);
5947 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5948 return extract_signed_integer (tmp
,
5949 TYPE_LENGTH (builtin_type_void_data_ptr
));
5953 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5955 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5956 const char *name
= bfd_get_section_name (abfd
, sect
);
5958 if (*abip
!= MIPS_ABI_UNKNOWN
)
5961 if (strncmp (name
, ".mdebug.", 8) != 0)
5964 if (strcmp (name
, ".mdebug.abi32") == 0)
5965 *abip
= MIPS_ABI_O32
;
5966 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5967 *abip
= MIPS_ABI_N32
;
5968 else if (strcmp (name
, ".mdebug.abi64") == 0)
5969 *abip
= MIPS_ABI_N64
;
5970 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5971 *abip
= MIPS_ABI_O64
;
5972 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5973 *abip
= MIPS_ABI_EABI32
;
5974 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5975 *abip
= MIPS_ABI_EABI64
;
5977 warning ("unsupported ABI %s.", name
+ 8);
5980 static enum mips_abi
5981 global_mips_abi (void)
5985 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5986 if (mips_abi_strings
[i
] == mips_abi_string
)
5987 return (enum mips_abi
) i
;
5989 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5992 static struct gdbarch
*
5993 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5995 struct gdbarch
*gdbarch
;
5996 struct gdbarch_tdep
*tdep
;
5998 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
6000 enum mips_fpu_type fpu_type
;
6002 /* First of all, extract the elf_flags, if available. */
6003 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6004 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6005 else if (arches
!= NULL
)
6006 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6010 fprintf_unfiltered (gdb_stdlog
,
6011 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6013 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6014 switch ((elf_flags
& EF_MIPS_ABI
))
6016 case E_MIPS_ABI_O32
:
6017 found_abi
= MIPS_ABI_O32
;
6019 case E_MIPS_ABI_O64
:
6020 found_abi
= MIPS_ABI_O64
;
6022 case E_MIPS_ABI_EABI32
:
6023 found_abi
= MIPS_ABI_EABI32
;
6025 case E_MIPS_ABI_EABI64
:
6026 found_abi
= MIPS_ABI_EABI64
;
6029 if ((elf_flags
& EF_MIPS_ABI2
))
6030 found_abi
= MIPS_ABI_N32
;
6032 found_abi
= MIPS_ABI_UNKNOWN
;
6036 /* GCC creates a pseudo-section whose name describes the ABI. */
6037 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6038 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6040 /* If we have no useful BFD information, use the ABI from the last
6041 MIPS architecture (if there is one). */
6042 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6043 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6045 /* Try the architecture for any hint of the correct ABI. */
6046 if (found_abi
== MIPS_ABI_UNKNOWN
6047 && info
.bfd_arch_info
!= NULL
6048 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6050 switch (info
.bfd_arch_info
->mach
)
6052 case bfd_mach_mips3900
:
6053 found_abi
= MIPS_ABI_EABI32
;
6055 case bfd_mach_mips4100
:
6056 case bfd_mach_mips5000
:
6057 found_abi
= MIPS_ABI_EABI64
;
6059 case bfd_mach_mips8000
:
6060 case bfd_mach_mips10000
:
6061 /* On Irix, ELF64 executables use the N64 ABI. The
6062 pseudo-sections which describe the ABI aren't present
6063 on IRIX. (Even for executables created by gcc.) */
6064 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6065 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6066 found_abi
= MIPS_ABI_N64
;
6068 found_abi
= MIPS_ABI_N32
;
6074 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6077 /* What has the user specified from the command line? */
6078 wanted_abi
= global_mips_abi ();
6080 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6083 /* Now that we have found what the ABI for this binary would be,
6084 check whether the user is overriding it. */
6085 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6086 mips_abi
= wanted_abi
;
6087 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6088 mips_abi
= found_abi
;
6090 mips_abi
= MIPS_ABI_O32
;
6092 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6095 /* Also used when doing an architecture lookup. */
6097 fprintf_unfiltered (gdb_stdlog
,
6098 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
6099 mips64_transfers_32bit_regs_p
);
6101 /* Determine the MIPS FPU type. */
6102 if (!mips_fpu_type_auto
)
6103 fpu_type
= mips_fpu_type
;
6104 else if (info
.bfd_arch_info
!= NULL
6105 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6106 switch (info
.bfd_arch_info
->mach
)
6108 case bfd_mach_mips3900
:
6109 case bfd_mach_mips4100
:
6110 case bfd_mach_mips4111
:
6111 case bfd_mach_mips4120
:
6112 fpu_type
= MIPS_FPU_NONE
;
6114 case bfd_mach_mips4650
:
6115 fpu_type
= MIPS_FPU_SINGLE
;
6118 fpu_type
= MIPS_FPU_DOUBLE
;
6121 else if (arches
!= NULL
)
6122 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6124 fpu_type
= MIPS_FPU_DOUBLE
;
6126 fprintf_unfiltered (gdb_stdlog
,
6127 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6129 /* try to find a pre-existing architecture */
6130 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6132 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6134 /* MIPS needs to be pedantic about which ABI the object is
6136 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6138 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6140 /* Need to be pedantic about which register virtual size is
6142 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6143 != mips64_transfers_32bit_regs_p
)
6145 /* Be pedantic about which FPU is selected. */
6146 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6148 return arches
->gdbarch
;
6151 /* Need a new architecture. Fill in a target specific vector. */
6152 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6153 gdbarch
= gdbarch_alloc (&info
, tdep
);
6154 tdep
->elf_flags
= elf_flags
;
6155 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6156 tdep
->found_abi
= found_abi
;
6157 tdep
->mips_abi
= mips_abi
;
6158 tdep
->mips_fpu_type
= fpu_type
;
6160 /* Initially set everything according to the default ABI/ISA. */
6161 set_gdbarch_short_bit (gdbarch
, 16);
6162 set_gdbarch_int_bit (gdbarch
, 32);
6163 set_gdbarch_float_bit (gdbarch
, 32);
6164 set_gdbarch_double_bit (gdbarch
, 64);
6165 set_gdbarch_long_double_bit (gdbarch
, 64);
6166 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6167 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6168 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6170 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6171 mips_elf_make_msymbol_special
);
6173 /* Fill in the OS dependant register numbers and names. */
6175 const char **reg_names
;
6176 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6177 struct mips_regnum
);
6178 if (info
.osabi
== GDB_OSABI_IRIX
)
6183 regnum
->badvaddr
= 66;
6186 regnum
->fp_control_status
= 69;
6187 regnum
->fp_implementation_revision
= 70;
6189 reg_names
= mips_irix_reg_names
;
6193 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6194 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6195 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6196 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6197 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6198 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6199 regnum
->fp_control_status
= 70;
6200 regnum
->fp_implementation_revision
= 71;
6202 if (info
.bfd_arch_info
!= NULL
6203 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6204 reg_names
= mips_tx39_reg_names
;
6206 reg_names
= mips_generic_reg_names
;
6208 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6209 replaced by read_pc? */
6210 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6211 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6212 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6213 set_gdbarch_num_regs (gdbarch
, num_regs
);
6214 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6215 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6216 tdep
->mips_processor_reg_names
= reg_names
;
6217 tdep
->regnum
= regnum
;
6223 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6224 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6225 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6226 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6227 tdep
->default_mask_address_p
= 0;
6228 set_gdbarch_long_bit (gdbarch
, 32);
6229 set_gdbarch_ptr_bit (gdbarch
, 32);
6230 set_gdbarch_long_long_bit (gdbarch
, 64);
6233 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6234 set_gdbarch_deprecated_store_return_value (gdbarch
,
6235 mips_o64_store_return_value
);
6236 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6237 mips_o64_extract_return_value
);
6238 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6239 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6240 tdep
->default_mask_address_p
= 0;
6241 set_gdbarch_long_bit (gdbarch
, 32);
6242 set_gdbarch_ptr_bit (gdbarch
, 32);
6243 set_gdbarch_long_long_bit (gdbarch
, 64);
6244 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
6246 case MIPS_ABI_EABI32
:
6247 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6248 set_gdbarch_deprecated_store_return_value (gdbarch
,
6249 mips_eabi_store_return_value
);
6250 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6251 mips_eabi_extract_return_value
);
6252 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6253 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6254 tdep
->default_mask_address_p
= 0;
6255 set_gdbarch_long_bit (gdbarch
, 32);
6256 set_gdbarch_ptr_bit (gdbarch
, 32);
6257 set_gdbarch_long_long_bit (gdbarch
, 64);
6258 set_gdbarch_deprecated_reg_struct_has_addr
6259 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6260 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6262 case MIPS_ABI_EABI64
:
6263 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6264 set_gdbarch_deprecated_store_return_value (gdbarch
,
6265 mips_eabi_store_return_value
);
6266 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6267 mips_eabi_extract_return_value
);
6268 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6269 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6270 tdep
->default_mask_address_p
= 0;
6271 set_gdbarch_long_bit (gdbarch
, 64);
6272 set_gdbarch_ptr_bit (gdbarch
, 64);
6273 set_gdbarch_long_long_bit (gdbarch
, 64);
6274 set_gdbarch_deprecated_reg_struct_has_addr
6275 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6276 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6279 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6280 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6281 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6282 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6283 tdep
->default_mask_address_p
= 0;
6284 set_gdbarch_long_bit (gdbarch
, 32);
6285 set_gdbarch_ptr_bit (gdbarch
, 32);
6286 set_gdbarch_long_long_bit (gdbarch
, 64);
6287 set_gdbarch_long_double_bit (gdbarch
, 128);
6288 set_gdbarch_long_double_format (gdbarch
,
6289 &floatformat_n32n64_long_double_big
);
6292 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6293 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6294 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6295 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6296 tdep
->default_mask_address_p
= 0;
6297 set_gdbarch_long_bit (gdbarch
, 64);
6298 set_gdbarch_ptr_bit (gdbarch
, 64);
6299 set_gdbarch_long_long_bit (gdbarch
, 64);
6300 set_gdbarch_long_double_bit (gdbarch
, 128);
6301 set_gdbarch_long_double_format (gdbarch
,
6302 &floatformat_n32n64_long_double_big
);
6305 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6308 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6309 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6312 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6313 flag in object files because to do so would make it impossible to
6314 link with libraries compiled without "-gp32". This is
6315 unnecessarily restrictive.
6317 We could solve this problem by adding "-gp32" multilibs to gcc,
6318 but to set this flag before gcc is built with such multilibs will
6319 break too many systems.''
6321 But even more unhelpfully, the default linker output target for
6322 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6323 for 64-bit programs - you need to change the ABI to change this,
6324 and not all gcc targets support that currently. Therefore using
6325 this flag to detect 32-bit mode would do the wrong thing given
6326 the current gcc - it would make GDB treat these 64-bit programs
6327 as 32-bit programs by default. */
6329 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6330 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6331 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6333 /* Add/remove bits from an address. The MIPS needs be careful to
6334 ensure that all 32 bit addresses are sign extended to 64 bits. */
6335 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6337 /* Unwind the frame. */
6338 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6339 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6341 /* Map debug register numbers onto internal register numbers. */
6342 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6343 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6344 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6345 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6346 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6347 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6348 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6349 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6351 /* MIPS version of CALL_DUMMY */
6353 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6354 replaced by a command, and all targets will default to on stack
6355 (regardless of the stack's execute status). */
6356 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6357 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6359 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6360 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6361 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6363 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6364 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6366 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6368 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6369 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6370 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6372 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6374 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6376 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6378 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6379 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6380 need to all be folded into the target vector. Since they are
6381 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6382 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6384 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6386 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6388 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6389 to support MIPS16. This is a bad thing. Make sure not to do it
6390 if we have an OS ABI that actually supports shared libraries, since
6391 shared library support is more important. If we have an OS someday
6392 that supports both shared libraries and MIPS16, we'll have to find
6393 a better place for these. */
6394 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6396 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6397 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6400 /* Hook in OS ABI-specific overrides, if they have been registered. */
6401 gdbarch_init_osabi (info
, gdbarch
);
6403 /* Unwind the frame. */
6404 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6405 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6406 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6407 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6408 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6409 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6410 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6411 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6417 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6419 struct gdbarch_info info
;
6421 /* Force the architecture to update, and (if it's a MIPS architecture)
6422 mips_gdbarch_init will take care of the rest. */
6423 gdbarch_info_init (&info
);
6424 gdbarch_update_p (info
);
6427 /* Print out which MIPS ABI is in use. */
6430 show_mips_abi (char *ignore_args
, int from_tty
)
6432 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6434 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6437 enum mips_abi global_abi
= global_mips_abi ();
6438 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6439 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6441 if (global_abi
== MIPS_ABI_UNKNOWN
)
6443 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6445 else if (global_abi
== actual_abi
)
6447 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6451 /* Probably shouldn't happen... */
6453 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6454 actual_abi_str
, mips_abi_strings
[global_abi
]);
6460 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6462 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6466 int ef_mips_32bitmode
;
6467 /* determine the ISA */
6468 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6486 /* determine the size of a pointer */
6487 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6488 fprintf_unfiltered (file
,
6489 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6491 fprintf_unfiltered (file
,
6492 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6494 fprintf_unfiltered (file
,
6495 "mips_dump_tdep: ef_mips_arch = %d\n",
6497 fprintf_unfiltered (file
,
6498 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6499 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6500 fprintf_unfiltered (file
,
6501 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6502 mips_mask_address_p (tdep
),
6503 tdep
->default_mask_address_p
);
6505 fprintf_unfiltered (file
,
6506 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6507 MIPS_DEFAULT_FPU_TYPE
,
6508 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6509 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6510 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6512 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6513 fprintf_unfiltered (file
,
6514 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6516 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6517 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6518 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6520 fprintf_unfiltered (file
,
6521 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6522 mips_stack_argsize (current_gdbarch
));
6523 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6524 fprintf_unfiltered (file
,
6525 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6526 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6527 fprintf_unfiltered (file
,
6528 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6529 XSTRING (ATTACH_DETACH
));
6530 fprintf_unfiltered (file
,
6531 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6532 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6533 fprintf_unfiltered (file
,
6534 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6535 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6536 fprintf_unfiltered (file
,
6537 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6538 FIRST_EMBED_REGNUM
);
6539 fprintf_unfiltered (file
,
6540 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6541 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6542 fprintf_unfiltered (file
,
6543 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6544 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6545 fprintf_unfiltered (file
,
6546 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6547 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6548 fprintf_unfiltered (file
,
6549 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6551 #ifdef MACHINE_CPROC_FP_OFFSET
6552 fprintf_unfiltered (file
,
6553 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6554 MACHINE_CPROC_FP_OFFSET
);
6556 #ifdef MACHINE_CPROC_PC_OFFSET
6557 fprintf_unfiltered (file
,
6558 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6559 MACHINE_CPROC_PC_OFFSET
);
6561 #ifdef MACHINE_CPROC_SP_OFFSET
6562 fprintf_unfiltered (file
,
6563 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6564 MACHINE_CPROC_SP_OFFSET
);
6566 fprintf_unfiltered (file
,
6567 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6569 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6570 fprintf_unfiltered (file
,
6571 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6572 fprintf_unfiltered (file
,
6573 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6574 fprintf_unfiltered (file
,
6575 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6576 MIPS_LAST_ARG_REGNUM
,
6577 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6578 fprintf_unfiltered (file
,
6579 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6580 fprintf_unfiltered (file
,
6581 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6582 mips_abi_regsize (current_gdbarch
));
6583 fprintf_unfiltered (file
,
6584 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6585 fprintf_unfiltered (file
,
6586 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6587 fprintf_unfiltered (file
,
6588 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6589 fprintf_unfiltered (file
,
6590 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6591 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6592 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6593 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6594 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6595 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6596 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6597 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6598 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6599 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6600 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6601 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6603 fprintf_unfiltered (file
,
6604 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6607 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6610 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6612 fprintf_unfiltered (file
,
6613 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6614 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6615 fprintf_unfiltered (file
,
6616 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6617 fprintf_unfiltered (file
,
6618 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6619 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6620 fprintf_unfiltered (file
,
6621 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6622 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6623 fprintf_unfiltered (file
,
6624 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6625 SOFTWARE_SINGLE_STEP_P ());
6626 fprintf_unfiltered (file
,
6627 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6628 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6629 #ifdef STACK_END_ADDR
6630 fprintf_unfiltered (file
,
6631 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6634 fprintf_unfiltered (file
,
6635 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6636 XSTRING (STEP_SKIPS_DELAY (PC
)));
6637 fprintf_unfiltered (file
,
6638 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6639 STEP_SKIPS_DELAY_P
);
6640 fprintf_unfiltered (file
,
6641 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6642 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6643 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6644 fprintf_unfiltered (file
,
6645 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6646 fprintf_unfiltered (file
,
6647 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6648 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6649 (TYPE
, CNT
, OTHERTYPE
)));
6650 fprintf_unfiltered (file
,
6651 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6652 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6654 fprintf_unfiltered (file
,
6655 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6656 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6659 fprintf_unfiltered (file
,
6660 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6662 #ifdef TRACE_FLAVOR_SIZE
6663 fprintf_unfiltered (file
,
6664 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6668 fprintf_unfiltered (file
,
6669 "mips_dump_tdep: TRACE_SET # %s\n",
6670 XSTRING (TRACE_SET (X
, STATE
)));
6672 #ifdef UNUSED_REGNUM
6673 fprintf_unfiltered (file
,
6674 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6676 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6677 fprintf_unfiltered (file
,
6678 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6679 (long) VM_MIN_ADDRESS
);
6680 fprintf_unfiltered (file
,
6681 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6682 fprintf_unfiltered (file
,
6683 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6686 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6689 _initialize_mips_tdep (void)
6691 static struct cmd_list_element
*mipsfpulist
= NULL
;
6692 struct cmd_list_element
*c
;
6694 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6695 if (MIPS_ABI_LAST
+ 1
6696 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6697 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6699 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6701 mips_pdr_data
= register_objfile_data ();
6703 /* Add root prefix command for all "set mips"/"show mips" commands */
6704 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6705 "Various MIPS specific commands.",
6706 &setmipscmdlist
, "set mips ", 0, &setlist
);
6708 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6709 "Various MIPS specific commands.",
6710 &showmipscmdlist
, "show mips ", 0, &showlist
);
6712 /* Allow the user to override the saved register size. */
6713 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6716 &mips_abi_regsize_string
, "\
6717 Set size of general purpose registers saved on the stack.\n\
6718 This option can be set to one of:\n\
6719 32 - Force GDB to treat saved GP registers as 32-bit\n\
6720 64 - Force GDB to treat saved GP registers as 64-bit\n\
6721 auto - Allow GDB to use the target's default setting or autodetect the\n\
6722 saved GP register size from information contained in the executable.\n\
6723 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6725 /* Allow the user to override the argument stack size. */
6726 deprecated_add_show_from_set
6727 (add_set_enum_cmd ("stack-arg-size",
6730 &mips_stack_argsize_string
, "\
6731 Set the amount of stack space reserved for each argument.\n\
6732 This option can be set to one of:\n\
6733 32 - Force GDB to allocate 32-bit chunks per argument\n\
6734 64 - Force GDB to allocate 64-bit chunks per argument\n\
6735 auto - Allow GDB to determine the correct setting from the current\n\
6736 target and executable (default)", &setmipscmdlist
),
6739 /* Allow the user to override the ABI. */
6740 c
= add_set_enum_cmd
6741 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6742 "Set the ABI used by this program.\n"
6743 "This option can be set to one of:\n"
6744 " auto - the default ABI associated with the current binary\n"
6746 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6747 set_cmd_sfunc (c
, mips_abi_update
);
6748 add_cmd ("abi", class_obscure
, show_mips_abi
,
6749 "Show ABI in use by MIPS target", &showmipscmdlist
);
6751 /* Let the user turn off floating point and set the fence post for
6752 heuristic_proc_start. */
6754 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6755 "Set use of MIPS floating-point coprocessor.",
6756 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6757 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6758 "Select single-precision MIPS floating-point coprocessor.",
6760 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6761 "Select double-precision MIPS floating-point coprocessor.",
6763 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6764 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6765 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6766 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6767 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6768 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6769 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6770 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6771 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6772 "Select MIPS floating-point coprocessor automatically.",
6774 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6775 "Show current use of MIPS floating-point coprocessor target.",
6778 /* We really would like to have both "0" and "unlimited" work, but
6779 command.c doesn't deal with that. So make it a var_zinteger
6780 because the user can always use "999999" or some such for unlimited. */
6781 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6782 (char *) &heuristic_fence_post
, "\
6783 Set the distance searched for the start of a function.\n\
6784 If you are debugging a stripped executable, GDB needs to search through the\n\
6785 program for the start of a function. This command sets the distance of the\n\
6786 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6787 /* We need to throw away the frame cache when we set this, since it
6788 might change our ability to get backtraces. */
6789 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6790 deprecated_add_show_from_set (c
, &showlist
);
6792 /* Allow the user to control whether the upper bits of 64-bit
6793 addresses should be zeroed. */
6794 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6795 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6796 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6797 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6798 allow GDB to determine the correct value.\n", "\
6799 Zerroing of upper 32 bits of 64-bit address is %s.",
6800 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6802 /* Allow the user to control the size of 32 bit registers within the
6803 raw remote packet. */
6804 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6805 &mips64_transfers_32bit_regs_p
, "\
6806 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6807 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6808 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6809 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6810 64 bits for others. Use \"off\" to disable compatibility mode", "\
6811 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6812 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6814 /* Debug this files internals. */
6815 deprecated_add_show_from_set
6816 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6817 &mips_debug
, "Set mips debugging.\n\
6818 When non-zero, mips specific debugging is enabled.", &setdebuglist
),