1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string
;
76 static const char *mips_abi_strings
[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc
;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto
[] = "auto";
98 static const char size_32
[] = "32";
99 static const char size_64
[] = "64";
101 static const char *size_enums
[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE
/* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto
= 1;
123 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
125 static int mips_debug
= 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi
;
135 enum mips_abi found_abi
;
136 enum mips_fpu_type mips_fpu_type
;
137 int mips_last_arg_regnum
;
138 int mips_last_fp_arg_regnum
;
139 int mips_default_saved_regsize
;
140 int mips_fp_register_double
;
141 int mips_default_stack_argsize
;
142 int gdb_target_is_mips64
;
143 int default_mask_address_p
;
145 enum gdb_osabi osabi
;
148 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
149 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
151 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
153 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
155 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
157 /* Return the currently configured (or set) saved register size. */
159 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
161 static const char *mips_saved_regsize_string
= size_auto
;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string
== size_auto
)
169 return MIPS_DEFAULT_SAVED_REGSIZE
;
170 else if (mips_saved_regsize_string
== size_64
)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
177 compatiblity mode. A return value of 1 means that we have
178 physical 64-bit registers, but should treat them as 32-bit registers. */
181 mips2_fp_compat (void)
183 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
185 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
189 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
190 in all the places we deal with FP registers. PR gdb/413. */
191 /* Otherwise check the FR bit in the status register - it controls
192 the FP compatiblity mode. If it is clear we are in compatibility
194 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
201 /* Indicate that the ABI makes use of double-precision registers
202 provided by the FPU (rather than combining pairs of registers to
203 form double-precision values). Do not use "TARGET_IS_MIPS64" to
204 determine if the ABI is using double-precision registers. See also
206 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
208 /* The amount of space reserved on the stack for registers. This is
209 different to MIPS_SAVED_REGSIZE as it determines the alignment of
210 data allocated after the registers have run out. */
212 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
214 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
216 static const char *mips_stack_argsize_string
= size_auto
;
219 mips_stack_argsize (void)
221 if (mips_stack_argsize_string
== size_auto
)
222 return MIPS_DEFAULT_STACK_ARGSIZE
;
223 else if (mips_stack_argsize_string
== size_64
)
225 else /* if (mips_stack_argsize_string == size_32) */
229 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
231 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
233 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
235 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
237 static void mips_print_register (int, int);
239 static mips_extra_func_info_t
240 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
242 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
244 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
246 int mips_set_processor_type (char *);
248 static void mips_show_processor_type_command (char *, int);
250 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
252 static mips_extra_func_info_t
253 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
255 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
256 mips_extra_func_info_t proc_desc
);
258 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
259 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
261 static struct type
*mips_float_register_type (void);
262 static struct type
*mips_double_register_type (void);
264 /* This value is the model of MIPS in use. It is derived from the value
265 of the PrID register. */
267 char *mips_processor_type
;
269 char *tmp_mips_processor_type
;
271 /* The list of available "set mips " and "show mips " commands */
273 static struct cmd_list_element
*setmipscmdlist
= NULL
;
274 static struct cmd_list_element
*showmipscmdlist
= NULL
;
276 /* A set of original names, to be used when restoring back to generic
277 registers from a specific set. */
279 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
280 char **mips_processor_reg_names
= mips_generic_reg_names
;
283 mips_register_name (int i
)
285 return mips_processor_reg_names
[i
];
288 /* Names of IDT R3041 registers. */
290 char *mips_r3041_reg_names
[] = {
291 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
292 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
293 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
294 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
295 "sr", "lo", "hi", "bad", "cause","pc",
296 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
297 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
298 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
299 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
300 "fsr", "fir", "fp", "",
301 "", "", "bus", "ccfg", "", "", "", "",
302 "", "", "port", "cmp", "", "", "epc", "prid",
305 /* Names of IDT R3051 registers. */
307 char *mips_r3051_reg_names
[] = {
308 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
309 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
310 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
311 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
312 "sr", "lo", "hi", "bad", "cause","pc",
313 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
314 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
315 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
316 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
317 "fsr", "fir", "fp", "",
318 "inx", "rand", "elo", "", "ctxt", "", "", "",
319 "", "", "ehi", "", "", "", "epc", "prid",
322 /* Names of IDT R3081 registers. */
324 char *mips_r3081_reg_names
[] = {
325 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
326 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
327 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
328 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
329 "sr", "lo", "hi", "bad", "cause","pc",
330 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
331 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
332 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
333 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
334 "fsr", "fir", "fp", "",
335 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
336 "", "", "ehi", "", "", "", "epc", "prid",
339 /* Names of LSI 33k registers. */
341 char *mips_lsi33k_reg_names
[] = {
342 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
343 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
344 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
345 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
346 "epc", "hi", "lo", "sr", "cause","badvaddr",
347 "dcic", "bpc", "bda", "", "", "", "", "",
348 "", "", "", "", "", "", "", "",
349 "", "", "", "", "", "", "", "",
350 "", "", "", "", "", "", "", "",
352 "", "", "", "", "", "", "", "",
353 "", "", "", "", "", "", "", "",
359 } mips_processor_type_table
[] = {
360 { "generic", mips_generic_reg_names
},
361 { "r3041", mips_r3041_reg_names
},
362 { "r3051", mips_r3051_reg_names
},
363 { "r3071", mips_r3081_reg_names
},
364 { "r3081", mips_r3081_reg_names
},
365 { "lsi33k", mips_lsi33k_reg_names
},
373 /* Table to translate MIPS16 register field to actual register number. */
374 static int mips16_to_32_reg
[8] =
375 {16, 17, 2, 3, 4, 5, 6, 7};
377 /* Heuristic_proc_start may hunt through the text section for a long
378 time across a 2400 baud serial line. Allows the user to limit this
381 static unsigned int heuristic_fence_post
= 0;
383 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
384 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
385 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
386 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
387 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
388 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
389 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
390 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
391 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
392 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
393 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
394 this will corrupt pdr.iline. Fortunately we don't use it. */
395 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
396 #define _PROC_MAGIC_ 0x0F0F0F0F
397 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
398 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
400 struct linked_proc_info
402 struct mips_extra_func_info info
;
403 struct linked_proc_info
*next
;
405 *linked_proc_desc_table
= NULL
;
408 mips_print_extra_frame_info (struct frame_info
*fi
)
412 && fi
->extra_info
->proc_desc
413 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
414 printf_filtered (" frame pointer is at %s+%s\n",
415 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
416 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
419 /* Number of bytes of storage in the actual machine representation for
420 register N. NOTE: This indirectly defines the register size
421 transfered by the GDB protocol. */
423 static int mips64_transfers_32bit_regs_p
= 0;
426 mips_register_raw_size (int reg_nr
)
428 if (mips64_transfers_32bit_regs_p
)
429 return REGISTER_VIRTUAL_SIZE (reg_nr
);
430 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
431 && FP_REGISTER_DOUBLE
)
432 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
439 /* Convert between RAW and VIRTUAL registers. The RAW register size
440 defines the remote-gdb packet. */
443 mips_register_convertible (int reg_nr
)
445 if (mips64_transfers_32bit_regs_p
)
448 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
452 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
453 char *raw_buf
, char *virt_buf
)
455 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
457 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
458 TYPE_LENGTH (virtual_type
));
462 TYPE_LENGTH (virtual_type
));
466 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
467 char *virt_buf
, char *raw_buf
)
469 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
470 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
471 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
473 TYPE_LENGTH (virtual_type
));
477 TYPE_LENGTH (virtual_type
));
481 mips_register_convert_to_type (int regnum
, struct type
*type
, char *buffer
)
483 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
484 && REGISTER_RAW_SIZE (regnum
) == 4
485 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
486 && TYPE_CODE(type
) == TYPE_CODE_FLT
487 && TYPE_LENGTH(type
) == 8)
490 memcpy (temp
, ((char *)(buffer
))+4, 4);
491 memcpy (((char *)(buffer
))+4, (buffer
), 4);
492 memcpy (((char *)(buffer
)), temp
, 4);
497 mips_register_convert_from_type (int regnum
, struct type
*type
, char *buffer
)
499 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
500 && REGISTER_RAW_SIZE (regnum
) == 4
501 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
502 && TYPE_CODE(type
) == TYPE_CODE_FLT
503 && TYPE_LENGTH(type
) == 8)
506 memcpy (temp
, ((char *)(buffer
))+4, 4);
507 memcpy (((char *)(buffer
))+4, (buffer
), 4);
508 memcpy (((char *)(buffer
)), temp
, 4);
512 /* Return the GDB type object for the "standard" data type
513 of data in register REG.
515 Note: kevinb/2002-08-01: The definition below should faithfully
516 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
517 definitions found in config/mips/tm-*.h. I'm concerned about
518 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
519 though. In some cases FP_REGNUM is in this range, and I doubt
520 that this code is correct for the 64-bit case. */
523 mips_register_virtual_type (int reg
)
525 if (FP0_REGNUM
<= reg
&& reg
< FP0_REGNUM
+ 32)
527 /* Floating point registers... */
528 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
529 return builtin_type_ieee_double_big
;
531 return builtin_type_ieee_double_little
;
533 else if (reg
== PS_REGNUM
/* CR */)
534 return builtin_type_uint32
;
535 else if (FCRCS_REGNUM
<= reg
&& reg
<= LAST_EMBED_REGNUM
)
536 return builtin_type_uint32
;
539 /* Everything else...
540 Return type appropriate for width of register. */
541 if (MIPS_REGSIZE
== TYPE_LENGTH (builtin_type_uint64
))
542 return builtin_type_uint64
;
544 return builtin_type_uint32
;
548 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
553 return ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
556 /* Should the upper word of 64-bit addresses be zeroed? */
557 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
560 mips_mask_address_p (void)
562 switch (mask_address_var
)
564 case AUTO_BOOLEAN_TRUE
:
566 case AUTO_BOOLEAN_FALSE
:
569 case AUTO_BOOLEAN_AUTO
:
570 return MIPS_DEFAULT_MASK_ADDRESS_P
;
572 internal_error (__FILE__
, __LINE__
,
573 "mips_mask_address_p: bad switch");
579 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
581 switch (mask_address_var
)
583 case AUTO_BOOLEAN_TRUE
:
584 printf_filtered ("The 32 bit mips address mask is enabled\n");
586 case AUTO_BOOLEAN_FALSE
:
587 printf_filtered ("The 32 bit mips address mask is disabled\n");
589 case AUTO_BOOLEAN_AUTO
:
590 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
591 mips_mask_address_p () ? "enabled" : "disabled");
594 internal_error (__FILE__
, __LINE__
,
595 "show_mask_address: bad switch");
600 /* Should call_function allocate stack space for a struct return? */
603 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
605 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
609 mips_n32n64_use_struct_convention (int gcc_p
, struct type
*type
)
611 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
615 mips_o32_use_struct_convention (int gcc_p
, struct type
*type
)
617 return 1; /* Structures are returned by ref in extra arg0. */
620 /* Should call_function pass struct by reference?
621 For each architecture, structs are passed either by
622 value or by reference, depending on their size. */
625 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
627 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
628 int len
= TYPE_LENGTH (check_typedef (type
));
630 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
631 return (len
> MIPS_SAVED_REGSIZE
);
637 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
639 return 0; /* Assumption: N32/N64 never passes struct by ref. */
643 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
645 return 0; /* Assumption: O32/O64 never passes struct by ref. */
648 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
651 pc_is_mips16 (bfd_vma memaddr
)
653 struct minimal_symbol
*sym
;
655 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
656 if (IS_MIPS16_ADDR (memaddr
))
659 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
660 the high bit of the info field. Use this to decide if the function is
661 MIPS16 or normal MIPS. */
662 sym
= lookup_minimal_symbol_by_pc (memaddr
);
664 return MSYMBOL_IS_SPECIAL (sym
);
669 /* MIPS believes that the PC has a sign extended value. Perhaphs the
670 all registers should be sign extended for simplicity? */
673 mips_read_pc (ptid_t ptid
)
675 return read_signed_register_pid (PC_REGNUM
, ptid
);
678 /* This returns the PC of the first inst after the prologue. If we can't
679 find the prologue, then return 0. */
682 after_prologue (CORE_ADDR pc
,
683 mips_extra_func_info_t proc_desc
)
685 struct symtab_and_line sal
;
686 CORE_ADDR func_addr
, func_end
;
688 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
689 to read the stack pointer from the current machine state, because
690 the current machine state has nothing to do with the information
691 we need from the proc_desc; and the process may or may not exist
694 proc_desc
= find_proc_desc (pc
, NULL
, 0);
698 /* If function is frameless, then we need to do it the hard way. I
699 strongly suspect that frameless always means prologueless... */
700 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
701 && PROC_FRAME_OFFSET (proc_desc
) == 0)
705 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
706 return 0; /* Unknown */
708 sal
= find_pc_line (func_addr
, 0);
710 if (sal
.end
< func_end
)
713 /* The line after the prologue is after the end of the function. In this
714 case, tell the caller to find the prologue the hard way. */
719 /* Decode a MIPS32 instruction that saves a register in the stack, and
720 set the appropriate bit in the general register mask or float register mask
721 to indicate which register is saved. This is a helper function
722 for mips_find_saved_regs. */
725 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
726 unsigned long *float_mask
)
730 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
731 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
732 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
734 /* It might be possible to use the instruction to
735 find the offset, rather than the code below which
736 is based on things being in a certain order in the
737 frame, but figuring out what the instruction's offset
738 is relative to might be a little tricky. */
739 reg
= (inst
& 0x001f0000) >> 16;
740 *gen_mask
|= (1 << reg
);
742 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
743 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
744 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
747 reg
= ((inst
& 0x001f0000) >> 16);
748 *float_mask
|= (1 << reg
);
752 /* Decode a MIPS16 instruction that saves a register in the stack, and
753 set the appropriate bit in the general register or float register mask
754 to indicate which register is saved. This is a helper function
755 for mips_find_saved_regs. */
758 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
760 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
762 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
763 *gen_mask
|= (1 << reg
);
765 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
767 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
768 *gen_mask
|= (1 << reg
);
770 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
771 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
772 *gen_mask
|= (1 << RA_REGNUM
);
776 /* Fetch and return instruction from the specified location. If the PC
777 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
780 mips_fetch_instruction (CORE_ADDR addr
)
782 char buf
[MIPS_INSTLEN
];
786 if (pc_is_mips16 (addr
))
788 instlen
= MIPS16_INSTLEN
;
789 addr
= UNMAKE_MIPS16_ADDR (addr
);
792 instlen
= MIPS_INSTLEN
;
793 status
= read_memory_nobpt (addr
, buf
, instlen
);
795 memory_error (status
, addr
);
796 return extract_unsigned_integer (buf
, instlen
);
800 /* These the fields of 32 bit mips instructions */
801 #define mips32_op(x) (x >> 26)
802 #define itype_op(x) (x >> 26)
803 #define itype_rs(x) ((x >> 21) & 0x1f)
804 #define itype_rt(x) ((x >> 16) & 0x1f)
805 #define itype_immediate(x) (x & 0xffff)
807 #define jtype_op(x) (x >> 26)
808 #define jtype_target(x) (x & 0x03ffffff)
810 #define rtype_op(x) (x >> 26)
811 #define rtype_rs(x) ((x >> 21) & 0x1f)
812 #define rtype_rt(x) ((x >> 16) & 0x1f)
813 #define rtype_rd(x) ((x >> 11) & 0x1f)
814 #define rtype_shamt(x) ((x >> 6) & 0x1f)
815 #define rtype_funct(x) (x & 0x3f)
818 mips32_relative_offset (unsigned long inst
)
821 x
= itype_immediate (inst
);
822 if (x
& 0x8000) /* sign bit set */
824 x
|= 0xffff0000; /* sign extension */
830 /* Determine whate to set a single step breakpoint while considering
833 mips32_next_pc (CORE_ADDR pc
)
837 inst
= mips_fetch_instruction (pc
);
838 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
840 if (itype_op (inst
) >> 2 == 5)
841 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
843 op
= (itype_op (inst
) & 0x03);
858 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
859 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
861 int tf
= itype_rt (inst
) & 0x01;
862 int cnum
= itype_rt (inst
) >> 2;
863 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
864 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
866 if (((cond
>> cnum
) & 0x01) == tf
)
867 pc
+= mips32_relative_offset (inst
) + 4;
872 pc
+= 4; /* Not a branch, next instruction is easy */
875 { /* This gets way messy */
877 /* Further subdivide into SPECIAL, REGIMM and other */
878 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
880 case 0: /* SPECIAL */
881 op
= rtype_funct (inst
);
886 /* Set PC to that address */
887 pc
= read_signed_register (rtype_rs (inst
));
893 break; /* end SPECIAL */
896 op
= itype_rt (inst
); /* branch condition */
901 case 16: /* BLTZAL */
902 case 18: /* BLTZALL */
904 if (read_signed_register (itype_rs (inst
)) < 0)
905 pc
+= mips32_relative_offset (inst
) + 4;
907 pc
+= 8; /* after the delay slot */
911 case 17: /* BGEZAL */
912 case 19: /* BGEZALL */
913 greater_equal_branch
:
914 if (read_signed_register (itype_rs (inst
)) >= 0)
915 pc
+= mips32_relative_offset (inst
) + 4;
917 pc
+= 8; /* after the delay slot */
919 /* All of the other instructions in the REGIMM category */
924 break; /* end REGIMM */
929 reg
= jtype_target (inst
) << 2;
930 /* Upper four bits get never changed... */
931 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
934 /* FIXME case JALX : */
937 reg
= jtype_target (inst
) << 2;
938 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
939 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
941 break; /* The new PC will be alternate mode */
942 case 4: /* BEQ, BEQL */
944 if (read_signed_register (itype_rs (inst
)) ==
945 read_signed_register (itype_rt (inst
)))
946 pc
+= mips32_relative_offset (inst
) + 4;
950 case 5: /* BNE, BNEL */
952 if (read_signed_register (itype_rs (inst
)) !=
953 read_signed_register (itype_rt (inst
)))
954 pc
+= mips32_relative_offset (inst
) + 4;
958 case 6: /* BLEZ, BLEZL */
960 if (read_signed_register (itype_rs (inst
) <= 0))
961 pc
+= mips32_relative_offset (inst
) + 4;
967 greater_branch
: /* BGTZ, BGTZL */
968 if (read_signed_register (itype_rs (inst
) > 0))
969 pc
+= mips32_relative_offset (inst
) + 4;
976 } /* mips32_next_pc */
978 /* Decoding the next place to set a breakpoint is irregular for the
979 mips 16 variant, but fortunately, there fewer instructions. We have to cope
980 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
981 We dont want to set a single step instruction on the extend instruction
985 /* Lots of mips16 instruction formats */
986 /* Predicting jumps requires itype,ritype,i8type
987 and their extensions extItype,extritype,extI8type
989 enum mips16_inst_fmts
991 itype
, /* 0 immediate 5,10 */
992 ritype
, /* 1 5,3,8 */
993 rrtype
, /* 2 5,3,3,5 */
994 rritype
, /* 3 5,3,3,5 */
995 rrrtype
, /* 4 5,3,3,3,2 */
996 rriatype
, /* 5 5,3,3,1,4 */
997 shifttype
, /* 6 5,3,3,3,2 */
998 i8type
, /* 7 5,3,8 */
999 i8movtype
, /* 8 5,3,3,5 */
1000 i8mov32rtype
, /* 9 5,3,5,3 */
1001 i64type
, /* 10 5,3,8 */
1002 ri64type
, /* 11 5,3,3,5 */
1003 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1004 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1005 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1006 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1007 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1008 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1009 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1010 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1011 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1012 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1014 /* I am heaping all the fields of the formats into one structure and
1015 then, only the fields which are involved in instruction extension */
1019 unsigned int regx
; /* Function in i8 type */
1024 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1025 for the bits which make up the immediatate extension. */
1028 extended_offset (unsigned int extension
)
1031 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1033 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1035 value
|= extension
& 0x01f; /* extract 4:0 */
1039 /* Only call this function if you know that this is an extendable
1040 instruction, It wont malfunction, but why make excess remote memory references?
1041 If the immediate operands get sign extended or somthing, do it after
1042 the extension is performed.
1044 /* FIXME: Every one of these cases needs to worry about sign extension
1045 when the offset is to be used in relative addressing */
1049 fetch_mips_16 (CORE_ADDR pc
)
1052 pc
&= 0xfffffffe; /* clear the low order bit */
1053 target_read_memory (pc
, buf
, 2);
1054 return extract_unsigned_integer (buf
, 2);
1058 unpack_mips16 (CORE_ADDR pc
,
1059 unsigned int extension
,
1061 enum mips16_inst_fmts insn_format
,
1062 struct upk_mips16
*upk
)
1067 switch (insn_format
)
1074 value
= extended_offset (extension
);
1075 value
= value
<< 11; /* rom for the original value */
1076 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1080 value
= inst
& 0x7ff;
1081 /* FIXME : Consider sign extension */
1090 { /* A register identifier and an offset */
1091 /* Most of the fields are the same as I type but the
1092 immediate value is of a different length */
1096 value
= extended_offset (extension
);
1097 value
= value
<< 8; /* from the original instruction */
1098 value
|= inst
& 0xff; /* eleven bits from instruction */
1099 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1100 if (value
& 0x4000) /* test the sign bit , bit 26 */
1102 value
&= ~0x3fff; /* remove the sign bit */
1108 value
= inst
& 0xff; /* 8 bits */
1109 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1110 /* FIXME: Do sign extension , this format needs it */
1111 if (value
& 0x80) /* THIS CONFUSES ME */
1113 value
&= 0xef; /* remove the sign bit */
1123 unsigned long value
;
1124 unsigned int nexthalf
;
1125 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1126 value
= value
<< 16;
1127 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1135 internal_error (__FILE__
, __LINE__
,
1138 upk
->offset
= offset
;
1145 add_offset_16 (CORE_ADDR pc
, int offset
)
1147 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1151 extended_mips16_next_pc (CORE_ADDR pc
,
1152 unsigned int extension
,
1155 int op
= (insn
>> 11);
1158 case 2: /* Branch */
1161 struct upk_mips16 upk
;
1162 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1163 offset
= upk
.offset
;
1169 pc
+= (offset
<< 1) + 2;
1172 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1174 struct upk_mips16 upk
;
1175 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1176 pc
= add_offset_16 (pc
, upk
.offset
);
1177 if ((insn
>> 10) & 0x01) /* Exchange mode */
1178 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1185 struct upk_mips16 upk
;
1187 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1188 reg
= read_signed_register (upk
.regx
);
1190 pc
+= (upk
.offset
<< 1) + 2;
1197 struct upk_mips16 upk
;
1199 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1200 reg
= read_signed_register (upk
.regx
);
1202 pc
+= (upk
.offset
<< 1) + 2;
1207 case 12: /* I8 Formats btez btnez */
1209 struct upk_mips16 upk
;
1211 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1212 /* upk.regx contains the opcode */
1213 reg
= read_signed_register (24); /* Test register is 24 */
1214 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1215 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1216 /* pc = add_offset_16(pc,upk.offset) ; */
1217 pc
+= (upk
.offset
<< 1) + 2;
1222 case 29: /* RR Formats JR, JALR, JALR-RA */
1224 struct upk_mips16 upk
;
1225 /* upk.fmt = rrtype; */
1230 upk
.regx
= (insn
>> 8) & 0x07;
1231 upk
.regy
= (insn
>> 5) & 0x07;
1239 break; /* Function return instruction */
1245 break; /* BOGUS Guess */
1247 pc
= read_signed_register (reg
);
1254 /* This is an instruction extension. Fetch the real instruction
1255 (which follows the extension) and decode things based on
1259 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1272 mips16_next_pc (CORE_ADDR pc
)
1274 unsigned int insn
= fetch_mips_16 (pc
);
1275 return extended_mips16_next_pc (pc
, 0, insn
);
1278 /* The mips_next_pc function supports single_step when the remote
1279 target monitor or stub is not developed enough to do a single_step.
1280 It works by decoding the current instruction and predicting where a
1281 branch will go. This isnt hard because all the data is available.
1282 The MIPS32 and MIPS16 variants are quite different */
1284 mips_next_pc (CORE_ADDR pc
)
1287 return mips16_next_pc (pc
);
1289 return mips32_next_pc (pc
);
1292 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1295 Note: kevinb/2002-08-09: The only caller of this function is (and
1296 should remain) mips_frame_init_saved_regs(). In fact,
1297 aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs()
1298 does nothing more than set frame->saved_regs[SP_REGNUM]. These two
1299 functions should really be combined and now that there is only one
1300 caller, it should be straightforward. (Watch out for multiple returns
1304 mips_find_saved_regs (struct frame_info
*fci
)
1307 CORE_ADDR reg_position
;
1308 /* r0 bit means kernel trap */
1310 /* What registers have been saved? Bitmasks. */
1311 unsigned long gen_mask
, float_mask
;
1312 mips_extra_func_info_t proc_desc
;
1315 frame_saved_regs_zalloc (fci
);
1317 /* If it is the frame for sigtramp, the saved registers are located
1318 in a sigcontext structure somewhere on the stack.
1319 If the stack layout for sigtramp changes we might have to change these
1320 constants and the companion fixup_sigtramp in mdebugread.c */
1321 #ifndef SIGFRAME_BASE
1322 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1323 above the sigtramp frame. */
1324 #define SIGFRAME_BASE MIPS_REGSIZE
1325 /* FIXME! Are these correct?? */
1326 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1327 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1328 #define SIGFRAME_FPREGSAVE_OFF \
1329 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1331 #ifndef SIGFRAME_REG_SIZE
1332 /* FIXME! Is this correct?? */
1333 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1335 if (fci
->signal_handler_caller
)
1337 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1339 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1340 + ireg
* SIGFRAME_REG_SIZE
;
1341 fci
->saved_regs
[ireg
] = reg_position
;
1343 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1345 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1346 + ireg
* SIGFRAME_REG_SIZE
;
1347 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1349 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1353 proc_desc
= fci
->extra_info
->proc_desc
;
1354 if (proc_desc
== NULL
)
1355 /* I'm not sure how/whether this can happen. Normally when we can't
1356 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1357 and set the saved_regs right away. */
1360 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1361 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1362 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1364 if ( /* In any frame other than the innermost or a frame interrupted by
1365 a signal, we assume that all registers have been saved.
1366 This assumes that all register saves in a function happen before
1367 the first function call. */
1368 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1370 /* In a dummy frame we know exactly where things are saved. */
1371 && !PROC_DESC_IS_DUMMY (proc_desc
)
1373 /* Don't bother unless we are inside a function prologue. Outside the
1374 prologue, we know where everything is. */
1376 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1378 /* Not sure exactly what kernel_trap means, but if it means
1379 the kernel saves the registers without a prologue doing it,
1380 we better not examine the prologue to see whether registers
1381 have been saved yet. */
1384 /* We need to figure out whether the registers that the proc_desc
1385 claims are saved have been saved yet. */
1389 /* Bitmasks; set if we have found a save for the register. */
1390 unsigned long gen_save_found
= 0;
1391 unsigned long float_save_found
= 0;
1394 /* If the address is odd, assume this is MIPS16 code. */
1395 addr
= PROC_LOW_ADDR (proc_desc
);
1396 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1398 /* Scan through this function's instructions preceding the current
1399 PC, and look for those that save registers. */
1400 while (addr
< fci
->pc
)
1402 inst
= mips_fetch_instruction (addr
);
1403 if (pc_is_mips16 (addr
))
1404 mips16_decode_reg_save (inst
, &gen_save_found
);
1406 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1409 gen_mask
= gen_save_found
;
1410 float_mask
= float_save_found
;
1413 /* Fill in the offsets for the registers which gen_mask says
1415 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1416 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1417 if (gen_mask
& 0x80000000)
1419 fci
->saved_regs
[ireg
] = reg_position
;
1420 reg_position
-= MIPS_SAVED_REGSIZE
;
1423 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1424 of that normally used by gcc. Therefore, we have to fetch the first
1425 instruction of the function, and if it's an entry instruction that
1426 saves $s0 or $s1, correct their saved addresses. */
1427 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1429 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1430 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1433 int sreg_count
= (inst
>> 6) & 3;
1435 /* Check if the ra register was pushed on the stack. */
1436 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1438 reg_position
-= MIPS_SAVED_REGSIZE
;
1440 /* Check if the s0 and s1 registers were pushed on the stack. */
1441 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1443 fci
->saved_regs
[reg
] = reg_position
;
1444 reg_position
-= MIPS_SAVED_REGSIZE
;
1449 /* Fill in the offsets for the registers which float_mask says
1451 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1453 /* Apparently, the freg_offset gives the offset to the first 64 bit
1456 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1457 designates the first saved 64 bit register.
1459 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1460 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1461 FREG_OFFSET, designates the address of the lower register of the
1462 register pair. Adjust the offset so that it designates the upper
1463 register of the pair -- i.e., the address of the first saved 32
1466 if (MIPS_SAVED_REGSIZE
== 4)
1467 reg_position
+= MIPS_SAVED_REGSIZE
;
1469 /* Fill in the offsets for the float registers which float_mask says
1471 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1472 if (float_mask
& 0x80000000)
1474 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1475 reg_position
-= MIPS_SAVED_REGSIZE
;
1478 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1481 /* Set up the 'saved_regs' array. This is a data structure containing
1482 the addresses on the stack where each register has been saved, for
1483 each stack frame. Registers that have not been saved will have
1484 zero here. The stack pointer register is special: rather than the
1485 address where the stack register has been saved, saved_regs[SP_REGNUM]
1486 will have the actual value of the previous frame's stack register. */
1489 mips_frame_init_saved_regs (struct frame_info
*frame
)
1491 if (frame
->saved_regs
== NULL
)
1493 mips_find_saved_regs (frame
);
1495 frame
->saved_regs
[SP_REGNUM
] = frame
->frame
;
1499 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1501 for (; fi
; fi
= fi
->next
)
1503 /* We have to get the saved sp from the sigcontext
1504 if it is a signal handler frame. */
1505 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1509 if (fi
->saved_regs
== NULL
)
1510 FRAME_INIT_SAVED_REGS (fi
);
1511 if (fi
->saved_regs
[regno
])
1512 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1515 return read_signed_register (regno
);
1518 /* mips_addr_bits_remove - remove useless address bits */
1521 mips_addr_bits_remove (CORE_ADDR addr
)
1523 if (GDB_TARGET_IS_MIPS64
)
1525 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1527 /* This hack is a work-around for existing boards using
1528 PMON, the simulator, and any other 64-bit targets that
1529 doesn't have true 64-bit addressing. On these targets,
1530 the upper 32 bits of addresses are ignored by the
1531 hardware. Thus, the PC or SP are likely to have been
1532 sign extended to all 1s by instruction sequences that
1533 load 32-bit addresses. For example, a typical piece of
1534 code that loads an address is this:
1535 lui $r2, <upper 16 bits>
1536 ori $r2, <lower 16 bits>
1537 But the lui sign-extends the value such that the upper 32
1538 bits may be all 1s. The workaround is simply to mask off
1539 these bits. In the future, gcc may be changed to support
1540 true 64-bit addressing, and this masking will have to be
1542 addr
&= (CORE_ADDR
) 0xffffffff;
1545 else if (mips_mask_address_p ())
1547 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1548 masking off bits, instead, the actual target should be asking
1549 for the address to be converted to a valid pointer. */
1550 /* Even when GDB is configured for some 32-bit targets
1551 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1552 so CORE_ADDR is 64 bits. So we still have to mask off
1553 useless bits from addresses. */
1554 addr
&= (CORE_ADDR
) 0xffffffff;
1559 /* mips_software_single_step() is called just before we want to resume
1560 the inferior, if we want to single-step it but there is no hardware
1561 or kernel single-step support (MIPS on GNU/Linux for example). We find
1562 the target of the coming instruction and breakpoint it.
1564 single_step is also called just after the inferior stops. If we had
1565 set up a simulated single-step, we undo our damage. */
1568 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1570 static CORE_ADDR next_pc
;
1571 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1572 static binsn_quantum break_mem
;
1575 if (insert_breakpoints_p
)
1577 pc
= read_register (PC_REGNUM
);
1578 next_pc
= mips_next_pc (pc
);
1580 target_insert_breakpoint (next_pc
, break_mem
);
1583 target_remove_breakpoint (next_pc
, break_mem
);
1587 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1591 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1592 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1593 tmp
= mips_skip_stub (pc
);
1594 prev
->pc
= tmp
? tmp
: pc
;
1599 mips_frame_saved_pc (struct frame_info
*frame
)
1602 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1603 /* We have to get the saved pc from the sigcontext
1604 if it is a signal handler frame. */
1605 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1606 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1608 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1609 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1611 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1613 return ADDR_BITS_REMOVE (saved_pc
);
1616 static struct mips_extra_func_info temp_proc_desc
;
1617 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1619 /* Set a register's saved stack address in temp_saved_regs. If an address
1620 has already been set for this register, do nothing; this way we will
1621 only recognize the first save of a given register in a function prologue.
1622 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1625 set_reg_offset (int regno
, CORE_ADDR offset
)
1627 if (temp_saved_regs
[regno
] == 0)
1628 temp_saved_regs
[regno
] = offset
;
1632 /* Test whether the PC points to the return instruction at the
1633 end of a function. */
1636 mips_about_to_return (CORE_ADDR pc
)
1638 if (pc_is_mips16 (pc
))
1639 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1640 generates a "jr $ra"; other times it generates code to load
1641 the return address from the stack to an accessible register (such
1642 as $a3), then a "jr" using that register. This second case
1643 is almost impossible to distinguish from an indirect jump
1644 used for switch statements, so we don't even try. */
1645 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1647 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1651 /* This fencepost looks highly suspicious to me. Removing it also
1652 seems suspicious as it could affect remote debugging across serial
1656 heuristic_proc_start (CORE_ADDR pc
)
1663 pc
= ADDR_BITS_REMOVE (pc
);
1665 fence
= start_pc
- heuristic_fence_post
;
1669 if (heuristic_fence_post
== UINT_MAX
1670 || fence
< VM_MIN_ADDRESS
)
1671 fence
= VM_MIN_ADDRESS
;
1673 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1675 /* search back for previous return */
1676 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1677 if (start_pc
< fence
)
1679 /* It's not clear to me why we reach this point when
1680 stop_soon_quietly, but with this test, at least we
1681 don't print out warnings for every child forked (eg, on
1682 decstation). 22apr93 rich@cygnus.com. */
1683 if (!stop_soon_quietly
)
1685 static int blurb_printed
= 0;
1687 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1692 /* This actually happens frequently in embedded
1693 development, when you first connect to a board
1694 and your stack pointer and pc are nowhere in
1695 particular. This message needs to give people
1696 in that situation enough information to
1697 determine that it's no big deal. */
1698 printf_filtered ("\n\
1699 GDB is unable to find the start of the function at 0x%s\n\
1700 and thus can't determine the size of that function's stack frame.\n\
1701 This means that GDB may be unable to access that stack frame, or\n\
1702 the frames below it.\n\
1703 This problem is most likely caused by an invalid program counter or\n\
1705 However, if you think GDB should simply search farther back\n\
1706 from 0x%s for code which looks like the beginning of a\n\
1707 function, you can increase the range of the search using the `set\n\
1708 heuristic-fence-post' command.\n",
1709 paddr_nz (pc
), paddr_nz (pc
));
1716 else if (pc_is_mips16 (start_pc
))
1718 unsigned short inst
;
1720 /* On MIPS16, any one of the following is likely to be the
1721 start of a function:
1725 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1726 inst
= mips_fetch_instruction (start_pc
);
1727 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1728 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1729 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1730 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1732 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1733 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1738 else if (mips_about_to_return (start_pc
))
1740 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1747 /* Fetch the immediate value from a MIPS16 instruction.
1748 If the previous instruction was an EXTEND, use it to extend
1749 the upper bits of the immediate value. This is a helper function
1750 for mips16_heuristic_proc_desc. */
1753 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1754 unsigned short inst
, /* current instruction */
1755 int nbits
, /* number of bits in imm field */
1756 int scale
, /* scale factor to be applied to imm */
1757 int is_signed
) /* is the imm field signed? */
1761 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1763 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1764 if (offset
& 0x8000) /* check for negative extend */
1765 offset
= 0 - (0x10000 - (offset
& 0xffff));
1766 return offset
| (inst
& 0x1f);
1770 int max_imm
= 1 << nbits
;
1771 int mask
= max_imm
- 1;
1772 int sign_bit
= max_imm
>> 1;
1774 offset
= inst
& mask
;
1775 if (is_signed
&& (offset
& sign_bit
))
1776 offset
= 0 - (max_imm
- offset
);
1777 return offset
* scale
;
1782 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1783 stream from start_pc to limit_pc. */
1786 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1787 struct frame_info
*next_frame
, CORE_ADDR sp
)
1790 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1791 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1792 unsigned inst
= 0; /* current instruction */
1793 unsigned entry_inst
= 0; /* the entry instruction */
1796 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1797 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1799 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1801 /* Save the previous instruction. If it's an EXTEND, we'll extract
1802 the immediate offset extension from it in mips16_get_imm. */
1805 /* Fetch and decode the instruction. */
1806 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1807 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1808 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1810 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1811 if (offset
< 0) /* negative stack adjustment? */
1812 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1814 /* Exit loop if a positive stack adjustment is found, which
1815 usually means that the stack cleanup code in the function
1816 epilogue is reached. */
1819 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1821 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1822 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1823 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1824 set_reg_offset (reg
, sp
+ offset
);
1826 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1828 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1829 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1830 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1831 set_reg_offset (reg
, sp
+ offset
);
1833 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1835 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1836 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1837 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1839 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1841 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1842 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1843 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1845 else if (inst
== 0x673d) /* move $s1, $sp */
1848 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1850 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1852 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1853 frame_addr
= sp
+ offset
;
1854 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1855 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1857 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1859 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1860 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1861 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1862 set_reg_offset (reg
, frame_addr
+ offset
);
1864 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1866 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1867 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1868 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1869 set_reg_offset (reg
, frame_addr
+ offset
);
1871 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1872 entry_inst
= inst
; /* save for later processing */
1873 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1874 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1877 /* The entry instruction is typically the first instruction in a function,
1878 and it stores registers at offsets relative to the value of the old SP
1879 (before the prologue). But the value of the sp parameter to this
1880 function is the new SP (after the prologue has been executed). So we
1881 can't calculate those offsets until we've seen the entire prologue,
1882 and can calculate what the old SP must have been. */
1883 if (entry_inst
!= 0)
1885 int areg_count
= (entry_inst
>> 8) & 7;
1886 int sreg_count
= (entry_inst
>> 6) & 3;
1888 /* The entry instruction always subtracts 32 from the SP. */
1889 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1891 /* Now we can calculate what the SP must have been at the
1892 start of the function prologue. */
1893 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1895 /* Check if a0-a3 were saved in the caller's argument save area. */
1896 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1898 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1899 set_reg_offset (reg
, sp
+ offset
);
1900 offset
+= MIPS_SAVED_REGSIZE
;
1903 /* Check if the ra register was pushed on the stack. */
1905 if (entry_inst
& 0x20)
1907 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1908 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1909 offset
-= MIPS_SAVED_REGSIZE
;
1912 /* Check if the s0 and s1 registers were pushed on the stack. */
1913 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1915 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1916 set_reg_offset (reg
, sp
+ offset
);
1917 offset
-= MIPS_SAVED_REGSIZE
;
1923 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1924 struct frame_info
*next_frame
, CORE_ADDR sp
)
1927 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1929 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1930 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1931 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1932 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1934 unsigned long inst
, high_word
, low_word
;
1937 /* Fetch the instruction. */
1938 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1940 /* Save some code by pre-extracting some useful fields. */
1941 high_word
= (inst
>> 16) & 0xffff;
1942 low_word
= inst
& 0xffff;
1943 reg
= high_word
& 0x1f;
1945 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1946 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1947 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1949 if (low_word
& 0x8000) /* negative stack adjustment? */
1950 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1952 /* Exit loop if a positive stack adjustment is found, which
1953 usually means that the stack cleanup code in the function
1954 epilogue is reached. */
1957 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1959 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1960 set_reg_offset (reg
, sp
+ low_word
);
1962 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1964 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1965 but the register size used is only 32 bits. Make the address
1966 for the saved register point to the lower 32 bits. */
1967 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1968 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1970 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1972 /* Old gcc frame, r30 is virtual frame pointer. */
1973 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1974 frame_addr
= sp
+ low_word
;
1975 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1977 unsigned alloca_adjust
;
1978 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1979 frame_addr
= read_next_frame_reg (next_frame
, 30);
1980 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1981 if (alloca_adjust
> 0)
1983 /* FP > SP + frame_size. This may be because
1984 * of an alloca or somethings similar.
1985 * Fix sp to "pre-alloca" value, and try again.
1987 sp
+= alloca_adjust
;
1992 /* move $30,$sp. With different versions of gas this will be either
1993 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1994 Accept any one of these. */
1995 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1997 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1998 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2000 unsigned alloca_adjust
;
2001 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2002 frame_addr
= read_next_frame_reg (next_frame
, 30);
2003 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2004 if (alloca_adjust
> 0)
2006 /* FP > SP + frame_size. This may be because
2007 * of an alloca or somethings similar.
2008 * Fix sp to "pre-alloca" value, and try again.
2010 sp
+= alloca_adjust
;
2015 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2017 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2018 set_reg_offset (reg
, frame_addr
+ low_word
);
2023 static mips_extra_func_info_t
2024 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2025 struct frame_info
*next_frame
, int cur_frame
)
2030 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
2036 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2037 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2038 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2039 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2040 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2042 if (start_pc
+ 200 < limit_pc
)
2043 limit_pc
= start_pc
+ 200;
2044 if (pc_is_mips16 (start_pc
))
2045 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2047 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2048 return &temp_proc_desc
;
2051 struct mips_objfile_private
2057 /* Global used to communicate between non_heuristic_proc_desc and
2058 compare_pdr_entries within qsort (). */
2059 static bfd
*the_bfd
;
2062 compare_pdr_entries (const void *a
, const void *b
)
2064 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2065 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2069 else if (lhs
== rhs
)
2075 static mips_extra_func_info_t
2076 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2078 CORE_ADDR startaddr
;
2079 mips_extra_func_info_t proc_desc
;
2080 struct block
*b
= block_for_pc (pc
);
2082 struct obj_section
*sec
;
2083 struct mips_objfile_private
*priv
;
2085 if (PC_IN_CALL_DUMMY (pc
, 0, 0))
2088 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2090 *addrptr
= startaddr
;
2094 sec
= find_pc_section (pc
);
2097 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2099 /* Search the ".pdr" section generated by GAS. This includes most of
2100 the information normally found in ECOFF PDRs. */
2102 the_bfd
= sec
->objfile
->obfd
;
2104 && (the_bfd
->format
== bfd_object
2105 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2106 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2108 /* Right now GAS only outputs the address as a four-byte sequence.
2109 This means that we should not bother with this method on 64-bit
2110 targets (until that is fixed). */
2112 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2113 sizeof (struct mips_objfile_private
));
2115 sec
->objfile
->obj_private
= priv
;
2117 else if (priv
== NULL
)
2121 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2122 sizeof (struct mips_objfile_private
));
2124 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2127 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2128 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2130 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2131 priv
->contents
, 0, priv
->size
);
2133 /* In general, the .pdr section is sorted. However, in the
2134 presence of multiple code sections (and other corner cases)
2135 it can become unsorted. Sort it so that we can use a faster
2137 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2142 sec
->objfile
->obj_private
= priv
;
2146 if (priv
->size
!= 0)
2152 high
= priv
->size
/ 32;
2158 mid
= (low
+ high
) / 2;
2160 ptr
= priv
->contents
+ mid
* 32;
2161 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2162 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2163 SECT_OFF_TEXT (sec
->objfile
));
2164 if (pdr_pc
== startaddr
)
2166 if (pdr_pc
> startaddr
)
2171 while (low
!= high
);
2175 struct symbol
*sym
= find_pc_function (pc
);
2177 /* Fill in what we need of the proc_desc. */
2178 proc_desc
= (mips_extra_func_info_t
)
2179 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2180 sizeof (struct mips_extra_func_info
));
2181 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2183 /* Only used for dummy frames. */
2184 PROC_HIGH_ADDR (proc_desc
) = 0;
2186 PROC_FRAME_OFFSET (proc_desc
)
2187 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2188 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2190 PROC_FRAME_ADJUST (proc_desc
) = 0;
2191 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2193 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2195 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2197 PROC_FREG_OFFSET (proc_desc
)
2198 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2199 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2201 proc_desc
->pdr
.isym
= (long) sym
;
2211 if (startaddr
> BLOCK_START (b
))
2213 /* This is the "pathological" case referred to in a comment in
2214 print_frame_info. It might be better to move this check into
2219 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
2221 /* If we never found a PDR for this function in symbol reading, then
2222 examine prologues to find the information. */
2225 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2226 if (PROC_FRAME_REG (proc_desc
) == -1)
2236 static mips_extra_func_info_t
2237 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2239 mips_extra_func_info_t proc_desc
;
2240 CORE_ADDR startaddr
;
2242 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2246 /* IF this is the topmost frame AND
2247 * (this proc does not have debugging information OR
2248 * the PC is in the procedure prologue)
2249 * THEN create a "heuristic" proc_desc (by analyzing
2250 * the actual code) to replace the "official" proc_desc.
2252 if (next_frame
== NULL
)
2254 struct symtab_and_line val
;
2255 struct symbol
*proc_symbol
=
2256 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2260 val
= find_pc_line (BLOCK_START
2261 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2263 val
.pc
= val
.end
? val
.end
: pc
;
2265 if (!proc_symbol
|| pc
< val
.pc
)
2267 mips_extra_func_info_t found_heuristic
=
2268 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2269 pc
, next_frame
, cur_frame
);
2270 if (found_heuristic
)
2271 proc_desc
= found_heuristic
;
2277 /* Is linked_proc_desc_table really necessary? It only seems to be used
2278 by procedure call dummys. However, the procedures being called ought
2279 to have their own proc_descs, and even if they don't,
2280 heuristic_proc_desc knows how to create them! */
2282 register struct linked_proc_info
*link
;
2284 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2285 if (PROC_LOW_ADDR (&link
->info
) <= pc
2286 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2290 startaddr
= heuristic_proc_start (pc
);
2293 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2299 get_frame_pointer (struct frame_info
*frame
,
2300 mips_extra_func_info_t proc_desc
)
2302 return ADDR_BITS_REMOVE (read_next_frame_reg (frame
,
2303 PROC_FRAME_REG (proc_desc
)) +
2304 PROC_FRAME_OFFSET (proc_desc
) -
2305 PROC_FRAME_ADJUST (proc_desc
));
2308 mips_extra_func_info_t cached_proc_desc
;
2311 mips_frame_chain (struct frame_info
*frame
)
2313 mips_extra_func_info_t proc_desc
;
2315 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2317 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2320 /* Check if the PC is inside a call stub. If it is, fetch the
2321 PC of the caller of that stub. */
2322 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2325 /* Look up the procedure descriptor for this PC. */
2326 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2330 cached_proc_desc
= proc_desc
;
2332 /* If no frame pointer and frame size is zero, we must be at end
2333 of stack (or otherwise hosed). If we don't check frame size,
2334 we loop forever if we see a zero size frame. */
2335 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2336 && PROC_FRAME_OFFSET (proc_desc
) == 0
2337 /* The previous frame from a sigtramp frame might be frameless
2338 and have frame size zero. */
2339 && !frame
->signal_handler_caller
)
2342 return get_frame_pointer (frame
, proc_desc
);
2346 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2350 /* Use proc_desc calculated in frame_chain */
2351 mips_extra_func_info_t proc_desc
=
2352 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2354 fci
->extra_info
= (struct frame_extra_info
*)
2355 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2357 fci
->saved_regs
= NULL
;
2358 fci
->extra_info
->proc_desc
=
2359 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2362 /* Fixup frame-pointer - only needed for top frame */
2363 /* This may not be quite right, if proc has a real frame register.
2364 Get the value of the frame relative sp, procedure might have been
2365 interrupted by a signal at it's very start. */
2366 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2367 && !PROC_DESC_IS_DUMMY (proc_desc
))
2368 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2370 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2372 if (proc_desc
== &temp_proc_desc
)
2376 /* Do not set the saved registers for a sigtramp frame,
2377 mips_find_saved_registers will do that for us.
2378 We can't use fci->signal_handler_caller, it is not yet set. */
2379 find_pc_partial_function (fci
->pc
, &name
,
2380 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2381 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2383 frame_saved_regs_zalloc (fci
);
2384 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2385 fci
->saved_regs
[PC_REGNUM
]
2386 = fci
->saved_regs
[RA_REGNUM
];
2387 /* Set value of previous frame's stack pointer. Remember that
2388 saved_regs[SP_REGNUM] is special in that it contains the
2389 value of the stack pointer register. The other saved_regs
2390 values are addresses (in the inferior) at which a given
2391 register's value may be found. */
2392 fci
->saved_regs
[SP_REGNUM
] = fci
->frame
;
2396 /* hack: if argument regs are saved, guess these contain args */
2397 /* assume we can't tell how many args for now */
2398 fci
->extra_info
->num_args
= -1;
2399 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2401 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2403 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2410 /* MIPS stack frames are almost impenetrable. When execution stops,
2411 we basically have to look at symbol information for the function
2412 that we stopped in, which tells us *which* register (if any) is
2413 the base of the frame pointer, and what offset from that register
2414 the frame itself is at.
2416 This presents a problem when trying to examine a stack in memory
2417 (that isn't executing at the moment), using the "frame" command. We
2418 don't have a PC, nor do we have any registers except SP.
2420 This routine takes two arguments, SP and PC, and tries to make the
2421 cached frames look as if these two arguments defined a frame on the
2422 cache. This allows the rest of info frame to extract the important
2423 arguments without difficulty. */
2426 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2429 error ("MIPS frame specifications require two arguments: sp and pc");
2431 return create_new_frame (argv
[0], argv
[1]);
2434 /* According to the current ABI, should the type be passed in a
2435 floating-point register (assuming that there is space)? When there
2436 is no FPU, FP are not even considered as possibile candidates for
2437 FP registers and, consequently this returns false - forces FP
2438 arguments into integer registers. */
2441 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2443 return ((typecode
== TYPE_CODE_FLT
2445 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2446 && TYPE_NFIELDS (arg_type
) == 1
2447 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2448 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2451 /* On o32, argument passing in GPRs depends on the alignment of the type being
2452 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2455 mips_type_needs_double_align (struct type
*type
)
2457 enum type_code typecode
= TYPE_CODE (type
);
2459 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2461 else if (typecode
== TYPE_CODE_STRUCT
)
2463 if (TYPE_NFIELDS (type
) < 1)
2465 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2467 else if (typecode
== TYPE_CODE_UNION
)
2471 n
= TYPE_NFIELDS (type
);
2472 for (i
= 0; i
< n
; i
++)
2473 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2480 /* Macros to round N up or down to the next A boundary;
2481 A must be a power of two. */
2483 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2484 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2487 mips_eabi_push_arguments (int nargs
,
2488 struct value
**args
,
2491 CORE_ADDR struct_addr
)
2497 int stack_offset
= 0;
2499 /* First ensure that the stack and structure return address (if any)
2500 are properly aligned. The stack has to be at least 64-bit
2501 aligned even on 32-bit machines, because doubles must be 64-bit
2502 aligned. For n32 and n64, stack frames need to be 128-bit
2503 aligned, so we round to this widest known alignment. */
2505 sp
= ROUND_DOWN (sp
, 16);
2506 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2508 /* Now make space on the stack for the args. We allocate more
2509 than necessary for EABI, because the first few arguments are
2510 passed in registers, but that's OK. */
2511 for (argnum
= 0; argnum
< nargs
; argnum
++)
2512 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2513 MIPS_STACK_ARGSIZE
);
2514 sp
-= ROUND_UP (len
, 16);
2517 fprintf_unfiltered (gdb_stdlog
,
2518 "mips_eabi_push_arguments: sp=0x%s allocated %d\n",
2519 paddr_nz (sp
), ROUND_UP (len
, 16));
2521 /* Initialize the integer and float register pointers. */
2523 float_argreg
= FPA0_REGNUM
;
2525 /* The struct_return pointer occupies the first parameter-passing reg. */
2529 fprintf_unfiltered (gdb_stdlog
,
2530 "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n",
2531 argreg
, paddr_nz (struct_addr
));
2532 write_register (argreg
++, struct_addr
);
2535 /* Now load as many as possible of the first arguments into
2536 registers, and push the rest onto the stack. Loop thru args
2537 from first to last. */
2538 for (argnum
= 0; argnum
< nargs
; argnum
++)
2541 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
2542 struct value
*arg
= args
[argnum
];
2543 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2544 int len
= TYPE_LENGTH (arg_type
);
2545 enum type_code typecode
= TYPE_CODE (arg_type
);
2548 fprintf_unfiltered (gdb_stdlog
,
2549 "mips_eabi_push_arguments: %d len=%d type=%d",
2550 argnum
+ 1, len
, (int) typecode
);
2552 /* The EABI passes structures that do not fit in a register by
2554 if (len
> MIPS_SAVED_REGSIZE
2555 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2557 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2558 typecode
= TYPE_CODE_PTR
;
2559 len
= MIPS_SAVED_REGSIZE
;
2562 fprintf_unfiltered (gdb_stdlog
, " push");
2565 val
= (char *) VALUE_CONTENTS (arg
);
2567 /* 32-bit ABIs always start floating point arguments in an
2568 even-numbered floating point register. Round the FP register
2569 up before the check to see if there are any FP registers
2570 left. Non MIPS_EABI targets also pass the FP in the integer
2571 registers so also round up normal registers. */
2572 if (!FP_REGISTER_DOUBLE
2573 && fp_register_arg_p (typecode
, arg_type
))
2575 if ((float_argreg
& 1))
2579 /* Floating point arguments passed in registers have to be
2580 treated specially. On 32-bit architectures, doubles
2581 are passed in register pairs; the even register gets
2582 the low word, and the odd register gets the high word.
2583 On non-EABI processors, the first two floating point arguments are
2584 also copied to general registers, because MIPS16 functions
2585 don't use float registers for arguments. This duplication of
2586 arguments in general registers can't hurt non-MIPS16 functions
2587 because those registers are normally skipped. */
2588 /* MIPS_EABI squeezes a struct that contains a single floating
2589 point value into an FP register instead of pushing it onto the
2591 if (fp_register_arg_p (typecode
, arg_type
)
2592 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2594 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2596 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2597 unsigned long regval
;
2599 /* Write the low word of the double to the even register(s). */
2600 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2602 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2603 float_argreg
, phex (regval
, 4));
2604 write_register (float_argreg
++, regval
);
2606 /* Write the high word of the double to the odd register(s). */
2607 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2609 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2610 float_argreg
, phex (regval
, 4));
2611 write_register (float_argreg
++, regval
);
2615 /* This is a floating point value that fits entirely
2616 in a single register. */
2617 /* On 32 bit ABI's the float_argreg is further adjusted
2618 above to ensure that it is even register aligned. */
2619 LONGEST regval
= extract_unsigned_integer (val
, len
);
2621 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2622 float_argreg
, phex (regval
, len
));
2623 write_register (float_argreg
++, regval
);
2628 /* Copy the argument to general registers or the stack in
2629 register-sized pieces. Large arguments are split between
2630 registers and stack. */
2631 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2632 are treated specially: Irix cc passes them in registers
2633 where gcc sometimes puts them on the stack. For maximum
2634 compatibility, we will put them in both places. */
2635 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2636 (len
% MIPS_SAVED_REGSIZE
!= 0));
2638 /* Note: Floating-point values that didn't fit into an FP
2639 register are only written to memory. */
2642 /* Remember if the argument was written to the stack. */
2643 int stack_used_p
= 0;
2645 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2648 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2651 /* Write this portion of the argument to the stack. */
2652 if (argreg
> MIPS_LAST_ARG_REGNUM
2654 || fp_register_arg_p (typecode
, arg_type
))
2656 /* Should shorter than int integer values be
2657 promoted to int before being stored? */
2658 int longword_offset
= 0;
2661 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2663 if (MIPS_STACK_ARGSIZE
== 8 &&
2664 (typecode
== TYPE_CODE_INT
||
2665 typecode
== TYPE_CODE_PTR
||
2666 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2667 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2668 else if ((typecode
== TYPE_CODE_STRUCT
||
2669 typecode
== TYPE_CODE_UNION
) &&
2670 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2671 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2676 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2677 paddr_nz (stack_offset
));
2678 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2679 paddr_nz (longword_offset
));
2682 addr
= sp
+ stack_offset
+ longword_offset
;
2687 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2689 for (i
= 0; i
< partial_len
; i
++)
2691 fprintf_unfiltered (gdb_stdlog
, "%02x",
2695 write_memory (addr
, val
, partial_len
);
2698 /* Note!!! This is NOT an else clause. Odd sized
2699 structs may go thru BOTH paths. Floating point
2700 arguments will not. */
2701 /* Write this portion of the argument to a general
2702 purpose register. */
2703 if (argreg
<= MIPS_LAST_ARG_REGNUM
2704 && !fp_register_arg_p (typecode
, arg_type
))
2706 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2709 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2711 phex (regval
, MIPS_SAVED_REGSIZE
));
2712 write_register (argreg
, regval
);
2719 /* Compute the the offset into the stack at which we
2720 will copy the next parameter.
2722 In the new EABI (and the NABI32), the stack_offset
2723 only needs to be adjusted when it has been used. */
2726 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2730 fprintf_unfiltered (gdb_stdlog
, "\n");
2733 /* Return adjusted stack pointer. */
2737 /* N32/N64 version of push_arguments. */
2740 mips_n32n64_push_arguments (int nargs
,
2741 struct value
**args
,
2744 CORE_ADDR struct_addr
)
2750 int stack_offset
= 0;
2752 /* First ensure that the stack and structure return address (if any)
2753 are properly aligned. The stack has to be at least 64-bit
2754 aligned even on 32-bit machines, because doubles must be 64-bit
2755 aligned. For n32 and n64, stack frames need to be 128-bit
2756 aligned, so we round to this widest known alignment. */
2758 sp
= ROUND_DOWN (sp
, 16);
2759 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2761 /* Now make space on the stack for the args. */
2762 for (argnum
= 0; argnum
< nargs
; argnum
++)
2763 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2764 MIPS_STACK_ARGSIZE
);
2765 sp
-= ROUND_UP (len
, 16);
2768 fprintf_unfiltered (gdb_stdlog
,
2769 "mips_n32n64_push_arguments: sp=0x%s allocated %d\n",
2770 paddr_nz (sp
), ROUND_UP (len
, 16));
2772 /* Initialize the integer and float register pointers. */
2774 float_argreg
= FPA0_REGNUM
;
2776 /* The struct_return pointer occupies the first parameter-passing reg. */
2780 fprintf_unfiltered (gdb_stdlog
,
2781 "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n",
2782 argreg
, paddr_nz (struct_addr
));
2783 write_register (argreg
++, struct_addr
);
2786 /* Now load as many as possible of the first arguments into
2787 registers, and push the rest onto the stack. Loop thru args
2788 from first to last. */
2789 for (argnum
= 0; argnum
< nargs
; argnum
++)
2792 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
2793 struct value
*arg
= args
[argnum
];
2794 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2795 int len
= TYPE_LENGTH (arg_type
);
2796 enum type_code typecode
= TYPE_CODE (arg_type
);
2799 fprintf_unfiltered (gdb_stdlog
,
2800 "mips_n32n64_push_arguments: %d len=%d type=%d",
2801 argnum
+ 1, len
, (int) typecode
);
2803 val
= (char *) VALUE_CONTENTS (arg
);
2805 if (fp_register_arg_p (typecode
, arg_type
)
2806 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2808 /* This is a floating point value that fits entirely
2809 in a single register. */
2810 /* On 32 bit ABI's the float_argreg is further adjusted
2811 above to ensure that it is even register aligned. */
2812 LONGEST regval
= extract_unsigned_integer (val
, len
);
2814 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2815 float_argreg
, phex (regval
, len
));
2816 write_register (float_argreg
++, regval
);
2819 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2820 argreg
, phex (regval
, len
));
2821 write_register (argreg
, regval
);
2826 /* Copy the argument to general registers or the stack in
2827 register-sized pieces. Large arguments are split between
2828 registers and stack. */
2829 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2830 are treated specially: Irix cc passes them in registers
2831 where gcc sometimes puts them on the stack. For maximum
2832 compatibility, we will put them in both places. */
2833 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2834 (len
% MIPS_SAVED_REGSIZE
!= 0));
2835 /* Note: Floating-point values that didn't fit into an FP
2836 register are only written to memory. */
2839 /* Rememer if the argument was written to the stack. */
2840 int stack_used_p
= 0;
2841 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
2842 len
: MIPS_SAVED_REGSIZE
;
2845 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2848 /* Write this portion of the argument to the stack. */
2849 if (argreg
> MIPS_LAST_ARG_REGNUM
2851 || fp_register_arg_p (typecode
, arg_type
))
2853 /* Should shorter than int integer values be
2854 promoted to int before being stored? */
2855 int longword_offset
= 0;
2858 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2860 if (MIPS_STACK_ARGSIZE
== 8 &&
2861 (typecode
== TYPE_CODE_INT
||
2862 typecode
== TYPE_CODE_PTR
||
2863 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2864 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2865 else if ((typecode
== TYPE_CODE_STRUCT
||
2866 typecode
== TYPE_CODE_UNION
) &&
2867 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2868 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2873 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2874 paddr_nz (stack_offset
));
2875 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2876 paddr_nz (longword_offset
));
2879 addr
= sp
+ stack_offset
+ longword_offset
;
2884 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2886 for (i
= 0; i
< partial_len
; i
++)
2888 fprintf_unfiltered (gdb_stdlog
, "%02x",
2892 write_memory (addr
, val
, partial_len
);
2895 /* Note!!! This is NOT an else clause. Odd sized
2896 structs may go thru BOTH paths. Floating point
2897 arguments will not. */
2898 /* Write this portion of the argument to a general
2899 purpose register. */
2900 if (argreg
<= MIPS_LAST_ARG_REGNUM
2901 && !fp_register_arg_p (typecode
, arg_type
))
2903 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2905 /* A non-floating-point argument being passed in a
2906 general register. If a struct or union, and if
2907 the remaining length is smaller than the register
2908 size, we have to adjust the register value on
2911 It does not seem to be necessary to do the
2912 same for integral types.
2914 cagney/2001-07-23: gdb/179: Also, GCC, when
2915 outputting LE O32 with sizeof (struct) <
2916 MIPS_SAVED_REGSIZE, generates a left shift as
2917 part of storing the argument in a register a
2918 register (the left shift isn't generated when
2919 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2920 is quite possible that this is GCC contradicting
2921 the LE/O32 ABI, GDB has not been adjusted to
2922 accommodate this. Either someone needs to
2923 demonstrate that the LE/O32 ABI specifies such a
2924 left shift OR this new ABI gets identified as
2925 such and GDB gets tweaked accordingly. */
2927 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2928 && partial_len
< MIPS_SAVED_REGSIZE
2929 && (typecode
== TYPE_CODE_STRUCT
||
2930 typecode
== TYPE_CODE_UNION
))
2931 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2935 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2937 phex (regval
, MIPS_SAVED_REGSIZE
));
2938 write_register (argreg
, regval
);
2945 /* Compute the the offset into the stack at which we
2946 will copy the next parameter.
2948 In N32 (N64?), the stack_offset only needs to be
2949 adjusted when it has been used. */
2952 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2956 fprintf_unfiltered (gdb_stdlog
, "\n");
2959 /* Return adjusted stack pointer. */
2963 /* O32/O64 version of push_arguments. */
2966 mips_o32o64_push_arguments (int nargs
,
2967 struct value
**args
,
2970 CORE_ADDR struct_addr
)
2976 int stack_offset
= 0;
2978 /* First ensure that the stack and structure return address (if any)
2979 are properly aligned. The stack has to be at least 64-bit
2980 aligned even on 32-bit machines, because doubles must be 64-bit
2981 aligned. For n32 and n64, stack frames need to be 128-bit
2982 aligned, so we round to this widest known alignment. */
2984 sp
= ROUND_DOWN (sp
, 16);
2985 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2987 /* Now make space on the stack for the args. */
2988 for (argnum
= 0; argnum
< nargs
; argnum
++)
2989 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2990 MIPS_STACK_ARGSIZE
);
2991 sp
-= ROUND_UP (len
, 16);
2994 fprintf_unfiltered (gdb_stdlog
,
2995 "mips_o32o64_push_arguments: sp=0x%s allocated %d\n",
2996 paddr_nz (sp
), ROUND_UP (len
, 16));
2998 /* Initialize the integer and float register pointers. */
3000 float_argreg
= FPA0_REGNUM
;
3002 /* The struct_return pointer occupies the first parameter-passing reg. */
3006 fprintf_unfiltered (gdb_stdlog
,
3007 "mips_o32o64_push_arguments: struct_return reg=%d 0x%s\n",
3008 argreg
, paddr_nz (struct_addr
));
3009 write_register (argreg
++, struct_addr
);
3010 stack_offset
+= MIPS_STACK_ARGSIZE
;
3013 /* Now load as many as possible of the first arguments into
3014 registers, and push the rest onto the stack. Loop thru args
3015 from first to last. */
3016 for (argnum
= 0; argnum
< nargs
; argnum
++)
3019 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
3020 struct value
*arg
= args
[argnum
];
3021 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3022 int len
= TYPE_LENGTH (arg_type
);
3023 enum type_code typecode
= TYPE_CODE (arg_type
);
3026 fprintf_unfiltered (gdb_stdlog
,
3027 "mips_o32o64_push_arguments: %d len=%d type=%d",
3028 argnum
+ 1, len
, (int) typecode
);
3030 val
= (char *) VALUE_CONTENTS (arg
);
3032 /* 32-bit ABIs always start floating point arguments in an
3033 even-numbered floating point register. Round the FP register
3034 up before the check to see if there are any FP registers
3035 left. O32/O64 targets also pass the FP in the integer
3036 registers so also round up normal registers. */
3037 if (!FP_REGISTER_DOUBLE
3038 && fp_register_arg_p (typecode
, arg_type
))
3040 if ((float_argreg
& 1))
3044 /* Floating point arguments passed in registers have to be
3045 treated specially. On 32-bit architectures, doubles
3046 are passed in register pairs; the even register gets
3047 the low word, and the odd register gets the high word.
3048 On O32/O64, the first two floating point arguments are
3049 also copied to general registers, because MIPS16 functions
3050 don't use float registers for arguments. This duplication of
3051 arguments in general registers can't hurt non-MIPS16 functions
3052 because those registers are normally skipped. */
3054 if (fp_register_arg_p (typecode
, arg_type
)
3055 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3057 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3059 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3060 unsigned long regval
;
3062 /* Write the low word of the double to the even register(s). */
3063 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3065 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3066 float_argreg
, phex (regval
, 4));
3067 write_register (float_argreg
++, regval
);
3069 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3070 argreg
, phex (regval
, 4));
3071 write_register (argreg
++, regval
);
3073 /* Write the high word of the double to the odd register(s). */
3074 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3076 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3077 float_argreg
, phex (regval
, 4));
3078 write_register (float_argreg
++, regval
);
3081 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3082 argreg
, phex (regval
, 4));
3083 write_register (argreg
++, regval
);
3087 /* This is a floating point value that fits entirely
3088 in a single register. */
3089 /* On 32 bit ABI's the float_argreg is further adjusted
3090 above to ensure that it is even register aligned. */
3091 LONGEST regval
= extract_unsigned_integer (val
, len
);
3093 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3094 float_argreg
, phex (regval
, len
));
3095 write_register (float_argreg
++, regval
);
3096 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3097 registers for each argument. The below is (my
3098 guess) to ensure that the corresponding integer
3099 register has reserved the same space. */
3101 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3102 argreg
, phex (regval
, len
));
3103 write_register (argreg
, regval
);
3104 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3106 /* Reserve space for the FP register. */
3107 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
3111 /* Copy the argument to general registers or the stack in
3112 register-sized pieces. Large arguments are split between
3113 registers and stack. */
3114 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3115 are treated specially: Irix cc passes them in registers
3116 where gcc sometimes puts them on the stack. For maximum
3117 compatibility, we will put them in both places. */
3118 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3119 (len
% MIPS_SAVED_REGSIZE
!= 0));
3120 /* Structures should be aligned to eight bytes (even arg registers)
3121 on MIPS_ABI_O32, if their first member has double precision. */
3122 if (MIPS_SAVED_REGSIZE
< 8
3123 && mips_type_needs_double_align (arg_type
))
3128 /* Note: Floating-point values that didn't fit into an FP
3129 register are only written to memory. */
3132 /* Remember if the argument was written to the stack. */
3133 int stack_used_p
= 0;
3135 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3138 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3141 /* Write this portion of the argument to the stack. */
3142 if (argreg
> MIPS_LAST_ARG_REGNUM
3144 || fp_register_arg_p (typecode
, arg_type
))
3146 /* Should shorter than int integer values be
3147 promoted to int before being stored? */
3148 int longword_offset
= 0;
3151 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3153 if (MIPS_STACK_ARGSIZE
== 8 &&
3154 (typecode
== TYPE_CODE_INT
||
3155 typecode
== TYPE_CODE_PTR
||
3156 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3157 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3162 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3163 paddr_nz (stack_offset
));
3164 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3165 paddr_nz (longword_offset
));
3168 addr
= sp
+ stack_offset
+ longword_offset
;
3173 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3175 for (i
= 0; i
< partial_len
; i
++)
3177 fprintf_unfiltered (gdb_stdlog
, "%02x",
3181 write_memory (addr
, val
, partial_len
);
3184 /* Note!!! This is NOT an else clause. Odd sized
3185 structs may go thru BOTH paths. Floating point
3186 arguments will not. */
3187 /* Write this portion of the argument to a general
3188 purpose register. */
3189 if (argreg
<= MIPS_LAST_ARG_REGNUM
3190 && !fp_register_arg_p (typecode
, arg_type
))
3192 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3193 /* Value may need to be sign extended, because
3194 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3196 /* A non-floating-point argument being passed in a
3197 general register. If a struct or union, and if
3198 the remaining length is smaller than the register
3199 size, we have to adjust the register value on
3202 It does not seem to be necessary to do the
3203 same for integral types.
3205 Also don't do this adjustment on O64 binaries.
3207 cagney/2001-07-23: gdb/179: Also, GCC, when
3208 outputting LE O32 with sizeof (struct) <
3209 MIPS_SAVED_REGSIZE, generates a left shift as
3210 part of storing the argument in a register a
3211 register (the left shift isn't generated when
3212 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3213 is quite possible that this is GCC contradicting
3214 the LE/O32 ABI, GDB has not been adjusted to
3215 accommodate this. Either someone needs to
3216 demonstrate that the LE/O32 ABI specifies such a
3217 left shift OR this new ABI gets identified as
3218 such and GDB gets tweaked accordingly. */
3220 if (MIPS_SAVED_REGSIZE
< 8
3221 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3222 && partial_len
< MIPS_SAVED_REGSIZE
3223 && (typecode
== TYPE_CODE_STRUCT
||
3224 typecode
== TYPE_CODE_UNION
))
3225 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3229 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3231 phex (regval
, MIPS_SAVED_REGSIZE
));
3232 write_register (argreg
, regval
);
3235 /* Prevent subsequent floating point arguments from
3236 being passed in floating point registers. */
3237 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3243 /* Compute the the offset into the stack at which we
3244 will copy the next parameter.
3246 In older ABIs, the caller reserved space for
3247 registers that contained arguments. This was loosely
3248 refered to as their "home". Consequently, space is
3249 always allocated. */
3251 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3255 fprintf_unfiltered (gdb_stdlog
, "\n");
3258 /* Return adjusted stack pointer. */
3263 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
3265 /* Set the return address register to point to the entry
3266 point of the program, where a breakpoint lies in wait. */
3267 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
3272 mips_push_register (CORE_ADDR
* sp
, int regno
)
3274 char *buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
3277 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
3279 regsize
= MIPS_SAVED_REGSIZE
;
3280 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3281 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
3286 regsize
= REGISTER_RAW_SIZE (regno
);
3290 read_register_gen (regno
, buffer
);
3291 write_memory (*sp
, buffer
+ offset
, regsize
);
3294 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
3295 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
3298 mips_push_dummy_frame (void)
3301 struct linked_proc_info
*link
= (struct linked_proc_info
*)
3302 xmalloc (sizeof (struct linked_proc_info
));
3303 mips_extra_func_info_t proc_desc
= &link
->info
;
3304 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
3305 CORE_ADDR old_sp
= sp
;
3306 link
->next
= linked_proc_desc_table
;
3307 linked_proc_desc_table
= link
;
3309 /* FIXME! are these correct ? */
3310 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
3311 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
3312 #define FLOAT_REG_SAVE_MASK MASK(0,19)
3313 #define FLOAT_SINGLE_REG_SAVE_MASK \
3314 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
3316 * The registers we must save are all those not preserved across
3317 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
3318 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
3319 * and FP Control/Status registers.
3322 * Dummy frame layout:
3325 * Saved MMHI, MMLO, FPC_CSR
3330 * Saved D18 (i.e. F19, F18)
3332 * Saved D0 (i.e. F1, F0)
3333 * Argument build area and stack arguments written via mips_push_arguments
3337 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
3338 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
3339 PROC_FRAME_OFFSET (proc_desc
) = 0;
3340 PROC_FRAME_ADJUST (proc_desc
) = 0;
3341 mips_push_register (&sp
, PC_REGNUM
);
3342 mips_push_register (&sp
, HI_REGNUM
);
3343 mips_push_register (&sp
, LO_REGNUM
);
3344 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
3346 /* Save general CPU registers */
3347 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
3348 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
3349 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
3350 for (ireg
= 32; --ireg
>= 0;)
3351 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
3352 mips_push_register (&sp
, ireg
);
3354 /* Save floating point registers starting with high order word */
3355 PROC_FREG_MASK (proc_desc
) =
3356 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
3357 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
3358 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
3360 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
3361 for (ireg
= 32; --ireg
>= 0;)
3362 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
3363 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
3365 /* Update the frame pointer for the call dummy and the stack pointer.
3366 Set the procedure's starting and ending addresses to point to the
3367 call dummy address at the entry point. */
3368 write_register (PUSH_FP_REGNUM
, old_sp
);
3369 write_register (SP_REGNUM
, sp
);
3370 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
3371 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
3372 SET_PROC_DESC_IS_DUMMY (proc_desc
);
3373 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
3377 mips_pop_frame (void)
3379 register int regnum
;
3380 struct frame_info
*frame
= get_current_frame ();
3381 CORE_ADDR new_sp
= FRAME_FP (frame
);
3383 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
3385 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
3386 if (frame
->saved_regs
== NULL
)
3387 FRAME_INIT_SAVED_REGS (frame
);
3388 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3390 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3391 && frame
->saved_regs
[regnum
])
3392 write_register (regnum
,
3393 read_memory_integer (frame
->saved_regs
[regnum
],
3394 MIPS_SAVED_REGSIZE
));
3396 write_register (SP_REGNUM
, new_sp
);
3397 flush_cached_frames ();
3399 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3401 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3403 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3405 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3407 if (&pi_ptr
->info
== proc_desc
)
3412 error ("Can't locate dummy extra frame info\n");
3414 if (prev_ptr
!= NULL
)
3415 prev_ptr
->next
= pi_ptr
->next
;
3417 linked_proc_desc_table
= pi_ptr
->next
;
3421 write_register (HI_REGNUM
,
3422 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3423 MIPS_SAVED_REGSIZE
));
3424 write_register (LO_REGNUM
,
3425 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3426 MIPS_SAVED_REGSIZE
));
3427 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3428 write_register (FCRCS_REGNUM
,
3429 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3430 MIPS_SAVED_REGSIZE
));
3434 /* Floating point register management.
3436 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3437 64bit operations, these early MIPS cpus treat fp register pairs
3438 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3439 registers and offer a compatibility mode that emulates the MIPS2 fp
3440 model. When operating in MIPS2 fp compat mode, later cpu's split
3441 double precision floats into two 32-bit chunks and store them in
3442 consecutive fp regs. To display 64-bit floats stored in this
3443 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3444 Throw in user-configurable endianness and you have a real mess.
3446 The way this works is:
3447 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3448 double-precision value will be split across two logical registers.
3449 The lower-numbered logical register will hold the low-order bits,
3450 regardless of the processor's endianness.
3451 - If we are on a 64-bit processor, and we are looking for a
3452 single-precision value, it will be in the low ordered bits
3453 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3454 save slot in memory.
3455 - If we are in 64-bit mode, everything is straightforward.
3457 Note that this code only deals with "live" registers at the top of the
3458 stack. We will attempt to deal with saved registers later, when
3459 the raw/cooked register interface is in place. (We need a general
3460 interface that can deal with dynamic saved register sizes -- fp
3461 regs could be 32 bits wide in one frame and 64 on the frame above
3464 static struct type
*
3465 mips_float_register_type (void)
3467 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3468 return builtin_type_ieee_single_big
;
3470 return builtin_type_ieee_single_little
;
3473 static struct type
*
3474 mips_double_register_type (void)
3476 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3477 return builtin_type_ieee_double_big
;
3479 return builtin_type_ieee_double_little
;
3482 /* Copy a 32-bit single-precision value from the current frame
3483 into rare_buffer. */
3486 mips_read_fp_register_single (int regno
, char *rare_buffer
)
3488 int raw_size
= REGISTER_RAW_SIZE (regno
);
3489 char *raw_buffer
= alloca (raw_size
);
3491 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
3492 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3495 /* We have a 64-bit value for this register. Find the low-order
3499 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3504 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3508 memcpy (rare_buffer
, raw_buffer
, 4);
3512 /* Copy a 64-bit double-precision value from the current frame into
3513 rare_buffer. This may include getting half of it from the next
3517 mips_read_fp_register_double (int regno
, char *rare_buffer
)
3519 int raw_size
= REGISTER_RAW_SIZE (regno
);
3521 if (raw_size
== 8 && !mips2_fp_compat ())
3523 /* We have a 64-bit value for this register, and we should use
3525 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
3526 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3530 if ((regno
- FP0_REGNUM
) & 1)
3531 internal_error (__FILE__
, __LINE__
,
3532 "mips_read_fp_register_double: bad access to "
3533 "odd-numbered FP register");
3535 /* mips_read_fp_register_single will find the correct 32 bits from
3537 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3539 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
3540 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
3544 mips_read_fp_register_single (regno
, rare_buffer
);
3545 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
3551 mips_print_register (int regnum
, int all
)
3553 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
3555 /* Get the data in raw format. */
3556 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3558 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
3562 /* If we have a actual 32-bit floating point register (or we are in
3563 32-bit compatibility mode), and the register is even-numbered,
3564 also print it as a double (spanning two registers). */
3565 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
3566 && (REGISTER_RAW_SIZE (regnum
) == 4
3567 || mips2_fp_compat ())
3568 && !((regnum
- FP0_REGNUM
) & 1))
3570 char *dbuffer
= alloca (2 * MAX_REGISTER_RAW_SIZE
);
3572 mips_read_fp_register_double (regnum
, dbuffer
);
3574 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
3575 val_print (mips_double_register_type (), dbuffer
, 0, 0,
3576 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3577 printf_filtered ("); ");
3579 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3581 /* The problem with printing numeric register names (r26, etc.) is that
3582 the user can't use them on input. Probably the best solution is to
3583 fix it so that either the numeric or the funky (a2, etc.) names
3584 are accepted on input. */
3585 if (regnum
< MIPS_NUMREGS
)
3586 printf_filtered ("(r%d): ", regnum
);
3588 printf_filtered (": ");
3590 /* If virtual format is floating, print it that way. */
3591 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3592 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
3594 /* We have a meaningful 64-bit value in this register. Show
3595 it as a 32-bit float and a 64-bit double. */
3596 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
3598 printf_filtered (" (float) ");
3599 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
3600 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3601 printf_filtered (", (double) ");
3602 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
3603 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3606 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
3607 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3608 /* Else print as integer in hex. */
3613 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3614 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3618 print_scalar_formatted (raw_buffer
+ offset
,
3619 REGISTER_VIRTUAL_TYPE (regnum
),
3620 'x', 0, gdb_stdout
);
3624 /* Replacement for generic do_registers_info.
3625 Print regs in pretty columns. */
3628 do_fp_register_row (int regnum
)
3629 { /* do values for FP (float) regs */
3631 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
3632 int inv1
, inv2
, inv3
;
3634 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
3636 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
3638 /* 4-byte registers: we can fit two registers per row. */
3639 /* Also print every pair of 4-byte regs as an 8-byte double. */
3640 mips_read_fp_register_single (regnum
, raw_buffer
);
3641 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3643 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
3644 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
3646 mips_read_fp_register_double (regnum
, raw_buffer
);
3647 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3649 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
3651 printf_filtered (": <invalid float>");
3653 printf_filtered ("%-17.9g", flt1
);
3655 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
3657 printf_filtered (": <invalid float>");
3659 printf_filtered ("%-17.9g", flt2
);
3661 printf_filtered (" dbl: ");
3663 printf_filtered ("<invalid double>");
3665 printf_filtered ("%-24.17g", doub
);
3666 printf_filtered ("\n");
3668 /* may want to do hex display here (future enhancement) */
3673 /* Eight byte registers: print each one as float AND as double. */
3674 mips_read_fp_register_single (regnum
, raw_buffer
);
3675 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
3677 mips_read_fp_register_double (regnum
, raw_buffer
);
3678 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3680 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
3682 printf_filtered ("<invalid float>");
3684 printf_filtered ("flt: %-17.9g", flt1
);
3686 printf_filtered (" dbl: ");
3688 printf_filtered ("<invalid double>");
3690 printf_filtered ("%-24.17g", doub
);
3692 printf_filtered ("\n");
3693 /* may want to do hex display here (future enhancement) */
3699 /* Print a row's worth of GP (int) registers, with name labels above */
3702 do_gp_register_row (int regnum
)
3704 /* do values for GP (int) regs */
3705 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
3706 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
3708 int start_regnum
= regnum
;
3709 int numregs
= NUM_REGS
;
3712 /* For GP registers, we print a separate row of names above the vals */
3713 printf_filtered (" ");
3714 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3716 if (*REGISTER_NAME (regnum
) == '\0')
3717 continue; /* unused register */
3718 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3719 break; /* end the row: reached FP register */
3720 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
3721 REGISTER_NAME (regnum
));
3724 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
3725 start_regnum
); /* print the R0 to R31 names */
3727 regnum
= start_regnum
; /* go back to start of row */
3728 /* now print the values in hex, 4 or 8 to the row */
3729 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3731 if (*REGISTER_NAME (regnum
) == '\0')
3732 continue; /* unused register */
3733 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3734 break; /* end row: reached FP register */
3735 /* OK: get the data in raw format. */
3736 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3737 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3738 /* pad small registers */
3739 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
3740 printf_filtered (" ");
3741 /* Now print the register value in hex, endian order. */
3742 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3743 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3744 byte
< REGISTER_RAW_SIZE (regnum
);
3746 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3748 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
3751 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3752 printf_filtered (" ");
3755 if (col
> 0) /* ie. if we actually printed anything... */
3756 printf_filtered ("\n");
3761 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3764 mips_do_registers_info (int regnum
, int fpregs
)
3766 if (regnum
!= -1) /* do one specified register */
3768 if (*(REGISTER_NAME (regnum
)) == '\0')
3769 error ("Not a valid register for the current processor type");
3771 mips_print_register (regnum
, 0);
3772 printf_filtered ("\n");
3775 /* do all (or most) registers */
3778 while (regnum
< NUM_REGS
)
3780 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3781 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
3782 regnum
= do_fp_register_row (regnum
); /* FP regs */
3784 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
3786 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
3791 /* Return number of args passed to a frame. described by FIP.
3792 Can return -1, meaning no way to tell. */
3795 mips_frame_num_args (struct frame_info
*frame
)
3800 /* Is this a branch with a delay slot? */
3802 static int is_delayed (unsigned long);
3805 is_delayed (unsigned long insn
)
3808 for (i
= 0; i
< NUMOPCODES
; ++i
)
3809 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
3810 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
3812 return (i
< NUMOPCODES
3813 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
3814 | INSN_COND_BRANCH_DELAY
3815 | INSN_COND_BRANCH_LIKELY
)));
3819 mips_step_skips_delay (CORE_ADDR pc
)
3821 char buf
[MIPS_INSTLEN
];
3823 /* There is no branch delay slot on MIPS16. */
3824 if (pc_is_mips16 (pc
))
3827 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
3828 /* If error reading memory, guess that it is not a delayed branch. */
3830 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
3834 /* Skip the PC past function prologue instructions (32-bit version).
3835 This is a helper function for mips_skip_prologue. */
3838 mips32_skip_prologue (CORE_ADDR pc
)
3842 int seen_sp_adjust
= 0;
3843 int load_immediate_bytes
= 0;
3845 /* Skip the typical prologue instructions. These are the stack adjustment
3846 instruction and the instructions that save registers on the stack
3847 or in the gcc frame. */
3848 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
3850 unsigned long high_word
;
3852 inst
= mips_fetch_instruction (pc
);
3853 high_word
= (inst
>> 16) & 0xffff;
3855 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
3856 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
3858 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
3859 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
3861 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3862 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3863 && (inst
& 0x001F0000)) /* reg != $zero */
3866 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3868 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
3870 continue; /* reg != $zero */
3872 /* move $s8,$sp. With different versions of gas this will be either
3873 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3874 Accept any one of these. */
3875 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3878 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3880 else if (high_word
== 0x3c1c) /* lui $gp,n */
3882 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
3884 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3885 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
3887 /* The following instructions load $at or $t0 with an immediate
3888 value in preparation for a stack adjustment via
3889 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3890 a local variable, so we accept them only before a stack adjustment
3891 instruction was seen. */
3892 else if (!seen_sp_adjust
)
3894 if (high_word
== 0x3c01 || /* lui $at,n */
3895 high_word
== 0x3c08) /* lui $t0,n */
3897 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3900 else if (high_word
== 0x3421 || /* ori $at,$at,n */
3901 high_word
== 0x3508 || /* ori $t0,$t0,n */
3902 high_word
== 0x3401 || /* ori $at,$zero,n */
3903 high_word
== 0x3408) /* ori $t0,$zero,n */
3905 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3915 /* In a frameless function, we might have incorrectly
3916 skipped some load immediate instructions. Undo the skipping
3917 if the load immediate was not followed by a stack adjustment. */
3918 if (load_immediate_bytes
&& !seen_sp_adjust
)
3919 pc
-= load_immediate_bytes
;
3923 /* Skip the PC past function prologue instructions (16-bit version).
3924 This is a helper function for mips_skip_prologue. */
3927 mips16_skip_prologue (CORE_ADDR pc
)
3930 int extend_bytes
= 0;
3931 int prev_extend_bytes
;
3933 /* Table of instructions likely to be found in a function prologue. */
3936 unsigned short inst
;
3937 unsigned short mask
;
3944 , /* addiu $sp,offset */
3948 , /* daddiu $sp,offset */
3952 , /* sw reg,n($sp) */
3956 , /* sd reg,n($sp) */
3960 , /* sw $ra,n($sp) */
3964 , /* sd $ra,n($sp) */
3972 , /* sw $a0-$a3,n($s1) */
3976 , /* move reg,$a0-$a3 */
3980 , /* entry pseudo-op */
3984 , /* addiu $s1,$sp,n */
3987 } /* end of table marker */
3990 /* Skip the typical prologue instructions. These are the stack adjustment
3991 instruction and the instructions that save registers on the stack
3992 or in the gcc frame. */
3993 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3995 unsigned short inst
;
3998 inst
= mips_fetch_instruction (pc
);
4000 /* Normally we ignore an extend instruction. However, if it is
4001 not followed by a valid prologue instruction, we must adjust
4002 the pc back over the extend so that it won't be considered
4003 part of the prologue. */
4004 if ((inst
& 0xf800) == 0xf000) /* extend */
4006 extend_bytes
= MIPS16_INSTLEN
;
4009 prev_extend_bytes
= extend_bytes
;
4012 /* Check for other valid prologue instructions besides extend. */
4013 for (i
= 0; table
[i
].mask
!= 0; i
++)
4014 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4016 if (table
[i
].mask
!= 0) /* it was in table? */
4017 continue; /* ignore it */
4021 /* Return the current pc, adjusted backwards by 2 if
4022 the previous instruction was an extend. */
4023 return pc
- prev_extend_bytes
;
4029 /* To skip prologues, I use this predicate. Returns either PC itself
4030 if the code at PC does not look like a function prologue; otherwise
4031 returns an address that (if we're lucky) follows the prologue. If
4032 LENIENT, then we must skip everything which is involved in setting
4033 up the frame (it's OK to skip more, just so long as we don't skip
4034 anything which might clobber the registers which are being saved.
4035 We must skip more in the case where part of the prologue is in the
4036 delay slot of a non-prologue instruction). */
4039 mips_skip_prologue (CORE_ADDR pc
)
4041 /* See if we can determine the end of the prologue via the symbol table.
4042 If so, then return either PC, or the PC after the prologue, whichever
4045 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4047 if (post_prologue_pc
!= 0)
4048 return max (pc
, post_prologue_pc
);
4050 /* Can't determine prologue from the symbol table, need to examine
4053 if (pc_is_mips16 (pc
))
4054 return mips16_skip_prologue (pc
);
4056 return mips32_skip_prologue (pc
);
4059 /* Determine how a return value is stored within the MIPS register
4060 file, given the return type `valtype'. */
4062 struct return_value_word
4071 return_value_location (struct type
*valtype
,
4072 struct return_value_word
*hi
,
4073 struct return_value_word
*lo
)
4075 int len
= TYPE_LENGTH (valtype
);
4077 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4078 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4079 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4081 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4083 /* We need to break a 64bit float in two 32 bit halves and
4084 spread them across a floating-point register pair. */
4085 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4086 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4087 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4088 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
4090 hi
->reg_offset
= lo
->reg_offset
;
4091 lo
->reg
= FP0_REGNUM
+ 0;
4092 hi
->reg
= FP0_REGNUM
+ 1;
4098 /* The floating point value fits in a single floating-point
4100 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4101 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
4104 lo
->reg
= FP0_REGNUM
;
4115 /* Locate a result possibly spread across two registers. */
4117 lo
->reg
= regnum
+ 0;
4118 hi
->reg
= regnum
+ 1;
4119 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4120 && len
< MIPS_SAVED_REGSIZE
)
4122 /* "un-left-justify" the value in the low register */
4123 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4128 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4129 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4130 && len
< MIPS_SAVED_REGSIZE
* 2
4131 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4132 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4134 /* "un-left-justify" the value spread across two registers. */
4135 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4136 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4138 hi
->len
= len
- lo
->len
;
4142 /* Only perform a partial copy of the second register. */
4145 if (len
> MIPS_SAVED_REGSIZE
)
4147 lo
->len
= MIPS_SAVED_REGSIZE
;
4148 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4156 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4157 && REGISTER_RAW_SIZE (regnum
) == 8
4158 && MIPS_SAVED_REGSIZE
== 4)
4160 /* Account for the fact that only the least-signficant part
4161 of the register is being used */
4162 lo
->reg_offset
+= 4;
4163 hi
->reg_offset
+= 4;
4166 hi
->buf_offset
= lo
->len
;
4170 /* Given a return value in `regbuf' with a type `valtype', extract and
4171 copy its value into `valbuf'. */
4174 mips_extract_return_value (struct type
*valtype
,
4175 char regbuf
[REGISTER_BYTES
],
4178 struct return_value_word lo
;
4179 struct return_value_word hi
;
4180 return_value_location (valtype
, &hi
, &lo
);
4182 memcpy (valbuf
+ lo
.buf_offset
,
4183 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4187 memcpy (valbuf
+ hi
.buf_offset
,
4188 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4192 /* Given a return value in `valbuf' with a type `valtype', write it's
4193 value into the appropriate register. */
4196 mips_store_return_value (struct type
*valtype
, char *valbuf
)
4198 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4199 struct return_value_word lo
;
4200 struct return_value_word hi
;
4201 return_value_location (valtype
, &hi
, &lo
);
4203 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4204 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4205 write_register_bytes (REGISTER_BYTE (lo
.reg
),
4207 REGISTER_RAW_SIZE (lo
.reg
));
4211 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4212 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4213 write_register_bytes (REGISTER_BYTE (hi
.reg
),
4215 REGISTER_RAW_SIZE (hi
.reg
));
4219 /* Exported procedure: Is PC in the signal trampoline code */
4222 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
4224 if (sigtramp_address
== 0)
4226 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
4229 /* Root of all "set mips "/"show mips " commands. This will eventually be
4230 used for all MIPS-specific commands. */
4233 show_mips_command (char *args
, int from_tty
)
4235 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4239 set_mips_command (char *args
, int from_tty
)
4241 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
4242 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4245 /* Commands to show/set the MIPS FPU type. */
4248 show_mipsfpu_command (char *args
, int from_tty
)
4251 switch (MIPS_FPU_TYPE
)
4253 case MIPS_FPU_SINGLE
:
4254 fpu
= "single-precision";
4256 case MIPS_FPU_DOUBLE
:
4257 fpu
= "double-precision";
4260 fpu
= "absent (none)";
4263 internal_error (__FILE__
, __LINE__
, "bad switch");
4265 if (mips_fpu_type_auto
)
4266 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4269 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
4275 set_mipsfpu_command (char *args
, int from_tty
)
4277 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4278 show_mipsfpu_command (args
, from_tty
);
4282 set_mipsfpu_single_command (char *args
, int from_tty
)
4284 mips_fpu_type
= MIPS_FPU_SINGLE
;
4285 mips_fpu_type_auto
= 0;
4286 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
4290 set_mipsfpu_double_command (char *args
, int from_tty
)
4292 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4293 mips_fpu_type_auto
= 0;
4294 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4298 set_mipsfpu_none_command (char *args
, int from_tty
)
4300 mips_fpu_type
= MIPS_FPU_NONE
;
4301 mips_fpu_type_auto
= 0;
4302 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
4306 set_mipsfpu_auto_command (char *args
, int from_tty
)
4308 mips_fpu_type_auto
= 1;
4311 /* Command to set the processor type. */
4314 mips_set_processor_type_command (char *args
, int from_tty
)
4318 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
4320 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
4321 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
4322 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
4324 /* Restore the value. */
4325 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
4330 if (!mips_set_processor_type (tmp_mips_processor_type
))
4332 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
4333 /* Restore its value. */
4334 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
4339 mips_show_processor_type_command (char *args
, int from_tty
)
4343 /* Modify the actual processor type. */
4346 mips_set_processor_type (char *str
)
4353 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
4355 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
4357 mips_processor_type
= str
;
4358 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
4360 /* FIXME tweak fpu flag too */
4367 /* Attempt to identify the particular processor model by reading the
4371 mips_read_processor_type (void)
4375 prid
= read_register (PRID_REGNUM
);
4377 if ((prid
& ~0xf) == 0x700)
4378 return savestring ("r3041", strlen ("r3041"));
4383 /* Just like reinit_frame_cache, but with the right arguments to be
4384 callable as an sfunc. */
4387 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4388 struct cmd_list_element
*c
)
4390 reinit_frame_cache ();
4394 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
4396 mips_extra_func_info_t proc_desc
;
4398 /* Search for the function containing this address. Set the low bit
4399 of the address when searching, in case we were given an even address
4400 that is the start of a 16-bit function. If we didn't do this,
4401 the search would fail because the symbol table says the function
4402 starts at an odd address, i.e. 1 byte past the given address. */
4403 memaddr
= ADDR_BITS_REMOVE (memaddr
);
4404 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
4406 /* Make an attempt to determine if this is a 16-bit function. If
4407 the procedure descriptor exists and the address therein is odd,
4408 it's definitely a 16-bit function. Otherwise, we have to just
4409 guess that if the address passed in is odd, it's 16-bits. */
4411 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
4412 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
4414 info
->mach
= pc_is_mips16 (memaddr
) ?
4415 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
4417 /* Round down the instruction address to the appropriate boundary. */
4418 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4420 /* Call the appropriate disassembler based on the target endian-ness. */
4421 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4422 return print_insn_big_mips (memaddr
, info
);
4424 return print_insn_little_mips (memaddr
, info
);
4427 /* Old-style breakpoint macros.
4428 The IDT board uses an unusual breakpoint value, and sometimes gets
4429 confused when it sees the usual MIPS breakpoint instruction. */
4431 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
4432 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
4433 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
4434 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
4435 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
4436 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
4437 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
4438 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
4440 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4441 counter value to determine whether a 16- or 32-bit breakpoint should be
4442 used. It returns a pointer to a string of bytes that encode a breakpoint
4443 instruction, stores the length of the string to *lenptr, and adjusts pc
4444 (if necessary) to point to the actual memory location where the
4445 breakpoint should be inserted. */
4447 const unsigned char *
4448 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
4450 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4452 if (pc_is_mips16 (*pcptr
))
4454 static unsigned char mips16_big_breakpoint
[] =
4455 MIPS16_BIG_BREAKPOINT
;
4456 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
4457 *lenptr
= sizeof (mips16_big_breakpoint
);
4458 return mips16_big_breakpoint
;
4462 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
4463 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
4464 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
4466 *lenptr
= sizeof (big_breakpoint
);
4468 if (strcmp (target_shortname
, "mips") == 0)
4469 return idt_big_breakpoint
;
4470 else if (strcmp (target_shortname
, "ddb") == 0
4471 || strcmp (target_shortname
, "pmon") == 0
4472 || strcmp (target_shortname
, "lsi") == 0)
4473 return pmon_big_breakpoint
;
4475 return big_breakpoint
;
4480 if (pc_is_mips16 (*pcptr
))
4482 static unsigned char mips16_little_breakpoint
[] =
4483 MIPS16_LITTLE_BREAKPOINT
;
4484 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
4485 *lenptr
= sizeof (mips16_little_breakpoint
);
4486 return mips16_little_breakpoint
;
4490 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
4491 static unsigned char pmon_little_breakpoint
[] =
4492 PMON_LITTLE_BREAKPOINT
;
4493 static unsigned char idt_little_breakpoint
[] =
4494 IDT_LITTLE_BREAKPOINT
;
4496 *lenptr
= sizeof (little_breakpoint
);
4498 if (strcmp (target_shortname
, "mips") == 0)
4499 return idt_little_breakpoint
;
4500 else if (strcmp (target_shortname
, "ddb") == 0
4501 || strcmp (target_shortname
, "pmon") == 0
4502 || strcmp (target_shortname
, "lsi") == 0)
4503 return pmon_little_breakpoint
;
4505 return little_breakpoint
;
4510 /* If PC is in a mips16 call or return stub, return the address of the target
4511 PC, which is either the callee or the caller. There are several
4512 cases which must be handled:
4514 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4515 target PC is in $31 ($ra).
4516 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4517 and the target PC is in $2.
4518 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4519 before the jal instruction, this is effectively a call stub
4520 and the the target PC is in $2. Otherwise this is effectively
4521 a return stub and the target PC is in $18.
4523 See the source code for the stubs in gcc/config/mips/mips16.S for
4526 This function implements the SKIP_TRAMPOLINE_CODE macro.
4530 mips_skip_stub (CORE_ADDR pc
)
4533 CORE_ADDR start_addr
;
4535 /* Find the starting address and name of the function containing the PC. */
4536 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4539 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4540 target PC is in $31 ($ra). */
4541 if (strcmp (name
, "__mips16_ret_sf") == 0
4542 || strcmp (name
, "__mips16_ret_df") == 0)
4543 return read_signed_register (RA_REGNUM
);
4545 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4547 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4548 and the target PC is in $2. */
4549 if (name
[19] >= '0' && name
[19] <= '9')
4550 return read_signed_register (2);
4552 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4553 before the jal instruction, this is effectively a call stub
4554 and the the target PC is in $2. Otherwise this is effectively
4555 a return stub and the target PC is in $18. */
4556 else if (name
[19] == 's' || name
[19] == 'd')
4558 if (pc
== start_addr
)
4560 /* Check if the target of the stub is a compiler-generated
4561 stub. Such a stub for a function bar might have a name
4562 like __fn_stub_bar, and might look like this:
4567 la $1,bar (becomes a lui/addiu pair)
4569 So scan down to the lui/addi and extract the target
4570 address from those two instructions. */
4572 CORE_ADDR target_pc
= read_signed_register (2);
4576 /* See if the name of the target function is __fn_stub_*. */
4577 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
4579 if (strncmp (name
, "__fn_stub_", 10) != 0
4580 && strcmp (name
, "etext") != 0
4581 && strcmp (name
, "_etext") != 0)
4584 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4585 The limit on the search is arbitrarily set to 20
4586 instructions. FIXME. */
4587 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
4589 inst
= mips_fetch_instruction (target_pc
);
4590 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4591 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4592 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4593 return pc
| (inst
& 0xffff); /* low word */
4596 /* Couldn't find the lui/addui pair, so return stub address. */
4600 /* This is the 'return' part of a call stub. The return
4601 address is in $r18. */
4602 return read_signed_register (18);
4605 return 0; /* not a stub */
4609 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
4610 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4613 mips_in_call_stub (CORE_ADDR pc
, char *name
)
4615 CORE_ADDR start_addr
;
4617 /* Find the starting address of the function containing the PC. If the
4618 caller didn't give us a name, look it up at the same time. */
4619 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
4622 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4624 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4625 if (name
[19] >= '0' && name
[19] <= '9')
4627 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4628 before the jal instruction, this is effectively a call stub. */
4629 else if (name
[19] == 's' || name
[19] == 'd')
4630 return pc
== start_addr
;
4633 return 0; /* not a stub */
4637 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
4638 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
4641 mips_in_return_stub (CORE_ADDR pc
, char *name
)
4643 CORE_ADDR start_addr
;
4645 /* Find the starting address of the function containing the PC. */
4646 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
4649 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4650 if (strcmp (name
, "__mips16_ret_sf") == 0
4651 || strcmp (name
, "__mips16_ret_df") == 0)
4654 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4655 i.e. after the jal instruction, this is effectively a return stub. */
4656 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
4657 && (name
[19] == 's' || name
[19] == 'd')
4658 && pc
!= start_addr
)
4661 return 0; /* not a stub */
4665 /* Return non-zero if the PC is in a library helper function that should
4666 be ignored. This implements the IGNORE_HELPER_CALL macro. */
4669 mips_ignore_helper (CORE_ADDR pc
)
4673 /* Find the starting address and name of the function containing the PC. */
4674 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
4677 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4678 that we want to ignore. */
4679 return (strcmp (name
, "__mips16_ret_sf") == 0
4680 || strcmp (name
, "__mips16_ret_df") == 0);
4684 /* Return a location where we can set a breakpoint that will be hit
4685 when an inferior function call returns. This is normally the
4686 program's entry point. Executables that don't have an entry
4687 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
4688 whose address is the location where the breakpoint should be placed. */
4691 mips_call_dummy_address (void)
4693 struct minimal_symbol
*sym
;
4695 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
4697 return SYMBOL_VALUE_ADDRESS (sym
);
4699 return entry_point_address ();
4703 /* If the current gcc for this target does not produce correct debugging
4704 information for float parameters, both prototyped and unprototyped, then
4705 define this macro. This forces gdb to always assume that floats are
4706 passed as doubles and then converted in the callee.
4708 For the mips chip, it appears that the debug info marks the parameters as
4709 floats regardless of whether the function is prototyped, but the actual
4710 values are passed as doubles for the non-prototyped case and floats for
4711 the prototyped case. Thus we choose to make the non-prototyped case work
4712 for C and break the prototyped case, since the non-prototyped case is
4713 probably much more common. (FIXME). */
4716 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
4718 return current_language
->la_language
== language_c
;
4721 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4722 the register stored on the stack (32) is different to its real raw
4723 size (64). The below ensures that registers are fetched from the
4724 stack using their ABI size and then stored into the RAW_BUFFER
4725 using their raw size.
4727 The alternative to adding this function would be to add an ABI
4728 macro - REGISTER_STACK_SIZE(). */
4731 mips_get_saved_register (char *raw_buffer
,
4734 struct frame_info
*frame
,
4736 enum lval_type
*lval
)
4740 if (!target_has_registers
)
4741 error ("No registers.");
4743 /* Normal systems don't optimize out things with register numbers. */
4744 if (optimized
!= NULL
)
4746 addr
= find_saved_register (frame
, regnum
);
4750 *lval
= lval_memory
;
4751 if (regnum
== SP_REGNUM
)
4753 if (raw_buffer
!= NULL
)
4755 /* Put it back in target format. */
4756 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
4763 if (raw_buffer
!= NULL
)
4767 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4769 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
4771 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
4772 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
4778 *lval
= lval_register
;
4779 addr
= REGISTER_BYTE (regnum
);
4780 if (raw_buffer
!= NULL
)
4781 read_register_gen (regnum
, raw_buffer
);
4787 /* Immediately after a function call, return the saved pc.
4788 Can't always go through the frames for this because on some machines
4789 the new frame is not set up until the new function executes
4790 some instructions. */
4793 mips_saved_pc_after_call (struct frame_info
*frame
)
4795 return read_signed_register (RA_REGNUM
);
4799 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4803 mips_stab_reg_to_regnum (int num
)
4808 return num
+ FP0_REGNUM
- 38;
4811 /* Convert a ecoff register number to a gdb REGNUM */
4814 mips_ecoff_reg_to_regnum (int num
)
4819 return num
+ FP0_REGNUM
- 32;
4822 /* Convert an integer into an address. By first converting the value
4823 into a pointer and then extracting it signed, the address is
4824 guarenteed to be correctly sign extended. */
4827 mips_integer_to_address (struct type
*type
, void *buf
)
4829 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4830 LONGEST val
= unpack_long (type
, buf
);
4831 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4832 return extract_signed_integer (tmp
,
4833 TYPE_LENGTH (builtin_type_void_data_ptr
));
4837 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4839 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4840 const char *name
= bfd_get_section_name (abfd
, sect
);
4842 if (*abip
!= MIPS_ABI_UNKNOWN
)
4845 if (strncmp (name
, ".mdebug.", 8) != 0)
4848 if (strcmp (name
, ".mdebug.abi32") == 0)
4849 *abip
= MIPS_ABI_O32
;
4850 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4851 *abip
= MIPS_ABI_N32
;
4852 else if (strcmp (name
, ".mdebug.abiN64") == 0)
4853 *abip
= MIPS_ABI_N64
;
4854 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4855 *abip
= MIPS_ABI_O64
;
4856 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4857 *abip
= MIPS_ABI_EABI32
;
4858 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4859 *abip
= MIPS_ABI_EABI64
;
4861 warning ("unsupported ABI %s.", name
+ 8);
4864 static enum mips_abi
4865 global_mips_abi (void)
4869 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4870 if (mips_abi_strings
[i
] == mips_abi_string
)
4871 return (enum mips_abi
) i
;
4873 internal_error (__FILE__
, __LINE__
,
4874 "unknown ABI string");
4877 static struct gdbarch
*
4878 mips_gdbarch_init (struct gdbarch_info info
,
4879 struct gdbarch_list
*arches
)
4881 static LONGEST mips_call_dummy_words
[] =
4883 struct gdbarch
*gdbarch
;
4884 struct gdbarch_tdep
*tdep
;
4886 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4887 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
4889 /* Reset the disassembly info, in case it was set to something
4891 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
4892 tm_print_insn_info
.arch
= bfd_arch_unknown
;
4893 tm_print_insn_info
.mach
= 0;
4899 /* First of all, extract the elf_flags, if available. */
4900 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4901 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4903 /* Try to determine the OS ABI of the object we are loading. If
4904 we end up with `unknown', just leave it that way. */
4905 osabi
= gdbarch_lookup_osabi (info
.abfd
);
4908 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4909 switch ((elf_flags
& EF_MIPS_ABI
))
4911 case E_MIPS_ABI_O32
:
4912 mips_abi
= MIPS_ABI_O32
;
4914 case E_MIPS_ABI_O64
:
4915 mips_abi
= MIPS_ABI_O64
;
4917 case E_MIPS_ABI_EABI32
:
4918 mips_abi
= MIPS_ABI_EABI32
;
4920 case E_MIPS_ABI_EABI64
:
4921 mips_abi
= MIPS_ABI_EABI64
;
4924 if ((elf_flags
& EF_MIPS_ABI2
))
4925 mips_abi
= MIPS_ABI_N32
;
4927 mips_abi
= MIPS_ABI_UNKNOWN
;
4931 /* GCC creates a pseudo-section whose name describes the ABI. */
4932 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4933 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
4935 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
4936 Use the ABI from the last architecture if there is one. */
4937 if (info
.abfd
== NULL
&& arches
!= NULL
)
4938 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4940 /* Try the architecture for any hint of the correct ABI. */
4941 if (mips_abi
== MIPS_ABI_UNKNOWN
4942 && info
.bfd_arch_info
!= NULL
4943 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4945 switch (info
.bfd_arch_info
->mach
)
4947 case bfd_mach_mips3900
:
4948 mips_abi
= MIPS_ABI_EABI32
;
4950 case bfd_mach_mips4100
:
4951 case bfd_mach_mips5000
:
4952 mips_abi
= MIPS_ABI_EABI64
;
4954 case bfd_mach_mips8000
:
4955 case bfd_mach_mips10000
:
4956 /* On Irix, ELF64 executables use the N64 ABI. The
4957 pseudo-sections which describe the ABI aren't present
4958 on IRIX. (Even for executables created by gcc.) */
4959 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4960 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4961 mips_abi
= MIPS_ABI_N64
;
4963 mips_abi
= MIPS_ABI_N32
;
4968 #ifdef MIPS_DEFAULT_ABI
4969 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4970 mips_abi
= MIPS_DEFAULT_ABI
;
4973 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4974 mips_abi
= MIPS_ABI_O32
;
4976 /* Now that we have found what the ABI for this binary would be,
4977 check whether the user is overriding it. */
4978 found_abi
= mips_abi
;
4979 wanted_abi
= global_mips_abi ();
4980 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4981 mips_abi
= wanted_abi
;
4985 fprintf_unfiltered (gdb_stdlog
,
4986 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4988 fprintf_unfiltered (gdb_stdlog
,
4989 "mips_gdbarch_init: mips_abi = %d\n",
4991 fprintf_unfiltered (gdb_stdlog
,
4992 "mips_gdbarch_init: found_mips_abi = %d\n",
4996 /* try to find a pre-existing architecture */
4997 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4999 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5001 /* MIPS needs to be pedantic about which ABI the object is
5003 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5005 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5007 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
5008 return arches
->gdbarch
;
5011 /* Need a new architecture. Fill in a target specific vector. */
5012 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5013 gdbarch
= gdbarch_alloc (&info
, tdep
);
5014 tdep
->elf_flags
= elf_flags
;
5015 tdep
->osabi
= osabi
;
5017 /* Initially set everything according to the default ABI/ISA. */
5018 set_gdbarch_short_bit (gdbarch
, 16);
5019 set_gdbarch_int_bit (gdbarch
, 32);
5020 set_gdbarch_float_bit (gdbarch
, 32);
5021 set_gdbarch_double_bit (gdbarch
, 64);
5022 set_gdbarch_long_double_bit (gdbarch
, 64);
5023 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
5024 set_gdbarch_max_register_raw_size (gdbarch
, 8);
5025 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
5026 tdep
->found_abi
= found_abi
;
5027 tdep
->mips_abi
= mips_abi
;
5032 set_gdbarch_push_arguments (gdbarch
, mips_o32o64_push_arguments
);
5033 tdep
->mips_default_saved_regsize
= 4;
5034 tdep
->mips_default_stack_argsize
= 4;
5035 tdep
->mips_fp_register_double
= 0;
5036 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5037 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5038 tdep
->gdb_target_is_mips64
= 0;
5039 tdep
->default_mask_address_p
= 0;
5040 set_gdbarch_long_bit (gdbarch
, 32);
5041 set_gdbarch_ptr_bit (gdbarch
, 32);
5042 set_gdbarch_long_long_bit (gdbarch
, 64);
5043 set_gdbarch_reg_struct_has_addr (gdbarch
,
5044 mips_o32_reg_struct_has_addr
);
5045 set_gdbarch_use_struct_convention (gdbarch
,
5046 mips_o32_use_struct_convention
);
5049 set_gdbarch_push_arguments (gdbarch
, mips_o32o64_push_arguments
);
5050 tdep
->mips_default_saved_regsize
= 8;
5051 tdep
->mips_default_stack_argsize
= 8;
5052 tdep
->mips_fp_register_double
= 1;
5053 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5054 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5055 tdep
->gdb_target_is_mips64
= 1;
5056 tdep
->default_mask_address_p
= 0;
5057 set_gdbarch_long_bit (gdbarch
, 32);
5058 set_gdbarch_ptr_bit (gdbarch
, 32);
5059 set_gdbarch_long_long_bit (gdbarch
, 64);
5060 set_gdbarch_reg_struct_has_addr (gdbarch
,
5061 mips_o32_reg_struct_has_addr
);
5062 set_gdbarch_use_struct_convention (gdbarch
,
5063 mips_o32_use_struct_convention
);
5065 case MIPS_ABI_EABI32
:
5066 set_gdbarch_push_arguments (gdbarch
, mips_eabi_push_arguments
);
5067 tdep
->mips_default_saved_regsize
= 4;
5068 tdep
->mips_default_stack_argsize
= 4;
5069 tdep
->mips_fp_register_double
= 0;
5070 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5071 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5072 tdep
->gdb_target_is_mips64
= 0;
5073 tdep
->default_mask_address_p
= 0;
5074 set_gdbarch_long_bit (gdbarch
, 32);
5075 set_gdbarch_ptr_bit (gdbarch
, 32);
5076 set_gdbarch_long_long_bit (gdbarch
, 64);
5077 set_gdbarch_reg_struct_has_addr (gdbarch
,
5078 mips_eabi_reg_struct_has_addr
);
5079 set_gdbarch_use_struct_convention (gdbarch
,
5080 mips_eabi_use_struct_convention
);
5082 case MIPS_ABI_EABI64
:
5083 set_gdbarch_push_arguments (gdbarch
, mips_eabi_push_arguments
);
5084 tdep
->mips_default_saved_regsize
= 8;
5085 tdep
->mips_default_stack_argsize
= 8;
5086 tdep
->mips_fp_register_double
= 1;
5087 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5088 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5089 tdep
->gdb_target_is_mips64
= 1;
5090 tdep
->default_mask_address_p
= 0;
5091 set_gdbarch_long_bit (gdbarch
, 64);
5092 set_gdbarch_ptr_bit (gdbarch
, 64);
5093 set_gdbarch_long_long_bit (gdbarch
, 64);
5094 set_gdbarch_reg_struct_has_addr (gdbarch
,
5095 mips_eabi_reg_struct_has_addr
);
5096 set_gdbarch_use_struct_convention (gdbarch
,
5097 mips_eabi_use_struct_convention
);
5100 set_gdbarch_push_arguments (gdbarch
, mips_n32n64_push_arguments
);
5101 tdep
->mips_default_saved_regsize
= 8;
5102 tdep
->mips_default_stack_argsize
= 8;
5103 tdep
->mips_fp_register_double
= 1;
5104 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5105 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5106 tdep
->gdb_target_is_mips64
= 1;
5107 tdep
->default_mask_address_p
= 0;
5108 set_gdbarch_long_bit (gdbarch
, 32);
5109 set_gdbarch_ptr_bit (gdbarch
, 32);
5110 set_gdbarch_long_long_bit (gdbarch
, 64);
5112 /* Set up the disassembler info, so that we get the right
5113 register names from libopcodes. */
5114 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
5115 tm_print_insn_info
.arch
= bfd_arch_mips
;
5116 if (info
.bfd_arch_info
!= NULL
5117 && info
.bfd_arch_info
->arch
== bfd_arch_mips
5118 && info
.bfd_arch_info
->mach
)
5119 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
5121 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
5123 set_gdbarch_use_struct_convention (gdbarch
,
5124 mips_n32n64_use_struct_convention
);
5125 set_gdbarch_reg_struct_has_addr (gdbarch
,
5126 mips_n32n64_reg_struct_has_addr
);
5129 set_gdbarch_push_arguments (gdbarch
, mips_n32n64_push_arguments
);
5130 tdep
->mips_default_saved_regsize
= 8;
5131 tdep
->mips_default_stack_argsize
= 8;
5132 tdep
->mips_fp_register_double
= 1;
5133 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5134 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5135 tdep
->gdb_target_is_mips64
= 1;
5136 tdep
->default_mask_address_p
= 0;
5137 set_gdbarch_long_bit (gdbarch
, 64);
5138 set_gdbarch_ptr_bit (gdbarch
, 64);
5139 set_gdbarch_long_long_bit (gdbarch
, 64);
5141 /* Set up the disassembler info, so that we get the right
5142 register names from libopcodes. */
5143 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
5144 tm_print_insn_info
.arch
= bfd_arch_mips
;
5145 if (info
.bfd_arch_info
!= NULL
5146 && info
.bfd_arch_info
->arch
== bfd_arch_mips
5147 && info
.bfd_arch_info
->mach
)
5148 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
5150 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
5152 set_gdbarch_use_struct_convention (gdbarch
,
5153 mips_n32n64_use_struct_convention
);
5154 set_gdbarch_reg_struct_has_addr (gdbarch
,
5155 mips_n32n64_reg_struct_has_addr
);
5158 internal_error (__FILE__
, __LINE__
,
5159 "unknown ABI in switch");
5162 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5163 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5166 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5167 flag in object files because to do so would make it impossible to
5168 link with libraries compiled without "-gp32". This is
5169 unnecessarily restrictive.
5171 We could solve this problem by adding "-gp32" multilibs to gcc,
5172 but to set this flag before gcc is built with such multilibs will
5173 break too many systems.''
5175 But even more unhelpfully, the default linker output target for
5176 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5177 for 64-bit programs - you need to change the ABI to change this,
5178 and not all gcc targets support that currently. Therefore using
5179 this flag to detect 32-bit mode would do the wrong thing given
5180 the current gcc - it would make GDB treat these 64-bit programs
5181 as 32-bit programs by default. */
5183 /* enable/disable the MIPS FPU */
5184 if (!mips_fpu_type_auto
)
5185 tdep
->mips_fpu_type
= mips_fpu_type
;
5186 else if (info
.bfd_arch_info
!= NULL
5187 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5188 switch (info
.bfd_arch_info
->mach
)
5190 case bfd_mach_mips3900
:
5191 case bfd_mach_mips4100
:
5192 case bfd_mach_mips4111
:
5193 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
5195 case bfd_mach_mips4650
:
5196 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
5199 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5203 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5205 /* MIPS version of register names. NOTE: At present the MIPS
5206 register name management is part way between the old -
5207 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
5208 Further work on it is required. */
5209 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5210 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5211 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
5212 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
5213 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5214 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
5216 /* Add/remove bits from an address. The MIPS needs be careful to
5217 ensure that all 32 bit addresses are sign extended to 64 bits. */
5218 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5220 /* There's a mess in stack frame creation. See comments in
5221 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
5222 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
5223 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
5225 /* Map debug register numbers onto internal register numbers. */
5226 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5227 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
5229 /* Initialize a frame */
5230 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
5231 set_gdbarch_frame_init_saved_regs (gdbarch
, mips_frame_init_saved_regs
);
5233 /* MIPS version of CALL_DUMMY */
5235 set_gdbarch_call_dummy_p (gdbarch
, 1);
5236 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
5237 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
5238 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
5239 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
5240 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
5241 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
5242 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
5243 set_gdbarch_call_dummy_length (gdbarch
, 0);
5244 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
5245 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
5246 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
5247 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
5248 set_gdbarch_register_convertible (gdbarch
, mips_register_convertible
);
5249 set_gdbarch_register_convert_to_virtual (gdbarch
,
5250 mips_register_convert_to_virtual
);
5251 set_gdbarch_register_convert_to_raw (gdbarch
,
5252 mips_register_convert_to_raw
);
5254 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
5256 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
5257 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
5259 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5260 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5261 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
5263 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5264 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
5266 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5267 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5268 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5270 set_gdbarch_function_start_offset (gdbarch
, 0);
5272 /* There are MIPS targets which do not yet use this since they still
5273 define REGISTER_VIRTUAL_TYPE. */
5274 set_gdbarch_register_virtual_type (gdbarch
, mips_register_virtual_type
);
5275 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
5277 set_gdbarch_do_registers_info (gdbarch
, mips_do_registers_info
);
5278 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
5280 /* Hook in OS ABI-specific overrides, if they have been registered. */
5281 gdbarch_init_osabi (info
, gdbarch
, osabi
);
5287 mips_abi_update (char *ignore_args
, int from_tty
,
5288 struct cmd_list_element
*c
)
5290 struct gdbarch_info info
;
5292 /* Force the architecture to update, and (if it's a MIPS architecture)
5293 mips_gdbarch_init will take care of the rest. */
5294 gdbarch_info_init (&info
);
5295 gdbarch_update_p (info
);
5299 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5301 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5305 int ef_mips_32bitmode
;
5306 /* determine the ISA */
5307 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5325 /* determine the size of a pointer */
5326 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5327 fprintf_unfiltered (file
,
5328 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5330 fprintf_unfiltered (file
,
5331 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5333 fprintf_unfiltered (file
,
5334 "mips_dump_tdep: ef_mips_arch = %d\n",
5336 fprintf_unfiltered (file
,
5337 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5339 mips_abi_strings
[tdep
->mips_abi
]);
5340 fprintf_unfiltered (file
,
5341 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5342 mips_mask_address_p (),
5343 tdep
->default_mask_address_p
);
5345 fprintf_unfiltered (file
,
5346 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5347 FP_REGISTER_DOUBLE
);
5348 fprintf_unfiltered (file
,
5349 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5350 MIPS_DEFAULT_FPU_TYPE
,
5351 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5352 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5353 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5355 fprintf_unfiltered (file
,
5356 "mips_dump_tdep: MIPS_EABI = %d\n",
5358 fprintf_unfiltered (file
,
5359 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
5360 MIPS_LAST_FP_ARG_REGNUM
,
5361 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
5362 fprintf_unfiltered (file
,
5363 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5365 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5366 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5367 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5369 fprintf_unfiltered (file
,
5370 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
5371 MIPS_DEFAULT_SAVED_REGSIZE
);
5372 fprintf_unfiltered (file
,
5373 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5374 FP_REGISTER_DOUBLE
);
5375 fprintf_unfiltered (file
,
5376 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
5377 MIPS_DEFAULT_STACK_ARGSIZE
);
5378 fprintf_unfiltered (file
,
5379 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
5380 MIPS_STACK_ARGSIZE
);
5381 fprintf_unfiltered (file
,
5382 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
5384 fprintf_unfiltered (file
,
5385 "mips_dump_tdep: A0_REGNUM = %d\n",
5387 fprintf_unfiltered (file
,
5388 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5389 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
5390 fprintf_unfiltered (file
,
5391 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5392 XSTRING (ATTACH_DETACH
));
5393 fprintf_unfiltered (file
,
5394 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
5396 fprintf_unfiltered (file
,
5397 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
5398 fprintf_unfiltered (file
,
5399 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
5401 fprintf_unfiltered (file
,
5402 "mips_dump_tdep: CPLUS_MARKER = %c\n",
5404 fprintf_unfiltered (file
,
5405 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
5407 fprintf_unfiltered (file
,
5408 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
5409 XSTRING (DO_REGISTERS_INFO
));
5410 fprintf_unfiltered (file
,
5411 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5412 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5413 fprintf_unfiltered (file
,
5414 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5415 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5416 fprintf_unfiltered (file
,
5417 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
5418 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
5419 fprintf_unfiltered (file
,
5420 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
5422 fprintf_unfiltered (file
,
5423 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
5425 fprintf_unfiltered (file
,
5426 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5427 FIRST_EMBED_REGNUM
);
5428 fprintf_unfiltered (file
,
5429 "mips_dump_tdep: FPA0_REGNUM = %d\n",
5431 fprintf_unfiltered (file
,
5432 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
5433 GDB_TARGET_IS_MIPS64
);
5434 fprintf_unfiltered (file
,
5435 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
5436 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
5437 fprintf_unfiltered (file
,
5438 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
5439 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
5440 fprintf_unfiltered (file
,
5441 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
5443 fprintf_unfiltered (file
,
5444 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
5445 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
5446 fprintf_unfiltered (file
,
5447 "mips_dump_tdep: HI_REGNUM = %d\n",
5449 fprintf_unfiltered (file
,
5450 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
5451 fprintf_unfiltered (file
,
5452 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
5453 fprintf_unfiltered (file
,
5454 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
5455 XSTRING (IGNORE_HELPER_CALL (PC
)));
5456 fprintf_unfiltered (file
,
5457 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5458 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
5459 fprintf_unfiltered (file
,
5460 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
5461 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
5462 fprintf_unfiltered (file
,
5463 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
5464 fprintf_unfiltered (file
,
5465 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5467 fprintf_unfiltered (file
,
5468 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
5469 fprintf_unfiltered (file
,
5470 "mips_dump_tdep: LO_REGNUM = %d\n",
5472 #ifdef MACHINE_CPROC_FP_OFFSET
5473 fprintf_unfiltered (file
,
5474 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5475 MACHINE_CPROC_FP_OFFSET
);
5477 #ifdef MACHINE_CPROC_PC_OFFSET
5478 fprintf_unfiltered (file
,
5479 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5480 MACHINE_CPROC_PC_OFFSET
);
5482 #ifdef MACHINE_CPROC_SP_OFFSET
5483 fprintf_unfiltered (file
,
5484 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5485 MACHINE_CPROC_SP_OFFSET
);
5487 fprintf_unfiltered (file
,
5488 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
5489 fprintf_unfiltered (file
,
5490 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
5491 fprintf_unfiltered (file
,
5492 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5494 fprintf_unfiltered (file
,
5495 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
5496 fprintf_unfiltered (file
,
5497 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5498 fprintf_unfiltered (file
,
5499 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5500 fprintf_unfiltered (file
,
5501 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
5503 fprintf_unfiltered (file
,
5504 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5505 MIPS_LAST_ARG_REGNUM
,
5506 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
5507 fprintf_unfiltered (file
,
5508 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
5510 fprintf_unfiltered (file
,
5511 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
5512 fprintf_unfiltered (file
,
5513 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
5514 MIPS_SAVED_REGSIZE
);
5515 fprintf_unfiltered (file
,
5516 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
5517 fprintf_unfiltered (file
,
5518 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
5519 XSTRING (MSYMBOL_SIZE (MSYM
)));
5520 fprintf_unfiltered (file
,
5521 "mips_dump_tdep: OP_LDFPR = used?\n");
5522 fprintf_unfiltered (file
,
5523 "mips_dump_tdep: OP_LDGPR = used?\n");
5524 fprintf_unfiltered (file
,
5525 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
5526 fprintf_unfiltered (file
,
5527 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
5528 fprintf_unfiltered (file
,
5529 "mips_dump_tdep: PRID_REGNUM = %d\n",
5531 fprintf_unfiltered (file
,
5532 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
5533 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
5534 fprintf_unfiltered (file
,
5535 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5536 fprintf_unfiltered (file
,
5537 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5538 fprintf_unfiltered (file
,
5539 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5540 fprintf_unfiltered (file
,
5541 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5542 fprintf_unfiltered (file
,
5543 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5544 fprintf_unfiltered (file
,
5545 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5546 fprintf_unfiltered (file
,
5547 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5548 fprintf_unfiltered (file
,
5549 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5550 fprintf_unfiltered (file
,
5551 "mips_dump_tdep: PROC_PC_REG = function?\n");
5552 fprintf_unfiltered (file
,
5553 "mips_dump_tdep: PROC_REG_MASK = function?\n");
5554 fprintf_unfiltered (file
,
5555 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5556 fprintf_unfiltered (file
,
5557 "mips_dump_tdep: PROC_SYMBOL = function?\n");
5558 fprintf_unfiltered (file
,
5559 "mips_dump_tdep: PS_REGNUM = %d\n",
5561 fprintf_unfiltered (file
,
5562 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
5564 fprintf_unfiltered (file
,
5565 "mips_dump_tdep: RA_REGNUM = %d\n",
5567 fprintf_unfiltered (file
,
5568 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
5569 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
5570 fprintf_unfiltered (file
,
5571 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
5572 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
5573 fprintf_unfiltered (file
,
5574 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
5575 fprintf_unfiltered (file
,
5576 "mips_dump_tdep: ROUND_DOWN = function?\n");
5577 fprintf_unfiltered (file
,
5578 "mips_dump_tdep: ROUND_UP = function?\n");
5580 fprintf_unfiltered (file
,
5581 "mips_dump_tdep: SAVED_BYTES = %d\n",
5585 fprintf_unfiltered (file
,
5586 "mips_dump_tdep: SAVED_FP = %d\n",
5590 fprintf_unfiltered (file
,
5591 "mips_dump_tdep: SAVED_PC = %d\n",
5594 fprintf_unfiltered (file
,
5595 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5596 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
5597 fprintf_unfiltered (file
,
5598 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
5599 fprintf_unfiltered (file
,
5600 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
5602 fprintf_unfiltered (file
,
5603 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
5604 SIGFRAME_FPREGSAVE_OFF
);
5605 fprintf_unfiltered (file
,
5606 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
5608 fprintf_unfiltered (file
,
5609 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
5610 SIGFRAME_REGSAVE_OFF
);
5611 fprintf_unfiltered (file
,
5612 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
5614 fprintf_unfiltered (file
,
5615 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
5616 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
5617 fprintf_unfiltered (file
,
5618 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5619 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
5620 fprintf_unfiltered (file
,
5621 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5622 SOFTWARE_SINGLE_STEP_P ());
5623 fprintf_unfiltered (file
,
5624 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5625 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
5626 #ifdef STACK_END_ADDR
5627 fprintf_unfiltered (file
,
5628 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5631 fprintf_unfiltered (file
,
5632 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5633 XSTRING (STEP_SKIPS_DELAY (PC
)));
5634 fprintf_unfiltered (file
,
5635 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5636 STEP_SKIPS_DELAY_P
);
5637 fprintf_unfiltered (file
,
5638 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5639 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
5640 fprintf_unfiltered (file
,
5641 "mips_dump_tdep: T9_REGNUM = %d\n",
5643 fprintf_unfiltered (file
,
5644 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5645 fprintf_unfiltered (file
,
5646 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5647 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
5648 fprintf_unfiltered (file
,
5649 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
5650 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
5651 fprintf_unfiltered (file
,
5652 "mips_dump_tdep: TARGET_MIPS = used?\n");
5653 fprintf_unfiltered (file
,
5654 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
5655 XSTRING (TM_PRINT_INSN_MACH
));
5657 fprintf_unfiltered (file
,
5658 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5659 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
5662 fprintf_unfiltered (file
,
5663 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
5666 #ifdef TRACE_FLAVOR_SIZE
5667 fprintf_unfiltered (file
,
5668 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5672 fprintf_unfiltered (file
,
5673 "mips_dump_tdep: TRACE_SET # %s\n",
5674 XSTRING (TRACE_SET (X
,STATE
)));
5676 fprintf_unfiltered (file
,
5677 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
5678 #ifdef UNUSED_REGNUM
5679 fprintf_unfiltered (file
,
5680 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
5683 fprintf_unfiltered (file
,
5684 "mips_dump_tdep: V0_REGNUM = %d\n",
5686 fprintf_unfiltered (file
,
5687 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5688 (long) VM_MIN_ADDRESS
);
5690 fprintf_unfiltered (file
,
5691 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
5694 fprintf_unfiltered (file
,
5695 "mips_dump_tdep: ZERO_REGNUM = %d\n",
5697 fprintf_unfiltered (file
,
5698 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
5701 fprintf_unfiltered (file
,
5702 "mips_dump_tdep: OS ABI = %s\n",
5703 gdbarch_osabi_name (tdep
->osabi
));
5707 _initialize_mips_tdep (void)
5709 static struct cmd_list_element
*mipsfpulist
= NULL
;
5710 struct cmd_list_element
*c
;
5712 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5713 if (MIPS_ABI_LAST
+ 1
5714 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5715 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
5717 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5718 if (!tm_print_insn
) /* Someone may have already set it */
5719 tm_print_insn
= gdb_print_insn_mips
;
5721 /* Add root prefix command for all "set mips"/"show mips" commands */
5722 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5723 "Various MIPS specific commands.",
5724 &setmipscmdlist
, "set mips ", 0, &setlist
);
5726 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5727 "Various MIPS specific commands.",
5728 &showmipscmdlist
, "show mips ", 0, &showlist
);
5730 /* Allow the user to override the saved register size. */
5731 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
5734 &mips_saved_regsize_string
, "\
5735 Set size of general purpose registers saved on the stack.\n\
5736 This option can be set to one of:\n\
5737 32 - Force GDB to treat saved GP registers as 32-bit\n\
5738 64 - Force GDB to treat saved GP registers as 64-bit\n\
5739 auto - Allow GDB to use the target's default setting or autodetect the\n\
5740 saved GP register size from information contained in the executable.\n\
5745 /* Allow the user to override the argument stack size. */
5746 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
5749 &mips_stack_argsize_string
, "\
5750 Set the amount of stack space reserved for each argument.\n\
5751 This option can be set to one of:\n\
5752 32 - Force GDB to allocate 32-bit chunks per argument\n\
5753 64 - Force GDB to allocate 64-bit chunks per argument\n\
5754 auto - Allow GDB to determine the correct setting from the current\n\
5755 target and executable (default)",
5759 /* Allow the user to override the ABI. */
5760 c
= add_set_enum_cmd
5761 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
5762 "Set the ABI used by this program.\n"
5763 "This option can be set to one of:\n"
5764 " auto - the default ABI associated with the current binary\n"
5772 add_show_from_set (c
, &showmipscmdlist
);
5773 set_cmd_sfunc (c
, mips_abi_update
);
5775 /* Let the user turn off floating point and set the fence post for
5776 heuristic_proc_start. */
5778 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5779 "Set use of MIPS floating-point coprocessor.",
5780 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5781 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5782 "Select single-precision MIPS floating-point coprocessor.",
5784 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5785 "Select double-precision MIPS floating-point coprocessor.",
5787 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5788 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5789 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5790 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5791 "Select no MIPS floating-point coprocessor.",
5793 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5794 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5795 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5796 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5797 "Select MIPS floating-point coprocessor automatically.",
5799 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5800 "Show current use of MIPS floating-point coprocessor target.",
5803 /* We really would like to have both "0" and "unlimited" work, but
5804 command.c doesn't deal with that. So make it a var_zinteger
5805 because the user can always use "999999" or some such for unlimited. */
5806 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
5807 (char *) &heuristic_fence_post
,
5809 Set the distance searched for the start of a function.\n\
5810 If you are debugging a stripped executable, GDB needs to search through the\n\
5811 program for the start of a function. This command sets the distance of the\n\
5812 search. The only need to set it is when debugging a stripped executable.",
5814 /* We need to throw away the frame cache when we set this, since it
5815 might change our ability to get backtraces. */
5816 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
5817 add_show_from_set (c
, &showlist
);
5819 /* Allow the user to control whether the upper bits of 64-bit
5820 addresses should be zeroed. */
5821 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
5822 Set zeroing of upper 32 bits of 64-bit addresses.\n\
5823 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5824 allow GDB to determine the correct value.\n", "\
5825 Show zeroing of upper 32 bits of 64-bit addresses.",
5826 NULL
, show_mask_address
,
5827 &setmipscmdlist
, &showmipscmdlist
);
5829 /* Allow the user to control the size of 32 bit registers within the
5830 raw remote packet. */
5831 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5834 (char *)&mips64_transfers_32bit_regs_p
, "\
5835 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5836 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5837 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5838 64 bits for others. Use \"off\" to disable compatibility mode",
5842 /* Debug this files internals. */
5843 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
5844 &mips_debug
, "Set mips debugging.\n\
5845 When non-zero, mips specific debugging is enabled.", &setdebuglist
),