1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 static const struct objfile_data
*mips_pdr_data
;
59 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
60 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
62 /* A useful bit in the CP0 status register (PS_REGNUM). */
63 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
64 #define ST0_FR (1 << 26)
66 /* The sizes of floating point registers. */
70 MIPS_FPU_SINGLE_REGSIZE
= 4,
71 MIPS_FPU_DOUBLE_REGSIZE
= 8
75 static const char *mips_abi_string
;
77 static const char *mips_abi_strings
[] = {
88 struct frame_extra_info
90 mips_extra_func_info_t proc_desc
;
94 /* Various MIPS ISA options (related to stack analysis) can be
95 overridden dynamically. Establish an enum/array for managing
98 static const char size_auto
[] = "auto";
99 static const char size_32
[] = "32";
100 static const char size_64
[] = "64";
102 static const char *size_enums
[] = {
109 /* Some MIPS boards don't support floating point while others only
110 support single-precision floating-point operations. See also
111 FP_REGISTER_DOUBLE. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int mips_fp_register_double
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
153 const struct mips_regnum
*
154 mips_regnum (struct gdbarch
*gdbarch
)
156 return gdbarch_tdep (gdbarch
)->regnum
;
160 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
162 return mips_regnum (gdbarch
)->fp0
+ 12;
165 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
166 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
168 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
170 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
172 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
174 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
175 functions to test, set, or clear bit 0 of addresses. */
178 is_mips16_addr (CORE_ADDR addr
)
184 make_mips16_addr (CORE_ADDR addr
)
190 unmake_mips16_addr (CORE_ADDR addr
)
192 return ((addr
) & ~1);
195 /* Return the contents of register REGNUM as a signed integer. */
198 read_signed_register (int regnum
)
200 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
201 deprecated_read_register_gen (regnum
, buf
);
202 return (extract_signed_integer
203 (buf
, register_size (current_gdbarch
, regnum
)));
207 read_signed_register_pid (int regnum
, ptid_t ptid
)
212 if (ptid_equal (ptid
, inferior_ptid
))
213 return read_signed_register (regnum
);
215 save_ptid
= inferior_ptid
;
217 inferior_ptid
= ptid
;
219 retval
= read_signed_register (regnum
);
221 inferior_ptid
= save_ptid
;
226 /* Return the MIPS ABI associated with GDBARCH. */
228 mips_abi (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->mips_abi
;
234 mips_isa_regsize (struct gdbarch
*gdbarch
)
236 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
237 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
240 /* Return the currently configured (or set) saved register size. */
242 static const char *mips_abi_regsize_string
= size_auto
;
245 mips_abi_regsize (struct gdbarch
*gdbarch
)
247 if (mips_abi_regsize_string
== size_auto
)
248 switch (mips_abi (gdbarch
))
250 case MIPS_ABI_EABI32
:
256 case MIPS_ABI_EABI64
:
258 case MIPS_ABI_UNKNOWN
:
261 internal_error (__FILE__
, __LINE__
, "bad switch");
263 else if (mips_abi_regsize_string
== size_64
)
265 else /* if (mips_abi_regsize_string == size_32) */
269 /* Functions for setting and testing a bit in a minimal symbol that
270 marks it as 16-bit function. The MSB of the minimal symbol's
271 "info" field is used for this purpose.
273 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
274 i.e. refers to a 16-bit function, and sets a "special" bit in a
275 minimal symbol to mark it as a 16-bit function
277 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
280 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
282 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
284 MSYMBOL_INFO (msym
) = (char *)
285 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
286 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
291 msymbol_is_special (struct minimal_symbol
*msym
)
293 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
296 /* XFER a value from the big/little/left end of the register.
297 Depending on the size of the value it might occupy the entire
298 register or just part of it. Make an allowance for this, aligning
299 things accordingly. */
302 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
303 enum bfd_endian endian
, bfd_byte
* in
,
304 const bfd_byte
* out
, int buf_offset
)
307 gdb_assert (reg_num
>= NUM_REGS
);
308 /* Need to transfer the left or right part of the register, based on
309 the targets byte order. */
313 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
315 case BFD_ENDIAN_LITTLE
:
318 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
322 internal_error (__FILE__
, __LINE__
, "bad switch");
325 fprintf_unfiltered (gdb_stderr
,
326 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
327 reg_num
, reg_offset
, buf_offset
, length
);
328 if (mips_debug
&& out
!= NULL
)
331 fprintf_unfiltered (gdb_stdlog
, "out ");
332 for (i
= 0; i
< length
; i
++)
333 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
336 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
339 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
341 if (mips_debug
&& in
!= NULL
)
344 fprintf_unfiltered (gdb_stdlog
, "in ");
345 for (i
= 0; i
< length
; i
++)
346 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
349 fprintf_unfiltered (gdb_stdlog
, "\n");
352 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
353 compatiblity mode. A return value of 1 means that we have
354 physical 64-bit registers, but should treat them as 32-bit registers. */
357 mips2_fp_compat (void)
359 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
361 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
366 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
367 in all the places we deal with FP registers. PR gdb/413. */
368 /* Otherwise check the FR bit in the status register - it controls
369 the FP compatiblity mode. If it is clear we are in compatibility
371 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
378 /* Indicate that the ABI makes use of double-precision registers
379 provided by the FPU (rather than combining pairs of registers to
380 form double-precision values). See also MIPS_FPU_TYPE. */
381 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
383 /* The amount of space reserved on the stack for registers. This is
384 different to MIPS_ABI_REGSIZE as it determines the alignment of
385 data allocated after the registers have run out. */
387 static const char *mips_stack_argsize_string
= size_auto
;
390 mips_stack_argsize (struct gdbarch
*gdbarch
)
392 if (mips_stack_argsize_string
== size_auto
)
393 return mips_abi_regsize (gdbarch
);
394 else if (mips_stack_argsize_string
== size_64
)
396 else /* if (mips_stack_argsize_string == size_32) */
400 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
402 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
403 struct frame_info
*, int);
405 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
407 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
409 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
411 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
412 struct frame_info
*next_frame
,
415 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
416 mips_extra_func_info_t proc_desc
);
418 static struct type
*mips_float_register_type (void);
419 static struct type
*mips_double_register_type (void);
421 /* The list of available "set mips " and "show mips " commands */
423 static struct cmd_list_element
*setmipscmdlist
= NULL
;
424 static struct cmd_list_element
*showmipscmdlist
= NULL
;
426 /* Integer registers 0 thru 31 are handled explicitly by
427 mips_register_name(). Processor specific registers 32 and above
428 are listed in the followign tables. */
431 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
435 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
436 "sr", "lo", "hi", "bad", "cause", "pc",
437 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
438 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
439 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
440 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
441 "fsr", "fir", "" /*"fp" */ , "",
442 "", "", "", "", "", "", "", "",
443 "", "", "", "", "", "", "", "",
446 /* Names of IDT R3041 registers. */
448 static const char *mips_r3041_reg_names
[] = {
449 "sr", "lo", "hi", "bad", "cause", "pc",
450 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
451 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
452 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
453 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
454 "fsr", "fir", "", /*"fp" */ "",
455 "", "", "bus", "ccfg", "", "", "", "",
456 "", "", "port", "cmp", "", "", "epc", "prid",
459 /* Names of tx39 registers. */
461 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
462 "sr", "lo", "hi", "bad", "cause", "pc",
463 "", "", "", "", "", "", "", "",
464 "", "", "", "", "", "", "", "",
465 "", "", "", "", "", "", "", "",
466 "", "", "", "", "", "", "", "",
468 "", "", "", "", "", "", "", "",
469 "", "", "config", "cache", "debug", "depc", "epc", ""
472 /* Names of IRIX registers. */
473 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
474 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
475 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
476 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
477 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
478 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
482 /* Return the name of the register corresponding to REGNO. */
484 mips_register_name (int regno
)
486 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
487 /* GPR names for all ABIs other than n32/n64. */
488 static char *mips_gpr_names
[] = {
489 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
490 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
491 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
492 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
495 /* GPR names for n32 and n64 ABIs. */
496 static char *mips_n32_n64_gpr_names
[] = {
497 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
498 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
499 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
500 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
503 enum mips_abi abi
= mips_abi (current_gdbarch
);
505 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
506 don't make the raw register names visible. */
507 int rawnum
= regno
% NUM_REGS
;
508 if (regno
< NUM_REGS
)
511 /* The MIPS integer registers are always mapped from 0 to 31. The
512 names of the registers (which reflects the conventions regarding
513 register use) vary depending on the ABI. */
514 if (0 <= rawnum
&& rawnum
< 32)
516 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
517 return mips_n32_n64_gpr_names
[rawnum
];
519 return mips_gpr_names
[rawnum
];
521 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
523 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
524 return tdep
->mips_processor_reg_names
[rawnum
- 32];
527 internal_error (__FILE__
, __LINE__
,
528 "mips_register_name: bad register number %d", rawnum
);
531 /* Return the groups that a MIPS register can be categorised into. */
534 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
535 struct reggroup
*reggroup
)
540 int rawnum
= regnum
% NUM_REGS
;
541 int pseudo
= regnum
/ NUM_REGS
;
542 if (reggroup
== all_reggroup
)
544 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
545 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
546 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
547 (gdbarch), as not all architectures are multi-arch. */
548 raw_p
= rawnum
< NUM_REGS
;
549 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
551 if (reggroup
== float_reggroup
)
552 return float_p
&& pseudo
;
553 if (reggroup
== vector_reggroup
)
554 return vector_p
&& pseudo
;
555 if (reggroup
== general_reggroup
)
556 return (!vector_p
&& !float_p
) && pseudo
;
557 /* Save the pseudo registers. Need to make certain that any code
558 extracting register values from a saved register cache also uses
560 if (reggroup
== save_reggroup
)
561 return raw_p
&& pseudo
;
562 /* Restore the same pseudo register. */
563 if (reggroup
== restore_reggroup
)
564 return raw_p
&& pseudo
;
568 /* Map the symbol table registers which live in the range [1 *
569 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
570 registers. Take care of alignment and size problems. */
573 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
574 int cookednum
, void *buf
)
576 int rawnum
= cookednum
% NUM_REGS
;
577 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
578 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
579 regcache_raw_read (regcache
, rawnum
, buf
);
580 else if (register_size (gdbarch
, rawnum
) >
581 register_size (gdbarch
, cookednum
))
583 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
584 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
585 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
587 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
590 internal_error (__FILE__
, __LINE__
, "bad register size");
594 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
595 struct regcache
*regcache
, int cookednum
,
598 int rawnum
= cookednum
% NUM_REGS
;
599 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
600 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
601 regcache_raw_write (regcache
, rawnum
, buf
);
602 else if (register_size (gdbarch
, rawnum
) >
603 register_size (gdbarch
, cookednum
))
605 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
606 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
607 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
609 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
612 internal_error (__FILE__
, __LINE__
, "bad register size");
615 /* Table to translate MIPS16 register field to actual register number. */
616 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
618 /* Heuristic_proc_start may hunt through the text section for a long
619 time across a 2400 baud serial line. Allows the user to limit this
622 static unsigned int heuristic_fence_post
= 0;
624 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
625 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
626 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
627 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
628 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
629 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
630 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
631 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
632 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
633 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
634 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
635 this will corrupt pdr.iline. Fortunately we don't use it. */
636 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
637 #define _PROC_MAGIC_ 0x0F0F0F0F
638 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
639 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
641 struct linked_proc_info
643 struct mips_extra_func_info info
;
644 struct linked_proc_info
*next
;
646 *linked_proc_desc_table
= NULL
;
648 /* Number of bytes of storage in the actual machine representation for
649 register N. NOTE: This defines the pseudo register type so need to
650 rebuild the architecture vector. */
652 static int mips64_transfers_32bit_regs_p
= 0;
655 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
656 struct cmd_list_element
*c
)
658 struct gdbarch_info info
;
659 gdbarch_info_init (&info
);
660 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
661 instead of relying on globals. Doing that would let generic code
662 handle the search for this specific architecture. */
663 if (!gdbarch_update_p (info
))
665 mips64_transfers_32bit_regs_p
= 0;
666 error ("32-bit compatibility mode not supported");
670 /* Convert to/from a register and the corresponding memory value. */
673 mips_convert_register_p (int regnum
, struct type
*type
)
675 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
676 && register_size (current_gdbarch
, regnum
) == 4
677 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
678 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
679 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
683 mips_register_to_value (struct frame_info
*frame
, int regnum
,
684 struct type
*type
, void *to
)
686 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
687 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
691 mips_value_to_register (struct frame_info
*frame
, int regnum
,
692 struct type
*type
, const void *from
)
694 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
695 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
698 /* Return the GDB type object for the "standard" data type of data in
702 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
704 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
705 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
706 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
708 /* The floating-point registers raw, or cooked, always match
709 mips_isa_regsize(), and also map 1:1, byte for byte. */
710 switch (gdbarch_byte_order (gdbarch
))
713 if (mips_isa_regsize (gdbarch
) == 4)
714 return builtin_type_ieee_single_big
;
716 return builtin_type_ieee_double_big
;
717 case BFD_ENDIAN_LITTLE
:
718 if (mips_isa_regsize (gdbarch
) == 4)
719 return builtin_type_ieee_single_little
;
721 return builtin_type_ieee_double_little
;
722 case BFD_ENDIAN_UNKNOWN
:
724 internal_error (__FILE__
, __LINE__
, "bad switch");
728 (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
729 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
730 /* The pseudo/cooked view of the embedded registers is always
731 32-bit. The raw view is handled below. */
732 return builtin_type_int32
;
733 else if (regnum
>= NUM_REGS
&& mips_isa_regsize (gdbarch
)
734 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
735 /* The target, while using a 64-bit register buffer, is only
736 transfering 32-bits of each integer register. Reflect this in
737 the cooked/pseudo register value. */
738 return builtin_type_int32
;
739 else if (mips_isa_regsize (gdbarch
) == 8)
741 return builtin_type_int64
;
744 return builtin_type_int32
;
747 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
752 return read_signed_register (SP_REGNUM
);
755 /* Should the upper word of 64-bit addresses be zeroed? */
756 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
759 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
761 switch (mask_address_var
)
763 case AUTO_BOOLEAN_TRUE
:
765 case AUTO_BOOLEAN_FALSE
:
768 case AUTO_BOOLEAN_AUTO
:
769 return tdep
->default_mask_address_p
;
771 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
777 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
779 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
780 switch (mask_address_var
)
782 case AUTO_BOOLEAN_TRUE
:
783 printf_filtered ("The 32 bit mips address mask is enabled\n");
785 case AUTO_BOOLEAN_FALSE
:
786 printf_filtered ("The 32 bit mips address mask is disabled\n");
788 case AUTO_BOOLEAN_AUTO
:
790 ("The 32 bit address mask is set automatically. Currently %s\n",
791 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
794 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
799 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
802 pc_is_mips16 (bfd_vma memaddr
)
804 struct minimal_symbol
*sym
;
806 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
807 if (is_mips16_addr (memaddr
))
810 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
811 the high bit of the info field. Use this to decide if the function is
812 MIPS16 or normal MIPS. */
813 sym
= lookup_minimal_symbol_by_pc (memaddr
);
815 return msymbol_is_special (sym
);
820 /* MIPS believes that the PC has a sign extended value. Perhaphs the
821 all registers should be sign extended for simplicity? */
824 mips_read_pc (ptid_t ptid
)
826 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
830 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
832 return frame_unwind_register_signed (next_frame
,
833 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
836 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
837 dummy frame. The frame ID's base needs to match the TOS value
838 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
841 static struct frame_id
842 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
844 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ SP_REGNUM
),
845 frame_pc_unwind (next_frame
));
849 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
851 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
854 /* This returns the PC of the first inst after the prologue. If we can't
855 find the prologue, then return 0. */
858 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
860 struct symtab_and_line sal
;
861 CORE_ADDR func_addr
, func_end
;
863 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
864 to read the stack pointer from the current machine state, because
865 the current machine state has nothing to do with the information
866 we need from the proc_desc; and the process may or may not exist
869 proc_desc
= find_proc_desc (pc
, NULL
, 0);
873 /* If function is frameless, then we need to do it the hard way. I
874 strongly suspect that frameless always means prologueless... */
875 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
876 && PROC_FRAME_OFFSET (proc_desc
) == 0)
880 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
881 return 0; /* Unknown */
883 sal
= find_pc_line (func_addr
, 0);
885 if (sal
.end
< func_end
)
888 /* The line after the prologue is after the end of the function. In this
889 case, tell the caller to find the prologue the hard way. */
894 /* Decode a MIPS32 instruction that saves a register in the stack, and
895 set the appropriate bit in the general register mask or float register mask
896 to indicate which register is saved. This is a helper function
897 for mips_find_saved_regs. */
900 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
901 unsigned long *float_mask
)
905 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
906 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
907 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
909 /* It might be possible to use the instruction to
910 find the offset, rather than the code below which
911 is based on things being in a certain order in the
912 frame, but figuring out what the instruction's offset
913 is relative to might be a little tricky. */
914 reg
= (inst
& 0x001f0000) >> 16;
915 *gen_mask
|= (1 << reg
);
917 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
918 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
919 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
922 reg
= ((inst
& 0x001f0000) >> 16);
923 *float_mask
|= (1 << reg
);
927 /* Decode a MIPS16 instruction that saves a register in the stack, and
928 set the appropriate bit in the general register or float register mask
929 to indicate which register is saved. This is a helper function
930 for mips_find_saved_regs. */
933 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
935 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
937 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
938 *gen_mask
|= (1 << reg
);
940 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
942 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
943 *gen_mask
|= (1 << reg
);
945 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
946 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
947 *gen_mask
|= (1 << RA_REGNUM
);
951 /* Fetch and return instruction from the specified location. If the PC
952 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
955 mips_fetch_instruction (CORE_ADDR addr
)
957 char buf
[MIPS_INSTLEN
];
961 if (pc_is_mips16 (addr
))
963 instlen
= MIPS16_INSTLEN
;
964 addr
= unmake_mips16_addr (addr
);
967 instlen
= MIPS_INSTLEN
;
968 status
= read_memory_nobpt (addr
, buf
, instlen
);
970 memory_error (status
, addr
);
971 return extract_unsigned_integer (buf
, instlen
);
975 mips16_fetch_instruction (CORE_ADDR addr
)
977 char buf
[MIPS_INSTLEN
];
981 instlen
= MIPS16_INSTLEN
;
982 addr
= unmake_mips16_addr (addr
);
983 status
= read_memory_nobpt (addr
, buf
, instlen
);
985 memory_error (status
, addr
);
986 return extract_unsigned_integer (buf
, instlen
);
990 mips32_fetch_instruction (CORE_ADDR addr
)
992 char buf
[MIPS_INSTLEN
];
995 instlen
= MIPS_INSTLEN
;
996 status
= read_memory_nobpt (addr
, buf
, instlen
);
998 memory_error (status
, addr
);
999 return extract_unsigned_integer (buf
, instlen
);
1003 /* These the fields of 32 bit mips instructions */
1004 #define mips32_op(x) (x >> 26)
1005 #define itype_op(x) (x >> 26)
1006 #define itype_rs(x) ((x >> 21) & 0x1f)
1007 #define itype_rt(x) ((x >> 16) & 0x1f)
1008 #define itype_immediate(x) (x & 0xffff)
1010 #define jtype_op(x) (x >> 26)
1011 #define jtype_target(x) (x & 0x03ffffff)
1013 #define rtype_op(x) (x >> 26)
1014 #define rtype_rs(x) ((x >> 21) & 0x1f)
1015 #define rtype_rt(x) ((x >> 16) & 0x1f)
1016 #define rtype_rd(x) ((x >> 11) & 0x1f)
1017 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1018 #define rtype_funct(x) (x & 0x3f)
1021 mips32_relative_offset (unsigned long inst
)
1024 x
= itype_immediate (inst
);
1025 if (x
& 0x8000) /* sign bit set */
1027 x
|= 0xffff0000; /* sign extension */
1033 /* Determine whate to set a single step breakpoint while considering
1034 branch prediction */
1036 mips32_next_pc (CORE_ADDR pc
)
1040 inst
= mips_fetch_instruction (pc
);
1041 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1043 if (itype_op (inst
) >> 2 == 5)
1044 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1046 op
= (itype_op (inst
) & 0x03);
1056 goto greater_branch
;
1061 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1062 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1064 int tf
= itype_rt (inst
) & 0x01;
1065 int cnum
= itype_rt (inst
) >> 2;
1067 read_signed_register (mips_regnum (current_gdbarch
)->
1069 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1071 if (((cond
>> cnum
) & 0x01) == tf
)
1072 pc
+= mips32_relative_offset (inst
) + 4;
1077 pc
+= 4; /* Not a branch, next instruction is easy */
1080 { /* This gets way messy */
1082 /* Further subdivide into SPECIAL, REGIMM and other */
1083 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1085 case 0: /* SPECIAL */
1086 op
= rtype_funct (inst
);
1091 /* Set PC to that address */
1092 pc
= read_signed_register (rtype_rs (inst
));
1098 break; /* end SPECIAL */
1099 case 1: /* REGIMM */
1101 op
= itype_rt (inst
); /* branch condition */
1106 case 16: /* BLTZAL */
1107 case 18: /* BLTZALL */
1109 if (read_signed_register (itype_rs (inst
)) < 0)
1110 pc
+= mips32_relative_offset (inst
) + 4;
1112 pc
+= 8; /* after the delay slot */
1116 case 17: /* BGEZAL */
1117 case 19: /* BGEZALL */
1118 if (read_signed_register (itype_rs (inst
)) >= 0)
1119 pc
+= mips32_relative_offset (inst
) + 4;
1121 pc
+= 8; /* after the delay slot */
1123 /* All of the other instructions in the REGIMM category */
1128 break; /* end REGIMM */
1133 reg
= jtype_target (inst
) << 2;
1134 /* Upper four bits get never changed... */
1135 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1138 /* FIXME case JALX : */
1141 reg
= jtype_target (inst
) << 2;
1142 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1143 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1145 break; /* The new PC will be alternate mode */
1146 case 4: /* BEQ, BEQL */
1148 if (read_signed_register (itype_rs (inst
)) ==
1149 read_signed_register (itype_rt (inst
)))
1150 pc
+= mips32_relative_offset (inst
) + 4;
1154 case 5: /* BNE, BNEL */
1156 if (read_signed_register (itype_rs (inst
)) !=
1157 read_signed_register (itype_rt (inst
)))
1158 pc
+= mips32_relative_offset (inst
) + 4;
1162 case 6: /* BLEZ, BLEZL */
1163 if (read_signed_register (itype_rs (inst
) <= 0))
1164 pc
+= mips32_relative_offset (inst
) + 4;
1170 greater_branch
: /* BGTZ, BGTZL */
1171 if (read_signed_register (itype_rs (inst
) > 0))
1172 pc
+= mips32_relative_offset (inst
) + 4;
1179 } /* mips32_next_pc */
1181 /* Decoding the next place to set a breakpoint is irregular for the
1182 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1183 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1184 We dont want to set a single step instruction on the extend instruction
1188 /* Lots of mips16 instruction formats */
1189 /* Predicting jumps requires itype,ritype,i8type
1190 and their extensions extItype,extritype,extI8type
1192 enum mips16_inst_fmts
1194 itype
, /* 0 immediate 5,10 */
1195 ritype
, /* 1 5,3,8 */
1196 rrtype
, /* 2 5,3,3,5 */
1197 rritype
, /* 3 5,3,3,5 */
1198 rrrtype
, /* 4 5,3,3,3,2 */
1199 rriatype
, /* 5 5,3,3,1,4 */
1200 shifttype
, /* 6 5,3,3,3,2 */
1201 i8type
, /* 7 5,3,8 */
1202 i8movtype
, /* 8 5,3,3,5 */
1203 i8mov32rtype
, /* 9 5,3,5,3 */
1204 i64type
, /* 10 5,3,8 */
1205 ri64type
, /* 11 5,3,3,5 */
1206 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1207 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1208 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1209 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1210 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1211 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1212 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1213 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1214 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1215 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1217 /* I am heaping all the fields of the formats into one structure and
1218 then, only the fields which are involved in instruction extension */
1222 unsigned int regx
; /* Function in i8 type */
1227 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1228 for the bits which make up the immediatate extension. */
1231 extended_offset (unsigned int extension
)
1234 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1236 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1238 value
|= extension
& 0x01f; /* extract 4:0 */
1242 /* Only call this function if you know that this is an extendable
1243 instruction, It wont malfunction, but why make excess remote memory references?
1244 If the immediate operands get sign extended or somthing, do it after
1245 the extension is performed.
1247 /* FIXME: Every one of these cases needs to worry about sign extension
1248 when the offset is to be used in relative addressing */
1252 fetch_mips_16 (CORE_ADDR pc
)
1255 pc
&= 0xfffffffe; /* clear the low order bit */
1256 target_read_memory (pc
, buf
, 2);
1257 return extract_unsigned_integer (buf
, 2);
1261 unpack_mips16 (CORE_ADDR pc
,
1262 unsigned int extension
,
1264 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1269 switch (insn_format
)
1276 value
= extended_offset (extension
);
1277 value
= value
<< 11; /* rom for the original value */
1278 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1282 value
= inst
& 0x7ff;
1283 /* FIXME : Consider sign extension */
1292 { /* A register identifier and an offset */
1293 /* Most of the fields are the same as I type but the
1294 immediate value is of a different length */
1298 value
= extended_offset (extension
);
1299 value
= value
<< 8; /* from the original instruction */
1300 value
|= inst
& 0xff; /* eleven bits from instruction */
1301 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1302 if (value
& 0x4000) /* test the sign bit , bit 26 */
1304 value
&= ~0x3fff; /* remove the sign bit */
1310 value
= inst
& 0xff; /* 8 bits */
1311 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1312 /* FIXME: Do sign extension , this format needs it */
1313 if (value
& 0x80) /* THIS CONFUSES ME */
1315 value
&= 0xef; /* remove the sign bit */
1325 unsigned long value
;
1326 unsigned int nexthalf
;
1327 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1328 value
= value
<< 16;
1329 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1337 internal_error (__FILE__
, __LINE__
, "bad switch");
1339 upk
->offset
= offset
;
1346 add_offset_16 (CORE_ADDR pc
, int offset
)
1348 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1352 extended_mips16_next_pc (CORE_ADDR pc
,
1353 unsigned int extension
, unsigned int insn
)
1355 int op
= (insn
>> 11);
1358 case 2: /* Branch */
1361 struct upk_mips16 upk
;
1362 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1363 offset
= upk
.offset
;
1369 pc
+= (offset
<< 1) + 2;
1372 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1374 struct upk_mips16 upk
;
1375 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1376 pc
= add_offset_16 (pc
, upk
.offset
);
1377 if ((insn
>> 10) & 0x01) /* Exchange mode */
1378 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1385 struct upk_mips16 upk
;
1387 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1388 reg
= read_signed_register (upk
.regx
);
1390 pc
+= (upk
.offset
<< 1) + 2;
1397 struct upk_mips16 upk
;
1399 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1400 reg
= read_signed_register (upk
.regx
);
1402 pc
+= (upk
.offset
<< 1) + 2;
1407 case 12: /* I8 Formats btez btnez */
1409 struct upk_mips16 upk
;
1411 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1412 /* upk.regx contains the opcode */
1413 reg
= read_signed_register (24); /* Test register is 24 */
1414 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1415 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1416 /* pc = add_offset_16(pc,upk.offset) ; */
1417 pc
+= (upk
.offset
<< 1) + 2;
1422 case 29: /* RR Formats JR, JALR, JALR-RA */
1424 struct upk_mips16 upk
;
1425 /* upk.fmt = rrtype; */
1430 upk
.regx
= (insn
>> 8) & 0x07;
1431 upk
.regy
= (insn
>> 5) & 0x07;
1439 break; /* Function return instruction */
1445 break; /* BOGUS Guess */
1447 pc
= read_signed_register (reg
);
1454 /* This is an instruction extension. Fetch the real instruction
1455 (which follows the extension) and decode things based on
1459 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1472 mips16_next_pc (CORE_ADDR pc
)
1474 unsigned int insn
= fetch_mips_16 (pc
);
1475 return extended_mips16_next_pc (pc
, 0, insn
);
1478 /* The mips_next_pc function supports single_step when the remote
1479 target monitor or stub is not developed enough to do a single_step.
1480 It works by decoding the current instruction and predicting where a
1481 branch will go. This isnt hard because all the data is available.
1482 The MIPS32 and MIPS16 variants are quite different */
1484 mips_next_pc (CORE_ADDR pc
)
1487 return mips16_next_pc (pc
);
1489 return mips32_next_pc (pc
);
1492 struct mips_frame_cache
1495 struct trad_frame_saved_reg
*saved_regs
;
1499 static struct mips_frame_cache
*
1500 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1502 mips_extra_func_info_t proc_desc
;
1503 struct mips_frame_cache
*cache
;
1504 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1506 /* r0 bit means kernel trap */
1508 /* What registers have been saved? Bitmasks. */
1509 unsigned long gen_mask
, float_mask
;
1511 if ((*this_cache
) != NULL
)
1512 return (*this_cache
);
1513 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1514 (*this_cache
) = cache
;
1515 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1517 /* Get the mdebug proc descriptor. */
1518 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1519 if (proc_desc
== NULL
)
1520 /* I'm not sure how/whether this can happen. Normally when we
1521 can't find a proc_desc, we "synthesize" one using
1522 heuristic_proc_desc and set the saved_regs right away. */
1525 /* Extract the frame's base. */
1526 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1527 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1529 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1530 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1531 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1533 /* In any frame other than the innermost or a frame interrupted by a
1534 signal, we assume that all registers have been saved. This
1535 assumes that all register saves in a function happen before the
1536 first function call. */
1537 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1538 /* Not sure exactly what kernel_trap means, but if it means the
1539 kernel saves the registers without a prologue doing it, we
1540 better not examine the prologue to see whether registers
1541 have been saved yet. */
1544 /* We need to figure out whether the registers that the
1545 proc_desc claims are saved have been saved yet. */
1549 /* Bitmasks; set if we have found a save for the register. */
1550 unsigned long gen_save_found
= 0;
1551 unsigned long float_save_found
= 0;
1554 /* If the address is odd, assume this is MIPS16 code. */
1555 addr
= PROC_LOW_ADDR (proc_desc
);
1556 mips16
= pc_is_mips16 (addr
);
1558 /* Scan through this function's instructions preceding the
1559 current PC, and look for those that save registers. */
1560 while (addr
< frame_pc_unwind (next_frame
))
1564 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1566 addr
+= MIPS16_INSTLEN
;
1570 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1571 &gen_save_found
, &float_save_found
);
1572 addr
+= MIPS_INSTLEN
;
1575 gen_mask
= gen_save_found
;
1576 float_mask
= float_save_found
;
1579 /* Fill in the offsets for the registers which gen_mask says were
1582 CORE_ADDR reg_position
= (cache
->base
1583 + PROC_REG_OFFSET (proc_desc
));
1585 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1586 if (gen_mask
& 0x80000000)
1588 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1589 reg_position
-= mips_abi_regsize (gdbarch
);
1593 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1594 order of that normally used by gcc. Therefore, we have to fetch
1595 the first instruction of the function, and if it's an entry
1596 instruction that saves $s0 or $s1, correct their saved addresses. */
1597 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1599 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1600 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1604 int sreg_count
= (inst
>> 6) & 3;
1606 /* Check if the ra register was pushed on the stack. */
1607 CORE_ADDR reg_position
= (cache
->base
1608 + PROC_REG_OFFSET (proc_desc
));
1610 reg_position
-= mips_abi_regsize (gdbarch
);
1612 /* Check if the s0 and s1 registers were pushed on the
1614 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1616 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1618 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1619 reg_position
-= mips_abi_regsize (gdbarch
);
1624 /* Fill in the offsets for the registers which float_mask says were
1627 CORE_ADDR reg_position
= (cache
->base
1628 + PROC_FREG_OFFSET (proc_desc
));
1630 /* Fill in the offsets for the float registers which float_mask
1632 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1633 if (float_mask
& 0x80000000)
1635 if (mips_abi_regsize (gdbarch
) == 4
1636 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1638 /* On a big endian 32 bit ABI, floating point registers
1639 are paired to form doubles such that the most
1640 significant part is in $f[N+1] and the least
1641 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1642 registers are also spilled as a pair and stored as a
1645 When little-endian the least significant part is
1646 stored first leading to the memory order $f[N] and
1649 Unfortunately, when big-endian the most significant
1650 part of the double is stored first, and the least
1651 significant is stored second. This leads to the
1652 registers being ordered in memory as firt $f[N+1] and
1655 For the big-endian case make certain that the
1656 addresses point at the correct (swapped) locations
1657 $f[N] and $f[N+1] pair (keep in mind that
1658 reg_position is decremented each time through the
1661 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1662 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1664 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1665 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1668 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1669 .addr
= reg_position
;
1670 reg_position
-= mips_abi_regsize (gdbarch
);
1673 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1674 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1677 /* SP_REGNUM, contains the value and not the address. */
1678 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ SP_REGNUM
, cache
->base
);
1680 return (*this_cache
);
1684 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1685 struct frame_id
*this_id
)
1687 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1689 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1693 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1695 int regnum
, int *optimizedp
,
1696 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1697 int *realnump
, void *valuep
)
1699 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1701 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
1702 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1705 static const struct frame_unwind mips_mdebug_frame_unwind
=
1708 mips_mdebug_frame_this_id
,
1709 mips_mdebug_frame_prev_register
1712 static const struct frame_unwind
*
1713 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1715 return &mips_mdebug_frame_unwind
;
1719 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1722 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1727 static const struct frame_base mips_mdebug_frame_base
= {
1728 &mips_mdebug_frame_unwind
,
1729 mips_mdebug_frame_base_address
,
1730 mips_mdebug_frame_base_address
,
1731 mips_mdebug_frame_base_address
1734 static const struct frame_base
*
1735 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1737 return &mips_mdebug_frame_base
;
1741 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1743 /* Always a pseudo. */
1744 gdb_assert (regno
>= NUM_REGS
);
1748 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1751 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1752 /* The SP_REGNUM is special, its value is stored in saved_regs.
1753 In fact, it is so special that it can even only be fetched
1754 using a raw register number! Once this code as been converted
1755 to frame-unwind the problem goes away. */
1756 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1758 return frame_unwind_register_signed (fi
, regno
);
1762 /* mips_addr_bits_remove - remove useless address bits */
1765 mips_addr_bits_remove (CORE_ADDR addr
)
1767 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1768 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1769 /* This hack is a work-around for existing boards using PMON, the
1770 simulator, and any other 64-bit targets that doesn't have true
1771 64-bit addressing. On these targets, the upper 32 bits of
1772 addresses are ignored by the hardware. Thus, the PC or SP are
1773 likely to have been sign extended to all 1s by instruction
1774 sequences that load 32-bit addresses. For example, a typical
1775 piece of code that loads an address is this:
1777 lui $r2, <upper 16 bits>
1778 ori $r2, <lower 16 bits>
1780 But the lui sign-extends the value such that the upper 32 bits
1781 may be all 1s. The workaround is simply to mask off these
1782 bits. In the future, gcc may be changed to support true 64-bit
1783 addressing, and this masking will have to be disabled. */
1784 return addr
&= 0xffffffffUL
;
1789 /* mips_software_single_step() is called just before we want to resume
1790 the inferior, if we want to single-step it but there is no hardware
1791 or kernel single-step support (MIPS on GNU/Linux for example). We find
1792 the target of the coming instruction and breakpoint it.
1794 single_step is also called just after the inferior stops. If we had
1795 set up a simulated single-step, we undo our damage. */
1798 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1800 static CORE_ADDR next_pc
;
1801 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1802 static binsn_quantum break_mem
;
1805 if (insert_breakpoints_p
)
1807 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
1808 next_pc
= mips_next_pc (pc
);
1810 target_insert_breakpoint (next_pc
, break_mem
);
1813 target_remove_breakpoint (next_pc
, break_mem
);
1816 static struct mips_extra_func_info temp_proc_desc
;
1818 /* This hack will go away once the get_prev_frame() code has been
1819 modified to set the frame's type first. That is BEFORE init extra
1820 frame info et.al. is called. This is because it will become
1821 possible to skip the init extra info call for sigtramp and dummy
1823 static CORE_ADDR
*temp_saved_regs
;
1825 /* Set a register's saved stack address in temp_saved_regs. If an
1826 address has already been set for this register, do nothing; this
1827 way we will only recognize the first save of a given register in a
1830 For simplicity, save the address in both [0 .. NUM_REGS) and
1831 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1832 is used as it is only second range (the ABI instead of ISA
1833 registers) that comes into play when finding saved registers in a
1837 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1839 if (saved_regs
[regno
] == 0)
1841 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1842 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1847 /* Test whether the PC points to the return instruction at the
1848 end of a function. */
1851 mips_about_to_return (CORE_ADDR pc
)
1853 if (pc_is_mips16 (pc
))
1854 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1855 generates a "jr $ra"; other times it generates code to load
1856 the return address from the stack to an accessible register (such
1857 as $a3), then a "jr" using that register. This second case
1858 is almost impossible to distinguish from an indirect jump
1859 used for switch statements, so we don't even try. */
1860 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1862 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1866 /* This fencepost looks highly suspicious to me. Removing it also
1867 seems suspicious as it could affect remote debugging across serial
1871 heuristic_proc_start (CORE_ADDR pc
)
1878 pc
= ADDR_BITS_REMOVE (pc
);
1880 fence
= start_pc
- heuristic_fence_post
;
1884 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
1885 fence
= VM_MIN_ADDRESS
;
1887 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1889 /* search back for previous return */
1890 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1891 if (start_pc
< fence
)
1893 /* It's not clear to me why we reach this point when
1894 stop_soon, but with this test, at least we
1895 don't print out warnings for every child forked (eg, on
1896 decstation). 22apr93 rich@cygnus.com. */
1897 if (stop_soon
== NO_STOP_QUIETLY
)
1899 static int blurb_printed
= 0;
1902 ("GDB can't find the start of the function at 0x%s.",
1907 /* This actually happens frequently in embedded
1908 development, when you first connect to a board
1909 and your stack pointer and pc are nowhere in
1910 particular. This message needs to give people
1911 in that situation enough information to
1912 determine that it's no big deal. */
1913 printf_filtered ("\n\
1914 GDB is unable to find the start of the function at 0x%s\n\
1915 and thus can't determine the size of that function's stack frame.\n\
1916 This means that GDB may be unable to access that stack frame, or\n\
1917 the frames below it.\n\
1918 This problem is most likely caused by an invalid program counter or\n\
1920 However, if you think GDB should simply search farther back\n\
1921 from 0x%s for code which looks like the beginning of a\n\
1922 function, you can increase the range of the search using the `set\n\
1923 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
1930 else if (pc_is_mips16 (start_pc
))
1932 unsigned short inst
;
1934 /* On MIPS16, any one of the following is likely to be the
1935 start of a function:
1939 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1940 inst
= mips_fetch_instruction (start_pc
);
1941 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1942 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1943 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1944 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1946 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1947 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1952 else if (mips_about_to_return (start_pc
))
1954 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1961 /* Fetch the immediate value from a MIPS16 instruction.
1962 If the previous instruction was an EXTEND, use it to extend
1963 the upper bits of the immediate value. This is a helper function
1964 for mips16_heuristic_proc_desc. */
1967 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1968 unsigned short inst
, /* current instruction */
1969 int nbits
, /* number of bits in imm field */
1970 int scale
, /* scale factor to be applied to imm */
1971 int is_signed
) /* is the imm field signed? */
1975 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1977 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1978 if (offset
& 0x8000) /* check for negative extend */
1979 offset
= 0 - (0x10000 - (offset
& 0xffff));
1980 return offset
| (inst
& 0x1f);
1984 int max_imm
= 1 << nbits
;
1985 int mask
= max_imm
- 1;
1986 int sign_bit
= max_imm
>> 1;
1988 offset
= inst
& mask
;
1989 if (is_signed
&& (offset
& sign_bit
))
1990 offset
= 0 - (max_imm
- offset
);
1991 return offset
* scale
;
1996 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1997 stream from start_pc to limit_pc. */
2000 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2001 struct frame_info
*next_frame
, CORE_ADDR sp
)
2004 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2005 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2006 unsigned inst
= 0; /* current instruction */
2007 unsigned entry_inst
= 0; /* the entry instruction */
2009 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2011 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2012 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2014 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2016 /* Save the previous instruction. If it's an EXTEND, we'll extract
2017 the immediate offset extension from it in mips16_get_imm. */
2020 /* Fetch and decode the instruction. */
2021 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2022 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2023 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2025 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2026 if (offset
< 0) /* negative stack adjustment? */
2027 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2029 /* Exit loop if a positive stack adjustment is found, which
2030 usually means that the stack cleanup code in the function
2031 epilogue is reached. */
2034 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2036 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2037 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2038 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2039 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2041 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2043 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2044 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2045 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2046 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2048 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2050 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2051 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2052 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2054 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2056 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2057 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2058 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2060 else if (inst
== 0x673d) /* move $s1, $sp */
2063 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2065 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2067 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2068 frame_addr
= sp
+ offset
;
2069 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2070 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2072 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2074 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2075 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2076 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2077 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2079 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2081 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2082 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2083 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2084 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2086 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2087 entry_inst
= inst
; /* save for later processing */
2088 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2089 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2092 /* The entry instruction is typically the first instruction in a function,
2093 and it stores registers at offsets relative to the value of the old SP
2094 (before the prologue). But the value of the sp parameter to this
2095 function is the new SP (after the prologue has been executed). So we
2096 can't calculate those offsets until we've seen the entire prologue,
2097 and can calculate what the old SP must have been. */
2098 if (entry_inst
!= 0)
2100 int areg_count
= (entry_inst
>> 8) & 7;
2101 int sreg_count
= (entry_inst
>> 6) & 3;
2103 /* The entry instruction always subtracts 32 from the SP. */
2104 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2106 /* Now we can calculate what the SP must have been at the
2107 start of the function prologue. */
2108 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2110 /* Check if a0-a3 were saved in the caller's argument save area. */
2111 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2113 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2114 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2115 offset
+= mips_abi_regsize (current_gdbarch
);
2118 /* Check if the ra register was pushed on the stack. */
2120 if (entry_inst
& 0x20)
2122 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2123 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2124 offset
-= mips_abi_regsize (current_gdbarch
);
2127 /* Check if the s0 and s1 registers were pushed on the stack. */
2128 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2130 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2131 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2132 offset
-= mips_abi_regsize (current_gdbarch
);
2138 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2139 struct frame_info
*next_frame
, CORE_ADDR sp
)
2142 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2144 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2145 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2146 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2147 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2148 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2150 unsigned long inst
, high_word
, low_word
;
2153 /* Fetch the instruction. */
2154 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2156 /* Save some code by pre-extracting some useful fields. */
2157 high_word
= (inst
>> 16) & 0xffff;
2158 low_word
= inst
& 0xffff;
2159 reg
= high_word
& 0x1f;
2161 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2162 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2163 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2165 if (low_word
& 0x8000) /* negative stack adjustment? */
2166 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2168 /* Exit loop if a positive stack adjustment is found, which
2169 usually means that the stack cleanup code in the function
2170 epilogue is reached. */
2173 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2175 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2176 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2178 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2180 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2181 but the register size used is only 32 bits. Make the address
2182 for the saved register point to the lower 32 bits. */
2183 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2184 set_reg_offset (temp_saved_regs
, reg
,
2185 sp
+ low_word
+ 8 - mips_isa_regsize (current_gdbarch
));
2187 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2189 /* Old gcc frame, r30 is virtual frame pointer. */
2190 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2191 frame_addr
= sp
+ low_word
;
2192 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2194 unsigned alloca_adjust
;
2195 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2196 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2197 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2198 if (alloca_adjust
> 0)
2200 /* FP > SP + frame_size. This may be because
2201 * of an alloca or somethings similar.
2202 * Fix sp to "pre-alloca" value, and try again.
2204 sp
+= alloca_adjust
;
2209 /* move $30,$sp. With different versions of gas this will be either
2210 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2211 Accept any one of these. */
2212 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2214 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2215 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2217 unsigned alloca_adjust
;
2218 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2219 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2220 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2221 if (alloca_adjust
> 0)
2223 /* FP > SP + frame_size. This may be because
2224 * of an alloca or somethings similar.
2225 * Fix sp to "pre-alloca" value, and try again.
2227 sp
+= alloca_adjust
;
2232 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2234 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2235 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2240 static mips_extra_func_info_t
2241 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2242 struct frame_info
*next_frame
, int cur_frame
)
2247 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2253 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2254 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2255 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2256 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2257 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2258 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2260 if (start_pc
+ 200 < limit_pc
)
2261 limit_pc
= start_pc
+ 200;
2262 if (pc_is_mips16 (start_pc
))
2263 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2265 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2266 return &temp_proc_desc
;
2269 struct mips_objfile_private
2275 /* Global used to communicate between non_heuristic_proc_desc and
2276 compare_pdr_entries within qsort (). */
2277 static bfd
*the_bfd
;
2280 compare_pdr_entries (const void *a
, const void *b
)
2282 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2283 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2287 else if (lhs
== rhs
)
2293 static mips_extra_func_info_t
2294 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2296 CORE_ADDR startaddr
;
2297 mips_extra_func_info_t proc_desc
;
2298 struct block
*b
= block_for_pc (pc
);
2300 struct obj_section
*sec
;
2301 struct mips_objfile_private
*priv
;
2303 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2306 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2308 *addrptr
= startaddr
;
2312 sec
= find_pc_section (pc
);
2315 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2317 /* Search the ".pdr" section generated by GAS. This includes most of
2318 the information normally found in ECOFF PDRs. */
2320 the_bfd
= sec
->objfile
->obfd
;
2322 && (the_bfd
->format
== bfd_object
2323 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2324 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2326 /* Right now GAS only outputs the address as a four-byte sequence.
2327 This means that we should not bother with this method on 64-bit
2328 targets (until that is fixed). */
2330 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2331 sizeof (struct mips_objfile_private
));
2333 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2335 else if (priv
== NULL
)
2339 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2340 sizeof (struct mips_objfile_private
));
2342 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2345 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2346 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2348 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2349 priv
->contents
, 0, priv
->size
);
2351 /* In general, the .pdr section is sorted. However, in the
2352 presence of multiple code sections (and other corner cases)
2353 it can become unsorted. Sort it so that we can use a faster
2355 qsort (priv
->contents
, priv
->size
/ 32, 32,
2356 compare_pdr_entries
);
2361 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2365 if (priv
->size
!= 0)
2372 high
= priv
->size
/ 32;
2374 /* We've found a .pdr section describing this objfile. We want to
2375 find the entry which describes this code address. The .pdr
2376 information is not very descriptive; we have only a function
2377 start address. We have to look for the closest entry, because
2378 the local symbol at the beginning of this function may have
2379 been stripped - so if we ask the symbol table for the start
2380 address we may get a preceding global function. */
2382 /* First, find the last .pdr entry starting at or before PC. */
2385 mid
= (low
+ high
) / 2;
2387 ptr
= priv
->contents
+ mid
* 32;
2388 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2389 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2390 SECT_OFF_TEXT (sec
->objfile
));
2397 while (low
!= high
);
2399 /* Both low and high point one past the PDR of interest. If
2400 both are zero, that means this PC is before any region
2401 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2405 ptr
= priv
->contents
+ (low
- 1) * 32;
2406 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2407 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2408 SECT_OFF_TEXT (sec
->objfile
));
2411 /* We don't have a range, so we have no way to know for sure
2412 whether we're in the correct PDR or a PDR for a preceding
2413 function and the current function was a stripped local
2414 symbol. But if the PDR's PC is at least as great as the
2415 best guess from the symbol table, assume that it does cover
2416 the right area; if a .pdr section is present at all then
2417 nearly every function will have an entry. The biggest exception
2418 will be the dynamic linker stubs; conveniently these are
2419 placed before .text instead of after. */
2421 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2423 struct symbol
*sym
= find_pc_function (pc
);
2428 /* Fill in what we need of the proc_desc. */
2429 proc_desc
= (mips_extra_func_info_t
)
2430 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2431 sizeof (struct mips_extra_func_info
));
2432 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2434 /* Only used for dummy frames. */
2435 PROC_HIGH_ADDR (proc_desc
) = 0;
2437 PROC_FRAME_OFFSET (proc_desc
)
2438 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2439 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2441 PROC_FRAME_ADJUST (proc_desc
) = 0;
2442 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2444 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2446 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2448 PROC_FREG_OFFSET (proc_desc
)
2449 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2450 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2452 proc_desc
->pdr
.isym
= (long) sym
;
2462 if (startaddr
> BLOCK_START (b
))
2464 /* This is the "pathological" case referred to in a comment in
2465 print_frame_info. It might be better to move this check into
2470 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2472 /* If we never found a PDR for this function in symbol reading, then
2473 examine prologues to find the information. */
2476 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2477 if (PROC_FRAME_REG (proc_desc
) == -1)
2487 static mips_extra_func_info_t
2488 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2490 mips_extra_func_info_t proc_desc
;
2491 CORE_ADDR startaddr
= 0;
2493 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2497 /* IF this is the topmost frame AND
2498 * (this proc does not have debugging information OR
2499 * the PC is in the procedure prologue)
2500 * THEN create a "heuristic" proc_desc (by analyzing
2501 * the actual code) to replace the "official" proc_desc.
2503 if (next_frame
== NULL
)
2505 struct symtab_and_line val
;
2506 struct symbol
*proc_symbol
=
2507 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2511 val
= find_pc_line (BLOCK_START
2512 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
2513 val
.pc
= val
.end
? val
.end
: pc
;
2515 if (!proc_symbol
|| pc
< val
.pc
)
2517 mips_extra_func_info_t found_heuristic
=
2518 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2519 pc
, next_frame
, cur_frame
);
2520 if (found_heuristic
)
2521 proc_desc
= found_heuristic
;
2527 /* Is linked_proc_desc_table really necessary? It only seems to be used
2528 by procedure call dummys. However, the procedures being called ought
2529 to have their own proc_descs, and even if they don't,
2530 heuristic_proc_desc knows how to create them! */
2532 struct linked_proc_info
*link
;
2534 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2535 if (PROC_LOW_ADDR (&link
->info
) <= pc
2536 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2540 startaddr
= heuristic_proc_start (pc
);
2542 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2547 /* MIPS stack frames are almost impenetrable. When execution stops,
2548 we basically have to look at symbol information for the function
2549 that we stopped in, which tells us *which* register (if any) is
2550 the base of the frame pointer, and what offset from that register
2551 the frame itself is at.
2553 This presents a problem when trying to examine a stack in memory
2554 (that isn't executing at the moment), using the "frame" command. We
2555 don't have a PC, nor do we have any registers except SP.
2557 This routine takes two arguments, SP and PC, and tries to make the
2558 cached frames look as if these two arguments defined a frame on the
2559 cache. This allows the rest of info frame to extract the important
2560 arguments without difficulty. */
2563 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2566 error ("MIPS frame specifications require two arguments: sp and pc");
2568 return create_new_frame (argv
[0], argv
[1]);
2571 /* According to the current ABI, should the type be passed in a
2572 floating-point register (assuming that there is space)? When there
2573 is no FPU, FP are not even considered as possibile candidates for
2574 FP registers and, consequently this returns false - forces FP
2575 arguments into integer registers. */
2578 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2580 return ((typecode
== TYPE_CODE_FLT
2582 && (typecode
== TYPE_CODE_STRUCT
2583 || typecode
== TYPE_CODE_UNION
)
2584 && TYPE_NFIELDS (arg_type
) == 1
2585 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2586 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2589 /* On o32, argument passing in GPRs depends on the alignment of the type being
2590 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2593 mips_type_needs_double_align (struct type
*type
)
2595 enum type_code typecode
= TYPE_CODE (type
);
2597 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2599 else if (typecode
== TYPE_CODE_STRUCT
)
2601 if (TYPE_NFIELDS (type
) < 1)
2603 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2605 else if (typecode
== TYPE_CODE_UNION
)
2609 n
= TYPE_NFIELDS (type
);
2610 for (i
= 0; i
< n
; i
++)
2611 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2618 /* Adjust the address downward (direction of stack growth) so that it
2619 is correctly aligned for a new stack frame. */
2621 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2623 return align_down (addr
, 16);
2626 /* Determine how a return value is stored within the MIPS register
2627 file, given the return type `valtype'. */
2629 struct return_value_word
2638 return_value_location (struct type
*valtype
,
2639 struct return_value_word
*hi
,
2640 struct return_value_word
*lo
)
2642 int len
= TYPE_LENGTH (valtype
);
2643 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2645 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2646 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2647 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2649 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2651 /* We need to break a 64bit float in two 32 bit halves and
2652 spread them across a floating-point register pair. */
2653 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2654 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
2655 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2656 && register_size (current_gdbarch
,
2657 mips_regnum (current_gdbarch
)->
2658 fp0
) == 8) ? 4 : 0);
2659 hi
->reg_offset
= lo
->reg_offset
;
2660 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
2661 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
2667 /* The floating point value fits in a single floating-point
2669 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2670 && register_size (current_gdbarch
,
2671 mips_regnum (current_gdbarch
)->
2673 && len
== 4) ? 4 : 0);
2674 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
2685 /* Locate a result possibly spread across two registers. */
2687 lo
->reg
= regnum
+ 0;
2688 hi
->reg
= regnum
+ 1;
2689 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2690 && len
< mips_abi_regsize (current_gdbarch
))
2692 /* "un-left-justify" the value in the low register */
2693 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
2698 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
2699 && len
< mips_abi_regsize (current_gdbarch
) * 2
2700 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2701 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2703 /* "un-left-justify" the value spread across two registers. */
2704 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
2705 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
2707 hi
->len
= len
- lo
->len
;
2711 /* Only perform a partial copy of the second register. */
2714 if (len
> mips_abi_regsize (current_gdbarch
))
2716 lo
->len
= mips_abi_regsize (current_gdbarch
);
2717 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
2725 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2726 && register_size (current_gdbarch
, regnum
) == 8
2727 && mips_abi_regsize (current_gdbarch
) == 4)
2729 /* Account for the fact that only the least-signficant part
2730 of the register is being used */
2731 lo
->reg_offset
+= 4;
2732 hi
->reg_offset
+= 4;
2735 hi
->buf_offset
= lo
->len
;
2739 /* Should call_function allocate stack space for a struct return? */
2742 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
2744 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2745 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
2748 /* Should call_function pass struct by reference?
2749 For each architecture, structs are passed either by
2750 value or by reference, depending on their size. */
2753 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2755 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
2756 int len
= TYPE_LENGTH (check_typedef (type
));
2757 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2759 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2760 return (len
> mips_abi_regsize (current_gdbarch
));
2766 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2767 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2768 int nargs
, struct value
**args
, CORE_ADDR sp
,
2769 int struct_return
, CORE_ADDR struct_addr
)
2775 int stack_offset
= 0;
2776 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2778 /* For shared libraries, "t9" needs to point at the function
2780 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2782 /* Set the return address register to point to the entry point of
2783 the program, where a breakpoint lies in wait. */
2784 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2786 /* First ensure that the stack and structure return address (if any)
2787 are properly aligned. The stack has to be at least 64-bit
2788 aligned even on 32-bit machines, because doubles must be 64-bit
2789 aligned. For n32 and n64, stack frames need to be 128-bit
2790 aligned, so we round to this widest known alignment. */
2792 sp
= align_down (sp
, 16);
2793 struct_addr
= align_down (struct_addr
, 16);
2795 /* Now make space on the stack for the args. We allocate more
2796 than necessary for EABI, because the first few arguments are
2797 passed in registers, but that's OK. */
2798 for (argnum
= 0; argnum
< nargs
; argnum
++)
2799 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2800 mips_stack_argsize (gdbarch
));
2801 sp
-= align_up (len
, 16);
2804 fprintf_unfiltered (gdb_stdlog
,
2805 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2806 paddr_nz (sp
), (long) align_up (len
, 16));
2808 /* Initialize the integer and float register pointers. */
2810 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2812 /* The struct_return pointer occupies the first parameter-passing reg. */
2816 fprintf_unfiltered (gdb_stdlog
,
2817 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2818 argreg
, paddr_nz (struct_addr
));
2819 write_register (argreg
++, struct_addr
);
2822 /* Now load as many as possible of the first arguments into
2823 registers, and push the rest onto the stack. Loop thru args
2824 from first to last. */
2825 for (argnum
= 0; argnum
< nargs
; argnum
++)
2828 char valbuf
[MAX_REGISTER_SIZE
];
2829 struct value
*arg
= args
[argnum
];
2830 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2831 int len
= TYPE_LENGTH (arg_type
);
2832 enum type_code typecode
= TYPE_CODE (arg_type
);
2835 fprintf_unfiltered (gdb_stdlog
,
2836 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2837 argnum
+ 1, len
, (int) typecode
);
2839 /* The EABI passes structures that do not fit in a register by
2841 if (len
> mips_abi_regsize (gdbarch
)
2842 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2844 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2845 VALUE_ADDRESS (arg
));
2846 typecode
= TYPE_CODE_PTR
;
2847 len
= mips_abi_regsize (gdbarch
);
2850 fprintf_unfiltered (gdb_stdlog
, " push");
2853 val
= (char *) VALUE_CONTENTS (arg
);
2855 /* 32-bit ABIs always start floating point arguments in an
2856 even-numbered floating point register. Round the FP register
2857 up before the check to see if there are any FP registers
2858 left. Non MIPS_EABI targets also pass the FP in the integer
2859 registers so also round up normal registers. */
2860 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
2862 if ((float_argreg
& 1))
2866 /* Floating point arguments passed in registers have to be
2867 treated specially. On 32-bit architectures, doubles
2868 are passed in register pairs; the even register gets
2869 the low word, and the odd register gets the high word.
2870 On non-EABI processors, the first two floating point arguments are
2871 also copied to general registers, because MIPS16 functions
2872 don't use float registers for arguments. This duplication of
2873 arguments in general registers can't hurt non-MIPS16 functions
2874 because those registers are normally skipped. */
2875 /* MIPS_EABI squeezes a struct that contains a single floating
2876 point value into an FP register instead of pushing it onto the
2878 if (fp_register_arg_p (typecode
, arg_type
)
2879 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2881 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2883 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2884 unsigned long regval
;
2886 /* Write the low word of the double to the even register(s). */
2887 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2889 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2890 float_argreg
, phex (regval
, 4));
2891 write_register (float_argreg
++, regval
);
2893 /* Write the high word of the double to the odd register(s). */
2894 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2896 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2897 float_argreg
, phex (regval
, 4));
2898 write_register (float_argreg
++, regval
);
2902 /* This is a floating point value that fits entirely
2903 in a single register. */
2904 /* On 32 bit ABI's the float_argreg is further adjusted
2905 above to ensure that it is even register aligned. */
2906 LONGEST regval
= extract_unsigned_integer (val
, len
);
2908 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2909 float_argreg
, phex (regval
, len
));
2910 write_register (float_argreg
++, regval
);
2915 /* Copy the argument to general registers or the stack in
2916 register-sized pieces. Large arguments are split between
2917 registers and stack. */
2918 /* Note: structs whose size is not a multiple of
2919 mips_isa_regsize() are treated specially: Irix cc passes them
2920 in registers where gcc sometimes puts them on the stack.
2921 For maximum compatibility, we will put them in both
2923 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2924 && (len
% mips_abi_regsize (gdbarch
) != 0));
2926 /* Note: Floating-point values that didn't fit into an FP
2927 register are only written to memory. */
2930 /* Remember if the argument was written to the stack. */
2931 int stack_used_p
= 0;
2932 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2933 ? len
: mips_abi_regsize (gdbarch
));
2936 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2939 /* Write this portion of the argument to the stack. */
2940 if (argreg
> MIPS_LAST_ARG_REGNUM
2942 || fp_register_arg_p (typecode
, arg_type
))
2944 /* Should shorter than int integer values be
2945 promoted to int before being stored? */
2946 int longword_offset
= 0;
2949 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2951 if (mips_stack_argsize (gdbarch
) == 8
2952 && (typecode
== TYPE_CODE_INT
2953 || typecode
== TYPE_CODE_PTR
2954 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2955 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2956 else if ((typecode
== TYPE_CODE_STRUCT
2957 || typecode
== TYPE_CODE_UNION
)
2958 && (TYPE_LENGTH (arg_type
)
2959 < mips_stack_argsize (gdbarch
)))
2960 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2965 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2966 paddr_nz (stack_offset
));
2967 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2968 paddr_nz (longword_offset
));
2971 addr
= sp
+ stack_offset
+ longword_offset
;
2976 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2978 for (i
= 0; i
< partial_len
; i
++)
2980 fprintf_unfiltered (gdb_stdlog
, "%02x",
2984 write_memory (addr
, val
, partial_len
);
2987 /* Note!!! This is NOT an else clause. Odd sized
2988 structs may go thru BOTH paths. Floating point
2989 arguments will not. */
2990 /* Write this portion of the argument to a general
2991 purpose register. */
2992 if (argreg
<= MIPS_LAST_ARG_REGNUM
2993 && !fp_register_arg_p (typecode
, arg_type
))
2996 extract_unsigned_integer (val
, partial_len
);
2999 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3002 mips_abi_regsize (gdbarch
)));
3003 write_register (argreg
, regval
);
3010 /* Compute the the offset into the stack at which we
3011 will copy the next parameter.
3013 In the new EABI (and the NABI32), the stack_offset
3014 only needs to be adjusted when it has been used. */
3017 stack_offset
+= align_up (partial_len
,
3018 mips_stack_argsize (gdbarch
));
3022 fprintf_unfiltered (gdb_stdlog
, "\n");
3025 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3027 /* Return adjusted stack pointer. */
3031 /* Given a return value in `regbuf' with a type `valtype', extract and
3032 copy its value into `valbuf'. */
3035 mips_eabi_extract_return_value (struct type
*valtype
,
3036 char regbuf
[], char *valbuf
)
3038 struct return_value_word lo
;
3039 struct return_value_word hi
;
3040 return_value_location (valtype
, &hi
, &lo
);
3042 memcpy (valbuf
+ lo
.buf_offset
,
3043 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3044 lo
.reg_offset
, lo
.len
);
3047 memcpy (valbuf
+ hi
.buf_offset
,
3048 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3049 hi
.reg_offset
, hi
.len
);
3052 /* Given a return value in `valbuf' with a type `valtype', write it's
3053 value into the appropriate register. */
3056 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3058 char raw_buffer
[MAX_REGISTER_SIZE
];
3059 struct return_value_word lo
;
3060 struct return_value_word hi
;
3061 return_value_location (valtype
, &hi
, &lo
);
3063 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3064 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3065 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3066 raw_buffer
, register_size (current_gdbarch
,
3071 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3072 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3073 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3075 register_size (current_gdbarch
,
3080 /* N32/N64 ABI stuff. */
3083 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3084 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3085 int nargs
, struct value
**args
, CORE_ADDR sp
,
3086 int struct_return
, CORE_ADDR struct_addr
)
3092 int stack_offset
= 0;
3093 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3095 /* For shared libraries, "t9" needs to point at the function
3097 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3099 /* Set the return address register to point to the entry point of
3100 the program, where a breakpoint lies in wait. */
3101 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3103 /* First ensure that the stack and structure return address (if any)
3104 are properly aligned. The stack has to be at least 64-bit
3105 aligned even on 32-bit machines, because doubles must be 64-bit
3106 aligned. For n32 and n64, stack frames need to be 128-bit
3107 aligned, so we round to this widest known alignment. */
3109 sp
= align_down (sp
, 16);
3110 struct_addr
= align_down (struct_addr
, 16);
3112 /* Now make space on the stack for the args. */
3113 for (argnum
= 0; argnum
< nargs
; argnum
++)
3114 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3115 mips_stack_argsize (gdbarch
));
3116 sp
-= align_up (len
, 16);
3119 fprintf_unfiltered (gdb_stdlog
,
3120 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3121 paddr_nz (sp
), (long) align_up (len
, 16));
3123 /* Initialize the integer and float register pointers. */
3125 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3127 /* The struct_return pointer occupies the first parameter-passing reg. */
3131 fprintf_unfiltered (gdb_stdlog
,
3132 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3133 argreg
, paddr_nz (struct_addr
));
3134 write_register (argreg
++, struct_addr
);
3137 /* Now load as many as possible of the first arguments into
3138 registers, and push the rest onto the stack. Loop thru args
3139 from first to last. */
3140 for (argnum
= 0; argnum
< nargs
; argnum
++)
3143 struct value
*arg
= args
[argnum
];
3144 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3145 int len
= TYPE_LENGTH (arg_type
);
3146 enum type_code typecode
= TYPE_CODE (arg_type
);
3149 fprintf_unfiltered (gdb_stdlog
,
3150 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3151 argnum
+ 1, len
, (int) typecode
);
3153 val
= (char *) VALUE_CONTENTS (arg
);
3155 if (fp_register_arg_p (typecode
, arg_type
)
3156 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3158 /* This is a floating point value that fits entirely
3159 in a single register. */
3160 /* On 32 bit ABI's the float_argreg is further adjusted
3161 above to ensure that it is even register aligned. */
3162 LONGEST regval
= extract_unsigned_integer (val
, len
);
3164 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3165 float_argreg
, phex (regval
, len
));
3166 write_register (float_argreg
++, regval
);
3169 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3170 argreg
, phex (regval
, len
));
3171 write_register (argreg
, regval
);
3176 /* Copy the argument to general registers or the stack in
3177 register-sized pieces. Large arguments are split between
3178 registers and stack. */
3179 /* Note: structs whose size is not a multiple of
3180 mips_isa_regsize() are treated specially: Irix cc passes them
3181 in registers where gcc sometimes puts them on the stack.
3182 For maximum compatibility, we will put them in both
3184 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3185 && (len
% mips_abi_regsize (gdbarch
) != 0));
3186 /* Note: Floating-point values that didn't fit into an FP
3187 register are only written to memory. */
3190 /* Rememer if the argument was written to the stack. */
3191 int stack_used_p
= 0;
3192 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3193 ? len
: mips_abi_regsize (gdbarch
));
3196 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3199 /* Write this portion of the argument to the stack. */
3200 if (argreg
> MIPS_LAST_ARG_REGNUM
3202 || fp_register_arg_p (typecode
, arg_type
))
3204 /* Should shorter than int integer values be
3205 promoted to int before being stored? */
3206 int longword_offset
= 0;
3209 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3211 if (mips_stack_argsize (gdbarch
) == 8
3212 && (typecode
== TYPE_CODE_INT
3213 || typecode
== TYPE_CODE_PTR
3214 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3215 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3220 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3221 paddr_nz (stack_offset
));
3222 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3223 paddr_nz (longword_offset
));
3226 addr
= sp
+ stack_offset
+ longword_offset
;
3231 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3233 for (i
= 0; i
< partial_len
; i
++)
3235 fprintf_unfiltered (gdb_stdlog
, "%02x",
3239 write_memory (addr
, val
, partial_len
);
3242 /* Note!!! This is NOT an else clause. Odd sized
3243 structs may go thru BOTH paths. Floating point
3244 arguments will not. */
3245 /* Write this portion of the argument to a general
3246 purpose register. */
3247 if (argreg
<= MIPS_LAST_ARG_REGNUM
3248 && !fp_register_arg_p (typecode
, arg_type
))
3251 extract_unsigned_integer (val
, partial_len
);
3253 /* A non-floating-point argument being passed in a
3254 general register. If a struct or union, and if
3255 the remaining length is smaller than the register
3256 size, we have to adjust the register value on
3259 It does not seem to be necessary to do the
3260 same for integral types.
3262 cagney/2001-07-23: gdb/179: Also, GCC, when
3263 outputting LE O32 with sizeof (struct) <
3264 mips_abi_regsize(), generates a left shift as
3265 part of storing the argument in a register a
3266 register (the left shift isn't generated when
3267 sizeof (struct) >= mips_abi_regsize()). Since
3268 it is quite possible that this is GCC
3269 contradicting the LE/O32 ABI, GDB has not been
3270 adjusted to accommodate this. Either someone
3271 needs to demonstrate that the LE/O32 ABI
3272 specifies such a left shift OR this new ABI gets
3273 identified as such and GDB gets tweaked
3276 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3277 && partial_len
< mips_abi_regsize (gdbarch
)
3278 && (typecode
== TYPE_CODE_STRUCT
||
3279 typecode
== TYPE_CODE_UNION
))
3280 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3284 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3287 mips_abi_regsize (gdbarch
)));
3288 write_register (argreg
, regval
);
3295 /* Compute the the offset into the stack at which we
3296 will copy the next parameter.
3298 In N32 (N64?), the stack_offset only needs to be
3299 adjusted when it has been used. */
3302 stack_offset
+= align_up (partial_len
,
3303 mips_stack_argsize (gdbarch
));
3307 fprintf_unfiltered (gdb_stdlog
, "\n");
3310 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3312 /* Return adjusted stack pointer. */
3316 static enum return_value_convention
3317 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3318 struct type
*type
, struct regcache
*regcache
,
3319 void *readbuf
, const void *writebuf
)
3321 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3322 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3323 || TYPE_CODE (type
) == TYPE_CODE_UNION
3324 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3325 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3326 return RETURN_VALUE_STRUCT_CONVENTION
;
3327 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3328 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3330 /* A floating-point value belongs in the least significant part
3333 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3334 mips_xfer_register (regcache
,
3335 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3337 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3338 return RETURN_VALUE_REGISTER_CONVENTION
;
3340 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3341 && TYPE_NFIELDS (type
) <= 2
3342 && TYPE_NFIELDS (type
) >= 1
3343 && ((TYPE_NFIELDS (type
) == 1
3344 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3346 || (TYPE_NFIELDS (type
) == 2
3347 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3349 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3351 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3353 /* A struct that contains one or two floats. Each value is part
3354 in the least significant part of their floating point
3358 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3359 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3361 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3364 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3366 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3367 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3368 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3370 return RETURN_VALUE_REGISTER_CONVENTION
;
3372 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3373 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3375 /* A structure or union. Extract the left justified value,
3376 regardless of the byte order. I.e. DO NOT USE
3380 for (offset
= 0, regnum
= V0_REGNUM
;
3381 offset
< TYPE_LENGTH (type
);
3382 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3384 int xfer
= register_size (current_gdbarch
, regnum
);
3385 if (offset
+ xfer
> TYPE_LENGTH (type
))
3386 xfer
= TYPE_LENGTH (type
) - offset
;
3388 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3389 offset
, xfer
, regnum
);
3390 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3391 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3393 return RETURN_VALUE_REGISTER_CONVENTION
;
3397 /* A scalar extract each part but least-significant-byte
3401 for (offset
= 0, regnum
= V0_REGNUM
;
3402 offset
< TYPE_LENGTH (type
);
3403 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3405 int xfer
= register_size (current_gdbarch
, regnum
);
3406 if (offset
+ xfer
> TYPE_LENGTH (type
))
3407 xfer
= TYPE_LENGTH (type
) - offset
;
3409 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3410 offset
, xfer
, regnum
);
3411 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3412 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3414 return RETURN_VALUE_REGISTER_CONVENTION
;
3418 /* O32 ABI stuff. */
3421 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3422 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3423 int nargs
, struct value
**args
, CORE_ADDR sp
,
3424 int struct_return
, CORE_ADDR struct_addr
)
3430 int stack_offset
= 0;
3431 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3433 /* For shared libraries, "t9" needs to point at the function
3435 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3437 /* Set the return address register to point to the entry point of
3438 the program, where a breakpoint lies in wait. */
3439 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3441 /* First ensure that the stack and structure return address (if any)
3442 are properly aligned. The stack has to be at least 64-bit
3443 aligned even on 32-bit machines, because doubles must be 64-bit
3444 aligned. For n32 and n64, stack frames need to be 128-bit
3445 aligned, so we round to this widest known alignment. */
3447 sp
= align_down (sp
, 16);
3448 struct_addr
= align_down (struct_addr
, 16);
3450 /* Now make space on the stack for the args. */
3451 for (argnum
= 0; argnum
< nargs
; argnum
++)
3452 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3453 mips_stack_argsize (gdbarch
));
3454 sp
-= align_up (len
, 16);
3457 fprintf_unfiltered (gdb_stdlog
,
3458 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3459 paddr_nz (sp
), (long) align_up (len
, 16));
3461 /* Initialize the integer and float register pointers. */
3463 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3465 /* The struct_return pointer occupies the first parameter-passing reg. */
3469 fprintf_unfiltered (gdb_stdlog
,
3470 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3471 argreg
, paddr_nz (struct_addr
));
3472 write_register (argreg
++, struct_addr
);
3473 stack_offset
+= mips_stack_argsize (gdbarch
);
3476 /* Now load as many as possible of the first arguments into
3477 registers, and push the rest onto the stack. Loop thru args
3478 from first to last. */
3479 for (argnum
= 0; argnum
< nargs
; argnum
++)
3482 struct value
*arg
= args
[argnum
];
3483 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3484 int len
= TYPE_LENGTH (arg_type
);
3485 enum type_code typecode
= TYPE_CODE (arg_type
);
3488 fprintf_unfiltered (gdb_stdlog
,
3489 "mips_o32_push_dummy_call: %d len=%d type=%d",
3490 argnum
+ 1, len
, (int) typecode
);
3492 val
= (char *) VALUE_CONTENTS (arg
);
3494 /* 32-bit ABIs always start floating point arguments in an
3495 even-numbered floating point register. Round the FP register
3496 up before the check to see if there are any FP registers
3497 left. O32/O64 targets also pass the FP in the integer
3498 registers so also round up normal registers. */
3499 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3501 if ((float_argreg
& 1))
3505 /* Floating point arguments passed in registers have to be
3506 treated specially. On 32-bit architectures, doubles
3507 are passed in register pairs; the even register gets
3508 the low word, and the odd register gets the high word.
3509 On O32/O64, the first two floating point arguments are
3510 also copied to general registers, because MIPS16 functions
3511 don't use float registers for arguments. This duplication of
3512 arguments in general registers can't hurt non-MIPS16 functions
3513 because those registers are normally skipped. */
3515 if (fp_register_arg_p (typecode
, arg_type
)
3516 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3518 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3520 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3521 unsigned long regval
;
3523 /* Write the low word of the double to the even register(s). */
3524 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3526 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3527 float_argreg
, phex (regval
, 4));
3528 write_register (float_argreg
++, regval
);
3530 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3531 argreg
, phex (regval
, 4));
3532 write_register (argreg
++, regval
);
3534 /* Write the high word of the double to the odd register(s). */
3535 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3537 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3538 float_argreg
, phex (regval
, 4));
3539 write_register (float_argreg
++, regval
);
3542 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3543 argreg
, phex (regval
, 4));
3544 write_register (argreg
++, regval
);
3548 /* This is a floating point value that fits entirely
3549 in a single register. */
3550 /* On 32 bit ABI's the float_argreg is further adjusted
3551 above to ensure that it is even register aligned. */
3552 LONGEST regval
= extract_unsigned_integer (val
, len
);
3554 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3555 float_argreg
, phex (regval
, len
));
3556 write_register (float_argreg
++, regval
);
3557 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3558 registers for each argument. The below is (my
3559 guess) to ensure that the corresponding integer
3560 register has reserved the same space. */
3562 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3563 argreg
, phex (regval
, len
));
3564 write_register (argreg
, regval
);
3565 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3567 /* Reserve space for the FP register. */
3568 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3572 /* Copy the argument to general registers or the stack in
3573 register-sized pieces. Large arguments are split between
3574 registers and stack. */
3575 /* Note: structs whose size is not a multiple of
3576 mips_isa_regsize() are treated specially: Irix cc passes them
3577 in registers where gcc sometimes puts them on the stack.
3578 For maximum compatibility, we will put them in both
3580 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3581 && (len
% mips_abi_regsize (gdbarch
) != 0));
3582 /* Structures should be aligned to eight bytes (even arg registers)
3583 on MIPS_ABI_O32, if their first member has double precision. */
3584 if (mips_abi_regsize (gdbarch
) < 8
3585 && mips_type_needs_double_align (arg_type
))
3590 /* Note: Floating-point values that didn't fit into an FP
3591 register are only written to memory. */
3594 /* Remember if the argument was written to the stack. */
3595 int stack_used_p
= 0;
3596 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3597 ? len
: mips_abi_regsize (gdbarch
));
3600 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3603 /* Write this portion of the argument to the stack. */
3604 if (argreg
> MIPS_LAST_ARG_REGNUM
3606 || fp_register_arg_p (typecode
, arg_type
))
3608 /* Should shorter than int integer values be
3609 promoted to int before being stored? */
3610 int longword_offset
= 0;
3613 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3615 if (mips_stack_argsize (gdbarch
) == 8
3616 && (typecode
== TYPE_CODE_INT
3617 || typecode
== TYPE_CODE_PTR
3618 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3619 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3624 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3625 paddr_nz (stack_offset
));
3626 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3627 paddr_nz (longword_offset
));
3630 addr
= sp
+ stack_offset
+ longword_offset
;
3635 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3637 for (i
= 0; i
< partial_len
; i
++)
3639 fprintf_unfiltered (gdb_stdlog
, "%02x",
3643 write_memory (addr
, val
, partial_len
);
3646 /* Note!!! This is NOT an else clause. Odd sized
3647 structs may go thru BOTH paths. Floating point
3648 arguments will not. */
3649 /* Write this portion of the argument to a general
3650 purpose register. */
3651 if (argreg
<= MIPS_LAST_ARG_REGNUM
3652 && !fp_register_arg_p (typecode
, arg_type
))
3654 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3655 /* Value may need to be sign extended, because
3656 mips_isa_regsize() != mips_abi_regsize(). */
3658 /* A non-floating-point argument being passed in a
3659 general register. If a struct or union, and if
3660 the remaining length is smaller than the register
3661 size, we have to adjust the register value on
3664 It does not seem to be necessary to do the
3665 same for integral types.
3667 Also don't do this adjustment on O64 binaries.
3669 cagney/2001-07-23: gdb/179: Also, GCC, when
3670 outputting LE O32 with sizeof (struct) <
3671 mips_abi_regsize(), generates a left shift as
3672 part of storing the argument in a register a
3673 register (the left shift isn't generated when
3674 sizeof (struct) >= mips_abi_regsize()). Since
3675 it is quite possible that this is GCC
3676 contradicting the LE/O32 ABI, GDB has not been
3677 adjusted to accommodate this. Either someone
3678 needs to demonstrate that the LE/O32 ABI
3679 specifies such a left shift OR this new ABI gets
3680 identified as such and GDB gets tweaked
3683 if (mips_abi_regsize (gdbarch
) < 8
3684 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3685 && partial_len
< mips_abi_regsize (gdbarch
)
3686 && (typecode
== TYPE_CODE_STRUCT
||
3687 typecode
== TYPE_CODE_UNION
))
3688 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3692 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3695 mips_abi_regsize (gdbarch
)));
3696 write_register (argreg
, regval
);
3699 /* Prevent subsequent floating point arguments from
3700 being passed in floating point registers. */
3701 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3707 /* Compute the the offset into the stack at which we
3708 will copy the next parameter.
3710 In older ABIs, the caller reserved space for
3711 registers that contained arguments. This was loosely
3712 refered to as their "home". Consequently, space is
3713 always allocated. */
3715 stack_offset
+= align_up (partial_len
,
3716 mips_stack_argsize (gdbarch
));
3720 fprintf_unfiltered (gdb_stdlog
, "\n");
3723 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3725 /* Return adjusted stack pointer. */
3729 static enum return_value_convention
3730 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3731 struct regcache
*regcache
,
3732 void *readbuf
, const void *writebuf
)
3734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3736 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3737 || TYPE_CODE (type
) == TYPE_CODE_UNION
3738 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3739 return RETURN_VALUE_STRUCT_CONVENTION
;
3740 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3741 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3743 /* A single-precision floating-point value. It fits in the
3744 least significant part of FP0. */
3746 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3747 mips_xfer_register (regcache
,
3748 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3750 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3751 return RETURN_VALUE_REGISTER_CONVENTION
;
3753 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3754 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3756 /* A double-precision floating-point value. The most
3757 significant part goes in FP1, and the least significant in
3760 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3761 switch (TARGET_BYTE_ORDER
)
3763 case BFD_ENDIAN_LITTLE
:
3764 mips_xfer_register (regcache
,
3765 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3766 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3767 mips_xfer_register (regcache
,
3768 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3769 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3771 case BFD_ENDIAN_BIG
:
3772 mips_xfer_register (regcache
,
3773 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3774 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3775 mips_xfer_register (regcache
,
3776 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3777 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3780 internal_error (__FILE__
, __LINE__
, "bad switch");
3782 return RETURN_VALUE_REGISTER_CONVENTION
;
3785 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3786 && TYPE_NFIELDS (type
) <= 2
3787 && TYPE_NFIELDS (type
) >= 1
3788 && ((TYPE_NFIELDS (type
) == 1
3789 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3791 || (TYPE_NFIELDS (type
) == 2
3792 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3794 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3796 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3798 /* A struct that contains one or two floats. Each value is part
3799 in the least significant part of their floating point
3801 bfd_byte reg
[MAX_REGISTER_SIZE
];
3804 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3805 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3807 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3810 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3812 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3813 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3814 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3816 return RETURN_VALUE_REGISTER_CONVENTION
;
3820 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3821 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3823 /* A structure or union. Extract the left justified value,
3824 regardless of the byte order. I.e. DO NOT USE
3828 for (offset
= 0, regnum
= V0_REGNUM
;
3829 offset
< TYPE_LENGTH (type
);
3830 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3832 int xfer
= register_size (current_gdbarch
, regnum
);
3833 if (offset
+ xfer
> TYPE_LENGTH (type
))
3834 xfer
= TYPE_LENGTH (type
) - offset
;
3836 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3837 offset
, xfer
, regnum
);
3838 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3839 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3841 return RETURN_VALUE_REGISTER_CONVENTION
;
3846 /* A scalar extract each part but least-significant-byte
3847 justified. o32 thinks registers are 4 byte, regardless of
3848 the ISA. mips_stack_argsize controls this. */
3851 for (offset
= 0, regnum
= V0_REGNUM
;
3852 offset
< TYPE_LENGTH (type
);
3853 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3855 int xfer
= mips_stack_argsize (gdbarch
);
3856 if (offset
+ xfer
> TYPE_LENGTH (type
))
3857 xfer
= TYPE_LENGTH (type
) - offset
;
3859 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3860 offset
, xfer
, regnum
);
3861 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3862 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3864 return RETURN_VALUE_REGISTER_CONVENTION
;
3868 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3872 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3873 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3875 struct value
**args
, CORE_ADDR sp
,
3876 int struct_return
, CORE_ADDR struct_addr
)
3882 int stack_offset
= 0;
3883 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3885 /* For shared libraries, "t9" needs to point at the function
3887 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3889 /* Set the return address register to point to the entry point of
3890 the program, where a breakpoint lies in wait. */
3891 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3893 /* First ensure that the stack and structure return address (if any)
3894 are properly aligned. The stack has to be at least 64-bit
3895 aligned even on 32-bit machines, because doubles must be 64-bit
3896 aligned. For n32 and n64, stack frames need to be 128-bit
3897 aligned, so we round to this widest known alignment. */
3899 sp
= align_down (sp
, 16);
3900 struct_addr
= align_down (struct_addr
, 16);
3902 /* Now make space on the stack for the args. */
3903 for (argnum
= 0; argnum
< nargs
; argnum
++)
3904 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3905 mips_stack_argsize (gdbarch
));
3906 sp
-= align_up (len
, 16);
3909 fprintf_unfiltered (gdb_stdlog
,
3910 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3911 paddr_nz (sp
), (long) align_up (len
, 16));
3913 /* Initialize the integer and float register pointers. */
3915 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3917 /* The struct_return pointer occupies the first parameter-passing reg. */
3921 fprintf_unfiltered (gdb_stdlog
,
3922 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3923 argreg
, paddr_nz (struct_addr
));
3924 write_register (argreg
++, struct_addr
);
3925 stack_offset
+= mips_stack_argsize (gdbarch
);
3928 /* Now load as many as possible of the first arguments into
3929 registers, and push the rest onto the stack. Loop thru args
3930 from first to last. */
3931 for (argnum
= 0; argnum
< nargs
; argnum
++)
3934 struct value
*arg
= args
[argnum
];
3935 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3936 int len
= TYPE_LENGTH (arg_type
);
3937 enum type_code typecode
= TYPE_CODE (arg_type
);
3940 fprintf_unfiltered (gdb_stdlog
,
3941 "mips_o64_push_dummy_call: %d len=%d type=%d",
3942 argnum
+ 1, len
, (int) typecode
);
3944 val
= (char *) VALUE_CONTENTS (arg
);
3946 /* 32-bit ABIs always start floating point arguments in an
3947 even-numbered floating point register. Round the FP register
3948 up before the check to see if there are any FP registers
3949 left. O32/O64 targets also pass the FP in the integer
3950 registers so also round up normal registers. */
3951 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3953 if ((float_argreg
& 1))
3957 /* Floating point arguments passed in registers have to be
3958 treated specially. On 32-bit architectures, doubles
3959 are passed in register pairs; the even register gets
3960 the low word, and the odd register gets the high word.
3961 On O32/O64, the first two floating point arguments are
3962 also copied to general registers, because MIPS16 functions
3963 don't use float registers for arguments. This duplication of
3964 arguments in general registers can't hurt non-MIPS16 functions
3965 because those registers are normally skipped. */
3967 if (fp_register_arg_p (typecode
, arg_type
)
3968 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3970 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3972 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3973 unsigned long regval
;
3975 /* Write the low word of the double to the even register(s). */
3976 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3978 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3979 float_argreg
, phex (regval
, 4));
3980 write_register (float_argreg
++, regval
);
3982 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3983 argreg
, phex (regval
, 4));
3984 write_register (argreg
++, regval
);
3986 /* Write the high word of the double to the odd register(s). */
3987 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3989 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3990 float_argreg
, phex (regval
, 4));
3991 write_register (float_argreg
++, regval
);
3994 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3995 argreg
, phex (regval
, 4));
3996 write_register (argreg
++, regval
);
4000 /* This is a floating point value that fits entirely
4001 in a single register. */
4002 /* On 32 bit ABI's the float_argreg is further adjusted
4003 above to ensure that it is even register aligned. */
4004 LONGEST regval
= extract_unsigned_integer (val
, len
);
4006 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4007 float_argreg
, phex (regval
, len
));
4008 write_register (float_argreg
++, regval
);
4009 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4010 registers for each argument. The below is (my
4011 guess) to ensure that the corresponding integer
4012 register has reserved the same space. */
4014 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4015 argreg
, phex (regval
, len
));
4016 write_register (argreg
, regval
);
4017 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
4019 /* Reserve space for the FP register. */
4020 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4024 /* Copy the argument to general registers or the stack in
4025 register-sized pieces. Large arguments are split between
4026 registers and stack. */
4027 /* Note: structs whose size is not a multiple of
4028 mips_isa_regsize() are treated specially: Irix cc passes them
4029 in registers where gcc sometimes puts them on the stack.
4030 For maximum compatibility, we will put them in both
4032 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4033 && (len
% mips_abi_regsize (gdbarch
) != 0));
4034 /* Structures should be aligned to eight bytes (even arg registers)
4035 on MIPS_ABI_O32, if their first member has double precision. */
4036 if (mips_abi_regsize (gdbarch
) < 8
4037 && mips_type_needs_double_align (arg_type
))
4042 /* Note: Floating-point values that didn't fit into an FP
4043 register are only written to memory. */
4046 /* Remember if the argument was written to the stack. */
4047 int stack_used_p
= 0;
4048 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4049 ? len
: mips_abi_regsize (gdbarch
));
4052 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4055 /* Write this portion of the argument to the stack. */
4056 if (argreg
> MIPS_LAST_ARG_REGNUM
4058 || fp_register_arg_p (typecode
, arg_type
))
4060 /* Should shorter than int integer values be
4061 promoted to int before being stored? */
4062 int longword_offset
= 0;
4065 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4067 if (mips_stack_argsize (gdbarch
) == 8
4068 && (typecode
== TYPE_CODE_INT
4069 || typecode
== TYPE_CODE_PTR
4070 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4071 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4076 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4077 paddr_nz (stack_offset
));
4078 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4079 paddr_nz (longword_offset
));
4082 addr
= sp
+ stack_offset
+ longword_offset
;
4087 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4089 for (i
= 0; i
< partial_len
; i
++)
4091 fprintf_unfiltered (gdb_stdlog
, "%02x",
4095 write_memory (addr
, val
, partial_len
);
4098 /* Note!!! This is NOT an else clause. Odd sized
4099 structs may go thru BOTH paths. Floating point
4100 arguments will not. */
4101 /* Write this portion of the argument to a general
4102 purpose register. */
4103 if (argreg
<= MIPS_LAST_ARG_REGNUM
4104 && !fp_register_arg_p (typecode
, arg_type
))
4106 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4107 /* Value may need to be sign extended, because
4108 mips_isa_regsize() != mips_abi_regsize(). */
4110 /* A non-floating-point argument being passed in a
4111 general register. If a struct or union, and if
4112 the remaining length is smaller than the register
4113 size, we have to adjust the register value on
4116 It does not seem to be necessary to do the
4117 same for integral types.
4119 Also don't do this adjustment on O64 binaries.
4121 cagney/2001-07-23: gdb/179: Also, GCC, when
4122 outputting LE O32 with sizeof (struct) <
4123 mips_abi_regsize(), generates a left shift as
4124 part of storing the argument in a register a
4125 register (the left shift isn't generated when
4126 sizeof (struct) >= mips_abi_regsize()). Since
4127 it is quite possible that this is GCC
4128 contradicting the LE/O32 ABI, GDB has not been
4129 adjusted to accommodate this. Either someone
4130 needs to demonstrate that the LE/O32 ABI
4131 specifies such a left shift OR this new ABI gets
4132 identified as such and GDB gets tweaked
4135 if (mips_abi_regsize (gdbarch
) < 8
4136 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4137 && partial_len
< mips_abi_regsize (gdbarch
)
4138 && (typecode
== TYPE_CODE_STRUCT
||
4139 typecode
== TYPE_CODE_UNION
))
4140 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4144 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4147 mips_abi_regsize (gdbarch
)));
4148 write_register (argreg
, regval
);
4151 /* Prevent subsequent floating point arguments from
4152 being passed in floating point registers. */
4153 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4159 /* Compute the the offset into the stack at which we
4160 will copy the next parameter.
4162 In older ABIs, the caller reserved space for
4163 registers that contained arguments. This was loosely
4164 refered to as their "home". Consequently, space is
4165 always allocated. */
4167 stack_offset
+= align_up (partial_len
,
4168 mips_stack_argsize (gdbarch
));
4172 fprintf_unfiltered (gdb_stdlog
, "\n");
4175 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
4177 /* Return adjusted stack pointer. */
4182 mips_o64_extract_return_value (struct type
*valtype
,
4183 char regbuf
[], char *valbuf
)
4185 struct return_value_word lo
;
4186 struct return_value_word hi
;
4187 return_value_location (valtype
, &hi
, &lo
);
4189 memcpy (valbuf
+ lo
.buf_offset
,
4190 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4191 lo
.reg_offset
, lo
.len
);
4194 memcpy (valbuf
+ hi
.buf_offset
,
4195 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4196 hi
.reg_offset
, hi
.len
);
4200 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4202 char raw_buffer
[MAX_REGISTER_SIZE
];
4203 struct return_value_word lo
;
4204 struct return_value_word hi
;
4205 return_value_location (valtype
, &hi
, &lo
);
4207 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4208 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4209 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4210 raw_buffer
, register_size (current_gdbarch
,
4215 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4216 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4217 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4219 register_size (current_gdbarch
,
4224 /* Floating point register management.
4226 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4227 64bit operations, these early MIPS cpus treat fp register pairs
4228 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4229 registers and offer a compatibility mode that emulates the MIPS2 fp
4230 model. When operating in MIPS2 fp compat mode, later cpu's split
4231 double precision floats into two 32-bit chunks and store them in
4232 consecutive fp regs. To display 64-bit floats stored in this
4233 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4234 Throw in user-configurable endianness and you have a real mess.
4236 The way this works is:
4237 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4238 double-precision value will be split across two logical registers.
4239 The lower-numbered logical register will hold the low-order bits,
4240 regardless of the processor's endianness.
4241 - If we are on a 64-bit processor, and we are looking for a
4242 single-precision value, it will be in the low ordered bits
4243 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4244 save slot in memory.
4245 - If we are in 64-bit mode, everything is straightforward.
4247 Note that this code only deals with "live" registers at the top of the
4248 stack. We will attempt to deal with saved registers later, when
4249 the raw/cooked register interface is in place. (We need a general
4250 interface that can deal with dynamic saved register sizes -- fp
4251 regs could be 32 bits wide in one frame and 64 on the frame above
4254 static struct type
*
4255 mips_float_register_type (void)
4257 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4258 return builtin_type_ieee_single_big
;
4260 return builtin_type_ieee_single_little
;
4263 static struct type
*
4264 mips_double_register_type (void)
4266 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4267 return builtin_type_ieee_double_big
;
4269 return builtin_type_ieee_double_little
;
4272 /* Copy a 32-bit single-precision value from the current frame
4273 into rare_buffer. */
4276 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4279 int raw_size
= register_size (current_gdbarch
, regno
);
4280 char *raw_buffer
= alloca (raw_size
);
4282 if (!frame_register_read (frame
, regno
, raw_buffer
))
4283 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4286 /* We have a 64-bit value for this register. Find the low-order
4290 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4295 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4299 memcpy (rare_buffer
, raw_buffer
, 4);
4303 /* Copy a 64-bit double-precision value from the current frame into
4304 rare_buffer. This may include getting half of it from the next
4308 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4311 int raw_size
= register_size (current_gdbarch
, regno
);
4313 if (raw_size
== 8 && !mips2_fp_compat ())
4315 /* We have a 64-bit value for this register, and we should use
4317 if (!frame_register_read (frame
, regno
, rare_buffer
))
4318 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4322 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4323 internal_error (__FILE__
, __LINE__
,
4324 "mips_read_fp_register_double: bad access to "
4325 "odd-numbered FP register");
4327 /* mips_read_fp_register_single will find the correct 32 bits from
4329 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4331 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4332 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4336 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4337 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4343 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4345 { /* do values for FP (float) regs */
4347 double doub
, flt1
; /* doubles extracted from raw hex data */
4351 (char *) alloca (2 *
4352 register_size (current_gdbarch
,
4353 mips_regnum (current_gdbarch
)->fp0
));
4355 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4356 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4359 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4361 /* 4-byte registers: Print hex and floating. Also print even
4362 numbered registers as doubles. */
4363 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4364 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4366 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4369 fprintf_filtered (file
, " flt: ");
4371 fprintf_filtered (file
, " <invalid float> ");
4373 fprintf_filtered (file
, "%-17.9g", flt1
);
4375 if (regnum
% 2 == 0)
4377 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4378 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4381 fprintf_filtered (file
, " dbl: ");
4383 fprintf_filtered (file
, "<invalid double>");
4385 fprintf_filtered (file
, "%-24.17g", doub
);
4390 /* Eight byte registers: print each one as hex, float and double. */
4391 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4392 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4394 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4395 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4398 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4401 fprintf_filtered (file
, " flt: ");
4403 fprintf_filtered (file
, "<invalid float>");
4405 fprintf_filtered (file
, "%-17.9g", flt1
);
4407 fprintf_filtered (file
, " dbl: ");
4409 fprintf_filtered (file
, "<invalid double>");
4411 fprintf_filtered (file
, "%-24.17g", doub
);
4416 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4417 int regnum
, int all
)
4419 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4420 char raw_buffer
[MAX_REGISTER_SIZE
];
4423 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4425 mips_print_fp_register (file
, frame
, regnum
);
4429 /* Get the data in raw format. */
4430 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4432 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4436 fputs_filtered (REGISTER_NAME (regnum
), file
);
4438 /* The problem with printing numeric register names (r26, etc.) is that
4439 the user can't use them on input. Probably the best solution is to
4440 fix it so that either the numeric or the funky (a2, etc.) names
4441 are accepted on input. */
4442 if (regnum
< MIPS_NUMREGS
)
4443 fprintf_filtered (file
, "(r%d): ", regnum
);
4445 fprintf_filtered (file
, ": ");
4447 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4449 register_size (current_gdbarch
,
4450 regnum
) - register_size (current_gdbarch
, regnum
);
4454 print_scalar_formatted (raw_buffer
+ offset
,
4455 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4459 /* Replacement for generic do_registers_info.
4460 Print regs in pretty columns. */
4463 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4466 fprintf_filtered (file
, " ");
4467 mips_print_fp_register (file
, frame
, regnum
);
4468 fprintf_filtered (file
, "\n");
4473 /* Print a row's worth of GP (int) registers, with name labels above */
4476 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4479 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4480 /* do values for GP (int) regs */
4481 char raw_buffer
[MAX_REGISTER_SIZE
];
4482 int ncols
= (mips_isa_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4486 /* For GP registers, we print a separate row of names above the vals */
4487 fprintf_filtered (file
, " ");
4488 for (col
= 0, regnum
= start_regnum
;
4489 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4491 if (*REGISTER_NAME (regnum
) == '\0')
4492 continue; /* unused register */
4493 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4495 break; /* end the row: reached FP register */
4496 fprintf_filtered (file
,
4497 mips_isa_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4498 REGISTER_NAME (regnum
));
4501 /* print the R0 to R31 names */
4502 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4503 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4505 fprintf_filtered (file
, "\n ");
4507 /* now print the values in hex, 4 or 8 to the row */
4508 for (col
= 0, regnum
= start_regnum
;
4509 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4511 if (*REGISTER_NAME (regnum
) == '\0')
4512 continue; /* unused register */
4513 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4515 break; /* end row: reached FP register */
4516 /* OK: get the data in raw format. */
4517 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4518 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4519 /* pad small registers */
4521 byte
< (mips_isa_regsize (current_gdbarch
)
4522 - register_size (current_gdbarch
, regnum
)); byte
++)
4523 printf_filtered (" ");
4524 /* Now print the register value in hex, endian order. */
4525 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4527 register_size (current_gdbarch
,
4528 regnum
) - register_size (current_gdbarch
, regnum
);
4529 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4530 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4532 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4534 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4535 fprintf_filtered (file
, " ");
4538 if (col
> 0) /* ie. if we actually printed anything... */
4539 fprintf_filtered (file
, "\n");
4544 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4547 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4548 struct frame_info
*frame
, int regnum
, int all
)
4550 if (regnum
!= -1) /* do one specified register */
4552 gdb_assert (regnum
>= NUM_REGS
);
4553 if (*(REGISTER_NAME (regnum
)) == '\0')
4554 error ("Not a valid register for the current processor type");
4556 mips_print_register (file
, frame
, regnum
, 0);
4557 fprintf_filtered (file
, "\n");
4560 /* do all (or most) registers */
4563 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4565 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4568 if (all
) /* true for "INFO ALL-REGISTERS" command */
4569 regnum
= print_fp_register_row (file
, frame
, regnum
);
4571 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4574 regnum
= print_gp_register_row (file
, frame
, regnum
);
4579 /* Is this a branch with a delay slot? */
4581 static int is_delayed (unsigned long);
4584 is_delayed (unsigned long insn
)
4587 for (i
= 0; i
< NUMOPCODES
; ++i
)
4588 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4589 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4591 return (i
< NUMOPCODES
4592 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4593 | INSN_COND_BRANCH_DELAY
4594 | INSN_COND_BRANCH_LIKELY
)));
4598 mips_step_skips_delay (CORE_ADDR pc
)
4600 char buf
[MIPS_INSTLEN
];
4602 /* There is no branch delay slot on MIPS16. */
4603 if (pc_is_mips16 (pc
))
4606 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4607 /* If error reading memory, guess that it is not a delayed branch. */
4609 return is_delayed ((unsigned long)
4610 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4613 /* Skip the PC past function prologue instructions (32-bit version).
4614 This is a helper function for mips_skip_prologue. */
4617 mips32_skip_prologue (CORE_ADDR pc
)
4621 int seen_sp_adjust
= 0;
4622 int load_immediate_bytes
= 0;
4624 /* Find an upper bound on the prologue. */
4625 end_pc
= skip_prologue_using_sal (pc
);
4627 end_pc
= pc
+ 100; /* Magic. */
4629 /* Skip the typical prologue instructions. These are the stack adjustment
4630 instruction and the instructions that save registers on the stack
4631 or in the gcc frame. */
4632 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4634 unsigned long high_word
;
4636 inst
= mips_fetch_instruction (pc
);
4637 high_word
= (inst
>> 16) & 0xffff;
4639 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4640 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4642 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4643 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4645 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4646 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4647 && (inst
& 0x001F0000)) /* reg != $zero */
4650 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4652 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4654 continue; /* reg != $zero */
4656 /* move $s8,$sp. With different versions of gas this will be either
4657 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4658 Accept any one of these. */
4659 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4662 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4664 else if (high_word
== 0x3c1c) /* lui $gp,n */
4666 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4668 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4669 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4671 /* The following instructions load $at or $t0 with an immediate
4672 value in preparation for a stack adjustment via
4673 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4674 a local variable, so we accept them only before a stack adjustment
4675 instruction was seen. */
4676 else if (!seen_sp_adjust
)
4678 if (high_word
== 0x3c01 || /* lui $at,n */
4679 high_word
== 0x3c08) /* lui $t0,n */
4681 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4684 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4685 high_word
== 0x3508 || /* ori $t0,$t0,n */
4686 high_word
== 0x3401 || /* ori $at,$zero,n */
4687 high_word
== 0x3408) /* ori $t0,$zero,n */
4689 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4699 /* In a frameless function, we might have incorrectly
4700 skipped some load immediate instructions. Undo the skipping
4701 if the load immediate was not followed by a stack adjustment. */
4702 if (load_immediate_bytes
&& !seen_sp_adjust
)
4703 pc
-= load_immediate_bytes
;
4707 /* Skip the PC past function prologue instructions (16-bit version).
4708 This is a helper function for mips_skip_prologue. */
4711 mips16_skip_prologue (CORE_ADDR pc
)
4714 int extend_bytes
= 0;
4715 int prev_extend_bytes
;
4717 /* Table of instructions likely to be found in a function prologue. */
4720 unsigned short inst
;
4721 unsigned short mask
;
4727 , /* addiu $sp,offset */
4730 , /* daddiu $sp,offset */
4733 , /* sw reg,n($sp) */
4736 , /* sd reg,n($sp) */
4739 , /* sw $ra,n($sp) */
4742 , /* sd $ra,n($sp) */
4748 , /* sw $a0-$a3,n($s1) */
4751 , /* move reg,$a0-$a3 */
4754 , /* entry pseudo-op */
4757 , /* addiu $s1,$sp,n */
4759 0, 0} /* end of table marker */
4762 /* Find an upper bound on the prologue. */
4763 end_pc
= skip_prologue_using_sal (pc
);
4765 end_pc
= pc
+ 100; /* Magic. */
4767 /* Skip the typical prologue instructions. These are the stack adjustment
4768 instruction and the instructions that save registers on the stack
4769 or in the gcc frame. */
4770 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4772 unsigned short inst
;
4775 inst
= mips_fetch_instruction (pc
);
4777 /* Normally we ignore an extend instruction. However, if it is
4778 not followed by a valid prologue instruction, we must adjust
4779 the pc back over the extend so that it won't be considered
4780 part of the prologue. */
4781 if ((inst
& 0xf800) == 0xf000) /* extend */
4783 extend_bytes
= MIPS16_INSTLEN
;
4786 prev_extend_bytes
= extend_bytes
;
4789 /* Check for other valid prologue instructions besides extend. */
4790 for (i
= 0; table
[i
].mask
!= 0; i
++)
4791 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4793 if (table
[i
].mask
!= 0) /* it was in table? */
4794 continue; /* ignore it */
4798 /* Return the current pc, adjusted backwards by 2 if
4799 the previous instruction was an extend. */
4800 return pc
- prev_extend_bytes
;
4806 /* To skip prologues, I use this predicate. Returns either PC itself
4807 if the code at PC does not look like a function prologue; otherwise
4808 returns an address that (if we're lucky) follows the prologue. If
4809 LENIENT, then we must skip everything which is involved in setting
4810 up the frame (it's OK to skip more, just so long as we don't skip
4811 anything which might clobber the registers which are being saved.
4812 We must skip more in the case where part of the prologue is in the
4813 delay slot of a non-prologue instruction). */
4816 mips_skip_prologue (CORE_ADDR pc
)
4818 /* See if we can determine the end of the prologue via the symbol table.
4819 If so, then return either PC, or the PC after the prologue, whichever
4822 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4824 if (post_prologue_pc
!= 0)
4825 return max (pc
, post_prologue_pc
);
4827 /* Can't determine prologue from the symbol table, need to examine
4830 if (pc_is_mips16 (pc
))
4831 return mips16_skip_prologue (pc
);
4833 return mips32_skip_prologue (pc
);
4836 /* Exported procedure: Is PC in the signal trampoline code */
4839 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
4841 if (sigtramp_address
== 0)
4843 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
4846 /* Root of all "set mips "/"show mips " commands. This will eventually be
4847 used for all MIPS-specific commands. */
4850 show_mips_command (char *args
, int from_tty
)
4852 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4856 set_mips_command (char *args
, int from_tty
)
4859 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4860 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4863 /* Commands to show/set the MIPS FPU type. */
4866 show_mipsfpu_command (char *args
, int from_tty
)
4869 switch (MIPS_FPU_TYPE
)
4871 case MIPS_FPU_SINGLE
:
4872 fpu
= "single-precision";
4874 case MIPS_FPU_DOUBLE
:
4875 fpu
= "double-precision";
4878 fpu
= "absent (none)";
4881 internal_error (__FILE__
, __LINE__
, "bad switch");
4883 if (mips_fpu_type_auto
)
4885 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4889 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4894 set_mipsfpu_command (char *args
, int from_tty
)
4897 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4898 show_mipsfpu_command (args
, from_tty
);
4902 set_mipsfpu_single_command (char *args
, int from_tty
)
4904 struct gdbarch_info info
;
4905 gdbarch_info_init (&info
);
4906 mips_fpu_type
= MIPS_FPU_SINGLE
;
4907 mips_fpu_type_auto
= 0;
4908 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4909 instead of relying on globals. Doing that would let generic code
4910 handle the search for this specific architecture. */
4911 if (!gdbarch_update_p (info
))
4912 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4916 set_mipsfpu_double_command (char *args
, int from_tty
)
4918 struct gdbarch_info info
;
4919 gdbarch_info_init (&info
);
4920 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4921 mips_fpu_type_auto
= 0;
4922 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4923 instead of relying on globals. Doing that would let generic code
4924 handle the search for this specific architecture. */
4925 if (!gdbarch_update_p (info
))
4926 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4930 set_mipsfpu_none_command (char *args
, int from_tty
)
4932 struct gdbarch_info info
;
4933 gdbarch_info_init (&info
);
4934 mips_fpu_type
= MIPS_FPU_NONE
;
4935 mips_fpu_type_auto
= 0;
4936 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4937 instead of relying on globals. Doing that would let generic code
4938 handle the search for this specific architecture. */
4939 if (!gdbarch_update_p (info
))
4940 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4944 set_mipsfpu_auto_command (char *args
, int from_tty
)
4946 mips_fpu_type_auto
= 1;
4949 /* Attempt to identify the particular processor model by reading the
4950 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4951 the relevant processor still exists (it dates back to '94) and
4952 secondly this is not the way to do this. The processor type should
4953 be set by forcing an architecture change. */
4956 deprecated_mips_set_processor_regs_hack (void)
4958 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4961 prid
= read_register (PRID_REGNUM
);
4963 if ((prid
& ~0xf) == 0x700)
4964 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4967 /* Just like reinit_frame_cache, but with the right arguments to be
4968 callable as an sfunc. */
4971 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4972 struct cmd_list_element
*c
)
4974 reinit_frame_cache ();
4978 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4980 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4981 mips_extra_func_info_t proc_desc
;
4983 /* Search for the function containing this address. Set the low bit
4984 of the address when searching, in case we were given an even address
4985 that is the start of a 16-bit function. If we didn't do this,
4986 the search would fail because the symbol table says the function
4987 starts at an odd address, i.e. 1 byte past the given address. */
4988 memaddr
= ADDR_BITS_REMOVE (memaddr
);
4989 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
4991 /* Make an attempt to determine if this is a 16-bit function. If
4992 the procedure descriptor exists and the address therein is odd,
4993 it's definitely a 16-bit function. Otherwise, we have to just
4994 guess that if the address passed in is odd, it's 16-bits. */
4995 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4996 disassembler needs to be able to locally determine the ISA, and
4997 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5001 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5002 info
->mach
= bfd_mach_mips16
;
5006 if (pc_is_mips16 (memaddr
))
5007 info
->mach
= bfd_mach_mips16
;
5010 /* Round down the instruction address to the appropriate boundary. */
5011 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5013 /* Set the disassembler options. */
5014 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5016 /* Set up the disassembler info, so that we get the right
5017 register names from libopcodes. */
5018 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5019 info
->disassembler_options
= "gpr-names=n32";
5021 info
->disassembler_options
= "gpr-names=64";
5022 info
->flavour
= bfd_target_elf_flavour
;
5025 /* This string is not recognized explicitly by the disassembler,
5026 but it tells the disassembler to not try to guess the ABI from
5027 the bfd elf headers, such that, if the user overrides the ABI
5028 of a program linked as NewABI, the disassembly will follow the
5029 register naming conventions specified by the user. */
5030 info
->disassembler_options
= "gpr-names=32";
5032 /* Call the appropriate disassembler based on the target endian-ness. */
5033 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5034 return print_insn_big_mips (memaddr
, info
);
5036 return print_insn_little_mips (memaddr
, info
);
5039 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5040 counter value to determine whether a 16- or 32-bit breakpoint should be
5041 used. It returns a pointer to a string of bytes that encode a breakpoint
5042 instruction, stores the length of the string to *lenptr, and adjusts pc
5043 (if necessary) to point to the actual memory location where the
5044 breakpoint should be inserted. */
5046 static const unsigned char *
5047 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5049 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5051 if (pc_is_mips16 (*pcptr
))
5053 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5054 *pcptr
= unmake_mips16_addr (*pcptr
);
5055 *lenptr
= sizeof (mips16_big_breakpoint
);
5056 return mips16_big_breakpoint
;
5060 /* The IDT board uses an unusual breakpoint value, and
5061 sometimes gets confused when it sees the usual MIPS
5062 breakpoint instruction. */
5063 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5064 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5065 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5067 *lenptr
= sizeof (big_breakpoint
);
5069 if (strcmp (target_shortname
, "mips") == 0)
5070 return idt_big_breakpoint
;
5071 else if (strcmp (target_shortname
, "ddb") == 0
5072 || strcmp (target_shortname
, "pmon") == 0
5073 || strcmp (target_shortname
, "lsi") == 0)
5074 return pmon_big_breakpoint
;
5076 return big_breakpoint
;
5081 if (pc_is_mips16 (*pcptr
))
5083 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5084 *pcptr
= unmake_mips16_addr (*pcptr
);
5085 *lenptr
= sizeof (mips16_little_breakpoint
);
5086 return mips16_little_breakpoint
;
5090 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5091 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5092 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5094 *lenptr
= sizeof (little_breakpoint
);
5096 if (strcmp (target_shortname
, "mips") == 0)
5097 return idt_little_breakpoint
;
5098 else if (strcmp (target_shortname
, "ddb") == 0
5099 || strcmp (target_shortname
, "pmon") == 0
5100 || strcmp (target_shortname
, "lsi") == 0)
5101 return pmon_little_breakpoint
;
5103 return little_breakpoint
;
5108 /* If PC is in a mips16 call or return stub, return the address of the target
5109 PC, which is either the callee or the caller. There are several
5110 cases which must be handled:
5112 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5113 target PC is in $31 ($ra).
5114 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5115 and the target PC is in $2.
5116 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5117 before the jal instruction, this is effectively a call stub
5118 and the the target PC is in $2. Otherwise this is effectively
5119 a return stub and the target PC is in $18.
5121 See the source code for the stubs in gcc/config/mips/mips16.S for
5124 This function implements the SKIP_TRAMPOLINE_CODE macro.
5128 mips_skip_stub (CORE_ADDR pc
)
5131 CORE_ADDR start_addr
;
5133 /* Find the starting address and name of the function containing the PC. */
5134 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5137 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5138 target PC is in $31 ($ra). */
5139 if (strcmp (name
, "__mips16_ret_sf") == 0
5140 || strcmp (name
, "__mips16_ret_df") == 0)
5141 return read_signed_register (RA_REGNUM
);
5143 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5145 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5146 and the target PC is in $2. */
5147 if (name
[19] >= '0' && name
[19] <= '9')
5148 return read_signed_register (2);
5150 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5151 before the jal instruction, this is effectively a call stub
5152 and the the target PC is in $2. Otherwise this is effectively
5153 a return stub and the target PC is in $18. */
5154 else if (name
[19] == 's' || name
[19] == 'd')
5156 if (pc
== start_addr
)
5158 /* Check if the target of the stub is a compiler-generated
5159 stub. Such a stub for a function bar might have a name
5160 like __fn_stub_bar, and might look like this:
5165 la $1,bar (becomes a lui/addiu pair)
5167 So scan down to the lui/addi and extract the target
5168 address from those two instructions. */
5170 CORE_ADDR target_pc
= read_signed_register (2);
5174 /* See if the name of the target function is __fn_stub_*. */
5175 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5178 if (strncmp (name
, "__fn_stub_", 10) != 0
5179 && strcmp (name
, "etext") != 0
5180 && strcmp (name
, "_etext") != 0)
5183 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5184 The limit on the search is arbitrarily set to 20
5185 instructions. FIXME. */
5186 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5188 inst
= mips_fetch_instruction (target_pc
);
5189 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5190 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5191 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5192 return pc
| (inst
& 0xffff); /* low word */
5195 /* Couldn't find the lui/addui pair, so return stub address. */
5199 /* This is the 'return' part of a call stub. The return
5200 address is in $r18. */
5201 return read_signed_register (18);
5204 return 0; /* not a stub */
5208 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5209 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5212 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5214 CORE_ADDR start_addr
;
5216 /* Find the starting address of the function containing the PC. If the
5217 caller didn't give us a name, look it up at the same time. */
5218 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5222 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5224 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5225 if (name
[19] >= '0' && name
[19] <= '9')
5227 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5228 before the jal instruction, this is effectively a call stub. */
5229 else if (name
[19] == 's' || name
[19] == 'd')
5230 return pc
== start_addr
;
5233 return 0; /* not a stub */
5237 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5238 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5241 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5243 CORE_ADDR start_addr
;
5245 /* Find the starting address of the function containing the PC. */
5246 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5249 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5250 if (strcmp (name
, "__mips16_ret_sf") == 0
5251 || strcmp (name
, "__mips16_ret_df") == 0)
5254 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5255 i.e. after the jal instruction, this is effectively a return stub. */
5256 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5257 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5260 return 0; /* not a stub */
5264 /* Return non-zero if the PC is in a library helper function that should
5265 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5268 mips_ignore_helper (CORE_ADDR pc
)
5272 /* Find the starting address and name of the function containing the PC. */
5273 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5276 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5277 that we want to ignore. */
5278 return (strcmp (name
, "__mips16_ret_sf") == 0
5279 || strcmp (name
, "__mips16_ret_df") == 0);
5283 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5284 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5287 mips_stab_reg_to_regnum (int num
)
5290 if (num
>= 0 && num
< 32)
5292 else if (num
>= 38 && num
< 70)
5293 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5295 regnum
= mips_regnum (current_gdbarch
)->hi
;
5297 regnum
= mips_regnum (current_gdbarch
)->lo
;
5299 /* This will hopefully (eventually) provoke a warning. Should
5300 we be calling complaint() here? */
5301 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5302 return NUM_REGS
+ regnum
;
5306 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5307 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5310 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5313 if (num
>= 0 && num
< 32)
5315 else if (num
>= 32 && num
< 64)
5316 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5318 regnum
= mips_regnum (current_gdbarch
)->hi
;
5320 regnum
= mips_regnum (current_gdbarch
)->lo
;
5322 /* This will hopefully (eventually) provoke a warning. Should we
5323 be calling complaint() here? */
5324 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5325 return NUM_REGS
+ regnum
;
5329 mips_register_sim_regno (int regnum
)
5331 /* Only makes sense to supply raw registers. */
5332 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5333 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5334 decide if it is valid. Should instead define a standard sim/gdb
5335 register numbering scheme. */
5336 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5337 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5340 return LEGACY_SIM_REGNO_IGNORE
;
5344 /* Convert an integer into an address. By first converting the value
5345 into a pointer and then extracting it signed, the address is
5346 guarenteed to be correctly sign extended. */
5349 mips_integer_to_address (struct type
*type
, void *buf
)
5351 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5352 LONGEST val
= unpack_long (type
, buf
);
5353 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5354 return extract_signed_integer (tmp
,
5355 TYPE_LENGTH (builtin_type_void_data_ptr
));
5359 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5361 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5362 const char *name
= bfd_get_section_name (abfd
, sect
);
5364 if (*abip
!= MIPS_ABI_UNKNOWN
)
5367 if (strncmp (name
, ".mdebug.", 8) != 0)
5370 if (strcmp (name
, ".mdebug.abi32") == 0)
5371 *abip
= MIPS_ABI_O32
;
5372 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5373 *abip
= MIPS_ABI_N32
;
5374 else if (strcmp (name
, ".mdebug.abi64") == 0)
5375 *abip
= MIPS_ABI_N64
;
5376 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5377 *abip
= MIPS_ABI_O64
;
5378 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5379 *abip
= MIPS_ABI_EABI32
;
5380 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5381 *abip
= MIPS_ABI_EABI64
;
5383 warning ("unsupported ABI %s.", name
+ 8);
5386 static enum mips_abi
5387 global_mips_abi (void)
5391 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5392 if (mips_abi_strings
[i
] == mips_abi_string
)
5393 return (enum mips_abi
) i
;
5395 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5398 static struct gdbarch
*
5399 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5401 struct gdbarch
*gdbarch
;
5402 struct gdbarch_tdep
*tdep
;
5404 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5406 enum mips_fpu_type fpu_type
;
5408 /* First of all, extract the elf_flags, if available. */
5409 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5410 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5411 else if (arches
!= NULL
)
5412 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5416 fprintf_unfiltered (gdb_stdlog
,
5417 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5419 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5420 switch ((elf_flags
& EF_MIPS_ABI
))
5422 case E_MIPS_ABI_O32
:
5423 found_abi
= MIPS_ABI_O32
;
5425 case E_MIPS_ABI_O64
:
5426 found_abi
= MIPS_ABI_O64
;
5428 case E_MIPS_ABI_EABI32
:
5429 found_abi
= MIPS_ABI_EABI32
;
5431 case E_MIPS_ABI_EABI64
:
5432 found_abi
= MIPS_ABI_EABI64
;
5435 if ((elf_flags
& EF_MIPS_ABI2
))
5436 found_abi
= MIPS_ABI_N32
;
5438 found_abi
= MIPS_ABI_UNKNOWN
;
5442 /* GCC creates a pseudo-section whose name describes the ABI. */
5443 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5444 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5446 /* If we have no usefu BFD information, use the ABI from the last
5447 MIPS architecture (if there is one). */
5448 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5449 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5451 /* Try the architecture for any hint of the correct ABI. */
5452 if (found_abi
== MIPS_ABI_UNKNOWN
5453 && info
.bfd_arch_info
!= NULL
5454 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5456 switch (info
.bfd_arch_info
->mach
)
5458 case bfd_mach_mips3900
:
5459 found_abi
= MIPS_ABI_EABI32
;
5461 case bfd_mach_mips4100
:
5462 case bfd_mach_mips5000
:
5463 found_abi
= MIPS_ABI_EABI64
;
5465 case bfd_mach_mips8000
:
5466 case bfd_mach_mips10000
:
5467 /* On Irix, ELF64 executables use the N64 ABI. The
5468 pseudo-sections which describe the ABI aren't present
5469 on IRIX. (Even for executables created by gcc.) */
5470 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5471 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5472 found_abi
= MIPS_ABI_N64
;
5474 found_abi
= MIPS_ABI_N32
;
5480 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5483 /* What has the user specified from the command line? */
5484 wanted_abi
= global_mips_abi ();
5486 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5489 /* Now that we have found what the ABI for this binary would be,
5490 check whether the user is overriding it. */
5491 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5492 mips_abi
= wanted_abi
;
5493 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5494 mips_abi
= found_abi
;
5496 mips_abi
= MIPS_ABI_O32
;
5498 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5501 /* Also used when doing an architecture lookup. */
5503 fprintf_unfiltered (gdb_stdlog
,
5504 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5505 mips64_transfers_32bit_regs_p
);
5507 /* Determine the MIPS FPU type. */
5508 if (!mips_fpu_type_auto
)
5509 fpu_type
= mips_fpu_type
;
5510 else if (info
.bfd_arch_info
!= NULL
5511 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5512 switch (info
.bfd_arch_info
->mach
)
5514 case bfd_mach_mips3900
:
5515 case bfd_mach_mips4100
:
5516 case bfd_mach_mips4111
:
5517 fpu_type
= MIPS_FPU_NONE
;
5519 case bfd_mach_mips4650
:
5520 fpu_type
= MIPS_FPU_SINGLE
;
5523 fpu_type
= MIPS_FPU_DOUBLE
;
5526 else if (arches
!= NULL
)
5527 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5529 fpu_type
= MIPS_FPU_DOUBLE
;
5531 fprintf_unfiltered (gdb_stdlog
,
5532 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5534 /* try to find a pre-existing architecture */
5535 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5537 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5539 /* MIPS needs to be pedantic about which ABI the object is
5541 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5543 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5545 /* Need to be pedantic about which register virtual size is
5547 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5548 != mips64_transfers_32bit_regs_p
)
5550 /* Be pedantic about which FPU is selected. */
5551 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5553 return arches
->gdbarch
;
5556 /* Need a new architecture. Fill in a target specific vector. */
5557 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5558 gdbarch
= gdbarch_alloc (&info
, tdep
);
5559 tdep
->elf_flags
= elf_flags
;
5560 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5561 tdep
->found_abi
= found_abi
;
5562 tdep
->mips_abi
= mips_abi
;
5563 tdep
->mips_fpu_type
= fpu_type
;
5565 /* Initially set everything according to the default ABI/ISA. */
5566 set_gdbarch_short_bit (gdbarch
, 16);
5567 set_gdbarch_int_bit (gdbarch
, 32);
5568 set_gdbarch_float_bit (gdbarch
, 32);
5569 set_gdbarch_double_bit (gdbarch
, 64);
5570 set_gdbarch_long_double_bit (gdbarch
, 64);
5571 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5572 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5573 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5575 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5576 mips_elf_make_msymbol_special
);
5578 /* Fill in the OS dependant register numbers and names. */
5580 const char **reg_names
;
5581 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5582 struct mips_regnum
);
5583 if (info
.osabi
== GDB_OSABI_IRIX
)
5588 regnum
->badvaddr
= 66;
5591 regnum
->fp_control_status
= 69;
5592 regnum
->fp_implementation_revision
= 70;
5594 reg_names
= mips_irix_reg_names
;
5598 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5599 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5600 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5601 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5602 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5603 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5604 regnum
->fp_control_status
= 70;
5605 regnum
->fp_implementation_revision
= 71;
5607 if (info
.bfd_arch_info
!= NULL
5608 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5609 reg_names
= mips_tx39_reg_names
;
5611 reg_names
= mips_generic_reg_names
;
5613 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5614 replaced by read_pc? */
5615 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5616 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5617 set_gdbarch_num_regs (gdbarch
, num_regs
);
5618 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5619 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5620 tdep
->mips_processor_reg_names
= reg_names
;
5621 tdep
->regnum
= regnum
;
5627 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5628 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5629 tdep
->mips_fp_register_double
= 0;
5630 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5631 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5632 tdep
->default_mask_address_p
= 0;
5633 set_gdbarch_long_bit (gdbarch
, 32);
5634 set_gdbarch_ptr_bit (gdbarch
, 32);
5635 set_gdbarch_long_long_bit (gdbarch
, 64);
5638 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5639 set_gdbarch_deprecated_store_return_value (gdbarch
,
5640 mips_o64_store_return_value
);
5641 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5642 mips_o64_extract_return_value
);
5643 tdep
->mips_fp_register_double
= 1;
5644 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5645 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5646 tdep
->default_mask_address_p
= 0;
5647 set_gdbarch_long_bit (gdbarch
, 32);
5648 set_gdbarch_ptr_bit (gdbarch
, 32);
5649 set_gdbarch_long_long_bit (gdbarch
, 64);
5650 set_gdbarch_use_struct_convention (gdbarch
,
5651 always_use_struct_convention
);
5653 case MIPS_ABI_EABI32
:
5654 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5655 set_gdbarch_deprecated_store_return_value (gdbarch
,
5656 mips_eabi_store_return_value
);
5657 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5658 mips_eabi_extract_return_value
);
5659 tdep
->mips_fp_register_double
= 0;
5660 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5661 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5662 tdep
->default_mask_address_p
= 0;
5663 set_gdbarch_long_bit (gdbarch
, 32);
5664 set_gdbarch_ptr_bit (gdbarch
, 32);
5665 set_gdbarch_long_long_bit (gdbarch
, 64);
5666 set_gdbarch_deprecated_reg_struct_has_addr
5667 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5668 set_gdbarch_use_struct_convention (gdbarch
,
5669 mips_eabi_use_struct_convention
);
5671 case MIPS_ABI_EABI64
:
5672 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5673 set_gdbarch_deprecated_store_return_value (gdbarch
,
5674 mips_eabi_store_return_value
);
5675 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5676 mips_eabi_extract_return_value
);
5677 tdep
->mips_fp_register_double
= 1;
5678 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5679 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5680 tdep
->default_mask_address_p
= 0;
5681 set_gdbarch_long_bit (gdbarch
, 64);
5682 set_gdbarch_ptr_bit (gdbarch
, 64);
5683 set_gdbarch_long_long_bit (gdbarch
, 64);
5684 set_gdbarch_deprecated_reg_struct_has_addr
5685 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5686 set_gdbarch_use_struct_convention (gdbarch
,
5687 mips_eabi_use_struct_convention
);
5690 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5691 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5692 tdep
->mips_fp_register_double
= 1;
5693 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5694 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5695 tdep
->default_mask_address_p
= 0;
5696 set_gdbarch_long_bit (gdbarch
, 32);
5697 set_gdbarch_ptr_bit (gdbarch
, 32);
5698 set_gdbarch_long_long_bit (gdbarch
, 64);
5701 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5702 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5703 tdep
->mips_fp_register_double
= 1;
5704 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5705 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5706 tdep
->default_mask_address_p
= 0;
5707 set_gdbarch_long_bit (gdbarch
, 64);
5708 set_gdbarch_ptr_bit (gdbarch
, 64);
5709 set_gdbarch_long_long_bit (gdbarch
, 64);
5712 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5715 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5716 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5719 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5720 flag in object files because to do so would make it impossible to
5721 link with libraries compiled without "-gp32". This is
5722 unnecessarily restrictive.
5724 We could solve this problem by adding "-gp32" multilibs to gcc,
5725 but to set this flag before gcc is built with such multilibs will
5726 break too many systems.''
5728 But even more unhelpfully, the default linker output target for
5729 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5730 for 64-bit programs - you need to change the ABI to change this,
5731 and not all gcc targets support that currently. Therefore using
5732 this flag to detect 32-bit mode would do the wrong thing given
5733 the current gcc - it would make GDB treat these 64-bit programs
5734 as 32-bit programs by default. */
5736 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5737 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5738 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5740 /* Add/remove bits from an address. The MIPS needs be careful to
5741 ensure that all 32 bit addresses are sign extended to 64 bits. */
5742 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5744 /* Unwind the frame. */
5745 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5746 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5748 /* Map debug register numbers onto internal register numbers. */
5749 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5750 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5751 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5752 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5753 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5754 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5755 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5756 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5758 /* MIPS version of CALL_DUMMY */
5760 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5761 replaced by a command, and all targets will default to on stack
5762 (regardless of the stack's execute status). */
5763 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5764 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5766 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5767 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5768 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5770 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5771 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5773 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5775 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5776 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5777 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5779 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5781 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5782 set_gdbarch_deprecated_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
5784 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5786 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5787 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5788 need to all be folded into the target vector. Since they are
5789 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5790 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5792 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5794 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
5796 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5797 to support MIPS16. This is a bad thing. Make sure not to do it
5798 if we have an OS ABI that actually supports shared libraries, since
5799 shared library support is more important. If we have an OS someday
5800 that supports both shared libraries and MIPS16, we'll have to find
5801 a better place for these. */
5802 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5804 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5805 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
5808 /* Hook in OS ABI-specific overrides, if they have been registered. */
5809 gdbarch_init_osabi (info
, gdbarch
);
5811 /* Unwind the frame. */
5812 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
5813 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
5819 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5821 struct gdbarch_info info
;
5823 /* Force the architecture to update, and (if it's a MIPS architecture)
5824 mips_gdbarch_init will take care of the rest. */
5825 gdbarch_info_init (&info
);
5826 gdbarch_update_p (info
);
5829 /* Print out which MIPS ABI is in use. */
5832 show_mips_abi (char *ignore_args
, int from_tty
)
5834 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5836 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5839 enum mips_abi global_abi
= global_mips_abi ();
5840 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5841 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5843 if (global_abi
== MIPS_ABI_UNKNOWN
)
5845 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5847 else if (global_abi
== actual_abi
)
5849 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5853 /* Probably shouldn't happen... */
5855 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5856 actual_abi_str
, mips_abi_strings
[global_abi
]);
5862 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5864 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5868 int ef_mips_32bitmode
;
5869 /* determine the ISA */
5870 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5888 /* determine the size of a pointer */
5889 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5890 fprintf_unfiltered (file
,
5891 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5893 fprintf_unfiltered (file
,
5894 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5896 fprintf_unfiltered (file
,
5897 "mips_dump_tdep: ef_mips_arch = %d\n",
5899 fprintf_unfiltered (file
,
5900 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5901 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5902 fprintf_unfiltered (file
,
5903 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5904 mips_mask_address_p (tdep
),
5905 tdep
->default_mask_address_p
);
5907 fprintf_unfiltered (file
,
5908 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5909 FP_REGISTER_DOUBLE
);
5910 fprintf_unfiltered (file
,
5911 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5912 MIPS_DEFAULT_FPU_TYPE
,
5913 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5914 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5915 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5917 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5918 fprintf_unfiltered (file
,
5919 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5921 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5922 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5923 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5925 fprintf_unfiltered (file
,
5926 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5927 FP_REGISTER_DOUBLE
);
5928 fprintf_unfiltered (file
,
5929 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5930 mips_stack_argsize (current_gdbarch
));
5931 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
5932 fprintf_unfiltered (file
,
5933 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5934 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
5935 fprintf_unfiltered (file
,
5936 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5937 XSTRING (ATTACH_DETACH
));
5938 fprintf_unfiltered (file
,
5939 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5940 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5941 fprintf_unfiltered (file
,
5942 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5943 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5944 fprintf_unfiltered (file
,
5945 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5946 FIRST_EMBED_REGNUM
);
5947 fprintf_unfiltered (file
,
5948 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
5949 XSTRING (IGNORE_HELPER_CALL (PC
)));
5950 fprintf_unfiltered (file
,
5951 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5952 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
5953 fprintf_unfiltered (file
,
5954 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
5955 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
5956 fprintf_unfiltered (file
,
5957 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5959 #ifdef MACHINE_CPROC_FP_OFFSET
5960 fprintf_unfiltered (file
,
5961 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5962 MACHINE_CPROC_FP_OFFSET
);
5964 #ifdef MACHINE_CPROC_PC_OFFSET
5965 fprintf_unfiltered (file
,
5966 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5967 MACHINE_CPROC_PC_OFFSET
);
5969 #ifdef MACHINE_CPROC_SP_OFFSET
5970 fprintf_unfiltered (file
,
5971 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5972 MACHINE_CPROC_SP_OFFSET
);
5974 fprintf_unfiltered (file
,
5975 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5977 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5978 fprintf_unfiltered (file
,
5979 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5980 fprintf_unfiltered (file
,
5981 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
5982 fprintf_unfiltered (file
,
5983 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5984 MIPS_LAST_ARG_REGNUM
,
5985 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
5986 fprintf_unfiltered (file
,
5987 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
5988 fprintf_unfiltered (file
,
5989 "mips_dump_tdep: mips_abi_regsize() = %d\n",
5990 mips_abi_regsize (current_gdbarch
));
5991 fprintf_unfiltered (file
,
5992 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
5993 fprintf_unfiltered (file
,
5994 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5995 fprintf_unfiltered (file
,
5996 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5997 fprintf_unfiltered (file
,
5998 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5999 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6000 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6001 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6002 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6003 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6004 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6005 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6006 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6007 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6008 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6009 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6011 fprintf_unfiltered (file
,
6012 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6015 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6018 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6020 fprintf_unfiltered (file
,
6021 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6022 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6023 fprintf_unfiltered (file
,
6024 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6025 fprintf_unfiltered (file
,
6026 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6027 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6028 fprintf_unfiltered (file
,
6029 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6030 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6031 fprintf_unfiltered (file
,
6032 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6033 SOFTWARE_SINGLE_STEP_P ());
6034 fprintf_unfiltered (file
,
6035 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6036 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6037 #ifdef STACK_END_ADDR
6038 fprintf_unfiltered (file
,
6039 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6042 fprintf_unfiltered (file
,
6043 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6044 XSTRING (STEP_SKIPS_DELAY (PC
)));
6045 fprintf_unfiltered (file
,
6046 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6047 STEP_SKIPS_DELAY_P
);
6048 fprintf_unfiltered (file
,
6049 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6050 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6051 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6052 fprintf_unfiltered (file
,
6053 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6054 fprintf_unfiltered (file
,
6055 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6056 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6057 (TYPE
, CNT
, OTHERTYPE
)));
6058 fprintf_unfiltered (file
,
6059 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6060 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6062 fprintf_unfiltered (file
,
6063 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6064 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6067 fprintf_unfiltered (file
,
6068 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6070 #ifdef TRACE_FLAVOR_SIZE
6071 fprintf_unfiltered (file
,
6072 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6076 fprintf_unfiltered (file
,
6077 "mips_dump_tdep: TRACE_SET # %s\n",
6078 XSTRING (TRACE_SET (X
, STATE
)));
6080 #ifdef UNUSED_REGNUM
6081 fprintf_unfiltered (file
,
6082 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6084 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6085 fprintf_unfiltered (file
,
6086 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6087 (long) VM_MIN_ADDRESS
);
6088 fprintf_unfiltered (file
,
6089 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6090 fprintf_unfiltered (file
,
6091 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6094 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6097 _initialize_mips_tdep (void)
6099 static struct cmd_list_element
*mipsfpulist
= NULL
;
6100 struct cmd_list_element
*c
;
6102 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6103 if (MIPS_ABI_LAST
+ 1
6104 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6105 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6107 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6109 mips_pdr_data
= register_objfile_data ();
6111 /* Add root prefix command for all "set mips"/"show mips" commands */
6112 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6113 "Various MIPS specific commands.",
6114 &setmipscmdlist
, "set mips ", 0, &setlist
);
6116 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6117 "Various MIPS specific commands.",
6118 &showmipscmdlist
, "show mips ", 0, &showlist
);
6120 /* Allow the user to override the saved register size. */
6121 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6124 &mips_abi_regsize_string
, "\
6125 Set size of general purpose registers saved on the stack.\n\
6126 This option can be set to one of:\n\
6127 32 - Force GDB to treat saved GP registers as 32-bit\n\
6128 64 - Force GDB to treat saved GP registers as 64-bit\n\
6129 auto - Allow GDB to use the target's default setting or autodetect the\n\
6130 saved GP register size from information contained in the executable.\n\
6131 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6133 /* Allow the user to override the argument stack size. */
6134 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6137 &mips_stack_argsize_string
, "\
6138 Set the amount of stack space reserved for each argument.\n\
6139 This option can be set to one of:\n\
6140 32 - Force GDB to allocate 32-bit chunks per argument\n\
6141 64 - Force GDB to allocate 64-bit chunks per argument\n\
6142 auto - Allow GDB to determine the correct setting from the current\n\
6143 target and executable (default)", &setmipscmdlist
), &showmipscmdlist
);
6145 /* Allow the user to override the ABI. */
6146 c
= add_set_enum_cmd
6147 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6148 "Set the ABI used by this program.\n"
6149 "This option can be set to one of:\n"
6150 " auto - the default ABI associated with the current binary\n"
6152 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6153 set_cmd_sfunc (c
, mips_abi_update
);
6154 add_cmd ("abi", class_obscure
, show_mips_abi
,
6155 "Show ABI in use by MIPS target", &showmipscmdlist
);
6157 /* Let the user turn off floating point and set the fence post for
6158 heuristic_proc_start. */
6160 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6161 "Set use of MIPS floating-point coprocessor.",
6162 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6163 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6164 "Select single-precision MIPS floating-point coprocessor.",
6166 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6167 "Select double-precision MIPS floating-point coprocessor.",
6169 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6170 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6171 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6172 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6173 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6174 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6175 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6176 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6177 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6178 "Select MIPS floating-point coprocessor automatically.",
6180 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6181 "Show current use of MIPS floating-point coprocessor target.",
6184 /* We really would like to have both "0" and "unlimited" work, but
6185 command.c doesn't deal with that. So make it a var_zinteger
6186 because the user can always use "999999" or some such for unlimited. */
6187 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6188 (char *) &heuristic_fence_post
, "\
6189 Set the distance searched for the start of a function.\n\
6190 If you are debugging a stripped executable, GDB needs to search through the\n\
6191 program for the start of a function. This command sets the distance of the\n\
6192 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6193 /* We need to throw away the frame cache when we set this, since it
6194 might change our ability to get backtraces. */
6195 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6196 add_show_from_set (c
, &showlist
);
6198 /* Allow the user to control whether the upper bits of 64-bit
6199 addresses should be zeroed. */
6200 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6201 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6202 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6203 allow GDB to determine the correct value.\n", "\
6204 Show zeroing of upper 32 bits of 64-bit addresses.",
6205 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6207 /* Allow the user to control the size of 32 bit registers within the
6208 raw remote packet. */
6209 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6210 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6211 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6212 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6213 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6214 64 bits for others. Use \"off\" to disable compatibility mode", "\
6215 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6216 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6217 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6218 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6220 /* Debug this files internals. */
6221 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6222 &mips_debug
, "Set mips debugging.\n\
6223 When non-zero, mips specific debugging is enabled.", &setdebuglist
), &showdebuglist
);