1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string
;
76 static const char *mips_abi_strings
[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc
;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto
[] = "auto";
98 static const char size_32
[] = "32";
99 static const char size_64
[] = "64";
101 static const char *size_enums
[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE
/* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto
= 1;
123 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
125 static int mips_debug
= 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi
;
135 enum mips_abi found_abi
;
136 enum mips_fpu_type mips_fpu_type
;
137 int mips_last_arg_regnum
;
138 int mips_last_fp_arg_regnum
;
139 int mips_default_saved_regsize
;
140 int mips_fp_register_double
;
141 int mips_default_stack_argsize
;
142 int gdb_target_is_mips64
;
143 int default_mask_address_p
;
145 enum gdb_osabi osabi
;
148 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
149 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
151 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
153 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
155 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
157 /* Return the currently configured (or set) saved register size. */
159 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
161 static const char *mips_saved_regsize_string
= size_auto
;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string
== size_auto
)
169 return MIPS_DEFAULT_SAVED_REGSIZE
;
170 else if (mips_saved_regsize_string
== size_64
)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* Functions for setting and testing a bit in a minimal symbol that
177 marks it as 16-bit function. The MSB of the minimal symbol's
178 "info" field is used for this purpose. This field is already
179 being used to store the symbol size, so the assumption is
180 that the symbol size cannot exceed 2^31.
182 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
183 i.e. refers to a 16-bit function, and sets a "special" bit in a
184 minimal symbol to mark it as a 16-bit function
186 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
187 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
188 the "info" field with the "special" bit masked out */
191 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
193 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
195 MSYMBOL_INFO (msym
) = (char *)
196 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
197 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
202 msymbol_is_special (struct minimal_symbol
*msym
)
204 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
208 msymbol_size (struct minimal_symbol
*msym
)
210 return ((long) MSYMBOL_INFO (msym
) & 0x7fffffff);
213 /* XFER a value from the big/little/left end of the register.
214 Depending on the size of the value it might occupy the entire
215 register or just part of it. Make an allowance for this, aligning
216 things accordingly. */
219 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
220 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
223 bfd_byte
*reg
= alloca (MAX_REGISTER_RAW_SIZE
);
225 /* Need to transfer the left or right part of the register, based on
226 the targets byte order. */
230 reg_offset
= REGISTER_RAW_SIZE (reg_num
) - length
;
232 case BFD_ENDIAN_LITTLE
:
235 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
239 internal_error (__FILE__
, __LINE__
, "bad switch");
242 fprintf_unfiltered (gdb_stderr
,
243 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
244 reg_num
, reg_offset
, buf_offset
, length
);
245 if (mips_debug
&& out
!= NULL
)
248 fprintf_unfiltered (gdb_stdlog
, "out ");
249 for (i
= 0; i
< length
; i
++)
250 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
253 regcache_raw_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
255 regcache_raw_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
256 if (mips_debug
&& in
!= NULL
)
259 fprintf_unfiltered (gdb_stdlog
, "in ");
260 for (i
= 0; i
< length
; i
++)
261 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
264 fprintf_unfiltered (gdb_stdlog
, "\n");
267 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
268 compatiblity mode. A return value of 1 means that we have
269 physical 64-bit registers, but should treat them as 32-bit registers. */
272 mips2_fp_compat (void)
274 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
276 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
280 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
281 in all the places we deal with FP registers. PR gdb/413. */
282 /* Otherwise check the FR bit in the status register - it controls
283 the FP compatiblity mode. If it is clear we are in compatibility
285 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
292 /* Indicate that the ABI makes use of double-precision registers
293 provided by the FPU (rather than combining pairs of registers to
294 form double-precision values). Do not use "TARGET_IS_MIPS64" to
295 determine if the ABI is using double-precision registers. See also
297 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
299 /* The amount of space reserved on the stack for registers. This is
300 different to MIPS_SAVED_REGSIZE as it determines the alignment of
301 data allocated after the registers have run out. */
303 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
305 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
307 static const char *mips_stack_argsize_string
= size_auto
;
310 mips_stack_argsize (void)
312 if (mips_stack_argsize_string
== size_auto
)
313 return MIPS_DEFAULT_STACK_ARGSIZE
;
314 else if (mips_stack_argsize_string
== size_64
)
316 else /* if (mips_stack_argsize_string == size_32) */
320 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
322 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
324 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
326 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
328 static void mips_print_register (int, int);
330 static mips_extra_func_info_t
331 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
333 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
335 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
337 static int mips_set_processor_type (char *);
339 static void mips_show_processor_type_command (char *, int);
341 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
343 static mips_extra_func_info_t
344 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
346 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
347 mips_extra_func_info_t proc_desc
);
349 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
350 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
352 static struct type
*mips_float_register_type (void);
353 static struct type
*mips_double_register_type (void);
355 /* This value is the model of MIPS in use. It is derived from the value
356 of the PrID register. */
358 char *mips_processor_type
;
360 char *tmp_mips_processor_type
;
362 /* The list of available "set mips " and "show mips " commands */
364 static struct cmd_list_element
*setmipscmdlist
= NULL
;
365 static struct cmd_list_element
*showmipscmdlist
= NULL
;
367 /* A set of original names, to be used when restoring back to generic
368 registers from a specific set. */
370 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
371 char **mips_processor_reg_names
= mips_generic_reg_names
;
374 mips_register_name (int i
)
376 return mips_processor_reg_names
[i
];
379 /* Names of IDT R3041 registers. */
381 char *mips_r3041_reg_names
[] = {
382 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
383 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
384 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
385 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
386 "sr", "lo", "hi", "bad", "cause","pc",
387 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
388 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
389 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
390 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
391 "fsr", "fir", "fp", "",
392 "", "", "bus", "ccfg", "", "", "", "",
393 "", "", "port", "cmp", "", "", "epc", "prid",
396 /* Names of IDT R3051 registers. */
398 char *mips_r3051_reg_names
[] = {
399 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
400 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
401 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
402 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
403 "sr", "lo", "hi", "bad", "cause","pc",
404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
408 "fsr", "fir", "fp", "",
409 "inx", "rand", "elo", "", "ctxt", "", "", "",
410 "", "", "ehi", "", "", "", "epc", "prid",
413 /* Names of IDT R3081 registers. */
415 char *mips_r3081_reg_names
[] = {
416 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
417 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
418 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
419 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
420 "sr", "lo", "hi", "bad", "cause","pc",
421 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
422 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
423 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
424 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
425 "fsr", "fir", "fp", "",
426 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
427 "", "", "ehi", "", "", "", "epc", "prid",
430 /* Names of LSI 33k registers. */
432 char *mips_lsi33k_reg_names
[] = {
433 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
434 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
435 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
436 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
437 "epc", "hi", "lo", "sr", "cause","badvaddr",
438 "dcic", "bpc", "bda", "", "", "", "", "",
439 "", "", "", "", "", "", "", "",
440 "", "", "", "", "", "", "", "",
441 "", "", "", "", "", "", "", "",
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
450 } mips_processor_type_table
[] = {
451 { "generic", mips_generic_reg_names
},
452 { "r3041", mips_r3041_reg_names
},
453 { "r3051", mips_r3051_reg_names
},
454 { "r3071", mips_r3081_reg_names
},
455 { "r3081", mips_r3081_reg_names
},
456 { "lsi33k", mips_lsi33k_reg_names
},
464 /* Table to translate MIPS16 register field to actual register number. */
465 static int mips16_to_32_reg
[8] =
466 {16, 17, 2, 3, 4, 5, 6, 7};
468 /* Heuristic_proc_start may hunt through the text section for a long
469 time across a 2400 baud serial line. Allows the user to limit this
472 static unsigned int heuristic_fence_post
= 0;
474 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
475 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
476 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
477 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
478 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
479 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
480 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
481 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
482 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
483 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
484 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
485 this will corrupt pdr.iline. Fortunately we don't use it. */
486 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
487 #define _PROC_MAGIC_ 0x0F0F0F0F
488 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
489 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
491 struct linked_proc_info
493 struct mips_extra_func_info info
;
494 struct linked_proc_info
*next
;
496 *linked_proc_desc_table
= NULL
;
499 mips_print_extra_frame_info (struct frame_info
*fi
)
503 && fi
->extra_info
->proc_desc
504 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
505 printf_filtered (" frame pointer is at %s+%s\n",
506 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
507 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
510 /* Number of bytes of storage in the actual machine representation for
511 register N. NOTE: This indirectly defines the register size
512 transfered by the GDB protocol. */
514 static int mips64_transfers_32bit_regs_p
= 0;
517 mips_register_raw_size (int reg_nr
)
519 if (mips64_transfers_32bit_regs_p
)
520 return REGISTER_VIRTUAL_SIZE (reg_nr
);
521 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
522 && FP_REGISTER_DOUBLE
)
523 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
530 /* Convert between RAW and VIRTUAL registers. The RAW register size
531 defines the remote-gdb packet. */
534 mips_register_convertible (int reg_nr
)
536 if (mips64_transfers_32bit_regs_p
)
539 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
543 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
544 char *raw_buf
, char *virt_buf
)
546 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
548 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
549 TYPE_LENGTH (virtual_type
));
553 TYPE_LENGTH (virtual_type
));
557 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
558 char *virt_buf
, char *raw_buf
)
560 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
561 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
562 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
564 TYPE_LENGTH (virtual_type
));
568 TYPE_LENGTH (virtual_type
));
572 mips_register_convert_to_type (int regnum
, struct type
*type
, char *buffer
)
574 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
575 && REGISTER_RAW_SIZE (regnum
) == 4
576 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
577 && TYPE_CODE(type
) == TYPE_CODE_FLT
578 && TYPE_LENGTH(type
) == 8)
581 memcpy (temp
, ((char *)(buffer
))+4, 4);
582 memcpy (((char *)(buffer
))+4, (buffer
), 4);
583 memcpy (((char *)(buffer
)), temp
, 4);
588 mips_register_convert_from_type (int regnum
, struct type
*type
, char *buffer
)
590 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
591 && REGISTER_RAW_SIZE (regnum
) == 4
592 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
593 && TYPE_CODE(type
) == TYPE_CODE_FLT
594 && TYPE_LENGTH(type
) == 8)
597 memcpy (temp
, ((char *)(buffer
))+4, 4);
598 memcpy (((char *)(buffer
))+4, (buffer
), 4);
599 memcpy (((char *)(buffer
)), temp
, 4);
603 /* Return the GDB type object for the "standard" data type
604 of data in register REG.
606 Note: kevinb/2002-08-01: The definition below should faithfully
607 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
608 definitions found in config/mips/tm-*.h. I'm concerned about
609 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
610 though. In some cases FP_REGNUM is in this range, and I doubt
611 that this code is correct for the 64-bit case. */
614 mips_register_virtual_type (int reg
)
616 if (FP0_REGNUM
<= reg
&& reg
< FP0_REGNUM
+ 32)
618 /* Floating point registers... */
619 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
620 return builtin_type_ieee_double_big
;
622 return builtin_type_ieee_double_little
;
624 else if (reg
== PS_REGNUM
/* CR */)
625 return builtin_type_uint32
;
626 else if (FCRCS_REGNUM
<= reg
&& reg
<= LAST_EMBED_REGNUM
)
627 return builtin_type_uint32
;
630 /* Everything else...
631 Return type appropriate for width of register. */
632 if (MIPS_REGSIZE
== TYPE_LENGTH (builtin_type_uint64
))
633 return builtin_type_uint64
;
635 return builtin_type_uint32
;
639 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
644 return ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
647 /* Should the upper word of 64-bit addresses be zeroed? */
648 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
651 mips_mask_address_p (void)
653 switch (mask_address_var
)
655 case AUTO_BOOLEAN_TRUE
:
657 case AUTO_BOOLEAN_FALSE
:
660 case AUTO_BOOLEAN_AUTO
:
661 return MIPS_DEFAULT_MASK_ADDRESS_P
;
663 internal_error (__FILE__
, __LINE__
,
664 "mips_mask_address_p: bad switch");
670 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
672 switch (mask_address_var
)
674 case AUTO_BOOLEAN_TRUE
:
675 printf_filtered ("The 32 bit mips address mask is enabled\n");
677 case AUTO_BOOLEAN_FALSE
:
678 printf_filtered ("The 32 bit mips address mask is disabled\n");
680 case AUTO_BOOLEAN_AUTO
:
681 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
682 mips_mask_address_p () ? "enabled" : "disabled");
685 internal_error (__FILE__
, __LINE__
,
686 "show_mask_address: bad switch");
691 /* Should call_function allocate stack space for a struct return? */
694 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
696 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
700 mips_n32n64_use_struct_convention (int gcc_p
, struct type
*type
)
702 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
706 mips_o32_use_struct_convention (int gcc_p
, struct type
*type
)
708 return 1; /* Structures are returned by ref in extra arg0. */
711 /* Should call_function pass struct by reference?
712 For each architecture, structs are passed either by
713 value or by reference, depending on their size. */
716 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
718 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
719 int len
= TYPE_LENGTH (check_typedef (type
));
721 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
722 return (len
> MIPS_SAVED_REGSIZE
);
728 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
730 return 0; /* Assumption: N32/N64 never passes struct by ref. */
734 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
736 return 0; /* Assumption: O32/O64 never passes struct by ref. */
739 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
742 pc_is_mips16 (bfd_vma memaddr
)
744 struct minimal_symbol
*sym
;
746 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
747 if (IS_MIPS16_ADDR (memaddr
))
750 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
751 the high bit of the info field. Use this to decide if the function is
752 MIPS16 or normal MIPS. */
753 sym
= lookup_minimal_symbol_by_pc (memaddr
);
755 return msymbol_is_special (sym
);
760 /* MIPS believes that the PC has a sign extended value. Perhaphs the
761 all registers should be sign extended for simplicity? */
764 mips_read_pc (ptid_t ptid
)
766 return read_signed_register_pid (PC_REGNUM
, ptid
);
769 /* This returns the PC of the first inst after the prologue. If we can't
770 find the prologue, then return 0. */
773 after_prologue (CORE_ADDR pc
,
774 mips_extra_func_info_t proc_desc
)
776 struct symtab_and_line sal
;
777 CORE_ADDR func_addr
, func_end
;
779 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
780 to read the stack pointer from the current machine state, because
781 the current machine state has nothing to do with the information
782 we need from the proc_desc; and the process may or may not exist
785 proc_desc
= find_proc_desc (pc
, NULL
, 0);
789 /* If function is frameless, then we need to do it the hard way. I
790 strongly suspect that frameless always means prologueless... */
791 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
792 && PROC_FRAME_OFFSET (proc_desc
) == 0)
796 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
797 return 0; /* Unknown */
799 sal
= find_pc_line (func_addr
, 0);
801 if (sal
.end
< func_end
)
804 /* The line after the prologue is after the end of the function. In this
805 case, tell the caller to find the prologue the hard way. */
810 /* Decode a MIPS32 instruction that saves a register in the stack, and
811 set the appropriate bit in the general register mask or float register mask
812 to indicate which register is saved. This is a helper function
813 for mips_find_saved_regs. */
816 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
817 unsigned long *float_mask
)
821 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
822 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
823 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
825 /* It might be possible to use the instruction to
826 find the offset, rather than the code below which
827 is based on things being in a certain order in the
828 frame, but figuring out what the instruction's offset
829 is relative to might be a little tricky. */
830 reg
= (inst
& 0x001f0000) >> 16;
831 *gen_mask
|= (1 << reg
);
833 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
834 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
835 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
838 reg
= ((inst
& 0x001f0000) >> 16);
839 *float_mask
|= (1 << reg
);
843 /* Decode a MIPS16 instruction that saves a register in the stack, and
844 set the appropriate bit in the general register or float register mask
845 to indicate which register is saved. This is a helper function
846 for mips_find_saved_regs. */
849 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
851 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
853 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
854 *gen_mask
|= (1 << reg
);
856 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
858 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
859 *gen_mask
|= (1 << reg
);
861 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
862 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
863 *gen_mask
|= (1 << RA_REGNUM
);
867 /* Fetch and return instruction from the specified location. If the PC
868 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
871 mips_fetch_instruction (CORE_ADDR addr
)
873 char buf
[MIPS_INSTLEN
];
877 if (pc_is_mips16 (addr
))
879 instlen
= MIPS16_INSTLEN
;
880 addr
= UNMAKE_MIPS16_ADDR (addr
);
883 instlen
= MIPS_INSTLEN
;
884 status
= read_memory_nobpt (addr
, buf
, instlen
);
886 memory_error (status
, addr
);
887 return extract_unsigned_integer (buf
, instlen
);
891 /* These the fields of 32 bit mips instructions */
892 #define mips32_op(x) (x >> 26)
893 #define itype_op(x) (x >> 26)
894 #define itype_rs(x) ((x >> 21) & 0x1f)
895 #define itype_rt(x) ((x >> 16) & 0x1f)
896 #define itype_immediate(x) (x & 0xffff)
898 #define jtype_op(x) (x >> 26)
899 #define jtype_target(x) (x & 0x03ffffff)
901 #define rtype_op(x) (x >> 26)
902 #define rtype_rs(x) ((x >> 21) & 0x1f)
903 #define rtype_rt(x) ((x >> 16) & 0x1f)
904 #define rtype_rd(x) ((x >> 11) & 0x1f)
905 #define rtype_shamt(x) ((x >> 6) & 0x1f)
906 #define rtype_funct(x) (x & 0x3f)
909 mips32_relative_offset (unsigned long inst
)
912 x
= itype_immediate (inst
);
913 if (x
& 0x8000) /* sign bit set */
915 x
|= 0xffff0000; /* sign extension */
921 /* Determine whate to set a single step breakpoint while considering
924 mips32_next_pc (CORE_ADDR pc
)
928 inst
= mips_fetch_instruction (pc
);
929 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
931 if (itype_op (inst
) >> 2 == 5)
932 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
934 op
= (itype_op (inst
) & 0x03);
949 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
950 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
952 int tf
= itype_rt (inst
) & 0x01;
953 int cnum
= itype_rt (inst
) >> 2;
954 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
955 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
957 if (((cond
>> cnum
) & 0x01) == tf
)
958 pc
+= mips32_relative_offset (inst
) + 4;
963 pc
+= 4; /* Not a branch, next instruction is easy */
966 { /* This gets way messy */
968 /* Further subdivide into SPECIAL, REGIMM and other */
969 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
971 case 0: /* SPECIAL */
972 op
= rtype_funct (inst
);
977 /* Set PC to that address */
978 pc
= read_signed_register (rtype_rs (inst
));
984 break; /* end SPECIAL */
987 op
= itype_rt (inst
); /* branch condition */
992 case 16: /* BLTZAL */
993 case 18: /* BLTZALL */
995 if (read_signed_register (itype_rs (inst
)) < 0)
996 pc
+= mips32_relative_offset (inst
) + 4;
998 pc
+= 8; /* after the delay slot */
1002 case 17: /* BGEZAL */
1003 case 19: /* BGEZALL */
1004 greater_equal_branch
:
1005 if (read_signed_register (itype_rs (inst
)) >= 0)
1006 pc
+= mips32_relative_offset (inst
) + 4;
1008 pc
+= 8; /* after the delay slot */
1010 /* All of the other instructions in the REGIMM category */
1015 break; /* end REGIMM */
1020 reg
= jtype_target (inst
) << 2;
1021 /* Upper four bits get never changed... */
1022 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1025 /* FIXME case JALX : */
1028 reg
= jtype_target (inst
) << 2;
1029 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1030 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1032 break; /* The new PC will be alternate mode */
1033 case 4: /* BEQ, BEQL */
1035 if (read_signed_register (itype_rs (inst
)) ==
1036 read_signed_register (itype_rt (inst
)))
1037 pc
+= mips32_relative_offset (inst
) + 4;
1041 case 5: /* BNE, BNEL */
1043 if (read_signed_register (itype_rs (inst
)) !=
1044 read_signed_register (itype_rt (inst
)))
1045 pc
+= mips32_relative_offset (inst
) + 4;
1049 case 6: /* BLEZ, BLEZL */
1051 if (read_signed_register (itype_rs (inst
) <= 0))
1052 pc
+= mips32_relative_offset (inst
) + 4;
1058 greater_branch
: /* BGTZ, BGTZL */
1059 if (read_signed_register (itype_rs (inst
) > 0))
1060 pc
+= mips32_relative_offset (inst
) + 4;
1067 } /* mips32_next_pc */
1069 /* Decoding the next place to set a breakpoint is irregular for the
1070 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1071 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1072 We dont want to set a single step instruction on the extend instruction
1076 /* Lots of mips16 instruction formats */
1077 /* Predicting jumps requires itype,ritype,i8type
1078 and their extensions extItype,extritype,extI8type
1080 enum mips16_inst_fmts
1082 itype
, /* 0 immediate 5,10 */
1083 ritype
, /* 1 5,3,8 */
1084 rrtype
, /* 2 5,3,3,5 */
1085 rritype
, /* 3 5,3,3,5 */
1086 rrrtype
, /* 4 5,3,3,3,2 */
1087 rriatype
, /* 5 5,3,3,1,4 */
1088 shifttype
, /* 6 5,3,3,3,2 */
1089 i8type
, /* 7 5,3,8 */
1090 i8movtype
, /* 8 5,3,3,5 */
1091 i8mov32rtype
, /* 9 5,3,5,3 */
1092 i64type
, /* 10 5,3,8 */
1093 ri64type
, /* 11 5,3,3,5 */
1094 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1095 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1096 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1097 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1098 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1099 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1100 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1101 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1102 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1103 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1105 /* I am heaping all the fields of the formats into one structure and
1106 then, only the fields which are involved in instruction extension */
1110 unsigned int regx
; /* Function in i8 type */
1115 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1116 for the bits which make up the immediatate extension. */
1119 extended_offset (unsigned int extension
)
1122 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1124 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1126 value
|= extension
& 0x01f; /* extract 4:0 */
1130 /* Only call this function if you know that this is an extendable
1131 instruction, It wont malfunction, but why make excess remote memory references?
1132 If the immediate operands get sign extended or somthing, do it after
1133 the extension is performed.
1135 /* FIXME: Every one of these cases needs to worry about sign extension
1136 when the offset is to be used in relative addressing */
1140 fetch_mips_16 (CORE_ADDR pc
)
1143 pc
&= 0xfffffffe; /* clear the low order bit */
1144 target_read_memory (pc
, buf
, 2);
1145 return extract_unsigned_integer (buf
, 2);
1149 unpack_mips16 (CORE_ADDR pc
,
1150 unsigned int extension
,
1152 enum mips16_inst_fmts insn_format
,
1153 struct upk_mips16
*upk
)
1158 switch (insn_format
)
1165 value
= extended_offset (extension
);
1166 value
= value
<< 11; /* rom for the original value */
1167 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1171 value
= inst
& 0x7ff;
1172 /* FIXME : Consider sign extension */
1181 { /* A register identifier and an offset */
1182 /* Most of the fields are the same as I type but the
1183 immediate value is of a different length */
1187 value
= extended_offset (extension
);
1188 value
= value
<< 8; /* from the original instruction */
1189 value
|= inst
& 0xff; /* eleven bits from instruction */
1190 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1191 if (value
& 0x4000) /* test the sign bit , bit 26 */
1193 value
&= ~0x3fff; /* remove the sign bit */
1199 value
= inst
& 0xff; /* 8 bits */
1200 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1201 /* FIXME: Do sign extension , this format needs it */
1202 if (value
& 0x80) /* THIS CONFUSES ME */
1204 value
&= 0xef; /* remove the sign bit */
1214 unsigned long value
;
1215 unsigned int nexthalf
;
1216 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1217 value
= value
<< 16;
1218 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1226 internal_error (__FILE__
, __LINE__
,
1229 upk
->offset
= offset
;
1236 add_offset_16 (CORE_ADDR pc
, int offset
)
1238 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1242 extended_mips16_next_pc (CORE_ADDR pc
,
1243 unsigned int extension
,
1246 int op
= (insn
>> 11);
1249 case 2: /* Branch */
1252 struct upk_mips16 upk
;
1253 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1254 offset
= upk
.offset
;
1260 pc
+= (offset
<< 1) + 2;
1263 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1265 struct upk_mips16 upk
;
1266 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1267 pc
= add_offset_16 (pc
, upk
.offset
);
1268 if ((insn
>> 10) & 0x01) /* Exchange mode */
1269 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1276 struct upk_mips16 upk
;
1278 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1279 reg
= read_signed_register (upk
.regx
);
1281 pc
+= (upk
.offset
<< 1) + 2;
1288 struct upk_mips16 upk
;
1290 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1291 reg
= read_signed_register (upk
.regx
);
1293 pc
+= (upk
.offset
<< 1) + 2;
1298 case 12: /* I8 Formats btez btnez */
1300 struct upk_mips16 upk
;
1302 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1303 /* upk.regx contains the opcode */
1304 reg
= read_signed_register (24); /* Test register is 24 */
1305 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1306 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1307 /* pc = add_offset_16(pc,upk.offset) ; */
1308 pc
+= (upk
.offset
<< 1) + 2;
1313 case 29: /* RR Formats JR, JALR, JALR-RA */
1315 struct upk_mips16 upk
;
1316 /* upk.fmt = rrtype; */
1321 upk
.regx
= (insn
>> 8) & 0x07;
1322 upk
.regy
= (insn
>> 5) & 0x07;
1330 break; /* Function return instruction */
1336 break; /* BOGUS Guess */
1338 pc
= read_signed_register (reg
);
1345 /* This is an instruction extension. Fetch the real instruction
1346 (which follows the extension) and decode things based on
1350 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1363 mips16_next_pc (CORE_ADDR pc
)
1365 unsigned int insn
= fetch_mips_16 (pc
);
1366 return extended_mips16_next_pc (pc
, 0, insn
);
1369 /* The mips_next_pc function supports single_step when the remote
1370 target monitor or stub is not developed enough to do a single_step.
1371 It works by decoding the current instruction and predicting where a
1372 branch will go. This isnt hard because all the data is available.
1373 The MIPS32 and MIPS16 variants are quite different */
1375 mips_next_pc (CORE_ADDR pc
)
1378 return mips16_next_pc (pc
);
1380 return mips32_next_pc (pc
);
1383 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1386 Note: kevinb/2002-08-09: The only caller of this function is (and
1387 should remain) mips_frame_init_saved_regs(). In fact,
1388 aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs()
1389 does nothing more than set frame->saved_regs[SP_REGNUM]. These two
1390 functions should really be combined and now that there is only one
1391 caller, it should be straightforward. (Watch out for multiple returns
1395 mips_find_saved_regs (struct frame_info
*fci
)
1398 CORE_ADDR reg_position
;
1399 /* r0 bit means kernel trap */
1401 /* What registers have been saved? Bitmasks. */
1402 unsigned long gen_mask
, float_mask
;
1403 mips_extra_func_info_t proc_desc
;
1406 frame_saved_regs_zalloc (fci
);
1408 /* If it is the frame for sigtramp, the saved registers are located
1409 in a sigcontext structure somewhere on the stack.
1410 If the stack layout for sigtramp changes we might have to change these
1411 constants and the companion fixup_sigtramp in mdebugread.c */
1412 #ifndef SIGFRAME_BASE
1413 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1414 above the sigtramp frame. */
1415 #define SIGFRAME_BASE MIPS_REGSIZE
1416 /* FIXME! Are these correct?? */
1417 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1418 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1419 #define SIGFRAME_FPREGSAVE_OFF \
1420 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1422 #ifndef SIGFRAME_REG_SIZE
1423 /* FIXME! Is this correct?? */
1424 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1426 if (fci
->signal_handler_caller
)
1428 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1430 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1431 + ireg
* SIGFRAME_REG_SIZE
;
1432 fci
->saved_regs
[ireg
] = reg_position
;
1434 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1436 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1437 + ireg
* SIGFRAME_REG_SIZE
;
1438 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1440 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1444 proc_desc
= fci
->extra_info
->proc_desc
;
1445 if (proc_desc
== NULL
)
1446 /* I'm not sure how/whether this can happen. Normally when we can't
1447 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1448 and set the saved_regs right away. */
1451 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1452 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1453 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1455 if ( /* In any frame other than the innermost or a frame interrupted by
1456 a signal, we assume that all registers have been saved.
1457 This assumes that all register saves in a function happen before
1458 the first function call. */
1459 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1461 /* In a dummy frame we know exactly where things are saved. */
1462 && !PROC_DESC_IS_DUMMY (proc_desc
)
1464 /* Don't bother unless we are inside a function prologue. Outside the
1465 prologue, we know where everything is. */
1467 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1469 /* Not sure exactly what kernel_trap means, but if it means
1470 the kernel saves the registers without a prologue doing it,
1471 we better not examine the prologue to see whether registers
1472 have been saved yet. */
1475 /* We need to figure out whether the registers that the proc_desc
1476 claims are saved have been saved yet. */
1480 /* Bitmasks; set if we have found a save for the register. */
1481 unsigned long gen_save_found
= 0;
1482 unsigned long float_save_found
= 0;
1485 /* If the address is odd, assume this is MIPS16 code. */
1486 addr
= PROC_LOW_ADDR (proc_desc
);
1487 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1489 /* Scan through this function's instructions preceding the current
1490 PC, and look for those that save registers. */
1491 while (addr
< fci
->pc
)
1493 inst
= mips_fetch_instruction (addr
);
1494 if (pc_is_mips16 (addr
))
1495 mips16_decode_reg_save (inst
, &gen_save_found
);
1497 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1500 gen_mask
= gen_save_found
;
1501 float_mask
= float_save_found
;
1504 /* Fill in the offsets for the registers which gen_mask says
1506 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1507 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1508 if (gen_mask
& 0x80000000)
1510 fci
->saved_regs
[ireg
] = reg_position
;
1511 reg_position
-= MIPS_SAVED_REGSIZE
;
1514 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1515 of that normally used by gcc. Therefore, we have to fetch the first
1516 instruction of the function, and if it's an entry instruction that
1517 saves $s0 or $s1, correct their saved addresses. */
1518 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1520 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1521 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1524 int sreg_count
= (inst
>> 6) & 3;
1526 /* Check if the ra register was pushed on the stack. */
1527 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1529 reg_position
-= MIPS_SAVED_REGSIZE
;
1531 /* Check if the s0 and s1 registers were pushed on the stack. */
1532 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1534 fci
->saved_regs
[reg
] = reg_position
;
1535 reg_position
-= MIPS_SAVED_REGSIZE
;
1540 /* Fill in the offsets for the registers which float_mask says
1542 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1544 /* Apparently, the freg_offset gives the offset to the first 64 bit
1547 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1548 designates the first saved 64 bit register.
1550 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1551 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1552 FREG_OFFSET, designates the address of the lower register of the
1553 register pair. Adjust the offset so that it designates the upper
1554 register of the pair -- i.e., the address of the first saved 32
1557 if (MIPS_SAVED_REGSIZE
== 4)
1558 reg_position
+= MIPS_SAVED_REGSIZE
;
1560 /* Fill in the offsets for the float registers which float_mask says
1562 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1563 if (float_mask
& 0x80000000)
1565 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1566 reg_position
-= MIPS_SAVED_REGSIZE
;
1569 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1572 /* Set up the 'saved_regs' array. This is a data structure containing
1573 the addresses on the stack where each register has been saved, for
1574 each stack frame. Registers that have not been saved will have
1575 zero here. The stack pointer register is special: rather than the
1576 address where the stack register has been saved, saved_regs[SP_REGNUM]
1577 will have the actual value of the previous frame's stack register. */
1580 mips_frame_init_saved_regs (struct frame_info
*frame
)
1582 if (frame
->saved_regs
== NULL
)
1584 mips_find_saved_regs (frame
);
1586 frame
->saved_regs
[SP_REGNUM
] = frame
->frame
;
1590 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1592 for (; fi
; fi
= fi
->next
)
1594 /* We have to get the saved sp from the sigcontext
1595 if it is a signal handler frame. */
1596 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1600 if (fi
->saved_regs
== NULL
)
1601 FRAME_INIT_SAVED_REGS (fi
);
1602 if (fi
->saved_regs
[regno
])
1603 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1606 return read_signed_register (regno
);
1609 /* mips_addr_bits_remove - remove useless address bits */
1612 mips_addr_bits_remove (CORE_ADDR addr
)
1614 if (GDB_TARGET_IS_MIPS64
)
1616 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1618 /* This hack is a work-around for existing boards using
1619 PMON, the simulator, and any other 64-bit targets that
1620 doesn't have true 64-bit addressing. On these targets,
1621 the upper 32 bits of addresses are ignored by the
1622 hardware. Thus, the PC or SP are likely to have been
1623 sign extended to all 1s by instruction sequences that
1624 load 32-bit addresses. For example, a typical piece of
1625 code that loads an address is this:
1626 lui $r2, <upper 16 bits>
1627 ori $r2, <lower 16 bits>
1628 But the lui sign-extends the value such that the upper 32
1629 bits may be all 1s. The workaround is simply to mask off
1630 these bits. In the future, gcc may be changed to support
1631 true 64-bit addressing, and this masking will have to be
1633 addr
&= (CORE_ADDR
) 0xffffffff;
1636 else if (mips_mask_address_p ())
1638 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1639 masking off bits, instead, the actual target should be asking
1640 for the address to be converted to a valid pointer. */
1641 /* Even when GDB is configured for some 32-bit targets
1642 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1643 so CORE_ADDR is 64 bits. So we still have to mask off
1644 useless bits from addresses. */
1645 addr
&= (CORE_ADDR
) 0xffffffff;
1650 /* mips_software_single_step() is called just before we want to resume
1651 the inferior, if we want to single-step it but there is no hardware
1652 or kernel single-step support (MIPS on GNU/Linux for example). We find
1653 the target of the coming instruction and breakpoint it.
1655 single_step is also called just after the inferior stops. If we had
1656 set up a simulated single-step, we undo our damage. */
1659 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1661 static CORE_ADDR next_pc
;
1662 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1663 static binsn_quantum break_mem
;
1666 if (insert_breakpoints_p
)
1668 pc
= read_register (PC_REGNUM
);
1669 next_pc
= mips_next_pc (pc
);
1671 target_insert_breakpoint (next_pc
, break_mem
);
1674 target_remove_breakpoint (next_pc
, break_mem
);
1678 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1682 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1683 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1684 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1685 prev
->pc
= tmp
? tmp
: pc
;
1690 mips_frame_saved_pc (struct frame_info
*frame
)
1693 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1694 /* We have to get the saved pc from the sigcontext
1695 if it is a signal handler frame. */
1696 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1697 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1699 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1700 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1702 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1704 return ADDR_BITS_REMOVE (saved_pc
);
1707 static struct mips_extra_func_info temp_proc_desc
;
1708 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1710 /* Set a register's saved stack address in temp_saved_regs. If an address
1711 has already been set for this register, do nothing; this way we will
1712 only recognize the first save of a given register in a function prologue.
1713 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1716 set_reg_offset (int regno
, CORE_ADDR offset
)
1718 if (temp_saved_regs
[regno
] == 0)
1719 temp_saved_regs
[regno
] = offset
;
1723 /* Test whether the PC points to the return instruction at the
1724 end of a function. */
1727 mips_about_to_return (CORE_ADDR pc
)
1729 if (pc_is_mips16 (pc
))
1730 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1731 generates a "jr $ra"; other times it generates code to load
1732 the return address from the stack to an accessible register (such
1733 as $a3), then a "jr" using that register. This second case
1734 is almost impossible to distinguish from an indirect jump
1735 used for switch statements, so we don't even try. */
1736 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1738 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1742 /* This fencepost looks highly suspicious to me. Removing it also
1743 seems suspicious as it could affect remote debugging across serial
1747 heuristic_proc_start (CORE_ADDR pc
)
1754 pc
= ADDR_BITS_REMOVE (pc
);
1756 fence
= start_pc
- heuristic_fence_post
;
1760 if (heuristic_fence_post
== UINT_MAX
1761 || fence
< VM_MIN_ADDRESS
)
1762 fence
= VM_MIN_ADDRESS
;
1764 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1766 /* search back for previous return */
1767 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1768 if (start_pc
< fence
)
1770 /* It's not clear to me why we reach this point when
1771 stop_soon_quietly, but with this test, at least we
1772 don't print out warnings for every child forked (eg, on
1773 decstation). 22apr93 rich@cygnus.com. */
1774 if (!stop_soon_quietly
)
1776 static int blurb_printed
= 0;
1778 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1783 /* This actually happens frequently in embedded
1784 development, when you first connect to a board
1785 and your stack pointer and pc are nowhere in
1786 particular. This message needs to give people
1787 in that situation enough information to
1788 determine that it's no big deal. */
1789 printf_filtered ("\n\
1790 GDB is unable to find the start of the function at 0x%s\n\
1791 and thus can't determine the size of that function's stack frame.\n\
1792 This means that GDB may be unable to access that stack frame, or\n\
1793 the frames below it.\n\
1794 This problem is most likely caused by an invalid program counter or\n\
1796 However, if you think GDB should simply search farther back\n\
1797 from 0x%s for code which looks like the beginning of a\n\
1798 function, you can increase the range of the search using the `set\n\
1799 heuristic-fence-post' command.\n",
1800 paddr_nz (pc
), paddr_nz (pc
));
1807 else if (pc_is_mips16 (start_pc
))
1809 unsigned short inst
;
1811 /* On MIPS16, any one of the following is likely to be the
1812 start of a function:
1816 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1817 inst
= mips_fetch_instruction (start_pc
);
1818 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1819 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1820 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1821 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1823 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1824 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1829 else if (mips_about_to_return (start_pc
))
1831 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1838 /* Fetch the immediate value from a MIPS16 instruction.
1839 If the previous instruction was an EXTEND, use it to extend
1840 the upper bits of the immediate value. This is a helper function
1841 for mips16_heuristic_proc_desc. */
1844 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1845 unsigned short inst
, /* current instruction */
1846 int nbits
, /* number of bits in imm field */
1847 int scale
, /* scale factor to be applied to imm */
1848 int is_signed
) /* is the imm field signed? */
1852 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1854 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1855 if (offset
& 0x8000) /* check for negative extend */
1856 offset
= 0 - (0x10000 - (offset
& 0xffff));
1857 return offset
| (inst
& 0x1f);
1861 int max_imm
= 1 << nbits
;
1862 int mask
= max_imm
- 1;
1863 int sign_bit
= max_imm
>> 1;
1865 offset
= inst
& mask
;
1866 if (is_signed
&& (offset
& sign_bit
))
1867 offset
= 0 - (max_imm
- offset
);
1868 return offset
* scale
;
1873 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1874 stream from start_pc to limit_pc. */
1877 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1878 struct frame_info
*next_frame
, CORE_ADDR sp
)
1881 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1882 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1883 unsigned inst
= 0; /* current instruction */
1884 unsigned entry_inst
= 0; /* the entry instruction */
1887 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1888 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1890 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1892 /* Save the previous instruction. If it's an EXTEND, we'll extract
1893 the immediate offset extension from it in mips16_get_imm. */
1896 /* Fetch and decode the instruction. */
1897 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1898 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1899 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1901 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1902 if (offset
< 0) /* negative stack adjustment? */
1903 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1905 /* Exit loop if a positive stack adjustment is found, which
1906 usually means that the stack cleanup code in the function
1907 epilogue is reached. */
1910 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1912 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1913 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1914 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1915 set_reg_offset (reg
, sp
+ offset
);
1917 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1919 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1920 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1921 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1922 set_reg_offset (reg
, sp
+ offset
);
1924 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1926 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1927 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1928 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1930 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1932 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1933 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1934 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1936 else if (inst
== 0x673d) /* move $s1, $sp */
1939 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1941 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1943 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1944 frame_addr
= sp
+ offset
;
1945 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1946 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1948 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1950 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1951 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1952 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1953 set_reg_offset (reg
, frame_addr
+ offset
);
1955 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1957 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1958 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1959 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1960 set_reg_offset (reg
, frame_addr
+ offset
);
1962 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1963 entry_inst
= inst
; /* save for later processing */
1964 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1965 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1968 /* The entry instruction is typically the first instruction in a function,
1969 and it stores registers at offsets relative to the value of the old SP
1970 (before the prologue). But the value of the sp parameter to this
1971 function is the new SP (after the prologue has been executed). So we
1972 can't calculate those offsets until we've seen the entire prologue,
1973 and can calculate what the old SP must have been. */
1974 if (entry_inst
!= 0)
1976 int areg_count
= (entry_inst
>> 8) & 7;
1977 int sreg_count
= (entry_inst
>> 6) & 3;
1979 /* The entry instruction always subtracts 32 from the SP. */
1980 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1982 /* Now we can calculate what the SP must have been at the
1983 start of the function prologue. */
1984 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1986 /* Check if a0-a3 were saved in the caller's argument save area. */
1987 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1989 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1990 set_reg_offset (reg
, sp
+ offset
);
1991 offset
+= MIPS_SAVED_REGSIZE
;
1994 /* Check if the ra register was pushed on the stack. */
1996 if (entry_inst
& 0x20)
1998 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1999 set_reg_offset (RA_REGNUM
, sp
+ offset
);
2000 offset
-= MIPS_SAVED_REGSIZE
;
2003 /* Check if the s0 and s1 registers were pushed on the stack. */
2004 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2006 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2007 set_reg_offset (reg
, sp
+ offset
);
2008 offset
-= MIPS_SAVED_REGSIZE
;
2014 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2015 struct frame_info
*next_frame
, CORE_ADDR sp
)
2018 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2020 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2021 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2022 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2023 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2025 unsigned long inst
, high_word
, low_word
;
2028 /* Fetch the instruction. */
2029 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2031 /* Save some code by pre-extracting some useful fields. */
2032 high_word
= (inst
>> 16) & 0xffff;
2033 low_word
= inst
& 0xffff;
2034 reg
= high_word
& 0x1f;
2036 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2037 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2038 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2040 if (low_word
& 0x8000) /* negative stack adjustment? */
2041 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2043 /* Exit loop if a positive stack adjustment is found, which
2044 usually means that the stack cleanup code in the function
2045 epilogue is reached. */
2048 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2050 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2051 set_reg_offset (reg
, sp
+ low_word
);
2053 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2055 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2056 but the register size used is only 32 bits. Make the address
2057 for the saved register point to the lower 32 bits. */
2058 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2059 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
2061 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2063 /* Old gcc frame, r30 is virtual frame pointer. */
2064 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2065 frame_addr
= sp
+ low_word
;
2066 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2068 unsigned alloca_adjust
;
2069 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2070 frame_addr
= read_next_frame_reg (next_frame
, 30);
2071 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2072 if (alloca_adjust
> 0)
2074 /* FP > SP + frame_size. This may be because
2075 * of an alloca or somethings similar.
2076 * Fix sp to "pre-alloca" value, and try again.
2078 sp
+= alloca_adjust
;
2083 /* move $30,$sp. With different versions of gas this will be either
2084 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2085 Accept any one of these. */
2086 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2088 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2089 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2091 unsigned alloca_adjust
;
2092 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2093 frame_addr
= read_next_frame_reg (next_frame
, 30);
2094 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2095 if (alloca_adjust
> 0)
2097 /* FP > SP + frame_size. This may be because
2098 * of an alloca or somethings similar.
2099 * Fix sp to "pre-alloca" value, and try again.
2101 sp
+= alloca_adjust
;
2106 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2108 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2109 set_reg_offset (reg
, frame_addr
+ low_word
);
2114 static mips_extra_func_info_t
2115 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2116 struct frame_info
*next_frame
, int cur_frame
)
2121 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
2127 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2128 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2129 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2130 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2131 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2133 if (start_pc
+ 200 < limit_pc
)
2134 limit_pc
= start_pc
+ 200;
2135 if (pc_is_mips16 (start_pc
))
2136 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2138 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2139 return &temp_proc_desc
;
2142 struct mips_objfile_private
2148 /* Global used to communicate between non_heuristic_proc_desc and
2149 compare_pdr_entries within qsort (). */
2150 static bfd
*the_bfd
;
2153 compare_pdr_entries (const void *a
, const void *b
)
2155 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2156 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2160 else if (lhs
== rhs
)
2166 static mips_extra_func_info_t
2167 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2169 CORE_ADDR startaddr
;
2170 mips_extra_func_info_t proc_desc
;
2171 struct block
*b
= block_for_pc (pc
);
2173 struct obj_section
*sec
;
2174 struct mips_objfile_private
*priv
;
2176 if (PC_IN_CALL_DUMMY (pc
, 0, 0))
2179 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2181 *addrptr
= startaddr
;
2185 sec
= find_pc_section (pc
);
2188 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2190 /* Search the ".pdr" section generated by GAS. This includes most of
2191 the information normally found in ECOFF PDRs. */
2193 the_bfd
= sec
->objfile
->obfd
;
2195 && (the_bfd
->format
== bfd_object
2196 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2197 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2199 /* Right now GAS only outputs the address as a four-byte sequence.
2200 This means that we should not bother with this method on 64-bit
2201 targets (until that is fixed). */
2203 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2204 sizeof (struct mips_objfile_private
));
2206 sec
->objfile
->obj_private
= priv
;
2208 else if (priv
== NULL
)
2212 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2213 sizeof (struct mips_objfile_private
));
2215 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2218 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2219 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2221 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2222 priv
->contents
, 0, priv
->size
);
2224 /* In general, the .pdr section is sorted. However, in the
2225 presence of multiple code sections (and other corner cases)
2226 it can become unsorted. Sort it so that we can use a faster
2228 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2233 sec
->objfile
->obj_private
= priv
;
2237 if (priv
->size
!= 0)
2243 high
= priv
->size
/ 32;
2249 mid
= (low
+ high
) / 2;
2251 ptr
= priv
->contents
+ mid
* 32;
2252 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2253 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2254 SECT_OFF_TEXT (sec
->objfile
));
2255 if (pdr_pc
== startaddr
)
2257 if (pdr_pc
> startaddr
)
2262 while (low
!= high
);
2266 struct symbol
*sym
= find_pc_function (pc
);
2268 /* Fill in what we need of the proc_desc. */
2269 proc_desc
= (mips_extra_func_info_t
)
2270 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2271 sizeof (struct mips_extra_func_info
));
2272 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2274 /* Only used for dummy frames. */
2275 PROC_HIGH_ADDR (proc_desc
) = 0;
2277 PROC_FRAME_OFFSET (proc_desc
)
2278 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2279 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2281 PROC_FRAME_ADJUST (proc_desc
) = 0;
2282 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2284 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2286 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2288 PROC_FREG_OFFSET (proc_desc
)
2289 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2290 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2292 proc_desc
->pdr
.isym
= (long) sym
;
2302 if (startaddr
> BLOCK_START (b
))
2304 /* This is the "pathological" case referred to in a comment in
2305 print_frame_info. It might be better to move this check into
2310 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
2312 /* If we never found a PDR for this function in symbol reading, then
2313 examine prologues to find the information. */
2316 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2317 if (PROC_FRAME_REG (proc_desc
) == -1)
2327 static mips_extra_func_info_t
2328 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2330 mips_extra_func_info_t proc_desc
;
2331 CORE_ADDR startaddr
;
2333 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2337 /* IF this is the topmost frame AND
2338 * (this proc does not have debugging information OR
2339 * the PC is in the procedure prologue)
2340 * THEN create a "heuristic" proc_desc (by analyzing
2341 * the actual code) to replace the "official" proc_desc.
2343 if (next_frame
== NULL
)
2345 struct symtab_and_line val
;
2346 struct symbol
*proc_symbol
=
2347 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2351 val
= find_pc_line (BLOCK_START
2352 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2354 val
.pc
= val
.end
? val
.end
: pc
;
2356 if (!proc_symbol
|| pc
< val
.pc
)
2358 mips_extra_func_info_t found_heuristic
=
2359 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2360 pc
, next_frame
, cur_frame
);
2361 if (found_heuristic
)
2362 proc_desc
= found_heuristic
;
2368 /* Is linked_proc_desc_table really necessary? It only seems to be used
2369 by procedure call dummys. However, the procedures being called ought
2370 to have their own proc_descs, and even if they don't,
2371 heuristic_proc_desc knows how to create them! */
2373 register struct linked_proc_info
*link
;
2375 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2376 if (PROC_LOW_ADDR (&link
->info
) <= pc
2377 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2381 startaddr
= heuristic_proc_start (pc
);
2384 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2390 get_frame_pointer (struct frame_info
*frame
,
2391 mips_extra_func_info_t proc_desc
)
2393 return ADDR_BITS_REMOVE (read_next_frame_reg (frame
,
2394 PROC_FRAME_REG (proc_desc
)) +
2395 PROC_FRAME_OFFSET (proc_desc
) -
2396 PROC_FRAME_ADJUST (proc_desc
));
2399 static mips_extra_func_info_t cached_proc_desc
;
2402 mips_frame_chain (struct frame_info
*frame
)
2404 mips_extra_func_info_t proc_desc
;
2406 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2408 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2411 /* Check if the PC is inside a call stub. If it is, fetch the
2412 PC of the caller of that stub. */
2413 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2416 /* Look up the procedure descriptor for this PC. */
2417 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2421 cached_proc_desc
= proc_desc
;
2423 /* If no frame pointer and frame size is zero, we must be at end
2424 of stack (or otherwise hosed). If we don't check frame size,
2425 we loop forever if we see a zero size frame. */
2426 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2427 && PROC_FRAME_OFFSET (proc_desc
) == 0
2428 /* The previous frame from a sigtramp frame might be frameless
2429 and have frame size zero. */
2430 && !frame
->signal_handler_caller
2431 /* Check if this is a call dummy frame. */
2432 && frame
->pc
!= CALL_DUMMY_ADDRESS ())
2435 return get_frame_pointer (frame
, proc_desc
);
2439 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2443 /* Use proc_desc calculated in frame_chain */
2444 mips_extra_func_info_t proc_desc
=
2445 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2447 fci
->extra_info
= (struct frame_extra_info
*)
2448 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2450 fci
->saved_regs
= NULL
;
2451 fci
->extra_info
->proc_desc
=
2452 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2455 /* Fixup frame-pointer - only needed for top frame */
2456 /* This may not be quite right, if proc has a real frame register.
2457 Get the value of the frame relative sp, procedure might have been
2458 interrupted by a signal at it's very start. */
2459 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2460 && !PROC_DESC_IS_DUMMY (proc_desc
))
2461 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2463 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2465 if (proc_desc
== &temp_proc_desc
)
2469 /* Do not set the saved registers for a sigtramp frame,
2470 mips_find_saved_registers will do that for us.
2471 We can't use fci->signal_handler_caller, it is not yet set. */
2472 find_pc_partial_function (fci
->pc
, &name
,
2473 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2474 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2476 frame_saved_regs_zalloc (fci
);
2477 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2478 fci
->saved_regs
[PC_REGNUM
]
2479 = fci
->saved_regs
[RA_REGNUM
];
2480 /* Set value of previous frame's stack pointer. Remember that
2481 saved_regs[SP_REGNUM] is special in that it contains the
2482 value of the stack pointer register. The other saved_regs
2483 values are addresses (in the inferior) at which a given
2484 register's value may be found. */
2485 fci
->saved_regs
[SP_REGNUM
] = fci
->frame
;
2489 /* hack: if argument regs are saved, guess these contain args */
2490 /* assume we can't tell how many args for now */
2491 fci
->extra_info
->num_args
= -1;
2492 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2494 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2496 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2503 /* MIPS stack frames are almost impenetrable. When execution stops,
2504 we basically have to look at symbol information for the function
2505 that we stopped in, which tells us *which* register (if any) is
2506 the base of the frame pointer, and what offset from that register
2507 the frame itself is at.
2509 This presents a problem when trying to examine a stack in memory
2510 (that isn't executing at the moment), using the "frame" command. We
2511 don't have a PC, nor do we have any registers except SP.
2513 This routine takes two arguments, SP and PC, and tries to make the
2514 cached frames look as if these two arguments defined a frame on the
2515 cache. This allows the rest of info frame to extract the important
2516 arguments without difficulty. */
2519 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2522 error ("MIPS frame specifications require two arguments: sp and pc");
2524 return create_new_frame (argv
[0], argv
[1]);
2527 /* According to the current ABI, should the type be passed in a
2528 floating-point register (assuming that there is space)? When there
2529 is no FPU, FP are not even considered as possibile candidates for
2530 FP registers and, consequently this returns false - forces FP
2531 arguments into integer registers. */
2534 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2536 return ((typecode
== TYPE_CODE_FLT
2538 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2539 && TYPE_NFIELDS (arg_type
) == 1
2540 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2541 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2544 /* On o32, argument passing in GPRs depends on the alignment of the type being
2545 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2548 mips_type_needs_double_align (struct type
*type
)
2550 enum type_code typecode
= TYPE_CODE (type
);
2552 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2554 else if (typecode
== TYPE_CODE_STRUCT
)
2556 if (TYPE_NFIELDS (type
) < 1)
2558 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2560 else if (typecode
== TYPE_CODE_UNION
)
2564 n
= TYPE_NFIELDS (type
);
2565 for (i
= 0; i
< n
; i
++)
2566 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2573 /* Macros to round N up or down to the next A boundary;
2574 A must be a power of two. */
2576 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2577 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2580 mips_eabi_push_arguments (int nargs
,
2581 struct value
**args
,
2584 CORE_ADDR struct_addr
)
2590 int stack_offset
= 0;
2592 /* First ensure that the stack and structure return address (if any)
2593 are properly aligned. The stack has to be at least 64-bit
2594 aligned even on 32-bit machines, because doubles must be 64-bit
2595 aligned. For n32 and n64, stack frames need to be 128-bit
2596 aligned, so we round to this widest known alignment. */
2598 sp
= ROUND_DOWN (sp
, 16);
2599 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2601 /* Now make space on the stack for the args. We allocate more
2602 than necessary for EABI, because the first few arguments are
2603 passed in registers, but that's OK. */
2604 for (argnum
= 0; argnum
< nargs
; argnum
++)
2605 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2606 MIPS_STACK_ARGSIZE
);
2607 sp
-= ROUND_UP (len
, 16);
2610 fprintf_unfiltered (gdb_stdlog
,
2611 "mips_eabi_push_arguments: sp=0x%s allocated %d\n",
2612 paddr_nz (sp
), ROUND_UP (len
, 16));
2614 /* Initialize the integer and float register pointers. */
2616 float_argreg
= FPA0_REGNUM
;
2618 /* The struct_return pointer occupies the first parameter-passing reg. */
2622 fprintf_unfiltered (gdb_stdlog
,
2623 "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n",
2624 argreg
, paddr_nz (struct_addr
));
2625 write_register (argreg
++, struct_addr
);
2628 /* Now load as many as possible of the first arguments into
2629 registers, and push the rest onto the stack. Loop thru args
2630 from first to last. */
2631 for (argnum
= 0; argnum
< nargs
; argnum
++)
2634 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
2635 struct value
*arg
= args
[argnum
];
2636 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2637 int len
= TYPE_LENGTH (arg_type
);
2638 enum type_code typecode
= TYPE_CODE (arg_type
);
2641 fprintf_unfiltered (gdb_stdlog
,
2642 "mips_eabi_push_arguments: %d len=%d type=%d",
2643 argnum
+ 1, len
, (int) typecode
);
2645 /* The EABI passes structures that do not fit in a register by
2647 if (len
> MIPS_SAVED_REGSIZE
2648 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2650 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2651 typecode
= TYPE_CODE_PTR
;
2652 len
= MIPS_SAVED_REGSIZE
;
2655 fprintf_unfiltered (gdb_stdlog
, " push");
2658 val
= (char *) VALUE_CONTENTS (arg
);
2660 /* 32-bit ABIs always start floating point arguments in an
2661 even-numbered floating point register. Round the FP register
2662 up before the check to see if there are any FP registers
2663 left. Non MIPS_EABI targets also pass the FP in the integer
2664 registers so also round up normal registers. */
2665 if (!FP_REGISTER_DOUBLE
2666 && fp_register_arg_p (typecode
, arg_type
))
2668 if ((float_argreg
& 1))
2672 /* Floating point arguments passed in registers have to be
2673 treated specially. On 32-bit architectures, doubles
2674 are passed in register pairs; the even register gets
2675 the low word, and the odd register gets the high word.
2676 On non-EABI processors, the first two floating point arguments are
2677 also copied to general registers, because MIPS16 functions
2678 don't use float registers for arguments. This duplication of
2679 arguments in general registers can't hurt non-MIPS16 functions
2680 because those registers are normally skipped. */
2681 /* MIPS_EABI squeezes a struct that contains a single floating
2682 point value into an FP register instead of pushing it onto the
2684 if (fp_register_arg_p (typecode
, arg_type
)
2685 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2687 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2689 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2690 unsigned long regval
;
2692 /* Write the low word of the double to the even register(s). */
2693 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2695 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2696 float_argreg
, phex (regval
, 4));
2697 write_register (float_argreg
++, regval
);
2699 /* Write the high word of the double to the odd register(s). */
2700 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2702 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2703 float_argreg
, phex (regval
, 4));
2704 write_register (float_argreg
++, regval
);
2708 /* This is a floating point value that fits entirely
2709 in a single register. */
2710 /* On 32 bit ABI's the float_argreg is further adjusted
2711 above to ensure that it is even register aligned. */
2712 LONGEST regval
= extract_unsigned_integer (val
, len
);
2714 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2715 float_argreg
, phex (regval
, len
));
2716 write_register (float_argreg
++, regval
);
2721 /* Copy the argument to general registers or the stack in
2722 register-sized pieces. Large arguments are split between
2723 registers and stack. */
2724 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2725 are treated specially: Irix cc passes them in registers
2726 where gcc sometimes puts them on the stack. For maximum
2727 compatibility, we will put them in both places. */
2728 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2729 (len
% MIPS_SAVED_REGSIZE
!= 0));
2731 /* Note: Floating-point values that didn't fit into an FP
2732 register are only written to memory. */
2735 /* Remember if the argument was written to the stack. */
2736 int stack_used_p
= 0;
2738 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2741 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2744 /* Write this portion of the argument to the stack. */
2745 if (argreg
> MIPS_LAST_ARG_REGNUM
2747 || fp_register_arg_p (typecode
, arg_type
))
2749 /* Should shorter than int integer values be
2750 promoted to int before being stored? */
2751 int longword_offset
= 0;
2754 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2756 if (MIPS_STACK_ARGSIZE
== 8 &&
2757 (typecode
== TYPE_CODE_INT
||
2758 typecode
== TYPE_CODE_PTR
||
2759 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2760 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2761 else if ((typecode
== TYPE_CODE_STRUCT
||
2762 typecode
== TYPE_CODE_UNION
) &&
2763 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2764 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2769 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2770 paddr_nz (stack_offset
));
2771 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2772 paddr_nz (longword_offset
));
2775 addr
= sp
+ stack_offset
+ longword_offset
;
2780 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2782 for (i
= 0; i
< partial_len
; i
++)
2784 fprintf_unfiltered (gdb_stdlog
, "%02x",
2788 write_memory (addr
, val
, partial_len
);
2791 /* Note!!! This is NOT an else clause. Odd sized
2792 structs may go thru BOTH paths. Floating point
2793 arguments will not. */
2794 /* Write this portion of the argument to a general
2795 purpose register. */
2796 if (argreg
<= MIPS_LAST_ARG_REGNUM
2797 && !fp_register_arg_p (typecode
, arg_type
))
2799 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2802 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2804 phex (regval
, MIPS_SAVED_REGSIZE
));
2805 write_register (argreg
, regval
);
2812 /* Compute the the offset into the stack at which we
2813 will copy the next parameter.
2815 In the new EABI (and the NABI32), the stack_offset
2816 only needs to be adjusted when it has been used. */
2819 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2823 fprintf_unfiltered (gdb_stdlog
, "\n");
2826 /* Return adjusted stack pointer. */
2830 /* N32/N64 version of push_arguments. */
2833 mips_n32n64_push_arguments (int nargs
,
2834 struct value
**args
,
2837 CORE_ADDR struct_addr
)
2843 int stack_offset
= 0;
2845 /* First ensure that the stack and structure return address (if any)
2846 are properly aligned. The stack has to be at least 64-bit
2847 aligned even on 32-bit machines, because doubles must be 64-bit
2848 aligned. For n32 and n64, stack frames need to be 128-bit
2849 aligned, so we round to this widest known alignment. */
2851 sp
= ROUND_DOWN (sp
, 16);
2852 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2854 /* Now make space on the stack for the args. */
2855 for (argnum
= 0; argnum
< nargs
; argnum
++)
2856 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2857 MIPS_STACK_ARGSIZE
);
2858 sp
-= ROUND_UP (len
, 16);
2861 fprintf_unfiltered (gdb_stdlog
,
2862 "mips_n32n64_push_arguments: sp=0x%s allocated %d\n",
2863 paddr_nz (sp
), ROUND_UP (len
, 16));
2865 /* Initialize the integer and float register pointers. */
2867 float_argreg
= FPA0_REGNUM
;
2869 /* The struct_return pointer occupies the first parameter-passing reg. */
2873 fprintf_unfiltered (gdb_stdlog
,
2874 "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n",
2875 argreg
, paddr_nz (struct_addr
));
2876 write_register (argreg
++, struct_addr
);
2879 /* Now load as many as possible of the first arguments into
2880 registers, and push the rest onto the stack. Loop thru args
2881 from first to last. */
2882 for (argnum
= 0; argnum
< nargs
; argnum
++)
2885 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
2886 struct value
*arg
= args
[argnum
];
2887 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2888 int len
= TYPE_LENGTH (arg_type
);
2889 enum type_code typecode
= TYPE_CODE (arg_type
);
2892 fprintf_unfiltered (gdb_stdlog
,
2893 "mips_n32n64_push_arguments: %d len=%d type=%d",
2894 argnum
+ 1, len
, (int) typecode
);
2896 val
= (char *) VALUE_CONTENTS (arg
);
2898 if (fp_register_arg_p (typecode
, arg_type
)
2899 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2901 /* This is a floating point value that fits entirely
2902 in a single register. */
2903 /* On 32 bit ABI's the float_argreg is further adjusted
2904 above to ensure that it is even register aligned. */
2905 LONGEST regval
= extract_unsigned_integer (val
, len
);
2907 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2908 float_argreg
, phex (regval
, len
));
2909 write_register (float_argreg
++, regval
);
2912 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2913 argreg
, phex (regval
, len
));
2914 write_register (argreg
, regval
);
2919 /* Copy the argument to general registers or the stack in
2920 register-sized pieces. Large arguments are split between
2921 registers and stack. */
2922 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2923 are treated specially: Irix cc passes them in registers
2924 where gcc sometimes puts them on the stack. For maximum
2925 compatibility, we will put them in both places. */
2926 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2927 (len
% MIPS_SAVED_REGSIZE
!= 0));
2928 /* Note: Floating-point values that didn't fit into an FP
2929 register are only written to memory. */
2932 /* Rememer if the argument was written to the stack. */
2933 int stack_used_p
= 0;
2934 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
2935 len
: MIPS_SAVED_REGSIZE
;
2938 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2941 /* Write this portion of the argument to the stack. */
2942 if (argreg
> MIPS_LAST_ARG_REGNUM
2944 || fp_register_arg_p (typecode
, arg_type
))
2946 /* Should shorter than int integer values be
2947 promoted to int before being stored? */
2948 int longword_offset
= 0;
2951 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2953 if (MIPS_STACK_ARGSIZE
== 8 &&
2954 (typecode
== TYPE_CODE_INT
||
2955 typecode
== TYPE_CODE_PTR
||
2956 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2957 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2958 else if ((typecode
== TYPE_CODE_STRUCT
||
2959 typecode
== TYPE_CODE_UNION
) &&
2960 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2961 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2966 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2967 paddr_nz (stack_offset
));
2968 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2969 paddr_nz (longword_offset
));
2972 addr
= sp
+ stack_offset
+ longword_offset
;
2977 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2979 for (i
= 0; i
< partial_len
; i
++)
2981 fprintf_unfiltered (gdb_stdlog
, "%02x",
2985 write_memory (addr
, val
, partial_len
);
2988 /* Note!!! This is NOT an else clause. Odd sized
2989 structs may go thru BOTH paths. Floating point
2990 arguments will not. */
2991 /* Write this portion of the argument to a general
2992 purpose register. */
2993 if (argreg
<= MIPS_LAST_ARG_REGNUM
2994 && !fp_register_arg_p (typecode
, arg_type
))
2996 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2998 /* A non-floating-point argument being passed in a
2999 general register. If a struct or union, and if
3000 the remaining length is smaller than the register
3001 size, we have to adjust the register value on
3004 It does not seem to be necessary to do the
3005 same for integral types.
3007 cagney/2001-07-23: gdb/179: Also, GCC, when
3008 outputting LE O32 with sizeof (struct) <
3009 MIPS_SAVED_REGSIZE, generates a left shift as
3010 part of storing the argument in a register a
3011 register (the left shift isn't generated when
3012 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3013 is quite possible that this is GCC contradicting
3014 the LE/O32 ABI, GDB has not been adjusted to
3015 accommodate this. Either someone needs to
3016 demonstrate that the LE/O32 ABI specifies such a
3017 left shift OR this new ABI gets identified as
3018 such and GDB gets tweaked accordingly. */
3020 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3021 && partial_len
< MIPS_SAVED_REGSIZE
3022 && (typecode
== TYPE_CODE_STRUCT
||
3023 typecode
== TYPE_CODE_UNION
))
3024 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3028 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3030 phex (regval
, MIPS_SAVED_REGSIZE
));
3031 write_register (argreg
, regval
);
3038 /* Compute the the offset into the stack at which we
3039 will copy the next parameter.
3041 In N32 (N64?), the stack_offset only needs to be
3042 adjusted when it has been used. */
3045 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3049 fprintf_unfiltered (gdb_stdlog
, "\n");
3052 /* Return adjusted stack pointer. */
3056 /* O32 version of push_arguments. */
3059 mips_o32_push_arguments (int nargs
,
3060 struct value
**args
,
3063 CORE_ADDR struct_addr
)
3069 int stack_offset
= 0;
3071 /* First ensure that the stack and structure return address (if any)
3072 are properly aligned. The stack has to be at least 64-bit
3073 aligned even on 32-bit machines, because doubles must be 64-bit
3074 aligned. For n32 and n64, stack frames need to be 128-bit
3075 aligned, so we round to this widest known alignment. */
3077 sp
= ROUND_DOWN (sp
, 16);
3078 struct_addr
= ROUND_DOWN (struct_addr
, 16);
3080 /* Now make space on the stack for the args. */
3081 for (argnum
= 0; argnum
< nargs
; argnum
++)
3082 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3083 MIPS_STACK_ARGSIZE
);
3084 sp
-= ROUND_UP (len
, 16);
3087 fprintf_unfiltered (gdb_stdlog
,
3088 "mips_o32_push_arguments: sp=0x%s allocated %d\n",
3089 paddr_nz (sp
), ROUND_UP (len
, 16));
3091 /* Initialize the integer and float register pointers. */
3093 float_argreg
= FPA0_REGNUM
;
3095 /* The struct_return pointer occupies the first parameter-passing reg. */
3099 fprintf_unfiltered (gdb_stdlog
,
3100 "mips_o32_push_arguments: struct_return reg=%d 0x%s\n",
3101 argreg
, paddr_nz (struct_addr
));
3102 write_register (argreg
++, struct_addr
);
3103 stack_offset
+= MIPS_STACK_ARGSIZE
;
3106 /* Now load as many as possible of the first arguments into
3107 registers, and push the rest onto the stack. Loop thru args
3108 from first to last. */
3109 for (argnum
= 0; argnum
< nargs
; argnum
++)
3112 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
3113 struct value
*arg
= args
[argnum
];
3114 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3115 int len
= TYPE_LENGTH (arg_type
);
3116 enum type_code typecode
= TYPE_CODE (arg_type
);
3119 fprintf_unfiltered (gdb_stdlog
,
3120 "mips_o32_push_arguments: %d len=%d type=%d",
3121 argnum
+ 1, len
, (int) typecode
);
3123 val
= (char *) VALUE_CONTENTS (arg
);
3125 /* 32-bit ABIs always start floating point arguments in an
3126 even-numbered floating point register. Round the FP register
3127 up before the check to see if there are any FP registers
3128 left. O32/O64 targets also pass the FP in the integer
3129 registers so also round up normal registers. */
3130 if (!FP_REGISTER_DOUBLE
3131 && fp_register_arg_p (typecode
, arg_type
))
3133 if ((float_argreg
& 1))
3137 /* Floating point arguments passed in registers have to be
3138 treated specially. On 32-bit architectures, doubles
3139 are passed in register pairs; the even register gets
3140 the low word, and the odd register gets the high word.
3141 On O32/O64, the first two floating point arguments are
3142 also copied to general registers, because MIPS16 functions
3143 don't use float registers for arguments. This duplication of
3144 arguments in general registers can't hurt non-MIPS16 functions
3145 because those registers are normally skipped. */
3147 if (fp_register_arg_p (typecode
, arg_type
)
3148 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3150 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3152 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3153 unsigned long regval
;
3155 /* Write the low word of the double to the even register(s). */
3156 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3158 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3159 float_argreg
, phex (regval
, 4));
3160 write_register (float_argreg
++, regval
);
3162 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3163 argreg
, phex (regval
, 4));
3164 write_register (argreg
++, regval
);
3166 /* Write the high word of the double to the odd register(s). */
3167 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3169 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3170 float_argreg
, phex (regval
, 4));
3171 write_register (float_argreg
++, regval
);
3174 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3175 argreg
, phex (regval
, 4));
3176 write_register (argreg
++, regval
);
3180 /* This is a floating point value that fits entirely
3181 in a single register. */
3182 /* On 32 bit ABI's the float_argreg is further adjusted
3183 above to ensure that it is even register aligned. */
3184 LONGEST regval
= extract_unsigned_integer (val
, len
);
3186 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3187 float_argreg
, phex (regval
, len
));
3188 write_register (float_argreg
++, regval
);
3189 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3190 registers for each argument. The below is (my
3191 guess) to ensure that the corresponding integer
3192 register has reserved the same space. */
3194 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3195 argreg
, phex (regval
, len
));
3196 write_register (argreg
, regval
);
3197 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3199 /* Reserve space for the FP register. */
3200 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
3204 /* Copy the argument to general registers or the stack in
3205 register-sized pieces. Large arguments are split between
3206 registers and stack. */
3207 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3208 are treated specially: Irix cc passes them in registers
3209 where gcc sometimes puts them on the stack. For maximum
3210 compatibility, we will put them in both places. */
3211 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3212 (len
% MIPS_SAVED_REGSIZE
!= 0));
3213 /* Structures should be aligned to eight bytes (even arg registers)
3214 on MIPS_ABI_O32, if their first member has double precision. */
3215 if (MIPS_SAVED_REGSIZE
< 8
3216 && mips_type_needs_double_align (arg_type
))
3221 /* Note: Floating-point values that didn't fit into an FP
3222 register are only written to memory. */
3225 /* Remember if the argument was written to the stack. */
3226 int stack_used_p
= 0;
3228 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3231 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3234 /* Write this portion of the argument to the stack. */
3235 if (argreg
> MIPS_LAST_ARG_REGNUM
3237 || fp_register_arg_p (typecode
, arg_type
))
3239 /* Should shorter than int integer values be
3240 promoted to int before being stored? */
3241 int longword_offset
= 0;
3244 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3246 if (MIPS_STACK_ARGSIZE
== 8 &&
3247 (typecode
== TYPE_CODE_INT
||
3248 typecode
== TYPE_CODE_PTR
||
3249 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3250 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3255 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3256 paddr_nz (stack_offset
));
3257 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3258 paddr_nz (longword_offset
));
3261 addr
= sp
+ stack_offset
+ longword_offset
;
3266 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3268 for (i
= 0; i
< partial_len
; i
++)
3270 fprintf_unfiltered (gdb_stdlog
, "%02x",
3274 write_memory (addr
, val
, partial_len
);
3277 /* Note!!! This is NOT an else clause. Odd sized
3278 structs may go thru BOTH paths. Floating point
3279 arguments will not. */
3280 /* Write this portion of the argument to a general
3281 purpose register. */
3282 if (argreg
<= MIPS_LAST_ARG_REGNUM
3283 && !fp_register_arg_p (typecode
, arg_type
))
3285 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3286 /* Value may need to be sign extended, because
3287 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3289 /* A non-floating-point argument being passed in a
3290 general register. If a struct or union, and if
3291 the remaining length is smaller than the register
3292 size, we have to adjust the register value on
3295 It does not seem to be necessary to do the
3296 same for integral types.
3298 Also don't do this adjustment on O64 binaries.
3300 cagney/2001-07-23: gdb/179: Also, GCC, when
3301 outputting LE O32 with sizeof (struct) <
3302 MIPS_SAVED_REGSIZE, generates a left shift as
3303 part of storing the argument in a register a
3304 register (the left shift isn't generated when
3305 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3306 is quite possible that this is GCC contradicting
3307 the LE/O32 ABI, GDB has not been adjusted to
3308 accommodate this. Either someone needs to
3309 demonstrate that the LE/O32 ABI specifies such a
3310 left shift OR this new ABI gets identified as
3311 such and GDB gets tweaked accordingly. */
3313 if (MIPS_SAVED_REGSIZE
< 8
3314 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3315 && partial_len
< MIPS_SAVED_REGSIZE
3316 && (typecode
== TYPE_CODE_STRUCT
||
3317 typecode
== TYPE_CODE_UNION
))
3318 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3322 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3324 phex (regval
, MIPS_SAVED_REGSIZE
));
3325 write_register (argreg
, regval
);
3328 /* Prevent subsequent floating point arguments from
3329 being passed in floating point registers. */
3330 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3336 /* Compute the the offset into the stack at which we
3337 will copy the next parameter.
3339 In older ABIs, the caller reserved space for
3340 registers that contained arguments. This was loosely
3341 refered to as their "home". Consequently, space is
3342 always allocated. */
3344 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3348 fprintf_unfiltered (gdb_stdlog
, "\n");
3351 /* Return adjusted stack pointer. */
3355 /* O64 version of push_arguments. */
3358 mips_o64_push_arguments (int nargs
,
3359 struct value
**args
,
3362 CORE_ADDR struct_addr
)
3368 int stack_offset
= 0;
3370 /* First ensure that the stack and structure return address (if any)
3371 are properly aligned. The stack has to be at least 64-bit
3372 aligned even on 32-bit machines, because doubles must be 64-bit
3373 aligned. For n32 and n64, stack frames need to be 128-bit
3374 aligned, so we round to this widest known alignment. */
3376 sp
= ROUND_DOWN (sp
, 16);
3377 struct_addr
= ROUND_DOWN (struct_addr
, 16);
3379 /* Now make space on the stack for the args. */
3380 for (argnum
= 0; argnum
< nargs
; argnum
++)
3381 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3382 MIPS_STACK_ARGSIZE
);
3383 sp
-= ROUND_UP (len
, 16);
3386 fprintf_unfiltered (gdb_stdlog
,
3387 "mips_o64_push_arguments: sp=0x%s allocated %d\n",
3388 paddr_nz (sp
), ROUND_UP (len
, 16));
3390 /* Initialize the integer and float register pointers. */
3392 float_argreg
= FPA0_REGNUM
;
3394 /* The struct_return pointer occupies the first parameter-passing reg. */
3398 fprintf_unfiltered (gdb_stdlog
,
3399 "mips_o64_push_arguments: struct_return reg=%d 0x%s\n",
3400 argreg
, paddr_nz (struct_addr
));
3401 write_register (argreg
++, struct_addr
);
3402 stack_offset
+= MIPS_STACK_ARGSIZE
;
3405 /* Now load as many as possible of the first arguments into
3406 registers, and push the rest onto the stack. Loop thru args
3407 from first to last. */
3408 for (argnum
= 0; argnum
< nargs
; argnum
++)
3411 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
3412 struct value
*arg
= args
[argnum
];
3413 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3414 int len
= TYPE_LENGTH (arg_type
);
3415 enum type_code typecode
= TYPE_CODE (arg_type
);
3418 fprintf_unfiltered (gdb_stdlog
,
3419 "mips_o64_push_arguments: %d len=%d type=%d",
3420 argnum
+ 1, len
, (int) typecode
);
3422 val
= (char *) VALUE_CONTENTS (arg
);
3424 /* 32-bit ABIs always start floating point arguments in an
3425 even-numbered floating point register. Round the FP register
3426 up before the check to see if there are any FP registers
3427 left. O32/O64 targets also pass the FP in the integer
3428 registers so also round up normal registers. */
3429 if (!FP_REGISTER_DOUBLE
3430 && fp_register_arg_p (typecode
, arg_type
))
3432 if ((float_argreg
& 1))
3436 /* Floating point arguments passed in registers have to be
3437 treated specially. On 32-bit architectures, doubles
3438 are passed in register pairs; the even register gets
3439 the low word, and the odd register gets the high word.
3440 On O32/O64, the first two floating point arguments are
3441 also copied to general registers, because MIPS16 functions
3442 don't use float registers for arguments. This duplication of
3443 arguments in general registers can't hurt non-MIPS16 functions
3444 because those registers are normally skipped. */
3446 if (fp_register_arg_p (typecode
, arg_type
)
3447 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3449 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3451 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3452 unsigned long regval
;
3454 /* Write the low word of the double to the even register(s). */
3455 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3457 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3458 float_argreg
, phex (regval
, 4));
3459 write_register (float_argreg
++, regval
);
3461 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3462 argreg
, phex (regval
, 4));
3463 write_register (argreg
++, regval
);
3465 /* Write the high word of the double to the odd register(s). */
3466 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3468 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3469 float_argreg
, phex (regval
, 4));
3470 write_register (float_argreg
++, regval
);
3473 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3474 argreg
, phex (regval
, 4));
3475 write_register (argreg
++, regval
);
3479 /* This is a floating point value that fits entirely
3480 in a single register. */
3481 /* On 32 bit ABI's the float_argreg is further adjusted
3482 above to ensure that it is even register aligned. */
3483 LONGEST regval
= extract_unsigned_integer (val
, len
);
3485 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3486 float_argreg
, phex (regval
, len
));
3487 write_register (float_argreg
++, regval
);
3488 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3489 registers for each argument. The below is (my
3490 guess) to ensure that the corresponding integer
3491 register has reserved the same space. */
3493 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3494 argreg
, phex (regval
, len
));
3495 write_register (argreg
, regval
);
3496 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3498 /* Reserve space for the FP register. */
3499 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
3503 /* Copy the argument to general registers or the stack in
3504 register-sized pieces. Large arguments are split between
3505 registers and stack. */
3506 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3507 are treated specially: Irix cc passes them in registers
3508 where gcc sometimes puts them on the stack. For maximum
3509 compatibility, we will put them in both places. */
3510 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3511 (len
% MIPS_SAVED_REGSIZE
!= 0));
3512 /* Structures should be aligned to eight bytes (even arg registers)
3513 on MIPS_ABI_O32, if their first member has double precision. */
3514 if (MIPS_SAVED_REGSIZE
< 8
3515 && mips_type_needs_double_align (arg_type
))
3520 /* Note: Floating-point values that didn't fit into an FP
3521 register are only written to memory. */
3524 /* Remember if the argument was written to the stack. */
3525 int stack_used_p
= 0;
3527 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3530 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3533 /* Write this portion of the argument to the stack. */
3534 if (argreg
> MIPS_LAST_ARG_REGNUM
3536 || fp_register_arg_p (typecode
, arg_type
))
3538 /* Should shorter than int integer values be
3539 promoted to int before being stored? */
3540 int longword_offset
= 0;
3543 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3545 if (MIPS_STACK_ARGSIZE
== 8 &&
3546 (typecode
== TYPE_CODE_INT
||
3547 typecode
== TYPE_CODE_PTR
||
3548 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3549 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3554 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3555 paddr_nz (stack_offset
));
3556 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3557 paddr_nz (longword_offset
));
3560 addr
= sp
+ stack_offset
+ longword_offset
;
3565 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3567 for (i
= 0; i
< partial_len
; i
++)
3569 fprintf_unfiltered (gdb_stdlog
, "%02x",
3573 write_memory (addr
, val
, partial_len
);
3576 /* Note!!! This is NOT an else clause. Odd sized
3577 structs may go thru BOTH paths. Floating point
3578 arguments will not. */
3579 /* Write this portion of the argument to a general
3580 purpose register. */
3581 if (argreg
<= MIPS_LAST_ARG_REGNUM
3582 && !fp_register_arg_p (typecode
, arg_type
))
3584 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3585 /* Value may need to be sign extended, because
3586 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3588 /* A non-floating-point argument being passed in a
3589 general register. If a struct or union, and if
3590 the remaining length is smaller than the register
3591 size, we have to adjust the register value on
3594 It does not seem to be necessary to do the
3595 same for integral types.
3597 Also don't do this adjustment on O64 binaries.
3599 cagney/2001-07-23: gdb/179: Also, GCC, when
3600 outputting LE O32 with sizeof (struct) <
3601 MIPS_SAVED_REGSIZE, generates a left shift as
3602 part of storing the argument in a register a
3603 register (the left shift isn't generated when
3604 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3605 is quite possible that this is GCC contradicting
3606 the LE/O32 ABI, GDB has not been adjusted to
3607 accommodate this. Either someone needs to
3608 demonstrate that the LE/O32 ABI specifies such a
3609 left shift OR this new ABI gets identified as
3610 such and GDB gets tweaked accordingly. */
3612 if (MIPS_SAVED_REGSIZE
< 8
3613 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3614 && partial_len
< MIPS_SAVED_REGSIZE
3615 && (typecode
== TYPE_CODE_STRUCT
||
3616 typecode
== TYPE_CODE_UNION
))
3617 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3621 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3623 phex (regval
, MIPS_SAVED_REGSIZE
));
3624 write_register (argreg
, regval
);
3627 /* Prevent subsequent floating point arguments from
3628 being passed in floating point registers. */
3629 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3635 /* Compute the the offset into the stack at which we
3636 will copy the next parameter.
3638 In older ABIs, the caller reserved space for
3639 registers that contained arguments. This was loosely
3640 refered to as their "home". Consequently, space is
3641 always allocated. */
3643 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3647 fprintf_unfiltered (gdb_stdlog
, "\n");
3650 /* Return adjusted stack pointer. */
3655 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
3657 /* Set the return address register to point to the entry
3658 point of the program, where a breakpoint lies in wait. */
3659 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
3664 mips_push_register (CORE_ADDR
* sp
, int regno
)
3666 char *buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
3669 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
3671 regsize
= MIPS_SAVED_REGSIZE
;
3672 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3673 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
3678 regsize
= REGISTER_RAW_SIZE (regno
);
3682 read_register_gen (regno
, buffer
);
3683 write_memory (*sp
, buffer
+ offset
, regsize
);
3686 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
3687 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
3690 mips_push_dummy_frame (void)
3693 struct linked_proc_info
*link
= (struct linked_proc_info
*)
3694 xmalloc (sizeof (struct linked_proc_info
));
3695 mips_extra_func_info_t proc_desc
= &link
->info
;
3696 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
3697 CORE_ADDR old_sp
= sp
;
3698 link
->next
= linked_proc_desc_table
;
3699 linked_proc_desc_table
= link
;
3701 /* FIXME! are these correct ? */
3702 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
3703 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
3704 #define FLOAT_REG_SAVE_MASK MASK(0,19)
3705 #define FLOAT_SINGLE_REG_SAVE_MASK \
3706 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
3708 * The registers we must save are all those not preserved across
3709 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
3710 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
3711 * and FP Control/Status registers.
3714 * Dummy frame layout:
3717 * Saved MMHI, MMLO, FPC_CSR
3722 * Saved D18 (i.e. F19, F18)
3724 * Saved D0 (i.e. F1, F0)
3725 * Argument build area and stack arguments written via mips_push_arguments
3729 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
3730 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
3731 PROC_FRAME_OFFSET (proc_desc
) = 0;
3732 PROC_FRAME_ADJUST (proc_desc
) = 0;
3733 mips_push_register (&sp
, PC_REGNUM
);
3734 mips_push_register (&sp
, HI_REGNUM
);
3735 mips_push_register (&sp
, LO_REGNUM
);
3736 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
3738 /* Save general CPU registers */
3739 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
3740 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
3741 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
3742 for (ireg
= 32; --ireg
>= 0;)
3743 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
3744 mips_push_register (&sp
, ireg
);
3746 /* Save floating point registers starting with high order word */
3747 PROC_FREG_MASK (proc_desc
) =
3748 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
3749 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
3750 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
3752 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
3753 for (ireg
= 32; --ireg
>= 0;)
3754 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
3755 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
3757 /* Update the frame pointer for the call dummy and the stack pointer.
3758 Set the procedure's starting and ending addresses to point to the
3759 call dummy address at the entry point. */
3760 write_register (PUSH_FP_REGNUM
, old_sp
);
3761 write_register (SP_REGNUM
, sp
);
3762 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
3763 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
3764 SET_PROC_DESC_IS_DUMMY (proc_desc
);
3765 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
3769 mips_pop_frame (void)
3771 register int regnum
;
3772 struct frame_info
*frame
= get_current_frame ();
3773 CORE_ADDR new_sp
= FRAME_FP (frame
);
3775 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
3777 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
3778 if (frame
->saved_regs
== NULL
)
3779 FRAME_INIT_SAVED_REGS (frame
);
3780 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3782 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3783 && frame
->saved_regs
[regnum
])
3784 write_register (regnum
,
3785 read_memory_integer (frame
->saved_regs
[regnum
],
3786 MIPS_SAVED_REGSIZE
));
3789 write_register (SP_REGNUM
, new_sp
);
3790 flush_cached_frames ();
3792 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3794 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3796 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3798 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3800 if (&pi_ptr
->info
== proc_desc
)
3805 error ("Can't locate dummy extra frame info\n");
3807 if (prev_ptr
!= NULL
)
3808 prev_ptr
->next
= pi_ptr
->next
;
3810 linked_proc_desc_table
= pi_ptr
->next
;
3814 write_register (HI_REGNUM
,
3815 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3816 MIPS_SAVED_REGSIZE
));
3817 write_register (LO_REGNUM
,
3818 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3819 MIPS_SAVED_REGSIZE
));
3820 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3821 write_register (FCRCS_REGNUM
,
3822 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3823 MIPS_SAVED_REGSIZE
));
3828 mips_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
3829 struct value
**args
, struct type
*type
, int gcc_p
)
3831 write_register(T9_REGNUM
, fun
);
3834 /* Floating point register management.
3836 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3837 64bit operations, these early MIPS cpus treat fp register pairs
3838 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3839 registers and offer a compatibility mode that emulates the MIPS2 fp
3840 model. When operating in MIPS2 fp compat mode, later cpu's split
3841 double precision floats into two 32-bit chunks and store them in
3842 consecutive fp regs. To display 64-bit floats stored in this
3843 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3844 Throw in user-configurable endianness and you have a real mess.
3846 The way this works is:
3847 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3848 double-precision value will be split across two logical registers.
3849 The lower-numbered logical register will hold the low-order bits,
3850 regardless of the processor's endianness.
3851 - If we are on a 64-bit processor, and we are looking for a
3852 single-precision value, it will be in the low ordered bits
3853 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3854 save slot in memory.
3855 - If we are in 64-bit mode, everything is straightforward.
3857 Note that this code only deals with "live" registers at the top of the
3858 stack. We will attempt to deal with saved registers later, when
3859 the raw/cooked register interface is in place. (We need a general
3860 interface that can deal with dynamic saved register sizes -- fp
3861 regs could be 32 bits wide in one frame and 64 on the frame above
3864 static struct type
*
3865 mips_float_register_type (void)
3867 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3868 return builtin_type_ieee_single_big
;
3870 return builtin_type_ieee_single_little
;
3873 static struct type
*
3874 mips_double_register_type (void)
3876 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3877 return builtin_type_ieee_double_big
;
3879 return builtin_type_ieee_double_little
;
3882 /* Copy a 32-bit single-precision value from the current frame
3883 into rare_buffer. */
3886 mips_read_fp_register_single (int regno
, char *rare_buffer
)
3888 int raw_size
= REGISTER_RAW_SIZE (regno
);
3889 char *raw_buffer
= alloca (raw_size
);
3891 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
3892 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3895 /* We have a 64-bit value for this register. Find the low-order
3899 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3904 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3908 memcpy (rare_buffer
, raw_buffer
, 4);
3912 /* Copy a 64-bit double-precision value from the current frame into
3913 rare_buffer. This may include getting half of it from the next
3917 mips_read_fp_register_double (int regno
, char *rare_buffer
)
3919 int raw_size
= REGISTER_RAW_SIZE (regno
);
3921 if (raw_size
== 8 && !mips2_fp_compat ())
3923 /* We have a 64-bit value for this register, and we should use
3925 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
3926 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3930 if ((regno
- FP0_REGNUM
) & 1)
3931 internal_error (__FILE__
, __LINE__
,
3932 "mips_read_fp_register_double: bad access to "
3933 "odd-numbered FP register");
3935 /* mips_read_fp_register_single will find the correct 32 bits from
3937 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3939 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
3940 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
3944 mips_read_fp_register_single (regno
, rare_buffer
);
3945 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
3951 mips_print_register (int regnum
, int all
)
3953 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
3955 /* Get the data in raw format. */
3956 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3958 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
3962 /* If we have a actual 32-bit floating point register (or we are in
3963 32-bit compatibility mode), and the register is even-numbered,
3964 also print it as a double (spanning two registers). */
3965 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
3966 && (REGISTER_RAW_SIZE (regnum
) == 4
3967 || mips2_fp_compat ())
3968 && !((regnum
- FP0_REGNUM
) & 1))
3970 char *dbuffer
= alloca (2 * MAX_REGISTER_RAW_SIZE
);
3972 mips_read_fp_register_double (regnum
, dbuffer
);
3974 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
3975 val_print (mips_double_register_type (), dbuffer
, 0, 0,
3976 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3977 printf_filtered ("); ");
3979 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3981 /* The problem with printing numeric register names (r26, etc.) is that
3982 the user can't use them on input. Probably the best solution is to
3983 fix it so that either the numeric or the funky (a2, etc.) names
3984 are accepted on input. */
3985 if (regnum
< MIPS_NUMREGS
)
3986 printf_filtered ("(r%d): ", regnum
);
3988 printf_filtered (": ");
3990 /* If virtual format is floating, print it that way. */
3991 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3992 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
3994 /* We have a meaningful 64-bit value in this register. Show
3995 it as a 32-bit float and a 64-bit double. */
3996 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
3998 printf_filtered (" (float) ");
3999 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
4000 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
4001 printf_filtered (", (double) ");
4002 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
4003 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
4006 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4007 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
4008 /* Else print as integer in hex. */
4013 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4014 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
4018 print_scalar_formatted (raw_buffer
+ offset
,
4019 REGISTER_VIRTUAL_TYPE (regnum
),
4020 'x', 0, gdb_stdout
);
4024 /* Replacement for generic do_registers_info.
4025 Print regs in pretty columns. */
4028 do_fp_register_row (int regnum
)
4029 { /* do values for FP (float) regs */
4031 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4032 int inv1
, inv2
, inv3
;
4034 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
4036 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
4038 /* 4-byte registers: we can fit two registers per row. */
4039 /* Also print every pair of 4-byte regs as an 8-byte double. */
4040 mips_read_fp_register_single (regnum
, raw_buffer
);
4041 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4043 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
4044 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
4046 mips_read_fp_register_double (regnum
, raw_buffer
);
4047 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
4049 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
4051 printf_filtered (": <invalid float>");
4053 printf_filtered ("%-17.9g", flt1
);
4055 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
4057 printf_filtered (": <invalid float>");
4059 printf_filtered ("%-17.9g", flt2
);
4061 printf_filtered (" dbl: ");
4063 printf_filtered ("<invalid double>");
4065 printf_filtered ("%-24.17g", doub
);
4066 printf_filtered ("\n");
4068 /* may want to do hex display here (future enhancement) */
4073 /* Eight byte registers: print each one as float AND as double. */
4074 mips_read_fp_register_single (regnum
, raw_buffer
);
4075 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
4077 mips_read_fp_register_double (regnum
, raw_buffer
);
4078 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
4080 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
4082 printf_filtered ("<invalid float>");
4084 printf_filtered ("flt: %-17.9g", flt1
);
4086 printf_filtered (" dbl: ");
4088 printf_filtered ("<invalid double>");
4090 printf_filtered ("%-24.17g", doub
);
4092 printf_filtered ("\n");
4093 /* may want to do hex display here (future enhancement) */
4099 /* Print a row's worth of GP (int) registers, with name labels above */
4102 do_gp_register_row (int regnum
)
4104 /* do values for GP (int) regs */
4105 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4106 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
4108 int start_regnum
= regnum
;
4109 int numregs
= NUM_REGS
;
4112 /* For GP registers, we print a separate row of names above the vals */
4113 printf_filtered (" ");
4114 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
4116 if (*REGISTER_NAME (regnum
) == '\0')
4117 continue; /* unused register */
4118 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4119 break; /* end the row: reached FP register */
4120 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
4121 REGISTER_NAME (regnum
));
4124 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
4125 start_regnum
); /* print the R0 to R31 names */
4127 regnum
= start_regnum
; /* go back to start of row */
4128 /* now print the values in hex, 4 or 8 to the row */
4129 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
4131 if (*REGISTER_NAME (regnum
) == '\0')
4132 continue; /* unused register */
4133 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4134 break; /* end row: reached FP register */
4135 /* OK: get the data in raw format. */
4136 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
4137 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4138 /* pad small registers */
4139 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
4140 printf_filtered (" ");
4141 /* Now print the register value in hex, endian order. */
4142 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4143 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
4144 byte
< REGISTER_RAW_SIZE (regnum
);
4146 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
4148 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
4151 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
4152 printf_filtered (" ");
4155 if (col
> 0) /* ie. if we actually printed anything... */
4156 printf_filtered ("\n");
4161 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4164 mips_do_registers_info (int regnum
, int fpregs
)
4166 if (regnum
!= -1) /* do one specified register */
4168 if (*(REGISTER_NAME (regnum
)) == '\0')
4169 error ("Not a valid register for the current processor type");
4171 mips_print_register (regnum
, 0);
4172 printf_filtered ("\n");
4175 /* do all (or most) registers */
4178 while (regnum
< NUM_REGS
)
4180 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4181 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
4182 regnum
= do_fp_register_row (regnum
); /* FP regs */
4184 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4186 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
4191 /* Is this a branch with a delay slot? */
4193 static int is_delayed (unsigned long);
4196 is_delayed (unsigned long insn
)
4199 for (i
= 0; i
< NUMOPCODES
; ++i
)
4200 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4201 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4203 return (i
< NUMOPCODES
4204 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4205 | INSN_COND_BRANCH_DELAY
4206 | INSN_COND_BRANCH_LIKELY
)));
4210 mips_step_skips_delay (CORE_ADDR pc
)
4212 char buf
[MIPS_INSTLEN
];
4214 /* There is no branch delay slot on MIPS16. */
4215 if (pc_is_mips16 (pc
))
4218 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4219 /* If error reading memory, guess that it is not a delayed branch. */
4221 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4225 /* Skip the PC past function prologue instructions (32-bit version).
4226 This is a helper function for mips_skip_prologue. */
4229 mips32_skip_prologue (CORE_ADDR pc
)
4233 int seen_sp_adjust
= 0;
4234 int load_immediate_bytes
= 0;
4236 /* Skip the typical prologue instructions. These are the stack adjustment
4237 instruction and the instructions that save registers on the stack
4238 or in the gcc frame. */
4239 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4241 unsigned long high_word
;
4243 inst
= mips_fetch_instruction (pc
);
4244 high_word
= (inst
>> 16) & 0xffff;
4246 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4247 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4249 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4250 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4252 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4253 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4254 && (inst
& 0x001F0000)) /* reg != $zero */
4257 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4259 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4261 continue; /* reg != $zero */
4263 /* move $s8,$sp. With different versions of gas this will be either
4264 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4265 Accept any one of these. */
4266 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4269 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4271 else if (high_word
== 0x3c1c) /* lui $gp,n */
4273 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4275 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4276 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4278 /* The following instructions load $at or $t0 with an immediate
4279 value in preparation for a stack adjustment via
4280 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4281 a local variable, so we accept them only before a stack adjustment
4282 instruction was seen. */
4283 else if (!seen_sp_adjust
)
4285 if (high_word
== 0x3c01 || /* lui $at,n */
4286 high_word
== 0x3c08) /* lui $t0,n */
4288 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4291 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4292 high_word
== 0x3508 || /* ori $t0,$t0,n */
4293 high_word
== 0x3401 || /* ori $at,$zero,n */
4294 high_word
== 0x3408) /* ori $t0,$zero,n */
4296 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4306 /* In a frameless function, we might have incorrectly
4307 skipped some load immediate instructions. Undo the skipping
4308 if the load immediate was not followed by a stack adjustment. */
4309 if (load_immediate_bytes
&& !seen_sp_adjust
)
4310 pc
-= load_immediate_bytes
;
4314 /* Skip the PC past function prologue instructions (16-bit version).
4315 This is a helper function for mips_skip_prologue. */
4318 mips16_skip_prologue (CORE_ADDR pc
)
4321 int extend_bytes
= 0;
4322 int prev_extend_bytes
;
4324 /* Table of instructions likely to be found in a function prologue. */
4327 unsigned short inst
;
4328 unsigned short mask
;
4335 , /* addiu $sp,offset */
4339 , /* daddiu $sp,offset */
4343 , /* sw reg,n($sp) */
4347 , /* sd reg,n($sp) */
4351 , /* sw $ra,n($sp) */
4355 , /* sd $ra,n($sp) */
4363 , /* sw $a0-$a3,n($s1) */
4367 , /* move reg,$a0-$a3 */
4371 , /* entry pseudo-op */
4375 , /* addiu $s1,$sp,n */
4378 } /* end of table marker */
4381 /* Skip the typical prologue instructions. These are the stack adjustment
4382 instruction and the instructions that save registers on the stack
4383 or in the gcc frame. */
4384 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4386 unsigned short inst
;
4389 inst
= mips_fetch_instruction (pc
);
4391 /* Normally we ignore an extend instruction. However, if it is
4392 not followed by a valid prologue instruction, we must adjust
4393 the pc back over the extend so that it won't be considered
4394 part of the prologue. */
4395 if ((inst
& 0xf800) == 0xf000) /* extend */
4397 extend_bytes
= MIPS16_INSTLEN
;
4400 prev_extend_bytes
= extend_bytes
;
4403 /* Check for other valid prologue instructions besides extend. */
4404 for (i
= 0; table
[i
].mask
!= 0; i
++)
4405 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4407 if (table
[i
].mask
!= 0) /* it was in table? */
4408 continue; /* ignore it */
4412 /* Return the current pc, adjusted backwards by 2 if
4413 the previous instruction was an extend. */
4414 return pc
- prev_extend_bytes
;
4420 /* To skip prologues, I use this predicate. Returns either PC itself
4421 if the code at PC does not look like a function prologue; otherwise
4422 returns an address that (if we're lucky) follows the prologue. If
4423 LENIENT, then we must skip everything which is involved in setting
4424 up the frame (it's OK to skip more, just so long as we don't skip
4425 anything which might clobber the registers which are being saved.
4426 We must skip more in the case where part of the prologue is in the
4427 delay slot of a non-prologue instruction). */
4430 mips_skip_prologue (CORE_ADDR pc
)
4432 /* See if we can determine the end of the prologue via the symbol table.
4433 If so, then return either PC, or the PC after the prologue, whichever
4436 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4438 if (post_prologue_pc
!= 0)
4439 return max (pc
, post_prologue_pc
);
4441 /* Can't determine prologue from the symbol table, need to examine
4444 if (pc_is_mips16 (pc
))
4445 return mips16_skip_prologue (pc
);
4447 return mips32_skip_prologue (pc
);
4450 /* Determine how a return value is stored within the MIPS register
4451 file, given the return type `valtype'. */
4453 struct return_value_word
4462 return_value_location (struct type
*valtype
,
4463 struct return_value_word
*hi
,
4464 struct return_value_word
*lo
)
4466 int len
= TYPE_LENGTH (valtype
);
4468 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4469 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4470 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4472 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4474 /* We need to break a 64bit float in two 32 bit halves and
4475 spread them across a floating-point register pair. */
4476 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4477 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4478 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4479 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
4481 hi
->reg_offset
= lo
->reg_offset
;
4482 lo
->reg
= FP0_REGNUM
+ 0;
4483 hi
->reg
= FP0_REGNUM
+ 1;
4489 /* The floating point value fits in a single floating-point
4491 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4492 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
4495 lo
->reg
= FP0_REGNUM
;
4506 /* Locate a result possibly spread across two registers. */
4508 lo
->reg
= regnum
+ 0;
4509 hi
->reg
= regnum
+ 1;
4510 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4511 && len
< MIPS_SAVED_REGSIZE
)
4513 /* "un-left-justify" the value in the low register */
4514 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4519 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4520 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4521 && len
< MIPS_SAVED_REGSIZE
* 2
4522 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4523 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4525 /* "un-left-justify" the value spread across two registers. */
4526 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4527 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4529 hi
->len
= len
- lo
->len
;
4533 /* Only perform a partial copy of the second register. */
4536 if (len
> MIPS_SAVED_REGSIZE
)
4538 lo
->len
= MIPS_SAVED_REGSIZE
;
4539 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4547 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4548 && REGISTER_RAW_SIZE (regnum
) == 8
4549 && MIPS_SAVED_REGSIZE
== 4)
4551 /* Account for the fact that only the least-signficant part
4552 of the register is being used */
4553 lo
->reg_offset
+= 4;
4554 hi
->reg_offset
+= 4;
4557 hi
->buf_offset
= lo
->len
;
4561 /* Given a return value in `regbuf' with a type `valtype', extract and
4562 copy its value into `valbuf'. */
4565 mips_eabi_extract_return_value (struct type
*valtype
,
4566 char regbuf
[REGISTER_BYTES
],
4569 struct return_value_word lo
;
4570 struct return_value_word hi
;
4571 return_value_location (valtype
, &hi
, &lo
);
4573 memcpy (valbuf
+ lo
.buf_offset
,
4574 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4578 memcpy (valbuf
+ hi
.buf_offset
,
4579 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4584 mips_o64_extract_return_value (struct type
*valtype
,
4585 char regbuf
[REGISTER_BYTES
],
4588 struct return_value_word lo
;
4589 struct return_value_word hi
;
4590 return_value_location (valtype
, &hi
, &lo
);
4592 memcpy (valbuf
+ lo
.buf_offset
,
4593 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4597 memcpy (valbuf
+ hi
.buf_offset
,
4598 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4602 /* Given a return value in `valbuf' with a type `valtype', write it's
4603 value into the appropriate register. */
4606 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4608 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4609 struct return_value_word lo
;
4610 struct return_value_word hi
;
4611 return_value_location (valtype
, &hi
, &lo
);
4613 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4614 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4615 write_register_bytes (REGISTER_BYTE (lo
.reg
),
4617 REGISTER_RAW_SIZE (lo
.reg
));
4621 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4622 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4623 write_register_bytes (REGISTER_BYTE (hi
.reg
),
4625 REGISTER_RAW_SIZE (hi
.reg
));
4630 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4632 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4633 struct return_value_word lo
;
4634 struct return_value_word hi
;
4635 return_value_location (valtype
, &hi
, &lo
);
4637 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4638 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4639 write_register_bytes (REGISTER_BYTE (lo
.reg
),
4641 REGISTER_RAW_SIZE (lo
.reg
));
4645 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4646 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4647 write_register_bytes (REGISTER_BYTE (hi
.reg
),
4649 REGISTER_RAW_SIZE (hi
.reg
));
4653 /* O32 ABI stuff. */
4656 mips_o32_xfer_return_value (struct type
*type
,
4657 struct regcache
*regcache
,
4658 bfd_byte
*in
, const bfd_byte
*out
)
4660 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4661 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4662 && TYPE_LENGTH (type
) == 4
4663 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4665 /* A single-precision floating-point value. It fits in the
4666 least significant part of FP0. */
4668 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4669 mips_xfer_register (regcache
, FP0_REGNUM
, TYPE_LENGTH (type
),
4670 TARGET_BYTE_ORDER
, in
, out
, 0);
4672 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4673 && TYPE_LENGTH (type
) == 8
4674 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4676 /* A double-precision floating-point value. It fits in the
4677 least significant part of FP0/FP1 but with byte ordering
4678 based on the target (???). */
4680 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0/$fp1\n");
4681 switch (TARGET_BYTE_ORDER
)
4683 case BFD_ENDIAN_LITTLE
:
4684 mips_xfer_register (regcache
, FP0_REGNUM
+ 0, 4,
4685 TARGET_BYTE_ORDER
, in
, out
, 0);
4686 mips_xfer_register (regcache
, FP0_REGNUM
+ 1, 4,
4687 TARGET_BYTE_ORDER
, in
, out
, 4);
4689 case BFD_ENDIAN_BIG
:
4690 mips_xfer_register (regcache
, FP0_REGNUM
+ 1, 4,
4691 TARGET_BYTE_ORDER
, in
, out
, 0);
4692 mips_xfer_register (regcache
, FP0_REGNUM
+ 0, 4,
4693 TARGET_BYTE_ORDER
, in
, out
, 4);
4696 internal_error (__FILE__
, __LINE__
, "bad switch");
4700 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4701 && TYPE_NFIELDS (type
) <= 2
4702 && TYPE_NFIELDS (type
) >= 1
4703 && ((TYPE_NFIELDS (type
) == 1
4704 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4706 || (TYPE_NFIELDS (type
) == 2
4707 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4709 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4711 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4713 /* A struct that contains one or two floats. Each value is part
4714 in the least significant part of their floating point
4716 bfd_byte
*reg
= alloca (MAX_REGISTER_RAW_SIZE
);
4719 for (field
= 0, regnum
= FP0_REGNUM
;
4720 field
< TYPE_NFIELDS (type
);
4721 field
++, regnum
+= 2)
4723 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4726 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4727 mips_xfer_register (regcache
, regnum
, TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4728 TARGET_BYTE_ORDER
, in
, out
, offset
);
4733 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4734 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4736 /* A structure or union. Extract the left justified value,
4737 regardless of the byte order. I.e. DO NOT USE
4741 for (offset
= 0, regnum
= V0_REGNUM
;
4742 offset
< TYPE_LENGTH (type
);
4743 offset
+= REGISTER_RAW_SIZE (regnum
), regnum
++)
4745 int xfer
= REGISTER_RAW_SIZE (regnum
);
4746 if (offset
+ xfer
> TYPE_LENGTH (type
))
4747 xfer
= TYPE_LENGTH (type
) - offset
;
4749 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4750 offset
, xfer
, regnum
);
4751 mips_xfer_register (regcache
, regnum
, xfer
, BFD_ENDIAN_UNKNOWN
,
4758 /* A scalar extract each part but least-significant-byte
4759 justified. o32 thinks registers are 4 byte, regardless of
4760 the ISA. mips_stack_argsize controls this. */
4763 for (offset
= 0, regnum
= V0_REGNUM
;
4764 offset
< TYPE_LENGTH (type
);
4765 offset
+= mips_stack_argsize (), regnum
++)
4767 int xfer
= mips_stack_argsize ();
4769 if (offset
+ xfer
> TYPE_LENGTH (type
))
4770 xfer
= TYPE_LENGTH (type
) - offset
;
4772 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4773 offset
, xfer
, regnum
);
4774 mips_xfer_register (regcache
, regnum
, xfer
, TARGET_BYTE_ORDER
,
4781 mips_o32_extract_return_value (struct type
*type
,
4782 struct regcache
*regcache
,
4785 mips_o32_xfer_return_value (type
, regcache
, valbuf
, NULL
);
4789 mips_o32_store_return_value (struct type
*type
, char *valbuf
)
4791 mips_o32_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
4794 /* N32/N44 ABI stuff. */
4797 mips_n32n64_xfer_return_value (struct type
*type
,
4798 struct regcache
*regcache
,
4799 bfd_byte
*in
, const bfd_byte
*out
)
4801 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4802 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4803 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4805 /* A floating-point value belongs in the least significant part
4808 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4809 mips_xfer_register (regcache
, FP0_REGNUM
, TYPE_LENGTH (type
),
4810 TARGET_BYTE_ORDER
, in
, out
, 0);
4812 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4813 && TYPE_NFIELDS (type
) <= 2
4814 && TYPE_NFIELDS (type
) >= 1
4815 && ((TYPE_NFIELDS (type
) == 1
4816 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4818 || (TYPE_NFIELDS (type
) == 2
4819 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4821 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4823 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4825 /* A struct that contains one or two floats. Each value is part
4826 in the least significant part of their floating point
4828 bfd_byte
*reg
= alloca (MAX_REGISTER_RAW_SIZE
);
4831 for (field
= 0, regnum
= FP0_REGNUM
;
4832 field
< TYPE_NFIELDS (type
);
4833 field
++, regnum
+= 2)
4835 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4838 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4839 mips_xfer_register (regcache
, regnum
, TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4840 TARGET_BYTE_ORDER
, in
, out
, offset
);
4843 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4844 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4846 /* A structure or union. Extract the left justified value,
4847 regardless of the byte order. I.e. DO NOT USE
4851 for (offset
= 0, regnum
= V0_REGNUM
;
4852 offset
< TYPE_LENGTH (type
);
4853 offset
+= REGISTER_RAW_SIZE (regnum
), regnum
++)
4855 int xfer
= REGISTER_RAW_SIZE (regnum
);
4856 if (offset
+ xfer
> TYPE_LENGTH (type
))
4857 xfer
= TYPE_LENGTH (type
) - offset
;
4859 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4860 offset
, xfer
, regnum
);
4861 mips_xfer_register (regcache
, regnum
, xfer
, BFD_ENDIAN_UNKNOWN
,
4867 /* A scalar extract each part but least-significant-byte
4871 for (offset
= 0, regnum
= V0_REGNUM
;
4872 offset
< TYPE_LENGTH (type
);
4873 offset
+= REGISTER_RAW_SIZE (regnum
), regnum
++)
4875 int xfer
= REGISTER_RAW_SIZE (regnum
);
4877 if (offset
+ xfer
> TYPE_LENGTH (type
))
4878 xfer
= TYPE_LENGTH (type
) - offset
;
4880 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4881 offset
, xfer
, regnum
);
4882 mips_xfer_register (regcache
, regnum
, xfer
, TARGET_BYTE_ORDER
,
4889 mips_n32n64_extract_return_value (struct type
*type
,
4890 struct regcache
*regcache
,
4893 mips_n32n64_xfer_return_value (type
, regcache
, valbuf
, NULL
);
4897 mips_n32n64_store_return_value (struct type
*type
, char *valbuf
)
4899 mips_n32n64_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
4903 mips_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
4905 /* Nothing to do -- push_arguments does all the work. */
4909 mips_extract_struct_value_address (struct regcache
*ignore
)
4911 /* FIXME: This will only work at random. The caller passes the
4912 struct_return address in V0, but it is not preserved. It may
4913 still be there, or this may be a random value. */
4914 return read_register (V0_REGNUM
);
4917 /* Exported procedure: Is PC in the signal trampoline code */
4920 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
4922 if (sigtramp_address
== 0)
4924 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
4927 /* Root of all "set mips "/"show mips " commands. This will eventually be
4928 used for all MIPS-specific commands. */
4931 show_mips_command (char *args
, int from_tty
)
4933 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4937 set_mips_command (char *args
, int from_tty
)
4939 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
4940 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4943 /* Commands to show/set the MIPS FPU type. */
4946 show_mipsfpu_command (char *args
, int from_tty
)
4949 switch (MIPS_FPU_TYPE
)
4951 case MIPS_FPU_SINGLE
:
4952 fpu
= "single-precision";
4954 case MIPS_FPU_DOUBLE
:
4955 fpu
= "double-precision";
4958 fpu
= "absent (none)";
4961 internal_error (__FILE__
, __LINE__
, "bad switch");
4963 if (mips_fpu_type_auto
)
4964 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4967 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
4973 set_mipsfpu_command (char *args
, int from_tty
)
4975 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4976 show_mipsfpu_command (args
, from_tty
);
4980 set_mipsfpu_single_command (char *args
, int from_tty
)
4982 mips_fpu_type
= MIPS_FPU_SINGLE
;
4983 mips_fpu_type_auto
= 0;
4984 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
4988 set_mipsfpu_double_command (char *args
, int from_tty
)
4990 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4991 mips_fpu_type_auto
= 0;
4992 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4996 set_mipsfpu_none_command (char *args
, int from_tty
)
4998 mips_fpu_type
= MIPS_FPU_NONE
;
4999 mips_fpu_type_auto
= 0;
5000 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
5004 set_mipsfpu_auto_command (char *args
, int from_tty
)
5006 mips_fpu_type_auto
= 1;
5009 /* Command to set the processor type. */
5012 mips_set_processor_type_command (char *args
, int from_tty
)
5016 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
5018 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5019 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5020 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
5022 /* Restore the value. */
5023 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5028 if (!mips_set_processor_type (tmp_mips_processor_type
))
5030 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
5031 /* Restore its value. */
5032 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5037 mips_show_processor_type_command (char *args
, int from_tty
)
5041 /* Modify the actual processor type. */
5044 mips_set_processor_type (char *str
)
5051 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5053 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
5055 mips_processor_type
= str
;
5056 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
5058 /* FIXME tweak fpu flag too */
5065 /* Attempt to identify the particular processor model by reading the
5069 mips_read_processor_type (void)
5073 prid
= read_register (PRID_REGNUM
);
5075 if ((prid
& ~0xf) == 0x700)
5076 return savestring ("r3041", strlen ("r3041"));
5081 /* Just like reinit_frame_cache, but with the right arguments to be
5082 callable as an sfunc. */
5085 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5086 struct cmd_list_element
*c
)
5088 reinit_frame_cache ();
5092 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
5094 mips_extra_func_info_t proc_desc
;
5096 /* Search for the function containing this address. Set the low bit
5097 of the address when searching, in case we were given an even address
5098 that is the start of a 16-bit function. If we didn't do this,
5099 the search would fail because the symbol table says the function
5100 starts at an odd address, i.e. 1 byte past the given address. */
5101 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5102 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
5104 /* Make an attempt to determine if this is a 16-bit function. If
5105 the procedure descriptor exists and the address therein is odd,
5106 it's definitely a 16-bit function. Otherwise, we have to just
5107 guess that if the address passed in is odd, it's 16-bits. */
5109 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
5110 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
5112 info
->mach
= pc_is_mips16 (memaddr
) ?
5113 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
5115 /* Round down the instruction address to the appropriate boundary. */
5116 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5118 /* Call the appropriate disassembler based on the target endian-ness. */
5119 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5120 return print_insn_big_mips (memaddr
, info
);
5122 return print_insn_little_mips (memaddr
, info
);
5125 /* Old-style breakpoint macros.
5126 The IDT board uses an unusual breakpoint value, and sometimes gets
5127 confused when it sees the usual MIPS breakpoint instruction. */
5129 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
5130 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
5131 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
5132 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
5133 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
5134 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
5135 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
5136 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
5138 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5139 counter value to determine whether a 16- or 32-bit breakpoint should be
5140 used. It returns a pointer to a string of bytes that encode a breakpoint
5141 instruction, stores the length of the string to *lenptr, and adjusts pc
5142 (if necessary) to point to the actual memory location where the
5143 breakpoint should be inserted. */
5145 static const unsigned char *
5146 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5148 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5150 if (pc_is_mips16 (*pcptr
))
5152 static unsigned char mips16_big_breakpoint
[] =
5153 MIPS16_BIG_BREAKPOINT
;
5154 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
5155 *lenptr
= sizeof (mips16_big_breakpoint
);
5156 return mips16_big_breakpoint
;
5160 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
5161 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
5162 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
5164 *lenptr
= sizeof (big_breakpoint
);
5166 if (strcmp (target_shortname
, "mips") == 0)
5167 return idt_big_breakpoint
;
5168 else if (strcmp (target_shortname
, "ddb") == 0
5169 || strcmp (target_shortname
, "pmon") == 0
5170 || strcmp (target_shortname
, "lsi") == 0)
5171 return pmon_big_breakpoint
;
5173 return big_breakpoint
;
5178 if (pc_is_mips16 (*pcptr
))
5180 static unsigned char mips16_little_breakpoint
[] =
5181 MIPS16_LITTLE_BREAKPOINT
;
5182 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
5183 *lenptr
= sizeof (mips16_little_breakpoint
);
5184 return mips16_little_breakpoint
;
5188 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
5189 static unsigned char pmon_little_breakpoint
[] =
5190 PMON_LITTLE_BREAKPOINT
;
5191 static unsigned char idt_little_breakpoint
[] =
5192 IDT_LITTLE_BREAKPOINT
;
5194 *lenptr
= sizeof (little_breakpoint
);
5196 if (strcmp (target_shortname
, "mips") == 0)
5197 return idt_little_breakpoint
;
5198 else if (strcmp (target_shortname
, "ddb") == 0
5199 || strcmp (target_shortname
, "pmon") == 0
5200 || strcmp (target_shortname
, "lsi") == 0)
5201 return pmon_little_breakpoint
;
5203 return little_breakpoint
;
5208 /* If PC is in a mips16 call or return stub, return the address of the target
5209 PC, which is either the callee or the caller. There are several
5210 cases which must be handled:
5212 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5213 target PC is in $31 ($ra).
5214 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5215 and the target PC is in $2.
5216 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5217 before the jal instruction, this is effectively a call stub
5218 and the the target PC is in $2. Otherwise this is effectively
5219 a return stub and the target PC is in $18.
5221 See the source code for the stubs in gcc/config/mips/mips16.S for
5224 This function implements the SKIP_TRAMPOLINE_CODE macro.
5228 mips_skip_stub (CORE_ADDR pc
)
5231 CORE_ADDR start_addr
;
5233 /* Find the starting address and name of the function containing the PC. */
5234 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5237 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5238 target PC is in $31 ($ra). */
5239 if (strcmp (name
, "__mips16_ret_sf") == 0
5240 || strcmp (name
, "__mips16_ret_df") == 0)
5241 return read_signed_register (RA_REGNUM
);
5243 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5245 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5246 and the target PC is in $2. */
5247 if (name
[19] >= '0' && name
[19] <= '9')
5248 return read_signed_register (2);
5250 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5251 before the jal instruction, this is effectively a call stub
5252 and the the target PC is in $2. Otherwise this is effectively
5253 a return stub and the target PC is in $18. */
5254 else if (name
[19] == 's' || name
[19] == 'd')
5256 if (pc
== start_addr
)
5258 /* Check if the target of the stub is a compiler-generated
5259 stub. Such a stub for a function bar might have a name
5260 like __fn_stub_bar, and might look like this:
5265 la $1,bar (becomes a lui/addiu pair)
5267 So scan down to the lui/addi and extract the target
5268 address from those two instructions. */
5270 CORE_ADDR target_pc
= read_signed_register (2);
5274 /* See if the name of the target function is __fn_stub_*. */
5275 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5277 if (strncmp (name
, "__fn_stub_", 10) != 0
5278 && strcmp (name
, "etext") != 0
5279 && strcmp (name
, "_etext") != 0)
5282 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5283 The limit on the search is arbitrarily set to 20
5284 instructions. FIXME. */
5285 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5287 inst
= mips_fetch_instruction (target_pc
);
5288 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5289 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5290 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5291 return pc
| (inst
& 0xffff); /* low word */
5294 /* Couldn't find the lui/addui pair, so return stub address. */
5298 /* This is the 'return' part of a call stub. The return
5299 address is in $r18. */
5300 return read_signed_register (18);
5303 return 0; /* not a stub */
5307 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5308 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5311 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5313 CORE_ADDR start_addr
;
5315 /* Find the starting address of the function containing the PC. If the
5316 caller didn't give us a name, look it up at the same time. */
5317 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5320 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5322 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5323 if (name
[19] >= '0' && name
[19] <= '9')
5325 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5326 before the jal instruction, this is effectively a call stub. */
5327 else if (name
[19] == 's' || name
[19] == 'd')
5328 return pc
== start_addr
;
5331 return 0; /* not a stub */
5335 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5336 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5339 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5341 CORE_ADDR start_addr
;
5343 /* Find the starting address of the function containing the PC. */
5344 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5347 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5348 if (strcmp (name
, "__mips16_ret_sf") == 0
5349 || strcmp (name
, "__mips16_ret_df") == 0)
5352 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5353 i.e. after the jal instruction, this is effectively a return stub. */
5354 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5355 && (name
[19] == 's' || name
[19] == 'd')
5356 && pc
!= start_addr
)
5359 return 0; /* not a stub */
5363 /* Return non-zero if the PC is in a library helper function that should
5364 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5367 mips_ignore_helper (CORE_ADDR pc
)
5371 /* Find the starting address and name of the function containing the PC. */
5372 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5375 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5376 that we want to ignore. */
5377 return (strcmp (name
, "__mips16_ret_sf") == 0
5378 || strcmp (name
, "__mips16_ret_df") == 0);
5382 /* Return a location where we can set a breakpoint that will be hit
5383 when an inferior function call returns. This is normally the
5384 program's entry point. Executables that don't have an entry
5385 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
5386 whose address is the location where the breakpoint should be placed. */
5389 mips_call_dummy_address (void)
5391 struct minimal_symbol
*sym
;
5393 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
5395 return SYMBOL_VALUE_ADDRESS (sym
);
5397 return entry_point_address ();
5401 /* If the current gcc for this target does not produce correct debugging
5402 information for float parameters, both prototyped and unprototyped, then
5403 define this macro. This forces gdb to always assume that floats are
5404 passed as doubles and then converted in the callee.
5406 For the mips chip, it appears that the debug info marks the parameters as
5407 floats regardless of whether the function is prototyped, but the actual
5408 values are passed as doubles for the non-prototyped case and floats for
5409 the prototyped case. Thus we choose to make the non-prototyped case work
5410 for C and break the prototyped case, since the non-prototyped case is
5411 probably much more common. (FIXME). */
5414 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
5416 return current_language
->la_language
== language_c
;
5419 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5420 the register stored on the stack (32) is different to its real raw
5421 size (64). The below ensures that registers are fetched from the
5422 stack using their ABI size and then stored into the RAW_BUFFER
5423 using their raw size.
5425 The alternative to adding this function would be to add an ABI
5426 macro - REGISTER_STACK_SIZE(). */
5429 mips_get_saved_register (char *raw_buffer
,
5432 struct frame_info
*frame
,
5434 enum lval_type
*lval
)
5438 if (!target_has_registers
)
5439 error ("No registers.");
5441 /* Normal systems don't optimize out things with register numbers. */
5442 if (optimized
!= NULL
)
5444 addr
= find_saved_register (frame
, regnum
);
5448 *lval
= lval_memory
;
5449 if (regnum
== SP_REGNUM
)
5451 if (raw_buffer
!= NULL
)
5453 /* Put it back in target format. */
5454 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
5461 if (raw_buffer
!= NULL
)
5465 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
5467 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
5469 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
5470 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
5476 *lval
= lval_register
;
5477 addr
= REGISTER_BYTE (regnum
);
5478 if (raw_buffer
!= NULL
)
5479 read_register_gen (regnum
, raw_buffer
);
5485 /* Immediately after a function call, return the saved pc.
5486 Can't always go through the frames for this because on some machines
5487 the new frame is not set up until the new function executes
5488 some instructions. */
5491 mips_saved_pc_after_call (struct frame_info
*frame
)
5493 return read_signed_register (RA_REGNUM
);
5497 /* Convert a dbx stab register number (from `r' declaration) to a gdb
5501 mips_stab_reg_to_regnum (int num
)
5506 return num
+ FP0_REGNUM
- 38;
5509 /* Convert a ecoff register number to a gdb REGNUM */
5512 mips_ecoff_reg_to_regnum (int num
)
5517 return num
+ FP0_REGNUM
- 32;
5520 /* Convert an integer into an address. By first converting the value
5521 into a pointer and then extracting it signed, the address is
5522 guarenteed to be correctly sign extended. */
5525 mips_integer_to_address (struct type
*type
, void *buf
)
5527 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5528 LONGEST val
= unpack_long (type
, buf
);
5529 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5530 return extract_signed_integer (tmp
,
5531 TYPE_LENGTH (builtin_type_void_data_ptr
));
5535 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5537 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5538 const char *name
= bfd_get_section_name (abfd
, sect
);
5540 if (*abip
!= MIPS_ABI_UNKNOWN
)
5543 if (strncmp (name
, ".mdebug.", 8) != 0)
5546 if (strcmp (name
, ".mdebug.abi32") == 0)
5547 *abip
= MIPS_ABI_O32
;
5548 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5549 *abip
= MIPS_ABI_N32
;
5550 else if (strcmp (name
, ".mdebug.abiN64") == 0)
5551 *abip
= MIPS_ABI_N64
;
5552 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5553 *abip
= MIPS_ABI_O64
;
5554 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5555 *abip
= MIPS_ABI_EABI32
;
5556 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5557 *abip
= MIPS_ABI_EABI64
;
5559 warning ("unsupported ABI %s.", name
+ 8);
5562 static enum mips_abi
5563 global_mips_abi (void)
5567 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5568 if (mips_abi_strings
[i
] == mips_abi_string
)
5569 return (enum mips_abi
) i
;
5571 internal_error (__FILE__
, __LINE__
,
5572 "unknown ABI string");
5575 static struct gdbarch
*
5576 mips_gdbarch_init (struct gdbarch_info info
,
5577 struct gdbarch_list
*arches
)
5579 static LONGEST mips_call_dummy_words
[] =
5581 struct gdbarch
*gdbarch
;
5582 struct gdbarch_tdep
*tdep
;
5584 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5585 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
5587 /* Reset the disassembly info, in case it was set to something
5589 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
5590 tm_print_insn_info
.arch
= bfd_arch_unknown
;
5591 tm_print_insn_info
.mach
= 0;
5597 /* First of all, extract the elf_flags, if available. */
5598 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5599 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5601 /* Try to determine the OS ABI of the object we are loading. If
5602 we end up with `unknown', just leave it that way. */
5603 osabi
= gdbarch_lookup_osabi (info
.abfd
);
5606 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5607 switch ((elf_flags
& EF_MIPS_ABI
))
5609 case E_MIPS_ABI_O32
:
5610 mips_abi
= MIPS_ABI_O32
;
5612 case E_MIPS_ABI_O64
:
5613 mips_abi
= MIPS_ABI_O64
;
5615 case E_MIPS_ABI_EABI32
:
5616 mips_abi
= MIPS_ABI_EABI32
;
5618 case E_MIPS_ABI_EABI64
:
5619 mips_abi
= MIPS_ABI_EABI64
;
5622 if ((elf_flags
& EF_MIPS_ABI2
))
5623 mips_abi
= MIPS_ABI_N32
;
5625 mips_abi
= MIPS_ABI_UNKNOWN
;
5629 /* GCC creates a pseudo-section whose name describes the ABI. */
5630 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5631 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
5633 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5634 Use the ABI from the last architecture if there is one. */
5635 if (info
.abfd
== NULL
&& arches
!= NULL
)
5636 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5638 /* Try the architecture for any hint of the correct ABI. */
5639 if (mips_abi
== MIPS_ABI_UNKNOWN
5640 && info
.bfd_arch_info
!= NULL
5641 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5643 switch (info
.bfd_arch_info
->mach
)
5645 case bfd_mach_mips3900
:
5646 mips_abi
= MIPS_ABI_EABI32
;
5648 case bfd_mach_mips4100
:
5649 case bfd_mach_mips5000
:
5650 mips_abi
= MIPS_ABI_EABI64
;
5652 case bfd_mach_mips8000
:
5653 case bfd_mach_mips10000
:
5654 /* On Irix, ELF64 executables use the N64 ABI. The
5655 pseudo-sections which describe the ABI aren't present
5656 on IRIX. (Even for executables created by gcc.) */
5657 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5658 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5659 mips_abi
= MIPS_ABI_N64
;
5661 mips_abi
= MIPS_ABI_N32
;
5666 if (mips_abi
== MIPS_ABI_UNKNOWN
)
5667 mips_abi
= MIPS_ABI_O32
;
5669 /* Now that we have found what the ABI for this binary would be,
5670 check whether the user is overriding it. */
5671 found_abi
= mips_abi
;
5672 wanted_abi
= global_mips_abi ();
5673 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5674 mips_abi
= wanted_abi
;
5678 fprintf_unfiltered (gdb_stdlog
,
5679 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5681 fprintf_unfiltered (gdb_stdlog
,
5682 "mips_gdbarch_init: mips_abi = %d\n",
5684 fprintf_unfiltered (gdb_stdlog
,
5685 "mips_gdbarch_init: found_mips_abi = %d\n",
5689 /* try to find a pre-existing architecture */
5690 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5692 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5694 /* MIPS needs to be pedantic about which ABI the object is
5696 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5698 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5700 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
5701 return arches
->gdbarch
;
5704 /* Need a new architecture. Fill in a target specific vector. */
5705 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5706 gdbarch
= gdbarch_alloc (&info
, tdep
);
5707 tdep
->elf_flags
= elf_flags
;
5708 tdep
->osabi
= osabi
;
5710 /* Initially set everything according to the default ABI/ISA. */
5711 set_gdbarch_short_bit (gdbarch
, 16);
5712 set_gdbarch_int_bit (gdbarch
, 32);
5713 set_gdbarch_float_bit (gdbarch
, 32);
5714 set_gdbarch_double_bit (gdbarch
, 64);
5715 set_gdbarch_long_double_bit (gdbarch
, 64);
5716 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
5717 set_gdbarch_max_register_raw_size (gdbarch
, 8);
5718 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
5719 tdep
->found_abi
= found_abi
;
5720 tdep
->mips_abi
= mips_abi
;
5722 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5723 mips_elf_make_msymbol_special
);
5728 set_gdbarch_push_arguments (gdbarch
, mips_o32_push_arguments
);
5729 set_gdbarch_store_return_value (gdbarch
, mips_o32_store_return_value
);
5730 set_gdbarch_extract_return_value (gdbarch
, mips_o32_extract_return_value
);
5731 tdep
->mips_default_saved_regsize
= 4;
5732 tdep
->mips_default_stack_argsize
= 4;
5733 tdep
->mips_fp_register_double
= 0;
5734 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5735 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5736 tdep
->gdb_target_is_mips64
= 0;
5737 tdep
->default_mask_address_p
= 0;
5738 set_gdbarch_long_bit (gdbarch
, 32);
5739 set_gdbarch_ptr_bit (gdbarch
, 32);
5740 set_gdbarch_long_long_bit (gdbarch
, 64);
5741 set_gdbarch_reg_struct_has_addr (gdbarch
,
5742 mips_o32_reg_struct_has_addr
);
5743 set_gdbarch_use_struct_convention (gdbarch
,
5744 mips_o32_use_struct_convention
);
5747 set_gdbarch_push_arguments (gdbarch
, mips_o64_push_arguments
);
5748 set_gdbarch_store_return_value (gdbarch
, mips_o64_store_return_value
);
5749 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5750 tdep
->mips_default_saved_regsize
= 8;
5751 tdep
->mips_default_stack_argsize
= 8;
5752 tdep
->mips_fp_register_double
= 1;
5753 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5754 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5755 tdep
->gdb_target_is_mips64
= 1;
5756 tdep
->default_mask_address_p
= 0;
5757 set_gdbarch_long_bit (gdbarch
, 32);
5758 set_gdbarch_ptr_bit (gdbarch
, 32);
5759 set_gdbarch_long_long_bit (gdbarch
, 64);
5760 set_gdbarch_reg_struct_has_addr (gdbarch
,
5761 mips_o32_reg_struct_has_addr
);
5762 set_gdbarch_use_struct_convention (gdbarch
,
5763 mips_o32_use_struct_convention
);
5765 case MIPS_ABI_EABI32
:
5766 set_gdbarch_push_arguments (gdbarch
, mips_eabi_push_arguments
);
5767 set_gdbarch_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5768 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5769 tdep
->mips_default_saved_regsize
= 4;
5770 tdep
->mips_default_stack_argsize
= 4;
5771 tdep
->mips_fp_register_double
= 0;
5772 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5773 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5774 tdep
->gdb_target_is_mips64
= 0;
5775 tdep
->default_mask_address_p
= 0;
5776 set_gdbarch_long_bit (gdbarch
, 32);
5777 set_gdbarch_ptr_bit (gdbarch
, 32);
5778 set_gdbarch_long_long_bit (gdbarch
, 64);
5779 set_gdbarch_reg_struct_has_addr (gdbarch
,
5780 mips_eabi_reg_struct_has_addr
);
5781 set_gdbarch_use_struct_convention (gdbarch
,
5782 mips_eabi_use_struct_convention
);
5784 case MIPS_ABI_EABI64
:
5785 set_gdbarch_push_arguments (gdbarch
, mips_eabi_push_arguments
);
5786 set_gdbarch_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5787 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5788 tdep
->mips_default_saved_regsize
= 8;
5789 tdep
->mips_default_stack_argsize
= 8;
5790 tdep
->mips_fp_register_double
= 1;
5791 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5792 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5793 tdep
->gdb_target_is_mips64
= 1;
5794 tdep
->default_mask_address_p
= 0;
5795 set_gdbarch_long_bit (gdbarch
, 64);
5796 set_gdbarch_ptr_bit (gdbarch
, 64);
5797 set_gdbarch_long_long_bit (gdbarch
, 64);
5798 set_gdbarch_reg_struct_has_addr (gdbarch
,
5799 mips_eabi_reg_struct_has_addr
);
5800 set_gdbarch_use_struct_convention (gdbarch
,
5801 mips_eabi_use_struct_convention
);
5804 set_gdbarch_push_arguments (gdbarch
, mips_n32n64_push_arguments
);
5805 set_gdbarch_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5806 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5807 tdep
->mips_default_saved_regsize
= 8;
5808 tdep
->mips_default_stack_argsize
= 8;
5809 tdep
->mips_fp_register_double
= 1;
5810 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5811 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5812 tdep
->gdb_target_is_mips64
= 1;
5813 tdep
->default_mask_address_p
= 0;
5814 set_gdbarch_long_bit (gdbarch
, 32);
5815 set_gdbarch_ptr_bit (gdbarch
, 32);
5816 set_gdbarch_long_long_bit (gdbarch
, 64);
5818 /* Set up the disassembler info, so that we get the right
5819 register names from libopcodes. */
5820 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
5821 tm_print_insn_info
.arch
= bfd_arch_mips
;
5822 if (info
.bfd_arch_info
!= NULL
5823 && info
.bfd_arch_info
->arch
== bfd_arch_mips
5824 && info
.bfd_arch_info
->mach
)
5825 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
5827 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
5829 set_gdbarch_use_struct_convention (gdbarch
,
5830 mips_n32n64_use_struct_convention
);
5831 set_gdbarch_reg_struct_has_addr (gdbarch
,
5832 mips_n32n64_reg_struct_has_addr
);
5835 set_gdbarch_push_arguments (gdbarch
, mips_n32n64_push_arguments
);
5836 set_gdbarch_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5837 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5838 tdep
->mips_default_saved_regsize
= 8;
5839 tdep
->mips_default_stack_argsize
= 8;
5840 tdep
->mips_fp_register_double
= 1;
5841 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5842 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5843 tdep
->gdb_target_is_mips64
= 1;
5844 tdep
->default_mask_address_p
= 0;
5845 set_gdbarch_long_bit (gdbarch
, 64);
5846 set_gdbarch_ptr_bit (gdbarch
, 64);
5847 set_gdbarch_long_long_bit (gdbarch
, 64);
5849 /* Set up the disassembler info, so that we get the right
5850 register names from libopcodes. */
5851 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
5852 tm_print_insn_info
.arch
= bfd_arch_mips
;
5853 if (info
.bfd_arch_info
!= NULL
5854 && info
.bfd_arch_info
->arch
== bfd_arch_mips
5855 && info
.bfd_arch_info
->mach
)
5856 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
5858 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
5860 set_gdbarch_use_struct_convention (gdbarch
,
5861 mips_n32n64_use_struct_convention
);
5862 set_gdbarch_reg_struct_has_addr (gdbarch
,
5863 mips_n32n64_reg_struct_has_addr
);
5866 internal_error (__FILE__
, __LINE__
,
5867 "unknown ABI in switch");
5870 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5871 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5874 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5875 flag in object files because to do so would make it impossible to
5876 link with libraries compiled without "-gp32". This is
5877 unnecessarily restrictive.
5879 We could solve this problem by adding "-gp32" multilibs to gcc,
5880 but to set this flag before gcc is built with such multilibs will
5881 break too many systems.''
5883 But even more unhelpfully, the default linker output target for
5884 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5885 for 64-bit programs - you need to change the ABI to change this,
5886 and not all gcc targets support that currently. Therefore using
5887 this flag to detect 32-bit mode would do the wrong thing given
5888 the current gcc - it would make GDB treat these 64-bit programs
5889 as 32-bit programs by default. */
5891 /* enable/disable the MIPS FPU */
5892 if (!mips_fpu_type_auto
)
5893 tdep
->mips_fpu_type
= mips_fpu_type
;
5894 else if (info
.bfd_arch_info
!= NULL
5895 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5896 switch (info
.bfd_arch_info
->mach
)
5898 case bfd_mach_mips3900
:
5899 case bfd_mach_mips4100
:
5900 case bfd_mach_mips4111
:
5901 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
5903 case bfd_mach_mips4650
:
5904 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
5907 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5911 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5913 /* MIPS version of register names. NOTE: At present the MIPS
5914 register name management is part way between the old -
5915 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
5916 Further work on it is required. */
5917 /* NOTE: many targets (esp. embedded) do not go thru the
5918 gdbarch_register_name vector at all, instead bypassing it
5919 by defining REGISTER_NAMES. */
5920 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5921 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5922 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
5923 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
5924 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5925 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
5927 /* Add/remove bits from an address. The MIPS needs be careful to
5928 ensure that all 32 bit addresses are sign extended to 64 bits. */
5929 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5931 /* There's a mess in stack frame creation. See comments in
5932 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
5933 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
5934 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
5936 /* Map debug register numbers onto internal register numbers. */
5937 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5938 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
5940 /* Initialize a frame */
5941 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
5942 set_gdbarch_frame_init_saved_regs (gdbarch
, mips_frame_init_saved_regs
);
5944 /* MIPS version of CALL_DUMMY */
5946 set_gdbarch_call_dummy_p (gdbarch
, 1);
5947 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
5948 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
5949 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
5950 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
5951 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
5952 set_gdbarch_push_dummy_frame (gdbarch
, mips_push_dummy_frame
);
5953 set_gdbarch_pop_frame (gdbarch
, mips_pop_frame
);
5954 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
5955 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
5956 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
5957 set_gdbarch_call_dummy_length (gdbarch
, 0);
5958 set_gdbarch_fix_call_dummy (gdbarch
, mips_fix_call_dummy
);
5959 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
5960 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
5961 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
5962 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
5963 set_gdbarch_register_convertible (gdbarch
, mips_register_convertible
);
5964 set_gdbarch_register_convert_to_virtual (gdbarch
,
5965 mips_register_convert_to_virtual
);
5966 set_gdbarch_register_convert_to_raw (gdbarch
,
5967 mips_register_convert_to_raw
);
5969 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
5971 set_gdbarch_frame_chain (gdbarch
, mips_frame_chain
);
5972 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
5973 set_gdbarch_frameless_function_invocation (gdbarch
,
5974 generic_frameless_function_invocation_not
);
5975 set_gdbarch_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
5976 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
5977 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
5978 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
5979 set_gdbarch_frame_args_skip (gdbarch
, 0);
5981 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
5983 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5984 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5985 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
5987 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5988 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
5990 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5991 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5992 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5994 set_gdbarch_function_start_offset (gdbarch
, 0);
5996 /* There are MIPS targets which do not yet use this since they still
5997 define REGISTER_VIRTUAL_TYPE. */
5998 set_gdbarch_register_virtual_type (gdbarch
, mips_register_virtual_type
);
5999 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
6001 set_gdbarch_do_registers_info (gdbarch
, mips_do_registers_info
);
6002 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6004 /* Hook in OS ABI-specific overrides, if they have been registered. */
6005 gdbarch_init_osabi (info
, gdbarch
, osabi
);
6007 set_gdbarch_store_struct_return (gdbarch
, mips_store_struct_return
);
6008 set_gdbarch_extract_struct_value_address (gdbarch
,
6009 mips_extract_struct_value_address
);
6011 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6013 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6014 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6020 mips_abi_update (char *ignore_args
, int from_tty
,
6021 struct cmd_list_element
*c
)
6023 struct gdbarch_info info
;
6025 /* Force the architecture to update, and (if it's a MIPS architecture)
6026 mips_gdbarch_init will take care of the rest. */
6027 gdbarch_info_init (&info
);
6028 gdbarch_update_p (info
);
6032 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6034 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6038 int ef_mips_32bitmode
;
6039 /* determine the ISA */
6040 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6058 /* determine the size of a pointer */
6059 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6060 fprintf_unfiltered (file
,
6061 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6063 fprintf_unfiltered (file
,
6064 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6066 fprintf_unfiltered (file
,
6067 "mips_dump_tdep: ef_mips_arch = %d\n",
6069 fprintf_unfiltered (file
,
6070 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6072 mips_abi_strings
[tdep
->mips_abi
]);
6073 fprintf_unfiltered (file
,
6074 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6075 mips_mask_address_p (),
6076 tdep
->default_mask_address_p
);
6078 fprintf_unfiltered (file
,
6079 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6080 FP_REGISTER_DOUBLE
);
6081 fprintf_unfiltered (file
,
6082 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6083 MIPS_DEFAULT_FPU_TYPE
,
6084 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6085 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6086 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6088 fprintf_unfiltered (file
,
6089 "mips_dump_tdep: MIPS_EABI = %d\n",
6091 fprintf_unfiltered (file
,
6092 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6093 MIPS_LAST_FP_ARG_REGNUM
,
6094 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
6095 fprintf_unfiltered (file
,
6096 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6098 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6099 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6100 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6102 fprintf_unfiltered (file
,
6103 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6104 MIPS_DEFAULT_SAVED_REGSIZE
);
6105 fprintf_unfiltered (file
,
6106 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6107 FP_REGISTER_DOUBLE
);
6108 fprintf_unfiltered (file
,
6109 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6110 MIPS_DEFAULT_STACK_ARGSIZE
);
6111 fprintf_unfiltered (file
,
6112 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6113 MIPS_STACK_ARGSIZE
);
6114 fprintf_unfiltered (file
,
6115 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
6117 fprintf_unfiltered (file
,
6118 "mips_dump_tdep: A0_REGNUM = %d\n",
6120 fprintf_unfiltered (file
,
6121 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6122 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6123 fprintf_unfiltered (file
,
6124 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6125 XSTRING (ATTACH_DETACH
));
6126 fprintf_unfiltered (file
,
6127 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6129 fprintf_unfiltered (file
,
6130 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
6131 fprintf_unfiltered (file
,
6132 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6134 fprintf_unfiltered (file
,
6135 "mips_dump_tdep: CPLUS_MARKER = %c\n",
6137 fprintf_unfiltered (file
,
6138 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
6139 XSTRING (DO_REGISTERS_INFO
));
6140 fprintf_unfiltered (file
,
6141 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6142 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6143 fprintf_unfiltered (file
,
6144 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6145 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6146 fprintf_unfiltered (file
,
6147 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6149 fprintf_unfiltered (file
,
6150 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6152 fprintf_unfiltered (file
,
6153 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6154 FIRST_EMBED_REGNUM
);
6155 fprintf_unfiltered (file
,
6156 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6158 fprintf_unfiltered (file
,
6159 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
6160 GDB_TARGET_IS_MIPS64
);
6161 fprintf_unfiltered (file
,
6162 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
6163 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
6164 fprintf_unfiltered (file
,
6165 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
6166 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
6167 fprintf_unfiltered (file
,
6168 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
6170 fprintf_unfiltered (file
,
6171 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
6172 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
6173 fprintf_unfiltered (file
,
6174 "mips_dump_tdep: HI_REGNUM = %d\n",
6176 fprintf_unfiltered (file
,
6177 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
6178 fprintf_unfiltered (file
,
6179 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
6180 fprintf_unfiltered (file
,
6181 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6182 XSTRING (IGNORE_HELPER_CALL (PC
)));
6183 fprintf_unfiltered (file
,
6184 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6185 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6186 fprintf_unfiltered (file
,
6187 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6188 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6189 fprintf_unfiltered (file
,
6190 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
6191 fprintf_unfiltered (file
,
6192 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6194 fprintf_unfiltered (file
,
6195 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
6196 fprintf_unfiltered (file
,
6197 "mips_dump_tdep: LO_REGNUM = %d\n",
6199 #ifdef MACHINE_CPROC_FP_OFFSET
6200 fprintf_unfiltered (file
,
6201 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6202 MACHINE_CPROC_FP_OFFSET
);
6204 #ifdef MACHINE_CPROC_PC_OFFSET
6205 fprintf_unfiltered (file
,
6206 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6207 MACHINE_CPROC_PC_OFFSET
);
6209 #ifdef MACHINE_CPROC_SP_OFFSET
6210 fprintf_unfiltered (file
,
6211 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6212 MACHINE_CPROC_SP_OFFSET
);
6214 fprintf_unfiltered (file
,
6215 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
6216 fprintf_unfiltered (file
,
6217 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
6218 fprintf_unfiltered (file
,
6219 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6221 fprintf_unfiltered (file
,
6222 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
6223 fprintf_unfiltered (file
,
6224 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6225 fprintf_unfiltered (file
,
6226 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6227 fprintf_unfiltered (file
,
6228 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6232 MIPS_LAST_ARG_REGNUM
,
6233 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6234 fprintf_unfiltered (file
,
6235 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6237 fprintf_unfiltered (file
,
6238 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6239 fprintf_unfiltered (file
,
6240 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6241 MIPS_SAVED_REGSIZE
);
6242 fprintf_unfiltered (file
,
6243 "mips_dump_tdep: OP_LDFPR = used?\n");
6244 fprintf_unfiltered (file
,
6245 "mips_dump_tdep: OP_LDGPR = used?\n");
6246 fprintf_unfiltered (file
,
6247 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
6248 fprintf_unfiltered (file
,
6249 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
6250 fprintf_unfiltered (file
,
6251 "mips_dump_tdep: PRID_REGNUM = %d\n",
6253 fprintf_unfiltered (file
,
6254 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
6255 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
6256 fprintf_unfiltered (file
,
6257 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6258 fprintf_unfiltered (file
,
6259 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6260 fprintf_unfiltered (file
,
6261 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6262 fprintf_unfiltered (file
,
6263 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6264 fprintf_unfiltered (file
,
6265 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6266 fprintf_unfiltered (file
,
6267 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6268 fprintf_unfiltered (file
,
6269 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6270 fprintf_unfiltered (file
,
6271 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6272 fprintf_unfiltered (file
,
6273 "mips_dump_tdep: PROC_PC_REG = function?\n");
6274 fprintf_unfiltered (file
,
6275 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6276 fprintf_unfiltered (file
,
6277 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6278 fprintf_unfiltered (file
,
6279 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6280 fprintf_unfiltered (file
,
6281 "mips_dump_tdep: PS_REGNUM = %d\n",
6283 fprintf_unfiltered (file
,
6284 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
6286 fprintf_unfiltered (file
,
6287 "mips_dump_tdep: RA_REGNUM = %d\n",
6289 fprintf_unfiltered (file
,
6290 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
6291 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
6292 fprintf_unfiltered (file
,
6293 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
6294 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
6295 fprintf_unfiltered (file
,
6296 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
6297 fprintf_unfiltered (file
,
6298 "mips_dump_tdep: ROUND_DOWN = function?\n");
6299 fprintf_unfiltered (file
,
6300 "mips_dump_tdep: ROUND_UP = function?\n");
6302 fprintf_unfiltered (file
,
6303 "mips_dump_tdep: SAVED_BYTES = %d\n",
6307 fprintf_unfiltered (file
,
6308 "mips_dump_tdep: SAVED_FP = %d\n",
6312 fprintf_unfiltered (file
,
6313 "mips_dump_tdep: SAVED_PC = %d\n",
6316 fprintf_unfiltered (file
,
6317 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6318 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6319 fprintf_unfiltered (file
,
6320 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6321 fprintf_unfiltered (file
,
6322 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6324 fprintf_unfiltered (file
,
6325 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6326 SIGFRAME_FPREGSAVE_OFF
);
6327 fprintf_unfiltered (file
,
6328 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6330 fprintf_unfiltered (file
,
6331 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6332 SIGFRAME_REGSAVE_OFF
);
6333 fprintf_unfiltered (file
,
6334 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6336 fprintf_unfiltered (file
,
6337 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6338 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6339 fprintf_unfiltered (file
,
6340 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6341 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6342 fprintf_unfiltered (file
,
6343 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6344 SOFTWARE_SINGLE_STEP_P ());
6345 fprintf_unfiltered (file
,
6346 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6347 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6348 #ifdef STACK_END_ADDR
6349 fprintf_unfiltered (file
,
6350 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6353 fprintf_unfiltered (file
,
6354 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6355 XSTRING (STEP_SKIPS_DELAY (PC
)));
6356 fprintf_unfiltered (file
,
6357 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6358 STEP_SKIPS_DELAY_P
);
6359 fprintf_unfiltered (file
,
6360 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6361 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6362 fprintf_unfiltered (file
,
6363 "mips_dump_tdep: T9_REGNUM = %d\n",
6365 fprintf_unfiltered (file
,
6366 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6367 fprintf_unfiltered (file
,
6368 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6369 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6370 fprintf_unfiltered (file
,
6371 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6372 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6373 fprintf_unfiltered (file
,
6374 "mips_dump_tdep: TARGET_MIPS = used?\n");
6375 fprintf_unfiltered (file
,
6376 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
6377 XSTRING (TM_PRINT_INSN_MACH
));
6379 fprintf_unfiltered (file
,
6380 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6381 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6384 fprintf_unfiltered (file
,
6385 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6388 #ifdef TRACE_FLAVOR_SIZE
6389 fprintf_unfiltered (file
,
6390 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6394 fprintf_unfiltered (file
,
6395 "mips_dump_tdep: TRACE_SET # %s\n",
6396 XSTRING (TRACE_SET (X
,STATE
)));
6398 fprintf_unfiltered (file
,
6399 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
6400 #ifdef UNUSED_REGNUM
6401 fprintf_unfiltered (file
,
6402 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6405 fprintf_unfiltered (file
,
6406 "mips_dump_tdep: V0_REGNUM = %d\n",
6408 fprintf_unfiltered (file
,
6409 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6410 (long) VM_MIN_ADDRESS
);
6412 fprintf_unfiltered (file
,
6413 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
6416 fprintf_unfiltered (file
,
6417 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6419 fprintf_unfiltered (file
,
6420 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6423 fprintf_unfiltered (file
,
6424 "mips_dump_tdep: OS ABI = %s\n",
6425 gdbarch_osabi_name (tdep
->osabi
));
6429 _initialize_mips_tdep (void)
6431 static struct cmd_list_element
*mipsfpulist
= NULL
;
6432 struct cmd_list_element
*c
;
6434 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6435 if (MIPS_ABI_LAST
+ 1
6436 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6437 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6439 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6440 if (!tm_print_insn
) /* Someone may have already set it */
6441 tm_print_insn
= gdb_print_insn_mips
;
6443 /* Add root prefix command for all "set mips"/"show mips" commands */
6444 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6445 "Various MIPS specific commands.",
6446 &setmipscmdlist
, "set mips ", 0, &setlist
);
6448 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6449 "Various MIPS specific commands.",
6450 &showmipscmdlist
, "show mips ", 0, &showlist
);
6452 /* Allow the user to override the saved register size. */
6453 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6456 &mips_saved_regsize_string
, "\
6457 Set size of general purpose registers saved on the stack.\n\
6458 This option can be set to one of:\n\
6459 32 - Force GDB to treat saved GP registers as 32-bit\n\
6460 64 - Force GDB to treat saved GP registers as 64-bit\n\
6461 auto - Allow GDB to use the target's default setting or autodetect the\n\
6462 saved GP register size from information contained in the executable.\n\
6467 /* Allow the user to override the argument stack size. */
6468 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6471 &mips_stack_argsize_string
, "\
6472 Set the amount of stack space reserved for each argument.\n\
6473 This option can be set to one of:\n\
6474 32 - Force GDB to allocate 32-bit chunks per argument\n\
6475 64 - Force GDB to allocate 64-bit chunks per argument\n\
6476 auto - Allow GDB to determine the correct setting from the current\n\
6477 target and executable (default)",
6481 /* Allow the user to override the ABI. */
6482 c
= add_set_enum_cmd
6483 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6484 "Set the ABI used by this program.\n"
6485 "This option can be set to one of:\n"
6486 " auto - the default ABI associated with the current binary\n"
6494 add_show_from_set (c
, &showmipscmdlist
);
6495 set_cmd_sfunc (c
, mips_abi_update
);
6497 /* Let the user turn off floating point and set the fence post for
6498 heuristic_proc_start. */
6500 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6501 "Set use of MIPS floating-point coprocessor.",
6502 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6503 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6504 "Select single-precision MIPS floating-point coprocessor.",
6506 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6507 "Select double-precision MIPS floating-point coprocessor.",
6509 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6510 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6511 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6512 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6513 "Select no MIPS floating-point coprocessor.",
6515 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6516 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6517 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6518 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6519 "Select MIPS floating-point coprocessor automatically.",
6521 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6522 "Show current use of MIPS floating-point coprocessor target.",
6525 /* We really would like to have both "0" and "unlimited" work, but
6526 command.c doesn't deal with that. So make it a var_zinteger
6527 because the user can always use "999999" or some such for unlimited. */
6528 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6529 (char *) &heuristic_fence_post
,
6531 Set the distance searched for the start of a function.\n\
6532 If you are debugging a stripped executable, GDB needs to search through the\n\
6533 program for the start of a function. This command sets the distance of the\n\
6534 search. The only need to set it is when debugging a stripped executable.",
6536 /* We need to throw away the frame cache when we set this, since it
6537 might change our ability to get backtraces. */
6538 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6539 add_show_from_set (c
, &showlist
);
6541 /* Allow the user to control whether the upper bits of 64-bit
6542 addresses should be zeroed. */
6543 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6544 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6545 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6546 allow GDB to determine the correct value.\n", "\
6547 Show zeroing of upper 32 bits of 64-bit addresses.",
6548 NULL
, show_mask_address
,
6549 &setmipscmdlist
, &showmipscmdlist
);
6551 /* Allow the user to control the size of 32 bit registers within the
6552 raw remote packet. */
6553 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6556 (char *)&mips64_transfers_32bit_regs_p
, "\
6557 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6558 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6559 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6560 64 bits for others. Use \"off\" to disable compatibility mode",
6564 /* Debug this files internals. */
6565 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6566 &mips_debug
, "Set mips debugging.\n\
6567 When non-zero, mips specific debugging is enabled.", &setdebuglist
),