1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
62 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
64 /* A useful bit in the CP0 status register (PS_REGNUM). */
65 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
66 #define ST0_FR (1 << 26)
68 /* The sizes of floating point registers. */
72 MIPS_FPU_SINGLE_REGSIZE
= 4,
73 MIPS_FPU_DOUBLE_REGSIZE
= 8
77 static const char *mips_abi_string
;
79 static const char *mips_abi_strings
[] = {
90 struct frame_extra_info
92 mips_extra_func_info_t proc_desc
;
96 /* Various MIPS ISA options (related to stack analysis) can be
97 overridden dynamically. Establish an enum/array for managing
100 static const char size_auto
[] = "auto";
101 static const char size_32
[] = "32";
102 static const char size_64
[] = "64";
104 static const char *size_enums
[] = {
111 /* Some MIPS boards don't support floating point while others only
112 support single-precision floating-point operations. */
116 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
117 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
118 MIPS_FPU_NONE
/* No floating point. */
121 #ifndef MIPS_DEFAULT_FPU_TYPE
122 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
124 static int mips_fpu_type_auto
= 1;
125 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
127 static int mips_debug
= 0;
129 /* MIPS specific per-architecture information */
132 /* from the elf header */
136 enum mips_abi mips_abi
;
137 enum mips_abi found_abi
;
138 enum mips_fpu_type mips_fpu_type
;
139 int mips_last_arg_regnum
;
140 int mips_last_fp_arg_regnum
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
154 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
160 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
161 They are implemented as a pair of 64bit doubles where the high
162 part holds the result of the operation rounded to double, and
163 the low double holds the difference between the exact result and
164 the rounded result. So "high" + "low" contains the result with
165 added precision. Unfortunately, the floatformat structure used
166 by GDB is not powerful enough to describe this format. As a temporary
167 measure, we define a 128bit floatformat that only uses the high part.
168 We lose a bit of precision but that's probably the best we can do
169 for now with the current infrastructure. */
171 static const struct floatformat floatformat_n32n64_long_double_big
=
173 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
174 floatformat_intbit_no
,
175 "floatformat_ieee_double_big",
176 n32n64_floatformat_always_valid
179 const struct mips_regnum
*
180 mips_regnum (struct gdbarch
*gdbarch
)
182 return gdbarch_tdep (gdbarch
)->regnum
;
186 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
188 return mips_regnum (gdbarch
)->fp0
+ 12;
191 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
192 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
194 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
196 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
198 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
200 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
201 functions to test, set, or clear bit 0 of addresses. */
204 is_mips16_addr (CORE_ADDR addr
)
210 make_mips16_addr (CORE_ADDR addr
)
216 unmake_mips16_addr (CORE_ADDR addr
)
218 return ((addr
) & ~1);
221 /* Return the contents of register REGNUM as a signed integer. */
224 read_signed_register (int regnum
)
226 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
227 deprecated_read_register_gen (regnum
, buf
);
228 return (extract_signed_integer
229 (buf
, register_size (current_gdbarch
, regnum
)));
233 read_signed_register_pid (int regnum
, ptid_t ptid
)
238 if (ptid_equal (ptid
, inferior_ptid
))
239 return read_signed_register (regnum
);
241 save_ptid
= inferior_ptid
;
243 inferior_ptid
= ptid
;
245 retval
= read_signed_register (regnum
);
247 inferior_ptid
= save_ptid
;
252 /* Return the MIPS ABI associated with GDBARCH. */
254 mips_abi (struct gdbarch
*gdbarch
)
256 return gdbarch_tdep (gdbarch
)->mips_abi
;
260 mips_isa_regsize (struct gdbarch
*gdbarch
)
262 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
263 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
266 /* Return the currently configured (or set) saved register size. */
268 static const char *mips_abi_regsize_string
= size_auto
;
271 mips_abi_regsize (struct gdbarch
*gdbarch
)
273 if (mips_abi_regsize_string
== size_auto
)
274 switch (mips_abi (gdbarch
))
276 case MIPS_ABI_EABI32
:
282 case MIPS_ABI_EABI64
:
284 case MIPS_ABI_UNKNOWN
:
287 internal_error (__FILE__
, __LINE__
, "bad switch");
289 else if (mips_abi_regsize_string
== size_64
)
291 else /* if (mips_abi_regsize_string == size_32) */
295 /* Functions for setting and testing a bit in a minimal symbol that
296 marks it as 16-bit function. The MSB of the minimal symbol's
297 "info" field is used for this purpose.
299 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
300 i.e. refers to a 16-bit function, and sets a "special" bit in a
301 minimal symbol to mark it as a 16-bit function
303 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
306 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
308 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
310 MSYMBOL_INFO (msym
) = (char *)
311 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
312 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
317 msymbol_is_special (struct minimal_symbol
*msym
)
319 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
322 /* XFER a value from the big/little/left end of the register.
323 Depending on the size of the value it might occupy the entire
324 register or just part of it. Make an allowance for this, aligning
325 things accordingly. */
328 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
329 enum bfd_endian endian
, bfd_byte
* in
,
330 const bfd_byte
* out
, int buf_offset
)
333 gdb_assert (reg_num
>= NUM_REGS
);
334 /* Need to transfer the left or right part of the register, based on
335 the targets byte order. */
339 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
341 case BFD_ENDIAN_LITTLE
:
344 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
348 internal_error (__FILE__
, __LINE__
, "bad switch");
351 fprintf_unfiltered (gdb_stderr
,
352 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
353 reg_num
, reg_offset
, buf_offset
, length
);
354 if (mips_debug
&& out
!= NULL
)
357 fprintf_unfiltered (gdb_stdlog
, "out ");
358 for (i
= 0; i
< length
; i
++)
359 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
362 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
365 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
367 if (mips_debug
&& in
!= NULL
)
370 fprintf_unfiltered (gdb_stdlog
, "in ");
371 for (i
= 0; i
< length
; i
++)
372 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
375 fprintf_unfiltered (gdb_stdlog
, "\n");
378 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
379 compatiblity mode. A return value of 1 means that we have
380 physical 64-bit registers, but should treat them as 32-bit registers. */
383 mips2_fp_compat (void)
385 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
387 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
392 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
393 in all the places we deal with FP registers. PR gdb/413. */
394 /* Otherwise check the FR bit in the status register - it controls
395 the FP compatiblity mode. If it is clear we are in compatibility
397 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
404 /* The amount of space reserved on the stack for registers. This is
405 different to MIPS_ABI_REGSIZE as it determines the alignment of
406 data allocated after the registers have run out. */
408 static const char *mips_stack_argsize_string
= size_auto
;
411 mips_stack_argsize (struct gdbarch
*gdbarch
)
413 if (mips_stack_argsize_string
== size_auto
)
414 return mips_abi_regsize (gdbarch
);
415 else if (mips_stack_argsize_string
== size_64
)
417 else /* if (mips_stack_argsize_string == size_32) */
421 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
424 struct frame_info
*, int);
425 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
428 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
430 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
432 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
434 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
435 struct frame_info
*next_frame
,
438 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
439 mips_extra_func_info_t proc_desc
);
441 static struct type
*mips_float_register_type (void);
442 static struct type
*mips_double_register_type (void);
444 /* The list of available "set mips " and "show mips " commands */
446 static struct cmd_list_element
*setmipscmdlist
= NULL
;
447 static struct cmd_list_element
*showmipscmdlist
= NULL
;
449 /* Integer registers 0 thru 31 are handled explicitly by
450 mips_register_name(). Processor specific registers 32 and above
451 are listed in the followign tables. */
454 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
458 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
459 "sr", "lo", "hi", "bad", "cause", "pc",
460 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
461 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
462 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
463 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
464 "fsr", "fir", "" /*"fp" */ , "",
465 "", "", "", "", "", "", "", "",
466 "", "", "", "", "", "", "", "",
469 /* Names of IDT R3041 registers. */
471 static const char *mips_r3041_reg_names
[] = {
472 "sr", "lo", "hi", "bad", "cause", "pc",
473 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
474 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
475 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
476 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
477 "fsr", "fir", "", /*"fp" */ "",
478 "", "", "bus", "ccfg", "", "", "", "",
479 "", "", "port", "cmp", "", "", "epc", "prid",
482 /* Names of tx39 registers. */
484 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
485 "sr", "lo", "hi", "bad", "cause", "pc",
486 "", "", "", "", "", "", "", "",
487 "", "", "", "", "", "", "", "",
488 "", "", "", "", "", "", "", "",
489 "", "", "", "", "", "", "", "",
491 "", "", "", "", "", "", "", "",
492 "", "", "config", "cache", "debug", "depc", "epc", ""
495 /* Names of IRIX registers. */
496 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
497 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
498 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
499 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
500 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
501 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
505 /* Return the name of the register corresponding to REGNO. */
507 mips_register_name (int regno
)
509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
510 /* GPR names for all ABIs other than n32/n64. */
511 static char *mips_gpr_names
[] = {
512 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
513 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
514 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
515 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
518 /* GPR names for n32 and n64 ABIs. */
519 static char *mips_n32_n64_gpr_names
[] = {
520 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
521 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
522 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
523 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
526 enum mips_abi abi
= mips_abi (current_gdbarch
);
528 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
529 don't make the raw register names visible. */
530 int rawnum
= regno
% NUM_REGS
;
531 if (regno
< NUM_REGS
)
534 /* The MIPS integer registers are always mapped from 0 to 31. The
535 names of the registers (which reflects the conventions regarding
536 register use) vary depending on the ABI. */
537 if (0 <= rawnum
&& rawnum
< 32)
539 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
540 return mips_n32_n64_gpr_names
[rawnum
];
542 return mips_gpr_names
[rawnum
];
544 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
546 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
547 return tdep
->mips_processor_reg_names
[rawnum
- 32];
550 internal_error (__FILE__
, __LINE__
,
551 "mips_register_name: bad register number %d", rawnum
);
554 /* Return the groups that a MIPS register can be categorised into. */
557 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
558 struct reggroup
*reggroup
)
563 int rawnum
= regnum
% NUM_REGS
;
564 int pseudo
= regnum
/ NUM_REGS
;
565 if (reggroup
== all_reggroup
)
567 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
568 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
569 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
570 (gdbarch), as not all architectures are multi-arch. */
571 raw_p
= rawnum
< NUM_REGS
;
572 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
574 if (reggroup
== float_reggroup
)
575 return float_p
&& pseudo
;
576 if (reggroup
== vector_reggroup
)
577 return vector_p
&& pseudo
;
578 if (reggroup
== general_reggroup
)
579 return (!vector_p
&& !float_p
) && pseudo
;
580 /* Save the pseudo registers. Need to make certain that any code
581 extracting register values from a saved register cache also uses
583 if (reggroup
== save_reggroup
)
584 return raw_p
&& pseudo
;
585 /* Restore the same pseudo register. */
586 if (reggroup
== restore_reggroup
)
587 return raw_p
&& pseudo
;
591 /* Map the symbol table registers which live in the range [1 *
592 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
593 registers. Take care of alignment and size problems. */
596 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
597 int cookednum
, void *buf
)
599 int rawnum
= cookednum
% NUM_REGS
;
600 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
601 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
602 regcache_raw_read (regcache
, rawnum
, buf
);
603 else if (register_size (gdbarch
, rawnum
) >
604 register_size (gdbarch
, cookednum
))
606 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
607 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
608 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
610 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
613 internal_error (__FILE__
, __LINE__
, "bad register size");
617 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
618 struct regcache
*regcache
, int cookednum
,
621 int rawnum
= cookednum
% NUM_REGS
;
622 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
623 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
624 regcache_raw_write (regcache
, rawnum
, buf
);
625 else if (register_size (gdbarch
, rawnum
) >
626 register_size (gdbarch
, cookednum
))
628 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
629 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
630 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
632 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
635 internal_error (__FILE__
, __LINE__
, "bad register size");
638 /* Table to translate MIPS16 register field to actual register number. */
639 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
641 /* Heuristic_proc_start may hunt through the text section for a long
642 time across a 2400 baud serial line. Allows the user to limit this
645 static unsigned int heuristic_fence_post
= 0;
647 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
648 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
649 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
650 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
651 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
652 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
653 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
654 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
655 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
656 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
657 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
658 this will corrupt pdr.iline. Fortunately we don't use it. */
659 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
660 #define _PROC_MAGIC_ 0x0F0F0F0F
661 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
662 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
664 struct linked_proc_info
666 struct mips_extra_func_info info
;
667 struct linked_proc_info
*next
;
669 *linked_proc_desc_table
= NULL
;
671 /* Number of bytes of storage in the actual machine representation for
672 register N. NOTE: This defines the pseudo register type so need to
673 rebuild the architecture vector. */
675 static int mips64_transfers_32bit_regs_p
= 0;
678 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
679 struct cmd_list_element
*c
)
681 struct gdbarch_info info
;
682 gdbarch_info_init (&info
);
683 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
684 instead of relying on globals. Doing that would let generic code
685 handle the search for this specific architecture. */
686 if (!gdbarch_update_p (info
))
688 mips64_transfers_32bit_regs_p
= 0;
689 error ("32-bit compatibility mode not supported");
693 /* Convert to/from a register and the corresponding memory value. */
696 mips_convert_register_p (int regnum
, struct type
*type
)
698 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
699 && register_size (current_gdbarch
, regnum
) == 4
700 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
701 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
702 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
706 mips_register_to_value (struct frame_info
*frame
, int regnum
,
707 struct type
*type
, void *to
)
709 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
710 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
714 mips_value_to_register (struct frame_info
*frame
, int regnum
,
715 struct type
*type
, const void *from
)
717 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
718 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
721 /* Return the GDB type object for the "standard" data type of data in
725 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
727 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
728 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
729 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
731 /* The floating-point registers raw, or cooked, always match
732 mips_isa_regsize(), and also map 1:1, byte for byte. */
733 switch (gdbarch_byte_order (gdbarch
))
736 if (mips_isa_regsize (gdbarch
) == 4)
737 return builtin_type_ieee_single_big
;
739 return builtin_type_ieee_double_big
;
740 case BFD_ENDIAN_LITTLE
:
741 if (mips_isa_regsize (gdbarch
) == 4)
742 return builtin_type_ieee_single_little
;
744 return builtin_type_ieee_double_little
;
745 case BFD_ENDIAN_UNKNOWN
:
747 internal_error (__FILE__
, __LINE__
, "bad switch");
750 else if (regnum
< NUM_REGS
)
752 /* The raw or ISA registers. These are all sized according to
754 if (mips_isa_regsize (gdbarch
) == 4)
755 return builtin_type_int32
;
757 return builtin_type_int64
;
761 /* The cooked or ABI registers. These are sized according to
762 the ABI (with a few complications). */
763 if (regnum
>= (NUM_REGS
764 + mips_regnum (current_gdbarch
)->fp_control_status
)
765 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
766 /* The pseudo/cooked view of the embedded registers is always
767 32-bit. The raw view is handled below. */
768 return builtin_type_int32
;
769 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
770 /* The target, while possibly using a 64-bit register buffer,
771 is only transfering 32-bits of each integer register.
772 Reflect this in the cooked/pseudo (ABI) register value. */
773 return builtin_type_int32
;
774 else if (mips_abi_regsize (gdbarch
) == 4)
775 /* The ABI is restricted to 32-bit registers (the ISA could be
777 return builtin_type_int32
;
780 return builtin_type_int64
;
784 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
789 return read_signed_register (MIPS_SP_REGNUM
);
792 /* Should the upper word of 64-bit addresses be zeroed? */
793 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
796 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
798 switch (mask_address_var
)
800 case AUTO_BOOLEAN_TRUE
:
802 case AUTO_BOOLEAN_FALSE
:
805 case AUTO_BOOLEAN_AUTO
:
806 return tdep
->default_mask_address_p
;
808 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
814 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
816 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
817 switch (mask_address_var
)
819 case AUTO_BOOLEAN_TRUE
:
820 printf_filtered ("The 32 bit mips address mask is enabled\n");
822 case AUTO_BOOLEAN_FALSE
:
823 printf_filtered ("The 32 bit mips address mask is disabled\n");
825 case AUTO_BOOLEAN_AUTO
:
827 ("The 32 bit address mask is set automatically. Currently %s\n",
828 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
831 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
836 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
839 pc_is_mips16 (bfd_vma memaddr
)
841 struct minimal_symbol
*sym
;
843 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
844 if (is_mips16_addr (memaddr
))
847 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
848 the high bit of the info field. Use this to decide if the function is
849 MIPS16 or normal MIPS. */
850 sym
= lookup_minimal_symbol_by_pc (memaddr
);
852 return msymbol_is_special (sym
);
857 /* MIPS believes that the PC has a sign extended value. Perhaps the
858 all registers should be sign extended for simplicity? */
861 mips_read_pc (ptid_t ptid
)
863 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
867 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
869 return frame_unwind_register_signed (next_frame
,
870 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
873 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
874 dummy frame. The frame ID's base needs to match the TOS value
875 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
878 static struct frame_id
879 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
881 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
882 frame_pc_unwind (next_frame
));
886 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
888 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
891 /* This returns the PC of the first inst after the prologue. If we can't
892 find the prologue, then return 0. */
895 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
897 struct symtab_and_line sal
;
898 CORE_ADDR func_addr
, func_end
;
900 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
901 to read the stack pointer from the current machine state, because
902 the current machine state has nothing to do with the information
903 we need from the proc_desc; and the process may or may not exist
906 proc_desc
= find_proc_desc (pc
, NULL
, 0);
910 /* If function is frameless, then we need to do it the hard way. I
911 strongly suspect that frameless always means prologueless... */
912 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
913 && PROC_FRAME_OFFSET (proc_desc
) == 0)
917 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
918 return 0; /* Unknown */
920 sal
= find_pc_line (func_addr
, 0);
922 if (sal
.end
< func_end
)
925 /* The line after the prologue is after the end of the function. In this
926 case, tell the caller to find the prologue the hard way. */
931 /* Decode a MIPS32 instruction that saves a register in the stack, and
932 set the appropriate bit in the general register mask or float register mask
933 to indicate which register is saved. This is a helper function
934 for mips_find_saved_regs. */
937 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
938 unsigned long *float_mask
)
942 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
943 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
944 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
946 /* It might be possible to use the instruction to
947 find the offset, rather than the code below which
948 is based on things being in a certain order in the
949 frame, but figuring out what the instruction's offset
950 is relative to might be a little tricky. */
951 reg
= (inst
& 0x001f0000) >> 16;
952 *gen_mask
|= (1 << reg
);
954 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
955 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
956 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
959 reg
= ((inst
& 0x001f0000) >> 16);
960 *float_mask
|= (1 << reg
);
964 /* Decode a MIPS16 instruction that saves a register in the stack, and
965 set the appropriate bit in the general register or float register mask
966 to indicate which register is saved. This is a helper function
967 for mips_find_saved_regs. */
970 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
972 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
974 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
975 *gen_mask
|= (1 << reg
);
977 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
979 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
980 *gen_mask
|= (1 << reg
);
982 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
983 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
984 *gen_mask
|= (1 << RA_REGNUM
);
988 /* Fetch and return instruction from the specified location. If the PC
989 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
992 mips_fetch_instruction (CORE_ADDR addr
)
994 char buf
[MIPS_INSTLEN
];
998 if (pc_is_mips16 (addr
))
1000 instlen
= MIPS16_INSTLEN
;
1001 addr
= unmake_mips16_addr (addr
);
1004 instlen
= MIPS_INSTLEN
;
1005 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1007 memory_error (status
, addr
);
1008 return extract_unsigned_integer (buf
, instlen
);
1012 mips16_fetch_instruction (CORE_ADDR addr
)
1014 char buf
[MIPS_INSTLEN
];
1018 instlen
= MIPS16_INSTLEN
;
1019 addr
= unmake_mips16_addr (addr
);
1020 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1022 memory_error (status
, addr
);
1023 return extract_unsigned_integer (buf
, instlen
);
1027 mips32_fetch_instruction (CORE_ADDR addr
)
1029 char buf
[MIPS_INSTLEN
];
1032 instlen
= MIPS_INSTLEN
;
1033 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1035 memory_error (status
, addr
);
1036 return extract_unsigned_integer (buf
, instlen
);
1040 /* These the fields of 32 bit mips instructions */
1041 #define mips32_op(x) (x >> 26)
1042 #define itype_op(x) (x >> 26)
1043 #define itype_rs(x) ((x >> 21) & 0x1f)
1044 #define itype_rt(x) ((x >> 16) & 0x1f)
1045 #define itype_immediate(x) (x & 0xffff)
1047 #define jtype_op(x) (x >> 26)
1048 #define jtype_target(x) (x & 0x03ffffff)
1050 #define rtype_op(x) (x >> 26)
1051 #define rtype_rs(x) ((x >> 21) & 0x1f)
1052 #define rtype_rt(x) ((x >> 16) & 0x1f)
1053 #define rtype_rd(x) ((x >> 11) & 0x1f)
1054 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1055 #define rtype_funct(x) (x & 0x3f)
1058 mips32_relative_offset (unsigned long inst
)
1061 x
= itype_immediate (inst
);
1062 if (x
& 0x8000) /* sign bit set */
1064 x
|= 0xffff0000; /* sign extension */
1070 /* Determine whate to set a single step breakpoint while considering
1071 branch prediction */
1073 mips32_next_pc (CORE_ADDR pc
)
1077 inst
= mips_fetch_instruction (pc
);
1078 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1080 if (itype_op (inst
) >> 2 == 5)
1081 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1083 op
= (itype_op (inst
) & 0x03);
1093 goto greater_branch
;
1098 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1099 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1101 int tf
= itype_rt (inst
) & 0x01;
1102 int cnum
= itype_rt (inst
) >> 2;
1104 read_signed_register (mips_regnum (current_gdbarch
)->
1106 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1108 if (((cond
>> cnum
) & 0x01) == tf
)
1109 pc
+= mips32_relative_offset (inst
) + 4;
1114 pc
+= 4; /* Not a branch, next instruction is easy */
1117 { /* This gets way messy */
1119 /* Further subdivide into SPECIAL, REGIMM and other */
1120 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1122 case 0: /* SPECIAL */
1123 op
= rtype_funct (inst
);
1128 /* Set PC to that address */
1129 pc
= read_signed_register (rtype_rs (inst
));
1135 break; /* end SPECIAL */
1136 case 1: /* REGIMM */
1138 op
= itype_rt (inst
); /* branch condition */
1143 case 16: /* BLTZAL */
1144 case 18: /* BLTZALL */
1146 if (read_signed_register (itype_rs (inst
)) < 0)
1147 pc
+= mips32_relative_offset (inst
) + 4;
1149 pc
+= 8; /* after the delay slot */
1153 case 17: /* BGEZAL */
1154 case 19: /* BGEZALL */
1155 if (read_signed_register (itype_rs (inst
)) >= 0)
1156 pc
+= mips32_relative_offset (inst
) + 4;
1158 pc
+= 8; /* after the delay slot */
1160 /* All of the other instructions in the REGIMM category */
1165 break; /* end REGIMM */
1170 reg
= jtype_target (inst
) << 2;
1171 /* Upper four bits get never changed... */
1172 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1175 /* FIXME case JALX : */
1178 reg
= jtype_target (inst
) << 2;
1179 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1180 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1182 break; /* The new PC will be alternate mode */
1183 case 4: /* BEQ, BEQL */
1185 if (read_signed_register (itype_rs (inst
)) ==
1186 read_signed_register (itype_rt (inst
)))
1187 pc
+= mips32_relative_offset (inst
) + 4;
1191 case 5: /* BNE, BNEL */
1193 if (read_signed_register (itype_rs (inst
)) !=
1194 read_signed_register (itype_rt (inst
)))
1195 pc
+= mips32_relative_offset (inst
) + 4;
1199 case 6: /* BLEZ, BLEZL */
1200 if (read_signed_register (itype_rs (inst
) <= 0))
1201 pc
+= mips32_relative_offset (inst
) + 4;
1207 greater_branch
: /* BGTZ, BGTZL */
1208 if (read_signed_register (itype_rs (inst
) > 0))
1209 pc
+= mips32_relative_offset (inst
) + 4;
1216 } /* mips32_next_pc */
1218 /* Decoding the next place to set a breakpoint is irregular for the
1219 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1220 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1221 We dont want to set a single step instruction on the extend instruction
1225 /* Lots of mips16 instruction formats */
1226 /* Predicting jumps requires itype,ritype,i8type
1227 and their extensions extItype,extritype,extI8type
1229 enum mips16_inst_fmts
1231 itype
, /* 0 immediate 5,10 */
1232 ritype
, /* 1 5,3,8 */
1233 rrtype
, /* 2 5,3,3,5 */
1234 rritype
, /* 3 5,3,3,5 */
1235 rrrtype
, /* 4 5,3,3,3,2 */
1236 rriatype
, /* 5 5,3,3,1,4 */
1237 shifttype
, /* 6 5,3,3,3,2 */
1238 i8type
, /* 7 5,3,8 */
1239 i8movtype
, /* 8 5,3,3,5 */
1240 i8mov32rtype
, /* 9 5,3,5,3 */
1241 i64type
, /* 10 5,3,8 */
1242 ri64type
, /* 11 5,3,3,5 */
1243 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1244 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1245 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1246 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1247 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1248 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1249 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1250 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1251 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1252 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1254 /* I am heaping all the fields of the formats into one structure and
1255 then, only the fields which are involved in instruction extension */
1259 unsigned int regx
; /* Function in i8 type */
1264 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1265 for the bits which make up the immediatate extension. */
1268 extended_offset (unsigned int extension
)
1271 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1273 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1275 value
|= extension
& 0x01f; /* extract 4:0 */
1279 /* Only call this function if you know that this is an extendable
1280 instruction, It wont malfunction, but why make excess remote memory references?
1281 If the immediate operands get sign extended or somthing, do it after
1282 the extension is performed.
1284 /* FIXME: Every one of these cases needs to worry about sign extension
1285 when the offset is to be used in relative addressing */
1289 fetch_mips_16 (CORE_ADDR pc
)
1292 pc
&= 0xfffffffe; /* clear the low order bit */
1293 target_read_memory (pc
, buf
, 2);
1294 return extract_unsigned_integer (buf
, 2);
1298 unpack_mips16 (CORE_ADDR pc
,
1299 unsigned int extension
,
1301 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1306 switch (insn_format
)
1313 value
= extended_offset (extension
);
1314 value
= value
<< 11; /* rom for the original value */
1315 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1319 value
= inst
& 0x7ff;
1320 /* FIXME : Consider sign extension */
1329 { /* A register identifier and an offset */
1330 /* Most of the fields are the same as I type but the
1331 immediate value is of a different length */
1335 value
= extended_offset (extension
);
1336 value
= value
<< 8; /* from the original instruction */
1337 value
|= inst
& 0xff; /* eleven bits from instruction */
1338 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1339 if (value
& 0x4000) /* test the sign bit , bit 26 */
1341 value
&= ~0x3fff; /* remove the sign bit */
1347 value
= inst
& 0xff; /* 8 bits */
1348 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1349 /* FIXME: Do sign extension , this format needs it */
1350 if (value
& 0x80) /* THIS CONFUSES ME */
1352 value
&= 0xef; /* remove the sign bit */
1362 unsigned long value
;
1363 unsigned int nexthalf
;
1364 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1365 value
= value
<< 16;
1366 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1374 internal_error (__FILE__
, __LINE__
, "bad switch");
1376 upk
->offset
= offset
;
1383 add_offset_16 (CORE_ADDR pc
, int offset
)
1385 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1389 extended_mips16_next_pc (CORE_ADDR pc
,
1390 unsigned int extension
, unsigned int insn
)
1392 int op
= (insn
>> 11);
1395 case 2: /* Branch */
1398 struct upk_mips16 upk
;
1399 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1400 offset
= upk
.offset
;
1406 pc
+= (offset
<< 1) + 2;
1409 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1411 struct upk_mips16 upk
;
1412 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1413 pc
= add_offset_16 (pc
, upk
.offset
);
1414 if ((insn
>> 10) & 0x01) /* Exchange mode */
1415 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1422 struct upk_mips16 upk
;
1424 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1425 reg
= read_signed_register (upk
.regx
);
1427 pc
+= (upk
.offset
<< 1) + 2;
1434 struct upk_mips16 upk
;
1436 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1437 reg
= read_signed_register (upk
.regx
);
1439 pc
+= (upk
.offset
<< 1) + 2;
1444 case 12: /* I8 Formats btez btnez */
1446 struct upk_mips16 upk
;
1448 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1449 /* upk.regx contains the opcode */
1450 reg
= read_signed_register (24); /* Test register is 24 */
1451 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1452 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1453 /* pc = add_offset_16(pc,upk.offset) ; */
1454 pc
+= (upk
.offset
<< 1) + 2;
1459 case 29: /* RR Formats JR, JALR, JALR-RA */
1461 struct upk_mips16 upk
;
1462 /* upk.fmt = rrtype; */
1467 upk
.regx
= (insn
>> 8) & 0x07;
1468 upk
.regy
= (insn
>> 5) & 0x07;
1476 break; /* Function return instruction */
1482 break; /* BOGUS Guess */
1484 pc
= read_signed_register (reg
);
1491 /* This is an instruction extension. Fetch the real instruction
1492 (which follows the extension) and decode things based on
1496 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1509 mips16_next_pc (CORE_ADDR pc
)
1511 unsigned int insn
= fetch_mips_16 (pc
);
1512 return extended_mips16_next_pc (pc
, 0, insn
);
1515 /* The mips_next_pc function supports single_step when the remote
1516 target monitor or stub is not developed enough to do a single_step.
1517 It works by decoding the current instruction and predicting where a
1518 branch will go. This isnt hard because all the data is available.
1519 The MIPS32 and MIPS16 variants are quite different */
1521 mips_next_pc (CORE_ADDR pc
)
1524 return mips16_next_pc (pc
);
1526 return mips32_next_pc (pc
);
1529 struct mips_frame_cache
1532 struct trad_frame_saved_reg
*saved_regs
;
1536 static struct mips_frame_cache
*
1537 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1539 mips_extra_func_info_t proc_desc
;
1540 struct mips_frame_cache
*cache
;
1541 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1542 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1543 /* r0 bit means kernel trap */
1545 /* What registers have been saved? Bitmasks. */
1546 unsigned long gen_mask
, float_mask
;
1548 if ((*this_cache
) != NULL
)
1549 return (*this_cache
);
1550 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1551 (*this_cache
) = cache
;
1552 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1554 /* Get the mdebug proc descriptor. */
1555 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1556 if (proc_desc
== NULL
)
1557 /* I'm not sure how/whether this can happen. Normally when we
1558 can't find a proc_desc, we "synthesize" one using
1559 heuristic_proc_desc and set the saved_regs right away. */
1562 /* Extract the frame's base. */
1563 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1564 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1566 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1567 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1568 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1570 /* In any frame other than the innermost or a frame interrupted by a
1571 signal, we assume that all registers have been saved. This
1572 assumes that all register saves in a function happen before the
1573 first function call. */
1574 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1575 /* Not sure exactly what kernel_trap means, but if it means the
1576 kernel saves the registers without a prologue doing it, we
1577 better not examine the prologue to see whether registers
1578 have been saved yet. */
1581 /* We need to figure out whether the registers that the
1582 proc_desc claims are saved have been saved yet. */
1586 /* Bitmasks; set if we have found a save for the register. */
1587 unsigned long gen_save_found
= 0;
1588 unsigned long float_save_found
= 0;
1591 /* If the address is odd, assume this is MIPS16 code. */
1592 addr
= PROC_LOW_ADDR (proc_desc
);
1593 mips16
= pc_is_mips16 (addr
);
1595 /* Scan through this function's instructions preceding the
1596 current PC, and look for those that save registers. */
1597 while (addr
< frame_pc_unwind (next_frame
))
1601 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1603 addr
+= MIPS16_INSTLEN
;
1607 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1608 &gen_save_found
, &float_save_found
);
1609 addr
+= MIPS_INSTLEN
;
1612 gen_mask
= gen_save_found
;
1613 float_mask
= float_save_found
;
1616 /* Fill in the offsets for the registers which gen_mask says were
1619 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1622 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1623 if (gen_mask
& 0x80000000)
1625 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1626 reg_position
-= mips_abi_regsize (gdbarch
);
1630 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1631 order of that normally used by gcc. Therefore, we have to fetch
1632 the first instruction of the function, and if it's an entry
1633 instruction that saves $s0 or $s1, correct their saved addresses. */
1634 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1636 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1637 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1641 int sreg_count
= (inst
>> 6) & 3;
1643 /* Check if the ra register was pushed on the stack. */
1644 CORE_ADDR reg_position
= (cache
->base
1645 + PROC_REG_OFFSET (proc_desc
));
1647 reg_position
-= mips_abi_regsize (gdbarch
);
1649 /* Check if the s0 and s1 registers were pushed on the
1651 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1653 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1655 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1656 reg_position
-= mips_abi_regsize (gdbarch
);
1661 /* Fill in the offsets for the registers which float_mask says were
1664 CORE_ADDR reg_position
= (cache
->base
1665 + PROC_FREG_OFFSET (proc_desc
));
1667 /* Fill in the offsets for the float registers which float_mask
1669 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1670 if (float_mask
& 0x80000000)
1672 if (mips_abi_regsize (gdbarch
) == 4
1673 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1675 /* On a big endian 32 bit ABI, floating point registers
1676 are paired to form doubles such that the most
1677 significant part is in $f[N+1] and the least
1678 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1679 registers are also spilled as a pair and stored as a
1682 When little-endian the least significant part is
1683 stored first leading to the memory order $f[N] and
1686 Unfortunately, when big-endian the most significant
1687 part of the double is stored first, and the least
1688 significant is stored second. This leads to the
1689 registers being ordered in memory as firt $f[N+1] and
1692 For the big-endian case make certain that the
1693 addresses point at the correct (swapped) locations
1694 $f[N] and $f[N+1] pair (keep in mind that
1695 reg_position is decremented each time through the
1698 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1699 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1701 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1702 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1705 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1706 .addr
= reg_position
;
1707 reg_position
-= mips_abi_regsize (gdbarch
);
1710 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1711 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1714 /* SP_REGNUM, contains the value and not the address. */
1715 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1717 return (*this_cache
);
1721 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1722 struct frame_id
*this_id
)
1724 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1726 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1730 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1732 int regnum
, int *optimizedp
,
1733 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1734 int *realnump
, void *valuep
)
1736 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1738 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1739 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1742 static const struct frame_unwind mips_mdebug_frame_unwind
=
1745 mips_mdebug_frame_this_id
,
1746 mips_mdebug_frame_prev_register
1749 static const struct frame_unwind
*
1750 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1752 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1753 CORE_ADDR startaddr
= 0;
1754 mips_extra_func_info_t proc_desc
;
1757 /* Only use the mdebug frame unwinder on mdebug frames where all the
1758 registers have been saved. Leave hard cases such as no mdebug or
1759 in prologue for the heuristic unwinders. */
1761 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1762 if (proc_desc
== NULL
)
1765 /* Not sure exactly what kernel_trap means, but if it means the
1766 kernel saves the registers without a prologue doing it, we better
1767 not examine the prologue to see whether registers have been saved
1769 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1771 return &mips_mdebug_frame_unwind
;
1773 /* In any frame other than the innermost or a frame interrupted by a
1774 signal, we assume that all registers have been saved. This
1775 assumes that all register saves in a function happen before the
1776 first function call. */
1777 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1778 return &mips_mdebug_frame_unwind
;
1784 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1787 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1792 static const struct frame_base mips_mdebug_frame_base
= {
1793 &mips_mdebug_frame_unwind
,
1794 mips_mdebug_frame_base_address
,
1795 mips_mdebug_frame_base_address
,
1796 mips_mdebug_frame_base_address
1799 static const struct frame_base
*
1800 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1802 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1803 return &mips_mdebug_frame_base
;
1808 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1809 Procedures that use the 32-bit instruction set are handled by the
1810 mips_insn32 unwinder. */
1812 static struct mips_frame_cache
*
1813 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1815 mips_extra_func_info_t proc_desc
;
1816 struct mips_frame_cache
*cache
;
1817 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1818 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1819 /* r0 bit means kernel trap */
1821 /* What registers have been saved? Bitmasks. */
1822 unsigned long gen_mask
, float_mask
;
1824 if ((*this_cache
) != NULL
)
1825 return (*this_cache
);
1826 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1827 (*this_cache
) = cache
;
1828 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1830 /* Get the mdebug proc descriptor. */
1831 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1832 if (proc_desc
== NULL
)
1833 /* I'm not sure how/whether this can happen. Normally when we
1834 can't find a proc_desc, we "synthesize" one using
1835 heuristic_proc_desc and set the saved_regs right away. */
1838 /* Extract the frame's base. */
1839 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1840 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1842 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1843 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1844 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1846 /* In any frame other than the innermost or a frame interrupted by a
1847 signal, we assume that all registers have been saved. This
1848 assumes that all register saves in a function happen before the
1849 first function call. */
1850 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1851 /* Not sure exactly what kernel_trap means, but if it means the
1852 kernel saves the registers without a prologue doing it, we
1853 better not examine the prologue to see whether registers
1854 have been saved yet. */
1857 /* We need to figure out whether the registers that the
1858 proc_desc claims are saved have been saved yet. */
1862 /* Bitmasks; set if we have found a save for the register. */
1863 unsigned long gen_save_found
= 0;
1864 unsigned long float_save_found
= 0;
1867 /* If the address is odd, assume this is MIPS16 code. */
1868 addr
= PROC_LOW_ADDR (proc_desc
);
1869 mips16
= pc_is_mips16 (addr
);
1871 /* Scan through this function's instructions preceding the
1872 current PC, and look for those that save registers. */
1873 while (addr
< frame_pc_unwind (next_frame
))
1877 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1879 addr
+= MIPS16_INSTLEN
;
1883 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1884 &gen_save_found
, &float_save_found
);
1885 addr
+= MIPS_INSTLEN
;
1888 gen_mask
= gen_save_found
;
1889 float_mask
= float_save_found
;
1892 /* Fill in the offsets for the registers which gen_mask says were
1895 CORE_ADDR reg_position
= (cache
->base
1896 + PROC_REG_OFFSET (proc_desc
));
1898 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1899 if (gen_mask
& 0x80000000)
1901 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1902 reg_position
-= mips_abi_regsize (gdbarch
);
1906 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1907 order of that normally used by gcc. Therefore, we have to fetch
1908 the first instruction of the function, and if it's an entry
1909 instruction that saves $s0 or $s1, correct their saved addresses. */
1910 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1912 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1913 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1917 int sreg_count
= (inst
>> 6) & 3;
1919 /* Check if the ra register was pushed on the stack. */
1920 CORE_ADDR reg_position
= (cache
->base
1921 + PROC_REG_OFFSET (proc_desc
));
1923 reg_position
-= mips_abi_regsize (gdbarch
);
1925 /* Check if the s0 and s1 registers were pushed on the
1927 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1929 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1931 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1932 reg_position
-= mips_abi_regsize (gdbarch
);
1937 /* Fill in the offsets for the registers which float_mask says were
1940 CORE_ADDR reg_position
= (cache
->base
1941 + PROC_FREG_OFFSET (proc_desc
));
1943 /* Fill in the offsets for the float registers which float_mask
1945 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1946 if (float_mask
& 0x80000000)
1948 if (mips_abi_regsize (gdbarch
) == 4
1949 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1951 /* On a big endian 32 bit ABI, floating point registers
1952 are paired to form doubles such that the most
1953 significant part is in $f[N+1] and the least
1954 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1955 registers are also spilled as a pair and stored as a
1958 When little-endian the least significant part is
1959 stored first leading to the memory order $f[N] and
1962 Unfortunately, when big-endian the most significant
1963 part of the double is stored first, and the least
1964 significant is stored second. This leads to the
1965 registers being ordered in memory as firt $f[N+1] and
1968 For the big-endian case make certain that the
1969 addresses point at the correct (swapped) locations
1970 $f[N] and $f[N+1] pair (keep in mind that
1971 reg_position is decremented each time through the
1974 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1975 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1977 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1978 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1981 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1982 .addr
= reg_position
;
1983 reg_position
-= mips_abi_regsize (gdbarch
);
1986 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1987 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1990 /* SP_REGNUM, contains the value and not the address. */
1991 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1993 return (*this_cache
);
1997 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1998 struct frame_id
*this_id
)
2000 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2002 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2006 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
2008 int regnum
, int *optimizedp
,
2009 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2010 int *realnump
, void *valuep
)
2012 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2014 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2015 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2018 static const struct frame_unwind mips_insn16_frame_unwind
=
2021 mips_insn16_frame_this_id
,
2022 mips_insn16_frame_prev_register
2025 static const struct frame_unwind
*
2026 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
2028 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2029 if (pc_is_mips16 (pc
))
2030 return &mips_insn16_frame_unwind
;
2035 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
2038 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2043 static const struct frame_base mips_insn16_frame_base
=
2045 &mips_insn16_frame_unwind
,
2046 mips_insn16_frame_base_address
,
2047 mips_insn16_frame_base_address
,
2048 mips_insn16_frame_base_address
2051 static const struct frame_base
*
2052 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
2054 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
2055 return &mips_insn16_frame_base
;
2060 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2061 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2062 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2065 static struct mips_frame_cache
*
2066 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2068 mips_extra_func_info_t proc_desc
;
2069 struct mips_frame_cache
*cache
;
2070 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2071 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2072 /* r0 bit means kernel trap */
2074 /* What registers have been saved? Bitmasks. */
2075 unsigned long gen_mask
, float_mask
;
2077 if ((*this_cache
) != NULL
)
2078 return (*this_cache
);
2079 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2080 (*this_cache
) = cache
;
2081 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2083 /* Get the mdebug proc descriptor. */
2084 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
2085 if (proc_desc
== NULL
)
2086 /* I'm not sure how/whether this can happen. Normally when we
2087 can't find a proc_desc, we "synthesize" one using
2088 heuristic_proc_desc and set the saved_regs right away. */
2091 /* Extract the frame's base. */
2092 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2093 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2095 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
2096 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
2097 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
2099 /* In any frame other than the innermost or a frame interrupted by a
2100 signal, we assume that all registers have been saved. This
2101 assumes that all register saves in a function happen before the
2102 first function call. */
2103 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
2104 /* Not sure exactly what kernel_trap means, but if it means the
2105 kernel saves the registers without a prologue doing it, we
2106 better not examine the prologue to see whether registers
2107 have been saved yet. */
2110 /* We need to figure out whether the registers that the
2111 proc_desc claims are saved have been saved yet. */
2115 /* Bitmasks; set if we have found a save for the register. */
2116 unsigned long gen_save_found
= 0;
2117 unsigned long float_save_found
= 0;
2120 /* If the address is odd, assume this is MIPS16 code. */
2121 addr
= PROC_LOW_ADDR (proc_desc
);
2122 mips16
= pc_is_mips16 (addr
);
2124 /* Scan through this function's instructions preceding the
2125 current PC, and look for those that save registers. */
2126 while (addr
< frame_pc_unwind (next_frame
))
2130 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
2132 addr
+= MIPS16_INSTLEN
;
2136 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
2137 &gen_save_found
, &float_save_found
);
2138 addr
+= MIPS_INSTLEN
;
2141 gen_mask
= gen_save_found
;
2142 float_mask
= float_save_found
;
2145 /* Fill in the offsets for the registers which gen_mask says were
2148 CORE_ADDR reg_position
= (cache
->base
2149 + PROC_REG_OFFSET (proc_desc
));
2151 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
2152 if (gen_mask
& 0x80000000)
2154 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
2155 reg_position
-= mips_abi_regsize (gdbarch
);
2159 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
2160 order of that normally used by gcc. Therefore, we have to fetch
2161 the first instruction of the function, and if it's an entry
2162 instruction that saves $s0 or $s1, correct their saved addresses. */
2163 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
2165 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
2166 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
2170 int sreg_count
= (inst
>> 6) & 3;
2172 /* Check if the ra register was pushed on the stack. */
2173 CORE_ADDR reg_position
= (cache
->base
2174 + PROC_REG_OFFSET (proc_desc
));
2176 reg_position
-= mips_abi_regsize (gdbarch
);
2178 /* Check if the s0 and s1 registers were pushed on the
2180 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
2182 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2184 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
2185 reg_position
-= mips_abi_regsize (gdbarch
);
2190 /* Fill in the offsets for the registers which float_mask says were
2193 CORE_ADDR reg_position
= (cache
->base
2194 + PROC_FREG_OFFSET (proc_desc
));
2196 /* Fill in the offsets for the float registers which float_mask
2198 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
2199 if (float_mask
& 0x80000000)
2201 if (mips_abi_regsize (gdbarch
) == 4
2202 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2204 /* On a big endian 32 bit ABI, floating point registers
2205 are paired to form doubles such that the most
2206 significant part is in $f[N+1] and the least
2207 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
2208 registers are also spilled as a pair and stored as a
2211 When little-endian the least significant part is
2212 stored first leading to the memory order $f[N] and
2215 Unfortunately, when big-endian the most significant
2216 part of the double is stored first, and the least
2217 significant is stored second. This leads to the
2218 registers being ordered in memory as firt $f[N+1] and
2221 For the big-endian case make certain that the
2222 addresses point at the correct (swapped) locations
2223 $f[N] and $f[N+1] pair (keep in mind that
2224 reg_position is decremented each time through the
2227 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2228 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
2230 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2231 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
2234 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2235 .addr
= reg_position
;
2236 reg_position
-= mips_abi_regsize (gdbarch
);
2239 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2240 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2243 /* SP_REGNUM, contains the value and not the address. */
2244 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2246 return (*this_cache
);
2250 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2251 struct frame_id
*this_id
)
2253 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2255 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2259 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2261 int regnum
, int *optimizedp
,
2262 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2263 int *realnump
, void *valuep
)
2265 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2267 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2268 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2271 static const struct frame_unwind mips_insn32_frame_unwind
=
2274 mips_insn32_frame_this_id
,
2275 mips_insn32_frame_prev_register
2278 static const struct frame_unwind
*
2279 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2281 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2282 if (! pc_is_mips16 (pc
))
2283 return &mips_insn32_frame_unwind
;
2288 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2291 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2296 static const struct frame_base mips_insn32_frame_base
=
2298 &mips_insn32_frame_unwind
,
2299 mips_insn32_frame_base_address
,
2300 mips_insn32_frame_base_address
,
2301 mips_insn32_frame_base_address
2304 static const struct frame_base
*
2305 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2307 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2308 return &mips_insn32_frame_base
;
2313 static struct trad_frame_cache
*
2314 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2317 CORE_ADDR start_addr
;
2318 CORE_ADDR stack_addr
;
2319 struct trad_frame_cache
*this_trad_cache
;
2321 if ((*this_cache
) != NULL
)
2322 return (*this_cache
);
2323 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2324 (*this_cache
) = this_trad_cache
;
2326 /* The return address is in the link register. */
2327 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2329 /* Frame ID, since it's a frameless / stackless function, no stack
2330 space is allocated and SP on entry is the current SP. */
2331 pc
= frame_pc_unwind (next_frame
);
2332 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2333 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2334 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2336 /* Assume that the frame's base is the same as the
2338 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2340 return this_trad_cache
;
2344 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2345 struct frame_id
*this_id
)
2347 struct trad_frame_cache
*this_trad_cache
2348 = mips_stub_frame_cache (next_frame
, this_cache
);
2349 trad_frame_get_id (this_trad_cache
, this_id
);
2353 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2355 int regnum
, int *optimizedp
,
2356 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2357 int *realnump
, void *valuep
)
2359 struct trad_frame_cache
*this_trad_cache
2360 = mips_stub_frame_cache (next_frame
, this_cache
);
2361 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2362 lvalp
, addrp
, realnump
, valuep
);
2365 static const struct frame_unwind mips_stub_frame_unwind
=
2368 mips_stub_frame_this_id
,
2369 mips_stub_frame_prev_register
2372 static const struct frame_unwind
*
2373 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2375 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2376 if (in_plt_section (pc
, NULL
))
2377 return &mips_stub_frame_unwind
;
2383 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2386 struct trad_frame_cache
*this_trad_cache
2387 = mips_stub_frame_cache (next_frame
, this_cache
);
2388 return trad_frame_get_this_base (this_trad_cache
);
2391 static const struct frame_base mips_stub_frame_base
=
2393 &mips_stub_frame_unwind
,
2394 mips_stub_frame_base_address
,
2395 mips_stub_frame_base_address
,
2396 mips_stub_frame_base_address
2399 static const struct frame_base
*
2400 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2402 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2403 return &mips_stub_frame_base
;
2409 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2411 /* Always a pseudo. */
2412 gdb_assert (regno
>= NUM_REGS
);
2416 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2419 else if ((regno
% NUM_REGS
) == MIPS_SP_REGNUM
)
2420 /* MIPS_SP_REGNUM is special, its value is stored in saved_regs.
2421 In fact, it is so special that it can even only be fetched
2422 using a raw register number! Once this code as been converted
2423 to frame-unwind the problem goes away. */
2424 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
2426 return frame_unwind_register_signed (fi
, regno
);
2430 /* mips_addr_bits_remove - remove useless address bits */
2433 mips_addr_bits_remove (CORE_ADDR addr
)
2435 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2436 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2437 /* This hack is a work-around for existing boards using PMON, the
2438 simulator, and any other 64-bit targets that doesn't have true
2439 64-bit addressing. On these targets, the upper 32 bits of
2440 addresses are ignored by the hardware. Thus, the PC or SP are
2441 likely to have been sign extended to all 1s by instruction
2442 sequences that load 32-bit addresses. For example, a typical
2443 piece of code that loads an address is this:
2445 lui $r2, <upper 16 bits>
2446 ori $r2, <lower 16 bits>
2448 But the lui sign-extends the value such that the upper 32 bits
2449 may be all 1s. The workaround is simply to mask off these
2450 bits. In the future, gcc may be changed to support true 64-bit
2451 addressing, and this masking will have to be disabled. */
2452 return addr
&= 0xffffffffUL
;
2457 /* mips_software_single_step() is called just before we want to resume
2458 the inferior, if we want to single-step it but there is no hardware
2459 or kernel single-step support (MIPS on GNU/Linux for example). We find
2460 the target of the coming instruction and breakpoint it.
2462 single_step is also called just after the inferior stops. If we had
2463 set up a simulated single-step, we undo our damage. */
2466 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2468 static CORE_ADDR next_pc
;
2469 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2470 static binsn_quantum break_mem
;
2473 if (insert_breakpoints_p
)
2475 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2476 next_pc
= mips_next_pc (pc
);
2478 target_insert_breakpoint (next_pc
, break_mem
);
2481 target_remove_breakpoint (next_pc
, break_mem
);
2484 static struct mips_extra_func_info temp_proc_desc
;
2486 /* This hack will go away once the get_prev_frame() code has been
2487 modified to set the frame's type first. That is BEFORE init extra
2488 frame info et.al. is called. This is because it will become
2489 possible to skip the init extra info call for sigtramp and dummy
2491 static CORE_ADDR
*temp_saved_regs
;
2493 /* Set a register's saved stack address in temp_saved_regs. If an
2494 address has already been set for this register, do nothing; this
2495 way we will only recognize the first save of a given register in a
2498 For simplicity, save the address in both [0 .. NUM_REGS) and
2499 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2500 is used as it is only second range (the ABI instead of ISA
2501 registers) that comes into play when finding saved registers in a
2505 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
2507 if (saved_regs
[regno
] == 0)
2509 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
2510 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
2515 /* Test whether the PC points to the return instruction at the
2516 end of a function. */
2519 mips_about_to_return (CORE_ADDR pc
)
2521 if (pc_is_mips16 (pc
))
2522 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2523 generates a "jr $ra"; other times it generates code to load
2524 the return address from the stack to an accessible register (such
2525 as $a3), then a "jr" using that register. This second case
2526 is almost impossible to distinguish from an indirect jump
2527 used for switch statements, so we don't even try. */
2528 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2530 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2534 /* This fencepost looks highly suspicious to me. Removing it also
2535 seems suspicious as it could affect remote debugging across serial
2539 heuristic_proc_start (CORE_ADDR pc
)
2546 pc
= ADDR_BITS_REMOVE (pc
);
2548 fence
= start_pc
- heuristic_fence_post
;
2552 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2553 fence
= VM_MIN_ADDRESS
;
2555 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2557 /* search back for previous return */
2558 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2559 if (start_pc
< fence
)
2561 /* It's not clear to me why we reach this point when
2562 stop_soon, but with this test, at least we
2563 don't print out warnings for every child forked (eg, on
2564 decstation). 22apr93 rich@cygnus.com. */
2565 if (stop_soon
== NO_STOP_QUIETLY
)
2567 static int blurb_printed
= 0;
2569 warning ("GDB can't find the start of the function at 0x%s.",
2574 /* This actually happens frequently in embedded
2575 development, when you first connect to a board
2576 and your stack pointer and pc are nowhere in
2577 particular. This message needs to give people
2578 in that situation enough information to
2579 determine that it's no big deal. */
2580 printf_filtered ("\n\
2581 GDB is unable to find the start of the function at 0x%s\n\
2582 and thus can't determine the size of that function's stack frame.\n\
2583 This means that GDB may be unable to access that stack frame, or\n\
2584 the frames below it.\n\
2585 This problem is most likely caused by an invalid program counter or\n\
2587 However, if you think GDB should simply search farther back\n\
2588 from 0x%s for code which looks like the beginning of a\n\
2589 function, you can increase the range of the search using the `set\n\
2590 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2597 else if (pc_is_mips16 (start_pc
))
2599 unsigned short inst
;
2601 /* On MIPS16, any one of the following is likely to be the
2602 start of a function:
2606 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2607 inst
= mips_fetch_instruction (start_pc
);
2608 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2609 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2610 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2611 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2613 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2614 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2619 else if (mips_about_to_return (start_pc
))
2621 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2628 /* Fetch the immediate value from a MIPS16 instruction.
2629 If the previous instruction was an EXTEND, use it to extend
2630 the upper bits of the immediate value. This is a helper function
2631 for mips16_heuristic_proc_desc. */
2634 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2635 unsigned short inst
, /* current instruction */
2636 int nbits
, /* number of bits in imm field */
2637 int scale
, /* scale factor to be applied to imm */
2638 int is_signed
) /* is the imm field signed? */
2642 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2644 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2645 if (offset
& 0x8000) /* check for negative extend */
2646 offset
= 0 - (0x10000 - (offset
& 0xffff));
2647 return offset
| (inst
& 0x1f);
2651 int max_imm
= 1 << nbits
;
2652 int mask
= max_imm
- 1;
2653 int sign_bit
= max_imm
>> 1;
2655 offset
= inst
& mask
;
2656 if (is_signed
&& (offset
& sign_bit
))
2657 offset
= 0 - (max_imm
- offset
);
2658 return offset
* scale
;
2663 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2664 stream from start_pc to limit_pc. */
2667 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2668 struct frame_info
*next_frame
, CORE_ADDR sp
)
2671 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2672 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2673 unsigned inst
= 0; /* current instruction */
2674 unsigned entry_inst
= 0; /* the entry instruction */
2676 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2678 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2679 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2681 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2683 /* Save the previous instruction. If it's an EXTEND, we'll extract
2684 the immediate offset extension from it in mips16_get_imm. */
2687 /* Fetch and decode the instruction. */
2688 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2689 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2690 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2692 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2693 if (offset
< 0) /* negative stack adjustment? */
2694 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2696 /* Exit loop if a positive stack adjustment is found, which
2697 usually means that the stack cleanup code in the function
2698 epilogue is reached. */
2701 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2703 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2704 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2705 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2706 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2708 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2710 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2711 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2712 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2713 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2715 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2717 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2718 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2719 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2721 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2723 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2724 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2725 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2727 else if (inst
== 0x673d) /* move $s1, $sp */
2730 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2732 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2734 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2735 frame_addr
= sp
+ offset
;
2736 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2737 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2739 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2741 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2742 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2743 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2744 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2746 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2748 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2749 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2750 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2751 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2753 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2754 entry_inst
= inst
; /* save for later processing */
2755 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2756 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2759 /* The entry instruction is typically the first instruction in a function,
2760 and it stores registers at offsets relative to the value of the old SP
2761 (before the prologue). But the value of the sp parameter to this
2762 function is the new SP (after the prologue has been executed). So we
2763 can't calculate those offsets until we've seen the entire prologue,
2764 and can calculate what the old SP must have been. */
2765 if (entry_inst
!= 0)
2767 int areg_count
= (entry_inst
>> 8) & 7;
2768 int sreg_count
= (entry_inst
>> 6) & 3;
2770 /* The entry instruction always subtracts 32 from the SP. */
2771 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2773 /* Now we can calculate what the SP must have been at the
2774 start of the function prologue. */
2775 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2777 /* Check if a0-a3 were saved in the caller's argument save area. */
2778 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2780 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2781 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2782 offset
+= mips_abi_regsize (current_gdbarch
);
2785 /* Check if the ra register was pushed on the stack. */
2787 if (entry_inst
& 0x20)
2789 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2790 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2791 offset
-= mips_abi_regsize (current_gdbarch
);
2794 /* Check if the s0 and s1 registers were pushed on the stack. */
2795 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2797 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2798 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2799 offset
-= mips_abi_regsize (current_gdbarch
);
2805 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2806 struct frame_info
*next_frame
, CORE_ADDR sp
)
2809 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2811 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2812 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2813 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2814 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2815 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2817 unsigned long inst
, high_word
, low_word
;
2820 /* Fetch the instruction. */
2821 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2823 /* Save some code by pre-extracting some useful fields. */
2824 high_word
= (inst
>> 16) & 0xffff;
2825 low_word
= inst
& 0xffff;
2826 reg
= high_word
& 0x1f;
2828 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2829 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2830 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2832 if (low_word
& 0x8000) /* negative stack adjustment? */
2833 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2835 /* Exit loop if a positive stack adjustment is found, which
2836 usually means that the stack cleanup code in the function
2837 epilogue is reached. */
2840 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2842 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2843 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2845 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2847 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2849 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2850 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2852 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2854 /* Old gcc frame, r30 is virtual frame pointer. */
2855 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2856 frame_addr
= sp
+ low_word
;
2857 else if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2859 unsigned alloca_adjust
;
2860 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2861 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2862 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2863 if (alloca_adjust
> 0)
2865 /* FP > SP + frame_size. This may be because
2866 * of an alloca or somethings similar.
2867 * Fix sp to "pre-alloca" value, and try again.
2869 sp
+= alloca_adjust
;
2874 /* move $30,$sp. With different versions of gas this will be either
2875 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2876 Accept any one of these. */
2877 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2879 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2880 if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2882 unsigned alloca_adjust
;
2883 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2884 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2885 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2886 if (alloca_adjust
> 0)
2888 /* FP > SP + frame_size. This may be because
2889 * of an alloca or somethings similar.
2890 * Fix sp to "pre-alloca" value, and try again.
2892 sp
+= alloca_adjust
;
2897 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2899 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2900 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2905 static mips_extra_func_info_t
2906 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2907 struct frame_info
*next_frame
, int cur_frame
)
2912 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2918 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2919 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2920 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2921 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2922 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2923 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2925 if (start_pc
+ 200 < limit_pc
)
2926 limit_pc
= start_pc
+ 200;
2927 if (pc_is_mips16 (start_pc
))
2928 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2930 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2931 return &temp_proc_desc
;
2934 struct mips_objfile_private
2940 /* Global used to communicate between non_heuristic_proc_desc and
2941 compare_pdr_entries within qsort (). */
2942 static bfd
*the_bfd
;
2945 compare_pdr_entries (const void *a
, const void *b
)
2947 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2948 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2952 else if (lhs
== rhs
)
2958 static mips_extra_func_info_t
2959 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2961 CORE_ADDR startaddr
;
2962 mips_extra_func_info_t proc_desc
;
2963 struct block
*b
= block_for_pc (pc
);
2965 struct obj_section
*sec
;
2966 struct mips_objfile_private
*priv
;
2968 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2970 *addrptr
= startaddr
;
2974 sec
= find_pc_section (pc
);
2977 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2979 /* Search the ".pdr" section generated by GAS. This includes most of
2980 the information normally found in ECOFF PDRs. */
2982 the_bfd
= sec
->objfile
->obfd
;
2984 && (the_bfd
->format
== bfd_object
2985 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2986 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2988 /* Right now GAS only outputs the address as a four-byte sequence.
2989 This means that we should not bother with this method on 64-bit
2990 targets (until that is fixed). */
2992 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2993 sizeof (struct mips_objfile_private
));
2995 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2997 else if (priv
== NULL
)
3001 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
3002 sizeof (struct mips_objfile_private
));
3004 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
3007 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
3008 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
3010 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
3011 priv
->contents
, 0, priv
->size
);
3013 /* In general, the .pdr section is sorted. However, in the
3014 presence of multiple code sections (and other corner cases)
3015 it can become unsorted. Sort it so that we can use a faster
3017 qsort (priv
->contents
, priv
->size
/ 32, 32,
3018 compare_pdr_entries
);
3023 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
3027 if (priv
->size
!= 0)
3034 high
= priv
->size
/ 32;
3036 /* We've found a .pdr section describing this objfile. We want to
3037 find the entry which describes this code address. The .pdr
3038 information is not very descriptive; we have only a function
3039 start address. We have to look for the closest entry, because
3040 the local symbol at the beginning of this function may have
3041 been stripped - so if we ask the symbol table for the start
3042 address we may get a preceding global function. */
3044 /* First, find the last .pdr entry starting at or before PC. */
3047 mid
= (low
+ high
) / 2;
3049 ptr
= priv
->contents
+ mid
* 32;
3050 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3051 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3052 SECT_OFF_TEXT (sec
->objfile
));
3059 while (low
!= high
);
3061 /* Both low and high point one past the PDR of interest. If
3062 both are zero, that means this PC is before any region
3063 covered by a PDR, i.e. pdr_pc for the first PDR entry is
3067 ptr
= priv
->contents
+ (low
- 1) * 32;
3068 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3069 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3070 SECT_OFF_TEXT (sec
->objfile
));
3073 /* We don't have a range, so we have no way to know for sure
3074 whether we're in the correct PDR or a PDR for a preceding
3075 function and the current function was a stripped local
3076 symbol. But if the PDR's PC is at least as great as the
3077 best guess from the symbol table, assume that it does cover
3078 the right area; if a .pdr section is present at all then
3079 nearly every function will have an entry. The biggest exception
3080 will be the dynamic linker stubs; conveniently these are
3081 placed before .text instead of after. */
3083 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
3085 struct symbol
*sym
= find_pc_function (pc
);
3090 /* Fill in what we need of the proc_desc. */
3091 proc_desc
= (mips_extra_func_info_t
)
3092 obstack_alloc (&sec
->objfile
->objfile_obstack
,
3093 sizeof (struct mips_extra_func_info
));
3094 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
3096 /* Only used for dummy frames. */
3097 PROC_HIGH_ADDR (proc_desc
) = 0;
3099 PROC_FRAME_OFFSET (proc_desc
)
3100 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
3101 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3103 PROC_FRAME_ADJUST (proc_desc
) = 0;
3104 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3106 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3108 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3110 PROC_FREG_OFFSET (proc_desc
)
3111 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
3112 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3114 proc_desc
->pdr
.isym
= (long) sym
;
3124 if (startaddr
> BLOCK_START (b
))
3126 /* This is the "pathological" case referred to in a comment in
3127 print_frame_info. It might be better to move this check into
3132 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
3134 /* If we never found a PDR for this function in symbol reading, then
3135 examine prologues to find the information. */
3138 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
3139 if (PROC_FRAME_REG (proc_desc
) == -1)
3149 static mips_extra_func_info_t
3150 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
3152 mips_extra_func_info_t proc_desc
;
3153 CORE_ADDR startaddr
= 0;
3155 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
3159 /* IF this is the topmost frame AND
3160 * (this proc does not have debugging information OR
3161 * the PC is in the procedure prologue)
3162 * THEN create a "heuristic" proc_desc (by analyzing
3163 * the actual code) to replace the "official" proc_desc.
3165 if (next_frame
== NULL
)
3167 struct symtab_and_line val
;
3168 struct symbol
*proc_symbol
=
3169 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
3173 val
= find_pc_line (BLOCK_START
3174 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
3175 val
.pc
= val
.end
? val
.end
: pc
;
3177 if (!proc_symbol
|| pc
< val
.pc
)
3179 mips_extra_func_info_t found_heuristic
=
3180 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
3181 pc
, next_frame
, cur_frame
);
3182 if (found_heuristic
)
3183 proc_desc
= found_heuristic
;
3189 /* Is linked_proc_desc_table really necessary? It only seems to be used
3190 by procedure call dummys. However, the procedures being called ought
3191 to have their own proc_descs, and even if they don't,
3192 heuristic_proc_desc knows how to create them! */
3194 struct linked_proc_info
*link
;
3196 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
3197 if (PROC_LOW_ADDR (&link
->info
) <= pc
3198 && PROC_HIGH_ADDR (&link
->info
) > pc
)
3202 startaddr
= heuristic_proc_start (pc
);
3204 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
3209 /* MIPS stack frames are almost impenetrable. When execution stops,
3210 we basically have to look at symbol information for the function
3211 that we stopped in, which tells us *which* register (if any) is
3212 the base of the frame pointer, and what offset from that register
3213 the frame itself is at.
3215 This presents a problem when trying to examine a stack in memory
3216 (that isn't executing at the moment), using the "frame" command. We
3217 don't have a PC, nor do we have any registers except SP.
3219 This routine takes two arguments, SP and PC, and tries to make the
3220 cached frames look as if these two arguments defined a frame on the
3221 cache. This allows the rest of info frame to extract the important
3222 arguments without difficulty. */
3225 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
3228 error ("MIPS frame specifications require two arguments: sp and pc");
3230 return create_new_frame (argv
[0], argv
[1]);
3233 /* According to the current ABI, should the type be passed in a
3234 floating-point register (assuming that there is space)? When there
3235 is no FPU, FP are not even considered as possibile candidates for
3236 FP registers and, consequently this returns false - forces FP
3237 arguments into integer registers. */
3240 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
3242 return ((typecode
== TYPE_CODE_FLT
3244 && (typecode
== TYPE_CODE_STRUCT
3245 || typecode
== TYPE_CODE_UNION
)
3246 && TYPE_NFIELDS (arg_type
) == 1
3247 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
3248 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
3251 /* On o32, argument passing in GPRs depends on the alignment of the type being
3252 passed. Return 1 if this type must be aligned to a doubleword boundary. */
3255 mips_type_needs_double_align (struct type
*type
)
3257 enum type_code typecode
= TYPE_CODE (type
);
3259 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
3261 else if (typecode
== TYPE_CODE_STRUCT
)
3263 if (TYPE_NFIELDS (type
) < 1)
3265 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
3267 else if (typecode
== TYPE_CODE_UNION
)
3271 n
= TYPE_NFIELDS (type
);
3272 for (i
= 0; i
< n
; i
++)
3273 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3280 /* Adjust the address downward (direction of stack growth) so that it
3281 is correctly aligned for a new stack frame. */
3283 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3285 return align_down (addr
, 16);
3288 /* Determine how a return value is stored within the MIPS register
3289 file, given the return type `valtype'. */
3291 struct return_value_word
3300 return_value_location (struct type
*valtype
,
3301 struct return_value_word
*hi
,
3302 struct return_value_word
*lo
)
3304 int len
= TYPE_LENGTH (valtype
);
3305 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3307 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3308 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3309 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3311 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3313 /* We need to break a 64bit float in two 32 bit halves and
3314 spread them across a floating-point register pair. */
3315 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3316 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3317 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3318 && register_size (current_gdbarch
,
3319 mips_regnum (current_gdbarch
)->
3320 fp0
) == 8) ? 4 : 0);
3321 hi
->reg_offset
= lo
->reg_offset
;
3322 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3323 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3329 /* The floating point value fits in a single floating-point
3331 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3332 && register_size (current_gdbarch
,
3333 mips_regnum (current_gdbarch
)->
3335 && len
== 4) ? 4 : 0);
3336 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3347 /* Locate a result possibly spread across two registers. */
3349 lo
->reg
= regnum
+ 0;
3350 hi
->reg
= regnum
+ 1;
3351 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3352 && len
< mips_abi_regsize (current_gdbarch
))
3354 /* "un-left-justify" the value in the low register */
3355 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3360 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3361 && len
< mips_abi_regsize (current_gdbarch
) * 2
3362 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3363 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3365 /* "un-left-justify" the value spread across two registers. */
3366 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3367 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3369 hi
->len
= len
- lo
->len
;
3373 /* Only perform a partial copy of the second register. */
3376 if (len
> mips_abi_regsize (current_gdbarch
))
3378 lo
->len
= mips_abi_regsize (current_gdbarch
);
3379 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3387 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3388 && register_size (current_gdbarch
, regnum
) == 8
3389 && mips_abi_regsize (current_gdbarch
) == 4)
3391 /* Account for the fact that only the least-signficant part
3392 of the register is being used */
3393 lo
->reg_offset
+= 4;
3394 hi
->reg_offset
+= 4;
3397 hi
->buf_offset
= lo
->len
;
3401 /* Should call_function allocate stack space for a struct return? */
3404 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3406 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3407 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3410 /* Should call_function pass struct by reference?
3411 For each architecture, structs are passed either by
3412 value or by reference, depending on their size. */
3415 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3417 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3418 int len
= TYPE_LENGTH (check_typedef (type
));
3419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3421 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3422 return (len
> mips_abi_regsize (current_gdbarch
));
3428 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3429 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3430 int nargs
, struct value
**args
, CORE_ADDR sp
,
3431 int struct_return
, CORE_ADDR struct_addr
)
3437 int stack_offset
= 0;
3438 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3439 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3441 /* For shared libraries, "t9" needs to point at the function
3443 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3445 /* Set the return address register to point to the entry point of
3446 the program, where a breakpoint lies in wait. */
3447 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3449 /* First ensure that the stack and structure return address (if any)
3450 are properly aligned. The stack has to be at least 64-bit
3451 aligned even on 32-bit machines, because doubles must be 64-bit
3452 aligned. For n32 and n64, stack frames need to be 128-bit
3453 aligned, so we round to this widest known alignment. */
3455 sp
= align_down (sp
, 16);
3456 struct_addr
= align_down (struct_addr
, 16);
3458 /* Now make space on the stack for the args. We allocate more
3459 than necessary for EABI, because the first few arguments are
3460 passed in registers, but that's OK. */
3461 for (argnum
= 0; argnum
< nargs
; argnum
++)
3462 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3463 mips_stack_argsize (gdbarch
));
3464 sp
-= align_up (len
, 16);
3467 fprintf_unfiltered (gdb_stdlog
,
3468 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3469 paddr_nz (sp
), (long) align_up (len
, 16));
3471 /* Initialize the integer and float register pointers. */
3473 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3475 /* The struct_return pointer occupies the first parameter-passing reg. */
3479 fprintf_unfiltered (gdb_stdlog
,
3480 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3481 argreg
, paddr_nz (struct_addr
));
3482 write_register (argreg
++, struct_addr
);
3485 /* Now load as many as possible of the first arguments into
3486 registers, and push the rest onto the stack. Loop thru args
3487 from first to last. */
3488 for (argnum
= 0; argnum
< nargs
; argnum
++)
3491 char valbuf
[MAX_REGISTER_SIZE
];
3492 struct value
*arg
= args
[argnum
];
3493 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3494 int len
= TYPE_LENGTH (arg_type
);
3495 enum type_code typecode
= TYPE_CODE (arg_type
);
3498 fprintf_unfiltered (gdb_stdlog
,
3499 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3500 argnum
+ 1, len
, (int) typecode
);
3502 /* The EABI passes structures that do not fit in a register by
3504 if (len
> mips_abi_regsize (gdbarch
)
3505 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3507 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3508 VALUE_ADDRESS (arg
));
3509 typecode
= TYPE_CODE_PTR
;
3510 len
= mips_abi_regsize (gdbarch
);
3513 fprintf_unfiltered (gdb_stdlog
, " push");
3516 val
= (char *) VALUE_CONTENTS (arg
);
3518 /* 32-bit ABIs always start floating point arguments in an
3519 even-numbered floating point register. Round the FP register
3520 up before the check to see if there are any FP registers
3521 left. Non MIPS_EABI targets also pass the FP in the integer
3522 registers so also round up normal registers. */
3523 if (mips_abi_regsize (gdbarch
) < 8
3524 && fp_register_arg_p (typecode
, arg_type
))
3526 if ((float_argreg
& 1))
3530 /* Floating point arguments passed in registers have to be
3531 treated specially. On 32-bit architectures, doubles
3532 are passed in register pairs; the even register gets
3533 the low word, and the odd register gets the high word.
3534 On non-EABI processors, the first two floating point arguments are
3535 also copied to general registers, because MIPS16 functions
3536 don't use float registers for arguments. This duplication of
3537 arguments in general registers can't hurt non-MIPS16 functions
3538 because those registers are normally skipped. */
3539 /* MIPS_EABI squeezes a struct that contains a single floating
3540 point value into an FP register instead of pushing it onto the
3542 if (fp_register_arg_p (typecode
, arg_type
)
3543 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3545 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3547 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3548 unsigned long regval
;
3550 /* Write the low word of the double to the even register(s). */
3551 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3553 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3554 float_argreg
, phex (regval
, 4));
3555 write_register (float_argreg
++, regval
);
3557 /* Write the high word of the double to the odd register(s). */
3558 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3560 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3561 float_argreg
, phex (regval
, 4));
3562 write_register (float_argreg
++, regval
);
3566 /* This is a floating point value that fits entirely
3567 in a single register. */
3568 /* On 32 bit ABI's the float_argreg is further adjusted
3569 above to ensure that it is even register aligned. */
3570 LONGEST regval
= extract_unsigned_integer (val
, len
);
3572 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3573 float_argreg
, phex (regval
, len
));
3574 write_register (float_argreg
++, regval
);
3579 /* Copy the argument to general registers or the stack in
3580 register-sized pieces. Large arguments are split between
3581 registers and stack. */
3582 /* Note: structs whose size is not a multiple of
3583 mips_abi_regsize() are treated specially: Irix cc passes
3584 them in registers where gcc sometimes puts them on the
3585 stack. For maximum compatibility, we will put them in
3587 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3588 && (len
% mips_abi_regsize (gdbarch
) != 0));
3590 /* Note: Floating-point values that didn't fit into an FP
3591 register are only written to memory. */
3594 /* Remember if the argument was written to the stack. */
3595 int stack_used_p
= 0;
3596 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3597 ? len
: mips_abi_regsize (gdbarch
));
3600 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3603 /* Write this portion of the argument to the stack. */
3604 if (argreg
> MIPS_LAST_ARG_REGNUM
3606 || fp_register_arg_p (typecode
, arg_type
))
3608 /* Should shorter than int integer values be
3609 promoted to int before being stored? */
3610 int longword_offset
= 0;
3613 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3615 if (mips_stack_argsize (gdbarch
) == 8
3616 && (typecode
== TYPE_CODE_INT
3617 || typecode
== TYPE_CODE_PTR
3618 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3619 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3620 else if ((typecode
== TYPE_CODE_STRUCT
3621 || typecode
== TYPE_CODE_UNION
)
3622 && (TYPE_LENGTH (arg_type
)
3623 < mips_stack_argsize (gdbarch
)))
3624 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3629 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3630 paddr_nz (stack_offset
));
3631 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3632 paddr_nz (longword_offset
));
3635 addr
= sp
+ stack_offset
+ longword_offset
;
3640 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3642 for (i
= 0; i
< partial_len
; i
++)
3644 fprintf_unfiltered (gdb_stdlog
, "%02x",
3648 write_memory (addr
, val
, partial_len
);
3651 /* Note!!! This is NOT an else clause. Odd sized
3652 structs may go thru BOTH paths. Floating point
3653 arguments will not. */
3654 /* Write this portion of the argument to a general
3655 purpose register. */
3656 if (argreg
<= MIPS_LAST_ARG_REGNUM
3657 && !fp_register_arg_p (typecode
, arg_type
))
3660 extract_unsigned_integer (val
, partial_len
);
3663 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3666 mips_abi_regsize (gdbarch
)));
3667 write_register (argreg
, regval
);
3674 /* Compute the the offset into the stack at which we
3675 will copy the next parameter.
3677 In the new EABI (and the NABI32), the stack_offset
3678 only needs to be adjusted when it has been used. */
3681 stack_offset
+= align_up (partial_len
,
3682 mips_stack_argsize (gdbarch
));
3686 fprintf_unfiltered (gdb_stdlog
, "\n");
3689 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3691 /* Return adjusted stack pointer. */
3695 /* Given a return value in `regbuf' with a type `valtype', extract and
3696 copy its value into `valbuf'. */
3699 mips_eabi_extract_return_value (struct type
*valtype
,
3700 char regbuf
[], char *valbuf
)
3702 struct return_value_word lo
;
3703 struct return_value_word hi
;
3704 return_value_location (valtype
, &hi
, &lo
);
3706 memcpy (valbuf
+ lo
.buf_offset
,
3707 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3708 lo
.reg_offset
, lo
.len
);
3711 memcpy (valbuf
+ hi
.buf_offset
,
3712 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3713 hi
.reg_offset
, hi
.len
);
3716 /* Given a return value in `valbuf' with a type `valtype', write it's
3717 value into the appropriate register. */
3720 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3722 char raw_buffer
[MAX_REGISTER_SIZE
];
3723 struct return_value_word lo
;
3724 struct return_value_word hi
;
3725 return_value_location (valtype
, &hi
, &lo
);
3727 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3728 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3729 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3730 raw_buffer
, register_size (current_gdbarch
,
3735 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3736 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3737 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3739 register_size (current_gdbarch
,
3744 /* N32/N64 ABI stuff. */
3747 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3748 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3749 int nargs
, struct value
**args
, CORE_ADDR sp
,
3750 int struct_return
, CORE_ADDR struct_addr
)
3756 int stack_offset
= 0;
3757 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3758 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3760 /* For shared libraries, "t9" needs to point at the function
3762 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3764 /* Set the return address register to point to the entry point of
3765 the program, where a breakpoint lies in wait. */
3766 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3768 /* First ensure that the stack and structure return address (if any)
3769 are properly aligned. The stack has to be at least 64-bit
3770 aligned even on 32-bit machines, because doubles must be 64-bit
3771 aligned. For n32 and n64, stack frames need to be 128-bit
3772 aligned, so we round to this widest known alignment. */
3774 sp
= align_down (sp
, 16);
3775 struct_addr
= align_down (struct_addr
, 16);
3777 /* Now make space on the stack for the args. */
3778 for (argnum
= 0; argnum
< nargs
; argnum
++)
3779 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3780 mips_stack_argsize (gdbarch
));
3781 sp
-= align_up (len
, 16);
3784 fprintf_unfiltered (gdb_stdlog
,
3785 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3786 paddr_nz (sp
), (long) align_up (len
, 16));
3788 /* Initialize the integer and float register pointers. */
3790 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3792 /* The struct_return pointer occupies the first parameter-passing reg. */
3796 fprintf_unfiltered (gdb_stdlog
,
3797 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3798 argreg
, paddr_nz (struct_addr
));
3799 write_register (argreg
++, struct_addr
);
3802 /* Now load as many as possible of the first arguments into
3803 registers, and push the rest onto the stack. Loop thru args
3804 from first to last. */
3805 for (argnum
= 0; argnum
< nargs
; argnum
++)
3808 struct value
*arg
= args
[argnum
];
3809 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3810 int len
= TYPE_LENGTH (arg_type
);
3811 enum type_code typecode
= TYPE_CODE (arg_type
);
3814 fprintf_unfiltered (gdb_stdlog
,
3815 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3816 argnum
+ 1, len
, (int) typecode
);
3818 val
= (char *) VALUE_CONTENTS (arg
);
3820 if (fp_register_arg_p (typecode
, arg_type
)
3821 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3823 /* This is a floating point value that fits entirely
3824 in a single register. */
3825 /* On 32 bit ABI's the float_argreg is further adjusted
3826 above to ensure that it is even register aligned. */
3827 LONGEST regval
= extract_unsigned_integer (val
, len
);
3829 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3830 float_argreg
, phex (regval
, len
));
3831 write_register (float_argreg
++, regval
);
3834 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3835 argreg
, phex (regval
, len
));
3836 write_register (argreg
, regval
);
3841 /* Copy the argument to general registers or the stack in
3842 register-sized pieces. Large arguments are split between
3843 registers and stack. */
3844 /* Note: structs whose size is not a multiple of
3845 mips_abi_regsize() are treated specially: Irix cc passes
3846 them in registers where gcc sometimes puts them on the
3847 stack. For maximum compatibility, we will put them in
3849 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3850 && (len
% mips_abi_regsize (gdbarch
) != 0));
3851 /* Note: Floating-point values that didn't fit into an FP
3852 register are only written to memory. */
3855 /* Rememer if the argument was written to the stack. */
3856 int stack_used_p
= 0;
3857 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3858 ? len
: mips_abi_regsize (gdbarch
));
3861 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3864 /* Write this portion of the argument to the stack. */
3865 if (argreg
> MIPS_LAST_ARG_REGNUM
3867 || fp_register_arg_p (typecode
, arg_type
))
3869 /* Should shorter than int integer values be
3870 promoted to int before being stored? */
3871 int longword_offset
= 0;
3874 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3876 if (mips_stack_argsize (gdbarch
) == 8
3877 && (typecode
== TYPE_CODE_INT
3878 || typecode
== TYPE_CODE_PTR
3879 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3880 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3885 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3886 paddr_nz (stack_offset
));
3887 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3888 paddr_nz (longword_offset
));
3891 addr
= sp
+ stack_offset
+ longword_offset
;
3896 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3898 for (i
= 0; i
< partial_len
; i
++)
3900 fprintf_unfiltered (gdb_stdlog
, "%02x",
3904 write_memory (addr
, val
, partial_len
);
3907 /* Note!!! This is NOT an else clause. Odd sized
3908 structs may go thru BOTH paths. Floating point
3909 arguments will not. */
3910 /* Write this portion of the argument to a general
3911 purpose register. */
3912 if (argreg
<= MIPS_LAST_ARG_REGNUM
3913 && !fp_register_arg_p (typecode
, arg_type
))
3916 extract_unsigned_integer (val
, partial_len
);
3918 /* A non-floating-point argument being passed in a
3919 general register. If a struct or union, and if
3920 the remaining length is smaller than the register
3921 size, we have to adjust the register value on
3924 It does not seem to be necessary to do the
3925 same for integral types.
3927 cagney/2001-07-23: gdb/179: Also, GCC, when
3928 outputting LE O32 with sizeof (struct) <
3929 mips_abi_regsize(), generates a left shift as
3930 part of storing the argument in a register a
3931 register (the left shift isn't generated when
3932 sizeof (struct) >= mips_abi_regsize()). Since
3933 it is quite possible that this is GCC
3934 contradicting the LE/O32 ABI, GDB has not been
3935 adjusted to accommodate this. Either someone
3936 needs to demonstrate that the LE/O32 ABI
3937 specifies such a left shift OR this new ABI gets
3938 identified as such and GDB gets tweaked
3941 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3942 && partial_len
< mips_abi_regsize (gdbarch
)
3943 && (typecode
== TYPE_CODE_STRUCT
||
3944 typecode
== TYPE_CODE_UNION
))
3945 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3949 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3952 mips_abi_regsize (gdbarch
)));
3953 write_register (argreg
, regval
);
3960 /* Compute the the offset into the stack at which we
3961 will copy the next parameter.
3963 In N32 (N64?), the stack_offset only needs to be
3964 adjusted when it has been used. */
3967 stack_offset
+= align_up (partial_len
,
3968 mips_stack_argsize (gdbarch
));
3972 fprintf_unfiltered (gdb_stdlog
, "\n");
3975 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3977 /* Return adjusted stack pointer. */
3981 static enum return_value_convention
3982 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3983 struct type
*type
, struct regcache
*regcache
,
3984 void *readbuf
, const void *writebuf
)
3986 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3987 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3988 || TYPE_CODE (type
) == TYPE_CODE_UNION
3989 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3990 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3991 return RETURN_VALUE_STRUCT_CONVENTION
;
3992 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3993 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3995 /* A floating-point value belongs in the least significant part
3998 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3999 mips_xfer_register (regcache
,
4000 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4002 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4003 return RETURN_VALUE_REGISTER_CONVENTION
;
4005 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4006 && TYPE_NFIELDS (type
) <= 2
4007 && TYPE_NFIELDS (type
) >= 1
4008 && ((TYPE_NFIELDS (type
) == 1
4009 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4011 || (TYPE_NFIELDS (type
) == 2
4012 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4014 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4016 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4018 /* A struct that contains one or two floats. Each value is part
4019 in the least significant part of their floating point
4023 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4024 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4026 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4029 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4031 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4032 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4033 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4035 return RETURN_VALUE_REGISTER_CONVENTION
;
4037 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4038 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4040 /* A structure or union. Extract the left justified value,
4041 regardless of the byte order. I.e. DO NOT USE
4045 for (offset
= 0, regnum
= V0_REGNUM
;
4046 offset
< TYPE_LENGTH (type
);
4047 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4049 int xfer
= register_size (current_gdbarch
, regnum
);
4050 if (offset
+ xfer
> TYPE_LENGTH (type
))
4051 xfer
= TYPE_LENGTH (type
) - offset
;
4053 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4054 offset
, xfer
, regnum
);
4055 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4056 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4058 return RETURN_VALUE_REGISTER_CONVENTION
;
4062 /* A scalar extract each part but least-significant-byte
4066 for (offset
= 0, regnum
= V0_REGNUM
;
4067 offset
< TYPE_LENGTH (type
);
4068 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4070 int xfer
= register_size (current_gdbarch
, regnum
);
4071 if (offset
+ xfer
> TYPE_LENGTH (type
))
4072 xfer
= TYPE_LENGTH (type
) - offset
;
4074 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4075 offset
, xfer
, regnum
);
4076 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4077 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4079 return RETURN_VALUE_REGISTER_CONVENTION
;
4083 /* O32 ABI stuff. */
4086 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4087 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4088 int nargs
, struct value
**args
, CORE_ADDR sp
,
4089 int struct_return
, CORE_ADDR struct_addr
)
4095 int stack_offset
= 0;
4096 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4097 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4099 /* For shared libraries, "t9" needs to point at the function
4101 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4103 /* Set the return address register to point to the entry point of
4104 the program, where a breakpoint lies in wait. */
4105 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4107 /* First ensure that the stack and structure return address (if any)
4108 are properly aligned. The stack has to be at least 64-bit
4109 aligned even on 32-bit machines, because doubles must be 64-bit
4110 aligned. For n32 and n64, stack frames need to be 128-bit
4111 aligned, so we round to this widest known alignment. */
4113 sp
= align_down (sp
, 16);
4114 struct_addr
= align_down (struct_addr
, 16);
4116 /* Now make space on the stack for the args. */
4117 for (argnum
= 0; argnum
< nargs
; argnum
++)
4118 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4119 mips_stack_argsize (gdbarch
));
4120 sp
-= align_up (len
, 16);
4123 fprintf_unfiltered (gdb_stdlog
,
4124 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
4125 paddr_nz (sp
), (long) align_up (len
, 16));
4127 /* Initialize the integer and float register pointers. */
4129 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4131 /* The struct_return pointer occupies the first parameter-passing reg. */
4135 fprintf_unfiltered (gdb_stdlog
,
4136 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
4137 argreg
, paddr_nz (struct_addr
));
4138 write_register (argreg
++, struct_addr
);
4139 stack_offset
+= mips_stack_argsize (gdbarch
);
4142 /* Now load as many as possible of the first arguments into
4143 registers, and push the rest onto the stack. Loop thru args
4144 from first to last. */
4145 for (argnum
= 0; argnum
< nargs
; argnum
++)
4148 struct value
*arg
= args
[argnum
];
4149 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4150 int len
= TYPE_LENGTH (arg_type
);
4151 enum type_code typecode
= TYPE_CODE (arg_type
);
4154 fprintf_unfiltered (gdb_stdlog
,
4155 "mips_o32_push_dummy_call: %d len=%d type=%d",
4156 argnum
+ 1, len
, (int) typecode
);
4158 val
= (char *) VALUE_CONTENTS (arg
);
4160 /* 32-bit ABIs always start floating point arguments in an
4161 even-numbered floating point register. Round the FP register
4162 up before the check to see if there are any FP registers
4163 left. O32/O64 targets also pass the FP in the integer
4164 registers so also round up normal registers. */
4165 if (mips_abi_regsize (gdbarch
) < 8
4166 && fp_register_arg_p (typecode
, arg_type
))
4168 if ((float_argreg
& 1))
4172 /* Floating point arguments passed in registers have to be
4173 treated specially. On 32-bit architectures, doubles
4174 are passed in register pairs; the even register gets
4175 the low word, and the odd register gets the high word.
4176 On O32/O64, the first two floating point arguments are
4177 also copied to general registers, because MIPS16 functions
4178 don't use float registers for arguments. This duplication of
4179 arguments in general registers can't hurt non-MIPS16 functions
4180 because those registers are normally skipped. */
4182 if (fp_register_arg_p (typecode
, arg_type
)
4183 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4185 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4187 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4188 unsigned long regval
;
4190 /* Write the low word of the double to the even register(s). */
4191 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4193 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4194 float_argreg
, phex (regval
, 4));
4195 write_register (float_argreg
++, regval
);
4197 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4198 argreg
, phex (regval
, 4));
4199 write_register (argreg
++, regval
);
4201 /* Write the high word of the double to the odd register(s). */
4202 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4204 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4205 float_argreg
, phex (regval
, 4));
4206 write_register (float_argreg
++, regval
);
4209 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4210 argreg
, phex (regval
, 4));
4211 write_register (argreg
++, regval
);
4215 /* This is a floating point value that fits entirely
4216 in a single register. */
4217 /* On 32 bit ABI's the float_argreg is further adjusted
4218 above to ensure that it is even register aligned. */
4219 LONGEST regval
= extract_unsigned_integer (val
, len
);
4221 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4222 float_argreg
, phex (regval
, len
));
4223 write_register (float_argreg
++, regval
);
4224 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4225 registers for each argument. The below is (my
4226 guess) to ensure that the corresponding integer
4227 register has reserved the same space. */
4229 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4230 argreg
, phex (regval
, len
));
4231 write_register (argreg
, regval
);
4232 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4234 /* Reserve space for the FP register. */
4235 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4239 /* Copy the argument to general registers or the stack in
4240 register-sized pieces. Large arguments are split between
4241 registers and stack. */
4242 /* Note: structs whose size is not a multiple of
4243 mips_abi_regsize() are treated specially: Irix cc passes
4244 them in registers where gcc sometimes puts them on the
4245 stack. For maximum compatibility, we will put them in
4247 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4248 && (len
% mips_abi_regsize (gdbarch
) != 0));
4249 /* Structures should be aligned to eight bytes (even arg registers)
4250 on MIPS_ABI_O32, if their first member has double precision. */
4251 if (mips_abi_regsize (gdbarch
) < 8
4252 && mips_type_needs_double_align (arg_type
))
4257 /* Note: Floating-point values that didn't fit into an FP
4258 register are only written to memory. */
4261 /* Remember if the argument was written to the stack. */
4262 int stack_used_p
= 0;
4263 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4264 ? len
: mips_abi_regsize (gdbarch
));
4267 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4270 /* Write this portion of the argument to the stack. */
4271 if (argreg
> MIPS_LAST_ARG_REGNUM
4273 || fp_register_arg_p (typecode
, arg_type
))
4275 /* Should shorter than int integer values be
4276 promoted to int before being stored? */
4277 int longword_offset
= 0;
4280 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4282 if (mips_stack_argsize (gdbarch
) == 8
4283 && (typecode
== TYPE_CODE_INT
4284 || typecode
== TYPE_CODE_PTR
4285 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4286 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4291 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4292 paddr_nz (stack_offset
));
4293 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4294 paddr_nz (longword_offset
));
4297 addr
= sp
+ stack_offset
+ longword_offset
;
4302 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4304 for (i
= 0; i
< partial_len
; i
++)
4306 fprintf_unfiltered (gdb_stdlog
, "%02x",
4310 write_memory (addr
, val
, partial_len
);
4313 /* Note!!! This is NOT an else clause. Odd sized
4314 structs may go thru BOTH paths. Floating point
4315 arguments will not. */
4316 /* Write this portion of the argument to a general
4317 purpose register. */
4318 if (argreg
<= MIPS_LAST_ARG_REGNUM
4319 && !fp_register_arg_p (typecode
, arg_type
))
4321 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4322 /* Value may need to be sign extended, because
4323 mips_isa_regsize() != mips_abi_regsize(). */
4325 /* A non-floating-point argument being passed in a
4326 general register. If a struct or union, and if
4327 the remaining length is smaller than the register
4328 size, we have to adjust the register value on
4331 It does not seem to be necessary to do the
4332 same for integral types.
4334 Also don't do this adjustment on O64 binaries.
4336 cagney/2001-07-23: gdb/179: Also, GCC, when
4337 outputting LE O32 with sizeof (struct) <
4338 mips_abi_regsize(), generates a left shift as
4339 part of storing the argument in a register a
4340 register (the left shift isn't generated when
4341 sizeof (struct) >= mips_abi_regsize()). Since
4342 it is quite possible that this is GCC
4343 contradicting the LE/O32 ABI, GDB has not been
4344 adjusted to accommodate this. Either someone
4345 needs to demonstrate that the LE/O32 ABI
4346 specifies such a left shift OR this new ABI gets
4347 identified as such and GDB gets tweaked
4350 if (mips_abi_regsize (gdbarch
) < 8
4351 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4352 && partial_len
< mips_abi_regsize (gdbarch
)
4353 && (typecode
== TYPE_CODE_STRUCT
||
4354 typecode
== TYPE_CODE_UNION
))
4355 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4359 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4362 mips_abi_regsize (gdbarch
)));
4363 write_register (argreg
, regval
);
4366 /* Prevent subsequent floating point arguments from
4367 being passed in floating point registers. */
4368 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4374 /* Compute the the offset into the stack at which we
4375 will copy the next parameter.
4377 In older ABIs, the caller reserved space for
4378 registers that contained arguments. This was loosely
4379 refered to as their "home". Consequently, space is
4380 always allocated. */
4382 stack_offset
+= align_up (partial_len
,
4383 mips_stack_argsize (gdbarch
));
4387 fprintf_unfiltered (gdb_stdlog
, "\n");
4390 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4392 /* Return adjusted stack pointer. */
4396 static enum return_value_convention
4397 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4398 struct regcache
*regcache
,
4399 void *readbuf
, const void *writebuf
)
4401 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4403 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4404 || TYPE_CODE (type
) == TYPE_CODE_UNION
4405 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4406 return RETURN_VALUE_STRUCT_CONVENTION
;
4407 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4408 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4410 /* A single-precision floating-point value. It fits in the
4411 least significant part of FP0. */
4413 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4414 mips_xfer_register (regcache
,
4415 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4417 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4418 return RETURN_VALUE_REGISTER_CONVENTION
;
4420 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4421 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4423 /* A double-precision floating-point value. The most
4424 significant part goes in FP1, and the least significant in
4427 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4428 switch (TARGET_BYTE_ORDER
)
4430 case BFD_ENDIAN_LITTLE
:
4431 mips_xfer_register (regcache
,
4432 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4433 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4434 mips_xfer_register (regcache
,
4435 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4436 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4438 case BFD_ENDIAN_BIG
:
4439 mips_xfer_register (regcache
,
4440 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4441 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4442 mips_xfer_register (regcache
,
4443 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4444 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4447 internal_error (__FILE__
, __LINE__
, "bad switch");
4449 return RETURN_VALUE_REGISTER_CONVENTION
;
4452 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4453 && TYPE_NFIELDS (type
) <= 2
4454 && TYPE_NFIELDS (type
) >= 1
4455 && ((TYPE_NFIELDS (type
) == 1
4456 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4458 || (TYPE_NFIELDS (type
) == 2
4459 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4461 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4463 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4465 /* A struct that contains one or two floats. Each value is part
4466 in the least significant part of their floating point
4468 bfd_byte reg
[MAX_REGISTER_SIZE
];
4471 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4472 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4474 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4477 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4479 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4480 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4481 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4483 return RETURN_VALUE_REGISTER_CONVENTION
;
4487 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4488 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4490 /* A structure or union. Extract the left justified value,
4491 regardless of the byte order. I.e. DO NOT USE
4495 for (offset
= 0, regnum
= V0_REGNUM
;
4496 offset
< TYPE_LENGTH (type
);
4497 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4499 int xfer
= register_size (current_gdbarch
, regnum
);
4500 if (offset
+ xfer
> TYPE_LENGTH (type
))
4501 xfer
= TYPE_LENGTH (type
) - offset
;
4503 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4504 offset
, xfer
, regnum
);
4505 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4506 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4508 return RETURN_VALUE_REGISTER_CONVENTION
;
4513 /* A scalar extract each part but least-significant-byte
4514 justified. o32 thinks registers are 4 byte, regardless of
4515 the ISA. mips_stack_argsize controls this. */
4518 for (offset
= 0, regnum
= V0_REGNUM
;
4519 offset
< TYPE_LENGTH (type
);
4520 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4522 int xfer
= mips_stack_argsize (gdbarch
);
4523 if (offset
+ xfer
> TYPE_LENGTH (type
))
4524 xfer
= TYPE_LENGTH (type
) - offset
;
4526 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4527 offset
, xfer
, regnum
);
4528 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4529 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4531 return RETURN_VALUE_REGISTER_CONVENTION
;
4535 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4539 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4540 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4542 struct value
**args
, CORE_ADDR sp
,
4543 int struct_return
, CORE_ADDR struct_addr
)
4549 int stack_offset
= 0;
4550 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4551 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4553 /* For shared libraries, "t9" needs to point at the function
4555 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4557 /* Set the return address register to point to the entry point of
4558 the program, where a breakpoint lies in wait. */
4559 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4561 /* First ensure that the stack and structure return address (if any)
4562 are properly aligned. The stack has to be at least 64-bit
4563 aligned even on 32-bit machines, because doubles must be 64-bit
4564 aligned. For n32 and n64, stack frames need to be 128-bit
4565 aligned, so we round to this widest known alignment. */
4567 sp
= align_down (sp
, 16);
4568 struct_addr
= align_down (struct_addr
, 16);
4570 /* Now make space on the stack for the args. */
4571 for (argnum
= 0; argnum
< nargs
; argnum
++)
4572 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4573 mips_stack_argsize (gdbarch
));
4574 sp
-= align_up (len
, 16);
4577 fprintf_unfiltered (gdb_stdlog
,
4578 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4579 paddr_nz (sp
), (long) align_up (len
, 16));
4581 /* Initialize the integer and float register pointers. */
4583 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4585 /* The struct_return pointer occupies the first parameter-passing reg. */
4589 fprintf_unfiltered (gdb_stdlog
,
4590 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4591 argreg
, paddr_nz (struct_addr
));
4592 write_register (argreg
++, struct_addr
);
4593 stack_offset
+= mips_stack_argsize (gdbarch
);
4596 /* Now load as many as possible of the first arguments into
4597 registers, and push the rest onto the stack. Loop thru args
4598 from first to last. */
4599 for (argnum
= 0; argnum
< nargs
; argnum
++)
4602 struct value
*arg
= args
[argnum
];
4603 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4604 int len
= TYPE_LENGTH (arg_type
);
4605 enum type_code typecode
= TYPE_CODE (arg_type
);
4608 fprintf_unfiltered (gdb_stdlog
,
4609 "mips_o64_push_dummy_call: %d len=%d type=%d",
4610 argnum
+ 1, len
, (int) typecode
);
4612 val
= (char *) VALUE_CONTENTS (arg
);
4614 /* 32-bit ABIs always start floating point arguments in an
4615 even-numbered floating point register. Round the FP register
4616 up before the check to see if there are any FP registers
4617 left. O32/O64 targets also pass the FP in the integer
4618 registers so also round up normal registers. */
4619 if (mips_abi_regsize (gdbarch
) < 8
4620 && fp_register_arg_p (typecode
, arg_type
))
4622 if ((float_argreg
& 1))
4626 /* Floating point arguments passed in registers have to be
4627 treated specially. On 32-bit architectures, doubles
4628 are passed in register pairs; the even register gets
4629 the low word, and the odd register gets the high word.
4630 On O32/O64, the first two floating point arguments are
4631 also copied to general registers, because MIPS16 functions
4632 don't use float registers for arguments. This duplication of
4633 arguments in general registers can't hurt non-MIPS16 functions
4634 because those registers are normally skipped. */
4636 if (fp_register_arg_p (typecode
, arg_type
)
4637 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4639 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4641 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4642 unsigned long regval
;
4644 /* Write the low word of the double to the even register(s). */
4645 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4647 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4648 float_argreg
, phex (regval
, 4));
4649 write_register (float_argreg
++, regval
);
4651 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4652 argreg
, phex (regval
, 4));
4653 write_register (argreg
++, regval
);
4655 /* Write the high word of the double to the odd register(s). */
4656 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4658 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4659 float_argreg
, phex (regval
, 4));
4660 write_register (float_argreg
++, regval
);
4663 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4664 argreg
, phex (regval
, 4));
4665 write_register (argreg
++, regval
);
4669 /* This is a floating point value that fits entirely
4670 in a single register. */
4671 /* On 32 bit ABI's the float_argreg is further adjusted
4672 above to ensure that it is even register aligned. */
4673 LONGEST regval
= extract_unsigned_integer (val
, len
);
4675 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4676 float_argreg
, phex (regval
, len
));
4677 write_register (float_argreg
++, regval
);
4678 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4679 registers for each argument. The below is (my
4680 guess) to ensure that the corresponding integer
4681 register has reserved the same space. */
4683 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4684 argreg
, phex (regval
, len
));
4685 write_register (argreg
, regval
);
4686 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4688 /* Reserve space for the FP register. */
4689 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4693 /* Copy the argument to general registers or the stack in
4694 register-sized pieces. Large arguments are split between
4695 registers and stack. */
4696 /* Note: structs whose size is not a multiple of
4697 mips_abi_regsize() are treated specially: Irix cc passes
4698 them in registers where gcc sometimes puts them on the
4699 stack. For maximum compatibility, we will put them in
4701 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4702 && (len
% mips_abi_regsize (gdbarch
) != 0));
4703 /* Structures should be aligned to eight bytes (even arg registers)
4704 on MIPS_ABI_O32, if their first member has double precision. */
4705 if (mips_abi_regsize (gdbarch
) < 8
4706 && mips_type_needs_double_align (arg_type
))
4711 /* Note: Floating-point values that didn't fit into an FP
4712 register are only written to memory. */
4715 /* Remember if the argument was written to the stack. */
4716 int stack_used_p
= 0;
4717 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4718 ? len
: mips_abi_regsize (gdbarch
));
4721 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4724 /* Write this portion of the argument to the stack. */
4725 if (argreg
> MIPS_LAST_ARG_REGNUM
4727 || fp_register_arg_p (typecode
, arg_type
))
4729 /* Should shorter than int integer values be
4730 promoted to int before being stored? */
4731 int longword_offset
= 0;
4734 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4736 if (mips_stack_argsize (gdbarch
) == 8
4737 && (typecode
== TYPE_CODE_INT
4738 || typecode
== TYPE_CODE_PTR
4739 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4740 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4745 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4746 paddr_nz (stack_offset
));
4747 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4748 paddr_nz (longword_offset
));
4751 addr
= sp
+ stack_offset
+ longword_offset
;
4756 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4758 for (i
= 0; i
< partial_len
; i
++)
4760 fprintf_unfiltered (gdb_stdlog
, "%02x",
4764 write_memory (addr
, val
, partial_len
);
4767 /* Note!!! This is NOT an else clause. Odd sized
4768 structs may go thru BOTH paths. Floating point
4769 arguments will not. */
4770 /* Write this portion of the argument to a general
4771 purpose register. */
4772 if (argreg
<= MIPS_LAST_ARG_REGNUM
4773 && !fp_register_arg_p (typecode
, arg_type
))
4775 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4776 /* Value may need to be sign extended, because
4777 mips_isa_regsize() != mips_abi_regsize(). */
4779 /* A non-floating-point argument being passed in a
4780 general register. If a struct or union, and if
4781 the remaining length is smaller than the register
4782 size, we have to adjust the register value on
4785 It does not seem to be necessary to do the
4786 same for integral types.
4788 Also don't do this adjustment on O64 binaries.
4790 cagney/2001-07-23: gdb/179: Also, GCC, when
4791 outputting LE O32 with sizeof (struct) <
4792 mips_abi_regsize(), generates a left shift as
4793 part of storing the argument in a register a
4794 register (the left shift isn't generated when
4795 sizeof (struct) >= mips_abi_regsize()). Since
4796 it is quite possible that this is GCC
4797 contradicting the LE/O32 ABI, GDB has not been
4798 adjusted to accommodate this. Either someone
4799 needs to demonstrate that the LE/O32 ABI
4800 specifies such a left shift OR this new ABI gets
4801 identified as such and GDB gets tweaked
4804 if (mips_abi_regsize (gdbarch
) < 8
4805 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4806 && partial_len
< mips_abi_regsize (gdbarch
)
4807 && (typecode
== TYPE_CODE_STRUCT
||
4808 typecode
== TYPE_CODE_UNION
))
4809 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4813 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4816 mips_abi_regsize (gdbarch
)));
4817 write_register (argreg
, regval
);
4820 /* Prevent subsequent floating point arguments from
4821 being passed in floating point registers. */
4822 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4828 /* Compute the the offset into the stack at which we
4829 will copy the next parameter.
4831 In older ABIs, the caller reserved space for
4832 registers that contained arguments. This was loosely
4833 refered to as their "home". Consequently, space is
4834 always allocated. */
4836 stack_offset
+= align_up (partial_len
,
4837 mips_stack_argsize (gdbarch
));
4841 fprintf_unfiltered (gdb_stdlog
, "\n");
4844 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4846 /* Return adjusted stack pointer. */
4851 mips_o64_extract_return_value (struct type
*valtype
,
4852 char regbuf
[], char *valbuf
)
4854 struct return_value_word lo
;
4855 struct return_value_word hi
;
4856 return_value_location (valtype
, &hi
, &lo
);
4858 memcpy (valbuf
+ lo
.buf_offset
,
4859 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4860 lo
.reg_offset
, lo
.len
);
4863 memcpy (valbuf
+ hi
.buf_offset
,
4864 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4865 hi
.reg_offset
, hi
.len
);
4869 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4871 char raw_buffer
[MAX_REGISTER_SIZE
];
4872 struct return_value_word lo
;
4873 struct return_value_word hi
;
4874 return_value_location (valtype
, &hi
, &lo
);
4876 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4877 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4878 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4879 raw_buffer
, register_size (current_gdbarch
,
4884 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4885 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4886 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4888 register_size (current_gdbarch
,
4893 /* Floating point register management.
4895 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4896 64bit operations, these early MIPS cpus treat fp register pairs
4897 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4898 registers and offer a compatibility mode that emulates the MIPS2 fp
4899 model. When operating in MIPS2 fp compat mode, later cpu's split
4900 double precision floats into two 32-bit chunks and store them in
4901 consecutive fp regs. To display 64-bit floats stored in this
4902 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4903 Throw in user-configurable endianness and you have a real mess.
4905 The way this works is:
4906 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4907 double-precision value will be split across two logical registers.
4908 The lower-numbered logical register will hold the low-order bits,
4909 regardless of the processor's endianness.
4910 - If we are on a 64-bit processor, and we are looking for a
4911 single-precision value, it will be in the low ordered bits
4912 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4913 save slot in memory.
4914 - If we are in 64-bit mode, everything is straightforward.
4916 Note that this code only deals with "live" registers at the top of the
4917 stack. We will attempt to deal with saved registers later, when
4918 the raw/cooked register interface is in place. (We need a general
4919 interface that can deal with dynamic saved register sizes -- fp
4920 regs could be 32 bits wide in one frame and 64 on the frame above
4923 static struct type
*
4924 mips_float_register_type (void)
4926 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4927 return builtin_type_ieee_single_big
;
4929 return builtin_type_ieee_single_little
;
4932 static struct type
*
4933 mips_double_register_type (void)
4935 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4936 return builtin_type_ieee_double_big
;
4938 return builtin_type_ieee_double_little
;
4941 /* Copy a 32-bit single-precision value from the current frame
4942 into rare_buffer. */
4945 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4948 int raw_size
= register_size (current_gdbarch
, regno
);
4949 char *raw_buffer
= alloca (raw_size
);
4951 if (!frame_register_read (frame
, regno
, raw_buffer
))
4952 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4955 /* We have a 64-bit value for this register. Find the low-order
4959 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4964 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4968 memcpy (rare_buffer
, raw_buffer
, 4);
4972 /* Copy a 64-bit double-precision value from the current frame into
4973 rare_buffer. This may include getting half of it from the next
4977 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4980 int raw_size
= register_size (current_gdbarch
, regno
);
4982 if (raw_size
== 8 && !mips2_fp_compat ())
4984 /* We have a 64-bit value for this register, and we should use
4986 if (!frame_register_read (frame
, regno
, rare_buffer
))
4987 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4991 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4992 internal_error (__FILE__
, __LINE__
,
4993 "mips_read_fp_register_double: bad access to "
4994 "odd-numbered FP register");
4996 /* mips_read_fp_register_single will find the correct 32 bits from
4998 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5000 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
5001 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
5005 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
5006 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
5012 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
5014 { /* do values for FP (float) regs */
5016 double doub
, flt1
; /* doubles extracted from raw hex data */
5020 (char *) alloca (2 *
5021 register_size (current_gdbarch
,
5022 mips_regnum (current_gdbarch
)->fp0
));
5024 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
5025 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
5028 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
5030 /* 4-byte registers: Print hex and floating. Also print even
5031 numbered registers as doubles. */
5032 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
5033 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
5035 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
5038 fprintf_filtered (file
, " flt: ");
5040 fprintf_filtered (file
, " <invalid float> ");
5042 fprintf_filtered (file
, "%-17.9g", flt1
);
5044 if (regnum
% 2 == 0)
5046 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
5047 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
5050 fprintf_filtered (file
, " dbl: ");
5052 fprintf_filtered (file
, "<invalid double>");
5054 fprintf_filtered (file
, "%-24.17g", doub
);
5059 /* Eight byte registers: print each one as hex, float and double. */
5060 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
5061 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
5063 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
5064 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
5067 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
5070 fprintf_filtered (file
, " flt: ");
5072 fprintf_filtered (file
, "<invalid float>");
5074 fprintf_filtered (file
, "%-17.9g", flt1
);
5076 fprintf_filtered (file
, " dbl: ");
5078 fprintf_filtered (file
, "<invalid double>");
5080 fprintf_filtered (file
, "%-24.17g", doub
);
5085 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
5086 int regnum
, int all
)
5088 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5089 char raw_buffer
[MAX_REGISTER_SIZE
];
5092 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
5094 mips_print_fp_register (file
, frame
, regnum
);
5098 /* Get the data in raw format. */
5099 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5101 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
5105 fputs_filtered (REGISTER_NAME (regnum
), file
);
5107 /* The problem with printing numeric register names (r26, etc.) is that
5108 the user can't use them on input. Probably the best solution is to
5109 fix it so that either the numeric or the funky (a2, etc.) names
5110 are accepted on input. */
5111 if (regnum
< MIPS_NUMREGS
)
5112 fprintf_filtered (file
, "(r%d): ", regnum
);
5114 fprintf_filtered (file
, ": ");
5116 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5118 register_size (current_gdbarch
,
5119 regnum
) - register_size (current_gdbarch
, regnum
);
5123 print_scalar_formatted (raw_buffer
+ offset
,
5124 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
5128 /* Replacement for generic do_registers_info.
5129 Print regs in pretty columns. */
5132 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5135 fprintf_filtered (file
, " ");
5136 mips_print_fp_register (file
, frame
, regnum
);
5137 fprintf_filtered (file
, "\n");
5142 /* Print a row's worth of GP (int) registers, with name labels above */
5145 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5148 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5149 /* do values for GP (int) regs */
5150 char raw_buffer
[MAX_REGISTER_SIZE
];
5151 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
5155 /* For GP registers, we print a separate row of names above the vals */
5156 fprintf_filtered (file
, " ");
5157 for (col
= 0, regnum
= start_regnum
;
5158 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5160 if (*REGISTER_NAME (regnum
) == '\0')
5161 continue; /* unused register */
5162 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5164 break; /* end the row: reached FP register */
5165 fprintf_filtered (file
,
5166 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
5167 REGISTER_NAME (regnum
));
5170 /* print the R0 to R31 names */
5171 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
5172 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
5174 fprintf_filtered (file
, "\n ");
5176 /* now print the values in hex, 4 or 8 to the row */
5177 for (col
= 0, regnum
= start_regnum
;
5178 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5180 if (*REGISTER_NAME (regnum
) == '\0')
5181 continue; /* unused register */
5182 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5184 break; /* end row: reached FP register */
5185 /* OK: get the data in raw format. */
5186 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5187 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
5188 /* pad small registers */
5190 byte
< (mips_abi_regsize (current_gdbarch
)
5191 - register_size (current_gdbarch
, regnum
)); byte
++)
5192 printf_filtered (" ");
5193 /* Now print the register value in hex, endian order. */
5194 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5196 register_size (current_gdbarch
,
5197 regnum
) - register_size (current_gdbarch
, regnum
);
5198 byte
< register_size (current_gdbarch
, regnum
); byte
++)
5199 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5201 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
5203 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5204 fprintf_filtered (file
, " ");
5207 if (col
> 0) /* ie. if we actually printed anything... */
5208 fprintf_filtered (file
, "\n");
5213 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
5216 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5217 struct frame_info
*frame
, int regnum
, int all
)
5219 if (regnum
!= -1) /* do one specified register */
5221 gdb_assert (regnum
>= NUM_REGS
);
5222 if (*(REGISTER_NAME (regnum
)) == '\0')
5223 error ("Not a valid register for the current processor type");
5225 mips_print_register (file
, frame
, regnum
, 0);
5226 fprintf_filtered (file
, "\n");
5229 /* do all (or most) registers */
5232 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
5234 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5237 if (all
) /* true for "INFO ALL-REGISTERS" command */
5238 regnum
= print_fp_register_row (file
, frame
, regnum
);
5240 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5243 regnum
= print_gp_register_row (file
, frame
, regnum
);
5248 /* Is this a branch with a delay slot? */
5250 static int is_delayed (unsigned long);
5253 is_delayed (unsigned long insn
)
5256 for (i
= 0; i
< NUMOPCODES
; ++i
)
5257 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5258 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5260 return (i
< NUMOPCODES
5261 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5262 | INSN_COND_BRANCH_DELAY
5263 | INSN_COND_BRANCH_LIKELY
)));
5267 mips_step_skips_delay (CORE_ADDR pc
)
5269 char buf
[MIPS_INSTLEN
];
5271 /* There is no branch delay slot on MIPS16. */
5272 if (pc_is_mips16 (pc
))
5275 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5276 /* If error reading memory, guess that it is not a delayed branch. */
5278 return is_delayed ((unsigned long)
5279 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5282 /* Skip the PC past function prologue instructions (32-bit version).
5283 This is a helper function for mips_skip_prologue. */
5286 mips32_skip_prologue (CORE_ADDR pc
)
5290 int seen_sp_adjust
= 0;
5291 int load_immediate_bytes
= 0;
5293 /* Find an upper bound on the prologue. */
5294 end_pc
= skip_prologue_using_sal (pc
);
5296 end_pc
= pc
+ 100; /* Magic. */
5298 /* Skip the typical prologue instructions. These are the stack adjustment
5299 instruction and the instructions that save registers on the stack
5300 or in the gcc frame. */
5301 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5303 unsigned long high_word
;
5305 inst
= mips_fetch_instruction (pc
);
5306 high_word
= (inst
>> 16) & 0xffff;
5308 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5309 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5311 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5312 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5314 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5315 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5316 && (inst
& 0x001F0000)) /* reg != $zero */
5319 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5321 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5323 continue; /* reg != $zero */
5325 /* move $s8,$sp. With different versions of gas this will be either
5326 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5327 Accept any one of these. */
5328 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5331 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5333 else if (high_word
== 0x3c1c) /* lui $gp,n */
5335 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5337 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5338 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5340 /* The following instructions load $at or $t0 with an immediate
5341 value in preparation for a stack adjustment via
5342 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5343 a local variable, so we accept them only before a stack adjustment
5344 instruction was seen. */
5345 else if (!seen_sp_adjust
)
5347 if (high_word
== 0x3c01 || /* lui $at,n */
5348 high_word
== 0x3c08) /* lui $t0,n */
5350 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5353 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5354 high_word
== 0x3508 || /* ori $t0,$t0,n */
5355 high_word
== 0x3401 || /* ori $at,$zero,n */
5356 high_word
== 0x3408) /* ori $t0,$zero,n */
5358 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5368 /* In a frameless function, we might have incorrectly
5369 skipped some load immediate instructions. Undo the skipping
5370 if the load immediate was not followed by a stack adjustment. */
5371 if (load_immediate_bytes
&& !seen_sp_adjust
)
5372 pc
-= load_immediate_bytes
;
5376 /* Skip the PC past function prologue instructions (16-bit version).
5377 This is a helper function for mips_skip_prologue. */
5380 mips16_skip_prologue (CORE_ADDR pc
)
5383 int extend_bytes
= 0;
5384 int prev_extend_bytes
;
5386 /* Table of instructions likely to be found in a function prologue. */
5389 unsigned short inst
;
5390 unsigned short mask
;
5396 , /* addiu $sp,offset */
5399 , /* daddiu $sp,offset */
5402 , /* sw reg,n($sp) */
5405 , /* sd reg,n($sp) */
5408 , /* sw $ra,n($sp) */
5411 , /* sd $ra,n($sp) */
5417 , /* sw $a0-$a3,n($s1) */
5420 , /* move reg,$a0-$a3 */
5423 , /* entry pseudo-op */
5426 , /* addiu $s1,$sp,n */
5428 0, 0} /* end of table marker */
5431 /* Find an upper bound on the prologue. */
5432 end_pc
= skip_prologue_using_sal (pc
);
5434 end_pc
= pc
+ 100; /* Magic. */
5436 /* Skip the typical prologue instructions. These are the stack adjustment
5437 instruction and the instructions that save registers on the stack
5438 or in the gcc frame. */
5439 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5441 unsigned short inst
;
5444 inst
= mips_fetch_instruction (pc
);
5446 /* Normally we ignore an extend instruction. However, if it is
5447 not followed by a valid prologue instruction, we must adjust
5448 the pc back over the extend so that it won't be considered
5449 part of the prologue. */
5450 if ((inst
& 0xf800) == 0xf000) /* extend */
5452 extend_bytes
= MIPS16_INSTLEN
;
5455 prev_extend_bytes
= extend_bytes
;
5458 /* Check for other valid prologue instructions besides extend. */
5459 for (i
= 0; table
[i
].mask
!= 0; i
++)
5460 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5462 if (table
[i
].mask
!= 0) /* it was in table? */
5463 continue; /* ignore it */
5467 /* Return the current pc, adjusted backwards by 2 if
5468 the previous instruction was an extend. */
5469 return pc
- prev_extend_bytes
;
5475 /* To skip prologues, I use this predicate. Returns either PC itself
5476 if the code at PC does not look like a function prologue; otherwise
5477 returns an address that (if we're lucky) follows the prologue. If
5478 LENIENT, then we must skip everything which is involved in setting
5479 up the frame (it's OK to skip more, just so long as we don't skip
5480 anything which might clobber the registers which are being saved.
5481 We must skip more in the case where part of the prologue is in the
5482 delay slot of a non-prologue instruction). */
5485 mips_skip_prologue (CORE_ADDR pc
)
5487 /* See if we can determine the end of the prologue via the symbol table.
5488 If so, then return either PC, or the PC after the prologue, whichever
5491 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
5493 if (post_prologue_pc
!= 0)
5494 return max (pc
, post_prologue_pc
);
5496 /* Can't determine prologue from the symbol table, need to examine
5499 if (pc_is_mips16 (pc
))
5500 return mips16_skip_prologue (pc
);
5502 return mips32_skip_prologue (pc
);
5505 /* Root of all "set mips "/"show mips " commands. This will eventually be
5506 used for all MIPS-specific commands. */
5509 show_mips_command (char *args
, int from_tty
)
5511 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5515 set_mips_command (char *args
, int from_tty
)
5518 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5519 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5522 /* Commands to show/set the MIPS FPU type. */
5525 show_mipsfpu_command (char *args
, int from_tty
)
5528 switch (MIPS_FPU_TYPE
)
5530 case MIPS_FPU_SINGLE
:
5531 fpu
= "single-precision";
5533 case MIPS_FPU_DOUBLE
:
5534 fpu
= "double-precision";
5537 fpu
= "absent (none)";
5540 internal_error (__FILE__
, __LINE__
, "bad switch");
5542 if (mips_fpu_type_auto
)
5544 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5548 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5553 set_mipsfpu_command (char *args
, int from_tty
)
5556 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5557 show_mipsfpu_command (args
, from_tty
);
5561 set_mipsfpu_single_command (char *args
, int from_tty
)
5563 struct gdbarch_info info
;
5564 gdbarch_info_init (&info
);
5565 mips_fpu_type
= MIPS_FPU_SINGLE
;
5566 mips_fpu_type_auto
= 0;
5567 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5568 instead of relying on globals. Doing that would let generic code
5569 handle the search for this specific architecture. */
5570 if (!gdbarch_update_p (info
))
5571 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5575 set_mipsfpu_double_command (char *args
, int from_tty
)
5577 struct gdbarch_info info
;
5578 gdbarch_info_init (&info
);
5579 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5580 mips_fpu_type_auto
= 0;
5581 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5582 instead of relying on globals. Doing that would let generic code
5583 handle the search for this specific architecture. */
5584 if (!gdbarch_update_p (info
))
5585 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5589 set_mipsfpu_none_command (char *args
, int from_tty
)
5591 struct gdbarch_info info
;
5592 gdbarch_info_init (&info
);
5593 mips_fpu_type
= MIPS_FPU_NONE
;
5594 mips_fpu_type_auto
= 0;
5595 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5596 instead of relying on globals. Doing that would let generic code
5597 handle the search for this specific architecture. */
5598 if (!gdbarch_update_p (info
))
5599 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5603 set_mipsfpu_auto_command (char *args
, int from_tty
)
5605 mips_fpu_type_auto
= 1;
5608 /* Attempt to identify the particular processor model by reading the
5609 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5610 the relevant processor still exists (it dates back to '94) and
5611 secondly this is not the way to do this. The processor type should
5612 be set by forcing an architecture change. */
5615 deprecated_mips_set_processor_regs_hack (void)
5617 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5620 prid
= read_register (PRID_REGNUM
);
5622 if ((prid
& ~0xf) == 0x700)
5623 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5626 /* Just like reinit_frame_cache, but with the right arguments to be
5627 callable as an sfunc. */
5630 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5631 struct cmd_list_element
*c
)
5633 reinit_frame_cache ();
5637 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5639 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5640 mips_extra_func_info_t proc_desc
;
5642 /* Search for the function containing this address. Set the low bit
5643 of the address when searching, in case we were given an even address
5644 that is the start of a 16-bit function. If we didn't do this,
5645 the search would fail because the symbol table says the function
5646 starts at an odd address, i.e. 1 byte past the given address. */
5647 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5648 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5650 /* Make an attempt to determine if this is a 16-bit function. If
5651 the procedure descriptor exists and the address therein is odd,
5652 it's definitely a 16-bit function. Otherwise, we have to just
5653 guess that if the address passed in is odd, it's 16-bits. */
5654 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5655 disassembler needs to be able to locally determine the ISA, and
5656 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5660 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5661 info
->mach
= bfd_mach_mips16
;
5665 if (pc_is_mips16 (memaddr
))
5666 info
->mach
= bfd_mach_mips16
;
5669 /* Round down the instruction address to the appropriate boundary. */
5670 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5672 /* Set the disassembler options. */
5673 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5675 /* Set up the disassembler info, so that we get the right
5676 register names from libopcodes. */
5677 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5678 info
->disassembler_options
= "gpr-names=n32";
5680 info
->disassembler_options
= "gpr-names=64";
5681 info
->flavour
= bfd_target_elf_flavour
;
5684 /* This string is not recognized explicitly by the disassembler,
5685 but it tells the disassembler to not try to guess the ABI from
5686 the bfd elf headers, such that, if the user overrides the ABI
5687 of a program linked as NewABI, the disassembly will follow the
5688 register naming conventions specified by the user. */
5689 info
->disassembler_options
= "gpr-names=32";
5691 /* Call the appropriate disassembler based on the target endian-ness. */
5692 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5693 return print_insn_big_mips (memaddr
, info
);
5695 return print_insn_little_mips (memaddr
, info
);
5698 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5699 counter value to determine whether a 16- or 32-bit breakpoint should be
5700 used. It returns a pointer to a string of bytes that encode a breakpoint
5701 instruction, stores the length of the string to *lenptr, and adjusts pc
5702 (if necessary) to point to the actual memory location where the
5703 breakpoint should be inserted. */
5705 static const unsigned char *
5706 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5708 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5710 if (pc_is_mips16 (*pcptr
))
5712 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5713 *pcptr
= unmake_mips16_addr (*pcptr
);
5714 *lenptr
= sizeof (mips16_big_breakpoint
);
5715 return mips16_big_breakpoint
;
5719 /* The IDT board uses an unusual breakpoint value, and
5720 sometimes gets confused when it sees the usual MIPS
5721 breakpoint instruction. */
5722 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5723 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5724 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5726 *lenptr
= sizeof (big_breakpoint
);
5728 if (strcmp (target_shortname
, "mips") == 0)
5729 return idt_big_breakpoint
;
5730 else if (strcmp (target_shortname
, "ddb") == 0
5731 || strcmp (target_shortname
, "pmon") == 0
5732 || strcmp (target_shortname
, "lsi") == 0)
5733 return pmon_big_breakpoint
;
5735 return big_breakpoint
;
5740 if (pc_is_mips16 (*pcptr
))
5742 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5743 *pcptr
= unmake_mips16_addr (*pcptr
);
5744 *lenptr
= sizeof (mips16_little_breakpoint
);
5745 return mips16_little_breakpoint
;
5749 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5750 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5751 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5753 *lenptr
= sizeof (little_breakpoint
);
5755 if (strcmp (target_shortname
, "mips") == 0)
5756 return idt_little_breakpoint
;
5757 else if (strcmp (target_shortname
, "ddb") == 0
5758 || strcmp (target_shortname
, "pmon") == 0
5759 || strcmp (target_shortname
, "lsi") == 0)
5760 return pmon_little_breakpoint
;
5762 return little_breakpoint
;
5767 /* If PC is in a mips16 call or return stub, return the address of the target
5768 PC, which is either the callee or the caller. There are several
5769 cases which must be handled:
5771 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5772 target PC is in $31 ($ra).
5773 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5774 and the target PC is in $2.
5775 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5776 before the jal instruction, this is effectively a call stub
5777 and the the target PC is in $2. Otherwise this is effectively
5778 a return stub and the target PC is in $18.
5780 See the source code for the stubs in gcc/config/mips/mips16.S for
5783 This function implements the SKIP_TRAMPOLINE_CODE macro.
5787 mips_skip_stub (CORE_ADDR pc
)
5790 CORE_ADDR start_addr
;
5792 /* Find the starting address and name of the function containing the PC. */
5793 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5796 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5797 target PC is in $31 ($ra). */
5798 if (strcmp (name
, "__mips16_ret_sf") == 0
5799 || strcmp (name
, "__mips16_ret_df") == 0)
5800 return read_signed_register (RA_REGNUM
);
5802 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5804 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5805 and the target PC is in $2. */
5806 if (name
[19] >= '0' && name
[19] <= '9')
5807 return read_signed_register (2);
5809 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5810 before the jal instruction, this is effectively a call stub
5811 and the the target PC is in $2. Otherwise this is effectively
5812 a return stub and the target PC is in $18. */
5813 else if (name
[19] == 's' || name
[19] == 'd')
5815 if (pc
== start_addr
)
5817 /* Check if the target of the stub is a compiler-generated
5818 stub. Such a stub for a function bar might have a name
5819 like __fn_stub_bar, and might look like this:
5824 la $1,bar (becomes a lui/addiu pair)
5826 So scan down to the lui/addi and extract the target
5827 address from those two instructions. */
5829 CORE_ADDR target_pc
= read_signed_register (2);
5833 /* See if the name of the target function is __fn_stub_*. */
5834 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5837 if (strncmp (name
, "__fn_stub_", 10) != 0
5838 && strcmp (name
, "etext") != 0
5839 && strcmp (name
, "_etext") != 0)
5842 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5843 The limit on the search is arbitrarily set to 20
5844 instructions. FIXME. */
5845 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5847 inst
= mips_fetch_instruction (target_pc
);
5848 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5849 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5850 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5851 return pc
| (inst
& 0xffff); /* low word */
5854 /* Couldn't find the lui/addui pair, so return stub address. */
5858 /* This is the 'return' part of a call stub. The return
5859 address is in $r18. */
5860 return read_signed_register (18);
5863 return 0; /* not a stub */
5867 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5868 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5871 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5873 CORE_ADDR start_addr
;
5875 /* Find the starting address of the function containing the PC. If the
5876 caller didn't give us a name, look it up at the same time. */
5877 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5881 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5883 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5884 if (name
[19] >= '0' && name
[19] <= '9')
5886 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5887 before the jal instruction, this is effectively a call stub. */
5888 else if (name
[19] == 's' || name
[19] == 'd')
5889 return pc
== start_addr
;
5892 return 0; /* not a stub */
5896 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5897 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5900 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5902 CORE_ADDR start_addr
;
5904 /* Find the starting address of the function containing the PC. */
5905 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5908 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5909 if (strcmp (name
, "__mips16_ret_sf") == 0
5910 || strcmp (name
, "__mips16_ret_df") == 0)
5913 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5914 i.e. after the jal instruction, this is effectively a return stub. */
5915 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5916 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5919 return 0; /* not a stub */
5923 /* Return non-zero if the PC is in a library helper function that
5924 should be ignored. This implements the
5925 DEPRECATED_IGNORE_HELPER_CALL macro. */
5928 mips_ignore_helper (CORE_ADDR pc
)
5932 /* Find the starting address and name of the function containing the PC. */
5933 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5936 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5937 that we want to ignore. */
5938 return (strcmp (name
, "__mips16_ret_sf") == 0
5939 || strcmp (name
, "__mips16_ret_df") == 0);
5943 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5944 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5947 mips_stab_reg_to_regnum (int num
)
5950 if (num
>= 0 && num
< 32)
5952 else if (num
>= 38 && num
< 70)
5953 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5955 regnum
= mips_regnum (current_gdbarch
)->hi
;
5957 regnum
= mips_regnum (current_gdbarch
)->lo
;
5959 /* This will hopefully (eventually) provoke a warning. Should
5960 we be calling complaint() here? */
5961 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5962 return NUM_REGS
+ regnum
;
5966 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5967 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5970 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5973 if (num
>= 0 && num
< 32)
5975 else if (num
>= 32 && num
< 64)
5976 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5978 regnum
= mips_regnum (current_gdbarch
)->hi
;
5980 regnum
= mips_regnum (current_gdbarch
)->lo
;
5982 /* This will hopefully (eventually) provoke a warning. Should we
5983 be calling complaint() here? */
5984 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5985 return NUM_REGS
+ regnum
;
5989 mips_register_sim_regno (int regnum
)
5991 /* Only makes sense to supply raw registers. */
5992 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5993 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5994 decide if it is valid. Should instead define a standard sim/gdb
5995 register numbering scheme. */
5996 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5997 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
6000 return LEGACY_SIM_REGNO_IGNORE
;
6004 /* Convert an integer into an address. By first converting the value
6005 into a pointer and then extracting it signed, the address is
6006 guarenteed to be correctly sign extended. */
6009 mips_integer_to_address (struct type
*type
, void *buf
)
6011 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
6012 LONGEST val
= unpack_long (type
, buf
);
6013 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
6014 return extract_signed_integer (tmp
,
6015 TYPE_LENGTH (builtin_type_void_data_ptr
));
6019 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
6021 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
6022 const char *name
= bfd_get_section_name (abfd
, sect
);
6024 if (*abip
!= MIPS_ABI_UNKNOWN
)
6027 if (strncmp (name
, ".mdebug.", 8) != 0)
6030 if (strcmp (name
, ".mdebug.abi32") == 0)
6031 *abip
= MIPS_ABI_O32
;
6032 else if (strcmp (name
, ".mdebug.abiN32") == 0)
6033 *abip
= MIPS_ABI_N32
;
6034 else if (strcmp (name
, ".mdebug.abi64") == 0)
6035 *abip
= MIPS_ABI_N64
;
6036 else if (strcmp (name
, ".mdebug.abiO64") == 0)
6037 *abip
= MIPS_ABI_O64
;
6038 else if (strcmp (name
, ".mdebug.eabi32") == 0)
6039 *abip
= MIPS_ABI_EABI32
;
6040 else if (strcmp (name
, ".mdebug.eabi64") == 0)
6041 *abip
= MIPS_ABI_EABI64
;
6043 warning ("unsupported ABI %s.", name
+ 8);
6046 static enum mips_abi
6047 global_mips_abi (void)
6051 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
6052 if (mips_abi_strings
[i
] == mips_abi_string
)
6053 return (enum mips_abi
) i
;
6055 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
6058 static struct gdbarch
*
6059 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6061 struct gdbarch
*gdbarch
;
6062 struct gdbarch_tdep
*tdep
;
6064 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
6066 enum mips_fpu_type fpu_type
;
6068 /* First of all, extract the elf_flags, if available. */
6069 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6070 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6071 else if (arches
!= NULL
)
6072 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6076 fprintf_unfiltered (gdb_stdlog
,
6077 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6079 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6080 switch ((elf_flags
& EF_MIPS_ABI
))
6082 case E_MIPS_ABI_O32
:
6083 found_abi
= MIPS_ABI_O32
;
6085 case E_MIPS_ABI_O64
:
6086 found_abi
= MIPS_ABI_O64
;
6088 case E_MIPS_ABI_EABI32
:
6089 found_abi
= MIPS_ABI_EABI32
;
6091 case E_MIPS_ABI_EABI64
:
6092 found_abi
= MIPS_ABI_EABI64
;
6095 if ((elf_flags
& EF_MIPS_ABI2
))
6096 found_abi
= MIPS_ABI_N32
;
6098 found_abi
= MIPS_ABI_UNKNOWN
;
6102 /* GCC creates a pseudo-section whose name describes the ABI. */
6103 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6104 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6106 /* If we have no useful BFD information, use the ABI from the last
6107 MIPS architecture (if there is one). */
6108 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6109 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6111 /* Try the architecture for any hint of the correct ABI. */
6112 if (found_abi
== MIPS_ABI_UNKNOWN
6113 && info
.bfd_arch_info
!= NULL
6114 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6116 switch (info
.bfd_arch_info
->mach
)
6118 case bfd_mach_mips3900
:
6119 found_abi
= MIPS_ABI_EABI32
;
6121 case bfd_mach_mips4100
:
6122 case bfd_mach_mips5000
:
6123 found_abi
= MIPS_ABI_EABI64
;
6125 case bfd_mach_mips8000
:
6126 case bfd_mach_mips10000
:
6127 /* On Irix, ELF64 executables use the N64 ABI. The
6128 pseudo-sections which describe the ABI aren't present
6129 on IRIX. (Even for executables created by gcc.) */
6130 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6131 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6132 found_abi
= MIPS_ABI_N64
;
6134 found_abi
= MIPS_ABI_N32
;
6140 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6143 /* What has the user specified from the command line? */
6144 wanted_abi
= global_mips_abi ();
6146 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6149 /* Now that we have found what the ABI for this binary would be,
6150 check whether the user is overriding it. */
6151 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6152 mips_abi
= wanted_abi
;
6153 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6154 mips_abi
= found_abi
;
6156 mips_abi
= MIPS_ABI_O32
;
6158 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6161 /* Also used when doing an architecture lookup. */
6163 fprintf_unfiltered (gdb_stdlog
,
6164 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
6165 mips64_transfers_32bit_regs_p
);
6167 /* Determine the MIPS FPU type. */
6168 if (!mips_fpu_type_auto
)
6169 fpu_type
= mips_fpu_type
;
6170 else if (info
.bfd_arch_info
!= NULL
6171 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6172 switch (info
.bfd_arch_info
->mach
)
6174 case bfd_mach_mips3900
:
6175 case bfd_mach_mips4100
:
6176 case bfd_mach_mips4111
:
6177 case bfd_mach_mips4120
:
6178 fpu_type
= MIPS_FPU_NONE
;
6180 case bfd_mach_mips4650
:
6181 fpu_type
= MIPS_FPU_SINGLE
;
6184 fpu_type
= MIPS_FPU_DOUBLE
;
6187 else if (arches
!= NULL
)
6188 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6190 fpu_type
= MIPS_FPU_DOUBLE
;
6192 fprintf_unfiltered (gdb_stdlog
,
6193 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6195 /* try to find a pre-existing architecture */
6196 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6198 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6200 /* MIPS needs to be pedantic about which ABI the object is
6202 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6204 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6206 /* Need to be pedantic about which register virtual size is
6208 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6209 != mips64_transfers_32bit_regs_p
)
6211 /* Be pedantic about which FPU is selected. */
6212 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6214 return arches
->gdbarch
;
6217 /* Need a new architecture. Fill in a target specific vector. */
6218 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6219 gdbarch
= gdbarch_alloc (&info
, tdep
);
6220 tdep
->elf_flags
= elf_flags
;
6221 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6222 tdep
->found_abi
= found_abi
;
6223 tdep
->mips_abi
= mips_abi
;
6224 tdep
->mips_fpu_type
= fpu_type
;
6226 /* Initially set everything according to the default ABI/ISA. */
6227 set_gdbarch_short_bit (gdbarch
, 16);
6228 set_gdbarch_int_bit (gdbarch
, 32);
6229 set_gdbarch_float_bit (gdbarch
, 32);
6230 set_gdbarch_double_bit (gdbarch
, 64);
6231 set_gdbarch_long_double_bit (gdbarch
, 64);
6232 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6233 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6234 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6236 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6237 mips_elf_make_msymbol_special
);
6239 /* Fill in the OS dependant register numbers and names. */
6241 const char **reg_names
;
6242 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6243 struct mips_regnum
);
6244 if (info
.osabi
== GDB_OSABI_IRIX
)
6249 regnum
->badvaddr
= 66;
6252 regnum
->fp_control_status
= 69;
6253 regnum
->fp_implementation_revision
= 70;
6255 reg_names
= mips_irix_reg_names
;
6259 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6260 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6261 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6262 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6263 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6264 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6265 regnum
->fp_control_status
= 70;
6266 regnum
->fp_implementation_revision
= 71;
6268 if (info
.bfd_arch_info
!= NULL
6269 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6270 reg_names
= mips_tx39_reg_names
;
6272 reg_names
= mips_generic_reg_names
;
6274 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6275 replaced by read_pc? */
6276 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6277 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6278 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6279 set_gdbarch_num_regs (gdbarch
, num_regs
);
6280 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6281 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6282 tdep
->mips_processor_reg_names
= reg_names
;
6283 tdep
->regnum
= regnum
;
6289 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6290 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6291 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6292 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6293 tdep
->default_mask_address_p
= 0;
6294 set_gdbarch_long_bit (gdbarch
, 32);
6295 set_gdbarch_ptr_bit (gdbarch
, 32);
6296 set_gdbarch_long_long_bit (gdbarch
, 64);
6299 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6300 set_gdbarch_deprecated_store_return_value (gdbarch
,
6301 mips_o64_store_return_value
);
6302 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6303 mips_o64_extract_return_value
);
6304 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6305 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6306 tdep
->default_mask_address_p
= 0;
6307 set_gdbarch_long_bit (gdbarch
, 32);
6308 set_gdbarch_ptr_bit (gdbarch
, 32);
6309 set_gdbarch_long_long_bit (gdbarch
, 64);
6310 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
6312 case MIPS_ABI_EABI32
:
6313 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6314 set_gdbarch_deprecated_store_return_value (gdbarch
,
6315 mips_eabi_store_return_value
);
6316 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6317 mips_eabi_extract_return_value
);
6318 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6319 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6320 tdep
->default_mask_address_p
= 0;
6321 set_gdbarch_long_bit (gdbarch
, 32);
6322 set_gdbarch_ptr_bit (gdbarch
, 32);
6323 set_gdbarch_long_long_bit (gdbarch
, 64);
6324 set_gdbarch_deprecated_reg_struct_has_addr
6325 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6326 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6328 case MIPS_ABI_EABI64
:
6329 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6330 set_gdbarch_deprecated_store_return_value (gdbarch
,
6331 mips_eabi_store_return_value
);
6332 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6333 mips_eabi_extract_return_value
);
6334 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6335 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6336 tdep
->default_mask_address_p
= 0;
6337 set_gdbarch_long_bit (gdbarch
, 64);
6338 set_gdbarch_ptr_bit (gdbarch
, 64);
6339 set_gdbarch_long_long_bit (gdbarch
, 64);
6340 set_gdbarch_deprecated_reg_struct_has_addr
6341 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6342 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6345 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6346 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6347 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6348 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6349 tdep
->default_mask_address_p
= 0;
6350 set_gdbarch_long_bit (gdbarch
, 32);
6351 set_gdbarch_ptr_bit (gdbarch
, 32);
6352 set_gdbarch_long_long_bit (gdbarch
, 64);
6353 set_gdbarch_long_double_bit (gdbarch
, 128);
6354 set_gdbarch_long_double_format (gdbarch
,
6355 &floatformat_n32n64_long_double_big
);
6358 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6359 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6360 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6361 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6362 tdep
->default_mask_address_p
= 0;
6363 set_gdbarch_long_bit (gdbarch
, 64);
6364 set_gdbarch_ptr_bit (gdbarch
, 64);
6365 set_gdbarch_long_long_bit (gdbarch
, 64);
6366 set_gdbarch_long_double_bit (gdbarch
, 128);
6367 set_gdbarch_long_double_format (gdbarch
,
6368 &floatformat_n32n64_long_double_big
);
6371 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6374 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6375 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6378 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6379 flag in object files because to do so would make it impossible to
6380 link with libraries compiled without "-gp32". This is
6381 unnecessarily restrictive.
6383 We could solve this problem by adding "-gp32" multilibs to gcc,
6384 but to set this flag before gcc is built with such multilibs will
6385 break too many systems.''
6387 But even more unhelpfully, the default linker output target for
6388 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6389 for 64-bit programs - you need to change the ABI to change this,
6390 and not all gcc targets support that currently. Therefore using
6391 this flag to detect 32-bit mode would do the wrong thing given
6392 the current gcc - it would make GDB treat these 64-bit programs
6393 as 32-bit programs by default. */
6395 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6396 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6397 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6399 /* Add/remove bits from an address. The MIPS needs be careful to
6400 ensure that all 32 bit addresses are sign extended to 64 bits. */
6401 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6403 /* Unwind the frame. */
6404 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6405 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6407 /* Map debug register numbers onto internal register numbers. */
6408 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6409 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6410 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6411 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6412 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6413 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6414 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6415 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6417 /* MIPS version of CALL_DUMMY */
6419 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6420 replaced by a command, and all targets will default to on stack
6421 (regardless of the stack's execute status). */
6422 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6423 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6425 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6426 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6427 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6429 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6430 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6432 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6434 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6435 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6436 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6438 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6440 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6442 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6444 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6445 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6446 need to all be folded into the target vector. Since they are
6447 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6448 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6450 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6452 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6454 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6455 to support MIPS16. This is a bad thing. Make sure not to do it
6456 if we have an OS ABI that actually supports shared libraries, since
6457 shared library support is more important. If we have an OS someday
6458 that supports both shared libraries and MIPS16, we'll have to find
6459 a better place for these. */
6460 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6462 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6463 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6466 /* Hook in OS ABI-specific overrides, if they have been registered. */
6467 gdbarch_init_osabi (info
, gdbarch
);
6469 /* Unwind the frame. */
6470 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6471 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6472 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6473 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6474 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6475 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6476 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6477 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6483 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6485 struct gdbarch_info info
;
6487 /* Force the architecture to update, and (if it's a MIPS architecture)
6488 mips_gdbarch_init will take care of the rest. */
6489 gdbarch_info_init (&info
);
6490 gdbarch_update_p (info
);
6493 /* Print out which MIPS ABI is in use. */
6496 show_mips_abi (char *ignore_args
, int from_tty
)
6498 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6500 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6503 enum mips_abi global_abi
= global_mips_abi ();
6504 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6505 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6507 if (global_abi
== MIPS_ABI_UNKNOWN
)
6509 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6511 else if (global_abi
== actual_abi
)
6513 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6517 /* Probably shouldn't happen... */
6519 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6520 actual_abi_str
, mips_abi_strings
[global_abi
]);
6526 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6528 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6532 int ef_mips_32bitmode
;
6533 /* determine the ISA */
6534 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6552 /* determine the size of a pointer */
6553 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6554 fprintf_unfiltered (file
,
6555 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6557 fprintf_unfiltered (file
,
6558 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6560 fprintf_unfiltered (file
,
6561 "mips_dump_tdep: ef_mips_arch = %d\n",
6563 fprintf_unfiltered (file
,
6564 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6565 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6566 fprintf_unfiltered (file
,
6567 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6568 mips_mask_address_p (tdep
),
6569 tdep
->default_mask_address_p
);
6571 fprintf_unfiltered (file
,
6572 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6573 MIPS_DEFAULT_FPU_TYPE
,
6574 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6575 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6576 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6578 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6579 fprintf_unfiltered (file
,
6580 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6582 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6583 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6584 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6586 fprintf_unfiltered (file
,
6587 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6588 mips_stack_argsize (current_gdbarch
));
6589 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6590 fprintf_unfiltered (file
,
6591 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6592 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6593 fprintf_unfiltered (file
,
6594 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6595 XSTRING (ATTACH_DETACH
));
6596 fprintf_unfiltered (file
,
6597 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6598 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6599 fprintf_unfiltered (file
,
6600 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6601 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6602 fprintf_unfiltered (file
,
6603 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6604 FIRST_EMBED_REGNUM
);
6605 fprintf_unfiltered (file
,
6606 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6607 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6608 fprintf_unfiltered (file
,
6609 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6610 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6611 fprintf_unfiltered (file
,
6612 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6613 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6614 fprintf_unfiltered (file
,
6615 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6617 #ifdef MACHINE_CPROC_FP_OFFSET
6618 fprintf_unfiltered (file
,
6619 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6620 MACHINE_CPROC_FP_OFFSET
);
6622 #ifdef MACHINE_CPROC_PC_OFFSET
6623 fprintf_unfiltered (file
,
6624 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6625 MACHINE_CPROC_PC_OFFSET
);
6627 #ifdef MACHINE_CPROC_SP_OFFSET
6628 fprintf_unfiltered (file
,
6629 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6630 MACHINE_CPROC_SP_OFFSET
);
6632 fprintf_unfiltered (file
,
6633 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6635 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6636 fprintf_unfiltered (file
,
6637 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6638 fprintf_unfiltered (file
,
6639 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6640 fprintf_unfiltered (file
,
6641 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6642 MIPS_LAST_ARG_REGNUM
,
6643 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6644 fprintf_unfiltered (file
,
6645 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6646 fprintf_unfiltered (file
,
6647 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6648 mips_abi_regsize (current_gdbarch
));
6649 fprintf_unfiltered (file
,
6650 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6651 fprintf_unfiltered (file
,
6652 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6653 fprintf_unfiltered (file
,
6654 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6655 fprintf_unfiltered (file
,
6656 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6657 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6658 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6659 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6660 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6661 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6662 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6663 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6664 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6665 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6666 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6667 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6669 fprintf_unfiltered (file
,
6670 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6673 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6676 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6678 fprintf_unfiltered (file
,
6679 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6680 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6681 fprintf_unfiltered (file
,
6682 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6683 fprintf_unfiltered (file
,
6684 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6685 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6686 fprintf_unfiltered (file
,
6687 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6688 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6689 fprintf_unfiltered (file
,
6690 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6691 SOFTWARE_SINGLE_STEP_P ());
6692 fprintf_unfiltered (file
,
6693 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6694 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6695 #ifdef STACK_END_ADDR
6696 fprintf_unfiltered (file
,
6697 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6700 fprintf_unfiltered (file
,
6701 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6702 XSTRING (STEP_SKIPS_DELAY (PC
)));
6703 fprintf_unfiltered (file
,
6704 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6705 STEP_SKIPS_DELAY_P
);
6706 fprintf_unfiltered (file
,
6707 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6708 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6709 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6710 fprintf_unfiltered (file
,
6711 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6712 fprintf_unfiltered (file
,
6713 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6714 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6715 (TYPE
, CNT
, OTHERTYPE
)));
6716 fprintf_unfiltered (file
,
6717 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6718 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6720 fprintf_unfiltered (file
,
6721 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6722 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6725 fprintf_unfiltered (file
,
6726 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6728 #ifdef TRACE_FLAVOR_SIZE
6729 fprintf_unfiltered (file
,
6730 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6734 fprintf_unfiltered (file
,
6735 "mips_dump_tdep: TRACE_SET # %s\n",
6736 XSTRING (TRACE_SET (X
, STATE
)));
6738 #ifdef UNUSED_REGNUM
6739 fprintf_unfiltered (file
,
6740 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6742 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6743 fprintf_unfiltered (file
,
6744 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6745 (long) VM_MIN_ADDRESS
);
6746 fprintf_unfiltered (file
,
6747 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6748 fprintf_unfiltered (file
,
6749 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6752 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6755 _initialize_mips_tdep (void)
6757 static struct cmd_list_element
*mipsfpulist
= NULL
;
6758 struct cmd_list_element
*c
;
6760 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6761 if (MIPS_ABI_LAST
+ 1
6762 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6763 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6765 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6767 mips_pdr_data
= register_objfile_data ();
6769 /* Add root prefix command for all "set mips"/"show mips" commands */
6770 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6771 "Various MIPS specific commands.",
6772 &setmipscmdlist
, "set mips ", 0, &setlist
);
6774 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6775 "Various MIPS specific commands.",
6776 &showmipscmdlist
, "show mips ", 0, &showlist
);
6778 /* Allow the user to override the saved register size. */
6779 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6782 &mips_abi_regsize_string
, "\
6783 Set size of general purpose registers saved on the stack.\n\
6784 This option can be set to one of:\n\
6785 32 - Force GDB to treat saved GP registers as 32-bit\n\
6786 64 - Force GDB to treat saved GP registers as 64-bit\n\
6787 auto - Allow GDB to use the target's default setting or autodetect the\n\
6788 saved GP register size from information contained in the executable.\n\
6789 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6791 /* Allow the user to override the argument stack size. */
6792 deprecated_add_show_from_set
6793 (add_set_enum_cmd ("stack-arg-size",
6796 &mips_stack_argsize_string
, "\
6797 Set the amount of stack space reserved for each argument.\n\
6798 This option can be set to one of:\n\
6799 32 - Force GDB to allocate 32-bit chunks per argument\n\
6800 64 - Force GDB to allocate 64-bit chunks per argument\n\
6801 auto - Allow GDB to determine the correct setting from the current\n\
6802 target and executable (default)", &setmipscmdlist
),
6805 /* Allow the user to override the ABI. */
6806 c
= add_set_enum_cmd
6807 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6808 "Set the ABI used by this program.\n"
6809 "This option can be set to one of:\n"
6810 " auto - the default ABI associated with the current binary\n"
6812 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6813 set_cmd_sfunc (c
, mips_abi_update
);
6814 add_cmd ("abi", class_obscure
, show_mips_abi
,
6815 "Show ABI in use by MIPS target", &showmipscmdlist
);
6817 /* Let the user turn off floating point and set the fence post for
6818 heuristic_proc_start. */
6820 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6821 "Set use of MIPS floating-point coprocessor.",
6822 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6823 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6824 "Select single-precision MIPS floating-point coprocessor.",
6826 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6827 "Select double-precision MIPS floating-point coprocessor.",
6829 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6830 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6831 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6832 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6833 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6834 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6835 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6836 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6837 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6838 "Select MIPS floating-point coprocessor automatically.",
6840 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6841 "Show current use of MIPS floating-point coprocessor target.",
6844 /* We really would like to have both "0" and "unlimited" work, but
6845 command.c doesn't deal with that. So make it a var_zinteger
6846 because the user can always use "999999" or some such for unlimited. */
6847 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6848 (char *) &heuristic_fence_post
, "\
6849 Set the distance searched for the start of a function.\n\
6850 If you are debugging a stripped executable, GDB needs to search through the\n\
6851 program for the start of a function. This command sets the distance of the\n\
6852 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6853 /* We need to throw away the frame cache when we set this, since it
6854 might change our ability to get backtraces. */
6855 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6856 deprecated_add_show_from_set (c
, &showlist
);
6858 /* Allow the user to control whether the upper bits of 64-bit
6859 addresses should be zeroed. */
6860 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6861 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6862 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6863 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6864 allow GDB to determine the correct value.\n", "\
6865 Zerroing of upper 32 bits of 64-bit address is %s.",
6866 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6868 /* Allow the user to control the size of 32 bit registers within the
6869 raw remote packet. */
6870 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6871 &mips64_transfers_32bit_regs_p
, "\
6872 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6873 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6874 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6875 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6876 64 bits for others. Use \"off\" to disable compatibility mode", "\
6877 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6878 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6880 /* Debug this files internals. */
6881 deprecated_add_show_from_set
6882 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6883 &mips_debug
, "Set mips debugging.\n\
6884 When non-zero, mips specific debugging is enabled.", &setdebuglist
),