1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *const mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 const struct register_alias mips_numeric_register_aliases
[] = {
146 #define R(n) { #n, n }
147 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
148 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
149 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
150 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
154 #ifndef MIPS_DEFAULT_FPU_TYPE
155 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157 static int mips_fpu_type_auto
= 1;
158 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
160 static int mips_debug
= 0;
162 /* Properties (for struct target_desc) describing the g/G packet
164 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
165 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
167 struct target_desc
*mips_tdesc_gp32
;
168 struct target_desc
*mips_tdesc_gp64
;
170 const struct mips_regnum
*
171 mips_regnum (struct gdbarch
*gdbarch
)
173 return gdbarch_tdep (gdbarch
)->regnum
;
177 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
179 return mips_regnum (gdbarch
)->fp0
+ 12;
182 /* Return 1 if REGNUM refers to a floating-point general register, raw
183 or cooked. Otherwise return 0. */
186 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
188 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
190 return (rawnum
>= mips_regnum (gdbarch
)->fp0
191 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
194 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
196 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
198 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
199 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
201 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
202 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
204 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
206 /* Return the MIPS ABI associated with GDBARCH. */
208 mips_abi (struct gdbarch
*gdbarch
)
210 return gdbarch_tdep (gdbarch
)->mips_abi
;
214 mips_isa_regsize (struct gdbarch
*gdbarch
)
216 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
218 /* If we know how big the registers are, use that size. */
219 if (tdep
->register_size_valid_p
)
220 return tdep
->register_size
;
222 /* Fall back to the previous behavior. */
223 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
224 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
227 /* Return the currently configured (or set) saved register size. */
230 mips_abi_regsize (struct gdbarch
*gdbarch
)
232 switch (mips_abi (gdbarch
))
234 case MIPS_ABI_EABI32
:
240 case MIPS_ABI_EABI64
:
242 case MIPS_ABI_UNKNOWN
:
245 internal_error (__FILE__
, __LINE__
, _("bad switch"));
249 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
250 functions to test, set, or clear bit 0 of addresses. */
253 is_mips16_addr (CORE_ADDR addr
)
259 unmake_mips16_addr (CORE_ADDR addr
)
261 return ((addr
) & ~(CORE_ADDR
) 1);
265 make_mips16_addr (CORE_ADDR addr
)
267 return ((addr
) | (CORE_ADDR
) 1);
270 /* Functions for setting and testing a bit in a minimal symbol that
271 marks it as 16-bit function. The MSB of the minimal symbol's
272 "info" field is used for this purpose.
274 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
275 i.e. refers to a 16-bit function, and sets a "special" bit in a
276 minimal symbol to mark it as a 16-bit function
278 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
281 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
283 if (ELF_ST_IS_MIPS16 (((elf_symbol_type
*)
284 (sym
))->internal_elf_sym
.st_other
))
286 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
291 msymbol_is_special (struct minimal_symbol
*msym
)
293 return MSYMBOL_TARGET_FLAG_1 (msym
);
296 /* XFER a value from the big/little/left end of the register.
297 Depending on the size of the value it might occupy the entire
298 register or just part of it. Make an allowance for this, aligning
299 things accordingly. */
302 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
303 int reg_num
, int length
,
304 enum bfd_endian endian
, gdb_byte
*in
,
305 const gdb_byte
*out
, int buf_offset
)
309 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
310 /* Need to transfer the left or right part of the register, based on
311 the targets byte order. */
315 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
317 case BFD_ENDIAN_LITTLE
:
320 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
324 internal_error (__FILE__
, __LINE__
, _("bad switch"));
327 fprintf_unfiltered (gdb_stderr
,
328 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
329 reg_num
, reg_offset
, buf_offset
, length
);
330 if (mips_debug
&& out
!= NULL
)
333 fprintf_unfiltered (gdb_stdlog
, "out ");
334 for (i
= 0; i
< length
; i
++)
335 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
338 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
341 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
343 if (mips_debug
&& in
!= NULL
)
346 fprintf_unfiltered (gdb_stdlog
, "in ");
347 for (i
= 0; i
< length
; i
++)
348 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
351 fprintf_unfiltered (gdb_stdlog
, "\n");
354 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
355 compatiblity mode. A return value of 1 means that we have
356 physical 64-bit registers, but should treat them as 32-bit registers. */
359 mips2_fp_compat (struct frame_info
*frame
)
361 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
362 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
364 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
368 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
369 in all the places we deal with FP registers. PR gdb/413. */
370 /* Otherwise check the FR bit in the status register - it controls
371 the FP compatiblity mode. If it is clear we are in compatibility
373 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
380 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
382 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
384 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
386 /* The list of available "set mips " and "show mips " commands. */
388 static struct cmd_list_element
*setmipscmdlist
= NULL
;
389 static struct cmd_list_element
*showmipscmdlist
= NULL
;
391 /* Integer registers 0 thru 31 are handled explicitly by
392 mips_register_name(). Processor specific registers 32 and above
393 are listed in the following tables. */
396 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
400 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
401 "sr", "lo", "hi", "bad", "cause", "pc",
402 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
403 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
404 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
405 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
409 /* Names of IDT R3041 registers. */
411 static const char *mips_r3041_reg_names
[] = {
412 "sr", "lo", "hi", "bad", "cause", "pc",
413 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
414 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
415 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
416 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
417 "fsr", "fir", "", /*"fp" */ "",
418 "", "", "bus", "ccfg", "", "", "", "",
419 "", "", "port", "cmp", "", "", "epc", "prid",
422 /* Names of tx39 registers. */
424 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
425 "sr", "lo", "hi", "bad", "cause", "pc",
426 "", "", "", "", "", "", "", "",
427 "", "", "", "", "", "", "", "",
428 "", "", "", "", "", "", "", "",
429 "", "", "", "", "", "", "", "",
431 "", "", "", "", "", "", "", "",
432 "", "", "config", "cache", "debug", "depc", "epc",
435 /* Names of IRIX registers. */
436 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
437 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
438 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
439 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
440 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
441 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
444 /* Names of registers with Linux kernels. */
445 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
446 "sr", "lo", "hi", "bad", "cause", "pc",
447 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
448 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
449 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
450 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
455 /* Return the name of the register corresponding to REGNO. */
457 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
459 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
460 /* GPR names for all ABIs other than n32/n64. */
461 static char *mips_gpr_names
[] = {
462 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
463 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
464 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
465 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
468 /* GPR names for n32 and n64 ABIs. */
469 static char *mips_n32_n64_gpr_names
[] = {
470 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
471 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
472 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
473 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
476 enum mips_abi abi
= mips_abi (gdbarch
);
478 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
479 but then don't make the raw register names visible. This (upper)
480 range of user visible register numbers are the pseudo-registers.
482 This approach was adopted accommodate the following scenario:
483 It is possible to debug a 64-bit device using a 32-bit
484 programming model. In such instances, the raw registers are
485 configured to be 64-bits wide, while the pseudo registers are
486 configured to be 32-bits wide. The registers that the user
487 sees - the pseudo registers - match the users expectations
488 given the programming model being used. */
489 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
490 if (regno
< gdbarch_num_regs (gdbarch
))
493 /* The MIPS integer registers are always mapped from 0 to 31. The
494 names of the registers (which reflects the conventions regarding
495 register use) vary depending on the ABI. */
496 if (0 <= rawnum
&& rawnum
< 32)
498 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
499 return mips_n32_n64_gpr_names
[rawnum
];
501 return mips_gpr_names
[rawnum
];
503 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
504 return tdesc_register_name (gdbarch
, rawnum
);
505 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
507 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
508 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
509 return tdep
->mips_processor_reg_names
[rawnum
- 32];
513 internal_error (__FILE__
, __LINE__
,
514 _("mips_register_name: bad register number %d"), rawnum
);
517 /* Return the groups that a MIPS register can be categorised into. */
520 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
521 struct reggroup
*reggroup
)
526 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
527 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
528 if (reggroup
== all_reggroup
)
530 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
531 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
532 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
533 (gdbarch), as not all architectures are multi-arch. */
534 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
535 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
536 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
538 if (reggroup
== float_reggroup
)
539 return float_p
&& pseudo
;
540 if (reggroup
== vector_reggroup
)
541 return vector_p
&& pseudo
;
542 if (reggroup
== general_reggroup
)
543 return (!vector_p
&& !float_p
) && pseudo
;
544 /* Save the pseudo registers. Need to make certain that any code
545 extracting register values from a saved register cache also uses
547 if (reggroup
== save_reggroup
)
548 return raw_p
&& pseudo
;
549 /* Restore the same pseudo register. */
550 if (reggroup
== restore_reggroup
)
551 return raw_p
&& pseudo
;
555 /* Return the groups that a MIPS register can be categorised into.
556 This version is only used if we have a target description which
557 describes real registers (and their groups). */
560 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
561 struct reggroup
*reggroup
)
563 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
564 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
567 /* Only save, restore, and display the pseudo registers. Need to
568 make certain that any code extracting register values from a
569 saved register cache also uses pseudo registers.
571 Note: saving and restoring the pseudo registers is slightly
572 strange; if we have 64 bits, we should save and restore all
573 64 bits. But this is hard and has little benefit. */
577 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
581 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
584 /* Map the symbol table registers which live in the range [1 *
585 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
586 registers. Take care of alignment and size problems. */
588 static enum register_status
589 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
590 int cookednum
, gdb_byte
*buf
)
592 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
593 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
594 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
595 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
596 return regcache_raw_read (regcache
, rawnum
, buf
);
597 else if (register_size (gdbarch
, rawnum
) >
598 register_size (gdbarch
, cookednum
))
600 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
601 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
604 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
606 enum register_status status
;
608 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
609 if (status
== REG_VALID
)
610 store_signed_integer (buf
, 4, byte_order
, regval
);
615 internal_error (__FILE__
, __LINE__
, _("bad register size"));
619 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
620 struct regcache
*regcache
, int cookednum
,
623 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
624 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
625 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
626 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
627 regcache_raw_write (regcache
, rawnum
, buf
);
628 else if (register_size (gdbarch
, rawnum
) >
629 register_size (gdbarch
, cookednum
))
631 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
632 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
635 /* Sign extend the shortened version of the register prior
636 to placing it in the raw register. This is required for
637 some mips64 parts in order to avoid unpredictable behavior. */
638 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
639 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
640 regcache_raw_write_signed (regcache
, rawnum
, regval
);
644 internal_error (__FILE__
, __LINE__
, _("bad register size"));
648 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
649 struct agent_expr
*ax
, int reg
)
651 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
652 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
653 && reg
< 2 * gdbarch_num_regs (gdbarch
));
655 ax_reg_mask (ax
, rawnum
);
661 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
662 struct agent_expr
*ax
, int reg
)
664 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
665 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
666 && reg
< 2 * gdbarch_num_regs (gdbarch
));
667 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
671 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
673 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
674 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
677 ax_simple (ax
, aop_lsh
);
680 ax_simple (ax
, aop_rsh_signed
);
684 internal_error (__FILE__
, __LINE__
, _("bad register size"));
689 /* Table to translate MIPS16 register field to actual register number. */
690 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
692 /* Heuristic_proc_start may hunt through the text section for a long
693 time across a 2400 baud serial line. Allows the user to limit this
696 static unsigned int heuristic_fence_post
= 0;
698 /* Number of bytes of storage in the actual machine representation for
699 register N. NOTE: This defines the pseudo register type so need to
700 rebuild the architecture vector. */
702 static int mips64_transfers_32bit_regs_p
= 0;
705 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
706 struct cmd_list_element
*c
)
708 struct gdbarch_info info
;
709 gdbarch_info_init (&info
);
710 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
711 instead of relying on globals. Doing that would let generic code
712 handle the search for this specific architecture. */
713 if (!gdbarch_update_p (info
))
715 mips64_transfers_32bit_regs_p
= 0;
716 error (_("32-bit compatibility mode not supported"));
720 /* Convert to/from a register and the corresponding memory value. */
722 /* This predicate tests for the case of an 8 byte floating point
723 value that is being transferred to or from a pair of floating point
724 registers each of which are (or are considered to be) only 4 bytes
727 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
730 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
731 && register_size (gdbarch
, regnum
) == 4
732 && mips_float_register_p (gdbarch
, regnum
)
733 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
736 /* This predicate tests for the case of a value of less than 8
737 bytes in width that is being transfered to or from an 8 byte
738 general purpose register. */
740 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
743 int num_regs
= gdbarch_num_regs (gdbarch
);
745 return (register_size (gdbarch
, regnum
) == 8
746 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
747 && TYPE_LENGTH (type
) < 8);
751 mips_convert_register_p (struct gdbarch
*gdbarch
,
752 int regnum
, struct type
*type
)
754 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
755 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
759 mips_register_to_value (struct frame_info
*frame
, int regnum
,
760 struct type
*type
, gdb_byte
*to
,
761 int *optimizedp
, int *unavailablep
)
763 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
765 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
767 get_frame_register (frame
, regnum
+ 0, to
+ 4);
768 get_frame_register (frame
, regnum
+ 1, to
+ 0);
770 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
771 optimizedp
, unavailablep
))
774 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
775 optimizedp
, unavailablep
))
777 *optimizedp
= *unavailablep
= 0;
780 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
782 int len
= TYPE_LENGTH (type
);
785 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
786 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
787 optimizedp
, unavailablep
))
790 *optimizedp
= *unavailablep
= 0;
795 internal_error (__FILE__
, __LINE__
,
796 _("mips_register_to_value: unrecognized case"));
801 mips_value_to_register (struct frame_info
*frame
, int regnum
,
802 struct type
*type
, const gdb_byte
*from
)
804 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
806 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
808 put_frame_register (frame
, regnum
+ 0, from
+ 4);
809 put_frame_register (frame
, regnum
+ 1, from
+ 0);
811 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
814 int len
= TYPE_LENGTH (type
);
816 /* Sign extend values, irrespective of type, that are stored to
817 a 64-bit general purpose register. (32-bit unsigned values
818 are stored as signed quantities within a 64-bit register.
819 When performing an operation, in compiled code, that combines
820 a 32-bit unsigned value with a signed 64-bit value, a type
821 conversion is first performed that zeroes out the high 32 bits.) */
822 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
825 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
827 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
828 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
829 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
833 if (from
[len
-1] & 0x80)
834 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
836 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
837 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
838 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
843 internal_error (__FILE__
, __LINE__
,
844 _("mips_value_to_register: unrecognized case"));
848 /* Return the GDB type object for the "standard" data type of data in
852 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
854 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
855 if (mips_float_register_p (gdbarch
, regnum
))
857 /* The floating-point registers raw, or cooked, always match
858 mips_isa_regsize(), and also map 1:1, byte for byte. */
859 if (mips_isa_regsize (gdbarch
) == 4)
860 return builtin_type (gdbarch
)->builtin_float
;
862 return builtin_type (gdbarch
)->builtin_double
;
864 else if (regnum
< gdbarch_num_regs (gdbarch
))
866 /* The raw or ISA registers. These are all sized according to
868 if (mips_isa_regsize (gdbarch
) == 4)
869 return builtin_type (gdbarch
)->builtin_int32
;
871 return builtin_type (gdbarch
)->builtin_int64
;
875 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
877 /* The cooked or ABI registers. These are sized according to
878 the ABI (with a few complications). */
879 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
880 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
881 return builtin_type (gdbarch
)->builtin_int32
;
882 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
883 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
884 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
885 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
886 /* The pseudo/cooked view of the embedded registers is always
887 32-bit. The raw view is handled below. */
888 return builtin_type (gdbarch
)->builtin_int32
;
889 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
890 /* The target, while possibly using a 64-bit register buffer,
891 is only transfering 32-bits of each integer register.
892 Reflect this in the cooked/pseudo (ABI) register value. */
893 return builtin_type (gdbarch
)->builtin_int32
;
894 else if (mips_abi_regsize (gdbarch
) == 4)
895 /* The ABI is restricted to 32-bit registers (the ISA could be
897 return builtin_type (gdbarch
)->builtin_int32
;
900 return builtin_type (gdbarch
)->builtin_int64
;
904 /* Return the GDB type for the pseudo register REGNUM, which is the
905 ABI-level view. This function is only called if there is a target
906 description which includes registers, so we know precisely the
907 types of hardware registers. */
910 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
912 const int num_regs
= gdbarch_num_regs (gdbarch
);
913 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
914 int rawnum
= regnum
% num_regs
;
915 struct type
*rawtype
;
917 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
919 /* Absent registers are still absent. */
920 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
921 if (TYPE_LENGTH (rawtype
) == 0)
924 if (rawnum
>= mips_regnum (gdbarch
)->fp0
925 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32)
926 /* Present the floating point registers however the hardware did;
927 do not try to convert between FPU layouts. */
930 /* Use pointer types for registers if we can. For n32 we can not,
931 since we do not have a 64-bit pointer type. */
932 if (mips_abi_regsize (gdbarch
)
933 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
935 if (rawnum
== MIPS_SP_REGNUM
936 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
937 return builtin_type (gdbarch
)->builtin_data_ptr
;
938 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
939 return builtin_type (gdbarch
)->builtin_func_ptr
;
942 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
943 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
944 || rawnum
== mips_regnum (gdbarch
)->lo
945 || rawnum
== mips_regnum (gdbarch
)->hi
946 || rawnum
== mips_regnum (gdbarch
)->badvaddr
947 || rawnum
== mips_regnum (gdbarch
)->cause
948 || rawnum
== mips_regnum (gdbarch
)->pc
949 || (mips_regnum (gdbarch
)->dspacc
!= -1
950 && rawnum
>= mips_regnum (gdbarch
)->dspacc
951 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
952 return builtin_type (gdbarch
)->builtin_int32
;
954 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
955 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
956 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
957 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
959 /* The pseudo/cooked view of embedded registers is always
960 32-bit, even if the target transfers 64-bit values for them.
961 New targets relying on XML descriptions should only transfer
962 the necessary 32 bits, but older versions of GDB expected 64,
963 so allow the target to provide 64 bits without interfering
964 with the displayed type. */
965 return builtin_type (gdbarch
)->builtin_int32
;
968 /* For all other registers, pass through the hardware type. */
972 /* Should the upper word of 64-bit addresses be zeroed? */
973 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
976 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
978 switch (mask_address_var
)
980 case AUTO_BOOLEAN_TRUE
:
982 case AUTO_BOOLEAN_FALSE
:
985 case AUTO_BOOLEAN_AUTO
:
986 return tdep
->default_mask_address_p
;
988 internal_error (__FILE__
, __LINE__
,
989 _("mips_mask_address_p: bad switch"));
995 show_mask_address (struct ui_file
*file
, int from_tty
,
996 struct cmd_list_element
*c
, const char *value
)
998 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
1000 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1001 switch (mask_address_var
)
1003 case AUTO_BOOLEAN_TRUE
:
1004 printf_filtered ("The 32 bit mips address mask is enabled\n");
1006 case AUTO_BOOLEAN_FALSE
:
1007 printf_filtered ("The 32 bit mips address mask is disabled\n");
1009 case AUTO_BOOLEAN_AUTO
:
1011 ("The 32 bit address mask is set automatically. Currently %s\n",
1012 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1015 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1020 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1023 mips_pc_is_mips16 (CORE_ADDR memaddr
)
1025 struct minimal_symbol
*sym
;
1027 /* A flag indicating that this is a MIPS16 function is stored by
1028 elfread.c in the high bit of the info field. Use this to decide
1029 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
1030 the address is set, assume this is a MIPS16 address. */
1031 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1033 return msymbol_is_special (sym
);
1035 return is_mips16_addr (memaddr
);
1038 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1040 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1041 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1042 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1043 static const char mips_str_call_stub
[] = "__call_stub_";
1044 static const char mips_str_fn_stub
[] = "__fn_stub_";
1046 /* This is used as a PIC thunk prefix. */
1048 static const char mips_str_pic
[] = ".pic.";
1050 /* Return non-zero if the PC is inside a call thunk (aka stub or
1051 trampoline) that should be treated as a temporary frame. */
1054 mips_in_frame_stub (CORE_ADDR pc
)
1056 CORE_ADDR start_addr
;
1059 /* Find the starting address of the function containing the PC. */
1060 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1063 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1064 if (strncmp (name
, mips_str_mips16_call_stub
,
1065 strlen (mips_str_mips16_call_stub
)) == 0)
1067 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1068 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1070 /* If the PC is in __fn_stub_*, this is a call stub. */
1071 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1074 return 0; /* Not a stub. */
1077 /* MIPS believes that the PC has a sign extended value. Perhaps the
1078 all registers should be sign extended for simplicity? */
1081 mips_read_pc (struct regcache
*regcache
)
1083 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1086 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1087 if (is_mips16_addr (pc
))
1088 pc
= unmake_mips16_addr (pc
);
1093 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1097 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1098 if (is_mips16_addr (pc
))
1099 pc
= unmake_mips16_addr (pc
);
1100 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1101 intermediate frames. In this case we can get the caller's address
1102 from $ra, or if $ra contains an address within a thunk as well, then
1103 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1104 and thus the caller's address is in $s2. */
1105 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1107 pc
= frame_unwind_register_signed
1108 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1109 if (is_mips16_addr (pc
))
1110 pc
= unmake_mips16_addr (pc
);
1111 if (mips_in_frame_stub (pc
))
1113 pc
= frame_unwind_register_signed
1114 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1115 if (is_mips16_addr (pc
))
1116 pc
= unmake_mips16_addr (pc
);
1123 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1125 return frame_unwind_register_signed
1126 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1129 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1130 dummy frame. The frame ID's base needs to match the TOS value
1131 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1134 static struct frame_id
1135 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1137 return frame_id_build
1138 (get_frame_register_signed (this_frame
,
1139 gdbarch_num_regs (gdbarch
)
1141 get_frame_pc (this_frame
));
1144 /* Implement the "write_pc" gdbarch method. */
1147 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1149 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1151 if (mips_pc_is_mips16 (pc
))
1152 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1154 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1157 /* Fetch and return instruction from the specified location. If the PC
1158 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1161 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1163 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1164 gdb_byte buf
[MIPS_INSN32_SIZE
];
1168 if (mips_pc_is_mips16 (addr
))
1170 instlen
= MIPS_INSN16_SIZE
;
1171 addr
= unmake_mips16_addr (addr
);
1174 instlen
= MIPS_INSN32_SIZE
;
1175 status
= target_read_memory (addr
, buf
, instlen
);
1177 memory_error (status
, addr
);
1178 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1181 /* These are the fields of 32 bit mips instructions. */
1182 #define mips32_op(x) (x >> 26)
1183 #define itype_op(x) (x >> 26)
1184 #define itype_rs(x) ((x >> 21) & 0x1f)
1185 #define itype_rt(x) ((x >> 16) & 0x1f)
1186 #define itype_immediate(x) (x & 0xffff)
1188 #define jtype_op(x) (x >> 26)
1189 #define jtype_target(x) (x & 0x03ffffff)
1191 #define rtype_op(x) (x >> 26)
1192 #define rtype_rs(x) ((x >> 21) & 0x1f)
1193 #define rtype_rt(x) ((x >> 16) & 0x1f)
1194 #define rtype_rd(x) ((x >> 11) & 0x1f)
1195 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1196 #define rtype_funct(x) (x & 0x3f)
1199 mips32_relative_offset (ULONGEST inst
)
1201 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1204 /* Determine the address of the next instruction executed after the INST
1205 floating condition branch instruction at PC. COUNT specifies the
1206 number of the floating condition bits tested by the branch. */
1209 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1210 ULONGEST inst
, CORE_ADDR pc
, int count
)
1212 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1213 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1214 int tf
= itype_rt (inst
) & 1;
1215 int mask
= (1 << count
) - 1;
1220 /* No way to handle; it'll most likely trap anyway. */
1223 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1224 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1226 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1227 pc
+= mips32_relative_offset (inst
);
1234 /* Determine where to set a single step breakpoint while considering
1235 branch prediction. */
1237 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1239 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1242 inst
= mips_fetch_instruction (gdbarch
, pc
);
1243 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1246 if (itype_op (inst
) >> 2 == 5)
1247 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1249 op
= (itype_op (inst
) & 0x03);
1259 goto greater_branch
;
1264 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1265 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1266 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1267 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 9
1268 && (itype_rt (inst
) & 2) == 0)
1269 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1270 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1271 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 10
1272 && (itype_rt (inst
) & 2) == 0)
1273 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1274 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1275 else if (itype_op (inst
) == 29)
1277 /* The new PC will be alternate mode. */
1281 reg
= jtype_target (inst
) << 2;
1282 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1283 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1286 pc
+= 4; /* Not a branch, next instruction is easy. */
1289 { /* This gets way messy. */
1291 /* Further subdivide into SPECIAL, REGIMM and other. */
1292 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1294 case 0: /* SPECIAL */
1295 op
= rtype_funct (inst
);
1300 /* Set PC to that address. */
1301 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1303 case 12: /* SYSCALL */
1305 struct gdbarch_tdep
*tdep
;
1307 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1308 if (tdep
->syscall_next_pc
!= NULL
)
1309 pc
= tdep
->syscall_next_pc (frame
);
1318 break; /* end SPECIAL */
1319 case 1: /* REGIMM */
1321 op
= itype_rt (inst
); /* branch condition */
1326 case 16: /* BLTZAL */
1327 case 18: /* BLTZALL */
1329 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1330 pc
+= mips32_relative_offset (inst
) + 4;
1332 pc
+= 8; /* after the delay slot */
1336 case 17: /* BGEZAL */
1337 case 19: /* BGEZALL */
1338 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1339 pc
+= mips32_relative_offset (inst
) + 4;
1341 pc
+= 8; /* after the delay slot */
1343 case 0x1c: /* BPOSGE32 */
1344 case 0x1e: /* BPOSGE64 */
1346 if (itype_rs (inst
) == 0)
1348 unsigned int pos
= (op
& 2) ? 64 : 32;
1349 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1352 /* No way to handle; it'll most likely trap anyway. */
1355 if ((get_frame_register_unsigned (frame
,
1356 dspctl
) & 0x7f) >= pos
)
1357 pc
+= mips32_relative_offset (inst
);
1362 /* All of the other instructions in the REGIMM category */
1367 break; /* end REGIMM */
1372 reg
= jtype_target (inst
) << 2;
1373 /* Upper four bits get never changed... */
1374 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1377 case 4: /* BEQ, BEQL */
1379 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1380 get_frame_register_signed (frame
, itype_rt (inst
)))
1381 pc
+= mips32_relative_offset (inst
) + 4;
1385 case 5: /* BNE, BNEL */
1387 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1388 get_frame_register_signed (frame
, itype_rt (inst
)))
1389 pc
+= mips32_relative_offset (inst
) + 4;
1393 case 6: /* BLEZ, BLEZL */
1394 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1395 pc
+= mips32_relative_offset (inst
) + 4;
1401 greater_branch
: /* BGTZ, BGTZL */
1402 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1403 pc
+= mips32_relative_offset (inst
) + 4;
1410 } /* mips32_next_pc */
1412 /* Decoding the next place to set a breakpoint is irregular for the
1413 mips 16 variant, but fortunately, there fewer instructions. We have
1414 to cope ith extensions for 16 bit instructions and a pair of actual
1415 32 bit instructions. We dont want to set a single step instruction
1416 on the extend instruction either. */
1418 /* Lots of mips16 instruction formats */
1419 /* Predicting jumps requires itype,ritype,i8type
1420 and their extensions extItype,extritype,extI8type. */
1421 enum mips16_inst_fmts
1423 itype
, /* 0 immediate 5,10 */
1424 ritype
, /* 1 5,3,8 */
1425 rrtype
, /* 2 5,3,3,5 */
1426 rritype
, /* 3 5,3,3,5 */
1427 rrrtype
, /* 4 5,3,3,3,2 */
1428 rriatype
, /* 5 5,3,3,1,4 */
1429 shifttype
, /* 6 5,3,3,3,2 */
1430 i8type
, /* 7 5,3,8 */
1431 i8movtype
, /* 8 5,3,3,5 */
1432 i8mov32rtype
, /* 9 5,3,5,3 */
1433 i64type
, /* 10 5,3,8 */
1434 ri64type
, /* 11 5,3,3,5 */
1435 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1436 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1437 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1438 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1439 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1440 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1441 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1442 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1443 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1444 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1446 /* I am heaping all the fields of the formats into one structure and
1447 then, only the fields which are involved in instruction extension. */
1451 unsigned int regx
; /* Function in i8 type. */
1456 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1457 for the bits which make up the immediate extension. */
1460 extended_offset (unsigned int extension
)
1464 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1466 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1468 value
|= extension
& 0x1f; /* Extract 4:0. */
1473 /* Only call this function if you know that this is an extendable
1474 instruction. It won't malfunction, but why make excess remote memory
1475 references? If the immediate operands get sign extended or something,
1476 do it after the extension is performed. */
1477 /* FIXME: Every one of these cases needs to worry about sign extension
1478 when the offset is to be used in relative addressing. */
1481 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1483 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1485 pc
&= 0xfffffffe; /* Clear the low order bit. */
1486 target_read_memory (pc
, buf
, 2);
1487 return extract_unsigned_integer (buf
, 2, byte_order
);
1491 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1492 unsigned int extension
,
1494 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1499 switch (insn_format
)
1506 value
= extended_offset ((extension
<< 16) | inst
);
1507 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1511 value
= inst
& 0x7ff;
1512 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
1521 { /* A register identifier and an offset. */
1522 /* Most of the fields are the same as I type but the
1523 immediate value is of a different length. */
1527 value
= extended_offset ((extension
<< 16) | inst
);
1528 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1532 value
= inst
& 0xff; /* 8 bits */
1533 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
1536 regx
= (inst
>> 8) & 0x07; /* i8 funct */
1542 unsigned long value
;
1543 unsigned int nexthalf
;
1544 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1545 value
= value
<< 16;
1546 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1555 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1557 upk
->offset
= offset
;
1564 add_offset_16 (CORE_ADDR pc
, int offset
)
1566 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1570 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1571 unsigned int extension
, unsigned int insn
)
1573 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1574 int op
= (insn
>> 11);
1577 case 2: /* Branch */
1580 struct upk_mips16 upk
;
1581 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1582 pc
+= (upk
.offset
<< 1) + 2;
1585 case 3: /* JAL , JALX - Watch out, these are 32 bit
1588 struct upk_mips16 upk
;
1589 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1590 pc
= add_offset_16 (pc
, upk
.offset
);
1591 if ((insn
>> 10) & 0x01) /* Exchange mode */
1592 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1599 struct upk_mips16 upk
;
1601 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1602 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1604 pc
+= (upk
.offset
<< 1) + 2;
1611 struct upk_mips16 upk
;
1613 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1614 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1616 pc
+= (upk
.offset
<< 1) + 2;
1621 case 12: /* I8 Formats btez btnez */
1623 struct upk_mips16 upk
;
1625 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1626 /* upk.regx contains the opcode */
1627 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1628 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1629 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1630 /* pc = add_offset_16(pc,upk.offset) ; */
1631 pc
+= (upk
.offset
<< 1) + 2;
1636 case 29: /* RR Formats JR, JALR, JALR-RA */
1638 struct upk_mips16 upk
;
1639 /* upk.fmt = rrtype; */
1644 upk
.regx
= (insn
>> 8) & 0x07;
1645 upk
.regy
= (insn
>> 5) & 0x07;
1646 if ((upk
.regy
& 1) == 0)
1647 reg
= mips16_to_32_reg
[upk
.regx
];
1649 reg
= 31; /* Function return instruction. */
1650 pc
= get_frame_register_signed (frame
, reg
);
1657 /* This is an instruction extension. Fetch the real instruction
1658 (which follows the extension) and decode things based on
1662 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1663 fetch_mips_16 (gdbarch
, pc
));
1676 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1678 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1679 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1680 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1683 /* The mips_next_pc function supports single_step when the remote
1684 target monitor or stub is not developed enough to do a single_step.
1685 It works by decoding the current instruction and predicting where a
1686 branch will go. This isnt hard because all the data is available.
1687 The MIPS32 and MIPS16 variants are quite different. */
1689 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1691 if (mips_pc_is_mips16 (pc
))
1692 return mips16_next_pc (frame
, pc
);
1694 return mips32_next_pc (frame
, pc
);
1697 struct mips_frame_cache
1700 struct trad_frame_saved_reg
*saved_regs
;
1703 /* Set a register's saved stack address in temp_saved_regs. If an
1704 address has already been set for this register, do nothing; this
1705 way we will only recognize the first save of a given register in a
1708 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1709 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1710 Strictly speaking, only the second range is used as it is only second
1711 range (the ABI instead of ISA registers) that comes into play when finding
1712 saved registers in a frame. */
1715 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1716 int regnum
, CORE_ADDR offset
)
1718 if (this_cache
!= NULL
1719 && this_cache
->saved_regs
[regnum
].addr
== -1)
1721 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1723 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1729 /* Fetch the immediate value from a MIPS16 instruction.
1730 If the previous instruction was an EXTEND, use it to extend
1731 the upper bits of the immediate value. This is a helper function
1732 for mips16_scan_prologue. */
1735 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1736 unsigned short inst
, /* current instruction */
1737 int nbits
, /* number of bits in imm field */
1738 int scale
, /* scale factor to be applied to imm */
1739 int is_signed
) /* is the imm field signed? */
1743 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1745 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1746 if (offset
& 0x8000) /* check for negative extend */
1747 offset
= 0 - (0x10000 - (offset
& 0xffff));
1748 return offset
| (inst
& 0x1f);
1752 int max_imm
= 1 << nbits
;
1753 int mask
= max_imm
- 1;
1754 int sign_bit
= max_imm
>> 1;
1756 offset
= inst
& mask
;
1757 if (is_signed
&& (offset
& sign_bit
))
1758 offset
= 0 - (max_imm
- offset
);
1759 return offset
* scale
;
1764 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1765 the associated FRAME_CACHE if not null.
1766 Return the address of the first instruction past the prologue. */
1769 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1770 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1771 struct frame_info
*this_frame
,
1772 struct mips_frame_cache
*this_cache
)
1775 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1777 long frame_offset
= 0; /* Size of stack frame. */
1778 long frame_adjust
= 0; /* Offset of FP from SP. */
1779 int frame_reg
= MIPS_SP_REGNUM
;
1780 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1781 unsigned inst
= 0; /* current instruction */
1782 unsigned entry_inst
= 0; /* the entry instruction */
1783 unsigned save_inst
= 0; /* the save instruction */
1786 int extend_bytes
= 0;
1787 int prev_extend_bytes
;
1788 CORE_ADDR end_prologue_addr
= 0;
1790 /* Can be called when there's no process, and hence when there's no
1792 if (this_frame
!= NULL
)
1793 sp
= get_frame_register_signed (this_frame
,
1794 gdbarch_num_regs (gdbarch
)
1799 if (limit_pc
> start_pc
+ 200)
1800 limit_pc
= start_pc
+ 200;
1802 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1804 /* Save the previous instruction. If it's an EXTEND, we'll extract
1805 the immediate offset extension from it in mips16_get_imm. */
1808 /* Fetch and decode the instruction. */
1809 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1811 /* Normally we ignore extend instructions. However, if it is
1812 not followed by a valid prologue instruction, then this
1813 instruction is not part of the prologue either. We must
1814 remember in this case to adjust the end_prologue_addr back
1816 if ((inst
& 0xf800) == 0xf000) /* extend */
1818 extend_bytes
= MIPS_INSN16_SIZE
;
1822 prev_extend_bytes
= extend_bytes
;
1825 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1826 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1828 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1829 if (offset
< 0) /* Negative stack adjustment? */
1830 frame_offset
-= offset
;
1832 /* Exit loop if a positive stack adjustment is found, which
1833 usually means that the stack cleanup code in the function
1834 epilogue is reached. */
1837 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1839 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1840 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1841 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1843 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1845 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1846 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1847 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1849 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1851 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1852 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1854 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1856 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1857 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1859 else if (inst
== 0x673d) /* move $s1, $sp */
1864 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1866 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1867 frame_addr
= sp
+ offset
;
1869 frame_adjust
= offset
;
1871 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1873 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1874 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1875 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1877 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1879 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1880 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1881 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1883 else if ((inst
& 0xf81f) == 0xe809
1884 && (inst
& 0x700) != 0x700) /* entry */
1885 entry_inst
= inst
; /* Save for later processing. */
1886 else if ((inst
& 0xff80) == 0x6480) /* save */
1888 save_inst
= inst
; /* Save for later processing. */
1889 if (prev_extend_bytes
) /* extend */
1890 save_inst
|= prev_inst
<< 16;
1892 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1893 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1894 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1896 /* This instruction is part of the prologue, but we don't
1897 need to do anything special to handle it. */
1901 /* This instruction is not an instruction typically found
1902 in a prologue, so we must have reached the end of the
1904 if (end_prologue_addr
== 0)
1905 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1909 /* The entry instruction is typically the first instruction in a function,
1910 and it stores registers at offsets relative to the value of the old SP
1911 (before the prologue). But the value of the sp parameter to this
1912 function is the new SP (after the prologue has been executed). So we
1913 can't calculate those offsets until we've seen the entire prologue,
1914 and can calculate what the old SP must have been. */
1915 if (entry_inst
!= 0)
1917 int areg_count
= (entry_inst
>> 8) & 7;
1918 int sreg_count
= (entry_inst
>> 6) & 3;
1920 /* The entry instruction always subtracts 32 from the SP. */
1923 /* Now we can calculate what the SP must have been at the
1924 start of the function prologue. */
1927 /* Check if a0-a3 were saved in the caller's argument save area. */
1928 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1930 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1931 offset
+= mips_abi_regsize (gdbarch
);
1934 /* Check if the ra register was pushed on the stack. */
1936 if (entry_inst
& 0x20)
1938 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1939 offset
-= mips_abi_regsize (gdbarch
);
1942 /* Check if the s0 and s1 registers were pushed on the stack. */
1943 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1945 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1946 offset
-= mips_abi_regsize (gdbarch
);
1950 /* The SAVE instruction is similar to ENTRY, except that defined by the
1951 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1952 size of the frame is specified as an immediate field of instruction
1953 and an extended variation exists which lets additional registers and
1954 frame space to be specified. The instruction always treats registers
1955 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1956 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1958 static int args_table
[16] = {
1959 0, 0, 0, 0, 1, 1, 1, 1,
1960 2, 2, 2, 0, 3, 3, 4, -1,
1962 static int astatic_table
[16] = {
1963 0, 1, 2, 3, 0, 1, 2, 3,
1964 0, 1, 2, 4, 0, 1, 0, -1,
1966 int aregs
= (save_inst
>> 16) & 0xf;
1967 int xsregs
= (save_inst
>> 24) & 0x7;
1968 int args
= args_table
[aregs
];
1969 int astatic
= astatic_table
[aregs
];
1974 warning (_("Invalid number of argument registers encoded in SAVE."));
1979 warning (_("Invalid number of static registers encoded in SAVE."));
1983 /* For standard SAVE the frame size of 0 means 128. */
1984 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1985 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1988 frame_offset
+= frame_size
;
1990 /* Now we can calculate what the SP must have been at the
1991 start of the function prologue. */
1994 /* Check if A0-A3 were saved in the caller's argument save area. */
1995 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1997 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1998 offset
+= mips_abi_regsize (gdbarch
);
2003 /* Check if the RA register was pushed on the stack. */
2004 if (save_inst
& 0x40)
2006 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2007 offset
-= mips_abi_regsize (gdbarch
);
2010 /* Check if the S8 register was pushed on the stack. */
2013 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2014 offset
-= mips_abi_regsize (gdbarch
);
2017 /* Check if S2-S7 were pushed on the stack. */
2018 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2020 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2021 offset
-= mips_abi_regsize (gdbarch
);
2024 /* Check if the S1 register was pushed on the stack. */
2025 if (save_inst
& 0x10)
2027 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2028 offset
-= mips_abi_regsize (gdbarch
);
2030 /* Check if the S0 register was pushed on the stack. */
2031 if (save_inst
& 0x20)
2033 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2034 offset
-= mips_abi_regsize (gdbarch
);
2037 /* Check if A0-A3 were pushed on the stack. */
2038 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2040 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2041 offset
-= mips_abi_regsize (gdbarch
);
2045 if (this_cache
!= NULL
)
2048 (get_frame_register_signed (this_frame
,
2049 gdbarch_num_regs (gdbarch
) + frame_reg
)
2050 + frame_offset
- frame_adjust
);
2051 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2052 be able to get rid of the assignment below, evetually. But it's
2053 still needed for now. */
2054 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2055 + mips_regnum (gdbarch
)->pc
]
2056 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2059 /* If we didn't reach the end of the prologue when scanning the function
2060 instructions, then set end_prologue_addr to the address of the
2061 instruction immediately after the last one we scanned. */
2062 if (end_prologue_addr
== 0)
2063 end_prologue_addr
= cur_pc
;
2065 return end_prologue_addr
;
2068 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2069 Procedures that use the 32-bit instruction set are handled by the
2070 mips_insn32 unwinder. */
2072 static struct mips_frame_cache
*
2073 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2075 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2076 struct mips_frame_cache
*cache
;
2078 if ((*this_cache
) != NULL
)
2079 return (*this_cache
);
2080 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2081 (*this_cache
) = cache
;
2082 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2084 /* Analyze the function prologue. */
2086 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2087 CORE_ADDR start_addr
;
2089 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2090 if (start_addr
== 0)
2091 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2092 /* We can't analyze the prologue if we couldn't find the begining
2094 if (start_addr
== 0)
2097 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2100 /* gdbarch_sp_regnum contains the value and not the address. */
2101 trad_frame_set_value (cache
->saved_regs
,
2102 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2105 return (*this_cache
);
2109 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2110 struct frame_id
*this_id
)
2112 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2114 /* This marks the outermost frame. */
2115 if (info
->base
== 0)
2117 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2120 static struct value
*
2121 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2122 void **this_cache
, int regnum
)
2124 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2126 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2130 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2131 struct frame_info
*this_frame
, void **this_cache
)
2133 CORE_ADDR pc
= get_frame_pc (this_frame
);
2134 if (mips_pc_is_mips16 (pc
))
2139 static const struct frame_unwind mips_insn16_frame_unwind
=
2142 default_frame_unwind_stop_reason
,
2143 mips_insn16_frame_this_id
,
2144 mips_insn16_frame_prev_register
,
2146 mips_insn16_frame_sniffer
2150 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2153 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2158 static const struct frame_base mips_insn16_frame_base
=
2160 &mips_insn16_frame_unwind
,
2161 mips_insn16_frame_base_address
,
2162 mips_insn16_frame_base_address
,
2163 mips_insn16_frame_base_address
2166 static const struct frame_base
*
2167 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2169 CORE_ADDR pc
= get_frame_pc (this_frame
);
2170 if (mips_pc_is_mips16 (pc
))
2171 return &mips_insn16_frame_base
;
2176 /* Mark all the registers as unset in the saved_regs array
2177 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2180 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2182 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2186 const int num_regs
= gdbarch_num_regs (gdbarch
);
2189 for (i
= 0; i
< num_regs
; i
++)
2191 this_cache
->saved_regs
[i
].addr
= -1;
2196 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2197 the associated FRAME_CACHE if not null.
2198 Return the address of the first instruction past the prologue. */
2201 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2202 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2203 struct frame_info
*this_frame
,
2204 struct mips_frame_cache
*this_cache
)
2207 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2211 int frame_reg
= MIPS_SP_REGNUM
;
2213 CORE_ADDR end_prologue_addr
= 0;
2214 int seen_sp_adjust
= 0;
2215 int load_immediate_bytes
= 0;
2216 int in_delay_slot
= 0;
2217 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2219 /* Can be called when there's no process, and hence when there's no
2221 if (this_frame
!= NULL
)
2222 sp
= get_frame_register_signed (this_frame
,
2223 gdbarch_num_regs (gdbarch
)
2228 if (limit_pc
> start_pc
+ 200)
2229 limit_pc
= start_pc
+ 200;
2234 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2236 unsigned long inst
, high_word
, low_word
;
2239 /* Fetch the instruction. */
2240 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2242 /* Save some code by pre-extracting some useful fields. */
2243 high_word
= (inst
>> 16) & 0xffff;
2244 low_word
= inst
& 0xffff;
2245 reg
= high_word
& 0x1f;
2247 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2248 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2249 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2251 if (low_word
& 0x8000) /* Negative stack adjustment? */
2252 frame_offset
+= 0x10000 - low_word
;
2254 /* Exit loop if a positive stack adjustment is found, which
2255 usually means that the stack cleanup code in the function
2256 epilogue is reached. */
2260 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2261 && !regsize_is_64_bits
)
2263 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2265 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2266 && regsize_is_64_bits
)
2268 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2269 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2271 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2273 /* Old gcc frame, r30 is virtual frame pointer. */
2274 if ((long) low_word
!= frame_offset
)
2275 frame_addr
= sp
+ low_word
;
2276 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2278 unsigned alloca_adjust
;
2281 frame_addr
= get_frame_register_signed
2282 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2284 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2285 if (alloca_adjust
> 0)
2287 /* FP > SP + frame_size. This may be because of
2288 an alloca or somethings similar. Fix sp to
2289 "pre-alloca" value, and try again. */
2290 sp
+= alloca_adjust
;
2291 /* Need to reset the status of all registers. Otherwise,
2292 we will hit a guard that prevents the new address
2293 for each register to be recomputed during the second
2295 reset_saved_regs (gdbarch
, this_cache
);
2300 /* move $30,$sp. With different versions of gas this will be either
2301 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2302 Accept any one of these. */
2303 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2305 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2306 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2308 unsigned alloca_adjust
;
2311 frame_addr
= get_frame_register_signed
2312 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2314 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2315 if (alloca_adjust
> 0)
2317 /* FP > SP + frame_size. This may be because of
2318 an alloca or somethings similar. Fix sp to
2319 "pre-alloca" value, and try again. */
2321 /* Need to reset the status of all registers. Otherwise,
2322 we will hit a guard that prevents the new address
2323 for each register to be recomputed during the second
2325 reset_saved_regs (gdbarch
, this_cache
);
2330 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2331 && !regsize_is_64_bits
)
2333 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2335 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2336 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2337 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2338 || high_word
== 0x3c1c /* lui $gp,n */
2339 || high_word
== 0x279c /* addiu $gp,$gp,n */
2340 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2341 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2344 /* These instructions are part of the prologue, but we don't
2345 need to do anything special to handle them. */
2347 /* The instructions below load $at or $t0 with an immediate
2348 value in preparation for a stack adjustment via
2349 subu $sp,$sp,[$at,$t0]. These instructions could also
2350 initialize a local variable, so we accept them only before
2351 a stack adjustment instruction was seen. */
2352 else if (!seen_sp_adjust
2353 && (high_word
== 0x3c01 /* lui $at,n */
2354 || high_word
== 0x3c08 /* lui $t0,n */
2355 || high_word
== 0x3421 /* ori $at,$at,n */
2356 || high_word
== 0x3508 /* ori $t0,$t0,n */
2357 || high_word
== 0x3401 /* ori $at,$zero,n */
2358 || high_word
== 0x3408 /* ori $t0,$zero,n */
2361 if (end_prologue_addr
== 0)
2362 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2366 /* This instruction is not an instruction typically found
2367 in a prologue, so we must have reached the end of the
2369 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2370 loop now? Why would we need to continue scanning the function
2372 if (end_prologue_addr
== 0)
2373 end_prologue_addr
= cur_pc
;
2375 /* Check for branches and jumps. For now, only jump to
2376 register are caught (i.e. returns). */
2377 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2381 /* If the previous instruction was a jump, we must have reached
2382 the end of the prologue by now. Stop scanning so that we do
2383 not go past the function return. */
2388 if (this_cache
!= NULL
)
2391 (get_frame_register_signed (this_frame
,
2392 gdbarch_num_regs (gdbarch
) + frame_reg
)
2394 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2395 this assignment below, eventually. But it's still needed
2397 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2398 + mips_regnum (gdbarch
)->pc
]
2399 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2403 /* If we didn't reach the end of the prologue when scanning the function
2404 instructions, then set end_prologue_addr to the address of the
2405 instruction immediately after the last one we scanned. */
2406 /* brobecker/2004-10-10: I don't think this would ever happen, but
2407 we may as well be careful and do our best if we have a null
2408 end_prologue_addr. */
2409 if (end_prologue_addr
== 0)
2410 end_prologue_addr
= cur_pc
;
2412 /* In a frameless function, we might have incorrectly
2413 skipped some load immediate instructions. Undo the skipping
2414 if the load immediate was not followed by a stack adjustment. */
2415 if (load_immediate_bytes
&& !seen_sp_adjust
)
2416 end_prologue_addr
-= load_immediate_bytes
;
2418 return end_prologue_addr
;
2421 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2422 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2423 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2426 static struct mips_frame_cache
*
2427 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2429 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2430 struct mips_frame_cache
*cache
;
2432 if ((*this_cache
) != NULL
)
2433 return (*this_cache
);
2435 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2436 (*this_cache
) = cache
;
2437 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2439 /* Analyze the function prologue. */
2441 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2442 CORE_ADDR start_addr
;
2444 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2445 if (start_addr
== 0)
2446 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2447 /* We can't analyze the prologue if we couldn't find the begining
2449 if (start_addr
== 0)
2452 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2455 /* gdbarch_sp_regnum contains the value and not the address. */
2456 trad_frame_set_value (cache
->saved_regs
,
2457 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2460 return (*this_cache
);
2464 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2465 struct frame_id
*this_id
)
2467 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2469 /* This marks the outermost frame. */
2470 if (info
->base
== 0)
2472 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2475 static struct value
*
2476 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2477 void **this_cache
, int regnum
)
2479 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2481 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2485 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2486 struct frame_info
*this_frame
, void **this_cache
)
2488 CORE_ADDR pc
= get_frame_pc (this_frame
);
2489 if (! mips_pc_is_mips16 (pc
))
2494 static const struct frame_unwind mips_insn32_frame_unwind
=
2497 default_frame_unwind_stop_reason
,
2498 mips_insn32_frame_this_id
,
2499 mips_insn32_frame_prev_register
,
2501 mips_insn32_frame_sniffer
2505 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2508 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2513 static const struct frame_base mips_insn32_frame_base
=
2515 &mips_insn32_frame_unwind
,
2516 mips_insn32_frame_base_address
,
2517 mips_insn32_frame_base_address
,
2518 mips_insn32_frame_base_address
2521 static const struct frame_base
*
2522 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2524 CORE_ADDR pc
= get_frame_pc (this_frame
);
2525 if (! mips_pc_is_mips16 (pc
))
2526 return &mips_insn32_frame_base
;
2531 static struct trad_frame_cache
*
2532 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2535 CORE_ADDR start_addr
;
2536 CORE_ADDR stack_addr
;
2537 struct trad_frame_cache
*this_trad_cache
;
2538 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2539 int num_regs
= gdbarch_num_regs (gdbarch
);
2541 if ((*this_cache
) != NULL
)
2542 return (*this_cache
);
2543 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2544 (*this_cache
) = this_trad_cache
;
2546 /* The return address is in the link register. */
2547 trad_frame_set_reg_realreg (this_trad_cache
,
2548 gdbarch_pc_regnum (gdbarch
),
2549 num_regs
+ MIPS_RA_REGNUM
);
2551 /* Frame ID, since it's a frameless / stackless function, no stack
2552 space is allocated and SP on entry is the current SP. */
2553 pc
= get_frame_pc (this_frame
);
2554 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2555 stack_addr
= get_frame_register_signed (this_frame
,
2556 num_regs
+ MIPS_SP_REGNUM
);
2557 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2559 /* Assume that the frame's base is the same as the
2561 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2563 return this_trad_cache
;
2567 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2568 struct frame_id
*this_id
)
2570 struct trad_frame_cache
*this_trad_cache
2571 = mips_stub_frame_cache (this_frame
, this_cache
);
2572 trad_frame_get_id (this_trad_cache
, this_id
);
2575 static struct value
*
2576 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2577 void **this_cache
, int regnum
)
2579 struct trad_frame_cache
*this_trad_cache
2580 = mips_stub_frame_cache (this_frame
, this_cache
);
2581 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2585 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2586 struct frame_info
*this_frame
, void **this_cache
)
2589 struct obj_section
*s
;
2590 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2591 struct minimal_symbol
*msym
;
2593 /* Use the stub unwinder for unreadable code. */
2594 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2597 if (in_plt_section (pc
, NULL
))
2600 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2601 s
= find_pc_section (pc
);
2604 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2605 ".MIPS.stubs") == 0)
2608 /* Calling a PIC function from a non-PIC function passes through a
2609 stub. The stub for foo is named ".pic.foo". */
2610 msym
= lookup_minimal_symbol_by_pc (pc
);
2612 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2613 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2619 static const struct frame_unwind mips_stub_frame_unwind
=
2622 default_frame_unwind_stop_reason
,
2623 mips_stub_frame_this_id
,
2624 mips_stub_frame_prev_register
,
2626 mips_stub_frame_sniffer
2630 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2633 struct trad_frame_cache
*this_trad_cache
2634 = mips_stub_frame_cache (this_frame
, this_cache
);
2635 return trad_frame_get_this_base (this_trad_cache
);
2638 static const struct frame_base mips_stub_frame_base
=
2640 &mips_stub_frame_unwind
,
2641 mips_stub_frame_base_address
,
2642 mips_stub_frame_base_address
,
2643 mips_stub_frame_base_address
2646 static const struct frame_base
*
2647 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2649 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2650 return &mips_stub_frame_base
;
2655 /* mips_addr_bits_remove - remove useless address bits */
2658 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2660 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2662 if (is_mips16_addr (addr
))
2663 addr
= unmake_mips16_addr (addr
);
2665 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2666 /* This hack is a work-around for existing boards using PMON, the
2667 simulator, and any other 64-bit targets that doesn't have true
2668 64-bit addressing. On these targets, the upper 32 bits of
2669 addresses are ignored by the hardware. Thus, the PC or SP are
2670 likely to have been sign extended to all 1s by instruction
2671 sequences that load 32-bit addresses. For example, a typical
2672 piece of code that loads an address is this:
2674 lui $r2, <upper 16 bits>
2675 ori $r2, <lower 16 bits>
2677 But the lui sign-extends the value such that the upper 32 bits
2678 may be all 1s. The workaround is simply to mask off these
2679 bits. In the future, gcc may be changed to support true 64-bit
2680 addressing, and this masking will have to be disabled. */
2681 return addr
&= 0xffffffffUL
;
2686 /* Instructions used during single-stepping of atomic sequences. */
2687 #define LL_OPCODE 0x30
2688 #define LLD_OPCODE 0x34
2689 #define SC_OPCODE 0x38
2690 #define SCD_OPCODE 0x3c
2692 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2693 instruction and ending with a SC/SCD instruction. If such a sequence
2694 is found, attempt to step through it. A breakpoint is placed at the end of
2698 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2699 struct address_space
*aspace
, CORE_ADDR pc
)
2701 CORE_ADDR breaks
[2] = {-1, -1};
2703 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2707 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2708 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2713 insn
= mips_fetch_instruction (gdbarch
, loc
);
2714 /* Assume all atomic sequences start with a ll/lld instruction. */
2715 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2718 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2720 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2723 loc
+= MIPS_INSN32_SIZE
;
2724 insn
= mips_fetch_instruction (gdbarch
, loc
);
2726 /* Assume that there is at most one branch in the atomic
2727 sequence. If a branch is found, put a breakpoint in its
2728 destination address. */
2729 switch (itype_op (insn
))
2731 case 0: /* SPECIAL */
2732 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2733 return 0; /* fallback to the standard single-step code. */
2735 case 1: /* REGIMM */
2736 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
2737 || ((itype_rt (insn
) & 0x1e) == 0
2738 && itype_rs (insn
) == 0)); /* BPOSGE* */
2742 return 0; /* fallback to the standard single-step code. */
2749 case 22: /* BLEZL */
2750 case 23: /* BGTTL */
2754 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
2755 && (itype_rt (insn
) & 0x2) == 0);
2756 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
2761 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2766 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2767 if (last_breakpoint
>= 1)
2768 return 0; /* More than one branch found, fallback to the
2769 standard single-step code. */
2770 breaks
[1] = branch_bp
;
2774 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2778 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2779 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2782 loc
+= MIPS_INSN32_SIZE
;
2784 /* Insert a breakpoint right after the end of the atomic sequence. */
2787 /* Check for duplicated breakpoints. Check also for a breakpoint
2788 placed (branch instruction's destination) in the atomic sequence. */
2789 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2790 last_breakpoint
= 0;
2792 /* Effectively inserts the breakpoints. */
2793 for (index
= 0; index
<= last_breakpoint
; index
++)
2794 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2799 /* mips_software_single_step() is called just before we want to resume
2800 the inferior, if we want to single-step it but there is no hardware
2801 or kernel single-step support (MIPS on GNU/Linux for example). We find
2802 the target of the coming instruction and breakpoint it. */
2805 mips_software_single_step (struct frame_info
*frame
)
2807 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2808 struct address_space
*aspace
= get_frame_address_space (frame
);
2809 CORE_ADDR pc
, next_pc
;
2811 pc
= get_frame_pc (frame
);
2812 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2815 next_pc
= mips_next_pc (frame
, pc
);
2817 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2821 /* Test whether the PC points to the return instruction at the
2822 end of a function. */
2825 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2830 /* This used to check for MIPS16, but this piece of code is never
2831 called for MIPS16 functions. */
2832 gdb_assert (!mips_pc_is_mips16 (pc
));
2834 insn
= mips_fetch_instruction (gdbarch
, pc
);
2836 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
2840 /* This fencepost looks highly suspicious to me. Removing it also
2841 seems suspicious as it could affect remote debugging across serial
2845 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2851 struct inferior
*inf
;
2853 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2855 fence
= start_pc
- heuristic_fence_post
;
2859 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2860 fence
= VM_MIN_ADDRESS
;
2862 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2864 inf
= current_inferior ();
2866 /* Search back for previous return. */
2867 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2868 if (start_pc
< fence
)
2870 /* It's not clear to me why we reach this point when
2871 stop_soon, but with this test, at least we
2872 don't print out warnings for every child forked (eg, on
2873 decstation). 22apr93 rich@cygnus.com. */
2874 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2876 static int blurb_printed
= 0;
2878 warning (_("GDB can't find the start of the function at %s."),
2879 paddress (gdbarch
, pc
));
2883 /* This actually happens frequently in embedded
2884 development, when you first connect to a board
2885 and your stack pointer and pc are nowhere in
2886 particular. This message needs to give people
2887 in that situation enough information to
2888 determine that it's no big deal. */
2889 printf_filtered ("\n\
2890 GDB is unable to find the start of the function at %s\n\
2891 and thus can't determine the size of that function's stack frame.\n\
2892 This means that GDB may be unable to access that stack frame, or\n\
2893 the frames below it.\n\
2894 This problem is most likely caused by an invalid program counter or\n\
2896 However, if you think GDB should simply search farther back\n\
2897 from %s for code which looks like the beginning of a\n\
2898 function, you can increase the range of the search using the `set\n\
2899 heuristic-fence-post' command.\n",
2900 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2907 else if (mips_pc_is_mips16 (start_pc
))
2909 unsigned short inst
;
2911 /* On MIPS16, any one of the following is likely to be the
2912 start of a function:
2918 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2919 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2920 if ((inst
& 0xff80) == 0x6480) /* save */
2922 if (start_pc
- instlen
>= fence
)
2924 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2925 if ((inst
& 0xf800) == 0xf000) /* extend */
2926 start_pc
-= instlen
;
2930 else if (((inst
& 0xf81f) == 0xe809
2931 && (inst
& 0x700) != 0x700) /* entry */
2932 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2933 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2934 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2936 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2937 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2942 else if (mips_about_to_return (gdbarch
, start_pc
))
2944 /* Skip return and its delay slot. */
2945 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2952 struct mips_objfile_private
2958 /* According to the current ABI, should the type be passed in a
2959 floating-point register (assuming that there is space)? When there
2960 is no FPU, FP are not even considered as possible candidates for
2961 FP registers and, consequently this returns false - forces FP
2962 arguments into integer registers. */
2965 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2966 struct type
*arg_type
)
2968 return ((typecode
== TYPE_CODE_FLT
2969 || (MIPS_EABI (gdbarch
)
2970 && (typecode
== TYPE_CODE_STRUCT
2971 || typecode
== TYPE_CODE_UNION
)
2972 && TYPE_NFIELDS (arg_type
) == 1
2973 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2975 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2978 /* On o32, argument passing in GPRs depends on the alignment of the type being
2979 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2982 mips_type_needs_double_align (struct type
*type
)
2984 enum type_code typecode
= TYPE_CODE (type
);
2986 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2988 else if (typecode
== TYPE_CODE_STRUCT
)
2990 if (TYPE_NFIELDS (type
) < 1)
2992 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2994 else if (typecode
== TYPE_CODE_UNION
)
2998 n
= TYPE_NFIELDS (type
);
2999 for (i
= 0; i
< n
; i
++)
3000 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3007 /* Adjust the address downward (direction of stack growth) so that it
3008 is correctly aligned for a new stack frame. */
3010 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3012 return align_down (addr
, 16);
3015 /* Implement the "push_dummy_code" gdbarch method. */
3018 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
3019 CORE_ADDR funaddr
, struct value
**args
,
3020 int nargs
, struct type
*value_type
,
3021 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
3022 struct regcache
*regcache
)
3025 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
3027 /* Reserve enough room on the stack for our breakpoint instruction. */
3028 *bp_addr
= sp
- sizeof (nop_insn
);
3030 /* The breakpoint layer automatically adjusts the address of
3031 breakpoints inserted in a branch delay slot. With enough
3032 bad luck, the 4 bytes located just before our breakpoint
3033 instruction could look like a branch instruction, and thus
3034 trigger the adjustement, and break the function call entirely.
3035 So, we reserve those 4 bytes and write a nop instruction
3036 to prevent that from happening. */
3037 nop_addr
= *bp_addr
- sizeof (nop_insn
);
3038 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
3039 sp
= mips_frame_align (gdbarch
, nop_addr
);
3041 /* Inferior resumes at the function entry point. */
3048 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3049 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3050 int nargs
, struct value
**args
, CORE_ADDR sp
,
3051 int struct_return
, CORE_ADDR struct_addr
)
3057 int stack_offset
= 0;
3058 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3059 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3060 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3061 int regsize
= mips_abi_regsize (gdbarch
);
3063 /* For shared libraries, "t9" needs to point at the function
3065 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3067 /* Set the return address register to point to the entry point of
3068 the program, where a breakpoint lies in wait. */
3069 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3071 /* First ensure that the stack and structure return address (if any)
3072 are properly aligned. The stack has to be at least 64-bit
3073 aligned even on 32-bit machines, because doubles must be 64-bit
3074 aligned. For n32 and n64, stack frames need to be 128-bit
3075 aligned, so we round to this widest known alignment. */
3077 sp
= align_down (sp
, 16);
3078 struct_addr
= align_down (struct_addr
, 16);
3080 /* Now make space on the stack for the args. We allocate more
3081 than necessary for EABI, because the first few arguments are
3082 passed in registers, but that's OK. */
3083 for (argnum
= 0; argnum
< nargs
; argnum
++)
3084 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
3085 sp
-= align_up (len
, 16);
3088 fprintf_unfiltered (gdb_stdlog
,
3089 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
3090 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3092 /* Initialize the integer and float register pointers. */
3093 argreg
= MIPS_A0_REGNUM
;
3094 float_argreg
= mips_fpa0_regnum (gdbarch
);
3096 /* The struct_return pointer occupies the first parameter-passing reg. */
3100 fprintf_unfiltered (gdb_stdlog
,
3101 "mips_eabi_push_dummy_call: "
3102 "struct_return reg=%d %s\n",
3103 argreg
, paddress (gdbarch
, struct_addr
));
3104 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3107 /* Now load as many as possible of the first arguments into
3108 registers, and push the rest onto the stack. Loop thru args
3109 from first to last. */
3110 for (argnum
= 0; argnum
< nargs
; argnum
++)
3112 const gdb_byte
*val
;
3113 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
3114 struct value
*arg
= args
[argnum
];
3115 struct type
*arg_type
= check_typedef (value_type (arg
));
3116 int len
= TYPE_LENGTH (arg_type
);
3117 enum type_code typecode
= TYPE_CODE (arg_type
);
3120 fprintf_unfiltered (gdb_stdlog
,
3121 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3122 argnum
+ 1, len
, (int) typecode
);
3124 /* Function pointer arguments to mips16 code need to be made into
3126 if (typecode
== TYPE_CODE_PTR
3127 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
3129 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
3131 if (mips_pc_is_mips16 (addr
))
3133 store_signed_integer (valbuf
, len
, byte_order
,
3134 make_mips16_addr (addr
));
3138 val
= value_contents (arg
);
3140 /* The EABI passes structures that do not fit in a register by
3142 else if (len
> regsize
3143 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3145 store_unsigned_integer (valbuf
, regsize
, byte_order
,
3146 value_address (arg
));
3147 typecode
= TYPE_CODE_PTR
;
3151 fprintf_unfiltered (gdb_stdlog
, " push");
3154 val
= value_contents (arg
);
3156 /* 32-bit ABIs always start floating point arguments in an
3157 even-numbered floating point register. Round the FP register
3158 up before the check to see if there are any FP registers
3159 left. Non MIPS_EABI targets also pass the FP in the integer
3160 registers so also round up normal registers. */
3161 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3163 if ((float_argreg
& 1))
3167 /* Floating point arguments passed in registers have to be
3168 treated specially. On 32-bit architectures, doubles
3169 are passed in register pairs; the even register gets
3170 the low word, and the odd register gets the high word.
3171 On non-EABI processors, the first two floating point arguments are
3172 also copied to general registers, because MIPS16 functions
3173 don't use float registers for arguments. This duplication of
3174 arguments in general registers can't hurt non-MIPS16 functions
3175 because those registers are normally skipped. */
3176 /* MIPS_EABI squeezes a struct that contains a single floating
3177 point value into an FP register instead of pushing it onto the
3179 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3180 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3182 /* EABI32 will pass doubles in consecutive registers, even on
3183 64-bit cores. At one time, we used to check the size of
3184 `float_argreg' to determine whether or not to pass doubles
3185 in consecutive registers, but this is not sufficient for
3186 making the ABI determination. */
3187 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3189 int low_offset
= gdbarch_byte_order (gdbarch
)
3190 == BFD_ENDIAN_BIG
? 4 : 0;
3193 /* Write the low word of the double to the even register(s). */
3194 regval
= extract_signed_integer (val
+ low_offset
,
3197 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3198 float_argreg
, phex (regval
, 4));
3199 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3201 /* Write the high word of the double to the odd register(s). */
3202 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3205 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3206 float_argreg
, phex (regval
, 4));
3207 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3211 /* This is a floating point value that fits entirely
3212 in a single register. */
3213 /* On 32 bit ABI's the float_argreg is further adjusted
3214 above to ensure that it is even register aligned. */
3215 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3217 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3218 float_argreg
, phex (regval
, len
));
3219 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3224 /* Copy the argument to general registers or the stack in
3225 register-sized pieces. Large arguments are split between
3226 registers and stack. */
3227 /* Note: structs whose size is not a multiple of regsize
3228 are treated specially: Irix cc passes
3229 them in registers where gcc sometimes puts them on the
3230 stack. For maximum compatibility, we will put them in
3232 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3234 /* Note: Floating-point values that didn't fit into an FP
3235 register are only written to memory. */
3238 /* Remember if the argument was written to the stack. */
3239 int stack_used_p
= 0;
3240 int partial_len
= (len
< regsize
? len
: regsize
);
3243 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3246 /* Write this portion of the argument to the stack. */
3247 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3249 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3251 /* Should shorter than int integer values be
3252 promoted to int before being stored? */
3253 int longword_offset
= 0;
3256 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3259 && (typecode
== TYPE_CODE_INT
3260 || typecode
== TYPE_CODE_PTR
3261 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3262 longword_offset
= regsize
- len
;
3263 else if ((typecode
== TYPE_CODE_STRUCT
3264 || typecode
== TYPE_CODE_UNION
)
3265 && TYPE_LENGTH (arg_type
) < regsize
)
3266 longword_offset
= regsize
- len
;
3271 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3272 paddress (gdbarch
, stack_offset
));
3273 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3274 paddress (gdbarch
, longword_offset
));
3277 addr
= sp
+ stack_offset
+ longword_offset
;
3282 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3283 paddress (gdbarch
, addr
));
3284 for (i
= 0; i
< partial_len
; i
++)
3286 fprintf_unfiltered (gdb_stdlog
, "%02x",
3290 write_memory (addr
, val
, partial_len
);
3293 /* Note!!! This is NOT an else clause. Odd sized
3294 structs may go thru BOTH paths. Floating point
3295 arguments will not. */
3296 /* Write this portion of the argument to a general
3297 purpose register. */
3298 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3299 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3302 extract_signed_integer (val
, partial_len
, byte_order
);
3305 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3307 phex (regval
, regsize
));
3308 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3315 /* Compute the offset into the stack at which we will
3316 copy the next parameter.
3318 In the new EABI (and the NABI32), the stack_offset
3319 only needs to be adjusted when it has been used. */
3322 stack_offset
+= align_up (partial_len
, regsize
);
3326 fprintf_unfiltered (gdb_stdlog
, "\n");
3329 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3331 /* Return adjusted stack pointer. */
3335 /* Determine the return value convention being used. */
3337 static enum return_value_convention
3338 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
3339 struct type
*type
, struct regcache
*regcache
,
3340 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3343 int fp_return_type
= 0;
3344 int offset
, regnum
, xfer
;
3346 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3347 return RETURN_VALUE_STRUCT_CONVENTION
;
3349 /* Floating point type? */
3350 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3352 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3354 /* Structs with a single field of float type
3355 are returned in a floating point register. */
3356 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3357 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3358 && TYPE_NFIELDS (type
) == 1)
3360 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3362 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3369 /* A floating-point value belongs in the least significant part
3372 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3373 regnum
= mips_regnum (gdbarch
)->fp0
;
3377 /* An integer value goes in V0/V1. */
3379 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3380 regnum
= MIPS_V0_REGNUM
;
3383 offset
< TYPE_LENGTH (type
);
3384 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3386 xfer
= mips_abi_regsize (gdbarch
);
3387 if (offset
+ xfer
> TYPE_LENGTH (type
))
3388 xfer
= TYPE_LENGTH (type
) - offset
;
3389 mips_xfer_register (gdbarch
, regcache
,
3390 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3391 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3395 return RETURN_VALUE_REGISTER_CONVENTION
;
3399 /* N32/N64 ABI stuff. */
3401 /* Search for a naturally aligned double at OFFSET inside a struct
3402 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3406 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3411 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3414 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3417 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3420 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3423 struct type
*field_type
;
3425 /* We're only looking at normal fields. */
3426 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3427 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3430 /* If we have gone past the offset, there is no double to pass. */
3431 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3435 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3437 /* If this field is entirely before the requested offset, go
3438 on to the next one. */
3439 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3442 /* If this is our special aligned double, we can stop. */
3443 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3444 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3447 /* This field starts at or before the requested offset, and
3448 overlaps it. If it is a structure, recurse inwards. */
3449 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3456 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3457 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3458 int nargs
, struct value
**args
, CORE_ADDR sp
,
3459 int struct_return
, CORE_ADDR struct_addr
)
3465 int stack_offset
= 0;
3466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3467 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3468 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3470 /* For shared libraries, "t9" needs to point at the function
3472 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3474 /* Set the return address register to point to the entry point of
3475 the program, where a breakpoint lies in wait. */
3476 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3478 /* First ensure that the stack and structure return address (if any)
3479 are properly aligned. The stack has to be at least 64-bit
3480 aligned even on 32-bit machines, because doubles must be 64-bit
3481 aligned. For n32 and n64, stack frames need to be 128-bit
3482 aligned, so we round to this widest known alignment. */
3484 sp
= align_down (sp
, 16);
3485 struct_addr
= align_down (struct_addr
, 16);
3487 /* Now make space on the stack for the args. */
3488 for (argnum
= 0; argnum
< nargs
; argnum
++)
3489 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3490 sp
-= align_up (len
, 16);
3493 fprintf_unfiltered (gdb_stdlog
,
3494 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3495 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3497 /* Initialize the integer and float register pointers. */
3498 argreg
= MIPS_A0_REGNUM
;
3499 float_argreg
= mips_fpa0_regnum (gdbarch
);
3501 /* The struct_return pointer occupies the first parameter-passing reg. */
3505 fprintf_unfiltered (gdb_stdlog
,
3506 "mips_n32n64_push_dummy_call: "
3507 "struct_return reg=%d %s\n",
3508 argreg
, paddress (gdbarch
, struct_addr
));
3509 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3512 /* Now load as many as possible of the first arguments into
3513 registers, and push the rest onto the stack. Loop thru args
3514 from first to last. */
3515 for (argnum
= 0; argnum
< nargs
; argnum
++)
3517 const gdb_byte
*val
;
3518 struct value
*arg
= args
[argnum
];
3519 struct type
*arg_type
= check_typedef (value_type (arg
));
3520 int len
= TYPE_LENGTH (arg_type
);
3521 enum type_code typecode
= TYPE_CODE (arg_type
);
3524 fprintf_unfiltered (gdb_stdlog
,
3525 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3526 argnum
+ 1, len
, (int) typecode
);
3528 val
= value_contents (arg
);
3530 /* A 128-bit long double value requires an even-odd pair of
3531 floating-point registers. */
3533 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3534 && (float_argreg
& 1))
3540 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3541 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3543 /* This is a floating point value that fits entirely
3544 in a single register or a pair of registers. */
3545 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3546 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3548 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3549 float_argreg
, phex (regval
, reglen
));
3550 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3553 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3554 argreg
, phex (regval
, reglen
));
3555 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3560 regval
= extract_unsigned_integer (val
+ reglen
,
3561 reglen
, byte_order
);
3563 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3564 float_argreg
, phex (regval
, reglen
));
3565 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3568 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3569 argreg
, phex (regval
, reglen
));
3570 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3577 /* Copy the argument to general registers or the stack in
3578 register-sized pieces. Large arguments are split between
3579 registers and stack. */
3580 /* For N32/N64, structs, unions, or other composite types are
3581 treated as a sequence of doublewords, and are passed in integer
3582 or floating point registers as though they were simple scalar
3583 parameters to the extent that they fit, with any excess on the
3584 stack packed according to the normal memory layout of the
3586 The caller does not reserve space for the register arguments;
3587 the callee is responsible for reserving it if required. */
3588 /* Note: Floating-point values that didn't fit into an FP
3589 register are only written to memory. */
3592 /* Remember if the argument was written to the stack. */
3593 int stack_used_p
= 0;
3594 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3597 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3600 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3601 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3603 /* Write this portion of the argument to the stack. */
3604 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3606 /* Should shorter than int integer values be
3607 promoted to int before being stored? */
3608 int longword_offset
= 0;
3611 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3613 if ((typecode
== TYPE_CODE_INT
3614 || typecode
== TYPE_CODE_PTR
)
3616 longword_offset
= MIPS64_REGSIZE
- len
;
3621 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3622 paddress (gdbarch
, stack_offset
));
3623 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3624 paddress (gdbarch
, longword_offset
));
3627 addr
= sp
+ stack_offset
+ longword_offset
;
3632 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3633 paddress (gdbarch
, addr
));
3634 for (i
= 0; i
< partial_len
; i
++)
3636 fprintf_unfiltered (gdb_stdlog
, "%02x",
3640 write_memory (addr
, val
, partial_len
);
3643 /* Note!!! This is NOT an else clause. Odd sized
3644 structs may go thru BOTH paths. */
3645 /* Write this portion of the argument to a general
3646 purpose register. */
3647 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3651 /* Sign extend pointers, 32-bit integers and signed
3652 16-bit and 8-bit integers; everything else is taken
3655 if ((partial_len
== 4
3656 && (typecode
== TYPE_CODE_PTR
3657 || typecode
== TYPE_CODE_INT
))
3659 && typecode
== TYPE_CODE_INT
3660 && !TYPE_UNSIGNED (arg_type
)))
3661 regval
= extract_signed_integer (val
, partial_len
,
3664 regval
= extract_unsigned_integer (val
, partial_len
,
3667 /* A non-floating-point argument being passed in a
3668 general register. If a struct or union, and if
3669 the remaining length is smaller than the register
3670 size, we have to adjust the register value on
3673 It does not seem to be necessary to do the
3674 same for integral types. */
3676 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3677 && partial_len
< MIPS64_REGSIZE
3678 && (typecode
== TYPE_CODE_STRUCT
3679 || typecode
== TYPE_CODE_UNION
))
3680 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3684 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3686 phex (regval
, MIPS64_REGSIZE
));
3687 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3689 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3690 TYPE_LENGTH (arg_type
) - len
))
3693 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3695 phex (regval
, MIPS64_REGSIZE
));
3696 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3707 /* Compute the offset into the stack at which we will
3708 copy the next parameter.
3710 In N32 (N64?), the stack_offset only needs to be
3711 adjusted when it has been used. */
3714 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3718 fprintf_unfiltered (gdb_stdlog
, "\n");
3721 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3723 /* Return adjusted stack pointer. */
3727 static enum return_value_convention
3728 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
3729 struct type
*type
, struct regcache
*regcache
,
3730 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3732 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3734 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3736 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3737 if needed), as appropriate for the type. Composite results (struct,
3738 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3741 * A struct with only one or two floating point fields is returned in $f0
3742 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3745 * Any other composite results of at most 128 bits are returned in
3746 $2 (first 64 bits) and $3 (remainder, if necessary).
3748 * Larger composite results are handled by converting the function to a
3749 procedure with an implicit first parameter, which is a pointer to an area
3750 reserved by the caller to receive the result. [The o32-bit ABI requires
3751 that all composite results be handled by conversion to implicit first
3752 parameters. The MIPS/SGI Fortran implementation has always made a
3753 specific exception to return COMPLEX results in the floating point
3756 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3757 return RETURN_VALUE_STRUCT_CONVENTION
;
3758 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3759 && TYPE_LENGTH (type
) == 16
3760 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3762 /* A 128-bit floating-point value fills both $f0 and $f2. The
3763 two registers are used in the same as memory order, so the
3764 eight bytes with the lower memory address are in $f0. */
3766 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3767 mips_xfer_register (gdbarch
, regcache
,
3768 (gdbarch_num_regs (gdbarch
)
3769 + mips_regnum (gdbarch
)->fp0
),
3770 8, gdbarch_byte_order (gdbarch
),
3771 readbuf
, writebuf
, 0);
3772 mips_xfer_register (gdbarch
, regcache
,
3773 (gdbarch_num_regs (gdbarch
)
3774 + mips_regnum (gdbarch
)->fp0
+ 2),
3775 8, gdbarch_byte_order (gdbarch
),
3776 readbuf
? readbuf
+ 8 : readbuf
,
3777 writebuf
? writebuf
+ 8 : writebuf
, 0);
3778 return RETURN_VALUE_REGISTER_CONVENTION
;
3780 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3781 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3783 /* A single or double floating-point value that fits in FP0. */
3785 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3786 mips_xfer_register (gdbarch
, regcache
,
3787 (gdbarch_num_regs (gdbarch
)
3788 + mips_regnum (gdbarch
)->fp0
),
3790 gdbarch_byte_order (gdbarch
),
3791 readbuf
, writebuf
, 0);
3792 return RETURN_VALUE_REGISTER_CONVENTION
;
3794 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3795 && TYPE_NFIELDS (type
) <= 2
3796 && TYPE_NFIELDS (type
) >= 1
3797 && ((TYPE_NFIELDS (type
) == 1
3798 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3800 || (TYPE_NFIELDS (type
) == 2
3801 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3803 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3804 == TYPE_CODE_FLT
))))
3806 /* A struct that contains one or two floats. Each value is part
3807 in the least significant part of their floating point
3808 register (or GPR, for soft float). */
3811 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3812 ? mips_regnum (gdbarch
)->fp0
3814 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3816 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3819 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3821 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3823 /* A 16-byte long double field goes in two consecutive
3825 mips_xfer_register (gdbarch
, regcache
,
3826 gdbarch_num_regs (gdbarch
) + regnum
,
3828 gdbarch_byte_order (gdbarch
),
3829 readbuf
, writebuf
, offset
);
3830 mips_xfer_register (gdbarch
, regcache
,
3831 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3833 gdbarch_byte_order (gdbarch
),
3834 readbuf
, writebuf
, offset
+ 8);
3837 mips_xfer_register (gdbarch
, regcache
,
3838 gdbarch_num_regs (gdbarch
) + regnum
,
3839 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3840 gdbarch_byte_order (gdbarch
),
3841 readbuf
, writebuf
, offset
);
3843 return RETURN_VALUE_REGISTER_CONVENTION
;
3845 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3846 || TYPE_CODE (type
) == TYPE_CODE_UNION
3847 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3849 /* A composite type. Extract the left justified value,
3850 regardless of the byte order. I.e. DO NOT USE
3854 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3855 offset
< TYPE_LENGTH (type
);
3856 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3858 int xfer
= register_size (gdbarch
, regnum
);
3859 if (offset
+ xfer
> TYPE_LENGTH (type
))
3860 xfer
= TYPE_LENGTH (type
) - offset
;
3862 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3863 offset
, xfer
, regnum
);
3864 mips_xfer_register (gdbarch
, regcache
,
3865 gdbarch_num_regs (gdbarch
) + regnum
,
3866 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3869 return RETURN_VALUE_REGISTER_CONVENTION
;
3873 /* A scalar extract each part but least-significant-byte
3877 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3878 offset
< TYPE_LENGTH (type
);
3879 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3881 int xfer
= register_size (gdbarch
, regnum
);
3882 if (offset
+ xfer
> TYPE_LENGTH (type
))
3883 xfer
= TYPE_LENGTH (type
) - offset
;
3885 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3886 offset
, xfer
, regnum
);
3887 mips_xfer_register (gdbarch
, regcache
,
3888 gdbarch_num_regs (gdbarch
) + regnum
,
3889 xfer
, gdbarch_byte_order (gdbarch
),
3890 readbuf
, writebuf
, offset
);
3892 return RETURN_VALUE_REGISTER_CONVENTION
;
3896 /* Which registers to use for passing floating-point values between
3897 function calls, one of floating-point, general and both kinds of
3898 registers. O32 and O64 use different register kinds for standard
3899 MIPS and MIPS16 code; to make the handling of cases where we may
3900 not know what kind of code is being used (e.g. no debug information)
3901 easier we sometimes use both kinds. */
3910 /* O32 ABI stuff. */
3913 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3914 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3915 int nargs
, struct value
**args
, CORE_ADDR sp
,
3916 int struct_return
, CORE_ADDR struct_addr
)
3922 int stack_offset
= 0;
3923 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3924 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3925 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3927 /* For shared libraries, "t9" needs to point at the function
3929 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3931 /* Set the return address register to point to the entry point of
3932 the program, where a breakpoint lies in wait. */
3933 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3935 /* First ensure that the stack and structure return address (if any)
3936 are properly aligned. The stack has to be at least 64-bit
3937 aligned even on 32-bit machines, because doubles must be 64-bit
3938 aligned. For n32 and n64, stack frames need to be 128-bit
3939 aligned, so we round to this widest known alignment. */
3941 sp
= align_down (sp
, 16);
3942 struct_addr
= align_down (struct_addr
, 16);
3944 /* Now make space on the stack for the args. */
3945 for (argnum
= 0; argnum
< nargs
; argnum
++)
3947 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3948 int arglen
= TYPE_LENGTH (arg_type
);
3950 /* Align to double-word if necessary. */
3951 if (mips_type_needs_double_align (arg_type
))
3952 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3953 /* Allocate space on the stack. */
3954 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3956 sp
-= align_up (len
, 16);
3959 fprintf_unfiltered (gdb_stdlog
,
3960 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3961 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3963 /* Initialize the integer and float register pointers. */
3964 argreg
= MIPS_A0_REGNUM
;
3965 float_argreg
= mips_fpa0_regnum (gdbarch
);
3967 /* The struct_return pointer occupies the first parameter-passing reg. */
3971 fprintf_unfiltered (gdb_stdlog
,
3972 "mips_o32_push_dummy_call: "
3973 "struct_return reg=%d %s\n",
3974 argreg
, paddress (gdbarch
, struct_addr
));
3975 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3976 stack_offset
+= MIPS32_REGSIZE
;
3979 /* Now load as many as possible of the first arguments into
3980 registers, and push the rest onto the stack. Loop thru args
3981 from first to last. */
3982 for (argnum
= 0; argnum
< nargs
; argnum
++)
3984 const gdb_byte
*val
;
3985 struct value
*arg
= args
[argnum
];
3986 struct type
*arg_type
= check_typedef (value_type (arg
));
3987 int len
= TYPE_LENGTH (arg_type
);
3988 enum type_code typecode
= TYPE_CODE (arg_type
);
3991 fprintf_unfiltered (gdb_stdlog
,
3992 "mips_o32_push_dummy_call: %d len=%d type=%d",
3993 argnum
+ 1, len
, (int) typecode
);
3995 val
= value_contents (arg
);
3997 /* 32-bit ABIs always start floating point arguments in an
3998 even-numbered floating point register. Round the FP register
3999 up before the check to see if there are any FP registers
4000 left. O32 targets also pass the FP in the integer registers
4001 so also round up normal registers. */
4002 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4004 if ((float_argreg
& 1))
4008 /* Floating point arguments passed in registers have to be
4009 treated specially. On 32-bit architectures, doubles are
4010 passed in register pairs; the even FP register gets the
4011 low word, and the odd FP register gets the high word.
4012 On O32, the first two floating point arguments are also
4013 copied to general registers, following their memory order,
4014 because MIPS16 functions don't use float registers for
4015 arguments. This duplication of arguments in general
4016 registers can't hurt non-MIPS16 functions, because those
4017 registers are normally skipped. */
4019 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4020 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4022 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
4024 int freg_offset
= gdbarch_byte_order (gdbarch
)
4025 == BFD_ENDIAN_BIG
? 1 : 0;
4026 unsigned long regval
;
4029 regval
= extract_unsigned_integer (val
, 4, byte_order
);
4031 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4032 float_argreg
+ freg_offset
,
4034 regcache_cooked_write_unsigned (regcache
,
4035 float_argreg
++ + freg_offset
,
4038 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4039 argreg
, phex (regval
, 4));
4040 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
4043 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
4045 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4046 float_argreg
- freg_offset
,
4048 regcache_cooked_write_unsigned (regcache
,
4049 float_argreg
++ - freg_offset
,
4052 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4053 argreg
, phex (regval
, 4));
4054 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
4058 /* This is a floating point value that fits entirely
4059 in a single register. */
4060 /* On 32 bit ABI's the float_argreg is further adjusted
4061 above to ensure that it is even register aligned. */
4062 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4064 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4065 float_argreg
, phex (regval
, len
));
4066 regcache_cooked_write_unsigned (regcache
,
4067 float_argreg
++, regval
);
4068 /* Although two FP registers are reserved for each
4069 argument, only one corresponding integer register is
4072 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4073 argreg
, phex (regval
, len
));
4074 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
4076 /* Reserve space for the FP register. */
4077 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
4081 /* Copy the argument to general registers or the stack in
4082 register-sized pieces. Large arguments are split between
4083 registers and stack. */
4084 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
4085 are treated specially: Irix cc passes
4086 them in registers where gcc sometimes puts them on the
4087 stack. For maximum compatibility, we will put them in
4089 int odd_sized_struct
= (len
> MIPS32_REGSIZE
4090 && len
% MIPS32_REGSIZE
!= 0);
4091 /* Structures should be aligned to eight bytes (even arg registers)
4092 on MIPS_ABI_O32, if their first member has double precision. */
4093 if (mips_type_needs_double_align (arg_type
))
4098 stack_offset
+= MIPS32_REGSIZE
;
4103 /* Remember if the argument was written to the stack. */
4104 int stack_used_p
= 0;
4105 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
4108 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4111 /* Write this portion of the argument to the stack. */
4112 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4113 || odd_sized_struct
)
4115 /* Should shorter than int integer values be
4116 promoted to int before being stored? */
4117 int longword_offset
= 0;
4123 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4124 paddress (gdbarch
, stack_offset
));
4125 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4126 paddress (gdbarch
, longword_offset
));
4129 addr
= sp
+ stack_offset
+ longword_offset
;
4134 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4135 paddress (gdbarch
, addr
));
4136 for (i
= 0; i
< partial_len
; i
++)
4138 fprintf_unfiltered (gdb_stdlog
, "%02x",
4142 write_memory (addr
, val
, partial_len
);
4145 /* Note!!! This is NOT an else clause. Odd sized
4146 structs may go thru BOTH paths. */
4147 /* Write this portion of the argument to a general
4148 purpose register. */
4149 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4151 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4153 /* Value may need to be sign extended, because
4154 mips_isa_regsize() != mips_abi_regsize(). */
4156 /* A non-floating-point argument being passed in a
4157 general register. If a struct or union, and if
4158 the remaining length is smaller than the register
4159 size, we have to adjust the register value on
4162 It does not seem to be necessary to do the
4163 same for integral types.
4165 Also don't do this adjustment on O64 binaries.
4167 cagney/2001-07-23: gdb/179: Also, GCC, when
4168 outputting LE O32 with sizeof (struct) <
4169 mips_abi_regsize(), generates a left shift
4170 as part of storing the argument in a register
4171 (the left shift isn't generated when
4172 sizeof (struct) >= mips_abi_regsize()). Since
4173 it is quite possible that this is GCC
4174 contradicting the LE/O32 ABI, GDB has not been
4175 adjusted to accommodate this. Either someone
4176 needs to demonstrate that the LE/O32 ABI
4177 specifies such a left shift OR this new ABI gets
4178 identified as such and GDB gets tweaked
4181 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4182 && partial_len
< MIPS32_REGSIZE
4183 && (typecode
== TYPE_CODE_STRUCT
4184 || typecode
== TYPE_CODE_UNION
))
4185 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4189 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4191 phex (regval
, MIPS32_REGSIZE
));
4192 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4195 /* Prevent subsequent floating point arguments from
4196 being passed in floating point registers. */
4197 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4203 /* Compute the offset into the stack at which we will
4204 copy the next parameter.
4206 In older ABIs, the caller reserved space for
4207 registers that contained arguments. This was loosely
4208 refered to as their "home". Consequently, space is
4209 always allocated. */
4211 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4215 fprintf_unfiltered (gdb_stdlog
, "\n");
4218 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4220 /* Return adjusted stack pointer. */
4224 static enum return_value_convention
4225 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4226 struct type
*type
, struct regcache
*regcache
,
4227 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4229 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
4230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4231 int mips16
= mips_pc_is_mips16 (func_addr
);
4232 enum mips_fval_reg fval_reg
;
4234 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
4235 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4236 || TYPE_CODE (type
) == TYPE_CODE_UNION
4237 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4238 return RETURN_VALUE_STRUCT_CONVENTION
;
4239 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4240 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4242 /* A single-precision floating-point value. If reading in or copying,
4243 then we get it from/put it to FP0 for standard MIPS code or GPR2
4244 for MIPS16 code. If writing out only, then we put it to both FP0
4245 and GPR2. We do not support reading in with no function known, if
4246 this safety check ever triggers, then we'll have to try harder. */
4247 gdb_assert (function
|| !readbuf
);
4252 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4255 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
4257 case mips_fval_both
:
4258 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
4261 if (fval_reg
!= mips_fval_gpr
)
4262 mips_xfer_register (gdbarch
, regcache
,
4263 (gdbarch_num_regs (gdbarch
)
4264 + mips_regnum (gdbarch
)->fp0
),
4266 gdbarch_byte_order (gdbarch
),
4267 readbuf
, writebuf
, 0);
4268 if (fval_reg
!= mips_fval_fpr
)
4269 mips_xfer_register (gdbarch
, regcache
,
4270 gdbarch_num_regs (gdbarch
) + 2,
4272 gdbarch_byte_order (gdbarch
),
4273 readbuf
, writebuf
, 0);
4274 return RETURN_VALUE_REGISTER_CONVENTION
;
4276 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4277 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4279 /* A double-precision floating-point value. If reading in or copying,
4280 then we get it from/put it to FP1 and FP0 for standard MIPS code or
4281 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
4282 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
4283 no function known, if this safety check ever triggers, then we'll
4284 have to try harder. */
4285 gdb_assert (function
|| !readbuf
);
4290 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4293 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
4295 case mips_fval_both
:
4296 fprintf_unfiltered (gdb_stderr
,
4297 "Return float in $fp1/$fp0 and $2/$3\n");
4300 if (fval_reg
!= mips_fval_gpr
)
4302 /* The most significant part goes in FP1, and the least significant
4304 switch (gdbarch_byte_order (gdbarch
))
4306 case BFD_ENDIAN_LITTLE
:
4307 mips_xfer_register (gdbarch
, regcache
,
4308 (gdbarch_num_regs (gdbarch
)
4309 + mips_regnum (gdbarch
)->fp0
+ 0),
4310 4, gdbarch_byte_order (gdbarch
),
4311 readbuf
, writebuf
, 0);
4312 mips_xfer_register (gdbarch
, regcache
,
4313 (gdbarch_num_regs (gdbarch
)
4314 + mips_regnum (gdbarch
)->fp0
+ 1),
4315 4, gdbarch_byte_order (gdbarch
),
4316 readbuf
, writebuf
, 4);
4318 case BFD_ENDIAN_BIG
:
4319 mips_xfer_register (gdbarch
, regcache
,
4320 (gdbarch_num_regs (gdbarch
)
4321 + mips_regnum (gdbarch
)->fp0
+ 1),
4322 4, gdbarch_byte_order (gdbarch
),
4323 readbuf
, writebuf
, 0);
4324 mips_xfer_register (gdbarch
, regcache
,
4325 (gdbarch_num_regs (gdbarch
)
4326 + mips_regnum (gdbarch
)->fp0
+ 0),
4327 4, gdbarch_byte_order (gdbarch
),
4328 readbuf
, writebuf
, 4);
4331 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4334 if (fval_reg
!= mips_fval_fpr
)
4336 /* The two 32-bit parts are always placed in GPR2 and GPR3
4337 following these registers' memory order. */
4338 mips_xfer_register (gdbarch
, regcache
,
4339 gdbarch_num_regs (gdbarch
) + 2,
4340 4, gdbarch_byte_order (gdbarch
),
4341 readbuf
, writebuf
, 0);
4342 mips_xfer_register (gdbarch
, regcache
,
4343 gdbarch_num_regs (gdbarch
) + 3,
4344 4, gdbarch_byte_order (gdbarch
),
4345 readbuf
, writebuf
, 4);
4347 return RETURN_VALUE_REGISTER_CONVENTION
;
4350 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4351 && TYPE_NFIELDS (type
) <= 2
4352 && TYPE_NFIELDS (type
) >= 1
4353 && ((TYPE_NFIELDS (type
) == 1
4354 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4356 || (TYPE_NFIELDS (type
) == 2
4357 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4359 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4361 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4363 /* A struct that contains one or two floats. Each value is part
4364 in the least significant part of their floating point
4366 gdb_byte reg
[MAX_REGISTER_SIZE
];
4369 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4370 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4372 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4375 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4377 mips_xfer_register (gdbarch
, regcache
,
4378 gdbarch_num_regs (gdbarch
) + regnum
,
4379 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4380 gdbarch_byte_order (gdbarch
),
4381 readbuf
, writebuf
, offset
);
4383 return RETURN_VALUE_REGISTER_CONVENTION
;
4387 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4388 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4390 /* A structure or union. Extract the left justified value,
4391 regardless of the byte order. I.e. DO NOT USE
4395 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4396 offset
< TYPE_LENGTH (type
);
4397 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4399 int xfer
= register_size (gdbarch
, regnum
);
4400 if (offset
+ xfer
> TYPE_LENGTH (type
))
4401 xfer
= TYPE_LENGTH (type
) - offset
;
4403 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4404 offset
, xfer
, regnum
);
4405 mips_xfer_register (gdbarch
, regcache
,
4406 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4407 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4409 return RETURN_VALUE_REGISTER_CONVENTION
;
4414 /* A scalar extract each part but least-significant-byte
4415 justified. o32 thinks registers are 4 byte, regardless of
4419 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4420 offset
< TYPE_LENGTH (type
);
4421 offset
+= MIPS32_REGSIZE
, regnum
++)
4423 int xfer
= MIPS32_REGSIZE
;
4424 if (offset
+ xfer
> TYPE_LENGTH (type
))
4425 xfer
= TYPE_LENGTH (type
) - offset
;
4427 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4428 offset
, xfer
, regnum
);
4429 mips_xfer_register (gdbarch
, regcache
,
4430 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4431 gdbarch_byte_order (gdbarch
),
4432 readbuf
, writebuf
, offset
);
4434 return RETURN_VALUE_REGISTER_CONVENTION
;
4438 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4442 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4443 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4445 struct value
**args
, CORE_ADDR sp
,
4446 int struct_return
, CORE_ADDR struct_addr
)
4452 int stack_offset
= 0;
4453 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4454 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4455 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4457 /* For shared libraries, "t9" needs to point at the function
4459 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4461 /* Set the return address register to point to the entry point of
4462 the program, where a breakpoint lies in wait. */
4463 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4465 /* First ensure that the stack and structure return address (if any)
4466 are properly aligned. The stack has to be at least 64-bit
4467 aligned even on 32-bit machines, because doubles must be 64-bit
4468 aligned. For n32 and n64, stack frames need to be 128-bit
4469 aligned, so we round to this widest known alignment. */
4471 sp
= align_down (sp
, 16);
4472 struct_addr
= align_down (struct_addr
, 16);
4474 /* Now make space on the stack for the args. */
4475 for (argnum
= 0; argnum
< nargs
; argnum
++)
4477 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4478 int arglen
= TYPE_LENGTH (arg_type
);
4480 /* Allocate space on the stack. */
4481 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4483 sp
-= align_up (len
, 16);
4486 fprintf_unfiltered (gdb_stdlog
,
4487 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4488 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4490 /* Initialize the integer and float register pointers. */
4491 argreg
= MIPS_A0_REGNUM
;
4492 float_argreg
= mips_fpa0_regnum (gdbarch
);
4494 /* The struct_return pointer occupies the first parameter-passing reg. */
4498 fprintf_unfiltered (gdb_stdlog
,
4499 "mips_o64_push_dummy_call: "
4500 "struct_return reg=%d %s\n",
4501 argreg
, paddress (gdbarch
, struct_addr
));
4502 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4503 stack_offset
+= MIPS64_REGSIZE
;
4506 /* Now load as many as possible of the first arguments into
4507 registers, and push the rest onto the stack. Loop thru args
4508 from first to last. */
4509 for (argnum
= 0; argnum
< nargs
; argnum
++)
4511 const gdb_byte
*val
;
4512 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4513 struct value
*arg
= args
[argnum
];
4514 struct type
*arg_type
= check_typedef (value_type (arg
));
4515 int len
= TYPE_LENGTH (arg_type
);
4516 enum type_code typecode
= TYPE_CODE (arg_type
);
4519 fprintf_unfiltered (gdb_stdlog
,
4520 "mips_o64_push_dummy_call: %d len=%d type=%d",
4521 argnum
+ 1, len
, (int) typecode
);
4523 val
= value_contents (arg
);
4525 /* Function pointer arguments to mips16 code need to be made into
4527 if (typecode
== TYPE_CODE_PTR
4528 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4530 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4532 if (mips_pc_is_mips16 (addr
))
4534 store_signed_integer (valbuf
, len
, byte_order
,
4535 make_mips16_addr (addr
));
4540 /* Floating point arguments passed in registers have to be
4541 treated specially. On 32-bit architectures, doubles are
4542 passed in register pairs; the even FP register gets the
4543 low word, and the odd FP register gets the high word.
4544 On O64, the first two floating point arguments are also
4545 copied to general registers, because MIPS16 functions
4546 don't use float registers for arguments. This duplication
4547 of arguments in general registers can't hurt non-MIPS16
4548 functions because those registers are normally skipped. */
4550 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4551 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4553 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4555 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4556 float_argreg
, phex (regval
, len
));
4557 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4559 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4560 argreg
, phex (regval
, len
));
4561 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4563 /* Reserve space for the FP register. */
4564 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4568 /* Copy the argument to general registers or the stack in
4569 register-sized pieces. Large arguments are split between
4570 registers and stack. */
4571 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4572 are treated specially: Irix cc passes them in registers
4573 where gcc sometimes puts them on the stack. For maximum
4574 compatibility, we will put them in both places. */
4575 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4576 && len
% MIPS64_REGSIZE
!= 0);
4579 /* Remember if the argument was written to the stack. */
4580 int stack_used_p
= 0;
4581 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4584 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4587 /* Write this portion of the argument to the stack. */
4588 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4589 || odd_sized_struct
)
4591 /* Should shorter than int integer values be
4592 promoted to int before being stored? */
4593 int longword_offset
= 0;
4596 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4598 if ((typecode
== TYPE_CODE_INT
4599 || typecode
== TYPE_CODE_PTR
4600 || typecode
== TYPE_CODE_FLT
)
4602 longword_offset
= MIPS64_REGSIZE
- len
;
4607 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4608 paddress (gdbarch
, stack_offset
));
4609 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4610 paddress (gdbarch
, longword_offset
));
4613 addr
= sp
+ stack_offset
+ longword_offset
;
4618 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4619 paddress (gdbarch
, addr
));
4620 for (i
= 0; i
< partial_len
; i
++)
4622 fprintf_unfiltered (gdb_stdlog
, "%02x",
4626 write_memory (addr
, val
, partial_len
);
4629 /* Note!!! This is NOT an else clause. Odd sized
4630 structs may go thru BOTH paths. */
4631 /* Write this portion of the argument to a general
4632 purpose register. */
4633 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4635 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4637 /* Value may need to be sign extended, because
4638 mips_isa_regsize() != mips_abi_regsize(). */
4640 /* A non-floating-point argument being passed in a
4641 general register. If a struct or union, and if
4642 the remaining length is smaller than the register
4643 size, we have to adjust the register value on
4646 It does not seem to be necessary to do the
4647 same for integral types. */
4649 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4650 && partial_len
< MIPS64_REGSIZE
4651 && (typecode
== TYPE_CODE_STRUCT
4652 || typecode
== TYPE_CODE_UNION
))
4653 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4657 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4659 phex (regval
, MIPS64_REGSIZE
));
4660 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4663 /* Prevent subsequent floating point arguments from
4664 being passed in floating point registers. */
4665 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4671 /* Compute the offset into the stack at which we will
4672 copy the next parameter.
4674 In older ABIs, the caller reserved space for
4675 registers that contained arguments. This was loosely
4676 refered to as their "home". Consequently, space is
4677 always allocated. */
4679 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4683 fprintf_unfiltered (gdb_stdlog
, "\n");
4686 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4688 /* Return adjusted stack pointer. */
4692 static enum return_value_convention
4693 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4694 struct type
*type
, struct regcache
*regcache
,
4695 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4697 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
4698 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4699 int mips16
= mips_pc_is_mips16 (func_addr
);
4700 enum mips_fval_reg fval_reg
;
4702 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
4703 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4704 || TYPE_CODE (type
) == TYPE_CODE_UNION
4705 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4706 return RETURN_VALUE_STRUCT_CONVENTION
;
4707 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4709 /* A floating-point value. If reading in or copying, then we get it
4710 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
4711 If writing out only, then we put it to both FP0 and GPR2. We do
4712 not support reading in with no function known, if this safety
4713 check ever triggers, then we'll have to try harder. */
4714 gdb_assert (function
|| !readbuf
);
4719 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4722 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
4724 case mips_fval_both
:
4725 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
4728 if (fval_reg
!= mips_fval_gpr
)
4729 mips_xfer_register (gdbarch
, regcache
,
4730 (gdbarch_num_regs (gdbarch
)
4731 + mips_regnum (gdbarch
)->fp0
),
4733 gdbarch_byte_order (gdbarch
),
4734 readbuf
, writebuf
, 0);
4735 if (fval_reg
!= mips_fval_fpr
)
4736 mips_xfer_register (gdbarch
, regcache
,
4737 gdbarch_num_regs (gdbarch
) + 2,
4739 gdbarch_byte_order (gdbarch
),
4740 readbuf
, writebuf
, 0);
4741 return RETURN_VALUE_REGISTER_CONVENTION
;
4745 /* A scalar extract each part but least-significant-byte
4749 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4750 offset
< TYPE_LENGTH (type
);
4751 offset
+= MIPS64_REGSIZE
, regnum
++)
4753 int xfer
= MIPS64_REGSIZE
;
4754 if (offset
+ xfer
> TYPE_LENGTH (type
))
4755 xfer
= TYPE_LENGTH (type
) - offset
;
4757 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4758 offset
, xfer
, regnum
);
4759 mips_xfer_register (gdbarch
, regcache
,
4760 gdbarch_num_regs (gdbarch
) + regnum
,
4761 xfer
, gdbarch_byte_order (gdbarch
),
4762 readbuf
, writebuf
, offset
);
4764 return RETURN_VALUE_REGISTER_CONVENTION
;
4768 /* Floating point register management.
4770 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4771 64bit operations, these early MIPS cpus treat fp register pairs
4772 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4773 registers and offer a compatibility mode that emulates the MIPS2 fp
4774 model. When operating in MIPS2 fp compat mode, later cpu's split
4775 double precision floats into two 32-bit chunks and store them in
4776 consecutive fp regs. To display 64-bit floats stored in this
4777 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4778 Throw in user-configurable endianness and you have a real mess.
4780 The way this works is:
4781 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4782 double-precision value will be split across two logical registers.
4783 The lower-numbered logical register will hold the low-order bits,
4784 regardless of the processor's endianness.
4785 - If we are on a 64-bit processor, and we are looking for a
4786 single-precision value, it will be in the low ordered bits
4787 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4788 save slot in memory.
4789 - If we are in 64-bit mode, everything is straightforward.
4791 Note that this code only deals with "live" registers at the top of the
4792 stack. We will attempt to deal with saved registers later, when
4793 the raw/cooked register interface is in place. (We need a general
4794 interface that can deal with dynamic saved register sizes -- fp
4795 regs could be 32 bits wide in one frame and 64 on the frame above
4798 /* Copy a 32-bit single-precision value from the current frame
4799 into rare_buffer. */
4802 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4803 gdb_byte
*rare_buffer
)
4805 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4806 int raw_size
= register_size (gdbarch
, regno
);
4807 gdb_byte
*raw_buffer
= alloca (raw_size
);
4809 if (!frame_register_read (frame
, regno
, raw_buffer
))
4810 error (_("can't read register %d (%s)"),
4811 regno
, gdbarch_register_name (gdbarch
, regno
));
4814 /* We have a 64-bit value for this register. Find the low-order
4818 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4823 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4827 memcpy (rare_buffer
, raw_buffer
, 4);
4831 /* Copy a 64-bit double-precision value from the current frame into
4832 rare_buffer. This may include getting half of it from the next
4836 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4837 gdb_byte
*rare_buffer
)
4839 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4840 int raw_size
= register_size (gdbarch
, regno
);
4842 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4844 /* We have a 64-bit value for this register, and we should use
4846 if (!frame_register_read (frame
, regno
, rare_buffer
))
4847 error (_("can't read register %d (%s)"),
4848 regno
, gdbarch_register_name (gdbarch
, regno
));
4852 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4854 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4855 internal_error (__FILE__
, __LINE__
,
4856 _("mips_read_fp_register_double: bad access to "
4857 "odd-numbered FP register"));
4859 /* mips_read_fp_register_single will find the correct 32 bits from
4861 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4863 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4864 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4868 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4869 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4875 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4877 { /* Do values for FP (float) regs. */
4878 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4879 gdb_byte
*raw_buffer
;
4880 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4883 raw_buffer
= alloca (2 * register_size (gdbarch
,
4884 mips_regnum (gdbarch
)->fp0
));
4886 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4887 fprintf_filtered (file
, "%*s",
4888 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4891 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4893 struct value_print_options opts
;
4895 /* 4-byte registers: Print hex and floating. Also print even
4896 numbered registers as doubles. */
4897 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4898 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4901 get_formatted_print_options (&opts
, 'x');
4902 print_scalar_formatted (raw_buffer
,
4903 builtin_type (gdbarch
)->builtin_uint32
,
4906 fprintf_filtered (file
, " flt: ");
4908 fprintf_filtered (file
, " <invalid float> ");
4910 fprintf_filtered (file
, "%-17.9g", flt1
);
4912 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4914 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4915 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4918 fprintf_filtered (file
, " dbl: ");
4920 fprintf_filtered (file
, "<invalid double>");
4922 fprintf_filtered (file
, "%-24.17g", doub
);
4927 struct value_print_options opts
;
4929 /* Eight byte registers: print each one as hex, float and double. */
4930 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4931 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4934 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4935 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4938 get_formatted_print_options (&opts
, 'x');
4939 print_scalar_formatted (raw_buffer
,
4940 builtin_type (gdbarch
)->builtin_uint64
,
4943 fprintf_filtered (file
, " flt: ");
4945 fprintf_filtered (file
, "<invalid float>");
4947 fprintf_filtered (file
, "%-17.9g", flt1
);
4949 fprintf_filtered (file
, " dbl: ");
4951 fprintf_filtered (file
, "<invalid double>");
4953 fprintf_filtered (file
, "%-24.17g", doub
);
4958 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4961 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4963 struct value_print_options opts
;
4966 if (mips_float_register_p (gdbarch
, regnum
))
4968 mips_print_fp_register (file
, frame
, regnum
);
4972 val
= get_frame_register_value (frame
, regnum
);
4973 if (value_optimized_out (val
))
4975 fprintf_filtered (file
, "%s: [Invalid]",
4976 gdbarch_register_name (gdbarch
, regnum
));
4980 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4982 /* The problem with printing numeric register names (r26, etc.) is that
4983 the user can't use them on input. Probably the best solution is to
4984 fix it so that either the numeric or the funky (a2, etc.) names
4985 are accepted on input. */
4986 if (regnum
< MIPS_NUMREGS
)
4987 fprintf_filtered (file
, "(r%d): ", regnum
);
4989 fprintf_filtered (file
, ": ");
4991 get_formatted_print_options (&opts
, 'x');
4992 val_print_scalar_formatted (value_type (val
),
4993 value_contents_for_printing (val
),
4994 value_embedded_offset (val
),
4999 /* Replacement for generic do_registers_info.
5000 Print regs in pretty columns. */
5003 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5006 fprintf_filtered (file
, " ");
5007 mips_print_fp_register (file
, frame
, regnum
);
5008 fprintf_filtered (file
, "\n");
5013 /* Print a row's worth of GP (int) registers, with name labels above. */
5016 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5019 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5020 /* Do values for GP (int) regs. */
5021 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
5022 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
5027 /* For GP registers, we print a separate row of names above the vals. */
5028 for (col
= 0, regnum
= start_regnum
;
5029 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
5030 + gdbarch_num_pseudo_regs (gdbarch
);
5033 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
5034 continue; /* unused register */
5035 if (mips_float_register_p (gdbarch
, regnum
))
5036 break; /* End the row: reached FP register. */
5037 /* Large registers are handled separately. */
5038 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
5041 break; /* End the row before this register. */
5043 /* Print this register on a row by itself. */
5044 mips_print_register (file
, frame
, regnum
);
5045 fprintf_filtered (file
, "\n");
5049 fprintf_filtered (file
, " ");
5050 fprintf_filtered (file
,
5051 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
5052 gdbarch_register_name (gdbarch
, regnum
));
5059 /* Print the R0 to R31 names. */
5060 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
5061 fprintf_filtered (file
, "\n R%-4d",
5062 start_regnum
% gdbarch_num_regs (gdbarch
));
5064 fprintf_filtered (file
, "\n ");
5066 /* Now print the values in hex, 4 or 8 to the row. */
5067 for (col
= 0, regnum
= start_regnum
;
5068 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
5069 + gdbarch_num_pseudo_regs (gdbarch
);
5072 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
5073 continue; /* unused register */
5074 if (mips_float_register_p (gdbarch
, regnum
))
5075 break; /* End row: reached FP register. */
5076 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
5077 break; /* End row: large register. */
5079 /* OK: get the data in raw format. */
5080 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5081 error (_("can't read register %d (%s)"),
5082 regnum
, gdbarch_register_name (gdbarch
, regnum
));
5083 /* pad small registers */
5085 byte
< (mips_abi_regsize (gdbarch
)
5086 - register_size (gdbarch
, regnum
)); byte
++)
5087 printf_filtered (" ");
5088 /* Now print the register value in hex, endian order. */
5089 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5091 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
5092 byte
< register_size (gdbarch
, regnum
); byte
++)
5093 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
5095 for (byte
= register_size (gdbarch
, regnum
) - 1;
5097 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
5098 fprintf_filtered (file
, " ");
5101 if (col
> 0) /* ie. if we actually printed anything... */
5102 fprintf_filtered (file
, "\n");
5107 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
5110 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5111 struct frame_info
*frame
, int regnum
, int all
)
5113 if (regnum
!= -1) /* Do one specified register. */
5115 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
5116 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
5117 error (_("Not a valid register for the current processor type"));
5119 mips_print_register (file
, frame
, regnum
);
5120 fprintf_filtered (file
, "\n");
5123 /* Do all (or most) registers. */
5125 regnum
= gdbarch_num_regs (gdbarch
);
5126 while (regnum
< gdbarch_num_regs (gdbarch
)
5127 + gdbarch_num_pseudo_regs (gdbarch
))
5129 if (mips_float_register_p (gdbarch
, regnum
))
5131 if (all
) /* True for "INFO ALL-REGISTERS" command. */
5132 regnum
= print_fp_register_row (file
, frame
, regnum
);
5134 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
5137 regnum
= print_gp_register_row (file
, frame
, regnum
);
5142 /* Is this a branch with a delay slot? */
5145 is_delayed (unsigned long insn
)
5148 for (i
= 0; i
< NUMOPCODES
; ++i
)
5149 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5150 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5152 return (i
< NUMOPCODES
5153 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5154 | INSN_COND_BRANCH_DELAY
5155 | INSN_COND_BRANCH_LIKELY
)));
5159 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
5160 struct frame_info
*frame
)
5162 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5163 CORE_ADDR pc
= get_frame_pc (frame
);
5164 gdb_byte buf
[MIPS_INSN32_SIZE
];
5166 /* There is no branch delay slot on MIPS16. */
5167 if (mips_pc_is_mips16 (pc
))
5170 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
5173 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
5174 /* If error reading memory, guess that it is not a delayed
5177 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
5180 /* To skip prologues, I use this predicate. Returns either PC itself
5181 if the code at PC does not look like a function prologue; otherwise
5182 returns an address that (if we're lucky) follows the prologue. If
5183 LENIENT, then we must skip everything which is involved in setting
5184 up the frame (it's OK to skip more, just so long as we don't skip
5185 anything which might clobber the registers which are being saved.
5186 We must skip more in the case where part of the prologue is in the
5187 delay slot of a non-prologue instruction). */
5190 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5193 CORE_ADDR func_addr
;
5195 /* See if we can determine the end of the prologue via the symbol table.
5196 If so, then return either PC, or the PC after the prologue, whichever
5198 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
5200 CORE_ADDR post_prologue_pc
5201 = skip_prologue_using_sal (gdbarch
, func_addr
);
5202 if (post_prologue_pc
!= 0)
5203 return max (pc
, post_prologue_pc
);
5206 /* Can't determine prologue from the symbol table, need to examine
5209 /* Find an upper limit on the function prologue using the debug
5210 information. If the debug information could not be used to provide
5211 that bound, then use an arbitrary large number as the upper bound. */
5212 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
5214 limit_pc
= pc
+ 100; /* Magic. */
5216 if (mips_pc_is_mips16 (pc
))
5217 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5219 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5222 /* Check whether the PC is in a function epilogue (32-bit version).
5223 This is a helper function for mips_in_function_epilogue_p. */
5225 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5227 CORE_ADDR func_addr
= 0, func_end
= 0;
5229 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5231 /* The MIPS epilogue is max. 12 bytes long. */
5232 CORE_ADDR addr
= func_end
- 12;
5234 if (addr
< func_addr
+ 4)
5235 addr
= func_addr
+ 4;
5239 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
5241 unsigned long high_word
;
5244 inst
= mips_fetch_instruction (gdbarch
, pc
);
5245 high_word
= (inst
>> 16) & 0xffff;
5247 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
5248 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
5249 && inst
!= 0x03e00008 /* jr $ra */
5250 && inst
!= 0x00000000) /* nop */
5260 /* Check whether the PC is in a function epilogue (16-bit version).
5261 This is a helper function for mips_in_function_epilogue_p. */
5263 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5265 CORE_ADDR func_addr
= 0, func_end
= 0;
5267 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5269 /* The MIPS epilogue is max. 12 bytes long. */
5270 CORE_ADDR addr
= func_end
- 12;
5272 if (addr
< func_addr
+ 4)
5273 addr
= func_addr
+ 4;
5277 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5279 unsigned short inst
;
5281 inst
= mips_fetch_instruction (gdbarch
, pc
);
5283 if ((inst
& 0xf800) == 0xf000) /* extend */
5286 if (inst
!= 0x6300 /* addiu $sp,offset */
5287 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5288 && inst
!= 0xe820 /* jr $ra */
5289 && inst
!= 0xe8a0 /* jrc $ra */
5290 && inst
!= 0x6500) /* nop */
5300 /* The epilogue is defined here as the area at the end of a function,
5301 after an instruction which destroys the function's stack frame. */
5303 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5305 if (mips_pc_is_mips16 (pc
))
5306 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5308 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5311 /* Root of all "set mips "/"show mips " commands. This will eventually be
5312 used for all MIPS-specific commands. */
5315 show_mips_command (char *args
, int from_tty
)
5317 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5321 set_mips_command (char *args
, int from_tty
)
5324 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5325 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5328 /* Commands to show/set the MIPS FPU type. */
5331 show_mipsfpu_command (char *args
, int from_tty
)
5335 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5338 ("The MIPS floating-point coprocessor is unknown "
5339 "because the current architecture is not MIPS.\n");
5343 switch (MIPS_FPU_TYPE (target_gdbarch
))
5345 case MIPS_FPU_SINGLE
:
5346 fpu
= "single-precision";
5348 case MIPS_FPU_DOUBLE
:
5349 fpu
= "double-precision";
5352 fpu
= "absent (none)";
5355 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5357 if (mips_fpu_type_auto
)
5358 printf_unfiltered ("The MIPS floating-point coprocessor "
5359 "is set automatically (currently %s)\n",
5363 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5368 set_mipsfpu_command (char *args
, int from_tty
)
5370 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5371 "\"single\",\"none\" or \"auto\".\n");
5372 show_mipsfpu_command (args
, from_tty
);
5376 set_mipsfpu_single_command (char *args
, int from_tty
)
5378 struct gdbarch_info info
;
5379 gdbarch_info_init (&info
);
5380 mips_fpu_type
= MIPS_FPU_SINGLE
;
5381 mips_fpu_type_auto
= 0;
5382 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5383 instead of relying on globals. Doing that would let generic code
5384 handle the search for this specific architecture. */
5385 if (!gdbarch_update_p (info
))
5386 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5390 set_mipsfpu_double_command (char *args
, int from_tty
)
5392 struct gdbarch_info info
;
5393 gdbarch_info_init (&info
);
5394 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5395 mips_fpu_type_auto
= 0;
5396 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5397 instead of relying on globals. Doing that would let generic code
5398 handle the search for this specific architecture. */
5399 if (!gdbarch_update_p (info
))
5400 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5404 set_mipsfpu_none_command (char *args
, int from_tty
)
5406 struct gdbarch_info info
;
5407 gdbarch_info_init (&info
);
5408 mips_fpu_type
= MIPS_FPU_NONE
;
5409 mips_fpu_type_auto
= 0;
5410 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5411 instead of relying on globals. Doing that would let generic code
5412 handle the search for this specific architecture. */
5413 if (!gdbarch_update_p (info
))
5414 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5418 set_mipsfpu_auto_command (char *args
, int from_tty
)
5420 mips_fpu_type_auto
= 1;
5423 /* Attempt to identify the particular processor model by reading the
5424 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5425 the relevant processor still exists (it dates back to '94) and
5426 secondly this is not the way to do this. The processor type should
5427 be set by forcing an architecture change. */
5430 deprecated_mips_set_processor_regs_hack (void)
5432 struct regcache
*regcache
= get_current_regcache ();
5433 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5434 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5437 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5438 if ((prid
& ~0xf) == 0x700)
5439 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5442 /* Just like reinit_frame_cache, but with the right arguments to be
5443 callable as an sfunc. */
5446 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5447 struct cmd_list_element
*c
)
5449 reinit_frame_cache ();
5453 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5455 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5456 disassembler needs to be able to locally determine the ISA, and
5457 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5459 if (mips_pc_is_mips16 (memaddr
))
5460 info
->mach
= bfd_mach_mips16
;
5462 /* Round down the instruction address to the appropriate boundary. */
5463 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5465 /* Set the disassembler options. */
5466 if (!info
->disassembler_options
)
5467 /* This string is not recognized explicitly by the disassembler,
5468 but it tells the disassembler to not try to guess the ABI from
5469 the bfd elf headers, such that, if the user overrides the ABI
5470 of a program linked as NewABI, the disassembly will follow the
5471 register naming conventions specified by the user. */
5472 info
->disassembler_options
= "gpr-names=32";
5474 /* Call the appropriate disassembler based on the target endian-ness. */
5475 if (info
->endian
== BFD_ENDIAN_BIG
)
5476 return print_insn_big_mips (memaddr
, info
);
5478 return print_insn_little_mips (memaddr
, info
);
5482 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5484 /* Set up the disassembler info, so that we get the right
5485 register names from libopcodes. */
5486 info
->disassembler_options
= "gpr-names=n32";
5487 info
->flavour
= bfd_target_elf_flavour
;
5489 return gdb_print_insn_mips (memaddr
, info
);
5493 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5495 /* Set up the disassembler info, so that we get the right
5496 register names from libopcodes. */
5497 info
->disassembler_options
= "gpr-names=64";
5498 info
->flavour
= bfd_target_elf_flavour
;
5500 return gdb_print_insn_mips (memaddr
, info
);
5503 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5504 program counter value to determine whether a 16- or 32-bit breakpoint
5505 should be used. It returns a pointer to a string of bytes that encode a
5506 breakpoint instruction, stores the length of the string to *lenptr, and
5507 adjusts pc (if necessary) to point to the actual memory location where
5508 the breakpoint should be inserted. */
5510 static const gdb_byte
*
5511 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5512 CORE_ADDR
*pcptr
, int *lenptr
)
5514 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5516 if (mips_pc_is_mips16 (*pcptr
))
5518 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5519 *pcptr
= unmake_mips16_addr (*pcptr
);
5520 *lenptr
= sizeof (mips16_big_breakpoint
);
5521 return mips16_big_breakpoint
;
5525 /* The IDT board uses an unusual breakpoint value, and
5526 sometimes gets confused when it sees the usual MIPS
5527 breakpoint instruction. */
5528 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5529 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5530 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5531 /* Likewise, IRIX appears to expect a different breakpoint,
5532 although this is not apparent until you try to use pthreads. */
5533 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5535 *lenptr
= sizeof (big_breakpoint
);
5537 if (strcmp (target_shortname
, "mips") == 0)
5538 return idt_big_breakpoint
;
5539 else if (strcmp (target_shortname
, "ddb") == 0
5540 || strcmp (target_shortname
, "pmon") == 0
5541 || strcmp (target_shortname
, "lsi") == 0)
5542 return pmon_big_breakpoint
;
5543 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5544 return irix_big_breakpoint
;
5546 return big_breakpoint
;
5551 if (mips_pc_is_mips16 (*pcptr
))
5553 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5554 *pcptr
= unmake_mips16_addr (*pcptr
);
5555 *lenptr
= sizeof (mips16_little_breakpoint
);
5556 return mips16_little_breakpoint
;
5560 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5561 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5562 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5564 *lenptr
= sizeof (little_breakpoint
);
5566 if (strcmp (target_shortname
, "mips") == 0)
5567 return idt_little_breakpoint
;
5568 else if (strcmp (target_shortname
, "ddb") == 0
5569 || strcmp (target_shortname
, "pmon") == 0
5570 || strcmp (target_shortname
, "lsi") == 0)
5571 return pmon_little_breakpoint
;
5573 return little_breakpoint
;
5578 /* Return non-zero if the ADDR instruction has a branch delay slot
5579 (i.e. it is a jump or branch instruction). This function is based
5580 on mips32_next_pc. */
5583 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
5585 gdb_byte buf
[MIPS_INSN32_SIZE
];
5592 status
= target_read_memory (addr
, buf
, MIPS_INSN32_SIZE
);
5596 inst
= mips_fetch_instruction (gdbarch
, addr
);
5597 op
= itype_op (inst
);
5598 if ((inst
& 0xe0000000) != 0)
5600 rs
= itype_rs (inst
);
5601 rt
= itype_rt (inst
);
5602 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
5603 || op
== 29 /* JALX: bits 011101 */
5606 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
5607 || (rs
== 9 && (rt
& 0x2) == 0)
5608 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
5609 || (rs
== 10 && (rt
& 0x2) == 0))));
5610 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
5613 switch (op
& 0x07) /* extract bits 28,27,26 */
5615 case 0: /* SPECIAL */
5616 op
= rtype_funct (inst
);
5617 return (op
== 8 /* JR */
5618 || op
== 9); /* JALR */
5619 break; /* end SPECIAL */
5620 case 1: /* REGIMM */
5621 rs
= itype_rs (inst
);
5622 rt
= itype_rt (inst
); /* branch condition */
5623 return ((rt
& 0xc) == 0
5624 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
5625 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
5626 || ((rt
& 0x1e) == 0x1c && rs
== 0));
5627 /* BPOSGE32, BPOSGE64: bits 1110x */
5628 break; /* end REGIMM */
5629 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
5635 /* Return non-zero if the ADDR instruction, which must be a 32-bit
5636 instruction if MUSTBE32 is set or can be any instruction otherwise,
5637 has a branch delay slot (i.e. it is a non-compact jump instruction). */
5640 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
5643 gdb_byte buf
[MIPS_INSN16_SIZE
];
5644 unsigned short inst
;
5647 status
= target_read_memory (addr
, buf
, MIPS_INSN16_SIZE
);
5651 inst
= mips_fetch_instruction (gdbarch
, addr
);
5653 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
5654 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
5657 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
5658 This assumes KSSEG exists. */
5661 mips_segment_boundary (CORE_ADDR bpaddr
)
5663 CORE_ADDR mask
= CORE_ADDR_MAX
;
5666 if (sizeof (CORE_ADDR
) == 8)
5667 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
5668 a compiler warning produced where CORE_ADDR is a 32-bit type even
5669 though in that case this is dead code). */
5670 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
5673 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
5674 segsize
= 29; /* 32-bit compatibility segment */
5676 segsize
= 62; /* xkseg */
5678 case 2: /* xkphys */
5681 default: /* xksseg (1), xkuseg/kuseg (0) */
5685 else if (bpaddr
& 0x80000000) /* kernel segment */
5688 segsize
= 31; /* user segment */
5690 return bpaddr
& mask
;
5693 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
5694 it backwards if necessary. Return the address of the new location. */
5697 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5699 CORE_ADDR prev_addr
, next_addr
;
5701 CORE_ADDR func_addr
;
5703 /* If a breakpoint is set on the instruction in a branch delay slot,
5704 GDB gets confused. When the breakpoint is hit, the PC isn't on
5705 the instruction in the branch delay slot, the PC will point to
5706 the branch instruction. Since the PC doesn't match any known
5707 breakpoints, GDB reports a trap exception.
5709 There are two possible fixes for this problem.
5711 1) When the breakpoint gets hit, see if the BD bit is set in the
5712 Cause register (which indicates the last exception occurred in a
5713 branch delay slot). If the BD bit is set, fix the PC to point to
5714 the instruction in the branch delay slot.
5716 2) When the user sets the breakpoint, don't allow him to set the
5717 breakpoint on the instruction in the branch delay slot. Instead
5718 move the breakpoint to the branch instruction (which will have
5721 The problem with the first solution is that if the user then
5722 single-steps the processor, the branch instruction will get
5723 skipped (since GDB thinks the PC is on the instruction in the
5726 So, we'll use the second solution. To do this we need to know if
5727 the instruction we're trying to set the breakpoint on is in the
5728 branch delay slot. */
5730 boundary
= mips_segment_boundary (bpaddr
);
5732 /* Make sure we don't scan back before the beginning of the current
5733 function, since we may fetch constant data or insns that look like
5734 a jump. Of course we might do that anyway if the compiler has
5735 moved constants inline. :-( */
5736 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
5737 && func_addr
> boundary
&& func_addr
<= bpaddr
)
5738 boundary
= func_addr
;
5740 if (!mips_pc_is_mips16 (bpaddr
))
5742 if (bpaddr
== boundary
)
5745 /* If the previous instruction has a branch delay slot, we have
5746 to move the breakpoint to the branch instruction. */
5747 prev_addr
= bpaddr
- 4;
5748 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
5753 struct minimal_symbol
*sym
;
5754 CORE_ADDR addr
, jmpaddr
;
5757 boundary
= unmake_mips16_addr (boundary
);
5759 /* The only MIPS16 instructions with delay slots are JAL, JALX,
5760 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
5761 so try for that first, then try the 2 byte JALR/JR.
5762 FIXME: We have to assume that bpaddr is not the second half
5763 of an extended instruction. */
5767 for (i
= 1; i
< 4; i
++)
5769 if (unmake_mips16_addr (addr
) == boundary
)
5772 if (i
== 1 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 0))
5773 /* Looks like a JR/JALR at [target-1], but it could be
5774 the second word of a previous JAL/JALX, so record it
5775 and check back one more. */
5778 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 1))
5781 /* Looks like a JAL/JALX at [target-2], but it could also
5782 be the second word of a previous JAL/JALX, record it,
5783 and check back one more. */
5786 /* Looks like a JAL/JALX at [target-3], so any previously
5787 recorded JAL/JALX or JR/JALR must be wrong, because:
5790 -2: JAL-ext (can't be JAL/JALX)
5791 -1: bdslot (can't be JR/JALR)
5794 Of course it could be another JAL-ext which looks
5795 like a JAL, but in that case we'd have broken out
5796 of this loop at [target-2]:
5800 -2: bdslot (can't be jmp)
5807 /* Not a jump instruction: if we're at [target-1] this
5808 could be the second word of a JAL/JALX, so continue;
5809 otherwise we're done. */
5822 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
5823 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
5826 mips_is_stub_suffix (const char *suffix
, int zero
)
5831 return zero
&& suffix
[1] == '\0';
5833 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
5838 return suffix
[1] == '\0';
5844 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
5845 call stubs, one of sf, df, sc, or dc. */
5848 mips_is_stub_mode (const char *mode
)
5850 return ((mode
[0] == 's' || mode
[0] == 'd')
5851 && (mode
[1] == 'f' || mode
[1] == 'c'));
5854 /* Code at PC is a compiler-generated stub. Such a stub for a function
5855 bar might have a name like __fn_stub_bar, and might look like this:
5862 followed by (or interspersed with):
5869 addiu $25, $25, %lo(bar)
5872 ($1 may be used in old code; for robustness we accept any register)
5875 lui $28, %hi(_gp_disp)
5876 addiu $28, $28, %lo(_gp_disp)
5879 addiu $25, $25, %lo(bar)
5882 In the case of a __call_stub_bar stub, the sequence to set up
5883 arguments might look like this:
5890 followed by (or interspersed with) one of the jump sequences above.
5892 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
5893 of J or JR, respectively, followed by:
5899 We are at the beginning of the stub here, and scan down and extract
5900 the target address from the jump immediate instruction or, if a jump
5901 register instruction is used, from the register referred. Return
5902 the value of PC calculated or 0 if inconclusive.
5904 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
5907 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
5909 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5910 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5911 int addrreg
= MIPS_ZERO_REGNUM
;
5912 CORE_ADDR start_pc
= pc
;
5913 CORE_ADDR target_pc
= 0;
5920 status
== 0 && target_pc
== 0 && i
< 20;
5921 i
++, pc
+= MIPS_INSN32_SIZE
)
5923 ULONGEST inst
= mips_fetch_instruction (gdbarch
, pc
);
5929 switch (itype_op (inst
))
5931 case 0: /* SPECIAL */
5932 switch (rtype_funct (inst
))
5936 rs
= rtype_rs (inst
);
5937 if (rs
== MIPS_GP_REGNUM
)
5938 target_pc
= gp
; /* Hmm... */
5939 else if (rs
== addrreg
)
5943 case 0x21: /* ADDU */
5944 rt
= rtype_rt (inst
);
5945 rs
= rtype_rs (inst
);
5946 rd
= rtype_rd (inst
);
5947 if (rd
== MIPS_GP_REGNUM
5948 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
5949 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
5957 target_pc
= jtype_target (inst
) << 2;
5958 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
5962 rt
= itype_rt (inst
);
5963 rs
= itype_rs (inst
);
5966 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
5967 if (rt
== MIPS_GP_REGNUM
)
5969 else if (rt
== addrreg
)
5975 rt
= itype_rt (inst
);
5976 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
5977 if (rt
== MIPS_GP_REGNUM
)
5979 else if (rt
!= MIPS_ZERO_REGNUM
)
5987 rt
= itype_rt (inst
);
5988 rs
= itype_rs (inst
);
5989 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
5990 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
5994 memset (buf
, 0, sizeof (buf
));
5995 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
5997 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
6006 /* If PC is in a MIPS16 call or return stub, return the address of the
6007 target PC, which is either the callee or the caller. There are several
6008 cases which must be handled:
6010 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
6011 and the target PC is in $31 ($ra).
6012 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
6013 and the target PC is in $2.
6014 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
6015 i.e. before the JALR instruction, this is effectively a call stub
6016 and the target PC is in $2. Otherwise this is effectively
6017 a return stub and the target PC is in $18.
6018 * If the PC is at the start of __call_stub_fp_*, i.e. before the
6019 JAL or JALR instruction, this is effectively a call stub and the
6020 target PC is buried in the instruction stream. Otherwise this
6021 is effectively a return stub and the target PC is in $18.
6022 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
6023 stub and the target PC is buried in the instruction stream.
6025 See the source code for the stubs in gcc/config/mips/mips16.S, or the
6026 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
6030 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
6032 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6033 CORE_ADDR start_addr
;
6037 /* Find the starting address and name of the function containing the PC. */
6038 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
6041 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
6042 and the target PC is in $31 ($ra). */
6043 prefixlen
= strlen (mips_str_mips16_ret_stub
);
6044 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
6045 && mips_is_stub_mode (name
+ prefixlen
)
6046 && name
[prefixlen
+ 2] == '\0')
6047 return get_frame_register_signed
6048 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
6050 /* If the PC is in __mips16_call_stub_*, this is one of the call
6051 call/return stubs. */
6052 prefixlen
= strlen (mips_str_mips16_call_stub
);
6053 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
6055 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
6056 and the target PC is in $2. */
6057 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
6058 return get_frame_register_signed
6059 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
6061 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
6062 i.e. before the JALR instruction, this is effectively a call stub
6063 and the target PC is in $2. Otherwise this is effectively
6064 a return stub and the target PC is in $18. */
6065 else if (mips_is_stub_mode (name
+ prefixlen
)
6066 && name
[prefixlen
+ 2] == '_'
6067 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
6069 if (pc
== start_addr
)
6070 /* This is the 'call' part of a call stub. The return
6071 address is in $2. */
6072 return get_frame_register_signed
6073 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
6075 /* This is the 'return' part of a call stub. The return
6076 address is in $18. */
6077 return get_frame_register_signed
6078 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
6081 return 0; /* Not a stub. */
6084 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
6085 compiler-generated call or call/return stubs. */
6086 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
6087 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
6089 if (pc
== start_addr
)
6090 /* This is the 'call' part of a call stub. Call this helper
6091 to scan through this code for interesting instructions
6092 and determine the final PC. */
6093 return mips_get_mips16_fn_stub_pc (frame
, pc
);
6095 /* This is the 'return' part of a call stub. The return address
6097 return get_frame_register_signed
6098 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
6101 return 0; /* Not a stub. */
6104 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
6105 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
6108 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
6110 CORE_ADDR start_addr
;
6113 /* Find the starting address of the function containing the PC. */
6114 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
6117 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
6118 the start, i.e. after the JALR instruction, this is effectively
6120 prefixlen
= strlen (mips_str_mips16_call_stub
);
6121 if (pc
!= start_addr
6122 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
6123 && mips_is_stub_mode (name
+ prefixlen
)
6124 && name
[prefixlen
+ 2] == '_'
6125 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
6128 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
6129 the JAL or JALR instruction, this is effectively a return stub. */
6130 prefixlen
= strlen (mips_str_call_fp_stub
);
6131 if (pc
!= start_addr
6132 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
6135 /* Consume the .pic. prefix of any PIC stub, this function must return
6136 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
6137 or the call stub path will trigger in handle_inferior_event causing
6139 prefixlen
= strlen (mips_str_pic
);
6140 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
6143 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
6144 prefixlen
= strlen (mips_str_mips16_ret_stub
);
6145 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
6146 && mips_is_stub_mode (name
+ prefixlen
)
6147 && name
[prefixlen
+ 2] == '\0')
6150 return 0; /* Not a stub. */
6153 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
6154 PC of the stub target. The stub just loads $t9 and jumps to it,
6155 so that $t9 has the correct value at function entry. */
6158 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
6160 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6161 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6162 struct minimal_symbol
*msym
;
6164 gdb_byte stub_code
[16];
6165 int32_t stub_words
[4];
6167 /* The stub for foo is named ".pic.foo", and is either two
6168 instructions inserted before foo or a three instruction sequence
6169 which jumps to foo. */
6170 msym
= lookup_minimal_symbol_by_pc (pc
);
6172 || SYMBOL_VALUE_ADDRESS (msym
) != pc
6173 || SYMBOL_LINKAGE_NAME (msym
) == NULL
6174 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
6177 /* A two-instruction header. */
6178 if (MSYMBOL_SIZE (msym
) == 8)
6181 /* A three-instruction (plus delay slot) trampoline. */
6182 if (MSYMBOL_SIZE (msym
) == 16)
6184 if (target_read_memory (pc
, stub_code
, 16) != 0)
6186 for (i
= 0; i
< 4; i
++)
6187 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
6190 /* A stub contains these instructions:
6193 addiu t9, t9, %lo(target)
6196 This works even for N64, since stubs are only generated with
6198 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
6199 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
6200 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
6201 && stub_words
[3] == 0x00000000)
6202 return ((((stub_words
[0] & 0x0000ffff) << 16)
6203 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
6206 /* Not a recognized stub. */
6211 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
6213 CORE_ADDR requested_pc
= pc
;
6214 CORE_ADDR target_pc
;
6221 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
6225 if (is_mips16_addr (pc
))
6226 pc
= unmake_mips16_addr (pc
);
6229 new_pc
= find_solib_trampoline_target (frame
, pc
);
6233 if (is_mips16_addr (pc
))
6234 pc
= unmake_mips16_addr (pc
);
6237 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
6241 if (is_mips16_addr (pc
))
6242 pc
= unmake_mips16_addr (pc
);
6245 while (pc
!= target_pc
);
6247 return pc
!= requested_pc
? pc
: 0;
6250 /* Convert a dbx stab register number (from `r' declaration) to a GDB
6251 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
6254 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
6257 if (num
>= 0 && num
< 32)
6259 else if (num
>= 38 && num
< 70)
6260 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
6262 regnum
= mips_regnum (gdbarch
)->hi
;
6264 regnum
= mips_regnum (gdbarch
)->lo
;
6265 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
6266 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
6268 /* This will hopefully (eventually) provoke a warning. Should
6269 we be calling complaint() here? */
6270 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
6271 return gdbarch_num_regs (gdbarch
) + regnum
;
6275 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
6276 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
6279 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
6282 if (num
>= 0 && num
< 32)
6284 else if (num
>= 32 && num
< 64)
6285 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
6287 regnum
= mips_regnum (gdbarch
)->hi
;
6289 regnum
= mips_regnum (gdbarch
)->lo
;
6290 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
6291 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
6293 /* This will hopefully (eventually) provoke a warning. Should we
6294 be calling complaint() here? */
6295 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
6296 return gdbarch_num_regs (gdbarch
) + regnum
;
6300 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
6302 /* Only makes sense to supply raw registers. */
6303 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
6304 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
6305 decide if it is valid. Should instead define a standard sim/gdb
6306 register numbering scheme. */
6307 if (gdbarch_register_name (gdbarch
,
6308 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
6309 && gdbarch_register_name (gdbarch
,
6310 gdbarch_num_regs (gdbarch
)
6311 + regnum
)[0] != '\0')
6314 return LEGACY_SIM_REGNO_IGNORE
;
6318 /* Convert an integer into an address. Extracting the value signed
6319 guarantees a correctly sign extended address. */
6322 mips_integer_to_address (struct gdbarch
*gdbarch
,
6323 struct type
*type
, const gdb_byte
*buf
)
6325 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6326 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
6329 /* Dummy virtual frame pointer method. This is no more or less accurate
6330 than most other architectures; we just need to be explicit about it,
6331 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
6332 an assertion failure. */
6335 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
6336 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
6338 *reg
= MIPS_SP_REGNUM
;
6343 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
6345 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
6346 const char *name
= bfd_get_section_name (abfd
, sect
);
6348 if (*abip
!= MIPS_ABI_UNKNOWN
)
6351 if (strncmp (name
, ".mdebug.", 8) != 0)
6354 if (strcmp (name
, ".mdebug.abi32") == 0)
6355 *abip
= MIPS_ABI_O32
;
6356 else if (strcmp (name
, ".mdebug.abiN32") == 0)
6357 *abip
= MIPS_ABI_N32
;
6358 else if (strcmp (name
, ".mdebug.abi64") == 0)
6359 *abip
= MIPS_ABI_N64
;
6360 else if (strcmp (name
, ".mdebug.abiO64") == 0)
6361 *abip
= MIPS_ABI_O64
;
6362 else if (strcmp (name
, ".mdebug.eabi32") == 0)
6363 *abip
= MIPS_ABI_EABI32
;
6364 else if (strcmp (name
, ".mdebug.eabi64") == 0)
6365 *abip
= MIPS_ABI_EABI64
;
6367 warning (_("unsupported ABI %s."), name
+ 8);
6371 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
6373 int *lbp
= (int *) obj
;
6374 const char *name
= bfd_get_section_name (abfd
, sect
);
6376 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
6378 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
6380 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
6381 warning (_("unrecognized .gcc_compiled_longXX"));
6384 static enum mips_abi
6385 global_mips_abi (void)
6389 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
6390 if (mips_abi_strings
[i
] == mips_abi_string
)
6391 return (enum mips_abi
) i
;
6393 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
6397 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
6399 /* If the size matches the set of 32-bit or 64-bit integer registers,
6400 assume that's what we've got. */
6401 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
6402 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
6404 /* If the size matches the full set of registers GDB traditionally
6405 knows about, including floating point, for either 32-bit or
6406 64-bit, assume that's what we've got. */
6407 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
6408 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
6410 /* Otherwise we don't have a useful guess. */
6413 static struct value
*
6414 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
6416 const int *reg_p
= baton
;
6417 return value_of_register (*reg_p
, frame
);
6420 static struct gdbarch
*
6421 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6423 struct gdbarch
*gdbarch
;
6424 struct gdbarch_tdep
*tdep
;
6426 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
6428 enum mips_fpu_type fpu_type
;
6429 struct tdesc_arch_data
*tdesc_data
= NULL
;
6430 int elf_fpu_type
= 0;
6431 const char **reg_names
;
6432 struct mips_regnum mips_regnum
, *regnum
;
6436 /* Fill in the OS dependent register numbers and names. */
6437 if (info
.osabi
== GDB_OSABI_IRIX
)
6439 mips_regnum
.fp0
= 32;
6440 mips_regnum
.pc
= 64;
6441 mips_regnum
.cause
= 65;
6442 mips_regnum
.badvaddr
= 66;
6443 mips_regnum
.hi
= 67;
6444 mips_regnum
.lo
= 68;
6445 mips_regnum
.fp_control_status
= 69;
6446 mips_regnum
.fp_implementation_revision
= 70;
6447 mips_regnum
.dspacc
= dspacc
= -1;
6448 mips_regnum
.dspctl
= dspctl
= -1;
6450 reg_names
= mips_irix_reg_names
;
6452 else if (info
.osabi
== GDB_OSABI_LINUX
)
6454 mips_regnum
.fp0
= 38;
6455 mips_regnum
.pc
= 37;
6456 mips_regnum
.cause
= 36;
6457 mips_regnum
.badvaddr
= 35;
6458 mips_regnum
.hi
= 34;
6459 mips_regnum
.lo
= 33;
6460 mips_regnum
.fp_control_status
= 70;
6461 mips_regnum
.fp_implementation_revision
= 71;
6462 mips_regnum
.dspacc
= -1;
6463 mips_regnum
.dspctl
= -1;
6467 reg_names
= mips_linux_reg_names
;
6471 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
6472 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
6473 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6474 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
6475 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
6476 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
6477 mips_regnum
.fp_control_status
= 70;
6478 mips_regnum
.fp_implementation_revision
= 71;
6479 mips_regnum
.dspacc
= dspacc
= -1;
6480 mips_regnum
.dspctl
= dspctl
= -1;
6481 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6482 if (info
.bfd_arch_info
!= NULL
6483 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6484 reg_names
= mips_tx39_reg_names
;
6486 reg_names
= mips_generic_reg_names
;
6489 /* Check any target description for validity. */
6490 if (tdesc_has_registers (info
.target_desc
))
6492 static const char *const mips_gprs
[] = {
6493 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6494 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6495 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6496 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6498 static const char *const mips_fprs
[] = {
6499 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6500 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6501 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6502 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
6505 const struct tdesc_feature
*feature
;
6508 feature
= tdesc_find_feature (info
.target_desc
,
6509 "org.gnu.gdb.mips.cpu");
6510 if (feature
== NULL
)
6513 tdesc_data
= tdesc_data_alloc ();
6516 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
6517 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6521 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6522 mips_regnum
.lo
, "lo");
6523 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6524 mips_regnum
.hi
, "hi");
6525 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6526 mips_regnum
.pc
, "pc");
6530 tdesc_data_cleanup (tdesc_data
);
6534 feature
= tdesc_find_feature (info
.target_desc
,
6535 "org.gnu.gdb.mips.cp0");
6536 if (feature
== NULL
)
6538 tdesc_data_cleanup (tdesc_data
);
6543 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6544 mips_regnum
.badvaddr
, "badvaddr");
6545 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6546 MIPS_PS_REGNUM
, "status");
6547 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6548 mips_regnum
.cause
, "cause");
6552 tdesc_data_cleanup (tdesc_data
);
6556 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
6557 backend is not prepared for that, though. */
6558 feature
= tdesc_find_feature (info
.target_desc
,
6559 "org.gnu.gdb.mips.fpu");
6560 if (feature
== NULL
)
6562 tdesc_data_cleanup (tdesc_data
);
6567 for (i
= 0; i
< 32; i
++)
6568 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6569 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
6571 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6572 mips_regnum
.fp_control_status
,
6575 &= tdesc_numbered_register (feature
, tdesc_data
,
6576 mips_regnum
.fp_implementation_revision
,
6581 tdesc_data_cleanup (tdesc_data
);
6587 feature
= tdesc_find_feature (info
.target_desc
,
6588 "org.gnu.gdb.mips.dsp");
6589 /* The DSP registers are optional; it's OK if they are absent. */
6590 if (feature
!= NULL
)
6594 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6595 dspacc
+ i
++, "hi1");
6596 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6597 dspacc
+ i
++, "lo1");
6598 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6599 dspacc
+ i
++, "hi2");
6600 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6601 dspacc
+ i
++, "lo2");
6602 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6603 dspacc
+ i
++, "hi3");
6604 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6605 dspacc
+ i
++, "lo3");
6607 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6612 tdesc_data_cleanup (tdesc_data
);
6616 mips_regnum
.dspacc
= dspacc
;
6617 mips_regnum
.dspctl
= dspctl
;
6621 /* It would be nice to detect an attempt to use a 64-bit ABI
6622 when only 32-bit registers are provided. */
6626 /* First of all, extract the elf_flags, if available. */
6627 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6628 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6629 else if (arches
!= NULL
)
6630 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6634 fprintf_unfiltered (gdb_stdlog
,
6635 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6637 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6638 switch ((elf_flags
& EF_MIPS_ABI
))
6640 case E_MIPS_ABI_O32
:
6641 found_abi
= MIPS_ABI_O32
;
6643 case E_MIPS_ABI_O64
:
6644 found_abi
= MIPS_ABI_O64
;
6646 case E_MIPS_ABI_EABI32
:
6647 found_abi
= MIPS_ABI_EABI32
;
6649 case E_MIPS_ABI_EABI64
:
6650 found_abi
= MIPS_ABI_EABI64
;
6653 if ((elf_flags
& EF_MIPS_ABI2
))
6654 found_abi
= MIPS_ABI_N32
;
6656 found_abi
= MIPS_ABI_UNKNOWN
;
6660 /* GCC creates a pseudo-section whose name describes the ABI. */
6661 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6662 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6664 /* If we have no useful BFD information, use the ABI from the last
6665 MIPS architecture (if there is one). */
6666 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6667 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6669 /* Try the architecture for any hint of the correct ABI. */
6670 if (found_abi
== MIPS_ABI_UNKNOWN
6671 && info
.bfd_arch_info
!= NULL
6672 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6674 switch (info
.bfd_arch_info
->mach
)
6676 case bfd_mach_mips3900
:
6677 found_abi
= MIPS_ABI_EABI32
;
6679 case bfd_mach_mips4100
:
6680 case bfd_mach_mips5000
:
6681 found_abi
= MIPS_ABI_EABI64
;
6683 case bfd_mach_mips8000
:
6684 case bfd_mach_mips10000
:
6685 /* On Irix, ELF64 executables use the N64 ABI. The
6686 pseudo-sections which describe the ABI aren't present
6687 on IRIX. (Even for executables created by gcc.) */
6688 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6689 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6690 found_abi
= MIPS_ABI_N64
;
6692 found_abi
= MIPS_ABI_N32
;
6697 /* Default 64-bit objects to N64 instead of O32. */
6698 if (found_abi
== MIPS_ABI_UNKNOWN
6699 && info
.abfd
!= NULL
6700 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6701 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6702 found_abi
= MIPS_ABI_N64
;
6705 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6708 /* What has the user specified from the command line? */
6709 wanted_abi
= global_mips_abi ();
6711 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6714 /* Now that we have found what the ABI for this binary would be,
6715 check whether the user is overriding it. */
6716 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6717 mips_abi
= wanted_abi
;
6718 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6719 mips_abi
= found_abi
;
6721 mips_abi
= MIPS_ABI_O32
;
6723 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6726 /* Also used when doing an architecture lookup. */
6728 fprintf_unfiltered (gdb_stdlog
,
6729 "mips_gdbarch_init: "
6730 "mips64_transfers_32bit_regs_p = %d\n",
6731 mips64_transfers_32bit_regs_p
);
6733 /* Determine the MIPS FPU type. */
6736 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6737 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6738 Tag_GNU_MIPS_ABI_FP
);
6739 #endif /* HAVE_ELF */
6741 if (!mips_fpu_type_auto
)
6742 fpu_type
= mips_fpu_type
;
6743 else if (elf_fpu_type
!= 0)
6745 switch (elf_fpu_type
)
6748 fpu_type
= MIPS_FPU_DOUBLE
;
6751 fpu_type
= MIPS_FPU_SINGLE
;
6755 /* Soft float or unknown. */
6756 fpu_type
= MIPS_FPU_NONE
;
6760 else if (info
.bfd_arch_info
!= NULL
6761 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6762 switch (info
.bfd_arch_info
->mach
)
6764 case bfd_mach_mips3900
:
6765 case bfd_mach_mips4100
:
6766 case bfd_mach_mips4111
:
6767 case bfd_mach_mips4120
:
6768 fpu_type
= MIPS_FPU_NONE
;
6770 case bfd_mach_mips4650
:
6771 fpu_type
= MIPS_FPU_SINGLE
;
6774 fpu_type
= MIPS_FPU_DOUBLE
;
6777 else if (arches
!= NULL
)
6778 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6780 fpu_type
= MIPS_FPU_DOUBLE
;
6782 fprintf_unfiltered (gdb_stdlog
,
6783 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6785 /* Check for blatant incompatibilities. */
6787 /* If we have only 32-bit registers, then we can't debug a 64-bit
6789 if (info
.target_desc
6790 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
6791 && mips_abi
!= MIPS_ABI_EABI32
6792 && mips_abi
!= MIPS_ABI_O32
)
6794 if (tdesc_data
!= NULL
)
6795 tdesc_data_cleanup (tdesc_data
);
6799 /* Try to find a pre-existing architecture. */
6800 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6802 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6804 /* MIPS needs to be pedantic about which ABI the object is
6806 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6808 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6810 /* Need to be pedantic about which register virtual size is
6812 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6813 != mips64_transfers_32bit_regs_p
)
6815 /* Be pedantic about which FPU is selected. */
6816 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6819 if (tdesc_data
!= NULL
)
6820 tdesc_data_cleanup (tdesc_data
);
6821 return arches
->gdbarch
;
6824 /* Need a new architecture. Fill in a target specific vector. */
6825 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6826 gdbarch
= gdbarch_alloc (&info
, tdep
);
6827 tdep
->elf_flags
= elf_flags
;
6828 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6829 tdep
->found_abi
= found_abi
;
6830 tdep
->mips_abi
= mips_abi
;
6831 tdep
->mips_fpu_type
= fpu_type
;
6832 tdep
->register_size_valid_p
= 0;
6833 tdep
->register_size
= 0;
6834 tdep
->gregset
= NULL
;
6835 tdep
->gregset64
= NULL
;
6836 tdep
->fpregset
= NULL
;
6837 tdep
->fpregset64
= NULL
;
6839 if (info
.target_desc
)
6841 /* Some useful properties can be inferred from the target. */
6842 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
6844 tdep
->register_size_valid_p
= 1;
6845 tdep
->register_size
= 4;
6847 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6849 tdep
->register_size_valid_p
= 1;
6850 tdep
->register_size
= 8;
6854 /* Initially set everything according to the default ABI/ISA. */
6855 set_gdbarch_short_bit (gdbarch
, 16);
6856 set_gdbarch_int_bit (gdbarch
, 32);
6857 set_gdbarch_float_bit (gdbarch
, 32);
6858 set_gdbarch_double_bit (gdbarch
, 64);
6859 set_gdbarch_long_double_bit (gdbarch
, 64);
6860 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6861 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6862 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6864 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6865 mips_ax_pseudo_register_collect
);
6866 set_gdbarch_ax_pseudo_register_push_stack
6867 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6869 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6870 mips_elf_make_msymbol_special
);
6872 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
6873 *regnum
= mips_regnum
;
6874 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6875 set_gdbarch_num_regs (gdbarch
, num_regs
);
6876 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6877 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6878 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6879 tdep
->mips_processor_reg_names
= reg_names
;
6880 tdep
->regnum
= regnum
;
6885 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6886 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6887 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6888 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6889 tdep
->default_mask_address_p
= 0;
6890 set_gdbarch_long_bit (gdbarch
, 32);
6891 set_gdbarch_ptr_bit (gdbarch
, 32);
6892 set_gdbarch_long_long_bit (gdbarch
, 64);
6895 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6896 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6897 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6898 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6899 tdep
->default_mask_address_p
= 0;
6900 set_gdbarch_long_bit (gdbarch
, 32);
6901 set_gdbarch_ptr_bit (gdbarch
, 32);
6902 set_gdbarch_long_long_bit (gdbarch
, 64);
6904 case MIPS_ABI_EABI32
:
6905 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6906 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6907 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6908 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6909 tdep
->default_mask_address_p
= 0;
6910 set_gdbarch_long_bit (gdbarch
, 32);
6911 set_gdbarch_ptr_bit (gdbarch
, 32);
6912 set_gdbarch_long_long_bit (gdbarch
, 64);
6914 case MIPS_ABI_EABI64
:
6915 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6916 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6917 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6918 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6919 tdep
->default_mask_address_p
= 0;
6920 set_gdbarch_long_bit (gdbarch
, 64);
6921 set_gdbarch_ptr_bit (gdbarch
, 64);
6922 set_gdbarch_long_long_bit (gdbarch
, 64);
6925 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6926 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6927 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6928 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6929 tdep
->default_mask_address_p
= 0;
6930 set_gdbarch_long_bit (gdbarch
, 32);
6931 set_gdbarch_ptr_bit (gdbarch
, 32);
6932 set_gdbarch_long_long_bit (gdbarch
, 64);
6933 set_gdbarch_long_double_bit (gdbarch
, 128);
6934 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6937 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6938 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6939 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6940 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6941 tdep
->default_mask_address_p
= 0;
6942 set_gdbarch_long_bit (gdbarch
, 64);
6943 set_gdbarch_ptr_bit (gdbarch
, 64);
6944 set_gdbarch_long_long_bit (gdbarch
, 64);
6945 set_gdbarch_long_double_bit (gdbarch
, 128);
6946 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6949 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6952 /* GCC creates a pseudo-section whose name specifies the size of
6953 longs, since -mlong32 or -mlong64 may be used independent of
6954 other options. How those options affect pointer sizes is ABI and
6955 architecture dependent, so use them to override the default sizes
6956 set by the ABI. This table shows the relationship between ABI,
6957 -mlongXX, and size of pointers:
6959 ABI -mlongXX ptr bits
6960 --- -------- --------
6974 Note that for o32 and eabi32, pointers are always 32 bits
6975 regardless of any -mlongXX option. For all others, pointers and
6976 longs are the same, as set by -mlongXX or set by defaults. */
6978 if (info
.abfd
!= NULL
)
6982 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6985 set_gdbarch_long_bit (gdbarch
, long_bit
);
6989 case MIPS_ABI_EABI32
:
6994 case MIPS_ABI_EABI64
:
6995 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6998 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
7003 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
7004 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
7007 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
7008 flag in object files because to do so would make it impossible to
7009 link with libraries compiled without "-gp32". This is
7010 unnecessarily restrictive.
7012 We could solve this problem by adding "-gp32" multilibs to gcc,
7013 but to set this flag before gcc is built with such multilibs will
7014 break too many systems.''
7016 But even more unhelpfully, the default linker output target for
7017 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
7018 for 64-bit programs - you need to change the ABI to change this,
7019 and not all gcc targets support that currently. Therefore using
7020 this flag to detect 32-bit mode would do the wrong thing given
7021 the current gcc - it would make GDB treat these 64-bit programs
7022 as 32-bit programs by default. */
7024 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
7025 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
7027 /* Add/remove bits from an address. The MIPS needs be careful to
7028 ensure that all 32 bit addresses are sign extended to 64 bits. */
7029 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
7031 /* Unwind the frame. */
7032 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
7033 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
7034 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
7036 /* Map debug register numbers onto internal register numbers. */
7037 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
7038 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
7039 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
7040 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
7041 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
7042 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
7044 /* MIPS version of CALL_DUMMY. */
7046 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7047 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
7048 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
7050 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
7051 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
7052 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
7054 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7055 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
7056 set_gdbarch_adjust_breakpoint_address (gdbarch
,
7057 mips_adjust_breakpoint_address
);
7059 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
7061 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
7063 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
7064 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
7065 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
7067 set_gdbarch_register_type (gdbarch
, mips_register_type
);
7069 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
7071 if (mips_abi
== MIPS_ABI_N32
)
7072 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
7073 else if (mips_abi
== MIPS_ABI_N64
)
7074 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
7076 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
7078 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
7079 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
7080 need to all be folded into the target vector. Since they are
7081 being used as guards for target_stopped_by_watchpoint, why not have
7082 target_stopped_by_watchpoint return the type of watchpoint that the code
7084 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
7086 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
7088 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
7089 to support MIPS16. This is a bad thing. Make sure not to do it
7090 if we have an OS ABI that actually supports shared libraries, since
7091 shared library support is more important. If we have an OS someday
7092 that supports both shared libraries and MIPS16, we'll have to find
7093 a better place for these.
7094 macro/2012-04-25: But that applies to return trampolines only and
7095 currently no MIPS OS ABI uses shared libraries that have them. */
7096 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
7098 set_gdbarch_single_step_through_delay (gdbarch
,
7099 mips_single_step_through_delay
);
7101 /* Virtual tables. */
7102 set_gdbarch_vbit_in_delta (gdbarch
, 1);
7104 mips_register_g_packet_guesses (gdbarch
);
7106 /* Hook in OS ABI-specific overrides, if they have been registered. */
7107 info
.tdep_info
= (void *) tdesc_data
;
7108 gdbarch_init_osabi (info
, gdbarch
);
7110 /* The hook may have adjusted num_regs, fetch the final value and
7111 set pc_regnum and sp_regnum now that it has been fixed. */
7112 num_regs
= gdbarch_num_regs (gdbarch
);
7113 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
7114 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
7116 /* Unwind the frame. */
7117 dwarf2_append_unwinders (gdbarch
);
7118 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
7119 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
7120 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
7121 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
7122 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
7123 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
7124 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
7128 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
7129 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
7131 /* Override the normal target description methods to handle our
7132 dual real and pseudo registers. */
7133 set_gdbarch_register_name (gdbarch
, mips_register_name
);
7134 set_gdbarch_register_reggroup_p (gdbarch
,
7135 mips_tdesc_register_reggroup_p
);
7137 num_regs
= gdbarch_num_regs (gdbarch
);
7138 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
7139 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
7140 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
7143 /* Add ABI-specific aliases for the registers. */
7144 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
7145 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
7146 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
7147 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
7149 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
7150 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
7151 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
7153 /* Add some other standard aliases. */
7154 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
7155 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
7156 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
7158 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
7159 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
7160 value_of_mips_user_reg
,
7161 &mips_numeric_register_aliases
[i
].regnum
);
7167 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
7169 struct gdbarch_info info
;
7171 /* Force the architecture to update, and (if it's a MIPS architecture)
7172 mips_gdbarch_init will take care of the rest. */
7173 gdbarch_info_init (&info
);
7174 gdbarch_update_p (info
);
7177 /* Print out which MIPS ABI is in use. */
7180 show_mips_abi (struct ui_file
*file
,
7182 struct cmd_list_element
*ignored_cmd
,
7183 const char *ignored_value
)
7185 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
7188 "The MIPS ABI is unknown because the current architecture "
7192 enum mips_abi global_abi
= global_mips_abi ();
7193 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
7194 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
7196 if (global_abi
== MIPS_ABI_UNKNOWN
)
7199 "The MIPS ABI is set automatically (currently \"%s\").\n",
7201 else if (global_abi
== actual_abi
)
7204 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
7208 /* Probably shouldn't happen... */
7209 fprintf_filtered (file
,
7210 "The (auto detected) MIPS ABI \"%s\" is in use "
7211 "even though the user setting was \"%s\".\n",
7212 actual_abi_str
, mips_abi_strings
[global_abi
]);
7218 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7224 int ef_mips_32bitmode
;
7225 /* Determine the ISA. */
7226 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
7244 /* Determine the size of a pointer. */
7245 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
7246 fprintf_unfiltered (file
,
7247 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
7249 fprintf_unfiltered (file
,
7250 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
7252 fprintf_unfiltered (file
,
7253 "mips_dump_tdep: ef_mips_arch = %d\n",
7255 fprintf_unfiltered (file
,
7256 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
7257 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
7258 fprintf_unfiltered (file
,
7260 "mips_mask_address_p() %d (default %d)\n",
7261 mips_mask_address_p (tdep
),
7262 tdep
->default_mask_address_p
);
7264 fprintf_unfiltered (file
,
7265 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
7266 MIPS_DEFAULT_FPU_TYPE
,
7267 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
7268 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
7269 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
7271 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
7272 MIPS_EABI (gdbarch
));
7273 fprintf_unfiltered (file
,
7274 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
7275 MIPS_FPU_TYPE (gdbarch
),
7276 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
7277 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
7278 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
7282 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
7285 _initialize_mips_tdep (void)
7287 static struct cmd_list_element
*mipsfpulist
= NULL
;
7288 struct cmd_list_element
*c
;
7290 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
7291 if (MIPS_ABI_LAST
+ 1
7292 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
7293 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
7295 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
7297 mips_pdr_data
= register_objfile_data ();
7299 /* Create feature sets with the appropriate properties. The values
7300 are not important. */
7301 mips_tdesc_gp32
= allocate_target_description ();
7302 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
7304 mips_tdesc_gp64
= allocate_target_description ();
7305 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
7307 /* Add root prefix command for all "set mips"/"show mips" commands. */
7308 add_prefix_cmd ("mips", no_class
, set_mips_command
,
7309 _("Various MIPS specific commands."),
7310 &setmipscmdlist
, "set mips ", 0, &setlist
);
7312 add_prefix_cmd ("mips", no_class
, show_mips_command
,
7313 _("Various MIPS specific commands."),
7314 &showmipscmdlist
, "show mips ", 0, &showlist
);
7316 /* Allow the user to override the ABI. */
7317 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
7318 &mips_abi_string
, _("\
7319 Set the MIPS ABI used by this program."), _("\
7320 Show the MIPS ABI used by this program."), _("\
7321 This option can be set to one of:\n\
7322 auto - the default ABI associated with the current binary\n\
7331 &setmipscmdlist
, &showmipscmdlist
);
7333 /* Let the user turn off floating point and set the fence post for
7334 heuristic_proc_start. */
7336 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
7337 _("Set use of MIPS floating-point coprocessor."),
7338 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
7339 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
7340 _("Select single-precision MIPS floating-point coprocessor."),
7342 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
7343 _("Select double-precision MIPS floating-point coprocessor."),
7345 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
7346 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
7347 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
7348 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
7349 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
7350 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
7351 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
7352 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
7353 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
7354 _("Select MIPS floating-point coprocessor automatically."),
7356 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
7357 _("Show current use of MIPS floating-point coprocessor target."),
7360 /* We really would like to have both "0" and "unlimited" work, but
7361 command.c doesn't deal with that. So make it a var_zinteger
7362 because the user can always use "999999" or some such for unlimited. */
7363 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
7364 &heuristic_fence_post
, _("\
7365 Set the distance searched for the start of a function."), _("\
7366 Show the distance searched for the start of a function."), _("\
7367 If you are debugging a stripped executable, GDB needs to search through the\n\
7368 program for the start of a function. This command sets the distance of the\n\
7369 search. The only need to set it is when debugging a stripped executable."),
7370 reinit_frame_cache_sfunc
,
7371 NULL
, /* FIXME: i18n: The distance searched for
7372 the start of a function is %s. */
7373 &setlist
, &showlist
);
7375 /* Allow the user to control whether the upper bits of 64-bit
7376 addresses should be zeroed. */
7377 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
7378 &mask_address_var
, _("\
7379 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
7380 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
7381 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
7382 allow GDB to determine the correct value."),
7383 NULL
, show_mask_address
,
7384 &setmipscmdlist
, &showmipscmdlist
);
7386 /* Allow the user to control the size of 32 bit registers within the
7387 raw remote packet. */
7388 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
7389 &mips64_transfers_32bit_regs_p
, _("\
7390 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
7392 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
7394 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
7395 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
7396 64 bits for others. Use \"off\" to disable compatibility mode"),
7397 set_mips64_transfers_32bit_regs
,
7398 NULL
, /* FIXME: i18n: Compatibility with 64-bit
7399 MIPS target that transfers 32-bit
7400 quantities is %s. */
7401 &setlist
, &showlist
);
7403 /* Debug this files internals. */
7404 add_setshow_zinteger_cmd ("mips", class_maintenance
,
7406 Set mips debugging."), _("\
7407 Show mips debugging."), _("\
7408 When non-zero, mips specific debugging is enabled."),
7410 NULL
, /* FIXME: i18n: Mips debugging is
7412 &setdebuglist
, &showdebuglist
);