1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
54 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
55 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
57 /* A useful bit in the CP0 status register (PS_REGNUM). */
58 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
59 #define ST0_FR (1 << 26)
61 /* The sizes of floating point registers. */
65 MIPS_FPU_SINGLE_REGSIZE
= 4,
66 MIPS_FPU_DOUBLE_REGSIZE
= 8
70 static const char *mips_abi_string
;
72 static const char *mips_abi_strings
[] = {
83 struct frame_extra_info
85 mips_extra_func_info_t proc_desc
;
89 /* Various MIPS ISA options (related to stack analysis) can be
90 overridden dynamically. Establish an enum/array for managing
93 static const char size_auto
[] = "auto";
94 static const char size_32
[] = "32";
95 static const char size_64
[] = "64";
97 static const char *size_enums
[] = {
104 /* Some MIPS boards don't support floating point while others only
105 support single-precision floating-point operations. See also
106 FP_REGISTER_DOUBLE. */
110 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
111 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
112 MIPS_FPU_NONE
/* No floating point. */
115 #ifndef MIPS_DEFAULT_FPU_TYPE
116 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
118 static int mips_fpu_type_auto
= 1;
119 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
121 static int mips_debug
= 0;
123 /* MIPS specific per-architecture information */
126 /* from the elf header */
130 enum mips_abi mips_abi
;
131 enum mips_abi found_abi
;
132 enum mips_fpu_type mips_fpu_type
;
133 int mips_last_arg_regnum
;
134 int mips_last_fp_arg_regnum
;
135 int mips_default_saved_regsize
;
136 int mips_fp_register_double
;
137 int mips_default_stack_argsize
;
138 int default_mask_address_p
;
139 /* Is the target using 64-bit raw integer registers but only
140 storing a left-aligned 32-bit value in each? */
141 int mips64_transfers_32bit_regs_p
;
142 /* Indexes for various registers. IRIX and embedded have
143 different values. This contains the "public" fields. Don't
144 add any that do not need to be public. */
145 const struct mips_regnum
*regnum
;
146 /* Register names table for the current register set. */
147 const char **mips_processor_reg_names
;
150 const struct mips_regnum
*
151 mips_regnum (struct gdbarch
*gdbarch
)
153 return gdbarch_tdep (gdbarch
)->regnum
;
157 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
159 return mips_regnum (gdbarch
)->fp0
+ 12;
162 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
163 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
165 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
167 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
169 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
171 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
172 functions to test, set, or clear bit 0 of addresses. */
175 is_mips16_addr (CORE_ADDR addr
)
181 make_mips16_addr (CORE_ADDR addr
)
187 unmake_mips16_addr (CORE_ADDR addr
)
189 return ((addr
) & ~1);
192 /* Return the contents of register REGNUM as a signed integer. */
195 read_signed_register (int regnum
)
197 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
198 deprecated_read_register_gen (regnum
, buf
);
199 return (extract_signed_integer
200 (buf
, register_size (current_gdbarch
, regnum
)));
204 read_signed_register_pid (int regnum
, ptid_t ptid
)
209 if (ptid_equal (ptid
, inferior_ptid
))
210 return read_signed_register (regnum
);
212 save_ptid
= inferior_ptid
;
214 inferior_ptid
= ptid
;
216 retval
= read_signed_register (regnum
);
218 inferior_ptid
= save_ptid
;
223 /* Return the MIPS ABI associated with GDBARCH. */
225 mips_abi (struct gdbarch
*gdbarch
)
227 return gdbarch_tdep (gdbarch
)->mips_abi
;
231 mips_regsize (struct gdbarch
*gdbarch
)
233 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
234 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
237 /* Return the currently configured (or set) saved register size. */
239 static const char *mips_saved_regsize_string
= size_auto
;
242 mips_saved_regsize (struct gdbarch_tdep
*tdep
)
244 if (mips_saved_regsize_string
== size_auto
)
245 return tdep
->mips_default_saved_regsize
;
246 else if (mips_saved_regsize_string
== size_64
)
248 else /* if (mips_saved_regsize_string == size_32) */
252 /* Functions for setting and testing a bit in a minimal symbol that
253 marks it as 16-bit function. The MSB of the minimal symbol's
254 "info" field is used for this purpose.
256 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
257 i.e. refers to a 16-bit function, and sets a "special" bit in a
258 minimal symbol to mark it as a 16-bit function
260 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
263 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
265 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
267 MSYMBOL_INFO (msym
) = (char *)
268 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
269 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
274 msymbol_is_special (struct minimal_symbol
*msym
)
276 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
279 /* XFER a value from the big/little/left end of the register.
280 Depending on the size of the value it might occupy the entire
281 register or just part of it. Make an allowance for this, aligning
282 things accordingly. */
285 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
286 enum bfd_endian endian
, bfd_byte
* in
,
287 const bfd_byte
* out
, int buf_offset
)
289 bfd_byte reg
[MAX_REGISTER_SIZE
];
291 gdb_assert (reg_num
>= NUM_REGS
);
292 /* Need to transfer the left or right part of the register, based on
293 the targets byte order. */
297 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
299 case BFD_ENDIAN_LITTLE
:
302 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
306 internal_error (__FILE__
, __LINE__
, "bad switch");
309 fprintf_unfiltered (gdb_stderr
,
310 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
311 reg_num
, reg_offset
, buf_offset
, length
);
312 if (mips_debug
&& out
!= NULL
)
315 fprintf_unfiltered (gdb_stdlog
, "out ");
316 for (i
= 0; i
< length
; i
++)
317 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
320 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
323 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
325 if (mips_debug
&& in
!= NULL
)
328 fprintf_unfiltered (gdb_stdlog
, "in ");
329 for (i
= 0; i
< length
; i
++)
330 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
333 fprintf_unfiltered (gdb_stdlog
, "\n");
336 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
337 compatiblity mode. A return value of 1 means that we have
338 physical 64-bit registers, but should treat them as 32-bit registers. */
341 mips2_fp_compat (void)
343 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
345 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
350 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
351 in all the places we deal with FP registers. PR gdb/413. */
352 /* Otherwise check the FR bit in the status register - it controls
353 the FP compatiblity mode. If it is clear we are in compatibility
355 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
362 /* Indicate that the ABI makes use of double-precision registers
363 provided by the FPU (rather than combining pairs of registers to
364 form double-precision values). See also MIPS_FPU_TYPE. */
365 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
367 /* The amount of space reserved on the stack for registers. This is
368 different to MIPS_SAVED_REGSIZE as it determines the alignment of
369 data allocated after the registers have run out. */
371 static const char *mips_stack_argsize_string
= size_auto
;
374 mips_stack_argsize (struct gdbarch_tdep
*tdep
)
376 if (mips_stack_argsize_string
== size_auto
)
377 return tdep
->mips_default_stack_argsize
;
378 else if (mips_stack_argsize_string
== size_64
)
380 else /* if (mips_stack_argsize_string == size_32) */
384 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
386 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
387 struct frame_info
*, int);
389 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
391 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
393 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
395 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
396 struct frame_info
*next_frame
,
399 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
400 mips_extra_func_info_t proc_desc
);
402 static struct type
*mips_float_register_type (void);
403 static struct type
*mips_double_register_type (void);
405 /* The list of available "set mips " and "show mips " commands */
407 static struct cmd_list_element
*setmipscmdlist
= NULL
;
408 static struct cmd_list_element
*showmipscmdlist
= NULL
;
410 /* Integer registers 0 thru 31 are handled explicitly by
411 mips_register_name(). Processor specific registers 32 and above
412 are listed in the followign tables. */
415 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
419 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
420 "sr", "lo", "hi", "bad", "cause", "pc",
421 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
422 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
423 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
424 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
425 "fsr", "fir", "" /*"fp" */ , "",
426 "", "", "", "", "", "", "", "",
427 "", "", "", "", "", "", "", "",
430 /* Names of IDT R3041 registers. */
432 static const char *mips_r3041_reg_names
[] = {
433 "sr", "lo", "hi", "bad", "cause", "pc",
434 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
435 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
436 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
437 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
438 "fsr", "fir", "", /*"fp" */ "",
439 "", "", "bus", "ccfg", "", "", "", "",
440 "", "", "port", "cmp", "", "", "epc", "prid",
443 /* Names of tx39 registers. */
445 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
446 "sr", "lo", "hi", "bad", "cause", "pc",
447 "", "", "", "", "", "", "", "",
448 "", "", "", "", "", "", "", "",
449 "", "", "", "", "", "", "", "",
450 "", "", "", "", "", "", "", "",
452 "", "", "", "", "", "", "", "",
453 "", "", "config", "cache", "debug", "depc", "epc", ""
456 /* Names of IRIX registers. */
457 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
458 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
459 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
460 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
461 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
462 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
466 /* Return the name of the register corresponding to REGNO. */
468 mips_register_name (int regno
)
470 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
471 /* GPR names for all ABIs other than n32/n64. */
472 static char *mips_gpr_names
[] = {
473 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
474 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
475 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
476 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
479 /* GPR names for n32 and n64 ABIs. */
480 static char *mips_n32_n64_gpr_names
[] = {
481 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
482 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
483 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
484 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
487 enum mips_abi abi
= mips_abi (current_gdbarch
);
489 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
490 don't make the raw register names visible. */
491 int rawnum
= regno
% NUM_REGS
;
492 if (regno
< NUM_REGS
)
495 /* The MIPS integer registers are always mapped from 0 to 31. The
496 names of the registers (which reflects the conventions regarding
497 register use) vary depending on the ABI. */
498 if (0 <= rawnum
&& rawnum
< 32)
500 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
501 return mips_n32_n64_gpr_names
[rawnum
];
503 return mips_gpr_names
[rawnum
];
505 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
507 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
508 return tdep
->mips_processor_reg_names
[rawnum
- 32];
511 internal_error (__FILE__
, __LINE__
,
512 "mips_register_name: bad register number %d", rawnum
);
515 /* Return the groups that a MIPS register can be categorised into. */
518 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
519 struct reggroup
*reggroup
)
524 int rawnum
= regnum
% NUM_REGS
;
525 int pseudo
= regnum
/ NUM_REGS
;
526 if (reggroup
== all_reggroup
)
528 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
529 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
530 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
531 (gdbarch), as not all architectures are multi-arch. */
532 raw_p
= rawnum
< NUM_REGS
;
533 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
535 if (reggroup
== float_reggroup
)
536 return float_p
&& pseudo
;
537 if (reggroup
== vector_reggroup
)
538 return vector_p
&& pseudo
;
539 if (reggroup
== general_reggroup
)
540 return (!vector_p
&& !float_p
) && pseudo
;
541 /* Save the pseudo registers. Need to make certain that any code
542 extracting register values from a saved register cache also uses
544 if (reggroup
== save_reggroup
)
545 return raw_p
&& pseudo
;
546 /* Restore the same pseudo register. */
547 if (reggroup
== restore_reggroup
)
548 return raw_p
&& pseudo
;
552 /* Map the symbol table registers which live in the range [1 *
553 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
554 registers. Take care of alignment and size problems. */
557 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
558 int cookednum
, void *buf
)
560 int rawnum
= cookednum
% NUM_REGS
;
561 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
562 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
563 regcache_raw_read (regcache
, rawnum
, buf
);
564 else if (register_size (gdbarch
, rawnum
) >
565 register_size (gdbarch
, cookednum
))
567 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
568 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
569 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
571 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
574 internal_error (__FILE__
, __LINE__
, "bad register size");
578 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
579 struct regcache
*regcache
, int cookednum
,
582 int rawnum
= cookednum
% NUM_REGS
;
583 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
584 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
585 regcache_raw_write (regcache
, rawnum
, buf
);
586 else if (register_size (gdbarch
, rawnum
) >
587 register_size (gdbarch
, cookednum
))
589 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
590 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
591 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
593 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
596 internal_error (__FILE__
, __LINE__
, "bad register size");
599 /* Table to translate MIPS16 register field to actual register number. */
600 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
602 /* Heuristic_proc_start may hunt through the text section for a long
603 time across a 2400 baud serial line. Allows the user to limit this
606 static unsigned int heuristic_fence_post
= 0;
608 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
609 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
610 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
611 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
612 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
613 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
614 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
615 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
616 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
617 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
618 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
619 this will corrupt pdr.iline. Fortunately we don't use it. */
620 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
621 #define _PROC_MAGIC_ 0x0F0F0F0F
622 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
623 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
625 struct linked_proc_info
627 struct mips_extra_func_info info
;
628 struct linked_proc_info
*next
;
630 *linked_proc_desc_table
= NULL
;
632 /* Number of bytes of storage in the actual machine representation for
633 register N. NOTE: This defines the pseudo register type so need to
634 rebuild the architecture vector. */
636 static int mips64_transfers_32bit_regs_p
= 0;
639 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
640 struct cmd_list_element
*c
)
642 struct gdbarch_info info
;
643 gdbarch_info_init (&info
);
644 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
645 instead of relying on globals. Doing that would let generic code
646 handle the search for this specific architecture. */
647 if (!gdbarch_update_p (info
))
649 mips64_transfers_32bit_regs_p
= 0;
650 error ("32-bit compatibility mode not supported");
654 /* Convert to/from a register and the corresponding memory value. */
657 mips_convert_register_p (int regnum
, struct type
*type
)
659 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
660 && register_size (current_gdbarch
, regnum
) == 4
661 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
662 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
663 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
667 mips_register_to_value (struct frame_info
*frame
, int regnum
,
668 struct type
*type
, void *to
)
670 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
671 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
675 mips_value_to_register (struct frame_info
*frame
, int regnum
,
676 struct type
*type
, const void *from
)
678 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
679 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
682 /* Return the GDB type object for the "standard" data type of data in
686 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
688 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
689 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
690 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
692 /* The floating-point registers raw, or cooked, always match
693 mips_regsize(), and also map 1:1, byte for byte. */
694 switch (gdbarch_byte_order (gdbarch
))
697 if (mips_regsize (gdbarch
) == 4)
698 return builtin_type_ieee_single_big
;
700 return builtin_type_ieee_double_big
;
701 case BFD_ENDIAN_LITTLE
:
702 if (mips_regsize (gdbarch
) == 4)
703 return builtin_type_ieee_single_little
;
705 return builtin_type_ieee_double_little
;
706 case BFD_ENDIAN_UNKNOWN
:
708 internal_error (__FILE__
, __LINE__
, "bad switch");
712 (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
713 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
714 /* The pseudo/cooked view of the embedded registers is always
715 32-bit. The raw view is handled below. */
716 return builtin_type_int32
;
717 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
718 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
719 /* The target, while using a 64-bit register buffer, is only
720 transfering 32-bits of each integer register. Reflect this in
721 the cooked/pseudo register value. */
722 return builtin_type_int32
;
723 else if (mips_regsize (gdbarch
) == 8)
725 return builtin_type_int64
;
728 return builtin_type_int32
;
731 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
736 return read_signed_register (SP_REGNUM
);
739 /* Should the upper word of 64-bit addresses be zeroed? */
740 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
743 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
745 switch (mask_address_var
)
747 case AUTO_BOOLEAN_TRUE
:
749 case AUTO_BOOLEAN_FALSE
:
752 case AUTO_BOOLEAN_AUTO
:
753 return tdep
->default_mask_address_p
;
755 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
761 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
763 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
764 switch (mask_address_var
)
766 case AUTO_BOOLEAN_TRUE
:
767 printf_filtered ("The 32 bit mips address mask is enabled\n");
769 case AUTO_BOOLEAN_FALSE
:
770 printf_filtered ("The 32 bit mips address mask is disabled\n");
772 case AUTO_BOOLEAN_AUTO
:
774 ("The 32 bit address mask is set automatically. Currently %s\n",
775 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
778 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
783 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
786 pc_is_mips16 (bfd_vma memaddr
)
788 struct minimal_symbol
*sym
;
790 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
791 if (is_mips16_addr (memaddr
))
794 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
795 the high bit of the info field. Use this to decide if the function is
796 MIPS16 or normal MIPS. */
797 sym
= lookup_minimal_symbol_by_pc (memaddr
);
799 return msymbol_is_special (sym
);
804 /* MIPS believes that the PC has a sign extended value. Perhaphs the
805 all registers should be sign extended for simplicity? */
808 mips_read_pc (ptid_t ptid
)
810 return read_signed_register_pid (PC_REGNUM
, ptid
);
813 /* This returns the PC of the first inst after the prologue. If we can't
814 find the prologue, then return 0. */
817 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
819 struct symtab_and_line sal
;
820 CORE_ADDR func_addr
, func_end
;
822 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
823 to read the stack pointer from the current machine state, because
824 the current machine state has nothing to do with the information
825 we need from the proc_desc; and the process may or may not exist
828 proc_desc
= find_proc_desc (pc
, NULL
, 0);
832 /* If function is frameless, then we need to do it the hard way. I
833 strongly suspect that frameless always means prologueless... */
834 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
835 && PROC_FRAME_OFFSET (proc_desc
) == 0)
839 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
840 return 0; /* Unknown */
842 sal
= find_pc_line (func_addr
, 0);
844 if (sal
.end
< func_end
)
847 /* The line after the prologue is after the end of the function. In this
848 case, tell the caller to find the prologue the hard way. */
853 /* Decode a MIPS32 instruction that saves a register in the stack, and
854 set the appropriate bit in the general register mask or float register mask
855 to indicate which register is saved. This is a helper function
856 for mips_find_saved_regs. */
859 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
860 unsigned long *float_mask
)
864 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
865 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
866 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
868 /* It might be possible to use the instruction to
869 find the offset, rather than the code below which
870 is based on things being in a certain order in the
871 frame, but figuring out what the instruction's offset
872 is relative to might be a little tricky. */
873 reg
= (inst
& 0x001f0000) >> 16;
874 *gen_mask
|= (1 << reg
);
876 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
877 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
878 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
881 reg
= ((inst
& 0x001f0000) >> 16);
882 *float_mask
|= (1 << reg
);
886 /* Decode a MIPS16 instruction that saves a register in the stack, and
887 set the appropriate bit in the general register or float register mask
888 to indicate which register is saved. This is a helper function
889 for mips_find_saved_regs. */
892 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
894 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
896 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
897 *gen_mask
|= (1 << reg
);
899 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
901 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
902 *gen_mask
|= (1 << reg
);
904 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
905 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
906 *gen_mask
|= (1 << RA_REGNUM
);
910 /* Fetch and return instruction from the specified location. If the PC
911 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
914 mips_fetch_instruction (CORE_ADDR addr
)
916 char buf
[MIPS_INSTLEN
];
920 if (pc_is_mips16 (addr
))
922 instlen
= MIPS16_INSTLEN
;
923 addr
= unmake_mips16_addr (addr
);
926 instlen
= MIPS_INSTLEN
;
927 status
= read_memory_nobpt (addr
, buf
, instlen
);
929 memory_error (status
, addr
);
930 return extract_unsigned_integer (buf
, instlen
);
934 /* These the fields of 32 bit mips instructions */
935 #define mips32_op(x) (x >> 26)
936 #define itype_op(x) (x >> 26)
937 #define itype_rs(x) ((x >> 21) & 0x1f)
938 #define itype_rt(x) ((x >> 16) & 0x1f)
939 #define itype_immediate(x) (x & 0xffff)
941 #define jtype_op(x) (x >> 26)
942 #define jtype_target(x) (x & 0x03ffffff)
944 #define rtype_op(x) (x >> 26)
945 #define rtype_rs(x) ((x >> 21) & 0x1f)
946 #define rtype_rt(x) ((x >> 16) & 0x1f)
947 #define rtype_rd(x) ((x >> 11) & 0x1f)
948 #define rtype_shamt(x) ((x >> 6) & 0x1f)
949 #define rtype_funct(x) (x & 0x3f)
952 mips32_relative_offset (unsigned long inst
)
955 x
= itype_immediate (inst
);
956 if (x
& 0x8000) /* sign bit set */
958 x
|= 0xffff0000; /* sign extension */
964 /* Determine whate to set a single step breakpoint while considering
967 mips32_next_pc (CORE_ADDR pc
)
971 inst
= mips_fetch_instruction (pc
);
972 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
974 if (itype_op (inst
) >> 2 == 5)
975 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
977 op
= (itype_op (inst
) & 0x03);
992 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
993 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
995 int tf
= itype_rt (inst
) & 0x01;
996 int cnum
= itype_rt (inst
) >> 2;
998 read_signed_register (mips_regnum (current_gdbarch
)->
1000 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1002 if (((cond
>> cnum
) & 0x01) == tf
)
1003 pc
+= mips32_relative_offset (inst
) + 4;
1008 pc
+= 4; /* Not a branch, next instruction is easy */
1011 { /* This gets way messy */
1013 /* Further subdivide into SPECIAL, REGIMM and other */
1014 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1016 case 0: /* SPECIAL */
1017 op
= rtype_funct (inst
);
1022 /* Set PC to that address */
1023 pc
= read_signed_register (rtype_rs (inst
));
1029 break; /* end SPECIAL */
1030 case 1: /* REGIMM */
1032 op
= itype_rt (inst
); /* branch condition */
1037 case 16: /* BLTZAL */
1038 case 18: /* BLTZALL */
1040 if (read_signed_register (itype_rs (inst
)) < 0)
1041 pc
+= mips32_relative_offset (inst
) + 4;
1043 pc
+= 8; /* after the delay slot */
1047 case 17: /* BGEZAL */
1048 case 19: /* BGEZALL */
1049 if (read_signed_register (itype_rs (inst
)) >= 0)
1050 pc
+= mips32_relative_offset (inst
) + 4;
1052 pc
+= 8; /* after the delay slot */
1054 /* All of the other instructions in the REGIMM category */
1059 break; /* end REGIMM */
1064 reg
= jtype_target (inst
) << 2;
1065 /* Upper four bits get never changed... */
1066 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1069 /* FIXME case JALX : */
1072 reg
= jtype_target (inst
) << 2;
1073 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1074 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1076 break; /* The new PC will be alternate mode */
1077 case 4: /* BEQ, BEQL */
1079 if (read_signed_register (itype_rs (inst
)) ==
1080 read_signed_register (itype_rt (inst
)))
1081 pc
+= mips32_relative_offset (inst
) + 4;
1085 case 5: /* BNE, BNEL */
1087 if (read_signed_register (itype_rs (inst
)) !=
1088 read_signed_register (itype_rt (inst
)))
1089 pc
+= mips32_relative_offset (inst
) + 4;
1093 case 6: /* BLEZ, BLEZL */
1094 if (read_signed_register (itype_rs (inst
) <= 0))
1095 pc
+= mips32_relative_offset (inst
) + 4;
1101 greater_branch
: /* BGTZ, BGTZL */
1102 if (read_signed_register (itype_rs (inst
) > 0))
1103 pc
+= mips32_relative_offset (inst
) + 4;
1110 } /* mips32_next_pc */
1112 /* Decoding the next place to set a breakpoint is irregular for the
1113 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1114 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1115 We dont want to set a single step instruction on the extend instruction
1119 /* Lots of mips16 instruction formats */
1120 /* Predicting jumps requires itype,ritype,i8type
1121 and their extensions extItype,extritype,extI8type
1123 enum mips16_inst_fmts
1125 itype
, /* 0 immediate 5,10 */
1126 ritype
, /* 1 5,3,8 */
1127 rrtype
, /* 2 5,3,3,5 */
1128 rritype
, /* 3 5,3,3,5 */
1129 rrrtype
, /* 4 5,3,3,3,2 */
1130 rriatype
, /* 5 5,3,3,1,4 */
1131 shifttype
, /* 6 5,3,3,3,2 */
1132 i8type
, /* 7 5,3,8 */
1133 i8movtype
, /* 8 5,3,3,5 */
1134 i8mov32rtype
, /* 9 5,3,5,3 */
1135 i64type
, /* 10 5,3,8 */
1136 ri64type
, /* 11 5,3,3,5 */
1137 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1138 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1139 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1140 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1141 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1142 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1143 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1144 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1145 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1146 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1148 /* I am heaping all the fields of the formats into one structure and
1149 then, only the fields which are involved in instruction extension */
1153 unsigned int regx
; /* Function in i8 type */
1158 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1159 for the bits which make up the immediatate extension. */
1162 extended_offset (unsigned int extension
)
1165 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1167 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1169 value
|= extension
& 0x01f; /* extract 4:0 */
1173 /* Only call this function if you know that this is an extendable
1174 instruction, It wont malfunction, but why make excess remote memory references?
1175 If the immediate operands get sign extended or somthing, do it after
1176 the extension is performed.
1178 /* FIXME: Every one of these cases needs to worry about sign extension
1179 when the offset is to be used in relative addressing */
1183 fetch_mips_16 (CORE_ADDR pc
)
1186 pc
&= 0xfffffffe; /* clear the low order bit */
1187 target_read_memory (pc
, buf
, 2);
1188 return extract_unsigned_integer (buf
, 2);
1192 unpack_mips16 (CORE_ADDR pc
,
1193 unsigned int extension
,
1195 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1200 switch (insn_format
)
1207 value
= extended_offset (extension
);
1208 value
= value
<< 11; /* rom for the original value */
1209 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1213 value
= inst
& 0x7ff;
1214 /* FIXME : Consider sign extension */
1223 { /* A register identifier and an offset */
1224 /* Most of the fields are the same as I type but the
1225 immediate value is of a different length */
1229 value
= extended_offset (extension
);
1230 value
= value
<< 8; /* from the original instruction */
1231 value
|= inst
& 0xff; /* eleven bits from instruction */
1232 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1233 if (value
& 0x4000) /* test the sign bit , bit 26 */
1235 value
&= ~0x3fff; /* remove the sign bit */
1241 value
= inst
& 0xff; /* 8 bits */
1242 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1243 /* FIXME: Do sign extension , this format needs it */
1244 if (value
& 0x80) /* THIS CONFUSES ME */
1246 value
&= 0xef; /* remove the sign bit */
1256 unsigned long value
;
1257 unsigned int nexthalf
;
1258 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1259 value
= value
<< 16;
1260 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1268 internal_error (__FILE__
, __LINE__
, "bad switch");
1270 upk
->offset
= offset
;
1277 add_offset_16 (CORE_ADDR pc
, int offset
)
1279 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1283 extended_mips16_next_pc (CORE_ADDR pc
,
1284 unsigned int extension
, unsigned int insn
)
1286 int op
= (insn
>> 11);
1289 case 2: /* Branch */
1292 struct upk_mips16 upk
;
1293 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1294 offset
= upk
.offset
;
1300 pc
+= (offset
<< 1) + 2;
1303 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1305 struct upk_mips16 upk
;
1306 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1307 pc
= add_offset_16 (pc
, upk
.offset
);
1308 if ((insn
>> 10) & 0x01) /* Exchange mode */
1309 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1316 struct upk_mips16 upk
;
1318 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1319 reg
= read_signed_register (upk
.regx
);
1321 pc
+= (upk
.offset
<< 1) + 2;
1328 struct upk_mips16 upk
;
1330 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1331 reg
= read_signed_register (upk
.regx
);
1333 pc
+= (upk
.offset
<< 1) + 2;
1338 case 12: /* I8 Formats btez btnez */
1340 struct upk_mips16 upk
;
1342 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1343 /* upk.regx contains the opcode */
1344 reg
= read_signed_register (24); /* Test register is 24 */
1345 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1346 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1347 /* pc = add_offset_16(pc,upk.offset) ; */
1348 pc
+= (upk
.offset
<< 1) + 2;
1353 case 29: /* RR Formats JR, JALR, JALR-RA */
1355 struct upk_mips16 upk
;
1356 /* upk.fmt = rrtype; */
1361 upk
.regx
= (insn
>> 8) & 0x07;
1362 upk
.regy
= (insn
>> 5) & 0x07;
1370 break; /* Function return instruction */
1376 break; /* BOGUS Guess */
1378 pc
= read_signed_register (reg
);
1385 /* This is an instruction extension. Fetch the real instruction
1386 (which follows the extension) and decode things based on
1390 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1403 mips16_next_pc (CORE_ADDR pc
)
1405 unsigned int insn
= fetch_mips_16 (pc
);
1406 return extended_mips16_next_pc (pc
, 0, insn
);
1409 /* The mips_next_pc function supports single_step when the remote
1410 target monitor or stub is not developed enough to do a single_step.
1411 It works by decoding the current instruction and predicting where a
1412 branch will go. This isnt hard because all the data is available.
1413 The MIPS32 and MIPS16 variants are quite different */
1415 mips_next_pc (CORE_ADDR pc
)
1418 return mips16_next_pc (pc
);
1420 return mips32_next_pc (pc
);
1423 /* Set up the 'saved_regs' array. This is a data structure containing
1424 the addresses on the stack where each register has been saved, for
1425 each stack frame. Registers that have not been saved will have
1426 zero here. The stack pointer register is special: rather than the
1427 address where the stack register has been saved,
1428 saved_regs[SP_REGNUM] will have the actual value of the previous
1429 frame's stack register. */
1432 mips_find_saved_regs (struct frame_info
*fci
)
1435 /* r0 bit means kernel trap */
1437 /* What registers have been saved? Bitmasks. */
1438 unsigned long gen_mask
, float_mask
;
1439 mips_extra_func_info_t proc_desc
;
1441 CORE_ADDR
*saved_regs
;
1442 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1444 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1446 saved_regs
= frame_saved_regs_zalloc (fci
);
1448 /* If it is the frame for sigtramp, the saved registers are located
1449 in a sigcontext structure somewhere on the stack. If the stack
1450 layout for sigtramp changes we might have to change these
1451 constants and the companion fixup_sigtramp in mdebugread.c */
1452 #ifndef SIGFRAME_BASE
1453 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1454 above the sigtramp frame. */
1455 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1456 /* FIXME! Are these correct?? */
1457 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1458 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1459 #define SIGFRAME_FPREGSAVE_OFF \
1460 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1462 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1464 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1466 CORE_ADDR reg_position
=
1467 (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
+
1468 ireg
* mips_regsize (current_gdbarch
));
1469 set_reg_offset (saved_regs
, ireg
, reg_position
);
1471 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1473 CORE_ADDR reg_position
= (get_frame_base (fci
)
1474 + SIGFRAME_FPREGSAVE_OFF
1475 + ireg
* mips_regsize (current_gdbarch
));
1476 set_reg_offset (saved_regs
,
1477 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1481 set_reg_offset (saved_regs
, PC_REGNUM
,
1482 get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1483 /* SP_REGNUM, contains the value and not the address. */
1484 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1488 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1489 if (proc_desc
== NULL
)
1490 /* I'm not sure how/whether this can happen. Normally when we
1491 can't find a proc_desc, we "synthesize" one using
1492 heuristic_proc_desc and set the saved_regs right away. */
1495 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1496 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1497 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1499 if ( /* In any frame other than the innermost or a frame interrupted
1500 by a signal, we assume that all registers have been saved.
1501 This assumes that all register saves in a function happen
1502 before the first function call. */
1503 (get_next_frame (fci
) == NULL
1504 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1505 /* In a dummy frame we know exactly where things are saved. */
1506 && !PROC_DESC_IS_DUMMY (proc_desc
)
1507 /* Don't bother unless we are inside a function prologue.
1508 Outside the prologue, we know where everything is. */
1509 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1510 /* Not sure exactly what kernel_trap means, but if it means the
1511 kernel saves the registers without a prologue doing it, we
1512 better not examine the prologue to see whether registers
1513 have been saved yet. */
1516 /* We need to figure out whether the registers that the
1517 proc_desc claims are saved have been saved yet. */
1521 /* Bitmasks; set if we have found a save for the register. */
1522 unsigned long gen_save_found
= 0;
1523 unsigned long float_save_found
= 0;
1526 /* If the address is odd, assume this is MIPS16 code. */
1527 addr
= PROC_LOW_ADDR (proc_desc
);
1528 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1530 /* Scan through this function's instructions preceding the
1531 current PC, and look for those that save registers. */
1532 while (addr
< get_frame_pc (fci
))
1534 inst
= mips_fetch_instruction (addr
);
1535 if (pc_is_mips16 (addr
))
1536 mips16_decode_reg_save (inst
, &gen_save_found
);
1538 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1541 gen_mask
= gen_save_found
;
1542 float_mask
= float_save_found
;
1545 /* Fill in the offsets for the registers which gen_mask says were
1548 CORE_ADDR reg_position
= (get_frame_base (fci
)
1549 + PROC_REG_OFFSET (proc_desc
));
1550 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1551 if (gen_mask
& 0x80000000)
1553 set_reg_offset (saved_regs
, ireg
, reg_position
);
1554 reg_position
-= mips_saved_regsize (tdep
);
1558 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1559 order of that normally used by gcc. Therefore, we have to fetch
1560 the first instruction of the function, and if it's an entry
1561 instruction that saves $s0 or $s1, correct their saved addresses. */
1562 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1564 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1565 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1569 int sreg_count
= (inst
>> 6) & 3;
1571 /* Check if the ra register was pushed on the stack. */
1572 CORE_ADDR reg_position
= (get_frame_base (fci
)
1573 + PROC_REG_OFFSET (proc_desc
));
1575 reg_position
-= mips_saved_regsize (tdep
);
1577 /* Check if the s0 and s1 registers were pushed on the
1579 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1581 set_reg_offset (saved_regs
, reg
, reg_position
);
1582 reg_position
-= mips_saved_regsize (tdep
);
1587 /* Fill in the offsets for the registers which float_mask says were
1590 CORE_ADDR reg_position
= (get_frame_base (fci
)
1591 + PROC_FREG_OFFSET (proc_desc
));
1593 /* Fill in the offsets for the float registers which float_mask
1595 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1596 if (float_mask
& 0x80000000)
1598 if (mips_saved_regsize (tdep
) == 4
1599 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1601 /* On a big endian 32 bit ABI, floating point registers
1602 are paired to form doubles such that the most
1603 significant part is in $f[N+1] and the least
1604 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1605 registers are also spilled as a pair and stored as a
1608 When little-endian the least significant part is
1609 stored first leading to the memory order $f[N] and
1612 Unfortunately, when big-endian the most significant
1613 part of the double is stored first, and the least
1614 significant is stored second. This leads to the
1615 registers being ordered in memory as firt $f[N+1] and
1618 For the big-endian case make certain that the
1619 addresses point at the correct (swapped) locations
1620 $f[N] and $f[N+1] pair (keep in mind that
1621 reg_position is decremented each time through the
1624 set_reg_offset (saved_regs
,
1625 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1626 reg_position
- mips_saved_regsize (tdep
));
1628 set_reg_offset (saved_regs
,
1629 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1630 reg_position
+ mips_saved_regsize (tdep
));
1633 set_reg_offset (saved_regs
,
1634 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1636 reg_position
-= mips_saved_regsize (tdep
);
1639 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1642 /* SP_REGNUM, contains the value and not the address. */
1643 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1647 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1649 /* Always a pseudo. */
1650 gdb_assert (regno
>= NUM_REGS
);
1654 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1657 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1658 /* The SP_REGNUM is special, its value is stored in saved_regs.
1659 In fact, it is so special that it can even only be fetched
1660 using a raw register number! Once this code as been converted
1661 to frame-unwind the problem goes away. */
1662 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1664 return frame_unwind_register_signed (fi
, regno
);
1668 /* mips_addr_bits_remove - remove useless address bits */
1671 mips_addr_bits_remove (CORE_ADDR addr
)
1673 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1674 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1675 /* This hack is a work-around for existing boards using PMON, the
1676 simulator, and any other 64-bit targets that doesn't have true
1677 64-bit addressing. On these targets, the upper 32 bits of
1678 addresses are ignored by the hardware. Thus, the PC or SP are
1679 likely to have been sign extended to all 1s by instruction
1680 sequences that load 32-bit addresses. For example, a typical
1681 piece of code that loads an address is this:
1683 lui $r2, <upper 16 bits>
1684 ori $r2, <lower 16 bits>
1686 But the lui sign-extends the value such that the upper 32 bits
1687 may be all 1s. The workaround is simply to mask off these
1688 bits. In the future, gcc may be changed to support true 64-bit
1689 addressing, and this masking will have to be disabled. */
1690 return addr
&= 0xffffffffUL
;
1695 /* mips_software_single_step() is called just before we want to resume
1696 the inferior, if we want to single-step it but there is no hardware
1697 or kernel single-step support (MIPS on GNU/Linux for example). We find
1698 the target of the coming instruction and breakpoint it.
1700 single_step is also called just after the inferior stops. If we had
1701 set up a simulated single-step, we undo our damage. */
1704 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1706 static CORE_ADDR next_pc
;
1707 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1708 static binsn_quantum break_mem
;
1711 if (insert_breakpoints_p
)
1713 pc
= read_register (PC_REGNUM
);
1714 next_pc
= mips_next_pc (pc
);
1716 target_insert_breakpoint (next_pc
, break_mem
);
1719 target_remove_breakpoint (next_pc
, break_mem
);
1723 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1728 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1729 : get_next_frame (prev
)
1730 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
)) : read_pc ());
1731 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1732 return tmp
? tmp
: pc
;
1737 mips_frame_saved_pc (struct frame_info
*frame
)
1740 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1742 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1744 /* Always unwind the cooked PC register value. */
1745 saved_pc
= frame_unwind_register_signed (frame
, NUM_REGS
+ PC_REGNUM
);
1749 mips_extra_func_info_t proc_desc
1750 = get_frame_extra_info (frame
)->proc_desc
;
1751 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1752 saved_pc
= read_memory_integer ((get_frame_base (frame
)
1753 - mips_saved_regsize (tdep
)),
1754 mips_saved_regsize (tdep
));
1757 /* We have to get the saved pc from the sigcontext if it is
1758 a signal handler frame. */
1759 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1760 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1761 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1764 return ADDR_BITS_REMOVE (saved_pc
);
1767 static struct mips_extra_func_info temp_proc_desc
;
1769 /* This hack will go away once the get_prev_frame() code has been
1770 modified to set the frame's type first. That is BEFORE init extra
1771 frame info et.al. is called. This is because it will become
1772 possible to skip the init extra info call for sigtramp and dummy
1774 static CORE_ADDR
*temp_saved_regs
;
1776 /* Set a register's saved stack address in temp_saved_regs. If an
1777 address has already been set for this register, do nothing; this
1778 way we will only recognize the first save of a given register in a
1781 For simplicity, save the address in both [0 .. NUM_REGS) and
1782 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1783 is used as it is only second range (the ABI instead of ISA
1784 registers) that comes into play when finding saved registers in a
1788 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1790 if (saved_regs
[regno
] == 0)
1792 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1793 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1798 /* Test whether the PC points to the return instruction at the
1799 end of a function. */
1802 mips_about_to_return (CORE_ADDR pc
)
1804 if (pc_is_mips16 (pc
))
1805 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1806 generates a "jr $ra"; other times it generates code to load
1807 the return address from the stack to an accessible register (such
1808 as $a3), then a "jr" using that register. This second case
1809 is almost impossible to distinguish from an indirect jump
1810 used for switch statements, so we don't even try. */
1811 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1813 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1817 /* This fencepost looks highly suspicious to me. Removing it also
1818 seems suspicious as it could affect remote debugging across serial
1822 heuristic_proc_start (CORE_ADDR pc
)
1829 pc
= ADDR_BITS_REMOVE (pc
);
1831 fence
= start_pc
- heuristic_fence_post
;
1835 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
1836 fence
= VM_MIN_ADDRESS
;
1838 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1840 /* search back for previous return */
1841 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1842 if (start_pc
< fence
)
1844 /* It's not clear to me why we reach this point when
1845 stop_soon, but with this test, at least we
1846 don't print out warnings for every child forked (eg, on
1847 decstation). 22apr93 rich@cygnus.com. */
1848 if (stop_soon
== NO_STOP_QUIETLY
)
1850 static int blurb_printed
= 0;
1853 ("Warning: GDB can't find the start of the function at 0x%s.",
1858 /* This actually happens frequently in embedded
1859 development, when you first connect to a board
1860 and your stack pointer and pc are nowhere in
1861 particular. This message needs to give people
1862 in that situation enough information to
1863 determine that it's no big deal. */
1864 printf_filtered ("\n\
1865 GDB is unable to find the start of the function at 0x%s\n\
1866 and thus can't determine the size of that function's stack frame.\n\
1867 This means that GDB may be unable to access that stack frame, or\n\
1868 the frames below it.\n\
1869 This problem is most likely caused by an invalid program counter or\n\
1871 However, if you think GDB should simply search farther back\n\
1872 from 0x%s for code which looks like the beginning of a\n\
1873 function, you can increase the range of the search using the `set\n\
1874 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
1881 else if (pc_is_mips16 (start_pc
))
1883 unsigned short inst
;
1885 /* On MIPS16, any one of the following is likely to be the
1886 start of a function:
1890 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1891 inst
= mips_fetch_instruction (start_pc
);
1892 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1893 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1894 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1895 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1897 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1898 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1903 else if (mips_about_to_return (start_pc
))
1905 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1912 /* Fetch the immediate value from a MIPS16 instruction.
1913 If the previous instruction was an EXTEND, use it to extend
1914 the upper bits of the immediate value. This is a helper function
1915 for mips16_heuristic_proc_desc. */
1918 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1919 unsigned short inst
, /* current instruction */
1920 int nbits
, /* number of bits in imm field */
1921 int scale
, /* scale factor to be applied to imm */
1922 int is_signed
) /* is the imm field signed? */
1926 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1928 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1929 if (offset
& 0x8000) /* check for negative extend */
1930 offset
= 0 - (0x10000 - (offset
& 0xffff));
1931 return offset
| (inst
& 0x1f);
1935 int max_imm
= 1 << nbits
;
1936 int mask
= max_imm
- 1;
1937 int sign_bit
= max_imm
>> 1;
1939 offset
= inst
& mask
;
1940 if (is_signed
&& (offset
& sign_bit
))
1941 offset
= 0 - (max_imm
- offset
);
1942 return offset
* scale
;
1947 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1948 stream from start_pc to limit_pc. */
1951 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1952 struct frame_info
*next_frame
, CORE_ADDR sp
)
1955 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1956 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1957 unsigned inst
= 0; /* current instruction */
1958 unsigned entry_inst
= 0; /* the entry instruction */
1960 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1962 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1963 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1965 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1967 /* Save the previous instruction. If it's an EXTEND, we'll extract
1968 the immediate offset extension from it in mips16_get_imm. */
1971 /* Fetch and decode the instruction. */
1972 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1973 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1974 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1976 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1977 if (offset
< 0) /* negative stack adjustment? */
1978 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1980 /* Exit loop if a positive stack adjustment is found, which
1981 usually means that the stack cleanup code in the function
1982 epilogue is reached. */
1985 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1987 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1988 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1989 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1990 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
1992 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1994 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1995 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1996 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1997 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
1999 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2001 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2002 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2003 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2005 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2007 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2008 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2009 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2011 else if (inst
== 0x673d) /* move $s1, $sp */
2014 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2016 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2018 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2019 frame_addr
= sp
+ offset
;
2020 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2021 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2023 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2025 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2026 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2027 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2028 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2030 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2032 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2033 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2034 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2035 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2037 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2038 entry_inst
= inst
; /* save for later processing */
2039 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2040 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2043 /* The entry instruction is typically the first instruction in a function,
2044 and it stores registers at offsets relative to the value of the old SP
2045 (before the prologue). But the value of the sp parameter to this
2046 function is the new SP (after the prologue has been executed). So we
2047 can't calculate those offsets until we've seen the entire prologue,
2048 and can calculate what the old SP must have been. */
2049 if (entry_inst
!= 0)
2051 int areg_count
= (entry_inst
>> 8) & 7;
2052 int sreg_count
= (entry_inst
>> 6) & 3;
2054 /* The entry instruction always subtracts 32 from the SP. */
2055 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2057 /* Now we can calculate what the SP must have been at the
2058 start of the function prologue. */
2059 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2061 /* Check if a0-a3 were saved in the caller's argument save area. */
2062 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2064 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2065 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2066 offset
+= mips_saved_regsize (tdep
);
2069 /* Check if the ra register was pushed on the stack. */
2071 if (entry_inst
& 0x20)
2073 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2074 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2075 offset
-= mips_saved_regsize (tdep
);
2078 /* Check if the s0 and s1 registers were pushed on the stack. */
2079 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2081 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2082 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2083 offset
-= mips_saved_regsize (tdep
);
2089 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2090 struct frame_info
*next_frame
, CORE_ADDR sp
)
2093 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2095 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2096 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2097 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2098 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2099 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2101 unsigned long inst
, high_word
, low_word
;
2104 /* Fetch the instruction. */
2105 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2107 /* Save some code by pre-extracting some useful fields. */
2108 high_word
= (inst
>> 16) & 0xffff;
2109 low_word
= inst
& 0xffff;
2110 reg
= high_word
& 0x1f;
2112 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2113 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2114 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2116 if (low_word
& 0x8000) /* negative stack adjustment? */
2117 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2119 /* Exit loop if a positive stack adjustment is found, which
2120 usually means that the stack cleanup code in the function
2121 epilogue is reached. */
2124 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2126 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2127 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2129 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2131 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2132 but the register size used is only 32 bits. Make the address
2133 for the saved register point to the lower 32 bits. */
2134 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2135 set_reg_offset (temp_saved_regs
, reg
,
2136 sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2138 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2140 /* Old gcc frame, r30 is virtual frame pointer. */
2141 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2142 frame_addr
= sp
+ low_word
;
2143 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2145 unsigned alloca_adjust
;
2146 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2147 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2148 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2149 if (alloca_adjust
> 0)
2151 /* FP > SP + frame_size. This may be because
2152 * of an alloca or somethings similar.
2153 * Fix sp to "pre-alloca" value, and try again.
2155 sp
+= alloca_adjust
;
2160 /* move $30,$sp. With different versions of gas this will be either
2161 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2162 Accept any one of these. */
2163 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2165 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2166 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2168 unsigned alloca_adjust
;
2169 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2170 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2171 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2172 if (alloca_adjust
> 0)
2174 /* FP > SP + frame_size. This may be because
2175 * of an alloca or somethings similar.
2176 * Fix sp to "pre-alloca" value, and try again.
2178 sp
+= alloca_adjust
;
2183 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2185 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2186 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2191 static mips_extra_func_info_t
2192 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2193 struct frame_info
*next_frame
, int cur_frame
)
2198 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2204 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2205 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2206 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2207 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2208 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2209 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2211 if (start_pc
+ 200 < limit_pc
)
2212 limit_pc
= start_pc
+ 200;
2213 if (pc_is_mips16 (start_pc
))
2214 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2216 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2217 return &temp_proc_desc
;
2220 struct mips_objfile_private
2226 /* Global used to communicate between non_heuristic_proc_desc and
2227 compare_pdr_entries within qsort (). */
2228 static bfd
*the_bfd
;
2231 compare_pdr_entries (const void *a
, const void *b
)
2233 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2234 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2238 else if (lhs
== rhs
)
2244 static mips_extra_func_info_t
2245 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2247 CORE_ADDR startaddr
;
2248 mips_extra_func_info_t proc_desc
;
2249 struct block
*b
= block_for_pc (pc
);
2251 struct obj_section
*sec
;
2252 struct mips_objfile_private
*priv
;
2254 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2257 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2259 *addrptr
= startaddr
;
2263 sec
= find_pc_section (pc
);
2266 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2268 /* Search the ".pdr" section generated by GAS. This includes most of
2269 the information normally found in ECOFF PDRs. */
2271 the_bfd
= sec
->objfile
->obfd
;
2273 && (the_bfd
->format
== bfd_object
2274 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2275 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2277 /* Right now GAS only outputs the address as a four-byte sequence.
2278 This means that we should not bother with this method on 64-bit
2279 targets (until that is fixed). */
2281 priv
= obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2282 sizeof (struct mips_objfile_private
));
2284 sec
->objfile
->obj_private
= priv
;
2286 else if (priv
== NULL
)
2290 priv
= obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2291 sizeof (struct mips_objfile_private
));
2293 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2296 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2297 priv
->contents
= obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2299 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2300 priv
->contents
, 0, priv
->size
);
2302 /* In general, the .pdr section is sorted. However, in the
2303 presence of multiple code sections (and other corner cases)
2304 it can become unsorted. Sort it so that we can use a faster
2306 qsort (priv
->contents
, priv
->size
/ 32, 32,
2307 compare_pdr_entries
);
2312 sec
->objfile
->obj_private
= priv
;
2316 if (priv
->size
!= 0)
2322 high
= priv
->size
/ 32;
2328 mid
= (low
+ high
) / 2;
2330 ptr
= priv
->contents
+ mid
* 32;
2331 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2332 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2333 SECT_OFF_TEXT (sec
->objfile
));
2334 if (pdr_pc
== startaddr
)
2336 if (pdr_pc
> startaddr
)
2341 while (low
!= high
);
2345 struct symbol
*sym
= find_pc_function (pc
);
2347 /* Fill in what we need of the proc_desc. */
2348 proc_desc
= (mips_extra_func_info_t
)
2349 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2350 sizeof (struct mips_extra_func_info
));
2351 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2353 /* Only used for dummy frames. */
2354 PROC_HIGH_ADDR (proc_desc
) = 0;
2356 PROC_FRAME_OFFSET (proc_desc
)
2357 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2358 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2360 PROC_FRAME_ADJUST (proc_desc
) = 0;
2361 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2363 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2365 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2367 PROC_FREG_OFFSET (proc_desc
)
2368 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2369 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2371 proc_desc
->pdr
.isym
= (long) sym
;
2381 if (startaddr
> BLOCK_START (b
))
2383 /* This is the "pathological" case referred to in a comment in
2384 print_frame_info. It might be better to move this check into
2389 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2391 /* If we never found a PDR for this function in symbol reading, then
2392 examine prologues to find the information. */
2395 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2396 if (PROC_FRAME_REG (proc_desc
) == -1)
2406 static mips_extra_func_info_t
2407 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2409 mips_extra_func_info_t proc_desc
;
2410 CORE_ADDR startaddr
= 0;
2412 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2416 /* IF this is the topmost frame AND
2417 * (this proc does not have debugging information OR
2418 * the PC is in the procedure prologue)
2419 * THEN create a "heuristic" proc_desc (by analyzing
2420 * the actual code) to replace the "official" proc_desc.
2422 if (next_frame
== NULL
)
2424 struct symtab_and_line val
;
2425 struct symbol
*proc_symbol
=
2426 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2430 val
= find_pc_line (BLOCK_START
2431 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
2432 val
.pc
= val
.end
? val
.end
: pc
;
2434 if (!proc_symbol
|| pc
< val
.pc
)
2436 mips_extra_func_info_t found_heuristic
=
2437 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2438 pc
, next_frame
, cur_frame
);
2439 if (found_heuristic
)
2440 proc_desc
= found_heuristic
;
2446 /* Is linked_proc_desc_table really necessary? It only seems to be used
2447 by procedure call dummys. However, the procedures being called ought
2448 to have their own proc_descs, and even if they don't,
2449 heuristic_proc_desc knows how to create them! */
2451 struct linked_proc_info
*link
;
2453 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2454 if (PROC_LOW_ADDR (&link
->info
) <= pc
2455 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2459 startaddr
= heuristic_proc_start (pc
);
2461 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2467 get_frame_pointer (struct frame_info
*frame
, mips_extra_func_info_t proc_desc
)
2469 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2470 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2473 static mips_extra_func_info_t cached_proc_desc
;
2476 mips_frame_chain (struct frame_info
*frame
)
2478 mips_extra_func_info_t proc_desc
;
2480 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2482 /* Check if the PC is inside a call stub. If it is, fetch the
2483 PC of the caller of that stub. */
2484 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2487 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2489 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2490 is well, frame->frame the bottom of the current frame will
2491 contain that value. */
2492 return get_frame_base (frame
);
2495 /* Look up the procedure descriptor for this PC. */
2496 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2500 cached_proc_desc
= proc_desc
;
2502 /* If no frame pointer and frame size is zero, we must be at end
2503 of stack (or otherwise hosed). If we don't check frame size,
2504 we loop forever if we see a zero size frame. */
2505 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2506 && PROC_FRAME_OFFSET (proc_desc
) == 0
2507 /* The previous frame from a sigtramp frame might be frameless
2508 and have frame size zero. */
2509 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2510 /* For a generic dummy frame, let get_frame_pointer() unwind a
2511 register value saved as part of the dummy frame call. */
2512 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2515 return get_frame_pointer (frame
, proc_desc
);
2519 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2522 mips_extra_func_info_t proc_desc
;
2524 if (get_frame_type (fci
) == DUMMY_FRAME
)
2527 /* Use proc_desc calculated in frame_chain. When there is no
2528 next frame, i.e, get_next_frame (fci) == NULL, we call
2529 find_proc_desc () to calculate it, passing an explicit
2530 NULL as the frame parameter. */
2532 get_next_frame (fci
)
2534 : find_proc_desc (get_frame_pc (fci
),
2535 NULL
/* i.e, get_next_frame (fci) */ ,
2538 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2540 get_frame_extra_info (fci
)->proc_desc
=
2541 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2544 /* Fixup frame-pointer - only needed for top frame */
2545 /* This may not be quite right, if proc has a real frame register.
2546 Get the value of the frame relative sp, procedure might have been
2547 interrupted by a signal at it's very start. */
2548 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2549 && !PROC_DESC_IS_DUMMY (proc_desc
))
2550 deprecated_update_frame_base_hack (fci
,
2551 read_next_frame_reg (get_next_frame
2555 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2556 /* Do not ``fix'' fci->frame. It will have the value of the
2557 generic dummy frame's top-of-stack (since the draft
2558 fci->frame is obtained by returning the unwound stack
2559 pointer) and that is what we want. That way the fci->frame
2560 value will match the top-of-stack value that was saved as
2561 part of the dummy frames data. */
2564 deprecated_update_frame_base_hack (fci
,
2565 get_frame_pointer (get_next_frame
2569 if (proc_desc
== &temp_proc_desc
)
2573 /* Do not set the saved registers for a sigtramp frame,
2574 mips_find_saved_registers will do that for us. We can't
2575 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2577 /* FIXME: cagney/2002-11-18: This problem will go away once
2578 frame.c:get_prev_frame() is modified to set the frame's
2579 type before calling functions like this. */
2580 find_pc_partial_function (get_frame_pc (fci
), &name
,
2581 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2582 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2584 frame_saved_regs_zalloc (fci
);
2585 /* Set value of previous frame's stack pointer.
2586 Remember that saved_regs[SP_REGNUM] is special in
2587 that it contains the value of the stack pointer
2588 register. The other saved_regs values are addresses
2589 (in the inferior) at which a given register's value
2591 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2592 get_frame_base (fci
));
2593 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2594 temp_saved_regs
[RA_REGNUM
]);
2595 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2596 SIZEOF_FRAME_SAVED_REGS
);
2600 /* hack: if argument regs are saved, guess these contain args */
2601 /* assume we can't tell how many args for now */
2602 get_frame_extra_info (fci
)->num_args
= -1;
2603 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2605 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2607 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2614 /* MIPS stack frames are almost impenetrable. When execution stops,
2615 we basically have to look at symbol information for the function
2616 that we stopped in, which tells us *which* register (if any) is
2617 the base of the frame pointer, and what offset from that register
2618 the frame itself is at.
2620 This presents a problem when trying to examine a stack in memory
2621 (that isn't executing at the moment), using the "frame" command. We
2622 don't have a PC, nor do we have any registers except SP.
2624 This routine takes two arguments, SP and PC, and tries to make the
2625 cached frames look as if these two arguments defined a frame on the
2626 cache. This allows the rest of info frame to extract the important
2627 arguments without difficulty. */
2630 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2633 error ("MIPS frame specifications require two arguments: sp and pc");
2635 return create_new_frame (argv
[0], argv
[1]);
2638 /* According to the current ABI, should the type be passed in a
2639 floating-point register (assuming that there is space)? When there
2640 is no FPU, FP are not even considered as possibile candidates for
2641 FP registers and, consequently this returns false - forces FP
2642 arguments into integer registers. */
2645 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2647 return ((typecode
== TYPE_CODE_FLT
2649 && (typecode
== TYPE_CODE_STRUCT
2650 || typecode
== TYPE_CODE_UNION
)
2651 && TYPE_NFIELDS (arg_type
) == 1
2652 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2653 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2656 /* On o32, argument passing in GPRs depends on the alignment of the type being
2657 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2660 mips_type_needs_double_align (struct type
*type
)
2662 enum type_code typecode
= TYPE_CODE (type
);
2664 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2666 else if (typecode
== TYPE_CODE_STRUCT
)
2668 if (TYPE_NFIELDS (type
) < 1)
2670 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2672 else if (typecode
== TYPE_CODE_UNION
)
2676 n
= TYPE_NFIELDS (type
);
2677 for (i
= 0; i
< n
; i
++)
2678 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2685 /* Adjust the address downward (direction of stack growth) so that it
2686 is correctly aligned for a new stack frame. */
2688 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2690 return align_down (addr
, 16);
2693 /* Determine how a return value is stored within the MIPS register
2694 file, given the return type `valtype'. */
2696 struct return_value_word
2705 return_value_location (struct type
*valtype
,
2706 struct return_value_word
*hi
,
2707 struct return_value_word
*lo
)
2709 int len
= TYPE_LENGTH (valtype
);
2710 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2712 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2713 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2714 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2716 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2718 /* We need to break a 64bit float in two 32 bit halves and
2719 spread them across a floating-point register pair. */
2720 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2721 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
2722 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2723 && register_size (current_gdbarch
,
2724 mips_regnum (current_gdbarch
)->
2725 fp0
) == 8) ? 4 : 0);
2726 hi
->reg_offset
= lo
->reg_offset
;
2727 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
2728 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
2734 /* The floating point value fits in a single floating-point
2736 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2737 && register_size (current_gdbarch
,
2738 mips_regnum (current_gdbarch
)->
2740 && len
== 4) ? 4 : 0);
2741 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
2752 /* Locate a result possibly spread across two registers. */
2754 lo
->reg
= regnum
+ 0;
2755 hi
->reg
= regnum
+ 1;
2756 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2757 && len
< mips_saved_regsize (tdep
))
2759 /* "un-left-justify" the value in the low register */
2760 lo
->reg_offset
= mips_saved_regsize (tdep
) - len
;
2765 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_saved_regsize (tdep
) /* odd-size structs */
2766 && len
< mips_saved_regsize (tdep
) * 2
2767 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2768 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2770 /* "un-left-justify" the value spread across two registers. */
2771 lo
->reg_offset
= 2 * mips_saved_regsize (tdep
) - len
;
2772 lo
->len
= mips_saved_regsize (tdep
) - lo
->reg_offset
;
2774 hi
->len
= len
- lo
->len
;
2778 /* Only perform a partial copy of the second register. */
2781 if (len
> mips_saved_regsize (tdep
))
2783 lo
->len
= mips_saved_regsize (tdep
);
2784 hi
->len
= len
- mips_saved_regsize (tdep
);
2792 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2793 && register_size (current_gdbarch
, regnum
) == 8
2794 && mips_saved_regsize (tdep
) == 4)
2796 /* Account for the fact that only the least-signficant part
2797 of the register is being used */
2798 lo
->reg_offset
+= 4;
2799 hi
->reg_offset
+= 4;
2802 hi
->buf_offset
= lo
->len
;
2806 /* Should call_function allocate stack space for a struct return? */
2809 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
2811 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2812 return (TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
));
2815 /* Should call_function pass struct by reference?
2816 For each architecture, structs are passed either by
2817 value or by reference, depending on their size. */
2820 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2822 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
2823 int len
= TYPE_LENGTH (check_typedef (type
));
2824 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2826 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2827 return (len
> mips_saved_regsize (tdep
));
2833 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2834 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2835 int nargs
, struct value
**args
, CORE_ADDR sp
,
2836 int struct_return
, CORE_ADDR struct_addr
)
2842 int stack_offset
= 0;
2843 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2845 /* For shared libraries, "t9" needs to point at the function
2847 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2849 /* Set the return address register to point to the entry point of
2850 the program, where a breakpoint lies in wait. */
2851 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2853 /* First ensure that the stack and structure return address (if any)
2854 are properly aligned. The stack has to be at least 64-bit
2855 aligned even on 32-bit machines, because doubles must be 64-bit
2856 aligned. For n32 and n64, stack frames need to be 128-bit
2857 aligned, so we round to this widest known alignment. */
2859 sp
= align_down (sp
, 16);
2860 struct_addr
= align_down (struct_addr
, 16);
2862 /* Now make space on the stack for the args. We allocate more
2863 than necessary for EABI, because the first few arguments are
2864 passed in registers, but that's OK. */
2865 for (argnum
= 0; argnum
< nargs
; argnum
++)
2866 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2867 mips_stack_argsize (tdep
));
2868 sp
-= align_up (len
, 16);
2871 fprintf_unfiltered (gdb_stdlog
,
2872 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2873 paddr_nz (sp
), (long) align_up (len
, 16));
2875 /* Initialize the integer and float register pointers. */
2877 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2879 /* The struct_return pointer occupies the first parameter-passing reg. */
2883 fprintf_unfiltered (gdb_stdlog
,
2884 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2885 argreg
, paddr_nz (struct_addr
));
2886 write_register (argreg
++, struct_addr
);
2889 /* Now load as many as possible of the first arguments into
2890 registers, and push the rest onto the stack. Loop thru args
2891 from first to last. */
2892 for (argnum
= 0; argnum
< nargs
; argnum
++)
2895 char valbuf
[MAX_REGISTER_SIZE
];
2896 struct value
*arg
= args
[argnum
];
2897 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2898 int len
= TYPE_LENGTH (arg_type
);
2899 enum type_code typecode
= TYPE_CODE (arg_type
);
2902 fprintf_unfiltered (gdb_stdlog
,
2903 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2904 argnum
+ 1, len
, (int) typecode
);
2906 /* The EABI passes structures that do not fit in a register by
2908 if (len
> mips_saved_regsize (tdep
)
2909 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2911 store_unsigned_integer (valbuf
, mips_saved_regsize (tdep
),
2912 VALUE_ADDRESS (arg
));
2913 typecode
= TYPE_CODE_PTR
;
2914 len
= mips_saved_regsize (tdep
);
2917 fprintf_unfiltered (gdb_stdlog
, " push");
2920 val
= (char *) VALUE_CONTENTS (arg
);
2922 /* 32-bit ABIs always start floating point arguments in an
2923 even-numbered floating point register. Round the FP register
2924 up before the check to see if there are any FP registers
2925 left. Non MIPS_EABI targets also pass the FP in the integer
2926 registers so also round up normal registers. */
2927 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
2929 if ((float_argreg
& 1))
2933 /* Floating point arguments passed in registers have to be
2934 treated specially. On 32-bit architectures, doubles
2935 are passed in register pairs; the even register gets
2936 the low word, and the odd register gets the high word.
2937 On non-EABI processors, the first two floating point arguments are
2938 also copied to general registers, because MIPS16 functions
2939 don't use float registers for arguments. This duplication of
2940 arguments in general registers can't hurt non-MIPS16 functions
2941 because those registers are normally skipped. */
2942 /* MIPS_EABI squeezes a struct that contains a single floating
2943 point value into an FP register instead of pushing it onto the
2945 if (fp_register_arg_p (typecode
, arg_type
)
2946 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2948 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2950 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2951 unsigned long regval
;
2953 /* Write the low word of the double to the even register(s). */
2954 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2956 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2957 float_argreg
, phex (regval
, 4));
2958 write_register (float_argreg
++, regval
);
2960 /* Write the high word of the double to the odd register(s). */
2961 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2963 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2964 float_argreg
, phex (regval
, 4));
2965 write_register (float_argreg
++, regval
);
2969 /* This is a floating point value that fits entirely
2970 in a single register. */
2971 /* On 32 bit ABI's the float_argreg is further adjusted
2972 above to ensure that it is even register aligned. */
2973 LONGEST regval
= extract_unsigned_integer (val
, len
);
2975 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2976 float_argreg
, phex (regval
, len
));
2977 write_register (float_argreg
++, regval
);
2982 /* Copy the argument to general registers or the stack in
2983 register-sized pieces. Large arguments are split between
2984 registers and stack. */
2985 /* Note: structs whose size is not a multiple of
2986 mips_regsize() are treated specially: Irix cc passes them
2987 in registers where gcc sometimes puts them on the stack.
2988 For maximum compatibility, we will put them in both
2990 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
2991 && (len
% mips_saved_regsize (tdep
) != 0));
2993 /* Note: Floating-point values that didn't fit into an FP
2994 register are only written to memory. */
2997 /* Remember if the argument was written to the stack. */
2998 int stack_used_p
= 0;
2999 int partial_len
= (len
< mips_saved_regsize (tdep
)
3000 ? len
: mips_saved_regsize (tdep
));
3003 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3006 /* Write this portion of the argument to the stack. */
3007 if (argreg
> MIPS_LAST_ARG_REGNUM
3009 || fp_register_arg_p (typecode
, arg_type
))
3011 /* Should shorter than int integer values be
3012 promoted to int before being stored? */
3013 int longword_offset
= 0;
3016 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3018 if (mips_stack_argsize (tdep
) == 8
3019 && (typecode
== TYPE_CODE_INT
3020 || typecode
== TYPE_CODE_PTR
3021 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3022 longword_offset
= mips_stack_argsize (tdep
) - len
;
3023 else if ((typecode
== TYPE_CODE_STRUCT
3024 || typecode
== TYPE_CODE_UNION
)
3025 && (TYPE_LENGTH (arg_type
)
3026 < mips_stack_argsize (tdep
)))
3027 longword_offset
= mips_stack_argsize (tdep
) - len
;
3032 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3033 paddr_nz (stack_offset
));
3034 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3035 paddr_nz (longword_offset
));
3038 addr
= sp
+ stack_offset
+ longword_offset
;
3043 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3045 for (i
= 0; i
< partial_len
; i
++)
3047 fprintf_unfiltered (gdb_stdlog
, "%02x",
3051 write_memory (addr
, val
, partial_len
);
3054 /* Note!!! This is NOT an else clause. Odd sized
3055 structs may go thru BOTH paths. Floating point
3056 arguments will not. */
3057 /* Write this portion of the argument to a general
3058 purpose register. */
3059 if (argreg
<= MIPS_LAST_ARG_REGNUM
3060 && !fp_register_arg_p (typecode
, arg_type
))
3063 extract_unsigned_integer (val
, partial_len
);
3066 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3069 mips_saved_regsize (tdep
)));
3070 write_register (argreg
, regval
);
3077 /* Compute the the offset into the stack at which we
3078 will copy the next parameter.
3080 In the new EABI (and the NABI32), the stack_offset
3081 only needs to be adjusted when it has been used. */
3084 stack_offset
+= align_up (partial_len
,
3085 mips_stack_argsize (tdep
));
3089 fprintf_unfiltered (gdb_stdlog
, "\n");
3092 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3094 /* Return adjusted stack pointer. */
3098 /* Given a return value in `regbuf' with a type `valtype', extract and
3099 copy its value into `valbuf'. */
3102 mips_eabi_extract_return_value (struct type
*valtype
,
3103 char regbuf
[], char *valbuf
)
3105 struct return_value_word lo
;
3106 struct return_value_word hi
;
3107 return_value_location (valtype
, &hi
, &lo
);
3109 memcpy (valbuf
+ lo
.buf_offset
,
3110 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3111 lo
.reg_offset
, lo
.len
);
3114 memcpy (valbuf
+ hi
.buf_offset
,
3115 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3116 hi
.reg_offset
, hi
.len
);
3119 /* Given a return value in `valbuf' with a type `valtype', write it's
3120 value into the appropriate register. */
3123 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3125 char raw_buffer
[MAX_REGISTER_SIZE
];
3126 struct return_value_word lo
;
3127 struct return_value_word hi
;
3128 return_value_location (valtype
, &hi
, &lo
);
3130 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3131 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3132 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3133 raw_buffer
, register_size (current_gdbarch
,
3138 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3139 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3140 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3142 register_size (current_gdbarch
,
3147 /* N32/N64 ABI stuff. */
3150 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3151 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3152 int nargs
, struct value
**args
, CORE_ADDR sp
,
3153 int struct_return
, CORE_ADDR struct_addr
)
3159 int stack_offset
= 0;
3160 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3162 /* For shared libraries, "t9" needs to point at the function
3164 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3166 /* Set the return address register to point to the entry point of
3167 the program, where a breakpoint lies in wait. */
3168 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3170 /* First ensure that the stack and structure return address (if any)
3171 are properly aligned. The stack has to be at least 64-bit
3172 aligned even on 32-bit machines, because doubles must be 64-bit
3173 aligned. For n32 and n64, stack frames need to be 128-bit
3174 aligned, so we round to this widest known alignment. */
3176 sp
= align_down (sp
, 16);
3177 struct_addr
= align_down (struct_addr
, 16);
3179 /* Now make space on the stack for the args. */
3180 for (argnum
= 0; argnum
< nargs
; argnum
++)
3181 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3182 mips_stack_argsize (tdep
));
3183 sp
-= align_up (len
, 16);
3186 fprintf_unfiltered (gdb_stdlog
,
3187 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3188 paddr_nz (sp
), (long) align_up (len
, 16));
3190 /* Initialize the integer and float register pointers. */
3192 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3194 /* The struct_return pointer occupies the first parameter-passing reg. */
3198 fprintf_unfiltered (gdb_stdlog
,
3199 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3200 argreg
, paddr_nz (struct_addr
));
3201 write_register (argreg
++, struct_addr
);
3204 /* Now load as many as possible of the first arguments into
3205 registers, and push the rest onto the stack. Loop thru args
3206 from first to last. */
3207 for (argnum
= 0; argnum
< nargs
; argnum
++)
3210 char valbuf
[MAX_REGISTER_SIZE
];
3211 struct value
*arg
= args
[argnum
];
3212 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3213 int len
= TYPE_LENGTH (arg_type
);
3214 enum type_code typecode
= TYPE_CODE (arg_type
);
3217 fprintf_unfiltered (gdb_stdlog
,
3218 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3219 argnum
+ 1, len
, (int) typecode
);
3221 val
= (char *) VALUE_CONTENTS (arg
);
3223 if (fp_register_arg_p (typecode
, arg_type
)
3224 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3226 /* This is a floating point value that fits entirely
3227 in a single register. */
3228 /* On 32 bit ABI's the float_argreg is further adjusted
3229 above to ensure that it is even register aligned. */
3230 LONGEST regval
= extract_unsigned_integer (val
, len
);
3232 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3233 float_argreg
, phex (regval
, len
));
3234 write_register (float_argreg
++, regval
);
3237 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3238 argreg
, phex (regval
, len
));
3239 write_register (argreg
, regval
);
3244 /* Copy the argument to general registers or the stack in
3245 register-sized pieces. Large arguments are split between
3246 registers and stack. */
3247 /* Note: structs whose size is not a multiple of
3248 mips_regsize() are treated specially: Irix cc passes them
3249 in registers where gcc sometimes puts them on the stack.
3250 For maximum compatibility, we will put them in both
3252 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3253 && (len
% mips_saved_regsize (tdep
) != 0));
3254 /* Note: Floating-point values that didn't fit into an FP
3255 register are only written to memory. */
3258 /* Rememer if the argument was written to the stack. */
3259 int stack_used_p
= 0;
3260 int partial_len
= (len
< mips_saved_regsize (tdep
)
3261 ? len
: mips_saved_regsize (tdep
));
3264 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3267 /* Write this portion of the argument to the stack. */
3268 if (argreg
> MIPS_LAST_ARG_REGNUM
3270 || fp_register_arg_p (typecode
, arg_type
))
3272 /* Should shorter than int integer values be
3273 promoted to int before being stored? */
3274 int longword_offset
= 0;
3277 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3279 if (mips_stack_argsize (tdep
) == 8
3280 && (typecode
== TYPE_CODE_INT
3281 || typecode
== TYPE_CODE_PTR
3282 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3283 longword_offset
= mips_stack_argsize (tdep
) - len
;
3288 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3289 paddr_nz (stack_offset
));
3290 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3291 paddr_nz (longword_offset
));
3294 addr
= sp
+ stack_offset
+ longword_offset
;
3299 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3301 for (i
= 0; i
< partial_len
; i
++)
3303 fprintf_unfiltered (gdb_stdlog
, "%02x",
3307 write_memory (addr
, val
, partial_len
);
3310 /* Note!!! This is NOT an else clause. Odd sized
3311 structs may go thru BOTH paths. Floating point
3312 arguments will not. */
3313 /* Write this portion of the argument to a general
3314 purpose register. */
3315 if (argreg
<= MIPS_LAST_ARG_REGNUM
3316 && !fp_register_arg_p (typecode
, arg_type
))
3319 extract_unsigned_integer (val
, partial_len
);
3321 /* A non-floating-point argument being passed in a
3322 general register. If a struct or union, and if
3323 the remaining length is smaller than the register
3324 size, we have to adjust the register value on
3327 It does not seem to be necessary to do the
3328 same for integral types.
3330 cagney/2001-07-23: gdb/179: Also, GCC, when
3331 outputting LE O32 with sizeof (struct) <
3332 mips_saved_regsize(), generates a left shift as
3333 part of storing the argument in a register a
3334 register (the left shift isn't generated when
3335 sizeof (struct) >= mips_saved_regsize()). Since
3336 it is quite possible that this is GCC
3337 contradicting the LE/O32 ABI, GDB has not been
3338 adjusted to accommodate this. Either someone
3339 needs to demonstrate that the LE/O32 ABI
3340 specifies such a left shift OR this new ABI gets
3341 identified as such and GDB gets tweaked
3344 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3345 && partial_len
< mips_saved_regsize (tdep
)
3346 && (typecode
== TYPE_CODE_STRUCT
||
3347 typecode
== TYPE_CODE_UNION
))
3348 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3352 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3355 mips_saved_regsize (tdep
)));
3356 write_register (argreg
, regval
);
3363 /* Compute the the offset into the stack at which we
3364 will copy the next parameter.
3366 In N32 (N64?), the stack_offset only needs to be
3367 adjusted when it has been used. */
3370 stack_offset
+= align_up (partial_len
,
3371 mips_stack_argsize (tdep
));
3375 fprintf_unfiltered (gdb_stdlog
, "\n");
3378 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3380 /* Return adjusted stack pointer. */
3384 static enum return_value_convention
3385 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3386 struct type
*type
, struct regcache
*regcache
,
3387 void *readbuf
, const void *writebuf
)
3389 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3390 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3391 || TYPE_CODE (type
) == TYPE_CODE_UNION
3392 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3393 || TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
))
3394 return RETURN_VALUE_STRUCT_CONVENTION
;
3395 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3396 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3398 /* A floating-point value belongs in the least significant part
3401 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3402 mips_xfer_register (regcache
,
3403 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3405 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3406 return RETURN_VALUE_REGISTER_CONVENTION
;
3408 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3409 && TYPE_NFIELDS (type
) <= 2
3410 && TYPE_NFIELDS (type
) >= 1
3411 && ((TYPE_NFIELDS (type
) == 1
3412 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3414 || (TYPE_NFIELDS (type
) == 2
3415 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3417 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3419 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3421 /* A struct that contains one or two floats. Each value is part
3422 in the least significant part of their floating point
3424 bfd_byte reg
[MAX_REGISTER_SIZE
];
3427 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3428 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3430 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3433 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3435 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3436 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3437 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3439 return RETURN_VALUE_REGISTER_CONVENTION
;
3441 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3442 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3444 /* A structure or union. Extract the left justified value,
3445 regardless of the byte order. I.e. DO NOT USE
3449 for (offset
= 0, regnum
= V0_REGNUM
;
3450 offset
< TYPE_LENGTH (type
);
3451 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3453 int xfer
= register_size (current_gdbarch
, regnum
);
3454 if (offset
+ xfer
> TYPE_LENGTH (type
))
3455 xfer
= TYPE_LENGTH (type
) - offset
;
3457 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3458 offset
, xfer
, regnum
);
3459 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3460 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3462 return RETURN_VALUE_REGISTER_CONVENTION
;
3466 /* A scalar extract each part but least-significant-byte
3470 for (offset
= 0, regnum
= V0_REGNUM
;
3471 offset
< TYPE_LENGTH (type
);
3472 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3474 int xfer
= register_size (current_gdbarch
, regnum
);
3476 if (offset
+ xfer
> TYPE_LENGTH (type
))
3477 xfer
= TYPE_LENGTH (type
) - offset
;
3479 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3480 offset
, xfer
, regnum
);
3481 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3482 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3484 return RETURN_VALUE_REGISTER_CONVENTION
;
3488 /* O32 ABI stuff. */
3491 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3492 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3493 int nargs
, struct value
**args
, CORE_ADDR sp
,
3494 int struct_return
, CORE_ADDR struct_addr
)
3500 int stack_offset
= 0;
3501 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3503 /* For shared libraries, "t9" needs to point at the function
3505 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3507 /* Set the return address register to point to the entry point of
3508 the program, where a breakpoint lies in wait. */
3509 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3511 /* First ensure that the stack and structure return address (if any)
3512 are properly aligned. The stack has to be at least 64-bit
3513 aligned even on 32-bit machines, because doubles must be 64-bit
3514 aligned. For n32 and n64, stack frames need to be 128-bit
3515 aligned, so we round to this widest known alignment. */
3517 sp
= align_down (sp
, 16);
3518 struct_addr
= align_down (struct_addr
, 16);
3520 /* Now make space on the stack for the args. */
3521 for (argnum
= 0; argnum
< nargs
; argnum
++)
3522 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3523 mips_stack_argsize (tdep
));
3524 sp
-= align_up (len
, 16);
3527 fprintf_unfiltered (gdb_stdlog
,
3528 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3529 paddr_nz (sp
), (long) align_up (len
, 16));
3531 /* Initialize the integer and float register pointers. */
3533 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3535 /* The struct_return pointer occupies the first parameter-passing reg. */
3539 fprintf_unfiltered (gdb_stdlog
,
3540 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3541 argreg
, paddr_nz (struct_addr
));
3542 write_register (argreg
++, struct_addr
);
3543 stack_offset
+= mips_stack_argsize (tdep
);
3546 /* Now load as many as possible of the first arguments into
3547 registers, and push the rest onto the stack. Loop thru args
3548 from first to last. */
3549 for (argnum
= 0; argnum
< nargs
; argnum
++)
3552 char valbuf
[MAX_REGISTER_SIZE
];
3553 struct value
*arg
= args
[argnum
];
3554 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3555 int len
= TYPE_LENGTH (arg_type
);
3556 enum type_code typecode
= TYPE_CODE (arg_type
);
3559 fprintf_unfiltered (gdb_stdlog
,
3560 "mips_o32_push_dummy_call: %d len=%d type=%d",
3561 argnum
+ 1, len
, (int) typecode
);
3563 val
= (char *) VALUE_CONTENTS (arg
);
3565 /* 32-bit ABIs always start floating point arguments in an
3566 even-numbered floating point register. Round the FP register
3567 up before the check to see if there are any FP registers
3568 left. O32/O64 targets also pass the FP in the integer
3569 registers so also round up normal registers. */
3570 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3572 if ((float_argreg
& 1))
3576 /* Floating point arguments passed in registers have to be
3577 treated specially. On 32-bit architectures, doubles
3578 are passed in register pairs; the even register gets
3579 the low word, and the odd register gets the high word.
3580 On O32/O64, the first two floating point arguments are
3581 also copied to general registers, because MIPS16 functions
3582 don't use float registers for arguments. This duplication of
3583 arguments in general registers can't hurt non-MIPS16 functions
3584 because those registers are normally skipped. */
3586 if (fp_register_arg_p (typecode
, arg_type
)
3587 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3589 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3591 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3592 unsigned long regval
;
3594 /* Write the low word of the double to the even register(s). */
3595 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3597 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3598 float_argreg
, phex (regval
, 4));
3599 write_register (float_argreg
++, regval
);
3601 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3602 argreg
, phex (regval
, 4));
3603 write_register (argreg
++, regval
);
3605 /* Write the high word of the double to the odd register(s). */
3606 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3608 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3609 float_argreg
, phex (regval
, 4));
3610 write_register (float_argreg
++, regval
);
3613 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3614 argreg
, phex (regval
, 4));
3615 write_register (argreg
++, regval
);
3619 /* This is a floating point value that fits entirely
3620 in a single register. */
3621 /* On 32 bit ABI's the float_argreg is further adjusted
3622 above to ensure that it is even register aligned. */
3623 LONGEST regval
= extract_unsigned_integer (val
, len
);
3625 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3626 float_argreg
, phex (regval
, len
));
3627 write_register (float_argreg
++, regval
);
3628 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3629 registers for each argument. The below is (my
3630 guess) to ensure that the corresponding integer
3631 register has reserved the same space. */
3633 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3634 argreg
, phex (regval
, len
));
3635 write_register (argreg
, regval
);
3636 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3638 /* Reserve space for the FP register. */
3639 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3643 /* Copy the argument to general registers or the stack in
3644 register-sized pieces. Large arguments are split between
3645 registers and stack. */
3646 /* Note: structs whose size is not a multiple of
3647 mips_regsize() are treated specially: Irix cc passes them
3648 in registers where gcc sometimes puts them on the stack.
3649 For maximum compatibility, we will put them in both
3651 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3652 && (len
% mips_saved_regsize (tdep
) != 0));
3653 /* Structures should be aligned to eight bytes (even arg registers)
3654 on MIPS_ABI_O32, if their first member has double precision. */
3655 if (mips_saved_regsize (tdep
) < 8
3656 && mips_type_needs_double_align (arg_type
))
3661 /* Note: Floating-point values that didn't fit into an FP
3662 register are only written to memory. */
3665 /* Remember if the argument was written to the stack. */
3666 int stack_used_p
= 0;
3667 int partial_len
= (len
< mips_saved_regsize (tdep
)
3668 ? len
: mips_saved_regsize (tdep
));
3671 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3674 /* Write this portion of the argument to the stack. */
3675 if (argreg
> MIPS_LAST_ARG_REGNUM
3677 || fp_register_arg_p (typecode
, arg_type
))
3679 /* Should shorter than int integer values be
3680 promoted to int before being stored? */
3681 int longword_offset
= 0;
3684 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3686 if (mips_stack_argsize (tdep
) == 8
3687 && (typecode
== TYPE_CODE_INT
3688 || typecode
== TYPE_CODE_PTR
3689 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3690 longword_offset
= mips_stack_argsize (tdep
) - len
;
3695 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3696 paddr_nz (stack_offset
));
3697 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3698 paddr_nz (longword_offset
));
3701 addr
= sp
+ stack_offset
+ longword_offset
;
3706 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3708 for (i
= 0; i
< partial_len
; i
++)
3710 fprintf_unfiltered (gdb_stdlog
, "%02x",
3714 write_memory (addr
, val
, partial_len
);
3717 /* Note!!! This is NOT an else clause. Odd sized
3718 structs may go thru BOTH paths. Floating point
3719 arguments will not. */
3720 /* Write this portion of the argument to a general
3721 purpose register. */
3722 if (argreg
<= MIPS_LAST_ARG_REGNUM
3723 && !fp_register_arg_p (typecode
, arg_type
))
3725 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3726 /* Value may need to be sign extended, because
3727 mips_regsize() != mips_saved_regsize(). */
3729 /* A non-floating-point argument being passed in a
3730 general register. If a struct or union, and if
3731 the remaining length is smaller than the register
3732 size, we have to adjust the register value on
3735 It does not seem to be necessary to do the
3736 same for integral types.
3738 Also don't do this adjustment on O64 binaries.
3740 cagney/2001-07-23: gdb/179: Also, GCC, when
3741 outputting LE O32 with sizeof (struct) <
3742 mips_saved_regsize(), generates a left shift as
3743 part of storing the argument in a register a
3744 register (the left shift isn't generated when
3745 sizeof (struct) >= mips_saved_regsize()). Since
3746 it is quite possible that this is GCC
3747 contradicting the LE/O32 ABI, GDB has not been
3748 adjusted to accommodate this. Either someone
3749 needs to demonstrate that the LE/O32 ABI
3750 specifies such a left shift OR this new ABI gets
3751 identified as such and GDB gets tweaked
3754 if (mips_saved_regsize (tdep
) < 8
3755 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3756 && partial_len
< mips_saved_regsize (tdep
)
3757 && (typecode
== TYPE_CODE_STRUCT
||
3758 typecode
== TYPE_CODE_UNION
))
3759 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3763 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3766 mips_saved_regsize (tdep
)));
3767 write_register (argreg
, regval
);
3770 /* Prevent subsequent floating point arguments from
3771 being passed in floating point registers. */
3772 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3778 /* Compute the the offset into the stack at which we
3779 will copy the next parameter.
3781 In older ABIs, the caller reserved space for
3782 registers that contained arguments. This was loosely
3783 refered to as their "home". Consequently, space is
3784 always allocated. */
3786 stack_offset
+= align_up (partial_len
,
3787 mips_stack_argsize (tdep
));
3791 fprintf_unfiltered (gdb_stdlog
, "\n");
3794 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3796 /* Return adjusted stack pointer. */
3800 static enum return_value_convention
3801 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3802 struct regcache
*regcache
,
3803 void *readbuf
, const void *writebuf
)
3805 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3807 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3808 || TYPE_CODE (type
) == TYPE_CODE_UNION
3809 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3810 return RETURN_VALUE_STRUCT_CONVENTION
;
3811 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3812 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3814 /* A single-precision floating-point value. It fits in the
3815 least significant part of FP0. */
3817 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3818 mips_xfer_register (regcache
,
3819 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3821 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3822 return RETURN_VALUE_REGISTER_CONVENTION
;
3824 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3825 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3827 /* A double-precision floating-point value. The most
3828 significant part goes in FP1, and the least significant in
3831 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3832 switch (TARGET_BYTE_ORDER
)
3834 case BFD_ENDIAN_LITTLE
:
3835 mips_xfer_register (regcache
,
3836 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3837 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3838 mips_xfer_register (regcache
,
3839 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3840 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3842 case BFD_ENDIAN_BIG
:
3843 mips_xfer_register (regcache
,
3844 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3845 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3846 mips_xfer_register (regcache
,
3847 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3848 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3851 internal_error (__FILE__
, __LINE__
, "bad switch");
3853 return RETURN_VALUE_REGISTER_CONVENTION
;
3856 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3857 && TYPE_NFIELDS (type
) <= 2
3858 && TYPE_NFIELDS (type
) >= 1
3859 && ((TYPE_NFIELDS (type
) == 1
3860 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3862 || (TYPE_NFIELDS (type
) == 2
3863 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3865 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3867 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3869 /* A struct that contains one or two floats. Each value is part
3870 in the least significant part of their floating point
3872 bfd_byte reg
[MAX_REGISTER_SIZE
];
3875 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3876 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3878 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3881 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3883 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3884 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3885 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3887 return RETURN_VALUE_REGISTER_CONVENTION
;
3891 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3892 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3894 /* A structure or union. Extract the left justified value,
3895 regardless of the byte order. I.e. DO NOT USE
3899 for (offset
= 0, regnum
= V0_REGNUM
;
3900 offset
< TYPE_LENGTH (type
);
3901 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3903 int xfer
= register_size (current_gdbarch
, regnum
);
3904 if (offset
+ xfer
> TYPE_LENGTH (type
))
3905 xfer
= TYPE_LENGTH (type
) - offset
;
3907 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3908 offset
, xfer
, regnum
);
3909 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3910 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3912 return RETURN_VALUE_REGISTER_CONVENTION
;
3917 /* A scalar extract each part but least-significant-byte
3918 justified. o32 thinks registers are 4 byte, regardless of
3919 the ISA. mips_stack_argsize controls this. */
3922 for (offset
= 0, regnum
= V0_REGNUM
;
3923 offset
< TYPE_LENGTH (type
);
3924 offset
+= mips_stack_argsize (tdep
), regnum
++)
3926 int xfer
= mips_stack_argsize (tdep
);
3928 if (offset
+ xfer
> TYPE_LENGTH (type
))
3929 xfer
= TYPE_LENGTH (type
) - offset
;
3931 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3932 offset
, xfer
, regnum
);
3933 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3934 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3936 return RETURN_VALUE_REGISTER_CONVENTION
;
3940 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3944 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3945 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3947 struct value
**args
, CORE_ADDR sp
,
3948 int struct_return
, CORE_ADDR struct_addr
)
3954 int stack_offset
= 0;
3955 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3957 /* For shared libraries, "t9" needs to point at the function
3959 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3961 /* Set the return address register to point to the entry point of
3962 the program, where a breakpoint lies in wait. */
3963 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3965 /* First ensure that the stack and structure return address (if any)
3966 are properly aligned. The stack has to be at least 64-bit
3967 aligned even on 32-bit machines, because doubles must be 64-bit
3968 aligned. For n32 and n64, stack frames need to be 128-bit
3969 aligned, so we round to this widest known alignment. */
3971 sp
= align_down (sp
, 16);
3972 struct_addr
= align_down (struct_addr
, 16);
3974 /* Now make space on the stack for the args. */
3975 for (argnum
= 0; argnum
< nargs
; argnum
++)
3976 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3977 mips_stack_argsize (tdep
));
3978 sp
-= align_up (len
, 16);
3981 fprintf_unfiltered (gdb_stdlog
,
3982 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3983 paddr_nz (sp
), (long) align_up (len
, 16));
3985 /* Initialize the integer and float register pointers. */
3987 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3989 /* The struct_return pointer occupies the first parameter-passing reg. */
3993 fprintf_unfiltered (gdb_stdlog
,
3994 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3995 argreg
, paddr_nz (struct_addr
));
3996 write_register (argreg
++, struct_addr
);
3997 stack_offset
+= mips_stack_argsize (tdep
);
4000 /* Now load as many as possible of the first arguments into
4001 registers, and push the rest onto the stack. Loop thru args
4002 from first to last. */
4003 for (argnum
= 0; argnum
< nargs
; argnum
++)
4006 char valbuf
[MAX_REGISTER_SIZE
];
4007 struct value
*arg
= args
[argnum
];
4008 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4009 int len
= TYPE_LENGTH (arg_type
);
4010 enum type_code typecode
= TYPE_CODE (arg_type
);
4013 fprintf_unfiltered (gdb_stdlog
,
4014 "mips_o64_push_dummy_call: %d len=%d type=%d",
4015 argnum
+ 1, len
, (int) typecode
);
4017 val
= (char *) VALUE_CONTENTS (arg
);
4019 /* 32-bit ABIs always start floating point arguments in an
4020 even-numbered floating point register. Round the FP register
4021 up before the check to see if there are any FP registers
4022 left. O32/O64 targets also pass the FP in the integer
4023 registers so also round up normal registers. */
4024 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
4026 if ((float_argreg
& 1))
4030 /* Floating point arguments passed in registers have to be
4031 treated specially. On 32-bit architectures, doubles
4032 are passed in register pairs; the even register gets
4033 the low word, and the odd register gets the high word.
4034 On O32/O64, the first two floating point arguments are
4035 also copied to general registers, because MIPS16 functions
4036 don't use float registers for arguments. This duplication of
4037 arguments in general registers can't hurt non-MIPS16 functions
4038 because those registers are normally skipped. */
4040 if (fp_register_arg_p (typecode
, arg_type
)
4041 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4043 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4045 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4046 unsigned long regval
;
4048 /* Write the low word of the double to the even register(s). */
4049 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4051 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4052 float_argreg
, phex (regval
, 4));
4053 write_register (float_argreg
++, regval
);
4055 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4056 argreg
, phex (regval
, 4));
4057 write_register (argreg
++, regval
);
4059 /* Write the high word of the double to the odd register(s). */
4060 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4062 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4063 float_argreg
, phex (regval
, 4));
4064 write_register (float_argreg
++, regval
);
4067 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4068 argreg
, phex (regval
, 4));
4069 write_register (argreg
++, regval
);
4073 /* This is a floating point value that fits entirely
4074 in a single register. */
4075 /* On 32 bit ABI's the float_argreg is further adjusted
4076 above to ensure that it is even register aligned. */
4077 LONGEST regval
= extract_unsigned_integer (val
, len
);
4079 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4080 float_argreg
, phex (regval
, len
));
4081 write_register (float_argreg
++, regval
);
4082 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4083 registers for each argument. The below is (my
4084 guess) to ensure that the corresponding integer
4085 register has reserved the same space. */
4087 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4088 argreg
, phex (regval
, len
));
4089 write_register (argreg
, regval
);
4090 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
4092 /* Reserve space for the FP register. */
4093 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
4097 /* Copy the argument to general registers or the stack in
4098 register-sized pieces. Large arguments are split between
4099 registers and stack. */
4100 /* Note: structs whose size is not a multiple of
4101 mips_regsize() are treated specially: Irix cc passes them
4102 in registers where gcc sometimes puts them on the stack.
4103 For maximum compatibility, we will put them in both
4105 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
4106 && (len
% mips_saved_regsize (tdep
) != 0));
4107 /* Structures should be aligned to eight bytes (even arg registers)
4108 on MIPS_ABI_O32, if their first member has double precision. */
4109 if (mips_saved_regsize (tdep
) < 8
4110 && mips_type_needs_double_align (arg_type
))
4115 /* Note: Floating-point values that didn't fit into an FP
4116 register are only written to memory. */
4119 /* Remember if the argument was written to the stack. */
4120 int stack_used_p
= 0;
4121 int partial_len
= (len
< mips_saved_regsize (tdep
)
4122 ? len
: mips_saved_regsize (tdep
));
4125 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4128 /* Write this portion of the argument to the stack. */
4129 if (argreg
> MIPS_LAST_ARG_REGNUM
4131 || fp_register_arg_p (typecode
, arg_type
))
4133 /* Should shorter than int integer values be
4134 promoted to int before being stored? */
4135 int longword_offset
= 0;
4138 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4140 if (mips_stack_argsize (tdep
) == 8
4141 && (typecode
== TYPE_CODE_INT
4142 || typecode
== TYPE_CODE_PTR
4143 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4144 longword_offset
= mips_stack_argsize (tdep
) - len
;
4149 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4150 paddr_nz (stack_offset
));
4151 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4152 paddr_nz (longword_offset
));
4155 addr
= sp
+ stack_offset
+ longword_offset
;
4160 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4162 for (i
= 0; i
< partial_len
; i
++)
4164 fprintf_unfiltered (gdb_stdlog
, "%02x",
4168 write_memory (addr
, val
, partial_len
);
4171 /* Note!!! This is NOT an else clause. Odd sized
4172 structs may go thru BOTH paths. Floating point
4173 arguments will not. */
4174 /* Write this portion of the argument to a general
4175 purpose register. */
4176 if (argreg
<= MIPS_LAST_ARG_REGNUM
4177 && !fp_register_arg_p (typecode
, arg_type
))
4179 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4180 /* Value may need to be sign extended, because
4181 mips_regsize() != mips_saved_regsize(). */
4183 /* A non-floating-point argument being passed in a
4184 general register. If a struct or union, and if
4185 the remaining length is smaller than the register
4186 size, we have to adjust the register value on
4189 It does not seem to be necessary to do the
4190 same for integral types.
4192 Also don't do this adjustment on O64 binaries.
4194 cagney/2001-07-23: gdb/179: Also, GCC, when
4195 outputting LE O32 with sizeof (struct) <
4196 mips_saved_regsize(), generates a left shift as
4197 part of storing the argument in a register a
4198 register (the left shift isn't generated when
4199 sizeof (struct) >= mips_saved_regsize()). Since
4200 it is quite possible that this is GCC
4201 contradicting the LE/O32 ABI, GDB has not been
4202 adjusted to accommodate this. Either someone
4203 needs to demonstrate that the LE/O32 ABI
4204 specifies such a left shift OR this new ABI gets
4205 identified as such and GDB gets tweaked
4208 if (mips_saved_regsize (tdep
) < 8
4209 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4210 && partial_len
< mips_saved_regsize (tdep
)
4211 && (typecode
== TYPE_CODE_STRUCT
||
4212 typecode
== TYPE_CODE_UNION
))
4213 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
4217 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4220 mips_saved_regsize (tdep
)));
4221 write_register (argreg
, regval
);
4224 /* Prevent subsequent floating point arguments from
4225 being passed in floating point registers. */
4226 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4232 /* Compute the the offset into the stack at which we
4233 will copy the next parameter.
4235 In older ABIs, the caller reserved space for
4236 registers that contained arguments. This was loosely
4237 refered to as their "home". Consequently, space is
4238 always allocated. */
4240 stack_offset
+= align_up (partial_len
,
4241 mips_stack_argsize (tdep
));
4245 fprintf_unfiltered (gdb_stdlog
, "\n");
4248 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
4250 /* Return adjusted stack pointer. */
4255 mips_o64_extract_return_value (struct type
*valtype
,
4256 char regbuf
[], char *valbuf
)
4258 struct return_value_word lo
;
4259 struct return_value_word hi
;
4260 return_value_location (valtype
, &hi
, &lo
);
4262 memcpy (valbuf
+ lo
.buf_offset
,
4263 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4264 lo
.reg_offset
, lo
.len
);
4267 memcpy (valbuf
+ hi
.buf_offset
,
4268 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4269 hi
.reg_offset
, hi
.len
);
4273 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4275 char raw_buffer
[MAX_REGISTER_SIZE
];
4276 struct return_value_word lo
;
4277 struct return_value_word hi
;
4278 return_value_location (valtype
, &hi
, &lo
);
4280 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4281 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4282 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4283 raw_buffer
, register_size (current_gdbarch
,
4288 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4289 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4290 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4292 register_size (current_gdbarch
,
4298 mips_pop_frame (void)
4301 struct frame_info
*frame
= get_current_frame ();
4302 CORE_ADDR new_sp
= get_frame_base (frame
);
4303 mips_extra_func_info_t proc_desc
;
4304 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4306 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
4308 generic_pop_dummy_frame ();
4309 flush_cached_frames ();
4313 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
4314 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
4315 mips_find_saved_regs (frame
);
4316 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
4317 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
4318 && deprecated_get_frame_saved_regs (frame
)[regnum
])
4320 /* Floating point registers must not be sign extended, in case
4321 mips_saved_regsize() = 4 but sizeof (FP0_REGNUM) == 8. */
4323 if (mips_regnum (current_gdbarch
)->fp0
<= regnum
4324 && regnum
< mips_regnum (current_gdbarch
)->fp0
+ 32)
4325 write_register (regnum
,
4326 read_memory_unsigned_integer
4327 (deprecated_get_frame_saved_regs (frame
)[regnum
],
4328 mips_saved_regsize (tdep
)));
4330 write_register (regnum
,
4331 read_memory_integer (deprecated_get_frame_saved_regs
4333 mips_saved_regsize (tdep
)));
4336 write_register (SP_REGNUM
, new_sp
);
4337 flush_cached_frames ();
4339 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
4341 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
4343 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
4344 pi_ptr
!= NULL
; prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
4346 if (&pi_ptr
->info
== proc_desc
)
4351 error ("Can't locate dummy extra frame info\n");
4353 if (prev_ptr
!= NULL
)
4354 prev_ptr
->next
= pi_ptr
->next
;
4356 linked_proc_desc_table
= pi_ptr
->next
;
4360 write_register (mips_regnum (current_gdbarch
)->hi
,
4361 read_memory_integer ((new_sp
4362 - 2 * mips_saved_regsize (tdep
)),
4363 mips_saved_regsize (tdep
)));
4364 write_register (mips_regnum (current_gdbarch
)->lo
,
4365 read_memory_integer ((new_sp
4366 - 3 * mips_saved_regsize (tdep
)),
4367 mips_saved_regsize (tdep
)));
4368 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
4369 write_register (mips_regnum (current_gdbarch
)->fp_control_status
,
4370 read_memory_integer ((new_sp
4372 4 * mips_saved_regsize (tdep
)),
4373 mips_saved_regsize (tdep
)));
4377 /* Floating point register management.
4379 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4380 64bit operations, these early MIPS cpus treat fp register pairs
4381 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4382 registers and offer a compatibility mode that emulates the MIPS2 fp
4383 model. When operating in MIPS2 fp compat mode, later cpu's split
4384 double precision floats into two 32-bit chunks and store them in
4385 consecutive fp regs. To display 64-bit floats stored in this
4386 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4387 Throw in user-configurable endianness and you have a real mess.
4389 The way this works is:
4390 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4391 double-precision value will be split across two logical registers.
4392 The lower-numbered logical register will hold the low-order bits,
4393 regardless of the processor's endianness.
4394 - If we are on a 64-bit processor, and we are looking for a
4395 single-precision value, it will be in the low ordered bits
4396 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4397 save slot in memory.
4398 - If we are in 64-bit mode, everything is straightforward.
4400 Note that this code only deals with "live" registers at the top of the
4401 stack. We will attempt to deal with saved registers later, when
4402 the raw/cooked register interface is in place. (We need a general
4403 interface that can deal with dynamic saved register sizes -- fp
4404 regs could be 32 bits wide in one frame and 64 on the frame above
4407 static struct type
*
4408 mips_float_register_type (void)
4410 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4411 return builtin_type_ieee_single_big
;
4413 return builtin_type_ieee_single_little
;
4416 static struct type
*
4417 mips_double_register_type (void)
4419 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4420 return builtin_type_ieee_double_big
;
4422 return builtin_type_ieee_double_little
;
4425 /* Copy a 32-bit single-precision value from the current frame
4426 into rare_buffer. */
4429 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4432 int raw_size
= register_size (current_gdbarch
, regno
);
4433 char *raw_buffer
= alloca (raw_size
);
4435 if (!frame_register_read (frame
, regno
, raw_buffer
))
4436 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4439 /* We have a 64-bit value for this register. Find the low-order
4443 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4448 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4452 memcpy (rare_buffer
, raw_buffer
, 4);
4456 /* Copy a 64-bit double-precision value from the current frame into
4457 rare_buffer. This may include getting half of it from the next
4461 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4464 int raw_size
= register_size (current_gdbarch
, regno
);
4466 if (raw_size
== 8 && !mips2_fp_compat ())
4468 /* We have a 64-bit value for this register, and we should use
4470 if (!frame_register_read (frame
, regno
, rare_buffer
))
4471 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4475 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4476 internal_error (__FILE__
, __LINE__
,
4477 "mips_read_fp_register_double: bad access to "
4478 "odd-numbered FP register");
4480 /* mips_read_fp_register_single will find the correct 32 bits from
4482 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4484 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4485 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4489 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4490 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4496 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4498 { /* do values for FP (float) regs */
4500 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4501 int inv1
, inv2
, namelen
;
4504 (char *) alloca (2 *
4505 register_size (current_gdbarch
,
4506 mips_regnum (current_gdbarch
)->fp0
));
4508 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4509 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4512 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4514 /* 4-byte registers: Print hex and floating. Also print even
4515 numbered registers as doubles. */
4516 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4517 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4519 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4522 fprintf_filtered (file
, " flt: ");
4524 fprintf_filtered (file
, " <invalid float> ");
4526 fprintf_filtered (file
, "%-17.9g", flt1
);
4528 if (regnum
% 2 == 0)
4530 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4531 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4534 fprintf_filtered (file
, " dbl: ");
4536 fprintf_filtered (file
, "<invalid double>");
4538 fprintf_filtered (file
, "%-24.17g", doub
);
4543 /* Eight byte registers: print each one as hex, float and double. */
4544 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4545 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4547 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4548 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4551 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4554 fprintf_filtered (file
, " flt: ");
4556 fprintf_filtered (file
, "<invalid float>");
4558 fprintf_filtered (file
, "%-17.9g", flt1
);
4560 fprintf_filtered (file
, " dbl: ");
4562 fprintf_filtered (file
, "<invalid double>");
4564 fprintf_filtered (file
, "%-24.17g", doub
);
4569 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4570 int regnum
, int all
)
4572 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4573 char raw_buffer
[MAX_REGISTER_SIZE
];
4576 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4578 mips_print_fp_register (file
, frame
, regnum
);
4582 /* Get the data in raw format. */
4583 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4585 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4589 fputs_filtered (REGISTER_NAME (regnum
), file
);
4591 /* The problem with printing numeric register names (r26, etc.) is that
4592 the user can't use them on input. Probably the best solution is to
4593 fix it so that either the numeric or the funky (a2, etc.) names
4594 are accepted on input. */
4595 if (regnum
< MIPS_NUMREGS
)
4596 fprintf_filtered (file
, "(r%d): ", regnum
);
4598 fprintf_filtered (file
, ": ");
4600 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4602 register_size (current_gdbarch
,
4603 regnum
) - register_size (current_gdbarch
, regnum
);
4607 print_scalar_formatted (raw_buffer
+ offset
,
4608 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4612 /* Replacement for generic do_registers_info.
4613 Print regs in pretty columns. */
4616 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4619 fprintf_filtered (file
, " ");
4620 mips_print_fp_register (file
, frame
, regnum
);
4621 fprintf_filtered (file
, "\n");
4626 /* Print a row's worth of GP (int) registers, with name labels above */
4629 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4632 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4633 /* do values for GP (int) regs */
4634 char raw_buffer
[MAX_REGISTER_SIZE
];
4635 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4639 /* For GP registers, we print a separate row of names above the vals */
4640 fprintf_filtered (file
, " ");
4641 for (col
= 0, regnum
= start_regnum
;
4642 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4644 if (*REGISTER_NAME (regnum
) == '\0')
4645 continue; /* unused register */
4646 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4648 break; /* end the row: reached FP register */
4649 fprintf_filtered (file
,
4650 mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4651 REGISTER_NAME (regnum
));
4654 /* print the R0 to R31 names */
4655 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4656 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4658 fprintf_filtered (file
, "\n ");
4660 /* now print the values in hex, 4 or 8 to the row */
4661 for (col
= 0, regnum
= start_regnum
;
4662 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4664 if (*REGISTER_NAME (regnum
) == '\0')
4665 continue; /* unused register */
4666 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4668 break; /* end row: reached FP register */
4669 /* OK: get the data in raw format. */
4670 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4671 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4672 /* pad small registers */
4674 byte
< (mips_regsize (current_gdbarch
)
4675 - register_size (current_gdbarch
, regnum
)); byte
++)
4676 printf_filtered (" ");
4677 /* Now print the register value in hex, endian order. */
4678 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4680 register_size (current_gdbarch
,
4681 regnum
) - register_size (current_gdbarch
, regnum
);
4682 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4683 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4685 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4687 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4688 fprintf_filtered (file
, " ");
4691 if (col
> 0) /* ie. if we actually printed anything... */
4692 fprintf_filtered (file
, "\n");
4697 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4700 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4701 struct frame_info
*frame
, int regnum
, int all
)
4703 if (regnum
!= -1) /* do one specified register */
4705 gdb_assert (regnum
>= NUM_REGS
);
4706 if (*(REGISTER_NAME (regnum
)) == '\0')
4707 error ("Not a valid register for the current processor type");
4709 mips_print_register (file
, frame
, regnum
, 0);
4710 fprintf_filtered (file
, "\n");
4713 /* do all (or most) registers */
4716 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4718 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4721 if (all
) /* true for "INFO ALL-REGISTERS" command */
4722 regnum
= print_fp_register_row (file
, frame
, regnum
);
4724 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4727 regnum
= print_gp_register_row (file
, frame
, regnum
);
4732 /* Is this a branch with a delay slot? */
4734 static int is_delayed (unsigned long);
4737 is_delayed (unsigned long insn
)
4740 for (i
= 0; i
< NUMOPCODES
; ++i
)
4741 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4742 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4744 return (i
< NUMOPCODES
4745 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4746 | INSN_COND_BRANCH_DELAY
4747 | INSN_COND_BRANCH_LIKELY
)));
4751 mips_step_skips_delay (CORE_ADDR pc
)
4753 char buf
[MIPS_INSTLEN
];
4755 /* There is no branch delay slot on MIPS16. */
4756 if (pc_is_mips16 (pc
))
4759 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4760 /* If error reading memory, guess that it is not a delayed branch. */
4762 return is_delayed ((unsigned long)
4763 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4767 /* Given PC at the function's start address, attempt to find the
4768 prologue end using SAL information. Return zero if the skip fails.
4770 A non-optimized prologue traditionally has one SAL for the function
4771 and a second for the function body. A single line function has
4772 them both pointing at the same line.
4774 An optimized prologue is similar but the prologue may contain
4775 instructions (SALs) from the instruction body. Need to skip those
4776 while not getting into the function body.
4778 The functions end point and an increasing SAL line are used as
4779 indicators of the prologue's endpoint.
4781 This code is based on the function refine_prologue_limit (versions
4782 found in both ia64 and ppc). */
4785 skip_prologue_using_sal (CORE_ADDR func_addr
)
4787 struct symtab_and_line prologue_sal
;
4791 /* Get an initial range for the function. */
4792 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
4793 start_pc
+= FUNCTION_START_OFFSET
;
4795 prologue_sal
= find_pc_line (start_pc
, 0);
4796 if (prologue_sal
.line
!= 0)
4798 while (prologue_sal
.end
< end_pc
)
4800 struct symtab_and_line sal
;
4802 sal
= find_pc_line (prologue_sal
.end
, 0);
4805 /* Assume that a consecutive SAL for the same (or larger)
4806 line mark the prologue -> body transition. */
4807 if (sal
.line
>= prologue_sal
.line
)
4809 /* The case in which compiler's optimizer/scheduler has
4810 moved instructions into the prologue. We look ahead in
4811 the function looking for address ranges whose
4812 corresponding line number is less the first one that we
4813 found for the function. This is more conservative then
4814 refine_prologue_limit which scans a large number of SALs
4815 looking for any in the prologue */
4819 return prologue_sal
.end
;
4822 /* Skip the PC past function prologue instructions (32-bit version).
4823 This is a helper function for mips_skip_prologue. */
4826 mips32_skip_prologue (CORE_ADDR pc
)
4830 int seen_sp_adjust
= 0;
4831 int load_immediate_bytes
= 0;
4833 /* Find an upper bound on the prologue. */
4834 end_pc
= skip_prologue_using_sal (pc
);
4836 end_pc
= pc
+ 100; /* Magic. */
4838 /* Skip the typical prologue instructions. These are the stack adjustment
4839 instruction and the instructions that save registers on the stack
4840 or in the gcc frame. */
4841 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4843 unsigned long high_word
;
4845 inst
= mips_fetch_instruction (pc
);
4846 high_word
= (inst
>> 16) & 0xffff;
4848 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4849 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4851 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4852 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4854 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4855 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4856 && (inst
& 0x001F0000)) /* reg != $zero */
4859 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4861 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4863 continue; /* reg != $zero */
4865 /* move $s8,$sp. With different versions of gas this will be either
4866 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4867 Accept any one of these. */
4868 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4871 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4873 else if (high_word
== 0x3c1c) /* lui $gp,n */
4875 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4877 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4878 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4880 /* The following instructions load $at or $t0 with an immediate
4881 value in preparation for a stack adjustment via
4882 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4883 a local variable, so we accept them only before a stack adjustment
4884 instruction was seen. */
4885 else if (!seen_sp_adjust
)
4887 if (high_word
== 0x3c01 || /* lui $at,n */
4888 high_word
== 0x3c08) /* lui $t0,n */
4890 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4893 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4894 high_word
== 0x3508 || /* ori $t0,$t0,n */
4895 high_word
== 0x3401 || /* ori $at,$zero,n */
4896 high_word
== 0x3408) /* ori $t0,$zero,n */
4898 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4908 /* In a frameless function, we might have incorrectly
4909 skipped some load immediate instructions. Undo the skipping
4910 if the load immediate was not followed by a stack adjustment. */
4911 if (load_immediate_bytes
&& !seen_sp_adjust
)
4912 pc
-= load_immediate_bytes
;
4916 /* Skip the PC past function prologue instructions (16-bit version).
4917 This is a helper function for mips_skip_prologue. */
4920 mips16_skip_prologue (CORE_ADDR pc
)
4923 int extend_bytes
= 0;
4924 int prev_extend_bytes
;
4926 /* Table of instructions likely to be found in a function prologue. */
4929 unsigned short inst
;
4930 unsigned short mask
;
4936 , /* addiu $sp,offset */
4939 , /* daddiu $sp,offset */
4942 , /* sw reg,n($sp) */
4945 , /* sd reg,n($sp) */
4948 , /* sw $ra,n($sp) */
4951 , /* sd $ra,n($sp) */
4957 , /* sw $a0-$a3,n($s1) */
4960 , /* move reg,$a0-$a3 */
4963 , /* entry pseudo-op */
4966 , /* addiu $s1,$sp,n */
4968 0, 0} /* end of table marker */
4971 /* Find an upper bound on the prologue. */
4972 end_pc
= skip_prologue_using_sal (pc
);
4974 end_pc
= pc
+ 100; /* Magic. */
4976 /* Skip the typical prologue instructions. These are the stack adjustment
4977 instruction and the instructions that save registers on the stack
4978 or in the gcc frame. */
4979 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4981 unsigned short inst
;
4984 inst
= mips_fetch_instruction (pc
);
4986 /* Normally we ignore an extend instruction. However, if it is
4987 not followed by a valid prologue instruction, we must adjust
4988 the pc back over the extend so that it won't be considered
4989 part of the prologue. */
4990 if ((inst
& 0xf800) == 0xf000) /* extend */
4992 extend_bytes
= MIPS16_INSTLEN
;
4995 prev_extend_bytes
= extend_bytes
;
4998 /* Check for other valid prologue instructions besides extend. */
4999 for (i
= 0; table
[i
].mask
!= 0; i
++)
5000 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5002 if (table
[i
].mask
!= 0) /* it was in table? */
5003 continue; /* ignore it */
5007 /* Return the current pc, adjusted backwards by 2 if
5008 the previous instruction was an extend. */
5009 return pc
- prev_extend_bytes
;
5015 /* To skip prologues, I use this predicate. Returns either PC itself
5016 if the code at PC does not look like a function prologue; otherwise
5017 returns an address that (if we're lucky) follows the prologue. If
5018 LENIENT, then we must skip everything which is involved in setting
5019 up the frame (it's OK to skip more, just so long as we don't skip
5020 anything which might clobber the registers which are being saved.
5021 We must skip more in the case where part of the prologue is in the
5022 delay slot of a non-prologue instruction). */
5025 mips_skip_prologue (CORE_ADDR pc
)
5027 /* See if we can determine the end of the prologue via the symbol table.
5028 If so, then return either PC, or the PC after the prologue, whichever
5031 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
5033 if (post_prologue_pc
!= 0)
5034 return max (pc
, post_prologue_pc
);
5036 /* Can't determine prologue from the symbol table, need to examine
5039 if (pc_is_mips16 (pc
))
5040 return mips16_skip_prologue (pc
);
5042 return mips32_skip_prologue (pc
);
5045 /* Exported procedure: Is PC in the signal trampoline code */
5048 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5050 if (sigtramp_address
== 0)
5052 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5055 /* Root of all "set mips "/"show mips " commands. This will eventually be
5056 used for all MIPS-specific commands. */
5059 show_mips_command (char *args
, int from_tty
)
5061 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5065 set_mips_command (char *args
, int from_tty
)
5068 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5069 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5072 /* Commands to show/set the MIPS FPU type. */
5075 show_mipsfpu_command (char *args
, int from_tty
)
5078 switch (MIPS_FPU_TYPE
)
5080 case MIPS_FPU_SINGLE
:
5081 fpu
= "single-precision";
5083 case MIPS_FPU_DOUBLE
:
5084 fpu
= "double-precision";
5087 fpu
= "absent (none)";
5090 internal_error (__FILE__
, __LINE__
, "bad switch");
5092 if (mips_fpu_type_auto
)
5094 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5098 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5103 set_mipsfpu_command (char *args
, int from_tty
)
5106 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5107 show_mipsfpu_command (args
, from_tty
);
5111 set_mipsfpu_single_command (char *args
, int from_tty
)
5113 struct gdbarch_info info
;
5114 gdbarch_info_init (&info
);
5115 mips_fpu_type
= MIPS_FPU_SINGLE
;
5116 mips_fpu_type_auto
= 0;
5117 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5118 instead of relying on globals. Doing that would let generic code
5119 handle the search for this specific architecture. */
5120 if (!gdbarch_update_p (info
))
5121 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5125 set_mipsfpu_double_command (char *args
, int from_tty
)
5127 struct gdbarch_info info
;
5128 gdbarch_info_init (&info
);
5129 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5130 mips_fpu_type_auto
= 0;
5131 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5132 instead of relying on globals. Doing that would let generic code
5133 handle the search for this specific architecture. */
5134 if (!gdbarch_update_p (info
))
5135 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5139 set_mipsfpu_none_command (char *args
, int from_tty
)
5141 struct gdbarch_info info
;
5142 gdbarch_info_init (&info
);
5143 mips_fpu_type
= MIPS_FPU_NONE
;
5144 mips_fpu_type_auto
= 0;
5145 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5146 instead of relying on globals. Doing that would let generic code
5147 handle the search for this specific architecture. */
5148 if (!gdbarch_update_p (info
))
5149 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5153 set_mipsfpu_auto_command (char *args
, int from_tty
)
5155 mips_fpu_type_auto
= 1;
5158 /* Attempt to identify the particular processor model by reading the
5159 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5160 the relevant processor still exists (it dates back to '94) and
5161 secondly this is not the way to do this. The processor type should
5162 be set by forcing an architecture change. */
5165 deprecated_mips_set_processor_regs_hack (void)
5167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5170 prid
= read_register (PRID_REGNUM
);
5172 if ((prid
& ~0xf) == 0x700)
5173 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5176 /* Just like reinit_frame_cache, but with the right arguments to be
5177 callable as an sfunc. */
5180 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5181 struct cmd_list_element
*c
)
5183 reinit_frame_cache ();
5187 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5189 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5190 mips_extra_func_info_t proc_desc
;
5192 /* Search for the function containing this address. Set the low bit
5193 of the address when searching, in case we were given an even address
5194 that is the start of a 16-bit function. If we didn't do this,
5195 the search would fail because the symbol table says the function
5196 starts at an odd address, i.e. 1 byte past the given address. */
5197 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5198 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5200 /* Make an attempt to determine if this is a 16-bit function. If
5201 the procedure descriptor exists and the address therein is odd,
5202 it's definitely a 16-bit function. Otherwise, we have to just
5203 guess that if the address passed in is odd, it's 16-bits. */
5204 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5205 disassembler needs to be able to locally determine the ISA, and
5206 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5210 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5211 info
->mach
= bfd_mach_mips16
;
5215 if (pc_is_mips16 (memaddr
))
5216 info
->mach
= bfd_mach_mips16
;
5219 /* Round down the instruction address to the appropriate boundary. */
5220 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5222 /* Set the disassembler options. */
5223 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5225 /* Set up the disassembler info, so that we get the right
5226 register names from libopcodes. */
5227 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5228 info
->disassembler_options
= "gpr-names=n32";
5230 info
->disassembler_options
= "gpr-names=64";
5231 info
->flavour
= bfd_target_elf_flavour
;
5234 /* This string is not recognized explicitly by the disassembler,
5235 but it tells the disassembler to not try to guess the ABI from
5236 the bfd elf headers, such that, if the user overrides the ABI
5237 of a program linked as NewABI, the disassembly will follow the
5238 register naming conventions specified by the user. */
5239 info
->disassembler_options
= "gpr-names=32";
5241 /* Call the appropriate disassembler based on the target endian-ness. */
5242 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5243 return print_insn_big_mips (memaddr
, info
);
5245 return print_insn_little_mips (memaddr
, info
);
5248 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5249 counter value to determine whether a 16- or 32-bit breakpoint should be
5250 used. It returns a pointer to a string of bytes that encode a breakpoint
5251 instruction, stores the length of the string to *lenptr, and adjusts pc
5252 (if necessary) to point to the actual memory location where the
5253 breakpoint should be inserted. */
5255 static const unsigned char *
5256 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5258 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5260 if (pc_is_mips16 (*pcptr
))
5262 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5263 *pcptr
= unmake_mips16_addr (*pcptr
);
5264 *lenptr
= sizeof (mips16_big_breakpoint
);
5265 return mips16_big_breakpoint
;
5269 /* The IDT board uses an unusual breakpoint value, and
5270 sometimes gets confused when it sees the usual MIPS
5271 breakpoint instruction. */
5272 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5273 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5274 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5276 *lenptr
= sizeof (big_breakpoint
);
5278 if (strcmp (target_shortname
, "mips") == 0)
5279 return idt_big_breakpoint
;
5280 else if (strcmp (target_shortname
, "ddb") == 0
5281 || strcmp (target_shortname
, "pmon") == 0
5282 || strcmp (target_shortname
, "lsi") == 0)
5283 return pmon_big_breakpoint
;
5285 return big_breakpoint
;
5290 if (pc_is_mips16 (*pcptr
))
5292 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5293 *pcptr
= unmake_mips16_addr (*pcptr
);
5294 *lenptr
= sizeof (mips16_little_breakpoint
);
5295 return mips16_little_breakpoint
;
5299 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5300 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5301 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5303 *lenptr
= sizeof (little_breakpoint
);
5305 if (strcmp (target_shortname
, "mips") == 0)
5306 return idt_little_breakpoint
;
5307 else if (strcmp (target_shortname
, "ddb") == 0
5308 || strcmp (target_shortname
, "pmon") == 0
5309 || strcmp (target_shortname
, "lsi") == 0)
5310 return pmon_little_breakpoint
;
5312 return little_breakpoint
;
5317 /* If PC is in a mips16 call or return stub, return the address of the target
5318 PC, which is either the callee or the caller. There are several
5319 cases which must be handled:
5321 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5322 target PC is in $31 ($ra).
5323 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5324 and the target PC is in $2.
5325 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5326 before the jal instruction, this is effectively a call stub
5327 and the the target PC is in $2. Otherwise this is effectively
5328 a return stub and the target PC is in $18.
5330 See the source code for the stubs in gcc/config/mips/mips16.S for
5333 This function implements the SKIP_TRAMPOLINE_CODE macro.
5337 mips_skip_stub (CORE_ADDR pc
)
5340 CORE_ADDR start_addr
;
5342 /* Find the starting address and name of the function containing the PC. */
5343 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5346 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5347 target PC is in $31 ($ra). */
5348 if (strcmp (name
, "__mips16_ret_sf") == 0
5349 || strcmp (name
, "__mips16_ret_df") == 0)
5350 return read_signed_register (RA_REGNUM
);
5352 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5354 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5355 and the target PC is in $2. */
5356 if (name
[19] >= '0' && name
[19] <= '9')
5357 return read_signed_register (2);
5359 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5360 before the jal instruction, this is effectively a call stub
5361 and the the target PC is in $2. Otherwise this is effectively
5362 a return stub and the target PC is in $18. */
5363 else if (name
[19] == 's' || name
[19] == 'd')
5365 if (pc
== start_addr
)
5367 /* Check if the target of the stub is a compiler-generated
5368 stub. Such a stub for a function bar might have a name
5369 like __fn_stub_bar, and might look like this:
5374 la $1,bar (becomes a lui/addiu pair)
5376 So scan down to the lui/addi and extract the target
5377 address from those two instructions. */
5379 CORE_ADDR target_pc
= read_signed_register (2);
5383 /* See if the name of the target function is __fn_stub_*. */
5384 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5387 if (strncmp (name
, "__fn_stub_", 10) != 0
5388 && strcmp (name
, "etext") != 0
5389 && strcmp (name
, "_etext") != 0)
5392 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5393 The limit on the search is arbitrarily set to 20
5394 instructions. FIXME. */
5395 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5397 inst
= mips_fetch_instruction (target_pc
);
5398 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5399 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5400 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5401 return pc
| (inst
& 0xffff); /* low word */
5404 /* Couldn't find the lui/addui pair, so return stub address. */
5408 /* This is the 'return' part of a call stub. The return
5409 address is in $r18. */
5410 return read_signed_register (18);
5413 return 0; /* not a stub */
5417 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5418 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5421 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5423 CORE_ADDR start_addr
;
5425 /* Find the starting address of the function containing the PC. If the
5426 caller didn't give us a name, look it up at the same time. */
5427 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5431 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5433 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5434 if (name
[19] >= '0' && name
[19] <= '9')
5436 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5437 before the jal instruction, this is effectively a call stub. */
5438 else if (name
[19] == 's' || name
[19] == 'd')
5439 return pc
== start_addr
;
5442 return 0; /* not a stub */
5446 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5447 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5450 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5452 CORE_ADDR start_addr
;
5454 /* Find the starting address of the function containing the PC. */
5455 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5458 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5459 if (strcmp (name
, "__mips16_ret_sf") == 0
5460 || strcmp (name
, "__mips16_ret_df") == 0)
5463 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5464 i.e. after the jal instruction, this is effectively a return stub. */
5465 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5466 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5469 return 0; /* not a stub */
5473 /* Return non-zero if the PC is in a library helper function that should
5474 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5477 mips_ignore_helper (CORE_ADDR pc
)
5481 /* Find the starting address and name of the function containing the PC. */
5482 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5485 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5486 that we want to ignore. */
5487 return (strcmp (name
, "__mips16_ret_sf") == 0
5488 || strcmp (name
, "__mips16_ret_df") == 0);
5492 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5493 the register stored on the stack (32) is different to its real raw
5494 size (64). The below ensures that registers are fetched from the
5495 stack using their ABI size and then stored into the RAW_BUFFER
5496 using their raw size.
5498 The alternative to adding this function would be to add an ABI
5499 macro - REGISTER_STACK_SIZE(). */
5502 mips_get_saved_register (char *raw_buffer
,
5505 struct frame_info
*frame
,
5506 int regnum
, enum lval_type
*lvalp
)
5509 enum lval_type lvalx
;
5513 /* Always a pseudo. */
5514 gdb_assert (regnum
>= NUM_REGS
);
5516 /* Make certain that all needed parameters are present. */
5521 if (optimizedp
== NULL
)
5522 optimizedp
= &optimizedx
;
5524 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5525 /* The SP_REGNUM is special, its value is stored in saved_regs.
5526 In fact, it is so special that it can even only be fetched
5527 using a raw register number! Once this code as been converted
5528 to frame-unwind the problem goes away. */
5529 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5530 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5531 &realnumx
, raw_buffer
);
5533 /* Get it from the next frame. */
5534 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5535 regnum
, optimizedp
, lvalp
, addrp
,
5536 &realnumx
, raw_buffer
);
5539 /* Immediately after a function call, return the saved pc.
5540 Can't always go through the frames for this because on some machines
5541 the new frame is not set up until the new function executes
5542 some instructions. */
5545 mips_saved_pc_after_call (struct frame_info
*frame
)
5547 return read_signed_register (RA_REGNUM
);
5551 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5552 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5555 mips_stab_reg_to_regnum (int num
)
5558 if (num
>= 0 && num
< 32)
5560 else if (num
>= 38 && num
< 70)
5561 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5563 regnum
= mips_regnum (current_gdbarch
)->hi
;
5565 regnum
= mips_regnum (current_gdbarch
)->lo
;
5567 /* This will hopefully (eventually) provoke a warning. Should
5568 we be calling complaint() here? */
5569 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5570 return NUM_REGS
+ regnum
;
5574 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5575 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5578 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5581 if (num
>= 0 && num
< 32)
5583 else if (num
>= 32 && num
< 64)
5584 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5586 regnum
= mips_regnum (current_gdbarch
)->hi
;
5588 regnum
= mips_regnum (current_gdbarch
)->lo
;
5590 /* This will hopefully (eventually) provoke a warning. Should we
5591 be calling complaint() here? */
5592 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5593 return NUM_REGS
+ regnum
;
5597 mips_register_sim_regno (int regnum
)
5599 /* Only makes sense to supply raw registers. */
5600 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5601 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5602 decide if it is valid. Should instead define a standard sim/gdb
5603 register numbering scheme. */
5604 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5605 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5608 return LEGACY_SIM_REGNO_IGNORE
;
5612 /* Convert an integer into an address. By first converting the value
5613 into a pointer and then extracting it signed, the address is
5614 guarenteed to be correctly sign extended. */
5617 mips_integer_to_address (struct type
*type
, void *buf
)
5619 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5620 LONGEST val
= unpack_long (type
, buf
);
5621 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5622 return extract_signed_integer (tmp
,
5623 TYPE_LENGTH (builtin_type_void_data_ptr
));
5627 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5629 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5630 const char *name
= bfd_get_section_name (abfd
, sect
);
5632 if (*abip
!= MIPS_ABI_UNKNOWN
)
5635 if (strncmp (name
, ".mdebug.", 8) != 0)
5638 if (strcmp (name
, ".mdebug.abi32") == 0)
5639 *abip
= MIPS_ABI_O32
;
5640 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5641 *abip
= MIPS_ABI_N32
;
5642 else if (strcmp (name
, ".mdebug.abi64") == 0)
5643 *abip
= MIPS_ABI_N64
;
5644 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5645 *abip
= MIPS_ABI_O64
;
5646 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5647 *abip
= MIPS_ABI_EABI32
;
5648 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5649 *abip
= MIPS_ABI_EABI64
;
5651 warning ("unsupported ABI %s.", name
+ 8);
5654 static enum mips_abi
5655 global_mips_abi (void)
5659 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5660 if (mips_abi_strings
[i
] == mips_abi_string
)
5661 return (enum mips_abi
) i
;
5663 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5666 static struct gdbarch
*
5667 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5669 struct gdbarch
*gdbarch
;
5670 struct gdbarch_tdep
*tdep
;
5672 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5674 enum mips_fpu_type fpu_type
;
5676 /* First of all, extract the elf_flags, if available. */
5677 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5678 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5679 else if (arches
!= NULL
)
5680 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5684 fprintf_unfiltered (gdb_stdlog
,
5685 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5687 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5688 switch ((elf_flags
& EF_MIPS_ABI
))
5690 case E_MIPS_ABI_O32
:
5691 found_abi
= MIPS_ABI_O32
;
5693 case E_MIPS_ABI_O64
:
5694 found_abi
= MIPS_ABI_O64
;
5696 case E_MIPS_ABI_EABI32
:
5697 found_abi
= MIPS_ABI_EABI32
;
5699 case E_MIPS_ABI_EABI64
:
5700 found_abi
= MIPS_ABI_EABI64
;
5703 if ((elf_flags
& EF_MIPS_ABI2
))
5704 found_abi
= MIPS_ABI_N32
;
5706 found_abi
= MIPS_ABI_UNKNOWN
;
5710 /* GCC creates a pseudo-section whose name describes the ABI. */
5711 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5712 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5714 /* If we have no usefu BFD information, use the ABI from the last
5715 MIPS architecture (if there is one). */
5716 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5717 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5719 /* Try the architecture for any hint of the correct ABI. */
5720 if (found_abi
== MIPS_ABI_UNKNOWN
5721 && info
.bfd_arch_info
!= NULL
5722 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5724 switch (info
.bfd_arch_info
->mach
)
5726 case bfd_mach_mips3900
:
5727 found_abi
= MIPS_ABI_EABI32
;
5729 case bfd_mach_mips4100
:
5730 case bfd_mach_mips5000
:
5731 found_abi
= MIPS_ABI_EABI64
;
5733 case bfd_mach_mips8000
:
5734 case bfd_mach_mips10000
:
5735 /* On Irix, ELF64 executables use the N64 ABI. The
5736 pseudo-sections which describe the ABI aren't present
5737 on IRIX. (Even for executables created by gcc.) */
5738 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5739 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5740 found_abi
= MIPS_ABI_N64
;
5742 found_abi
= MIPS_ABI_N32
;
5748 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5751 /* What has the user specified from the command line? */
5752 wanted_abi
= global_mips_abi ();
5754 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5757 /* Now that we have found what the ABI for this binary would be,
5758 check whether the user is overriding it. */
5759 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5760 mips_abi
= wanted_abi
;
5761 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5762 mips_abi
= found_abi
;
5764 mips_abi
= MIPS_ABI_O32
;
5766 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5769 /* Also used when doing an architecture lookup. */
5771 fprintf_unfiltered (gdb_stdlog
,
5772 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5773 mips64_transfers_32bit_regs_p
);
5775 /* Determine the MIPS FPU type. */
5776 if (!mips_fpu_type_auto
)
5777 fpu_type
= mips_fpu_type
;
5778 else if (info
.bfd_arch_info
!= NULL
5779 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5780 switch (info
.bfd_arch_info
->mach
)
5782 case bfd_mach_mips3900
:
5783 case bfd_mach_mips4100
:
5784 case bfd_mach_mips4111
:
5785 fpu_type
= MIPS_FPU_NONE
;
5787 case bfd_mach_mips4650
:
5788 fpu_type
= MIPS_FPU_SINGLE
;
5791 fpu_type
= MIPS_FPU_DOUBLE
;
5794 else if (arches
!= NULL
)
5795 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5797 fpu_type
= MIPS_FPU_DOUBLE
;
5799 fprintf_unfiltered (gdb_stdlog
,
5800 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5802 /* try to find a pre-existing architecture */
5803 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5805 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5807 /* MIPS needs to be pedantic about which ABI the object is
5809 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5811 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5813 /* Need to be pedantic about which register virtual size is
5815 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5816 != mips64_transfers_32bit_regs_p
)
5818 /* Be pedantic about which FPU is selected. */
5819 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5821 return arches
->gdbarch
;
5824 /* Need a new architecture. Fill in a target specific vector. */
5825 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5826 gdbarch
= gdbarch_alloc (&info
, tdep
);
5827 tdep
->elf_flags
= elf_flags
;
5828 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5829 tdep
->found_abi
= found_abi
;
5830 tdep
->mips_abi
= mips_abi
;
5831 tdep
->mips_fpu_type
= fpu_type
;
5833 /* Initially set everything according to the default ABI/ISA. */
5834 set_gdbarch_short_bit (gdbarch
, 16);
5835 set_gdbarch_int_bit (gdbarch
, 32);
5836 set_gdbarch_float_bit (gdbarch
, 32);
5837 set_gdbarch_double_bit (gdbarch
, 64);
5838 set_gdbarch_long_double_bit (gdbarch
, 64);
5839 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5840 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5841 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5843 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5844 mips_elf_make_msymbol_special
);
5846 /* Fill in the OS dependant register numbers and names. */
5848 const char **reg_names
;
5849 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5850 struct mips_regnum
);
5851 if (info
.osabi
== GDB_OSABI_IRIX
)
5856 regnum
->badvaddr
= 66;
5859 regnum
->fp_control_status
= 69;
5860 regnum
->fp_implementation_revision
= 70;
5862 reg_names
= mips_irix_reg_names
;
5866 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5867 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5868 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5869 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5870 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5871 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5872 regnum
->fp_control_status
= 70;
5873 regnum
->fp_implementation_revision
= 71;
5875 if (info
.bfd_arch_info
!= NULL
5876 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5877 reg_names
= mips_tx39_reg_names
;
5879 reg_names
= mips_generic_reg_names
;
5881 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5882 replaced by read_pc? */
5883 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5884 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5885 set_gdbarch_num_regs (gdbarch
, num_regs
);
5886 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5887 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5888 tdep
->mips_processor_reg_names
= reg_names
;
5889 tdep
->regnum
= regnum
;
5895 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5896 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5897 tdep
->mips_default_saved_regsize
= 4;
5898 tdep
->mips_default_stack_argsize
= 4;
5899 tdep
->mips_fp_register_double
= 0;
5900 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5901 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5902 tdep
->default_mask_address_p
= 0;
5903 set_gdbarch_long_bit (gdbarch
, 32);
5904 set_gdbarch_ptr_bit (gdbarch
, 32);
5905 set_gdbarch_long_long_bit (gdbarch
, 64);
5908 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5909 set_gdbarch_deprecated_store_return_value (gdbarch
,
5910 mips_o64_store_return_value
);
5911 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5912 mips_o64_extract_return_value
);
5913 tdep
->mips_default_saved_regsize
= 8;
5914 tdep
->mips_default_stack_argsize
= 8;
5915 tdep
->mips_fp_register_double
= 1;
5916 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5917 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5918 tdep
->default_mask_address_p
= 0;
5919 set_gdbarch_long_bit (gdbarch
, 32);
5920 set_gdbarch_ptr_bit (gdbarch
, 32);
5921 set_gdbarch_long_long_bit (gdbarch
, 64);
5922 set_gdbarch_use_struct_convention (gdbarch
,
5923 always_use_struct_convention
);
5925 case MIPS_ABI_EABI32
:
5926 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5927 set_gdbarch_deprecated_store_return_value (gdbarch
,
5928 mips_eabi_store_return_value
);
5929 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5930 mips_eabi_extract_return_value
);
5931 tdep
->mips_default_saved_regsize
= 4;
5932 tdep
->mips_default_stack_argsize
= 4;
5933 tdep
->mips_fp_register_double
= 0;
5934 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5935 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5936 tdep
->default_mask_address_p
= 0;
5937 set_gdbarch_long_bit (gdbarch
, 32);
5938 set_gdbarch_ptr_bit (gdbarch
, 32);
5939 set_gdbarch_long_long_bit (gdbarch
, 64);
5940 set_gdbarch_deprecated_reg_struct_has_addr
5941 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5942 set_gdbarch_use_struct_convention (gdbarch
,
5943 mips_eabi_use_struct_convention
);
5945 case MIPS_ABI_EABI64
:
5946 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5947 set_gdbarch_deprecated_store_return_value (gdbarch
,
5948 mips_eabi_store_return_value
);
5949 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5950 mips_eabi_extract_return_value
);
5951 tdep
->mips_default_saved_regsize
= 8;
5952 tdep
->mips_default_stack_argsize
= 8;
5953 tdep
->mips_fp_register_double
= 1;
5954 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5955 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5956 tdep
->default_mask_address_p
= 0;
5957 set_gdbarch_long_bit (gdbarch
, 64);
5958 set_gdbarch_ptr_bit (gdbarch
, 64);
5959 set_gdbarch_long_long_bit (gdbarch
, 64);
5960 set_gdbarch_deprecated_reg_struct_has_addr
5961 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5962 set_gdbarch_use_struct_convention (gdbarch
,
5963 mips_eabi_use_struct_convention
);
5966 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5967 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5968 tdep
->mips_default_saved_regsize
= 8;
5969 tdep
->mips_default_stack_argsize
= 8;
5970 tdep
->mips_fp_register_double
= 1;
5971 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5972 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5973 tdep
->default_mask_address_p
= 0;
5974 set_gdbarch_long_bit (gdbarch
, 32);
5975 set_gdbarch_ptr_bit (gdbarch
, 32);
5976 set_gdbarch_long_long_bit (gdbarch
, 64);
5979 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5980 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5981 tdep
->mips_default_saved_regsize
= 8;
5982 tdep
->mips_default_stack_argsize
= 8;
5983 tdep
->mips_fp_register_double
= 1;
5984 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5985 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5986 tdep
->default_mask_address_p
= 0;
5987 set_gdbarch_long_bit (gdbarch
, 64);
5988 set_gdbarch_ptr_bit (gdbarch
, 64);
5989 set_gdbarch_long_long_bit (gdbarch
, 64);
5992 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5995 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5996 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5999 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6000 flag in object files because to do so would make it impossible to
6001 link with libraries compiled without "-gp32". This is
6002 unnecessarily restrictive.
6004 We could solve this problem by adding "-gp32" multilibs to gcc,
6005 but to set this flag before gcc is built with such multilibs will
6006 break too many systems.''
6008 But even more unhelpfully, the default linker output target for
6009 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6010 for 64-bit programs - you need to change the ABI to change this,
6011 and not all gcc targets support that currently. Therefore using
6012 this flag to detect 32-bit mode would do the wrong thing given
6013 the current gcc - it would make GDB treat these 64-bit programs
6014 as 32-bit programs by default. */
6016 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6017 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
6018 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6019 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6021 /* Add/remove bits from an address. The MIPS needs be careful to
6022 ensure that all 32 bit addresses are sign extended to 64 bits. */
6023 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6025 /* There's a mess in stack frame creation. See comments in
6026 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6027 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
,
6028 mips_init_frame_pc_first
);
6030 /* Map debug register numbers onto internal register numbers. */
6031 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6032 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6033 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6034 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6035 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6036 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6037 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6038 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6040 /* Initialize a frame */
6041 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
,
6042 mips_find_saved_regs
);
6043 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
,
6044 mips_init_extra_frame_info
);
6046 /* MIPS version of CALL_DUMMY */
6048 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6049 replaced by a command, and all targets will default to on stack
6050 (regardless of the stack's execute status). */
6051 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6052 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6053 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6054 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
,
6055 generic_save_dummy_frame_tos
);
6057 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6058 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6059 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6061 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6062 set_gdbarch_frameless_function_invocation (gdbarch
,
6063 generic_frameless_function_invocation_not
);
6064 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6065 set_gdbarch_frame_args_skip (gdbarch
, 0);
6067 set_gdbarch_deprecated_get_saved_register (gdbarch
,
6068 mips_get_saved_register
);
6070 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6071 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6073 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6074 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
,
6075 mips_saved_pc_after_call
);
6077 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6078 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6079 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6081 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6083 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6084 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6086 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6088 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6089 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6090 need to all be folded into the target vector. Since they are
6091 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6092 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6094 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6096 /* Hook in OS ABI-specific overrides, if they have been registered. */
6097 gdbarch_init_osabi (info
, gdbarch
);
6099 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6101 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6102 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6108 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6110 struct gdbarch_info info
;
6112 /* Force the architecture to update, and (if it's a MIPS architecture)
6113 mips_gdbarch_init will take care of the rest. */
6114 gdbarch_info_init (&info
);
6115 gdbarch_update_p (info
);
6118 /* Print out which MIPS ABI is in use. */
6121 show_mips_abi (char *ignore_args
, int from_tty
)
6123 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6125 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6128 enum mips_abi global_abi
= global_mips_abi ();
6129 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6130 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6132 if (global_abi
== MIPS_ABI_UNKNOWN
)
6134 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6136 else if (global_abi
== actual_abi
)
6138 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6142 /* Probably shouldn't happen... */
6144 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6145 actual_abi_str
, mips_abi_strings
[global_abi
]);
6151 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6157 int ef_mips_32bitmode
;
6158 /* determine the ISA */
6159 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6177 /* determine the size of a pointer */
6178 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6179 fprintf_unfiltered (file
,
6180 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6182 fprintf_unfiltered (file
,
6183 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6185 fprintf_unfiltered (file
,
6186 "mips_dump_tdep: ef_mips_arch = %d\n",
6188 fprintf_unfiltered (file
,
6189 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6190 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6191 fprintf_unfiltered (file
,
6192 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6193 mips_mask_address_p (tdep
),
6194 tdep
->default_mask_address_p
);
6196 fprintf_unfiltered (file
,
6197 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6198 FP_REGISTER_DOUBLE
);
6199 fprintf_unfiltered (file
,
6200 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6201 MIPS_DEFAULT_FPU_TYPE
,
6202 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6203 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6204 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6206 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6207 fprintf_unfiltered (file
,
6208 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6210 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6211 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6212 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6214 fprintf_unfiltered (file
,
6215 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6216 FP_REGISTER_DOUBLE
);
6217 fprintf_unfiltered (file
,
6218 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6219 mips_stack_argsize (tdep
));
6220 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6221 fprintf_unfiltered (file
,
6222 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6223 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6224 fprintf_unfiltered (file
,
6225 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6226 XSTRING (ATTACH_DETACH
));
6227 fprintf_unfiltered (file
,
6228 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6229 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6232 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6233 fprintf_unfiltered (file
,
6234 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6235 FIRST_EMBED_REGNUM
);
6236 fprintf_unfiltered (file
,
6237 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6238 XSTRING (IGNORE_HELPER_CALL (PC
)));
6239 fprintf_unfiltered (file
,
6240 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6241 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6242 fprintf_unfiltered (file
,
6243 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6244 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6245 fprintf_unfiltered (file
,
6246 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6248 #ifdef MACHINE_CPROC_FP_OFFSET
6249 fprintf_unfiltered (file
,
6250 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6251 MACHINE_CPROC_FP_OFFSET
);
6253 #ifdef MACHINE_CPROC_PC_OFFSET
6254 fprintf_unfiltered (file
,
6255 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6256 MACHINE_CPROC_PC_OFFSET
);
6258 #ifdef MACHINE_CPROC_SP_OFFSET
6259 fprintf_unfiltered (file
,
6260 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6261 MACHINE_CPROC_SP_OFFSET
);
6263 fprintf_unfiltered (file
,
6264 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6266 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6267 fprintf_unfiltered (file
,
6268 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6269 fprintf_unfiltered (file
,
6270 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6271 fprintf_unfiltered (file
,
6272 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6273 MIPS_LAST_ARG_REGNUM
,
6274 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6275 fprintf_unfiltered (file
,
6276 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6277 fprintf_unfiltered (file
,
6278 "mips_dump_tdep: mips_saved_regsize() = %d\n",
6279 mips_saved_regsize (tdep
));
6280 fprintf_unfiltered (file
,
6281 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6282 fprintf_unfiltered (file
,
6283 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6284 fprintf_unfiltered (file
,
6285 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6286 fprintf_unfiltered (file
,
6287 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6288 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6289 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6290 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6291 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6292 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6293 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6294 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6295 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6296 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6297 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6298 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6300 fprintf_unfiltered (file
,
6301 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6304 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6307 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6309 fprintf_unfiltered (file
,
6310 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6311 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6312 fprintf_unfiltered (file
,
6313 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6314 fprintf_unfiltered (file
,
6315 "mips_dump_tdep: SIGFRAME_BASE = %d\n", SIGFRAME_BASE
);
6316 fprintf_unfiltered (file
,
6317 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6318 SIGFRAME_FPREGSAVE_OFF
);
6319 fprintf_unfiltered (file
,
6320 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6322 fprintf_unfiltered (file
,
6323 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6324 SIGFRAME_REGSAVE_OFF
);
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6327 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6328 fprintf_unfiltered (file
,
6329 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6330 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6331 fprintf_unfiltered (file
,
6332 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6333 SOFTWARE_SINGLE_STEP_P ());
6334 fprintf_unfiltered (file
,
6335 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6336 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6337 #ifdef STACK_END_ADDR
6338 fprintf_unfiltered (file
,
6339 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6342 fprintf_unfiltered (file
,
6343 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6344 XSTRING (STEP_SKIPS_DELAY (PC
)));
6345 fprintf_unfiltered (file
,
6346 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6347 STEP_SKIPS_DELAY_P
);
6348 fprintf_unfiltered (file
,
6349 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6350 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6351 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6352 fprintf_unfiltered (file
,
6353 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6354 fprintf_unfiltered (file
,
6355 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6356 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6357 (TYPE
, CNT
, OTHERTYPE
)));
6358 fprintf_unfiltered (file
,
6359 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6360 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6362 fprintf_unfiltered (file
,
6363 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6364 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6367 fprintf_unfiltered (file
,
6368 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6370 #ifdef TRACE_FLAVOR_SIZE
6371 fprintf_unfiltered (file
,
6372 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6376 fprintf_unfiltered (file
,
6377 "mips_dump_tdep: TRACE_SET # %s\n",
6378 XSTRING (TRACE_SET (X
, STATE
)));
6380 #ifdef UNUSED_REGNUM
6381 fprintf_unfiltered (file
,
6382 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6384 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6385 fprintf_unfiltered (file
,
6386 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6387 (long) VM_MIN_ADDRESS
);
6388 fprintf_unfiltered (file
,
6389 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6390 fprintf_unfiltered (file
,
6391 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6394 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6397 _initialize_mips_tdep (void)
6399 static struct cmd_list_element
*mipsfpulist
= NULL
;
6400 struct cmd_list_element
*c
;
6402 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6403 if (MIPS_ABI_LAST
+ 1
6404 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6405 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6407 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6409 /* Add root prefix command for all "set mips"/"show mips" commands */
6410 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6411 "Various MIPS specific commands.",
6412 &setmipscmdlist
, "set mips ", 0, &setlist
);
6414 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6415 "Various MIPS specific commands.",
6416 &showmipscmdlist
, "show mips ", 0, &showlist
);
6418 /* Allow the user to override the saved register size. */
6419 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6422 &mips_saved_regsize_string
, "\
6423 Set size of general purpose registers saved on the stack.\n\
6424 This option can be set to one of:\n\
6425 32 - Force GDB to treat saved GP registers as 32-bit\n\
6426 64 - Force GDB to treat saved GP registers as 64-bit\n\
6427 auto - Allow GDB to use the target's default setting or autodetect the\n\
6428 saved GP register size from information contained in the executable.\n\
6429 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6431 /* Allow the user to override the argument stack size. */
6432 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6435 &mips_stack_argsize_string
, "\
6436 Set the amount of stack space reserved for each argument.\n\
6437 This option can be set to one of:\n\
6438 32 - Force GDB to allocate 32-bit chunks per argument\n\
6439 64 - Force GDB to allocate 64-bit chunks per argument\n\
6440 auto - Allow GDB to determine the correct setting from the current\n\
6441 target and executable (default)", &setmipscmdlist
), &showmipscmdlist
);
6443 /* Allow the user to override the ABI. */
6444 c
= add_set_enum_cmd
6445 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6446 "Set the ABI used by this program.\n"
6447 "This option can be set to one of:\n"
6448 " auto - the default ABI associated with the current binary\n"
6450 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6451 set_cmd_sfunc (c
, mips_abi_update
);
6452 add_cmd ("abi", class_obscure
, show_mips_abi
,
6453 "Show ABI in use by MIPS target", &showmipscmdlist
);
6455 /* Let the user turn off floating point and set the fence post for
6456 heuristic_proc_start. */
6458 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6459 "Set use of MIPS floating-point coprocessor.",
6460 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6461 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6462 "Select single-precision MIPS floating-point coprocessor.",
6464 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6465 "Select double-precision MIPS floating-point coprocessor.",
6467 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6468 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6469 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6470 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6471 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6472 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6473 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6474 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6475 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6476 "Select MIPS floating-point coprocessor automatically.",
6478 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6479 "Show current use of MIPS floating-point coprocessor target.",
6482 /* We really would like to have both "0" and "unlimited" work, but
6483 command.c doesn't deal with that. So make it a var_zinteger
6484 because the user can always use "999999" or some such for unlimited. */
6485 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6486 (char *) &heuristic_fence_post
, "\
6487 Set the distance searched for the start of a function.\n\
6488 If you are debugging a stripped executable, GDB needs to search through the\n\
6489 program for the start of a function. This command sets the distance of the\n\
6490 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6491 /* We need to throw away the frame cache when we set this, since it
6492 might change our ability to get backtraces. */
6493 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6494 add_show_from_set (c
, &showlist
);
6496 /* Allow the user to control whether the upper bits of 64-bit
6497 addresses should be zeroed. */
6498 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6499 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6500 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6501 allow GDB to determine the correct value.\n", "\
6502 Show zeroing of upper 32 bits of 64-bit addresses.",
6503 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6505 /* Allow the user to control the size of 32 bit registers within the
6506 raw remote packet. */
6507 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6508 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6509 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6510 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6511 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6512 64 bits for others. Use \"off\" to disable compatibility mode", "\
6513 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6514 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6515 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6516 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6518 /* Debug this files internals. */
6519 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6520 &mips_debug
, "Set mips debugging.\n\
6521 When non-zero, mips specific debugging is enabled.", &setdebuglist
), &showdebuglist
);