1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
67 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
68 static int mips16_instruction_has_delay_slot (unsigned short inst
,
71 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
73 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
75 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
76 CORE_ADDR addr
, int mustbe32
);
78 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
79 struct frame_info
*, const char *);
81 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
82 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
83 #define ST0_FR (1 << 26)
85 /* The sizes of floating point registers. */
89 MIPS_FPU_SINGLE_REGSIZE
= 4,
90 MIPS_FPU_DOUBLE_REGSIZE
= 8
99 static const char *mips_abi_string
;
101 static const char *const mips_abi_strings
[] = {
112 /* Enum describing the different kinds of breakpoints. */
114 enum mips_breakpoint_kind
116 /* 16-bit MIPS16 mode breakpoint. */
117 MIPS_BP_KIND_MIPS16
= 2,
119 /* 16-bit microMIPS mode breakpoint. */
120 MIPS_BP_KIND_MICROMIPS16
= 3,
122 /* 32-bit standard MIPS mode breakpoint. */
123 MIPS_BP_KIND_MIPS32
= 4,
125 /* 32-bit microMIPS mode breakpoint. */
126 MIPS_BP_KIND_MICROMIPS32
= 5,
129 /* For backwards compatibility we default to MIPS16. This flag is
130 overridden as soon as unambiguous ELF file flags tell us the
131 compressed ISA encoding used. */
132 static const char mips_compression_mips16
[] = "mips16";
133 static const char mips_compression_micromips
[] = "micromips";
134 static const char *const mips_compression_strings
[] =
136 mips_compression_mips16
,
137 mips_compression_micromips
,
141 static const char *mips_compression_string
= mips_compression_mips16
;
143 /* The standard register names, and all the valid aliases for them. */
144 struct register_alias
150 /* Aliases for o32 and most other ABIs. */
151 const struct register_alias mips_o32_aliases
[] = {
158 /* Aliases for n32 and n64. */
159 const struct register_alias mips_n32_n64_aliases
[] = {
166 /* Aliases for ABI-independent registers. */
167 const struct register_alias mips_register_aliases
[] = {
168 /* The architecture manuals specify these ABI-independent names for
170 #define R(n) { "r" #n, n }
171 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
172 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
173 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
174 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
177 /* k0 and k1 are sometimes called these instead (for "kernel
182 /* This is the traditional GDB name for the CP0 status register. */
183 { "sr", MIPS_PS_REGNUM
},
185 /* This is the traditional GDB name for the CP0 BadVAddr register. */
186 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
188 /* This is the traditional GDB name for the FCSR. */
189 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
192 const struct register_alias mips_numeric_register_aliases
[] = {
193 #define R(n) { #n, n }
194 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
195 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
196 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
197 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
201 #ifndef MIPS_DEFAULT_FPU_TYPE
202 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
204 static int mips_fpu_type_auto
= 1;
205 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
207 static unsigned int mips_debug
= 0;
209 /* Properties (for struct target_desc) describing the g/G packet
211 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
212 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
214 struct target_desc
*mips_tdesc_gp32
;
215 struct target_desc
*mips_tdesc_gp64
;
217 const struct mips_regnum
*
218 mips_regnum (struct gdbarch
*gdbarch
)
220 return gdbarch_tdep (gdbarch
)->regnum
;
224 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
226 return mips_regnum (gdbarch
)->fp0
+ 12;
229 /* Return 1 if REGNUM refers to a floating-point general register, raw
230 or cooked. Otherwise return 0. */
233 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
235 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
237 return (rawnum
>= mips_regnum (gdbarch
)->fp0
238 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
241 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
243 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
245 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
246 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
248 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
249 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
251 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
253 /* Return the MIPS ABI associated with GDBARCH. */
255 mips_abi (struct gdbarch
*gdbarch
)
257 return gdbarch_tdep (gdbarch
)->mips_abi
;
261 mips_isa_regsize (struct gdbarch
*gdbarch
)
263 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
265 /* If we know how big the registers are, use that size. */
266 if (tdep
->register_size_valid_p
)
267 return tdep
->register_size
;
269 /* Fall back to the previous behavior. */
270 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
271 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
274 /* Max saved register size. */
275 #define MAX_MIPS_ABI_REGSIZE 8
277 /* Return the currently configured (or set) saved register size. */
280 mips_abi_regsize (struct gdbarch
*gdbarch
)
282 switch (mips_abi (gdbarch
))
284 case MIPS_ABI_EABI32
:
290 case MIPS_ABI_EABI64
:
292 case MIPS_ABI_UNKNOWN
:
295 internal_error (__FILE__
, __LINE__
, _("bad switch"));
299 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
300 are some functions to handle addresses associated with compressed
301 code including but not limited to testing, setting, or clearing
302 bit 0 of such addresses. */
304 /* Return one iff compressed code is the MIPS16 instruction set. */
307 is_mips16_isa (struct gdbarch
*gdbarch
)
309 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
312 /* Return one iff compressed code is the microMIPS instruction set. */
315 is_micromips_isa (struct gdbarch
*gdbarch
)
317 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
320 /* Return one iff ADDR denotes compressed code. */
323 is_compact_addr (CORE_ADDR addr
)
328 /* Return one iff ADDR denotes standard ISA code. */
331 is_mips_addr (CORE_ADDR addr
)
333 return !is_compact_addr (addr
);
336 /* Return one iff ADDR denotes MIPS16 code. */
339 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
341 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
344 /* Return one iff ADDR denotes microMIPS code. */
347 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
349 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
352 /* Strip the ISA (compression) bit off from ADDR. */
355 unmake_compact_addr (CORE_ADDR addr
)
357 return ((addr
) & ~(CORE_ADDR
) 1);
360 /* Add the ISA (compression) bit to ADDR. */
363 make_compact_addr (CORE_ADDR addr
)
365 return ((addr
) | (CORE_ADDR
) 1);
368 /* Extern version of unmake_compact_addr; we use a separate function
369 so that unmake_compact_addr can be inlined throughout this file. */
372 mips_unmake_compact_addr (CORE_ADDR addr
)
374 return unmake_compact_addr (addr
);
377 /* Functions for setting and testing a bit in a minimal symbol that
378 marks it as MIPS16 or microMIPS function. The MSB of the minimal
379 symbol's "info" field is used for this purpose.
381 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
382 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
383 one of the "special" bits in a minimal symbol to mark it accordingly.
384 The test checks an ELF-private flag that is valid for true function
385 symbols only; for synthetic symbols such as for PLT stubs that have
386 no ELF-private part at all the MIPS BFD backend arranges for this
387 information to be carried in the asymbol's udata field instead.
389 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
390 in a minimal symbol. */
393 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
395 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
396 unsigned char st_other
;
398 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
399 st_other
= elfsym
->internal_elf_sym
.st_other
;
400 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
401 st_other
= sym
->udata
.i
;
405 if (ELF_ST_IS_MICROMIPS (st_other
))
407 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
408 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
410 else if (ELF_ST_IS_MIPS16 (st_other
))
412 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
413 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
417 /* Return one iff MSYM refers to standard ISA code. */
420 msymbol_is_mips (struct minimal_symbol
*msym
)
422 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
423 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
426 /* Return one iff MSYM refers to MIPS16 code. */
429 msymbol_is_mips16 (struct minimal_symbol
*msym
)
431 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
434 /* Return one iff MSYM refers to microMIPS code. */
437 msymbol_is_micromips (struct minimal_symbol
*msym
)
439 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
442 /* Set the ISA bit in the main symbol too, complementing the corresponding
443 minimal symbol setting and reflecting the run-time value of the symbol.
444 The need for comes from the ISA bit having been cleared as code in
445 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
446 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
447 of symbols referring to compressed code different in GDB to the values
448 used by actual code. That in turn makes them evaluate incorrectly in
449 expressions, producing results different to what the same expressions
450 yield when compiled into the program being debugged. */
453 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
455 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
457 /* We are in symbol reading so it is OK to cast away constness. */
458 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
459 CORE_ADDR compact_block_start
;
460 struct bound_minimal_symbol msym
;
462 compact_block_start
= BLOCK_START (block
) | 1;
463 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
464 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
466 BLOCK_START (block
) = compact_block_start
;
471 /* XFER a value from the big/little/left end of the register.
472 Depending on the size of the value it might occupy the entire
473 register or just part of it. Make an allowance for this, aligning
474 things accordingly. */
477 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
478 int reg_num
, int length
,
479 enum bfd_endian endian
, gdb_byte
*in
,
480 const gdb_byte
*out
, int buf_offset
)
484 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
485 /* Need to transfer the left or right part of the register, based on
486 the targets byte order. */
490 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
492 case BFD_ENDIAN_LITTLE
:
495 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
499 internal_error (__FILE__
, __LINE__
, _("bad switch"));
502 fprintf_unfiltered (gdb_stderr
,
503 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
504 reg_num
, reg_offset
, buf_offset
, length
);
505 if (mips_debug
&& out
!= NULL
)
508 fprintf_unfiltered (gdb_stdlog
, "out ");
509 for (i
= 0; i
< length
; i
++)
510 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
513 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
515 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
517 if (mips_debug
&& in
!= NULL
)
520 fprintf_unfiltered (gdb_stdlog
, "in ");
521 for (i
= 0; i
< length
; i
++)
522 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
525 fprintf_unfiltered (gdb_stdlog
, "\n");
528 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
529 compatiblity mode. A return value of 1 means that we have
530 physical 64-bit registers, but should treat them as 32-bit registers. */
533 mips2_fp_compat (struct frame_info
*frame
)
535 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
536 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
538 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
542 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
543 in all the places we deal with FP registers. PR gdb/413. */
544 /* Otherwise check the FR bit in the status register - it controls
545 the FP compatiblity mode. If it is clear we are in compatibility
547 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
554 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
556 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
558 /* The list of available "set mips " and "show mips " commands. */
560 static struct cmd_list_element
*setmipscmdlist
= NULL
;
561 static struct cmd_list_element
*showmipscmdlist
= NULL
;
563 /* Integer registers 0 thru 31 are handled explicitly by
564 mips_register_name(). Processor specific registers 32 and above
565 are listed in the following tables. */
568 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
572 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
573 "sr", "lo", "hi", "bad", "cause", "pc",
574 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
575 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
576 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
577 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
581 /* Names of tx39 registers. */
583 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
584 "sr", "lo", "hi", "bad", "cause", "pc",
585 "", "", "", "", "", "", "", "",
586 "", "", "", "", "", "", "", "",
587 "", "", "", "", "", "", "", "",
588 "", "", "", "", "", "", "", "",
590 "", "", "", "", "", "", "", "",
591 "", "", "config", "cache", "debug", "depc", "epc",
594 /* Names of registers with Linux kernels. */
595 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
596 "sr", "lo", "hi", "bad", "cause", "pc",
597 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
598 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
599 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
600 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
605 /* Return the name of the register corresponding to REGNO. */
607 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
609 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
610 /* GPR names for all ABIs other than n32/n64. */
611 static const char *mips_gpr_names
[] = {
612 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
613 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
614 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
615 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
618 /* GPR names for n32 and n64 ABIs. */
619 static const char *mips_n32_n64_gpr_names
[] = {
620 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
621 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
622 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
623 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
626 enum mips_abi abi
= mips_abi (gdbarch
);
628 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
629 but then don't make the raw register names visible. This (upper)
630 range of user visible register numbers are the pseudo-registers.
632 This approach was adopted accommodate the following scenario:
633 It is possible to debug a 64-bit device using a 32-bit
634 programming model. In such instances, the raw registers are
635 configured to be 64-bits wide, while the pseudo registers are
636 configured to be 32-bits wide. The registers that the user
637 sees - the pseudo registers - match the users expectations
638 given the programming model being used. */
639 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
640 if (regno
< gdbarch_num_regs (gdbarch
))
643 /* The MIPS integer registers are always mapped from 0 to 31. The
644 names of the registers (which reflects the conventions regarding
645 register use) vary depending on the ABI. */
646 if (0 <= rawnum
&& rawnum
< 32)
648 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
649 return mips_n32_n64_gpr_names
[rawnum
];
651 return mips_gpr_names
[rawnum
];
653 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
654 return tdesc_register_name (gdbarch
, rawnum
);
655 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
657 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
658 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
659 return tdep
->mips_processor_reg_names
[rawnum
- 32];
663 internal_error (__FILE__
, __LINE__
,
664 _("mips_register_name: bad register number %d"), rawnum
);
667 /* Return the groups that a MIPS register can be categorised into. */
670 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
671 struct reggroup
*reggroup
)
676 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
677 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
678 if (reggroup
== all_reggroup
)
680 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
681 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
682 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
683 (gdbarch), as not all architectures are multi-arch. */
684 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
685 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
686 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
688 if (reggroup
== float_reggroup
)
689 return float_p
&& pseudo
;
690 if (reggroup
== vector_reggroup
)
691 return vector_p
&& pseudo
;
692 if (reggroup
== general_reggroup
)
693 return (!vector_p
&& !float_p
) && pseudo
;
694 /* Save the pseudo registers. Need to make certain that any code
695 extracting register values from a saved register cache also uses
697 if (reggroup
== save_reggroup
)
698 return raw_p
&& pseudo
;
699 /* Restore the same pseudo register. */
700 if (reggroup
== restore_reggroup
)
701 return raw_p
&& pseudo
;
705 /* Return the groups that a MIPS register can be categorised into.
706 This version is only used if we have a target description which
707 describes real registers (and their groups). */
710 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
711 struct reggroup
*reggroup
)
713 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
714 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
717 /* Only save, restore, and display the pseudo registers. Need to
718 make certain that any code extracting register values from a
719 saved register cache also uses pseudo registers.
721 Note: saving and restoring the pseudo registers is slightly
722 strange; if we have 64 bits, we should save and restore all
723 64 bits. But this is hard and has little benefit. */
727 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
731 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
734 /* Map the symbol table registers which live in the range [1 *
735 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
736 registers. Take care of alignment and size problems. */
738 static enum register_status
739 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
740 int cookednum
, gdb_byte
*buf
)
742 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
743 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
744 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
745 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
746 return regcache
->raw_read (rawnum
, buf
);
747 else if (register_size (gdbarch
, rawnum
) >
748 register_size (gdbarch
, cookednum
))
750 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
751 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
754 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
756 enum register_status status
;
758 status
= regcache
->raw_read (rawnum
, ®val
);
759 if (status
== REG_VALID
)
760 store_signed_integer (buf
, 4, byte_order
, regval
);
765 internal_error (__FILE__
, __LINE__
, _("bad register size"));
769 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
770 struct regcache
*regcache
, int cookednum
,
773 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
774 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
775 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
776 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
777 regcache
->raw_write (rawnum
, buf
);
778 else if (register_size (gdbarch
, rawnum
) >
779 register_size (gdbarch
, cookednum
))
781 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
782 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
785 /* Sign extend the shortened version of the register prior
786 to placing it in the raw register. This is required for
787 some mips64 parts in order to avoid unpredictable behavior. */
788 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
789 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
790 regcache_raw_write_signed (regcache
, rawnum
, regval
);
794 internal_error (__FILE__
, __LINE__
, _("bad register size"));
798 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
799 struct agent_expr
*ax
, int reg
)
801 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
802 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
803 && reg
< 2 * gdbarch_num_regs (gdbarch
));
805 ax_reg_mask (ax
, rawnum
);
811 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
812 struct agent_expr
*ax
, int reg
)
814 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
815 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
816 && reg
< 2 * gdbarch_num_regs (gdbarch
));
817 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
821 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
823 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
824 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
827 ax_simple (ax
, aop_lsh
);
830 ax_simple (ax
, aop_rsh_signed
);
834 internal_error (__FILE__
, __LINE__
, _("bad register size"));
839 /* Table to translate 3-bit register field to actual register number. */
840 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
842 /* Heuristic_proc_start may hunt through the text section for a long
843 time across a 2400 baud serial line. Allows the user to limit this
846 static int heuristic_fence_post
= 0;
848 /* Number of bytes of storage in the actual machine representation for
849 register N. NOTE: This defines the pseudo register type so need to
850 rebuild the architecture vector. */
852 static int mips64_transfers_32bit_regs_p
= 0;
855 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
856 struct cmd_list_element
*c
)
858 struct gdbarch_info info
;
859 gdbarch_info_init (&info
);
860 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
861 instead of relying on globals. Doing that would let generic code
862 handle the search for this specific architecture. */
863 if (!gdbarch_update_p (info
))
865 mips64_transfers_32bit_regs_p
= 0;
866 error (_("32-bit compatibility mode not supported"));
870 /* Convert to/from a register and the corresponding memory value. */
872 /* This predicate tests for the case of an 8 byte floating point
873 value that is being transferred to or from a pair of floating point
874 registers each of which are (or are considered to be) only 4 bytes
877 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
880 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
881 && register_size (gdbarch
, regnum
) == 4
882 && mips_float_register_p (gdbarch
, regnum
)
883 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
886 /* This predicate tests for the case of a value of less than 8
887 bytes in width that is being transfered to or from an 8 byte
888 general purpose register. */
890 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
893 int num_regs
= gdbarch_num_regs (gdbarch
);
895 return (register_size (gdbarch
, regnum
) == 8
896 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
897 && TYPE_LENGTH (type
) < 8);
901 mips_convert_register_p (struct gdbarch
*gdbarch
,
902 int regnum
, struct type
*type
)
904 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
905 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
909 mips_register_to_value (struct frame_info
*frame
, int regnum
,
910 struct type
*type
, gdb_byte
*to
,
911 int *optimizedp
, int *unavailablep
)
913 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
915 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
917 get_frame_register (frame
, regnum
+ 0, to
+ 4);
918 get_frame_register (frame
, regnum
+ 1, to
+ 0);
920 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
921 optimizedp
, unavailablep
))
924 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
925 optimizedp
, unavailablep
))
927 *optimizedp
= *unavailablep
= 0;
930 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
932 int len
= TYPE_LENGTH (type
);
935 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
936 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
937 optimizedp
, unavailablep
))
940 *optimizedp
= *unavailablep
= 0;
945 internal_error (__FILE__
, __LINE__
,
946 _("mips_register_to_value: unrecognized case"));
951 mips_value_to_register (struct frame_info
*frame
, int regnum
,
952 struct type
*type
, const gdb_byte
*from
)
954 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
956 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
958 put_frame_register (frame
, regnum
+ 0, from
+ 4);
959 put_frame_register (frame
, regnum
+ 1, from
+ 0);
961 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
964 int len
= TYPE_LENGTH (type
);
966 /* Sign extend values, irrespective of type, that are stored to
967 a 64-bit general purpose register. (32-bit unsigned values
968 are stored as signed quantities within a 64-bit register.
969 When performing an operation, in compiled code, that combines
970 a 32-bit unsigned value with a signed 64-bit value, a type
971 conversion is first performed that zeroes out the high 32 bits.) */
972 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
975 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
977 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
978 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
979 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
983 if (from
[len
-1] & 0x80)
984 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
986 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
987 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
988 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
993 internal_error (__FILE__
, __LINE__
,
994 _("mips_value_to_register: unrecognized case"));
998 /* Return the GDB type object for the "standard" data type of data in
1001 static struct type
*
1002 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1004 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1005 if (mips_float_register_p (gdbarch
, regnum
))
1007 /* The floating-point registers raw, or cooked, always match
1008 mips_isa_regsize(), and also map 1:1, byte for byte. */
1009 if (mips_isa_regsize (gdbarch
) == 4)
1010 return builtin_type (gdbarch
)->builtin_float
;
1012 return builtin_type (gdbarch
)->builtin_double
;
1014 else if (regnum
< gdbarch_num_regs (gdbarch
))
1016 /* The raw or ISA registers. These are all sized according to
1018 if (mips_isa_regsize (gdbarch
) == 4)
1019 return builtin_type (gdbarch
)->builtin_int32
;
1021 return builtin_type (gdbarch
)->builtin_int64
;
1025 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1027 /* The cooked or ABI registers. These are sized according to
1028 the ABI (with a few complications). */
1029 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1030 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1031 return builtin_type (gdbarch
)->builtin_int32
;
1032 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1033 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1034 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1035 /* The pseudo/cooked view of the embedded registers is always
1036 32-bit. The raw view is handled below. */
1037 return builtin_type (gdbarch
)->builtin_int32
;
1038 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1039 /* The target, while possibly using a 64-bit register buffer,
1040 is only transfering 32-bits of each integer register.
1041 Reflect this in the cooked/pseudo (ABI) register value. */
1042 return builtin_type (gdbarch
)->builtin_int32
;
1043 else if (mips_abi_regsize (gdbarch
) == 4)
1044 /* The ABI is restricted to 32-bit registers (the ISA could be
1046 return builtin_type (gdbarch
)->builtin_int32
;
1049 return builtin_type (gdbarch
)->builtin_int64
;
1053 /* Return the GDB type for the pseudo register REGNUM, which is the
1054 ABI-level view. This function is only called if there is a target
1055 description which includes registers, so we know precisely the
1056 types of hardware registers. */
1058 static struct type
*
1059 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1061 const int num_regs
= gdbarch_num_regs (gdbarch
);
1062 int rawnum
= regnum
% num_regs
;
1063 struct type
*rawtype
;
1065 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1067 /* Absent registers are still absent. */
1068 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1069 if (TYPE_LENGTH (rawtype
) == 0)
1072 /* Present the floating point registers however the hardware did;
1073 do not try to convert between FPU layouts. */
1074 if (mips_float_register_p (gdbarch
, rawnum
))
1077 /* Floating-point control registers are always 32-bit even though for
1078 backwards compatibility reasons 64-bit targets will transfer them
1079 as 64-bit quantities even if using XML descriptions. */
1080 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1081 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1082 return builtin_type (gdbarch
)->builtin_int32
;
1084 /* Use pointer types for registers if we can. For n32 we can not,
1085 since we do not have a 64-bit pointer type. */
1086 if (mips_abi_regsize (gdbarch
)
1087 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1089 if (rawnum
== MIPS_SP_REGNUM
1090 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1091 return builtin_type (gdbarch
)->builtin_data_ptr
;
1092 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1093 return builtin_type (gdbarch
)->builtin_func_ptr
;
1096 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1097 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1098 || rawnum
== mips_regnum (gdbarch
)->lo
1099 || rawnum
== mips_regnum (gdbarch
)->hi
1100 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1101 || rawnum
== mips_regnum (gdbarch
)->cause
1102 || rawnum
== mips_regnum (gdbarch
)->pc
1103 || (mips_regnum (gdbarch
)->dspacc
!= -1
1104 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1105 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1106 return builtin_type (gdbarch
)->builtin_int32
;
1108 /* The pseudo/cooked view of embedded registers is always
1109 32-bit, even if the target transfers 64-bit values for them.
1110 New targets relying on XML descriptions should only transfer
1111 the necessary 32 bits, but older versions of GDB expected 64,
1112 so allow the target to provide 64 bits without interfering
1113 with the displayed type. */
1114 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1115 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1116 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1117 return builtin_type (gdbarch
)->builtin_int32
;
1119 /* For all other registers, pass through the hardware type. */
1123 /* Should the upper word of 64-bit addresses be zeroed? */
1124 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1127 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1129 switch (mask_address_var
)
1131 case AUTO_BOOLEAN_TRUE
:
1133 case AUTO_BOOLEAN_FALSE
:
1136 case AUTO_BOOLEAN_AUTO
:
1137 return tdep
->default_mask_address_p
;
1139 internal_error (__FILE__
, __LINE__
,
1140 _("mips_mask_address_p: bad switch"));
1146 show_mask_address (struct ui_file
*file
, int from_tty
,
1147 struct cmd_list_element
*c
, const char *value
)
1149 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1151 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1152 switch (mask_address_var
)
1154 case AUTO_BOOLEAN_TRUE
:
1155 printf_filtered ("The 32 bit mips address mask is enabled\n");
1157 case AUTO_BOOLEAN_FALSE
:
1158 printf_filtered ("The 32 bit mips address mask is disabled\n");
1160 case AUTO_BOOLEAN_AUTO
:
1162 ("The 32 bit address mask is set automatically. Currently %s\n",
1163 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1166 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1171 /* Tell if the program counter value in MEMADDR is in a standard ISA
1175 mips_pc_is_mips (CORE_ADDR memaddr
)
1177 struct bound_minimal_symbol sym
;
1179 /* Flags indicating that this is a MIPS16 or microMIPS function is
1180 stored by elfread.c in the high bit of the info field. Use this
1181 to decide if the function is standard MIPS. Otherwise if bit 0
1182 of the address is clear, then this is a standard MIPS function. */
1183 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1185 return msymbol_is_mips (sym
.minsym
);
1187 return is_mips_addr (memaddr
);
1190 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1193 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1195 struct bound_minimal_symbol sym
;
1197 /* A flag indicating that this is a MIPS16 function is stored by
1198 elfread.c in the high bit of the info field. Use this to decide
1199 if the function is MIPS16. Otherwise if bit 0 of the address is
1200 set, then ELF file flags will tell if this is a MIPS16 function. */
1201 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1203 return msymbol_is_mips16 (sym
.minsym
);
1205 return is_mips16_addr (gdbarch
, memaddr
);
1208 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1211 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1213 struct bound_minimal_symbol sym
;
1215 /* A flag indicating that this is a microMIPS function is stored by
1216 elfread.c in the high bit of the info field. Use this to decide
1217 if the function is microMIPS. Otherwise if bit 0 of the address
1218 is set, then ELF file flags will tell if this is a microMIPS
1220 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1222 return msymbol_is_micromips (sym
.minsym
);
1224 return is_micromips_addr (gdbarch
, memaddr
);
1227 /* Tell the ISA type of the function the program counter value in MEMADDR
1230 static enum mips_isa
1231 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1233 struct bound_minimal_symbol sym
;
1235 /* A flag indicating that this is a MIPS16 or a microMIPS function
1236 is stored by elfread.c in the high bit of the info field. Use
1237 this to decide if the function is MIPS16 or microMIPS or normal
1238 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1239 flags will tell if this is a MIPS16 or a microMIPS function. */
1240 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1243 if (msymbol_is_micromips (sym
.minsym
))
1244 return ISA_MICROMIPS
;
1245 else if (msymbol_is_mips16 (sym
.minsym
))
1252 if (is_mips_addr (memaddr
))
1254 else if (is_micromips_addr (gdbarch
, memaddr
))
1255 return ISA_MICROMIPS
;
1261 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1262 The need for comes from the ISA bit having been cleared, making
1263 addresses in FDE, range records, etc. referring to compressed code
1264 different to those in line information, the symbol table and finally
1265 the PC register. That in turn confuses many operations. */
1268 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1270 pc
= unmake_compact_addr (pc
);
1271 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1274 /* Recalculate the line record requested so that the resulting PC has
1275 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1276 this adjustment comes from some records associated with compressed
1277 code having the ISA bit cleared, most notably at function prologue
1278 ends. The ISA bit is in this context retrieved from the minimal
1279 symbol covering the address requested, which in turn has been
1280 constructed from the binary's symbol table rather than DWARF-2
1281 information. The correct setting of the ISA bit is required for
1282 breakpoint addresses to correctly match against the stop PC.
1284 As line entries can specify relative address adjustments we need to
1285 keep track of the absolute value of the last line address recorded
1286 in line information, so that we can calculate the actual address to
1287 apply the ISA bit adjustment to. We use PC for this tracking and
1288 keep the original address there.
1290 As such relative address adjustments can be odd within compressed
1291 code we need to keep track of the last line address with the ISA
1292 bit adjustment applied too, as the original address may or may not
1293 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1294 the adjusted address there.
1296 For relative address adjustments we then use these variables to
1297 calculate the address intended by line information, which will be
1298 PC-relative, and return an updated adjustment carrying ISA bit
1299 information, which will be ADJ_PC-relative. For absolute address
1300 adjustments we just return the same address that we store in ADJ_PC
1303 As the first line entry can be relative to an implied address value
1304 of 0 we need to have the initial address set up that we store in PC
1305 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1306 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1309 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1311 static CORE_ADDR adj_pc
;
1312 static CORE_ADDR pc
;
1315 pc
= rel
? pc
+ addr
: addr
;
1316 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1317 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1322 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1324 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1325 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1326 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1327 static const char mips_str_call_stub
[] = "__call_stub_";
1328 static const char mips_str_fn_stub
[] = "__fn_stub_";
1330 /* This is used as a PIC thunk prefix. */
1332 static const char mips_str_pic
[] = ".pic.";
1334 /* Return non-zero if the PC is inside a call thunk (aka stub or
1335 trampoline) that should be treated as a temporary frame. */
1338 mips_in_frame_stub (CORE_ADDR pc
)
1340 CORE_ADDR start_addr
;
1343 /* Find the starting address of the function containing the PC. */
1344 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1347 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1348 if (startswith (name
, mips_str_mips16_call_stub
))
1350 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1351 if (startswith (name
, mips_str_call_stub
))
1353 /* If the PC is in __fn_stub_*, this is a call stub. */
1354 if (startswith (name
, mips_str_fn_stub
))
1357 return 0; /* Not a stub. */
1360 /* MIPS believes that the PC has a sign extended value. Perhaps the
1361 all registers should be sign extended for simplicity? */
1364 mips_read_pc (readable_regcache
*regcache
)
1366 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1369 regcache
->cooked_read (regnum
, &pc
);
1374 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1378 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1379 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1380 intermediate frames. In this case we can get the caller's address
1381 from $ra, or if $ra contains an address within a thunk as well, then
1382 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1383 and thus the caller's address is in $s2. */
1384 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1386 pc
= frame_unwind_register_signed
1387 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1388 if (mips_in_frame_stub (pc
))
1389 pc
= frame_unwind_register_signed
1390 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1396 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1398 return frame_unwind_register_signed
1399 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1402 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1403 dummy frame. The frame ID's base needs to match the TOS value
1404 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1407 static struct frame_id
1408 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1410 return frame_id_build
1411 (get_frame_register_signed (this_frame
,
1412 gdbarch_num_regs (gdbarch
)
1414 get_frame_pc (this_frame
));
1417 /* Implement the "write_pc" gdbarch method. */
1420 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1422 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1424 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1427 /* Fetch and return instruction from the specified location. Handle
1428 MIPS16/microMIPS as appropriate. */
1431 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1432 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1434 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1435 gdb_byte buf
[MIPS_INSN32_SIZE
];
1443 instlen
= MIPS_INSN16_SIZE
;
1444 addr
= unmake_compact_addr (addr
);
1447 instlen
= MIPS_INSN32_SIZE
;
1450 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1453 err
= target_read_memory (addr
, buf
, instlen
);
1459 memory_error (TARGET_XFER_E_IO
, addr
);
1462 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1465 /* These are the fields of 32 bit mips instructions. */
1466 #define mips32_op(x) (x >> 26)
1467 #define itype_op(x) (x >> 26)
1468 #define itype_rs(x) ((x >> 21) & 0x1f)
1469 #define itype_rt(x) ((x >> 16) & 0x1f)
1470 #define itype_immediate(x) (x & 0xffff)
1472 #define jtype_op(x) (x >> 26)
1473 #define jtype_target(x) (x & 0x03ffffff)
1475 #define rtype_op(x) (x >> 26)
1476 #define rtype_rs(x) ((x >> 21) & 0x1f)
1477 #define rtype_rt(x) ((x >> 16) & 0x1f)
1478 #define rtype_rd(x) ((x >> 11) & 0x1f)
1479 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1480 #define rtype_funct(x) (x & 0x3f)
1482 /* MicroMIPS instruction fields. */
1483 #define micromips_op(x) ((x) >> 10)
1485 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1486 bit and the size respectively of the field extracted. */
1487 #define b0s4_imm(x) ((x) & 0xf)
1488 #define b0s5_imm(x) ((x) & 0x1f)
1489 #define b0s5_reg(x) ((x) & 0x1f)
1490 #define b0s7_imm(x) ((x) & 0x7f)
1491 #define b0s10_imm(x) ((x) & 0x3ff)
1492 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1493 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1494 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1495 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1496 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1497 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1498 #define b6s4_op(x) (((x) >> 6) & 0xf)
1499 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1501 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1502 respectively of the field extracted. */
1503 #define b0s6_op(x) ((x) & 0x3f)
1504 #define b0s11_op(x) ((x) & 0x7ff)
1505 #define b0s12_imm(x) ((x) & 0xfff)
1506 #define b0s16_imm(x) ((x) & 0xffff)
1507 #define b0s26_imm(x) ((x) & 0x3ffffff)
1508 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1509 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1510 #define b12s4_op(x) (((x) >> 12) & 0xf)
1512 /* Return the size in bytes of the instruction INSN encoded in the ISA
1516 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1521 if ((micromips_op (insn
) & 0x4) == 0x4
1522 || (micromips_op (insn
) & 0x7) == 0x0)
1523 return 2 * MIPS_INSN16_SIZE
;
1525 return MIPS_INSN16_SIZE
;
1527 if ((insn
& 0xf800) == 0xf000)
1528 return 2 * MIPS_INSN16_SIZE
;
1530 return MIPS_INSN16_SIZE
;
1532 return MIPS_INSN32_SIZE
;
1534 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1538 mips32_relative_offset (ULONGEST inst
)
1540 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1543 /* Determine the address of the next instruction executed after the INST
1544 floating condition branch instruction at PC. COUNT specifies the
1545 number of the floating condition bits tested by the branch. */
1548 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1549 ULONGEST inst
, CORE_ADDR pc
, int count
)
1551 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1552 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1553 int tf
= itype_rt (inst
) & 1;
1554 int mask
= (1 << count
) - 1;
1559 /* No way to handle; it'll most likely trap anyway. */
1562 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1563 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1565 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1566 pc
+= mips32_relative_offset (inst
);
1573 /* Return nonzero if the gdbarch is an Octeon series. */
1576 is_octeon (struct gdbarch
*gdbarch
)
1578 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1580 return (info
->mach
== bfd_mach_mips_octeon
1581 || info
->mach
== bfd_mach_mips_octeonp
1582 || info
->mach
== bfd_mach_mips_octeon2
);
1585 /* Return true if the OP represents the Octeon's BBIT instruction. */
1588 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1590 if (!is_octeon (gdbarch
))
1592 /* BBIT0 is encoded as LWC2: 110 010. */
1593 /* BBIT032 is encoded as LDC2: 110 110. */
1594 /* BBIT1 is encoded as SWC2: 111 010. */
1595 /* BBIT132 is encoded as SDC2: 111 110. */
1596 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1602 /* Determine where to set a single step breakpoint while considering
1603 branch prediction. */
1606 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1608 struct gdbarch
*gdbarch
= regcache
->arch ();
1611 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1612 op
= itype_op (inst
);
1613 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1617 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1628 goto greater_branch
;
1633 else if (op
== 17 && itype_rs (inst
) == 8)
1634 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1635 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1636 else if (op
== 17 && itype_rs (inst
) == 9
1637 && (itype_rt (inst
) & 2) == 0)
1638 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1639 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1640 else if (op
== 17 && itype_rs (inst
) == 10
1641 && (itype_rt (inst
) & 2) == 0)
1642 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1643 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1646 /* The new PC will be alternate mode. */
1650 reg
= jtype_target (inst
) << 2;
1651 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1652 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1654 else if (is_octeon_bbit_op (op
, gdbarch
))
1658 branch_if
= op
== 58 || op
== 62;
1659 bit
= itype_rt (inst
);
1661 /* Take into account the *32 instructions. */
1662 if (op
== 54 || op
== 62)
1665 if (((regcache_raw_get_signed (regcache
,
1666 itype_rs (inst
)) >> bit
) & 1)
1668 pc
+= mips32_relative_offset (inst
) + 4;
1670 pc
+= 8; /* After the delay slot. */
1674 pc
+= 4; /* Not a branch, next instruction is easy. */
1677 { /* This gets way messy. */
1679 /* Further subdivide into SPECIAL, REGIMM and other. */
1680 switch (op
& 0x07) /* Extract bits 28,27,26. */
1682 case 0: /* SPECIAL */
1683 op
= rtype_funct (inst
);
1688 /* Set PC to that address. */
1689 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1691 case 12: /* SYSCALL */
1693 struct gdbarch_tdep
*tdep
;
1695 tdep
= gdbarch_tdep (gdbarch
);
1696 if (tdep
->syscall_next_pc
!= NULL
)
1697 pc
= tdep
->syscall_next_pc (get_current_frame ());
1706 break; /* end SPECIAL */
1707 case 1: /* REGIMM */
1709 op
= itype_rt (inst
); /* branch condition */
1714 case 16: /* BLTZAL */
1715 case 18: /* BLTZALL */
1717 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1718 pc
+= mips32_relative_offset (inst
) + 4;
1720 pc
+= 8; /* after the delay slot */
1724 case 17: /* BGEZAL */
1725 case 19: /* BGEZALL */
1726 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1727 pc
+= mips32_relative_offset (inst
) + 4;
1729 pc
+= 8; /* after the delay slot */
1731 case 0x1c: /* BPOSGE32 */
1732 case 0x1e: /* BPOSGE64 */
1734 if (itype_rs (inst
) == 0)
1736 unsigned int pos
= (op
& 2) ? 64 : 32;
1737 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1740 /* No way to handle; it'll most likely trap anyway. */
1743 if ((regcache_raw_get_unsigned (regcache
,
1744 dspctl
) & 0x7f) >= pos
)
1745 pc
+= mips32_relative_offset (inst
);
1750 /* All of the other instructions in the REGIMM category */
1755 break; /* end REGIMM */
1760 reg
= jtype_target (inst
) << 2;
1761 /* Upper four bits get never changed... */
1762 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1765 case 4: /* BEQ, BEQL */
1767 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1768 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1769 pc
+= mips32_relative_offset (inst
) + 4;
1773 case 5: /* BNE, BNEL */
1775 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1776 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1777 pc
+= mips32_relative_offset (inst
) + 4;
1781 case 6: /* BLEZ, BLEZL */
1782 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1783 pc
+= mips32_relative_offset (inst
) + 4;
1789 greater_branch
: /* BGTZ, BGTZL */
1790 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1791 pc
+= mips32_relative_offset (inst
) + 4;
1798 } /* mips32_next_pc */
1800 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1804 micromips_relative_offset7 (ULONGEST insn
)
1806 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1809 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1813 micromips_relative_offset10 (ULONGEST insn
)
1815 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1818 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1822 micromips_relative_offset16 (ULONGEST insn
)
1824 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1827 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1830 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1834 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1835 return mips_insn_size (ISA_MICROMIPS
, insn
);
1838 /* Calculate the address of the next microMIPS instruction to execute
1839 after the INSN coprocessor 1 conditional branch instruction at the
1840 address PC. COUNT denotes the number of coprocessor condition bits
1841 examined by the branch. */
1844 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1845 ULONGEST insn
, CORE_ADDR pc
, int count
)
1847 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1848 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1849 int tf
= b5s5_op (insn
>> 16) & 1;
1850 int mask
= (1 << count
) - 1;
1855 /* No way to handle; it'll most likely trap anyway. */
1858 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1859 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1861 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1862 pc
+= micromips_relative_offset16 (insn
);
1864 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1869 /* Calculate the address of the next microMIPS instruction to execute
1870 after the instruction at the address PC. */
1873 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1875 struct gdbarch
*gdbarch
= regcache
->arch ();
1878 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1879 pc
+= MIPS_INSN16_SIZE
;
1880 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1882 /* 32-bit instructions. */
1883 case 2 * MIPS_INSN16_SIZE
:
1885 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1886 pc
+= MIPS_INSN16_SIZE
;
1887 switch (micromips_op (insn
>> 16))
1889 case 0x00: /* POOL32A: bits 000000 */
1890 if (b0s6_op (insn
) == 0x3c
1891 /* POOL32Axf: bits 000000 ... 111100 */
1892 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1893 /* JALR, JALR.HB: 000000 000x111100 111100 */
1894 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1895 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16));
1898 case 0x10: /* POOL32I: bits 010000 */
1899 switch (b5s5_op (insn
>> 16))
1901 case 0x00: /* BLTZ: bits 010000 00000 */
1902 case 0x01: /* BLTZAL: bits 010000 00001 */
1903 case 0x11: /* BLTZALS: bits 010000 10001 */
1904 if (regcache_raw_get_signed (regcache
,
1905 b0s5_reg (insn
>> 16)) < 0)
1906 pc
+= micromips_relative_offset16 (insn
);
1908 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1911 case 0x02: /* BGEZ: bits 010000 00010 */
1912 case 0x03: /* BGEZAL: bits 010000 00011 */
1913 case 0x13: /* BGEZALS: bits 010000 10011 */
1914 if (regcache_raw_get_signed (regcache
,
1915 b0s5_reg (insn
>> 16)) >= 0)
1916 pc
+= micromips_relative_offset16 (insn
);
1918 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1921 case 0x04: /* BLEZ: bits 010000 00100 */
1922 if (regcache_raw_get_signed (regcache
,
1923 b0s5_reg (insn
>> 16)) <= 0)
1924 pc
+= micromips_relative_offset16 (insn
);
1926 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1929 case 0x05: /* BNEZC: bits 010000 00101 */
1930 if (regcache_raw_get_signed (regcache
,
1931 b0s5_reg (insn
>> 16)) != 0)
1932 pc
+= micromips_relative_offset16 (insn
);
1935 case 0x06: /* BGTZ: bits 010000 00110 */
1936 if (regcache_raw_get_signed (regcache
,
1937 b0s5_reg (insn
>> 16)) > 0)
1938 pc
+= micromips_relative_offset16 (insn
);
1940 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1943 case 0x07: /* BEQZC: bits 010000 00111 */
1944 if (regcache_raw_get_signed (regcache
,
1945 b0s5_reg (insn
>> 16)) == 0)
1946 pc
+= micromips_relative_offset16 (insn
);
1949 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1950 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1951 if (((insn
>> 16) & 0x3) == 0x0)
1952 /* BC2F, BC2T: don't know how to handle these. */
1956 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1957 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1959 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1960 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1963 /* No way to handle; it'll most likely trap anyway. */
1966 if ((regcache_raw_get_unsigned (regcache
,
1967 dspctl
) & 0x7f) >= pos
)
1968 pc
+= micromips_relative_offset16 (insn
);
1970 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1974 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1975 /* BC1ANY2F: bits 010000 11100 xxx01 */
1976 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1977 /* BC1ANY2T: bits 010000 11101 xxx01 */
1978 if (((insn
>> 16) & 0x2) == 0x0)
1979 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
1980 ((insn
>> 16) & 0x1) + 1);
1983 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1984 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1985 if (((insn
>> 16) & 0x3) == 0x1)
1986 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
1991 case 0x1d: /* JALS: bits 011101 */
1992 case 0x35: /* J: bits 110101 */
1993 case 0x3d: /* JAL: bits 111101 */
1994 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1997 case 0x25: /* BEQ: bits 100101 */
1998 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
1999 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2000 pc
+= micromips_relative_offset16 (insn
);
2002 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2005 case 0x2d: /* BNE: bits 101101 */
2006 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2007 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2008 pc
+= micromips_relative_offset16 (insn
);
2010 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2013 case 0x3c: /* JALX: bits 111100 */
2014 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2019 /* 16-bit instructions. */
2020 case MIPS_INSN16_SIZE
:
2021 switch (micromips_op (insn
))
2023 case 0x11: /* POOL16C: bits 010001 */
2024 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2025 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2026 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2027 else if (b5s5_op (insn
) == 0x18)
2028 /* JRADDIUSP: bits 010001 11000 */
2029 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2032 case 0x23: /* BEQZ16: bits 100011 */
2034 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2036 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2037 pc
+= micromips_relative_offset7 (insn
);
2039 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2043 case 0x2b: /* BNEZ16: bits 101011 */
2045 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2047 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2048 pc
+= micromips_relative_offset7 (insn
);
2050 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2054 case 0x33: /* B16: bits 110011 */
2055 pc
+= micromips_relative_offset10 (insn
);
2064 /* Decoding the next place to set a breakpoint is irregular for the
2065 mips 16 variant, but fortunately, there fewer instructions. We have
2066 to cope ith extensions for 16 bit instructions and a pair of actual
2067 32 bit instructions. We dont want to set a single step instruction
2068 on the extend instruction either. */
2070 /* Lots of mips16 instruction formats */
2071 /* Predicting jumps requires itype,ritype,i8type
2072 and their extensions extItype,extritype,extI8type. */
2073 enum mips16_inst_fmts
2075 itype
, /* 0 immediate 5,10 */
2076 ritype
, /* 1 5,3,8 */
2077 rrtype
, /* 2 5,3,3,5 */
2078 rritype
, /* 3 5,3,3,5 */
2079 rrrtype
, /* 4 5,3,3,3,2 */
2080 rriatype
, /* 5 5,3,3,1,4 */
2081 shifttype
, /* 6 5,3,3,3,2 */
2082 i8type
, /* 7 5,3,8 */
2083 i8movtype
, /* 8 5,3,3,5 */
2084 i8mov32rtype
, /* 9 5,3,5,3 */
2085 i64type
, /* 10 5,3,8 */
2086 ri64type
, /* 11 5,3,3,5 */
2087 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2088 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2089 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2090 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2091 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2092 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2093 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2094 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2095 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2096 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2098 /* I am heaping all the fields of the formats into one structure and
2099 then, only the fields which are involved in instruction extension. */
2103 unsigned int regx
; /* Function in i8 type. */
2108 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2109 for the bits which make up the immediate extension. */
2112 extended_offset (unsigned int extension
)
2116 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2118 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2120 value
|= extension
& 0x1f; /* Extract 4:0. */
2125 /* Only call this function if you know that this is an extendable
2126 instruction. It won't malfunction, but why make excess remote memory
2127 references? If the immediate operands get sign extended or something,
2128 do it after the extension is performed. */
2129 /* FIXME: Every one of these cases needs to worry about sign extension
2130 when the offset is to be used in relative addressing. */
2133 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2135 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2138 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2139 target_read_memory (pc
, buf
, 2);
2140 return extract_unsigned_integer (buf
, 2, byte_order
);
2144 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2145 unsigned int extension
,
2147 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2152 switch (insn_format
)
2159 value
= extended_offset ((extension
<< 16) | inst
);
2160 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2164 value
= inst
& 0x7ff;
2165 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2174 { /* A register identifier and an offset. */
2175 /* Most of the fields are the same as I type but the
2176 immediate value is of a different length. */
2180 value
= extended_offset ((extension
<< 16) | inst
);
2181 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2185 value
= inst
& 0xff; /* 8 bits */
2186 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2189 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2195 unsigned long value
;
2196 unsigned int nexthalf
;
2197 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2198 value
= value
<< 16;
2199 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2200 /* Low bit still set. */
2208 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2210 upk
->offset
= offset
;
2216 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2217 and having a signed 16-bit OFFSET. */
2220 add_offset_16 (CORE_ADDR pc
, int offset
)
2222 return pc
+ (offset
<< 1) + 2;
2226 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2227 unsigned int extension
, unsigned int insn
)
2229 struct gdbarch
*gdbarch
= regcache
->arch ();
2230 int op
= (insn
>> 11);
2233 case 2: /* Branch */
2235 struct upk_mips16 upk
;
2236 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2237 pc
= add_offset_16 (pc
, upk
.offset
);
2240 case 3: /* JAL , JALX - Watch out, these are 32 bit
2243 struct upk_mips16 upk
;
2244 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2245 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2246 if ((insn
>> 10) & 0x01) /* Exchange mode */
2247 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2254 struct upk_mips16 upk
;
2256 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2257 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2259 pc
= add_offset_16 (pc
, upk
.offset
);
2266 struct upk_mips16 upk
;
2268 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2269 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2271 pc
= add_offset_16 (pc
, upk
.offset
);
2276 case 12: /* I8 Formats btez btnez */
2278 struct upk_mips16 upk
;
2280 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2281 /* upk.regx contains the opcode */
2282 /* Test register is 24 */
2283 reg
= regcache_raw_get_signed (regcache
, 24);
2284 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2285 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2286 pc
= add_offset_16 (pc
, upk
.offset
);
2291 case 29: /* RR Formats JR, JALR, JALR-RA */
2293 struct upk_mips16 upk
;
2294 /* upk.fmt = rrtype; */
2299 upk
.regx
= (insn
>> 8) & 0x07;
2300 upk
.regy
= (insn
>> 5) & 0x07;
2301 if ((upk
.regy
& 1) == 0)
2302 reg
= mips_reg3_to_reg
[upk
.regx
];
2304 reg
= 31; /* Function return instruction. */
2305 pc
= regcache_raw_get_signed (regcache
, reg
);
2312 /* This is an instruction extension. Fetch the real instruction
2313 (which follows the extension) and decode things based on
2317 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2318 fetch_mips_16 (gdbarch
, pc
));
2331 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2333 struct gdbarch
*gdbarch
= regcache
->arch ();
2334 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2335 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2338 /* The mips_next_pc function supports single_step when the remote
2339 target monitor or stub is not developed enough to do a single_step.
2340 It works by decoding the current instruction and predicting where a
2341 branch will go. This isn't hard because all the data is available.
2342 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2344 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2346 struct gdbarch
*gdbarch
= regcache
->arch ();
2348 if (mips_pc_is_mips16 (gdbarch
, pc
))
2349 return mips16_next_pc (regcache
, pc
);
2350 else if (mips_pc_is_micromips (gdbarch
, pc
))
2351 return micromips_next_pc (regcache
, pc
);
2353 return mips32_next_pc (regcache
, pc
);
2356 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2360 mips16_instruction_is_compact_branch (unsigned short insn
)
2362 switch (insn
& 0xf800)
2365 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2367 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2368 case 0x2800: /* BNEZ */
2369 case 0x2000: /* BEQZ */
2370 case 0x1000: /* B */
2377 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2381 micromips_instruction_is_compact_branch (unsigned short insn
)
2383 switch (micromips_op (insn
))
2385 case 0x11: /* POOL16C: bits 010001 */
2386 return (b5s5_op (insn
) == 0x18
2387 /* JRADDIUSP: bits 010001 11000 */
2388 || b5s5_op (insn
) == 0xd);
2389 /* JRC: bits 010011 01101 */
2390 case 0x10: /* POOL32I: bits 010000 */
2391 return (b5s5_op (insn
) & 0x1d) == 0x5;
2392 /* BEQZC/BNEZC: bits 010000 001x1 */
2398 struct mips_frame_cache
2401 struct trad_frame_saved_reg
*saved_regs
;
2404 /* Set a register's saved stack address in temp_saved_regs. If an
2405 address has already been set for this register, do nothing; this
2406 way we will only recognize the first save of a given register in a
2409 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2410 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2411 Strictly speaking, only the second range is used as it is only second
2412 range (the ABI instead of ISA registers) that comes into play when finding
2413 saved registers in a frame. */
2416 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2417 int regnum
, CORE_ADDR offset
)
2419 if (this_cache
!= NULL
2420 && this_cache
->saved_regs
[regnum
].addr
== -1)
2422 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2424 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2430 /* Fetch the immediate value from a MIPS16 instruction.
2431 If the previous instruction was an EXTEND, use it to extend
2432 the upper bits of the immediate value. This is a helper function
2433 for mips16_scan_prologue. */
2436 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2437 unsigned short inst
, /* current instruction */
2438 int nbits
, /* number of bits in imm field */
2439 int scale
, /* scale factor to be applied to imm */
2440 int is_signed
) /* is the imm field signed? */
2444 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2446 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2447 if (offset
& 0x8000) /* check for negative extend */
2448 offset
= 0 - (0x10000 - (offset
& 0xffff));
2449 return offset
| (inst
& 0x1f);
2453 int max_imm
= 1 << nbits
;
2454 int mask
= max_imm
- 1;
2455 int sign_bit
= max_imm
>> 1;
2457 offset
= inst
& mask
;
2458 if (is_signed
&& (offset
& sign_bit
))
2459 offset
= 0 - (max_imm
- offset
);
2460 return offset
* scale
;
2465 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2466 the associated FRAME_CACHE if not null.
2467 Return the address of the first instruction past the prologue. */
2470 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2471 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2472 struct frame_info
*this_frame
,
2473 struct mips_frame_cache
*this_cache
)
2475 int prev_non_prologue_insn
= 0;
2476 int this_non_prologue_insn
;
2477 int non_prologue_insns
= 0;
2480 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2482 long frame_offset
= 0; /* Size of stack frame. */
2483 long frame_adjust
= 0; /* Offset of FP from SP. */
2484 int frame_reg
= MIPS_SP_REGNUM
;
2485 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2486 unsigned inst
= 0; /* current instruction */
2487 unsigned entry_inst
= 0; /* the entry instruction */
2488 unsigned save_inst
= 0; /* the save instruction */
2489 int prev_delay_slot
= 0;
2493 int extend_bytes
= 0;
2494 int prev_extend_bytes
= 0;
2495 CORE_ADDR end_prologue_addr
;
2497 /* Can be called when there's no process, and hence when there's no
2499 if (this_frame
!= NULL
)
2500 sp
= get_frame_register_signed (this_frame
,
2501 gdbarch_num_regs (gdbarch
)
2506 if (limit_pc
> start_pc
+ 200)
2507 limit_pc
= start_pc
+ 200;
2510 /* Permit at most one non-prologue non-control-transfer instruction
2511 in the middle which may have been reordered by the compiler for
2513 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2515 this_non_prologue_insn
= 0;
2518 /* Save the previous instruction. If it's an EXTEND, we'll extract
2519 the immediate offset extension from it in mips16_get_imm. */
2522 /* Fetch and decode the instruction. */
2523 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2526 /* Normally we ignore extend instructions. However, if it is
2527 not followed by a valid prologue instruction, then this
2528 instruction is not part of the prologue either. We must
2529 remember in this case to adjust the end_prologue_addr back
2531 if ((inst
& 0xf800) == 0xf000) /* extend */
2533 extend_bytes
= MIPS_INSN16_SIZE
;
2537 prev_extend_bytes
= extend_bytes
;
2540 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2541 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2543 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2544 if (offset
< 0) /* Negative stack adjustment? */
2545 frame_offset
-= offset
;
2547 /* Exit loop if a positive stack adjustment is found, which
2548 usually means that the stack cleanup code in the function
2549 epilogue is reached. */
2552 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2554 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2555 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2556 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2558 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2560 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2561 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2562 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2564 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2566 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2567 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2569 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2571 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2572 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2574 else if (inst
== 0x673d) /* move $s1, $sp */
2579 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2581 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2582 frame_addr
= sp
+ offset
;
2584 frame_adjust
= offset
;
2586 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2588 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2589 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2590 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2592 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2594 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2595 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2596 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2598 else if ((inst
& 0xf81f) == 0xe809
2599 && (inst
& 0x700) != 0x700) /* entry */
2600 entry_inst
= inst
; /* Save for later processing. */
2601 else if ((inst
& 0xff80) == 0x6480) /* save */
2603 save_inst
= inst
; /* Save for later processing. */
2604 if (prev_extend_bytes
) /* extend */
2605 save_inst
|= prev_inst
<< 16;
2607 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2609 /* This instruction is part of the prologue, but we don't
2610 need to do anything special to handle it. */
2612 else if (mips16_instruction_has_delay_slot (inst
, 0))
2613 /* JAL/JALR/JALX/JR */
2615 /* The instruction in the delay slot can be a part
2616 of the prologue, so move forward once more. */
2618 if (mips16_instruction_has_delay_slot (inst
, 1))
2621 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2622 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2627 this_non_prologue_insn
= 1;
2630 non_prologue_insns
+= this_non_prologue_insn
;
2632 /* A jump or branch, or enough non-prologue insns seen? If so,
2633 then we must have reached the end of the prologue by now. */
2634 if (prev_delay_slot
|| non_prologue_insns
> 1
2635 || mips16_instruction_is_compact_branch (inst
))
2638 prev_non_prologue_insn
= this_non_prologue_insn
;
2639 prev_delay_slot
= in_delay_slot
;
2640 prev_pc
= cur_pc
- prev_extend_bytes
;
2643 /* The entry instruction is typically the first instruction in a function,
2644 and it stores registers at offsets relative to the value of the old SP
2645 (before the prologue). But the value of the sp parameter to this
2646 function is the new SP (after the prologue has been executed). So we
2647 can't calculate those offsets until we've seen the entire prologue,
2648 and can calculate what the old SP must have been. */
2649 if (entry_inst
!= 0)
2651 int areg_count
= (entry_inst
>> 8) & 7;
2652 int sreg_count
= (entry_inst
>> 6) & 3;
2654 /* The entry instruction always subtracts 32 from the SP. */
2657 /* Now we can calculate what the SP must have been at the
2658 start of the function prologue. */
2661 /* Check if a0-a3 were saved in the caller's argument save area. */
2662 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2664 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2665 offset
+= mips_abi_regsize (gdbarch
);
2668 /* Check if the ra register was pushed on the stack. */
2670 if (entry_inst
& 0x20)
2672 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2673 offset
-= mips_abi_regsize (gdbarch
);
2676 /* Check if the s0 and s1 registers were pushed on the stack. */
2677 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2679 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2680 offset
-= mips_abi_regsize (gdbarch
);
2684 /* The SAVE instruction is similar to ENTRY, except that defined by the
2685 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2686 size of the frame is specified as an immediate field of instruction
2687 and an extended variation exists which lets additional registers and
2688 frame space to be specified. The instruction always treats registers
2689 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2690 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2692 static int args_table
[16] = {
2693 0, 0, 0, 0, 1, 1, 1, 1,
2694 2, 2, 2, 0, 3, 3, 4, -1,
2696 static int astatic_table
[16] = {
2697 0, 1, 2, 3, 0, 1, 2, 3,
2698 0, 1, 2, 4, 0, 1, 0, -1,
2700 int aregs
= (save_inst
>> 16) & 0xf;
2701 int xsregs
= (save_inst
>> 24) & 0x7;
2702 int args
= args_table
[aregs
];
2703 int astatic
= astatic_table
[aregs
];
2708 warning (_("Invalid number of argument registers encoded in SAVE."));
2713 warning (_("Invalid number of static registers encoded in SAVE."));
2717 /* For standard SAVE the frame size of 0 means 128. */
2718 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2719 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2722 frame_offset
+= frame_size
;
2724 /* Now we can calculate what the SP must have been at the
2725 start of the function prologue. */
2728 /* Check if A0-A3 were saved in the caller's argument save area. */
2729 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2731 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2732 offset
+= mips_abi_regsize (gdbarch
);
2737 /* Check if the RA register was pushed on the stack. */
2738 if (save_inst
& 0x40)
2740 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2741 offset
-= mips_abi_regsize (gdbarch
);
2744 /* Check if the S8 register was pushed on the stack. */
2747 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2748 offset
-= mips_abi_regsize (gdbarch
);
2751 /* Check if S2-S7 were pushed on the stack. */
2752 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2754 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2755 offset
-= mips_abi_regsize (gdbarch
);
2758 /* Check if the S1 register was pushed on the stack. */
2759 if (save_inst
& 0x10)
2761 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2762 offset
-= mips_abi_regsize (gdbarch
);
2764 /* Check if the S0 register was pushed on the stack. */
2765 if (save_inst
& 0x20)
2767 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2768 offset
-= mips_abi_regsize (gdbarch
);
2771 /* Check if A0-A3 were pushed on the stack. */
2772 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2774 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2775 offset
-= mips_abi_regsize (gdbarch
);
2779 if (this_cache
!= NULL
)
2782 (get_frame_register_signed (this_frame
,
2783 gdbarch_num_regs (gdbarch
) + frame_reg
)
2784 + frame_offset
- frame_adjust
);
2785 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2786 be able to get rid of the assignment below, evetually. But it's
2787 still needed for now. */
2788 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2789 + mips_regnum (gdbarch
)->pc
]
2790 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2793 /* Set end_prologue_addr to the address of the instruction immediately
2794 after the last one we scanned. Unless the last one looked like a
2795 non-prologue instruction (and we looked ahead), in which case use
2796 its address instead. */
2797 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2798 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2800 return end_prologue_addr
;
2803 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2804 Procedures that use the 32-bit instruction set are handled by the
2805 mips_insn32 unwinder. */
2807 static struct mips_frame_cache
*
2808 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2810 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2811 struct mips_frame_cache
*cache
;
2813 if ((*this_cache
) != NULL
)
2814 return (struct mips_frame_cache
*) (*this_cache
);
2815 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2816 (*this_cache
) = cache
;
2817 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2819 /* Analyze the function prologue. */
2821 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2822 CORE_ADDR start_addr
;
2824 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2825 if (start_addr
== 0)
2826 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2827 /* We can't analyze the prologue if we couldn't find the begining
2829 if (start_addr
== 0)
2832 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2833 (struct mips_frame_cache
*) *this_cache
);
2836 /* gdbarch_sp_regnum contains the value and not the address. */
2837 trad_frame_set_value (cache
->saved_regs
,
2838 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2841 return (struct mips_frame_cache
*) (*this_cache
);
2845 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2846 struct frame_id
*this_id
)
2848 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2850 /* This marks the outermost frame. */
2851 if (info
->base
== 0)
2853 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2856 static struct value
*
2857 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2858 void **this_cache
, int regnum
)
2860 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2862 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2866 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2867 struct frame_info
*this_frame
, void **this_cache
)
2869 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2870 CORE_ADDR pc
= get_frame_pc (this_frame
);
2871 if (mips_pc_is_mips16 (gdbarch
, pc
))
2876 static const struct frame_unwind mips_insn16_frame_unwind
=
2879 default_frame_unwind_stop_reason
,
2880 mips_insn16_frame_this_id
,
2881 mips_insn16_frame_prev_register
,
2883 mips_insn16_frame_sniffer
2887 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2890 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2895 static const struct frame_base mips_insn16_frame_base
=
2897 &mips_insn16_frame_unwind
,
2898 mips_insn16_frame_base_address
,
2899 mips_insn16_frame_base_address
,
2900 mips_insn16_frame_base_address
2903 static const struct frame_base
*
2904 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2906 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2907 CORE_ADDR pc
= get_frame_pc (this_frame
);
2908 if (mips_pc_is_mips16 (gdbarch
, pc
))
2909 return &mips_insn16_frame_base
;
2914 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2915 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2916 interpreted directly, and then multiplied by 4. */
2919 micromips_decode_imm9 (int imm
)
2921 imm
= (imm
^ 0x100) - 0x100;
2922 if (imm
> -3 && imm
< 2)
2927 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2928 the address of the first instruction past the prologue. */
2931 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2932 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2933 struct frame_info
*this_frame
,
2934 struct mips_frame_cache
*this_cache
)
2936 CORE_ADDR end_prologue_addr
;
2937 int prev_non_prologue_insn
= 0;
2938 int frame_reg
= MIPS_SP_REGNUM
;
2939 int this_non_prologue_insn
;
2940 int non_prologue_insns
= 0;
2941 long frame_offset
= 0; /* Size of stack frame. */
2942 long frame_adjust
= 0; /* Offset of FP from SP. */
2943 int prev_delay_slot
= 0;
2947 ULONGEST insn
; /* current instruction */
2951 long v1_off
= 0; /* The assumption is LUI will replace it. */
2962 /* Can be called when there's no process, and hence when there's no
2964 if (this_frame
!= NULL
)
2965 sp
= get_frame_register_signed (this_frame
,
2966 gdbarch_num_regs (gdbarch
)
2971 if (limit_pc
> start_pc
+ 200)
2972 limit_pc
= start_pc
+ 200;
2975 /* Permit at most one non-prologue non-control-transfer instruction
2976 in the middle which may have been reordered by the compiler for
2978 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2980 this_non_prologue_insn
= 0;
2984 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2985 loc
+= MIPS_INSN16_SIZE
;
2986 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2988 /* 32-bit instructions. */
2989 case 2 * MIPS_INSN16_SIZE
:
2991 insn
|= mips_fetch_instruction (gdbarch
,
2992 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2993 loc
+= MIPS_INSN16_SIZE
;
2994 switch (micromips_op (insn
>> 16))
2996 /* Record $sp/$fp adjustment. */
2997 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2998 case 0x0: /* POOL32A: bits 000000 */
2999 case 0x16: /* POOL32S: bits 010110 */
3000 op
= b0s11_op (insn
);
3001 sreg
= b0s5_reg (insn
>> 16);
3002 treg
= b5s5_reg (insn
>> 16);
3003 dreg
= b11s5_reg (insn
);
3005 /* SUBU: bits 000000 00111010000 */
3006 /* DSUBU: bits 010110 00111010000 */
3007 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3009 /* (D)SUBU $sp, $v1 */
3011 else if (op
!= 0x150
3012 /* ADDU: bits 000000 00101010000 */
3013 /* DADDU: bits 010110 00101010000 */
3014 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3015 this_non_prologue_insn
= 1;
3018 case 0x8: /* POOL32B: bits 001000 */
3019 op
= b12s4_op (insn
);
3020 breg
= b0s5_reg (insn
>> 16);
3021 reglist
= sreg
= b5s5_reg (insn
>> 16);
3022 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3023 if ((op
== 0x9 || op
== 0xc)
3024 /* SWP: bits 001000 1001 */
3025 /* SDP: bits 001000 1100 */
3026 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3027 /* S[DW]P reg,offset($sp) */
3029 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3030 set_reg_offset (gdbarch
, this_cache
,
3032 set_reg_offset (gdbarch
, this_cache
,
3033 sreg
+ 1, sp
+ offset
+ s
);
3035 else if ((op
== 0xd || op
== 0xf)
3036 /* SWM: bits 001000 1101 */
3037 /* SDM: bits 001000 1111 */
3038 && breg
== MIPS_SP_REGNUM
3039 /* SWM reglist,offset($sp) */
3040 && ((reglist
>= 1 && reglist
<= 9)
3041 || (reglist
>= 16 && reglist
<= 25)))
3043 int sreglist
= std::min(reglist
& 0xf, 8);
3045 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3046 for (i
= 0; i
< sreglist
; i
++)
3047 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3048 if ((reglist
& 0xf) > 8)
3049 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3050 if ((reglist
& 0x10) == 0x10)
3051 set_reg_offset (gdbarch
, this_cache
,
3052 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3055 this_non_prologue_insn
= 1;
3058 /* Record $sp/$fp adjustment. */
3059 /* Discard (D)ADDIU $gp used for PIC code. */
3060 case 0xc: /* ADDIU: bits 001100 */
3061 case 0x17: /* DADDIU: bits 010111 */
3062 sreg
= b0s5_reg (insn
>> 16);
3063 dreg
= b5s5_reg (insn
>> 16);
3064 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3065 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3066 /* (D)ADDIU $sp, imm */
3068 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3069 /* (D)ADDIU $fp, $sp, imm */
3071 frame_adjust
= offset
;
3074 else if (sreg
!= 28 || dreg
!= 28)
3075 /* (D)ADDIU $gp, imm */
3076 this_non_prologue_insn
= 1;
3079 /* LUI $v1 is used for larger $sp adjustments. */
3080 /* Discard LUI $gp used for PIC code. */
3081 case 0x10: /* POOL32I: bits 010000 */
3082 if (b5s5_op (insn
>> 16) == 0xd
3083 /* LUI: bits 010000 001101 */
3084 && b0s5_reg (insn
>> 16) == 3)
3086 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3087 else if (b5s5_op (insn
>> 16) != 0xd
3088 /* LUI: bits 010000 001101 */
3089 || b0s5_reg (insn
>> 16) != 28)
3091 this_non_prologue_insn
= 1;
3094 /* ORI $v1 is used for larger $sp adjustments. */
3095 case 0x14: /* ORI: bits 010100 */
3096 sreg
= b0s5_reg (insn
>> 16);
3097 dreg
= b5s5_reg (insn
>> 16);
3098 if (sreg
== 3 && dreg
== 3)
3100 v1_off
|= b0s16_imm (insn
);
3102 this_non_prologue_insn
= 1;
3105 case 0x26: /* SWC1: bits 100110 */
3106 case 0x2e: /* SDC1: bits 101110 */
3107 breg
= b0s5_reg (insn
>> 16);
3108 if (breg
!= MIPS_SP_REGNUM
)
3109 /* S[DW]C1 reg,offset($sp) */
3110 this_non_prologue_insn
= 1;
3113 case 0x36: /* SD: bits 110110 */
3114 case 0x3e: /* SW: bits 111110 */
3115 breg
= b0s5_reg (insn
>> 16);
3116 sreg
= b5s5_reg (insn
>> 16);
3117 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3118 if (breg
== MIPS_SP_REGNUM
)
3119 /* S[DW] reg,offset($sp) */
3120 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3122 this_non_prologue_insn
= 1;
3126 /* The instruction in the delay slot can be a part
3127 of the prologue, so move forward once more. */
3128 if (micromips_instruction_has_delay_slot (insn
, 0))
3131 this_non_prologue_insn
= 1;
3137 /* 16-bit instructions. */
3138 case MIPS_INSN16_SIZE
:
3139 switch (micromips_op (insn
))
3141 case 0x3: /* MOVE: bits 000011 */
3142 sreg
= b0s5_reg (insn
);
3143 dreg
= b5s5_reg (insn
);
3144 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3147 else if ((sreg
& 0x1c) != 0x4)
3148 /* MOVE reg, $a0-$a3 */
3149 this_non_prologue_insn
= 1;
3152 case 0x11: /* POOL16C: bits 010001 */
3153 if (b6s4_op (insn
) == 0x5)
3154 /* SWM: bits 010001 0101 */
3156 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3157 reglist
= b4s2_regl (insn
);
3158 for (i
= 0; i
<= reglist
; i
++)
3159 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3160 set_reg_offset (gdbarch
, this_cache
,
3161 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3164 this_non_prologue_insn
= 1;
3167 case 0x13: /* POOL16D: bits 010011 */
3168 if ((insn
& 0x1) == 0x1)
3169 /* ADDIUSP: bits 010011 1 */
3170 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3171 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3172 /* ADDIUS5: bits 010011 0 */
3173 /* ADDIUS5 $sp, imm */
3174 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3176 this_non_prologue_insn
= 1;
3179 case 0x32: /* SWSP: bits 110010 */
3180 offset
= b0s5_imm (insn
) << 2;
3181 sreg
= b5s5_reg (insn
);
3182 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3186 /* The instruction in the delay slot can be a part
3187 of the prologue, so move forward once more. */
3188 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3191 this_non_prologue_insn
= 1;
3197 frame_offset
-= sp_adj
;
3199 non_prologue_insns
+= this_non_prologue_insn
;
3201 /* A jump or branch, enough non-prologue insns seen or positive
3202 stack adjustment? If so, then we must have reached the end
3203 of the prologue by now. */
3204 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3205 || micromips_instruction_is_compact_branch (insn
))
3208 prev_non_prologue_insn
= this_non_prologue_insn
;
3209 prev_delay_slot
= in_delay_slot
;
3213 if (this_cache
!= NULL
)
3216 (get_frame_register_signed (this_frame
,
3217 gdbarch_num_regs (gdbarch
) + frame_reg
)
3218 + frame_offset
- frame_adjust
);
3219 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3220 be able to get rid of the assignment below, evetually. But it's
3221 still needed for now. */
3222 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3223 + mips_regnum (gdbarch
)->pc
]
3224 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3227 /* Set end_prologue_addr to the address of the instruction immediately
3228 after the last one we scanned. Unless the last one looked like a
3229 non-prologue instruction (and we looked ahead), in which case use
3230 its address instead. */
3232 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3234 return end_prologue_addr
;
3237 /* Heuristic unwinder for procedures using microMIPS instructions.
3238 Procedures that use the 32-bit instruction set are handled by the
3239 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3241 static struct mips_frame_cache
*
3242 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3244 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3245 struct mips_frame_cache
*cache
;
3247 if ((*this_cache
) != NULL
)
3248 return (struct mips_frame_cache
*) (*this_cache
);
3250 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3251 (*this_cache
) = cache
;
3252 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3254 /* Analyze the function prologue. */
3256 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3257 CORE_ADDR start_addr
;
3259 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3260 if (start_addr
== 0)
3261 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3262 /* We can't analyze the prologue if we couldn't find the begining
3264 if (start_addr
== 0)
3267 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3268 (struct mips_frame_cache
*) *this_cache
);
3271 /* gdbarch_sp_regnum contains the value and not the address. */
3272 trad_frame_set_value (cache
->saved_regs
,
3273 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3276 return (struct mips_frame_cache
*) (*this_cache
);
3280 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3281 struct frame_id
*this_id
)
3283 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3285 /* This marks the outermost frame. */
3286 if (info
->base
== 0)
3288 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3291 static struct value
*
3292 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3293 void **this_cache
, int regnum
)
3295 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3297 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3301 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3302 struct frame_info
*this_frame
, void **this_cache
)
3304 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3305 CORE_ADDR pc
= get_frame_pc (this_frame
);
3307 if (mips_pc_is_micromips (gdbarch
, pc
))
3312 static const struct frame_unwind mips_micro_frame_unwind
=
3315 default_frame_unwind_stop_reason
,
3316 mips_micro_frame_this_id
,
3317 mips_micro_frame_prev_register
,
3319 mips_micro_frame_sniffer
3323 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3326 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3331 static const struct frame_base mips_micro_frame_base
=
3333 &mips_micro_frame_unwind
,
3334 mips_micro_frame_base_address
,
3335 mips_micro_frame_base_address
,
3336 mips_micro_frame_base_address
3339 static const struct frame_base
*
3340 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3342 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3343 CORE_ADDR pc
= get_frame_pc (this_frame
);
3345 if (mips_pc_is_micromips (gdbarch
, pc
))
3346 return &mips_micro_frame_base
;
3351 /* Mark all the registers as unset in the saved_regs array
3352 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3355 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3357 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3361 const int num_regs
= gdbarch_num_regs (gdbarch
);
3364 for (i
= 0; i
< num_regs
; i
++)
3366 this_cache
->saved_regs
[i
].addr
= -1;
3371 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3372 the associated FRAME_CACHE if not null.
3373 Return the address of the first instruction past the prologue. */
3376 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3377 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3378 struct frame_info
*this_frame
,
3379 struct mips_frame_cache
*this_cache
)
3381 int prev_non_prologue_insn
;
3382 int this_non_prologue_insn
;
3383 int non_prologue_insns
;
3384 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3386 int prev_delay_slot
;
3391 int frame_reg
= MIPS_SP_REGNUM
;
3393 CORE_ADDR end_prologue_addr
;
3394 int seen_sp_adjust
= 0;
3395 int load_immediate_bytes
= 0;
3397 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3399 /* Can be called when there's no process, and hence when there's no
3401 if (this_frame
!= NULL
)
3402 sp
= get_frame_register_signed (this_frame
,
3403 gdbarch_num_regs (gdbarch
)
3408 if (limit_pc
> start_pc
+ 200)
3409 limit_pc
= start_pc
+ 200;
3412 prev_non_prologue_insn
= 0;
3413 non_prologue_insns
= 0;
3414 prev_delay_slot
= 0;
3417 /* Permit at most one non-prologue non-control-transfer instruction
3418 in the middle which may have been reordered by the compiler for
3421 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3423 unsigned long inst
, high_word
;
3427 this_non_prologue_insn
= 0;
3430 /* Fetch the instruction. */
3431 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3434 /* Save some code by pre-extracting some useful fields. */
3435 high_word
= (inst
>> 16) & 0xffff;
3436 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3437 reg
= high_word
& 0x1f;
3439 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3440 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3441 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3443 if (offset
< 0) /* Negative stack adjustment? */
3444 frame_offset
-= offset
;
3446 /* Exit loop if a positive stack adjustment is found, which
3447 usually means that the stack cleanup code in the function
3448 epilogue is reached. */
3452 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3453 && !regsize_is_64_bits
)
3455 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3457 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3458 && regsize_is_64_bits
)
3460 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3461 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3463 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3465 /* Old gcc frame, r30 is virtual frame pointer. */
3466 if (offset
!= frame_offset
)
3467 frame_addr
= sp
+ offset
;
3468 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3470 unsigned alloca_adjust
;
3473 frame_addr
= get_frame_register_signed
3474 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3477 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3478 if (alloca_adjust
> 0)
3480 /* FP > SP + frame_size. This may be because of
3481 an alloca or somethings similar. Fix sp to
3482 "pre-alloca" value, and try again. */
3483 sp
+= alloca_adjust
;
3484 /* Need to reset the status of all registers. Otherwise,
3485 we will hit a guard that prevents the new address
3486 for each register to be recomputed during the second
3488 reset_saved_regs (gdbarch
, this_cache
);
3493 /* move $30,$sp. With different versions of gas this will be either
3494 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3495 Accept any one of these. */
3496 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3498 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3499 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3501 unsigned alloca_adjust
;
3504 frame_addr
= get_frame_register_signed
3505 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3507 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3508 if (alloca_adjust
> 0)
3510 /* FP > SP + frame_size. This may be because of
3511 an alloca or somethings similar. Fix sp to
3512 "pre-alloca" value, and try again. */
3514 /* Need to reset the status of all registers. Otherwise,
3515 we will hit a guard that prevents the new address
3516 for each register to be recomputed during the second
3518 reset_saved_regs (gdbarch
, this_cache
);
3523 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3524 && !regsize_is_64_bits
)
3526 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3528 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3529 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3530 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3531 || high_word
== 0x3c1c /* lui $gp,n */
3532 || high_word
== 0x279c /* addiu $gp,$gp,n */
3533 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3534 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3537 /* These instructions are part of the prologue, but we don't
3538 need to do anything special to handle them. */
3540 /* The instructions below load $at or $t0 with an immediate
3541 value in preparation for a stack adjustment via
3542 subu $sp,$sp,[$at,$t0]. These instructions could also
3543 initialize a local variable, so we accept them only before
3544 a stack adjustment instruction was seen. */
3545 else if (!seen_sp_adjust
3547 && (high_word
== 0x3c01 /* lui $at,n */
3548 || high_word
== 0x3c08 /* lui $t0,n */
3549 || high_word
== 0x3421 /* ori $at,$at,n */
3550 || high_word
== 0x3508 /* ori $t0,$t0,n */
3551 || high_word
== 0x3401 /* ori $at,$zero,n */
3552 || high_word
== 0x3408 /* ori $t0,$zero,n */
3555 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3557 /* Check for branches and jumps. The instruction in the delay
3558 slot can be a part of the prologue, so move forward once more. */
3559 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3563 /* This instruction is not an instruction typically found
3564 in a prologue, so we must have reached the end of the
3568 this_non_prologue_insn
= 1;
3571 non_prologue_insns
+= this_non_prologue_insn
;
3573 /* A jump or branch, or enough non-prologue insns seen? If so,
3574 then we must have reached the end of the prologue by now. */
3575 if (prev_delay_slot
|| non_prologue_insns
> 1)
3578 prev_non_prologue_insn
= this_non_prologue_insn
;
3579 prev_delay_slot
= in_delay_slot
;
3583 if (this_cache
!= NULL
)
3586 (get_frame_register_signed (this_frame
,
3587 gdbarch_num_regs (gdbarch
) + frame_reg
)
3589 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3590 this assignment below, eventually. But it's still needed
3592 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3593 + mips_regnum (gdbarch
)->pc
]
3594 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3598 /* Set end_prologue_addr to the address of the instruction immediately
3599 after the last one we scanned. Unless the last one looked like a
3600 non-prologue instruction (and we looked ahead), in which case use
3601 its address instead. */
3603 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3605 /* In a frameless function, we might have incorrectly
3606 skipped some load immediate instructions. Undo the skipping
3607 if the load immediate was not followed by a stack adjustment. */
3608 if (load_immediate_bytes
&& !seen_sp_adjust
)
3609 end_prologue_addr
-= load_immediate_bytes
;
3611 return end_prologue_addr
;
3614 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3615 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3616 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3617 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3619 static struct mips_frame_cache
*
3620 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3622 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3623 struct mips_frame_cache
*cache
;
3625 if ((*this_cache
) != NULL
)
3626 return (struct mips_frame_cache
*) (*this_cache
);
3628 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3629 (*this_cache
) = cache
;
3630 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3632 /* Analyze the function prologue. */
3634 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3635 CORE_ADDR start_addr
;
3637 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3638 if (start_addr
== 0)
3639 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3640 /* We can't analyze the prologue if we couldn't find the begining
3642 if (start_addr
== 0)
3645 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3646 (struct mips_frame_cache
*) *this_cache
);
3649 /* gdbarch_sp_regnum contains the value and not the address. */
3650 trad_frame_set_value (cache
->saved_regs
,
3651 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3654 return (struct mips_frame_cache
*) (*this_cache
);
3658 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3659 struct frame_id
*this_id
)
3661 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3663 /* This marks the outermost frame. */
3664 if (info
->base
== 0)
3666 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3669 static struct value
*
3670 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3671 void **this_cache
, int regnum
)
3673 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3675 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3679 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3680 struct frame_info
*this_frame
, void **this_cache
)
3682 CORE_ADDR pc
= get_frame_pc (this_frame
);
3683 if (mips_pc_is_mips (pc
))
3688 static const struct frame_unwind mips_insn32_frame_unwind
=
3691 default_frame_unwind_stop_reason
,
3692 mips_insn32_frame_this_id
,
3693 mips_insn32_frame_prev_register
,
3695 mips_insn32_frame_sniffer
3699 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3702 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3707 static const struct frame_base mips_insn32_frame_base
=
3709 &mips_insn32_frame_unwind
,
3710 mips_insn32_frame_base_address
,
3711 mips_insn32_frame_base_address
,
3712 mips_insn32_frame_base_address
3715 static const struct frame_base
*
3716 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3718 CORE_ADDR pc
= get_frame_pc (this_frame
);
3719 if (mips_pc_is_mips (pc
))
3720 return &mips_insn32_frame_base
;
3725 static struct trad_frame_cache
*
3726 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3729 CORE_ADDR start_addr
;
3730 CORE_ADDR stack_addr
;
3731 struct trad_frame_cache
*this_trad_cache
;
3732 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3733 int num_regs
= gdbarch_num_regs (gdbarch
);
3735 if ((*this_cache
) != NULL
)
3736 return (struct trad_frame_cache
*) (*this_cache
);
3737 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3738 (*this_cache
) = this_trad_cache
;
3740 /* The return address is in the link register. */
3741 trad_frame_set_reg_realreg (this_trad_cache
,
3742 gdbarch_pc_regnum (gdbarch
),
3743 num_regs
+ MIPS_RA_REGNUM
);
3745 /* Frame ID, since it's a frameless / stackless function, no stack
3746 space is allocated and SP on entry is the current SP. */
3747 pc
= get_frame_pc (this_frame
);
3748 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3749 stack_addr
= get_frame_register_signed (this_frame
,
3750 num_regs
+ MIPS_SP_REGNUM
);
3751 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3753 /* Assume that the frame's base is the same as the
3755 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3757 return this_trad_cache
;
3761 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3762 struct frame_id
*this_id
)
3764 struct trad_frame_cache
*this_trad_cache
3765 = mips_stub_frame_cache (this_frame
, this_cache
);
3766 trad_frame_get_id (this_trad_cache
, this_id
);
3769 static struct value
*
3770 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3771 void **this_cache
, int regnum
)
3773 struct trad_frame_cache
*this_trad_cache
3774 = mips_stub_frame_cache (this_frame
, this_cache
);
3775 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3779 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3780 struct frame_info
*this_frame
, void **this_cache
)
3783 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3784 struct bound_minimal_symbol msym
;
3786 /* Use the stub unwinder for unreadable code. */
3787 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3790 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3793 /* Calling a PIC function from a non-PIC function passes through a
3794 stub. The stub for foo is named ".pic.foo". */
3795 msym
= lookup_minimal_symbol_by_pc (pc
);
3796 if (msym
.minsym
!= NULL
3797 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3798 && startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
3804 static const struct frame_unwind mips_stub_frame_unwind
=
3807 default_frame_unwind_stop_reason
,
3808 mips_stub_frame_this_id
,
3809 mips_stub_frame_prev_register
,
3811 mips_stub_frame_sniffer
3815 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3818 struct trad_frame_cache
*this_trad_cache
3819 = mips_stub_frame_cache (this_frame
, this_cache
);
3820 return trad_frame_get_this_base (this_trad_cache
);
3823 static const struct frame_base mips_stub_frame_base
=
3825 &mips_stub_frame_unwind
,
3826 mips_stub_frame_base_address
,
3827 mips_stub_frame_base_address
,
3828 mips_stub_frame_base_address
3831 static const struct frame_base
*
3832 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3834 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3835 return &mips_stub_frame_base
;
3840 /* mips_addr_bits_remove - remove useless address bits */
3843 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3845 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3847 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3848 /* This hack is a work-around for existing boards using PMON, the
3849 simulator, and any other 64-bit targets that doesn't have true
3850 64-bit addressing. On these targets, the upper 32 bits of
3851 addresses are ignored by the hardware. Thus, the PC or SP are
3852 likely to have been sign extended to all 1s by instruction
3853 sequences that load 32-bit addresses. For example, a typical
3854 piece of code that loads an address is this:
3856 lui $r2, <upper 16 bits>
3857 ori $r2, <lower 16 bits>
3859 But the lui sign-extends the value such that the upper 32 bits
3860 may be all 1s. The workaround is simply to mask off these
3861 bits. In the future, gcc may be changed to support true 64-bit
3862 addressing, and this masking will have to be disabled. */
3863 return addr
&= 0xffffffffUL
;
3869 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3870 instruction and ending with a SC/SCD instruction. If such a sequence
3871 is found, attempt to step through it. A breakpoint is placed at the end of
3874 /* Instructions used during single-stepping of atomic sequences, standard
3876 #define LL_OPCODE 0x30
3877 #define LLD_OPCODE 0x34
3878 #define SC_OPCODE 0x38
3879 #define SCD_OPCODE 0x3c
3881 static std::vector
<CORE_ADDR
>
3882 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3884 CORE_ADDR breaks
[2] = {-1, -1};
3886 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3890 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3891 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3893 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3894 /* Assume all atomic sequences start with a ll/lld instruction. */
3895 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3898 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3900 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3903 loc
+= MIPS_INSN32_SIZE
;
3904 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3906 /* Assume that there is at most one branch in the atomic
3907 sequence. If a branch is found, put a breakpoint in its
3908 destination address. */
3909 switch (itype_op (insn
))
3911 case 0: /* SPECIAL */
3912 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3913 return {}; /* fallback to the standard single-step code. */
3915 case 1: /* REGIMM */
3916 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3917 || ((itype_rt (insn
) & 0x1e) == 0
3918 && itype_rs (insn
) == 0)); /* BPOSGE* */
3922 return {}; /* fallback to the standard single-step code. */
3929 case 22: /* BLEZL */
3930 case 23: /* BGTTL */
3934 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3935 && (itype_rt (insn
) & 0x2) == 0);
3936 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3941 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3946 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3947 if (last_breakpoint
>= 1)
3948 return {}; /* More than one branch found, fallback to the
3949 standard single-step code. */
3950 breaks
[1] = branch_bp
;
3954 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3958 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3959 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3962 loc
+= MIPS_INSN32_SIZE
;
3964 /* Insert a breakpoint right after the end of the atomic sequence. */
3967 /* Check for duplicated breakpoints. Check also for a breakpoint
3968 placed (branch instruction's destination) in the atomic sequence. */
3969 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3970 last_breakpoint
= 0;
3972 std::vector
<CORE_ADDR
> next_pcs
;
3974 /* Effectively inserts the breakpoints. */
3975 for (index
= 0; index
<= last_breakpoint
; index
++)
3976 next_pcs
.push_back (breaks
[index
]);
3981 static std::vector
<CORE_ADDR
>
3982 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3985 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3986 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3987 CORE_ADDR breaks
[2] = {-1, -1};
3988 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3996 /* Assume all atomic sequences start with a ll/lld instruction. */
3997 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3998 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4000 loc
+= MIPS_INSN16_SIZE
;
4002 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4003 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4005 loc
+= MIPS_INSN16_SIZE
;
4007 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4008 that no atomic sequence is longer than "atomic_sequence_length"
4010 for (insn_count
= 0;
4011 !sc_found
&& insn_count
< atomic_sequence_length
;
4016 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4017 loc
+= MIPS_INSN16_SIZE
;
4019 /* Assume that there is at most one conditional branch in the
4020 atomic sequence. If a branch is found, put a breakpoint in
4021 its destination address. */
4022 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4024 /* 32-bit instructions. */
4025 case 2 * MIPS_INSN16_SIZE
:
4026 switch (micromips_op (insn
))
4028 case 0x10: /* POOL32I: bits 010000 */
4029 if ((b5s5_op (insn
) & 0x18) != 0x0
4030 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4031 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4032 && (b5s5_op (insn
) & 0x1d) != 0x11
4033 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4034 && ((b5s5_op (insn
) & 0x1e) != 0x14
4035 || (insn
& 0x3) != 0x0)
4036 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4037 && (b5s5_op (insn
) & 0x1e) != 0x1a
4038 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4039 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4040 || (insn
& 0x3) != 0x0)
4041 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4042 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4043 || (insn
& 0x3) != 0x1))
4044 /* BC1ANY*: bits 010000 111xx xxx01 */
4048 case 0x25: /* BEQ: bits 100101 */
4049 case 0x2d: /* BNE: bits 101101 */
4051 insn
|= mips_fetch_instruction (gdbarch
,
4052 ISA_MICROMIPS
, loc
, NULL
);
4053 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4054 + micromips_relative_offset16 (insn
));
4058 case 0x00: /* POOL32A: bits 000000 */
4060 insn
|= mips_fetch_instruction (gdbarch
,
4061 ISA_MICROMIPS
, loc
, NULL
);
4062 if (b0s6_op (insn
) != 0x3c
4063 /* POOL32Axf: bits 000000 ... 111100 */
4064 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4065 /* JALR, JALR.HB: 000000 000x111100 111100 */
4066 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4070 case 0x1d: /* JALS: bits 011101 */
4071 case 0x35: /* J: bits 110101 */
4072 case 0x3d: /* JAL: bits 111101 */
4073 case 0x3c: /* JALX: bits 111100 */
4074 return {}; /* Fall back to the standard single-step code. */
4076 case 0x18: /* POOL32C: bits 011000 */
4077 if ((b12s4_op (insn
) & 0xb) == 0xb)
4078 /* SC, SCD: bits 011000 1x11 */
4082 loc
+= MIPS_INSN16_SIZE
;
4085 /* 16-bit instructions. */
4086 case MIPS_INSN16_SIZE
:
4087 switch (micromips_op (insn
))
4089 case 0x23: /* BEQZ16: bits 100011 */
4090 case 0x2b: /* BNEZ16: bits 101011 */
4091 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4095 case 0x11: /* POOL16C: bits 010001 */
4096 if ((b5s5_op (insn
) & 0x1c) != 0xc
4097 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4098 && b5s5_op (insn
) != 0x18)
4099 /* JRADDIUSP: bits 010001 11000 */
4101 return {}; /* Fall back to the standard single-step code. */
4103 case 0x33: /* B16: bits 110011 */
4104 return {}; /* Fall back to the standard single-step code. */
4110 if (last_breakpoint
>= 1)
4111 return {}; /* More than one branch found, fallback to the
4112 standard single-step code. */
4113 breaks
[1] = branch_bp
;
4120 /* Insert a breakpoint right after the end of the atomic sequence. */
4123 /* Check for duplicated breakpoints. Check also for a breakpoint
4124 placed (branch instruction's destination) in the atomic sequence */
4125 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4126 last_breakpoint
= 0;
4128 std::vector
<CORE_ADDR
> next_pcs
;
4130 /* Effectively inserts the breakpoints. */
4131 for (index
= 0; index
<= last_breakpoint
; index
++)
4132 next_pcs
.push_back (breaks
[index
]);
4137 static std::vector
<CORE_ADDR
>
4138 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4140 if (mips_pc_is_mips (pc
))
4141 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4142 else if (mips_pc_is_micromips (gdbarch
, pc
))
4143 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4148 /* mips_software_single_step() is called just before we want to resume
4149 the inferior, if we want to single-step it but there is no hardware
4150 or kernel single-step support (MIPS on GNU/Linux for example). We find
4151 the target of the coming instruction and breakpoint it. */
4153 std::vector
<CORE_ADDR
>
4154 mips_software_single_step (struct regcache
*regcache
)
4156 struct gdbarch
*gdbarch
= regcache
->arch ();
4157 CORE_ADDR pc
, next_pc
;
4159 pc
= regcache_read_pc (regcache
);
4160 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4162 if (!next_pcs
.empty ())
4165 next_pc
= mips_next_pc (regcache
, pc
);
4170 /* Test whether the PC points to the return instruction at the
4171 end of a function. */
4174 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4179 /* This used to check for MIPS16, but this piece of code is never
4180 called for MIPS16 functions. And likewise microMIPS ones. */
4181 gdb_assert (mips_pc_is_mips (pc
));
4183 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4185 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4189 /* This fencepost looks highly suspicious to me. Removing it also
4190 seems suspicious as it could affect remote debugging across serial
4194 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4200 struct inferior
*inf
;
4202 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4204 fence
= start_pc
- heuristic_fence_post
;
4208 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4209 fence
= VM_MIN_ADDRESS
;
4211 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4213 inf
= current_inferior ();
4215 /* Search back for previous return. */
4216 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4217 if (start_pc
< fence
)
4219 /* It's not clear to me why we reach this point when
4220 stop_soon, but with this test, at least we
4221 don't print out warnings for every child forked (eg, on
4222 decstation). 22apr93 rich@cygnus.com. */
4223 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4225 static int blurb_printed
= 0;
4227 warning (_("GDB can't find the start of the function at %s."),
4228 paddress (gdbarch
, pc
));
4232 /* This actually happens frequently in embedded
4233 development, when you first connect to a board
4234 and your stack pointer and pc are nowhere in
4235 particular. This message needs to give people
4236 in that situation enough information to
4237 determine that it's no big deal. */
4238 printf_filtered ("\n\
4239 GDB is unable to find the start of the function at %s\n\
4240 and thus can't determine the size of that function's stack frame.\n\
4241 This means that GDB may be unable to access that stack frame, or\n\
4242 the frames below it.\n\
4243 This problem is most likely caused by an invalid program counter or\n\
4245 However, if you think GDB should simply search farther back\n\
4246 from %s for code which looks like the beginning of a\n\
4247 function, you can increase the range of the search using the `set\n\
4248 heuristic-fence-post' command.\n",
4249 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4256 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4258 unsigned short inst
;
4260 /* On MIPS16, any one of the following is likely to be the
4261 start of a function:
4267 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4268 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4269 if ((inst
& 0xff80) == 0x6480) /* save */
4271 if (start_pc
- instlen
>= fence
)
4273 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4274 start_pc
- instlen
, NULL
);
4275 if ((inst
& 0xf800) == 0xf000) /* extend */
4276 start_pc
-= instlen
;
4280 else if (((inst
& 0xf81f) == 0xe809
4281 && (inst
& 0x700) != 0x700) /* entry */
4282 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4283 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4284 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4286 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4287 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4292 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4300 /* On microMIPS, any one of the following is likely to be the
4301 start of a function:
4305 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4306 switch (micromips_op (insn
))
4308 case 0xc: /* ADDIU: bits 001100 */
4309 case 0x17: /* DADDIU: bits 010111 */
4310 sreg
= b0s5_reg (insn
);
4311 dreg
= b5s5_reg (insn
);
4313 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4314 pc
+ MIPS_INSN16_SIZE
, NULL
);
4315 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4316 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4317 /* (D)ADDIU $sp, imm */
4322 case 0x10: /* POOL32I: bits 010000 */
4323 if (b5s5_op (insn
) == 0xd
4324 /* LUI: bits 010000 001101 */
4325 && b0s5_reg (insn
>> 16) == 28)
4330 case 0x13: /* POOL16D: bits 010011 */
4331 if ((insn
& 0x1) == 0x1)
4332 /* ADDIUSP: bits 010011 1 */
4334 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4340 /* ADDIUS5: bits 010011 0 */
4342 dreg
= b5s5_reg (insn
);
4343 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4344 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4345 /* ADDIUS5 $sp, -imm */
4353 else if (mips_about_to_return (gdbarch
, start_pc
))
4355 /* Skip return and its delay slot. */
4356 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4363 struct mips_objfile_private
4369 /* According to the current ABI, should the type be passed in a
4370 floating-point register (assuming that there is space)? When there
4371 is no FPU, FP are not even considered as possible candidates for
4372 FP registers and, consequently this returns false - forces FP
4373 arguments into integer registers. */
4376 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4377 struct type
*arg_type
)
4379 return ((typecode
== TYPE_CODE_FLT
4380 || (MIPS_EABI (gdbarch
)
4381 && (typecode
== TYPE_CODE_STRUCT
4382 || typecode
== TYPE_CODE_UNION
)
4383 && TYPE_NFIELDS (arg_type
) == 1
4384 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4386 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4389 /* On o32, argument passing in GPRs depends on the alignment of the type being
4390 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4393 mips_type_needs_double_align (struct type
*type
)
4395 enum type_code typecode
= TYPE_CODE (type
);
4397 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4399 else if (typecode
== TYPE_CODE_STRUCT
)
4401 if (TYPE_NFIELDS (type
) < 1)
4403 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4405 else if (typecode
== TYPE_CODE_UNION
)
4409 n
= TYPE_NFIELDS (type
);
4410 for (i
= 0; i
< n
; i
++)
4411 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4418 /* Adjust the address downward (direction of stack growth) so that it
4419 is correctly aligned for a new stack frame. */
4421 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4423 return align_down (addr
, 16);
4426 /* Implement the "push_dummy_code" gdbarch method. */
4429 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4430 CORE_ADDR funaddr
, struct value
**args
,
4431 int nargs
, struct type
*value_type
,
4432 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4433 struct regcache
*regcache
)
4435 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4439 /* Reserve enough room on the stack for our breakpoint instruction. */
4440 bp_slot
= sp
- sizeof (nop_insn
);
4442 /* Return to microMIPS mode if calling microMIPS code to avoid
4443 triggering an address error exception on processors that only
4444 support microMIPS execution. */
4445 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4446 ? make_compact_addr (bp_slot
) : bp_slot
);
4448 /* The breakpoint layer automatically adjusts the address of
4449 breakpoints inserted in a branch delay slot. With enough
4450 bad luck, the 4 bytes located just before our breakpoint
4451 instruction could look like a branch instruction, and thus
4452 trigger the adjustement, and break the function call entirely.
4453 So, we reserve those 4 bytes and write a nop instruction
4454 to prevent that from happening. */
4455 nop_addr
= bp_slot
- sizeof (nop_insn
);
4456 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4457 sp
= mips_frame_align (gdbarch
, nop_addr
);
4459 /* Inferior resumes at the function entry point. */
4466 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4467 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4468 int nargs
, struct value
**args
, CORE_ADDR sp
,
4469 int struct_return
, CORE_ADDR struct_addr
)
4475 int stack_offset
= 0;
4476 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4477 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4478 int abi_regsize
= mips_abi_regsize (gdbarch
);
4480 /* For shared libraries, "t9" needs to point at the function
4482 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4484 /* Set the return address register to point to the entry point of
4485 the program, where a breakpoint lies in wait. */
4486 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4488 /* First ensure that the stack and structure return address (if any)
4489 are properly aligned. The stack has to be at least 64-bit
4490 aligned even on 32-bit machines, because doubles must be 64-bit
4491 aligned. For n32 and n64, stack frames need to be 128-bit
4492 aligned, so we round to this widest known alignment. */
4494 sp
= align_down (sp
, 16);
4495 struct_addr
= align_down (struct_addr
, 16);
4497 /* Now make space on the stack for the args. We allocate more
4498 than necessary for EABI, because the first few arguments are
4499 passed in registers, but that's OK. */
4500 for (argnum
= 0; argnum
< nargs
; argnum
++)
4501 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4502 sp
-= align_up (len
, 16);
4505 fprintf_unfiltered (gdb_stdlog
,
4506 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4507 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4509 /* Initialize the integer and float register pointers. */
4510 argreg
= MIPS_A0_REGNUM
;
4511 float_argreg
= mips_fpa0_regnum (gdbarch
);
4513 /* The struct_return pointer occupies the first parameter-passing reg. */
4517 fprintf_unfiltered (gdb_stdlog
,
4518 "mips_eabi_push_dummy_call: "
4519 "struct_return reg=%d %s\n",
4520 argreg
, paddress (gdbarch
, struct_addr
));
4521 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4524 /* Now load as many as possible of the first arguments into
4525 registers, and push the rest onto the stack. Loop thru args
4526 from first to last. */
4527 for (argnum
= 0; argnum
< nargs
; argnum
++)
4529 const gdb_byte
*val
;
4530 /* This holds the address of structures that are passed by
4532 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4533 struct value
*arg
= args
[argnum
];
4534 struct type
*arg_type
= check_typedef (value_type (arg
));
4535 int len
= TYPE_LENGTH (arg_type
);
4536 enum type_code typecode
= TYPE_CODE (arg_type
);
4539 fprintf_unfiltered (gdb_stdlog
,
4540 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4541 argnum
+ 1, len
, (int) typecode
);
4543 /* The EABI passes structures that do not fit in a register by
4545 if (len
> abi_regsize
4546 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4548 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4549 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4550 value_address (arg
));
4551 typecode
= TYPE_CODE_PTR
;
4555 fprintf_unfiltered (gdb_stdlog
, " push");
4558 val
= value_contents (arg
);
4560 /* 32-bit ABIs always start floating point arguments in an
4561 even-numbered floating point register. Round the FP register
4562 up before the check to see if there are any FP registers
4563 left. Non MIPS_EABI targets also pass the FP in the integer
4564 registers so also round up normal registers. */
4565 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4567 if ((float_argreg
& 1))
4571 /* Floating point arguments passed in registers have to be
4572 treated specially. On 32-bit architectures, doubles
4573 are passed in register pairs; the even register gets
4574 the low word, and the odd register gets the high word.
4575 On non-EABI processors, the first two floating point arguments are
4576 also copied to general registers, because MIPS16 functions
4577 don't use float registers for arguments. This duplication of
4578 arguments in general registers can't hurt non-MIPS16 functions
4579 because those registers are normally skipped. */
4580 /* MIPS_EABI squeezes a struct that contains a single floating
4581 point value into an FP register instead of pushing it onto the
4583 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4584 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4586 /* EABI32 will pass doubles in consecutive registers, even on
4587 64-bit cores. At one time, we used to check the size of
4588 `float_argreg' to determine whether or not to pass doubles
4589 in consecutive registers, but this is not sufficient for
4590 making the ABI determination. */
4591 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4593 int low_offset
= gdbarch_byte_order (gdbarch
)
4594 == BFD_ENDIAN_BIG
? 4 : 0;
4597 /* Write the low word of the double to the even register(s). */
4598 regval
= extract_signed_integer (val
+ low_offset
,
4601 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4602 float_argreg
, phex (regval
, 4));
4603 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4605 /* Write the high word of the double to the odd register(s). */
4606 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4609 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4610 float_argreg
, phex (regval
, 4));
4611 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4615 /* This is a floating point value that fits entirely
4616 in a single register. */
4617 /* On 32 bit ABI's the float_argreg is further adjusted
4618 above to ensure that it is even register aligned. */
4619 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4621 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4622 float_argreg
, phex (regval
, len
));
4623 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4628 /* Copy the argument to general registers or the stack in
4629 register-sized pieces. Large arguments are split between
4630 registers and stack. */
4631 /* Note: structs whose size is not a multiple of abi_regsize
4632 are treated specially: Irix cc passes
4633 them in registers where gcc sometimes puts them on the
4634 stack. For maximum compatibility, we will put them in
4636 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4638 /* Note: Floating-point values that didn't fit into an FP
4639 register are only written to memory. */
4642 /* Remember if the argument was written to the stack. */
4643 int stack_used_p
= 0;
4644 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4647 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4650 /* Write this portion of the argument to the stack. */
4651 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4653 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4655 /* Should shorter than int integer values be
4656 promoted to int before being stored? */
4657 int longword_offset
= 0;
4660 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4662 if (abi_regsize
== 8
4663 && (typecode
== TYPE_CODE_INT
4664 || typecode
== TYPE_CODE_PTR
4665 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4666 longword_offset
= abi_regsize
- len
;
4667 else if ((typecode
== TYPE_CODE_STRUCT
4668 || typecode
== TYPE_CODE_UNION
)
4669 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4670 longword_offset
= abi_regsize
- len
;
4675 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4676 paddress (gdbarch
, stack_offset
));
4677 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4678 paddress (gdbarch
, longword_offset
));
4681 addr
= sp
+ stack_offset
+ longword_offset
;
4686 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4687 paddress (gdbarch
, addr
));
4688 for (i
= 0; i
< partial_len
; i
++)
4690 fprintf_unfiltered (gdb_stdlog
, "%02x",
4694 write_memory (addr
, val
, partial_len
);
4697 /* Note!!! This is NOT an else clause. Odd sized
4698 structs may go thru BOTH paths. Floating point
4699 arguments will not. */
4700 /* Write this portion of the argument to a general
4701 purpose register. */
4702 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4703 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4706 extract_signed_integer (val
, partial_len
, byte_order
);
4709 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4711 phex (regval
, abi_regsize
));
4712 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4719 /* Compute the offset into the stack at which we will
4720 copy the next parameter.
4722 In the new EABI (and the NABI32), the stack_offset
4723 only needs to be adjusted when it has been used. */
4726 stack_offset
+= align_up (partial_len
, abi_regsize
);
4730 fprintf_unfiltered (gdb_stdlog
, "\n");
4733 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4735 /* Return adjusted stack pointer. */
4739 /* Determine the return value convention being used. */
4741 static enum return_value_convention
4742 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4743 struct type
*type
, struct regcache
*regcache
,
4744 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4746 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4747 int fp_return_type
= 0;
4748 int offset
, regnum
, xfer
;
4750 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4751 return RETURN_VALUE_STRUCT_CONVENTION
;
4753 /* Floating point type? */
4754 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4756 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4758 /* Structs with a single field of float type
4759 are returned in a floating point register. */
4760 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4761 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4762 && TYPE_NFIELDS (type
) == 1)
4764 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4766 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4773 /* A floating-point value belongs in the least significant part
4776 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4777 regnum
= mips_regnum (gdbarch
)->fp0
;
4781 /* An integer value goes in V0/V1. */
4783 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4784 regnum
= MIPS_V0_REGNUM
;
4787 offset
< TYPE_LENGTH (type
);
4788 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4790 xfer
= mips_abi_regsize (gdbarch
);
4791 if (offset
+ xfer
> TYPE_LENGTH (type
))
4792 xfer
= TYPE_LENGTH (type
) - offset
;
4793 mips_xfer_register (gdbarch
, regcache
,
4794 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4795 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4799 return RETURN_VALUE_REGISTER_CONVENTION
;
4803 /* N32/N64 ABI stuff. */
4805 /* Search for a naturally aligned double at OFFSET inside a struct
4806 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4810 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4815 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4818 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4821 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4824 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4827 struct type
*field_type
;
4829 /* We're only looking at normal fields. */
4830 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4831 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4834 /* If we have gone past the offset, there is no double to pass. */
4835 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4839 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4841 /* If this field is entirely before the requested offset, go
4842 on to the next one. */
4843 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4846 /* If this is our special aligned double, we can stop. */
4847 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4848 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4851 /* This field starts at or before the requested offset, and
4852 overlaps it. If it is a structure, recurse inwards. */
4853 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4860 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4861 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4862 int nargs
, struct value
**args
, CORE_ADDR sp
,
4863 int struct_return
, CORE_ADDR struct_addr
)
4869 int stack_offset
= 0;
4870 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4871 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4873 /* For shared libraries, "t9" needs to point at the function
4875 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4877 /* Set the return address register to point to the entry point of
4878 the program, where a breakpoint lies in wait. */
4879 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4881 /* First ensure that the stack and structure return address (if any)
4882 are properly aligned. The stack has to be at least 64-bit
4883 aligned even on 32-bit machines, because doubles must be 64-bit
4884 aligned. For n32 and n64, stack frames need to be 128-bit
4885 aligned, so we round to this widest known alignment. */
4887 sp
= align_down (sp
, 16);
4888 struct_addr
= align_down (struct_addr
, 16);
4890 /* Now make space on the stack for the args. */
4891 for (argnum
= 0; argnum
< nargs
; argnum
++)
4892 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4893 sp
-= align_up (len
, 16);
4896 fprintf_unfiltered (gdb_stdlog
,
4897 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4898 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4900 /* Initialize the integer and float register pointers. */
4901 argreg
= MIPS_A0_REGNUM
;
4902 float_argreg
= mips_fpa0_regnum (gdbarch
);
4904 /* The struct_return pointer occupies the first parameter-passing reg. */
4908 fprintf_unfiltered (gdb_stdlog
,
4909 "mips_n32n64_push_dummy_call: "
4910 "struct_return reg=%d %s\n",
4911 argreg
, paddress (gdbarch
, struct_addr
));
4912 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4915 /* Now load as many as possible of the first arguments into
4916 registers, and push the rest onto the stack. Loop thru args
4917 from first to last. */
4918 for (argnum
= 0; argnum
< nargs
; argnum
++)
4920 const gdb_byte
*val
;
4921 struct value
*arg
= args
[argnum
];
4922 struct type
*arg_type
= check_typedef (value_type (arg
));
4923 int len
= TYPE_LENGTH (arg_type
);
4924 enum type_code typecode
= TYPE_CODE (arg_type
);
4927 fprintf_unfiltered (gdb_stdlog
,
4928 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4929 argnum
+ 1, len
, (int) typecode
);
4931 val
= value_contents (arg
);
4933 /* A 128-bit long double value requires an even-odd pair of
4934 floating-point registers. */
4936 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4937 && (float_argreg
& 1))
4943 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4944 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4946 /* This is a floating point value that fits entirely
4947 in a single register or a pair of registers. */
4948 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4949 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4951 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4952 float_argreg
, phex (regval
, reglen
));
4953 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4956 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4957 argreg
, phex (regval
, reglen
));
4958 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4963 regval
= extract_unsigned_integer (val
+ reglen
,
4964 reglen
, byte_order
);
4966 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4967 float_argreg
, phex (regval
, reglen
));
4968 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4971 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4972 argreg
, phex (regval
, reglen
));
4973 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4980 /* Copy the argument to general registers or the stack in
4981 register-sized pieces. Large arguments are split between
4982 registers and stack. */
4983 /* For N32/N64, structs, unions, or other composite types are
4984 treated as a sequence of doublewords, and are passed in integer
4985 or floating point registers as though they were simple scalar
4986 parameters to the extent that they fit, with any excess on the
4987 stack packed according to the normal memory layout of the
4989 The caller does not reserve space for the register arguments;
4990 the callee is responsible for reserving it if required. */
4991 /* Note: Floating-point values that didn't fit into an FP
4992 register are only written to memory. */
4995 /* Remember if the argument was written to the stack. */
4996 int stack_used_p
= 0;
4997 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5000 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5003 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5004 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5006 /* Write this portion of the argument to the stack. */
5007 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5009 /* Should shorter than int integer values be
5010 promoted to int before being stored? */
5011 int longword_offset
= 0;
5014 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5016 if ((typecode
== TYPE_CODE_INT
5017 || typecode
== TYPE_CODE_PTR
)
5019 longword_offset
= MIPS64_REGSIZE
- len
;
5024 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5025 paddress (gdbarch
, stack_offset
));
5026 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5027 paddress (gdbarch
, longword_offset
));
5030 addr
= sp
+ stack_offset
+ longword_offset
;
5035 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5036 paddress (gdbarch
, addr
));
5037 for (i
= 0; i
< partial_len
; i
++)
5039 fprintf_unfiltered (gdb_stdlog
, "%02x",
5043 write_memory (addr
, val
, partial_len
);
5046 /* Note!!! This is NOT an else clause. Odd sized
5047 structs may go thru BOTH paths. */
5048 /* Write this portion of the argument to a general
5049 purpose register. */
5050 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5054 /* Sign extend pointers, 32-bit integers and signed
5055 16-bit and 8-bit integers; everything else is taken
5058 if ((partial_len
== 4
5059 && (typecode
== TYPE_CODE_PTR
5060 || typecode
== TYPE_CODE_INT
))
5062 && typecode
== TYPE_CODE_INT
5063 && !TYPE_UNSIGNED (arg_type
)))
5064 regval
= extract_signed_integer (val
, partial_len
,
5067 regval
= extract_unsigned_integer (val
, partial_len
,
5070 /* A non-floating-point argument being passed in a
5071 general register. If a struct or union, and if
5072 the remaining length is smaller than the register
5073 size, we have to adjust the register value on
5076 It does not seem to be necessary to do the
5077 same for integral types. */
5079 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5080 && partial_len
< MIPS64_REGSIZE
5081 && (typecode
== TYPE_CODE_STRUCT
5082 || typecode
== TYPE_CODE_UNION
))
5083 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5087 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5089 phex (regval
, MIPS64_REGSIZE
));
5090 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5092 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5093 TYPE_LENGTH (arg_type
) - len
))
5096 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5098 phex (regval
, MIPS64_REGSIZE
));
5099 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5110 /* Compute the offset into the stack at which we will
5111 copy the next parameter.
5113 In N32 (N64?), the stack_offset only needs to be
5114 adjusted when it has been used. */
5117 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5121 fprintf_unfiltered (gdb_stdlog
, "\n");
5124 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5126 /* Return adjusted stack pointer. */
5130 static enum return_value_convention
5131 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5132 struct type
*type
, struct regcache
*regcache
,
5133 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5135 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5137 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5139 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5140 if needed), as appropriate for the type. Composite results (struct,
5141 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5144 * A struct with only one or two floating point fields is returned in $f0
5145 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5148 * Any other composite results of at most 128 bits are returned in
5149 $2 (first 64 bits) and $3 (remainder, if necessary).
5151 * Larger composite results are handled by converting the function to a
5152 procedure with an implicit first parameter, which is a pointer to an area
5153 reserved by the caller to receive the result. [The o32-bit ABI requires
5154 that all composite results be handled by conversion to implicit first
5155 parameters. The MIPS/SGI Fortran implementation has always made a
5156 specific exception to return COMPLEX results in the floating point
5159 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5160 return RETURN_VALUE_STRUCT_CONVENTION
;
5161 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5162 && TYPE_LENGTH (type
) == 16
5163 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5165 /* A 128-bit floating-point value fills both $f0 and $f2. The
5166 two registers are used in the same as memory order, so the
5167 eight bytes with the lower memory address are in $f0. */
5169 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5170 mips_xfer_register (gdbarch
, regcache
,
5171 (gdbarch_num_regs (gdbarch
)
5172 + mips_regnum (gdbarch
)->fp0
),
5173 8, gdbarch_byte_order (gdbarch
),
5174 readbuf
, writebuf
, 0);
5175 mips_xfer_register (gdbarch
, regcache
,
5176 (gdbarch_num_regs (gdbarch
)
5177 + mips_regnum (gdbarch
)->fp0
+ 2),
5178 8, gdbarch_byte_order (gdbarch
),
5179 readbuf
? readbuf
+ 8 : readbuf
,
5180 writebuf
? writebuf
+ 8 : writebuf
, 0);
5181 return RETURN_VALUE_REGISTER_CONVENTION
;
5183 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5184 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5186 /* A single or double floating-point value that fits in FP0. */
5188 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5189 mips_xfer_register (gdbarch
, regcache
,
5190 (gdbarch_num_regs (gdbarch
)
5191 + mips_regnum (gdbarch
)->fp0
),
5193 gdbarch_byte_order (gdbarch
),
5194 readbuf
, writebuf
, 0);
5195 return RETURN_VALUE_REGISTER_CONVENTION
;
5197 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5198 && TYPE_NFIELDS (type
) <= 2
5199 && TYPE_NFIELDS (type
) >= 1
5200 && ((TYPE_NFIELDS (type
) == 1
5201 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5203 || (TYPE_NFIELDS (type
) == 2
5204 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5206 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5207 == TYPE_CODE_FLT
))))
5209 /* A struct that contains one or two floats. Each value is part
5210 in the least significant part of their floating point
5211 register (or GPR, for soft float). */
5214 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5215 ? mips_regnum (gdbarch
)->fp0
5217 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5219 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5222 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5224 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5226 /* A 16-byte long double field goes in two consecutive
5228 mips_xfer_register (gdbarch
, regcache
,
5229 gdbarch_num_regs (gdbarch
) + regnum
,
5231 gdbarch_byte_order (gdbarch
),
5232 readbuf
, writebuf
, offset
);
5233 mips_xfer_register (gdbarch
, regcache
,
5234 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5236 gdbarch_byte_order (gdbarch
),
5237 readbuf
, writebuf
, offset
+ 8);
5240 mips_xfer_register (gdbarch
, regcache
,
5241 gdbarch_num_regs (gdbarch
) + regnum
,
5242 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5243 gdbarch_byte_order (gdbarch
),
5244 readbuf
, writebuf
, offset
);
5246 return RETURN_VALUE_REGISTER_CONVENTION
;
5248 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5249 || TYPE_CODE (type
) == TYPE_CODE_UNION
5250 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5252 /* A composite type. Extract the left justified value,
5253 regardless of the byte order. I.e. DO NOT USE
5257 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5258 offset
< TYPE_LENGTH (type
);
5259 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5261 int xfer
= register_size (gdbarch
, regnum
);
5262 if (offset
+ xfer
> TYPE_LENGTH (type
))
5263 xfer
= TYPE_LENGTH (type
) - offset
;
5265 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5266 offset
, xfer
, regnum
);
5267 mips_xfer_register (gdbarch
, regcache
,
5268 gdbarch_num_regs (gdbarch
) + regnum
,
5269 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5272 return RETURN_VALUE_REGISTER_CONVENTION
;
5276 /* A scalar extract each part but least-significant-byte
5280 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5281 offset
< TYPE_LENGTH (type
);
5282 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5284 int xfer
= register_size (gdbarch
, regnum
);
5285 if (offset
+ xfer
> TYPE_LENGTH (type
))
5286 xfer
= TYPE_LENGTH (type
) - offset
;
5288 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5289 offset
, xfer
, regnum
);
5290 mips_xfer_register (gdbarch
, regcache
,
5291 gdbarch_num_regs (gdbarch
) + regnum
,
5292 xfer
, gdbarch_byte_order (gdbarch
),
5293 readbuf
, writebuf
, offset
);
5295 return RETURN_VALUE_REGISTER_CONVENTION
;
5299 /* Which registers to use for passing floating-point values between
5300 function calls, one of floating-point, general and both kinds of
5301 registers. O32 and O64 use different register kinds for standard
5302 MIPS and MIPS16 code; to make the handling of cases where we may
5303 not know what kind of code is being used (e.g. no debug information)
5304 easier we sometimes use both kinds. */
5313 /* O32 ABI stuff. */
5316 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5317 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5318 int nargs
, struct value
**args
, CORE_ADDR sp
,
5319 int struct_return
, CORE_ADDR struct_addr
)
5325 int stack_offset
= 0;
5326 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5327 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5329 /* For shared libraries, "t9" needs to point at the function
5331 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5333 /* Set the return address register to point to the entry point of
5334 the program, where a breakpoint lies in wait. */
5335 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5337 /* First ensure that the stack and structure return address (if any)
5338 are properly aligned. The stack has to be at least 64-bit
5339 aligned even on 32-bit machines, because doubles must be 64-bit
5340 aligned. For n32 and n64, stack frames need to be 128-bit
5341 aligned, so we round to this widest known alignment. */
5343 sp
= align_down (sp
, 16);
5344 struct_addr
= align_down (struct_addr
, 16);
5346 /* Now make space on the stack for the args. */
5347 for (argnum
= 0; argnum
< nargs
; argnum
++)
5349 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5351 /* Align to double-word if necessary. */
5352 if (mips_type_needs_double_align (arg_type
))
5353 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5354 /* Allocate space on the stack. */
5355 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5357 sp
-= align_up (len
, 16);
5360 fprintf_unfiltered (gdb_stdlog
,
5361 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5362 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5364 /* Initialize the integer and float register pointers. */
5365 argreg
= MIPS_A0_REGNUM
;
5366 float_argreg
= mips_fpa0_regnum (gdbarch
);
5368 /* The struct_return pointer occupies the first parameter-passing reg. */
5372 fprintf_unfiltered (gdb_stdlog
,
5373 "mips_o32_push_dummy_call: "
5374 "struct_return reg=%d %s\n",
5375 argreg
, paddress (gdbarch
, struct_addr
));
5376 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5377 stack_offset
+= MIPS32_REGSIZE
;
5380 /* Now load as many as possible of the first arguments into
5381 registers, and push the rest onto the stack. Loop thru args
5382 from first to last. */
5383 for (argnum
= 0; argnum
< nargs
; argnum
++)
5385 const gdb_byte
*val
;
5386 struct value
*arg
= args
[argnum
];
5387 struct type
*arg_type
= check_typedef (value_type (arg
));
5388 int len
= TYPE_LENGTH (arg_type
);
5389 enum type_code typecode
= TYPE_CODE (arg_type
);
5392 fprintf_unfiltered (gdb_stdlog
,
5393 "mips_o32_push_dummy_call: %d len=%d type=%d",
5394 argnum
+ 1, len
, (int) typecode
);
5396 val
= value_contents (arg
);
5398 /* 32-bit ABIs always start floating point arguments in an
5399 even-numbered floating point register. Round the FP register
5400 up before the check to see if there are any FP registers
5401 left. O32 targets also pass the FP in the integer registers
5402 so also round up normal registers. */
5403 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5405 if ((float_argreg
& 1))
5409 /* Floating point arguments passed in registers have to be
5410 treated specially. On 32-bit architectures, doubles are
5411 passed in register pairs; the even FP register gets the
5412 low word, and the odd FP register gets the high word.
5413 On O32, the first two floating point arguments are also
5414 copied to general registers, following their memory order,
5415 because MIPS16 functions don't use float registers for
5416 arguments. This duplication of arguments in general
5417 registers can't hurt non-MIPS16 functions, because those
5418 registers are normally skipped. */
5420 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5421 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5423 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5425 int freg_offset
= gdbarch_byte_order (gdbarch
)
5426 == BFD_ENDIAN_BIG
? 1 : 0;
5427 unsigned long regval
;
5430 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5432 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5433 float_argreg
+ freg_offset
,
5435 regcache_cooked_write_unsigned (regcache
,
5436 float_argreg
++ + freg_offset
,
5439 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5440 argreg
, phex (regval
, 4));
5441 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5444 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5446 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5447 float_argreg
- freg_offset
,
5449 regcache_cooked_write_unsigned (regcache
,
5450 float_argreg
++ - freg_offset
,
5453 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5454 argreg
, phex (regval
, 4));
5455 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5459 /* This is a floating point value that fits entirely
5460 in a single register. */
5461 /* On 32 bit ABI's the float_argreg is further adjusted
5462 above to ensure that it is even register aligned. */
5463 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5465 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5466 float_argreg
, phex (regval
, len
));
5467 regcache_cooked_write_unsigned (regcache
,
5468 float_argreg
++, regval
);
5469 /* Although two FP registers are reserved for each
5470 argument, only one corresponding integer register is
5473 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5474 argreg
, phex (regval
, len
));
5475 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5477 /* Reserve space for the FP register. */
5478 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5482 /* Copy the argument to general registers or the stack in
5483 register-sized pieces. Large arguments are split between
5484 registers and stack. */
5485 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5486 are treated specially: Irix cc passes
5487 them in registers where gcc sometimes puts them on the
5488 stack. For maximum compatibility, we will put them in
5490 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5491 && len
% MIPS32_REGSIZE
!= 0);
5492 /* Structures should be aligned to eight bytes (even arg registers)
5493 on MIPS_ABI_O32, if their first member has double precision. */
5494 if (mips_type_needs_double_align (arg_type
))
5499 stack_offset
+= MIPS32_REGSIZE
;
5504 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5507 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5510 /* Write this portion of the argument to the stack. */
5511 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5512 || odd_sized_struct
)
5514 /* Should shorter than int integer values be
5515 promoted to int before being stored? */
5516 int longword_offset
= 0;
5521 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5522 paddress (gdbarch
, stack_offset
));
5523 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5524 paddress (gdbarch
, longword_offset
));
5527 addr
= sp
+ stack_offset
+ longword_offset
;
5532 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5533 paddress (gdbarch
, addr
));
5534 for (i
= 0; i
< partial_len
; i
++)
5536 fprintf_unfiltered (gdb_stdlog
, "%02x",
5540 write_memory (addr
, val
, partial_len
);
5543 /* Note!!! This is NOT an else clause. Odd sized
5544 structs may go thru BOTH paths. */
5545 /* Write this portion of the argument to a general
5546 purpose register. */
5547 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5549 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5551 /* Value may need to be sign extended, because
5552 mips_isa_regsize() != mips_abi_regsize(). */
5554 /* A non-floating-point argument being passed in a
5555 general register. If a struct or union, and if
5556 the remaining length is smaller than the register
5557 size, we have to adjust the register value on
5560 It does not seem to be necessary to do the
5561 same for integral types.
5563 Also don't do this adjustment on O64 binaries.
5565 cagney/2001-07-23: gdb/179: Also, GCC, when
5566 outputting LE O32 with sizeof (struct) <
5567 mips_abi_regsize(), generates a left shift
5568 as part of storing the argument in a register
5569 (the left shift isn't generated when
5570 sizeof (struct) >= mips_abi_regsize()). Since
5571 it is quite possible that this is GCC
5572 contradicting the LE/O32 ABI, GDB has not been
5573 adjusted to accommodate this. Either someone
5574 needs to demonstrate that the LE/O32 ABI
5575 specifies such a left shift OR this new ABI gets
5576 identified as such and GDB gets tweaked
5579 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5580 && partial_len
< MIPS32_REGSIZE
5581 && (typecode
== TYPE_CODE_STRUCT
5582 || typecode
== TYPE_CODE_UNION
))
5583 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5587 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5589 phex (regval
, MIPS32_REGSIZE
));
5590 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5593 /* Prevent subsequent floating point arguments from
5594 being passed in floating point registers. */
5595 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5601 /* Compute the offset into the stack at which we will
5602 copy the next parameter.
5604 In older ABIs, the caller reserved space for
5605 registers that contained arguments. This was loosely
5606 refered to as their "home". Consequently, space is
5607 always allocated. */
5609 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5613 fprintf_unfiltered (gdb_stdlog
, "\n");
5616 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5618 /* Return adjusted stack pointer. */
5622 static enum return_value_convention
5623 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5624 struct type
*type
, struct regcache
*regcache
,
5625 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5627 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5628 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5629 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5630 enum mips_fval_reg fval_reg
;
5632 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5633 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5634 || TYPE_CODE (type
) == TYPE_CODE_UNION
5635 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5636 return RETURN_VALUE_STRUCT_CONVENTION
;
5637 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5638 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5640 /* A single-precision floating-point value. If reading in or copying,
5641 then we get it from/put it to FP0 for standard MIPS code or GPR2
5642 for MIPS16 code. If writing out only, then we put it to both FP0
5643 and GPR2. We do not support reading in with no function known, if
5644 this safety check ever triggers, then we'll have to try harder. */
5645 gdb_assert (function
|| !readbuf
);
5650 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5653 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5655 case mips_fval_both
:
5656 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5659 if (fval_reg
!= mips_fval_gpr
)
5660 mips_xfer_register (gdbarch
, regcache
,
5661 (gdbarch_num_regs (gdbarch
)
5662 + mips_regnum (gdbarch
)->fp0
),
5664 gdbarch_byte_order (gdbarch
),
5665 readbuf
, writebuf
, 0);
5666 if (fval_reg
!= mips_fval_fpr
)
5667 mips_xfer_register (gdbarch
, regcache
,
5668 gdbarch_num_regs (gdbarch
) + 2,
5670 gdbarch_byte_order (gdbarch
),
5671 readbuf
, writebuf
, 0);
5672 return RETURN_VALUE_REGISTER_CONVENTION
;
5674 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5675 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5677 /* A double-precision floating-point value. If reading in or copying,
5678 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5679 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5680 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5681 no function known, if this safety check ever triggers, then we'll
5682 have to try harder. */
5683 gdb_assert (function
|| !readbuf
);
5688 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5691 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5693 case mips_fval_both
:
5694 fprintf_unfiltered (gdb_stderr
,
5695 "Return float in $fp1/$fp0 and $2/$3\n");
5698 if (fval_reg
!= mips_fval_gpr
)
5700 /* The most significant part goes in FP1, and the least significant
5702 switch (gdbarch_byte_order (gdbarch
))
5704 case BFD_ENDIAN_LITTLE
:
5705 mips_xfer_register (gdbarch
, regcache
,
5706 (gdbarch_num_regs (gdbarch
)
5707 + mips_regnum (gdbarch
)->fp0
+ 0),
5708 4, gdbarch_byte_order (gdbarch
),
5709 readbuf
, writebuf
, 0);
5710 mips_xfer_register (gdbarch
, regcache
,
5711 (gdbarch_num_regs (gdbarch
)
5712 + mips_regnum (gdbarch
)->fp0
+ 1),
5713 4, gdbarch_byte_order (gdbarch
),
5714 readbuf
, writebuf
, 4);
5716 case BFD_ENDIAN_BIG
:
5717 mips_xfer_register (gdbarch
, regcache
,
5718 (gdbarch_num_regs (gdbarch
)
5719 + mips_regnum (gdbarch
)->fp0
+ 1),
5720 4, gdbarch_byte_order (gdbarch
),
5721 readbuf
, writebuf
, 0);
5722 mips_xfer_register (gdbarch
, regcache
,
5723 (gdbarch_num_regs (gdbarch
)
5724 + mips_regnum (gdbarch
)->fp0
+ 0),
5725 4, gdbarch_byte_order (gdbarch
),
5726 readbuf
, writebuf
, 4);
5729 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5732 if (fval_reg
!= mips_fval_fpr
)
5734 /* The two 32-bit parts are always placed in GPR2 and GPR3
5735 following these registers' memory order. */
5736 mips_xfer_register (gdbarch
, regcache
,
5737 gdbarch_num_regs (gdbarch
) + 2,
5738 4, gdbarch_byte_order (gdbarch
),
5739 readbuf
, writebuf
, 0);
5740 mips_xfer_register (gdbarch
, regcache
,
5741 gdbarch_num_regs (gdbarch
) + 3,
5742 4, gdbarch_byte_order (gdbarch
),
5743 readbuf
, writebuf
, 4);
5745 return RETURN_VALUE_REGISTER_CONVENTION
;
5748 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5749 && TYPE_NFIELDS (type
) <= 2
5750 && TYPE_NFIELDS (type
) >= 1
5751 && ((TYPE_NFIELDS (type
) == 1
5752 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5754 || (TYPE_NFIELDS (type
) == 2
5755 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5757 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5759 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5761 /* A struct that contains one or two floats. Each value is part
5762 in the least significant part of their floating point
5766 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5767 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5769 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5772 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5774 mips_xfer_register (gdbarch
, regcache
,
5775 gdbarch_num_regs (gdbarch
) + regnum
,
5776 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5777 gdbarch_byte_order (gdbarch
),
5778 readbuf
, writebuf
, offset
);
5780 return RETURN_VALUE_REGISTER_CONVENTION
;
5784 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5785 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5787 /* A structure or union. Extract the left justified value,
5788 regardless of the byte order. I.e. DO NOT USE
5792 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5793 offset
< TYPE_LENGTH (type
);
5794 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5796 int xfer
= register_size (gdbarch
, regnum
);
5797 if (offset
+ xfer
> TYPE_LENGTH (type
))
5798 xfer
= TYPE_LENGTH (type
) - offset
;
5800 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5801 offset
, xfer
, regnum
);
5802 mips_xfer_register (gdbarch
, regcache
,
5803 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5804 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5806 return RETURN_VALUE_REGISTER_CONVENTION
;
5811 /* A scalar extract each part but least-significant-byte
5812 justified. o32 thinks registers are 4 byte, regardless of
5816 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5817 offset
< TYPE_LENGTH (type
);
5818 offset
+= MIPS32_REGSIZE
, regnum
++)
5820 int xfer
= MIPS32_REGSIZE
;
5821 if (offset
+ xfer
> TYPE_LENGTH (type
))
5822 xfer
= TYPE_LENGTH (type
) - offset
;
5824 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5825 offset
, xfer
, regnum
);
5826 mips_xfer_register (gdbarch
, regcache
,
5827 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5828 gdbarch_byte_order (gdbarch
),
5829 readbuf
, writebuf
, offset
);
5831 return RETURN_VALUE_REGISTER_CONVENTION
;
5835 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5839 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5840 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5842 struct value
**args
, CORE_ADDR sp
,
5843 int struct_return
, CORE_ADDR struct_addr
)
5849 int stack_offset
= 0;
5850 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5851 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5853 /* For shared libraries, "t9" needs to point at the function
5855 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5857 /* Set the return address register to point to the entry point of
5858 the program, where a breakpoint lies in wait. */
5859 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5861 /* First ensure that the stack and structure return address (if any)
5862 are properly aligned. The stack has to be at least 64-bit
5863 aligned even on 32-bit machines, because doubles must be 64-bit
5864 aligned. For n32 and n64, stack frames need to be 128-bit
5865 aligned, so we round to this widest known alignment. */
5867 sp
= align_down (sp
, 16);
5868 struct_addr
= align_down (struct_addr
, 16);
5870 /* Now make space on the stack for the args. */
5871 for (argnum
= 0; argnum
< nargs
; argnum
++)
5873 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5875 /* Allocate space on the stack. */
5876 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5878 sp
-= align_up (len
, 16);
5881 fprintf_unfiltered (gdb_stdlog
,
5882 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5883 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5885 /* Initialize the integer and float register pointers. */
5886 argreg
= MIPS_A0_REGNUM
;
5887 float_argreg
= mips_fpa0_regnum (gdbarch
);
5889 /* The struct_return pointer occupies the first parameter-passing reg. */
5893 fprintf_unfiltered (gdb_stdlog
,
5894 "mips_o64_push_dummy_call: "
5895 "struct_return reg=%d %s\n",
5896 argreg
, paddress (gdbarch
, struct_addr
));
5897 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5898 stack_offset
+= MIPS64_REGSIZE
;
5901 /* Now load as many as possible of the first arguments into
5902 registers, and push the rest onto the stack. Loop thru args
5903 from first to last. */
5904 for (argnum
= 0; argnum
< nargs
; argnum
++)
5906 const gdb_byte
*val
;
5907 struct value
*arg
= args
[argnum
];
5908 struct type
*arg_type
= check_typedef (value_type (arg
));
5909 int len
= TYPE_LENGTH (arg_type
);
5910 enum type_code typecode
= TYPE_CODE (arg_type
);
5913 fprintf_unfiltered (gdb_stdlog
,
5914 "mips_o64_push_dummy_call: %d len=%d type=%d",
5915 argnum
+ 1, len
, (int) typecode
);
5917 val
= value_contents (arg
);
5919 /* Floating point arguments passed in registers have to be
5920 treated specially. On 32-bit architectures, doubles are
5921 passed in register pairs; the even FP register gets the
5922 low word, and the odd FP register gets the high word.
5923 On O64, the first two floating point arguments are also
5924 copied to general registers, because MIPS16 functions
5925 don't use float registers for arguments. This duplication
5926 of arguments in general registers can't hurt non-MIPS16
5927 functions because those registers are normally skipped. */
5929 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5930 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5932 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5934 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5935 float_argreg
, phex (regval
, len
));
5936 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5938 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5939 argreg
, phex (regval
, len
));
5940 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5942 /* Reserve space for the FP register. */
5943 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5947 /* Copy the argument to general registers or the stack in
5948 register-sized pieces. Large arguments are split between
5949 registers and stack. */
5950 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5951 are treated specially: Irix cc passes them in registers
5952 where gcc sometimes puts them on the stack. For maximum
5953 compatibility, we will put them in both places. */
5954 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5955 && len
% MIPS64_REGSIZE
!= 0);
5958 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5961 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5964 /* Write this portion of the argument to the stack. */
5965 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5966 || odd_sized_struct
)
5968 /* Should shorter than int integer values be
5969 promoted to int before being stored? */
5970 int longword_offset
= 0;
5972 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5974 if ((typecode
== TYPE_CODE_INT
5975 || typecode
== TYPE_CODE_PTR
5976 || typecode
== TYPE_CODE_FLT
)
5978 longword_offset
= MIPS64_REGSIZE
- len
;
5983 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5984 paddress (gdbarch
, stack_offset
));
5985 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5986 paddress (gdbarch
, longword_offset
));
5989 addr
= sp
+ stack_offset
+ longword_offset
;
5994 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5995 paddress (gdbarch
, addr
));
5996 for (i
= 0; i
< partial_len
; i
++)
5998 fprintf_unfiltered (gdb_stdlog
, "%02x",
6002 write_memory (addr
, val
, partial_len
);
6005 /* Note!!! This is NOT an else clause. Odd sized
6006 structs may go thru BOTH paths. */
6007 /* Write this portion of the argument to a general
6008 purpose register. */
6009 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6011 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6013 /* Value may need to be sign extended, because
6014 mips_isa_regsize() != mips_abi_regsize(). */
6016 /* A non-floating-point argument being passed in a
6017 general register. If a struct or union, and if
6018 the remaining length is smaller than the register
6019 size, we have to adjust the register value on
6022 It does not seem to be necessary to do the
6023 same for integral types. */
6025 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6026 && partial_len
< MIPS64_REGSIZE
6027 && (typecode
== TYPE_CODE_STRUCT
6028 || typecode
== TYPE_CODE_UNION
))
6029 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6033 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6035 phex (regval
, MIPS64_REGSIZE
));
6036 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6039 /* Prevent subsequent floating point arguments from
6040 being passed in floating point registers. */
6041 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6047 /* Compute the offset into the stack at which we will
6048 copy the next parameter.
6050 In older ABIs, the caller reserved space for
6051 registers that contained arguments. This was loosely
6052 refered to as their "home". Consequently, space is
6053 always allocated. */
6055 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6059 fprintf_unfiltered (gdb_stdlog
, "\n");
6062 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6064 /* Return adjusted stack pointer. */
6068 static enum return_value_convention
6069 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6070 struct type
*type
, struct regcache
*regcache
,
6071 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6073 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6074 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6075 enum mips_fval_reg fval_reg
;
6077 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6078 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6079 || TYPE_CODE (type
) == TYPE_CODE_UNION
6080 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6081 return RETURN_VALUE_STRUCT_CONVENTION
;
6082 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6084 /* A floating-point value. If reading in or copying, then we get it
6085 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6086 If writing out only, then we put it to both FP0 and GPR2. We do
6087 not support reading in with no function known, if this safety
6088 check ever triggers, then we'll have to try harder. */
6089 gdb_assert (function
|| !readbuf
);
6094 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6097 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6099 case mips_fval_both
:
6100 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6103 if (fval_reg
!= mips_fval_gpr
)
6104 mips_xfer_register (gdbarch
, regcache
,
6105 (gdbarch_num_regs (gdbarch
)
6106 + mips_regnum (gdbarch
)->fp0
),
6108 gdbarch_byte_order (gdbarch
),
6109 readbuf
, writebuf
, 0);
6110 if (fval_reg
!= mips_fval_fpr
)
6111 mips_xfer_register (gdbarch
, regcache
,
6112 gdbarch_num_regs (gdbarch
) + 2,
6114 gdbarch_byte_order (gdbarch
),
6115 readbuf
, writebuf
, 0);
6116 return RETURN_VALUE_REGISTER_CONVENTION
;
6120 /* A scalar extract each part but least-significant-byte
6124 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6125 offset
< TYPE_LENGTH (type
);
6126 offset
+= MIPS64_REGSIZE
, regnum
++)
6128 int xfer
= MIPS64_REGSIZE
;
6129 if (offset
+ xfer
> TYPE_LENGTH (type
))
6130 xfer
= TYPE_LENGTH (type
) - offset
;
6132 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6133 offset
, xfer
, regnum
);
6134 mips_xfer_register (gdbarch
, regcache
,
6135 gdbarch_num_regs (gdbarch
) + regnum
,
6136 xfer
, gdbarch_byte_order (gdbarch
),
6137 readbuf
, writebuf
, offset
);
6139 return RETURN_VALUE_REGISTER_CONVENTION
;
6143 /* Floating point register management.
6145 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6146 64bit operations, these early MIPS cpus treat fp register pairs
6147 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6148 registers and offer a compatibility mode that emulates the MIPS2 fp
6149 model. When operating in MIPS2 fp compat mode, later cpu's split
6150 double precision floats into two 32-bit chunks and store them in
6151 consecutive fp regs. To display 64-bit floats stored in this
6152 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6153 Throw in user-configurable endianness and you have a real mess.
6155 The way this works is:
6156 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6157 double-precision value will be split across two logical registers.
6158 The lower-numbered logical register will hold the low-order bits,
6159 regardless of the processor's endianness.
6160 - If we are on a 64-bit processor, and we are looking for a
6161 single-precision value, it will be in the low ordered bits
6162 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6163 save slot in memory.
6164 - If we are in 64-bit mode, everything is straightforward.
6166 Note that this code only deals with "live" registers at the top of the
6167 stack. We will attempt to deal with saved registers later, when
6168 the raw/cooked register interface is in place. (We need a general
6169 interface that can deal with dynamic saved register sizes -- fp
6170 regs could be 32 bits wide in one frame and 64 on the frame above
6173 /* Copy a 32-bit single-precision value from the current frame
6174 into rare_buffer. */
6177 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6178 gdb_byte
*rare_buffer
)
6180 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6181 int raw_size
= register_size (gdbarch
, regno
);
6182 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6184 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6185 error (_("can't read register %d (%s)"),
6186 regno
, gdbarch_register_name (gdbarch
, regno
));
6189 /* We have a 64-bit value for this register. Find the low-order
6193 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6198 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6202 memcpy (rare_buffer
, raw_buffer
, 4);
6206 /* Copy a 64-bit double-precision value from the current frame into
6207 rare_buffer. This may include getting half of it from the next
6211 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6212 gdb_byte
*rare_buffer
)
6214 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6215 int raw_size
= register_size (gdbarch
, regno
);
6217 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6219 /* We have a 64-bit value for this register, and we should use
6221 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6222 error (_("can't read register %d (%s)"),
6223 regno
, gdbarch_register_name (gdbarch
, regno
));
6227 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6229 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6230 internal_error (__FILE__
, __LINE__
,
6231 _("mips_read_fp_register_double: bad access to "
6232 "odd-numbered FP register"));
6234 /* mips_read_fp_register_single will find the correct 32 bits from
6236 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6238 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6239 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6243 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6244 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6250 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6252 { /* Do values for FP (float) regs. */
6253 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6254 gdb_byte
*raw_buffer
;
6255 std::string flt_str
, dbl_str
;
6257 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6258 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6262 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6264 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6265 fprintf_filtered (file
, "%*s",
6266 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6269 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6271 struct value_print_options opts
;
6273 /* 4-byte registers: Print hex and floating. Also print even
6274 numbered registers as doubles. */
6275 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6276 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6278 get_formatted_print_options (&opts
, 'x');
6279 print_scalar_formatted (raw_buffer
,
6280 builtin_type (gdbarch
)->builtin_uint32
,
6283 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6285 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6287 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6288 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6290 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6295 struct value_print_options opts
;
6297 /* Eight byte registers: print each one as hex, float and double. */
6298 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6299 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6301 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6302 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6304 get_formatted_print_options (&opts
, 'x');
6305 print_scalar_formatted (raw_buffer
,
6306 builtin_type (gdbarch
)->builtin_uint64
,
6309 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6310 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6315 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6318 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6319 struct value_print_options opts
;
6322 if (mips_float_register_p (gdbarch
, regnum
))
6324 mips_print_fp_register (file
, frame
, regnum
);
6328 val
= get_frame_register_value (frame
, regnum
);
6330 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6332 /* The problem with printing numeric register names (r26, etc.) is that
6333 the user can't use them on input. Probably the best solution is to
6334 fix it so that either the numeric or the funky (a2, etc.) names
6335 are accepted on input. */
6336 if (regnum
< MIPS_NUMREGS
)
6337 fprintf_filtered (file
, "(r%d): ", regnum
);
6339 fprintf_filtered (file
, ": ");
6341 get_formatted_print_options (&opts
, 'x');
6342 val_print_scalar_formatted (value_type (val
),
6343 value_embedded_offset (val
),
6348 /* Print IEEE exception condition bits in FLAGS. */
6351 print_fpu_flags (struct ui_file
*file
, int flags
)
6353 if (flags
& (1 << 0))
6354 fputs_filtered (" inexact", file
);
6355 if (flags
& (1 << 1))
6356 fputs_filtered (" uflow", file
);
6357 if (flags
& (1 << 2))
6358 fputs_filtered (" oflow", file
);
6359 if (flags
& (1 << 3))
6360 fputs_filtered (" div0", file
);
6361 if (flags
& (1 << 4))
6362 fputs_filtered (" inval", file
);
6363 if (flags
& (1 << 5))
6364 fputs_filtered (" unimp", file
);
6365 fputc_filtered ('\n', file
);
6368 /* Print interesting information about the floating point processor
6369 (if present) or emulator. */
6372 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6373 struct frame_info
*frame
, const char *args
)
6375 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6376 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6380 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6381 type
= MIPS_FPU_NONE
;
6383 fprintf_filtered (file
, "fpu type: %s\n",
6384 type
== MIPS_FPU_DOUBLE
? "double-precision"
6385 : type
== MIPS_FPU_SINGLE
? "single-precision"
6388 if (type
== MIPS_FPU_NONE
)
6391 fprintf_filtered (file
, "reg size: %d bits\n",
6392 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6394 fputs_filtered ("cond :", file
);
6395 if (fcs
& (1 << 23))
6396 fputs_filtered (" 0", file
);
6397 for (i
= 1; i
<= 7; i
++)
6398 if (fcs
& (1 << (24 + i
)))
6399 fprintf_filtered (file
, " %d", i
);
6400 fputc_filtered ('\n', file
);
6402 fputs_filtered ("cause :", file
);
6403 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6404 fputs ("mask :", stdout
);
6405 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6406 fputs ("flags :", stdout
);
6407 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6409 fputs_filtered ("rounding: ", file
);
6412 case 0: fputs_filtered ("nearest\n", file
); break;
6413 case 1: fputs_filtered ("zero\n", file
); break;
6414 case 2: fputs_filtered ("+inf\n", file
); break;
6415 case 3: fputs_filtered ("-inf\n", file
); break;
6418 fputs_filtered ("flush :", file
);
6419 if (fcs
& (1 << 21))
6420 fputs_filtered (" nearest", file
);
6421 if (fcs
& (1 << 22))
6422 fputs_filtered (" override", file
);
6423 if (fcs
& (1 << 24))
6424 fputs_filtered (" zero", file
);
6425 if ((fcs
& (0xb << 21)) == 0)
6426 fputs_filtered (" no", file
);
6427 fputc_filtered ('\n', file
);
6429 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6430 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6431 fputc_filtered ('\n', file
);
6433 default_print_float_info (gdbarch
, file
, frame
, args
);
6436 /* Replacement for generic do_registers_info.
6437 Print regs in pretty columns. */
6440 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6443 fprintf_filtered (file
, " ");
6444 mips_print_fp_register (file
, frame
, regnum
);
6445 fprintf_filtered (file
, "\n");
6450 /* Print a row's worth of GP (int) registers, with name labels above. */
6453 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6456 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6457 /* Do values for GP (int) regs. */
6458 const gdb_byte
*raw_buffer
;
6459 struct value
*value
;
6460 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6465 /* For GP registers, we print a separate row of names above the vals. */
6466 for (col
= 0, regnum
= start_regnum
;
6467 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6468 + gdbarch_num_pseudo_regs (gdbarch
);
6471 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6472 continue; /* unused register */
6473 if (mips_float_register_p (gdbarch
, regnum
))
6474 break; /* End the row: reached FP register. */
6475 /* Large registers are handled separately. */
6476 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6479 break; /* End the row before this register. */
6481 /* Print this register on a row by itself. */
6482 mips_print_register (file
, frame
, regnum
);
6483 fprintf_filtered (file
, "\n");
6487 fprintf_filtered (file
, " ");
6488 fprintf_filtered (file
,
6489 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6490 gdbarch_register_name (gdbarch
, regnum
));
6497 /* Print the R0 to R31 names. */
6498 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6499 fprintf_filtered (file
, "\n R%-4d",
6500 start_regnum
% gdbarch_num_regs (gdbarch
));
6502 fprintf_filtered (file
, "\n ");
6504 /* Now print the values in hex, 4 or 8 to the row. */
6505 for (col
= 0, regnum
= start_regnum
;
6506 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6507 + gdbarch_num_pseudo_regs (gdbarch
);
6510 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6511 continue; /* unused register */
6512 if (mips_float_register_p (gdbarch
, regnum
))
6513 break; /* End row: reached FP register. */
6514 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6515 break; /* End row: large register. */
6517 /* OK: get the data in raw format. */
6518 value
= get_frame_register_value (frame
, regnum
);
6519 if (value_optimized_out (value
)
6520 || !value_entirely_available (value
))
6522 fprintf_filtered (file
, "%*s ",
6523 (int) mips_abi_regsize (gdbarch
) * 2,
6524 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6525 : "<unavailable>"));
6529 raw_buffer
= value_contents_all (value
);
6530 /* pad small registers */
6532 byte
< (mips_abi_regsize (gdbarch
)
6533 - register_size (gdbarch
, regnum
)); byte
++)
6534 fprintf_filtered (file
, " ");
6535 /* Now print the register value in hex, endian order. */
6536 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6538 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6539 byte
< register_size (gdbarch
, regnum
); byte
++)
6540 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6542 for (byte
= register_size (gdbarch
, regnum
) - 1;
6544 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6545 fprintf_filtered (file
, " ");
6548 if (col
> 0) /* ie. if we actually printed anything... */
6549 fprintf_filtered (file
, "\n");
6554 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6557 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6558 struct frame_info
*frame
, int regnum
, int all
)
6560 if (regnum
!= -1) /* Do one specified register. */
6562 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6563 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6564 error (_("Not a valid register for the current processor type"));
6566 mips_print_register (file
, frame
, regnum
);
6567 fprintf_filtered (file
, "\n");
6570 /* Do all (or most) registers. */
6572 regnum
= gdbarch_num_regs (gdbarch
);
6573 while (regnum
< gdbarch_num_regs (gdbarch
)
6574 + gdbarch_num_pseudo_regs (gdbarch
))
6576 if (mips_float_register_p (gdbarch
, regnum
))
6578 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6579 regnum
= print_fp_register_row (file
, frame
, regnum
);
6581 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6584 regnum
= print_gp_register_row (file
, frame
, regnum
);
6590 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6591 struct frame_info
*frame
)
6593 CORE_ADDR pc
= get_frame_pc (frame
);
6598 if ((mips_pc_is_mips (pc
)
6599 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6600 || (mips_pc_is_micromips (gdbarch
, pc
)
6601 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6602 || (mips_pc_is_mips16 (gdbarch
, pc
)
6603 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6606 isa
= mips_pc_isa (gdbarch
, pc
);
6607 /* _has_delay_slot above will have validated the read. */
6608 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6609 size
= mips_insn_size (isa
, insn
);
6611 const address_space
*aspace
= get_frame_address_space (frame
);
6613 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6616 /* To skip prologues, I use this predicate. Returns either PC itself
6617 if the code at PC does not look like a function prologue; otherwise
6618 returns an address that (if we're lucky) follows the prologue. If
6619 LENIENT, then we must skip everything which is involved in setting
6620 up the frame (it's OK to skip more, just so long as we don't skip
6621 anything which might clobber the registers which are being saved.
6622 We must skip more in the case where part of the prologue is in the
6623 delay slot of a non-prologue instruction). */
6626 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6629 CORE_ADDR func_addr
;
6631 /* See if we can determine the end of the prologue via the symbol table.
6632 If so, then return either PC, or the PC after the prologue, whichever
6634 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6636 CORE_ADDR post_prologue_pc
6637 = skip_prologue_using_sal (gdbarch
, func_addr
);
6638 if (post_prologue_pc
!= 0)
6639 return std::max (pc
, post_prologue_pc
);
6642 /* Can't determine prologue from the symbol table, need to examine
6645 /* Find an upper limit on the function prologue using the debug
6646 information. If the debug information could not be used to provide
6647 that bound, then use an arbitrary large number as the upper bound. */
6648 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6650 limit_pc
= pc
+ 100; /* Magic. */
6652 if (mips_pc_is_mips16 (gdbarch
, pc
))
6653 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6654 else if (mips_pc_is_micromips (gdbarch
, pc
))
6655 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6657 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6660 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6661 This is a helper function for mips_stack_frame_destroyed_p. */
6664 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6666 CORE_ADDR func_addr
= 0, func_end
= 0;
6668 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6670 /* The MIPS epilogue is max. 12 bytes long. */
6671 CORE_ADDR addr
= func_end
- 12;
6673 if (addr
< func_addr
+ 4)
6674 addr
= func_addr
+ 4;
6678 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6680 unsigned long high_word
;
6683 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6684 high_word
= (inst
>> 16) & 0xffff;
6686 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6687 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6688 && inst
!= 0x03e00008 /* jr $ra */
6689 && inst
!= 0x00000000) /* nop */
6699 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6700 This is a helper function for mips_stack_frame_destroyed_p. */
6703 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6705 CORE_ADDR func_addr
= 0;
6706 CORE_ADDR func_end
= 0;
6714 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6717 /* The microMIPS epilogue is max. 12 bytes long. */
6718 addr
= func_end
- 12;
6720 if (addr
< func_addr
+ 2)
6721 addr
= func_addr
+ 2;
6725 for (; pc
< func_end
; pc
+= loc
)
6728 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6729 loc
+= MIPS_INSN16_SIZE
;
6730 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6732 /* 32-bit instructions. */
6733 case 2 * MIPS_INSN16_SIZE
:
6735 insn
|= mips_fetch_instruction (gdbarch
,
6736 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6737 loc
+= MIPS_INSN16_SIZE
;
6738 switch (micromips_op (insn
>> 16))
6740 case 0xc: /* ADDIU: bits 001100 */
6741 case 0x17: /* DADDIU: bits 010111 */
6742 sreg
= b0s5_reg (insn
>> 16);
6743 dreg
= b5s5_reg (insn
>> 16);
6744 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6745 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6746 /* (D)ADDIU $sp, imm */
6756 /* 16-bit instructions. */
6757 case MIPS_INSN16_SIZE
:
6758 switch (micromips_op (insn
))
6760 case 0x3: /* MOVE: bits 000011 */
6761 sreg
= b0s5_reg (insn
);
6762 dreg
= b5s5_reg (insn
);
6763 if (sreg
== 0 && dreg
== 0)
6764 /* MOVE $zero, $zero aka NOP */
6768 case 0x11: /* POOL16C: bits 010001 */
6769 if (b5s5_op (insn
) == 0x18
6770 /* JRADDIUSP: bits 010011 11000 */
6771 || (b5s5_op (insn
) == 0xd
6772 /* JRC: bits 010011 01101 */
6773 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6778 case 0x13: /* POOL16D: bits 010011 */
6779 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6780 if ((insn
& 0x1) == 0x1
6781 /* ADDIUSP: bits 010011 1 */
6795 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6796 This is a helper function for mips_stack_frame_destroyed_p. */
6799 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6801 CORE_ADDR func_addr
= 0, func_end
= 0;
6803 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6805 /* The MIPS epilogue is max. 12 bytes long. */
6806 CORE_ADDR addr
= func_end
- 12;
6808 if (addr
< func_addr
+ 4)
6809 addr
= func_addr
+ 4;
6813 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6815 unsigned short inst
;
6817 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6819 if ((inst
& 0xf800) == 0xf000) /* extend */
6822 if (inst
!= 0x6300 /* addiu $sp,offset */
6823 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6824 && inst
!= 0xe820 /* jr $ra */
6825 && inst
!= 0xe8a0 /* jrc $ra */
6826 && inst
!= 0x6500) /* nop */
6836 /* Implement the stack_frame_destroyed_p gdbarch method.
6838 The epilogue is defined here as the area at the end of a function,
6839 after an instruction which destroys the function's stack frame. */
6842 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6844 if (mips_pc_is_mips16 (gdbarch
, pc
))
6845 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6846 else if (mips_pc_is_micromips (gdbarch
, pc
))
6847 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6849 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6852 /* Root of all "set mips "/"show mips " commands. This will eventually be
6853 used for all MIPS-specific commands. */
6856 show_mips_command (const char *args
, int from_tty
)
6858 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6862 set_mips_command (const char *args
, int from_tty
)
6865 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6866 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6869 /* Commands to show/set the MIPS FPU type. */
6872 show_mipsfpu_command (const char *args
, int from_tty
)
6876 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6879 ("The MIPS floating-point coprocessor is unknown "
6880 "because the current architecture is not MIPS.\n");
6884 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6886 case MIPS_FPU_SINGLE
:
6887 fpu
= "single-precision";
6889 case MIPS_FPU_DOUBLE
:
6890 fpu
= "double-precision";
6893 fpu
= "absent (none)";
6896 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6898 if (mips_fpu_type_auto
)
6899 printf_unfiltered ("The MIPS floating-point coprocessor "
6900 "is set automatically (currently %s)\n",
6904 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6909 set_mipsfpu_command (const char *args
, int from_tty
)
6911 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6912 "\"single\",\"none\" or \"auto\".\n");
6913 show_mipsfpu_command (args
, from_tty
);
6917 set_mipsfpu_single_command (const char *args
, int from_tty
)
6919 struct gdbarch_info info
;
6920 gdbarch_info_init (&info
);
6921 mips_fpu_type
= MIPS_FPU_SINGLE
;
6922 mips_fpu_type_auto
= 0;
6923 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6924 instead of relying on globals. Doing that would let generic code
6925 handle the search for this specific architecture. */
6926 if (!gdbarch_update_p (info
))
6927 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6931 set_mipsfpu_double_command (const char *args
, int from_tty
)
6933 struct gdbarch_info info
;
6934 gdbarch_info_init (&info
);
6935 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6936 mips_fpu_type_auto
= 0;
6937 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6938 instead of relying on globals. Doing that would let generic code
6939 handle the search for this specific architecture. */
6940 if (!gdbarch_update_p (info
))
6941 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6945 set_mipsfpu_none_command (const char *args
, int from_tty
)
6947 struct gdbarch_info info
;
6948 gdbarch_info_init (&info
);
6949 mips_fpu_type
= MIPS_FPU_NONE
;
6950 mips_fpu_type_auto
= 0;
6951 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6952 instead of relying on globals. Doing that would let generic code
6953 handle the search for this specific architecture. */
6954 if (!gdbarch_update_p (info
))
6955 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6959 set_mipsfpu_auto_command (const char *args
, int from_tty
)
6961 mips_fpu_type_auto
= 1;
6964 /* Just like reinit_frame_cache, but with the right arguments to be
6965 callable as an sfunc. */
6968 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
6969 struct cmd_list_element
*c
)
6971 reinit_frame_cache ();
6975 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6977 gdb_disassembler
*di
6978 = static_cast<gdb_disassembler
*>(info
->application_data
);
6979 struct gdbarch
*gdbarch
= di
->arch ();
6981 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6982 disassembler needs to be able to locally determine the ISA, and
6983 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6985 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6986 info
->mach
= bfd_mach_mips16
;
6987 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6988 info
->mach
= bfd_mach_mips_micromips
;
6990 /* Round down the instruction address to the appropriate boundary. */
6991 memaddr
&= (info
->mach
== bfd_mach_mips16
6992 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6994 /* Set the disassembler options. */
6995 if (!info
->disassembler_options
)
6996 /* This string is not recognized explicitly by the disassembler,
6997 but it tells the disassembler to not try to guess the ABI from
6998 the bfd elf headers, such that, if the user overrides the ABI
6999 of a program linked as NewABI, the disassembly will follow the
7000 register naming conventions specified by the user. */
7001 info
->disassembler_options
= "gpr-names=32";
7003 return default_print_insn (memaddr
, info
);
7007 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
7009 /* Set up the disassembler info, so that we get the right
7010 register names from libopcodes. */
7011 info
->disassembler_options
= "gpr-names=n32";
7012 info
->flavour
= bfd_target_elf_flavour
;
7014 return gdb_print_insn_mips (memaddr
, info
);
7018 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
7020 /* Set up the disassembler info, so that we get the right
7021 register names from libopcodes. */
7022 info
->disassembler_options
= "gpr-names=64";
7023 info
->flavour
= bfd_target_elf_flavour
;
7025 return gdb_print_insn_mips (memaddr
, info
);
7028 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7031 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7033 CORE_ADDR pc
= *pcptr
;
7035 if (mips_pc_is_mips16 (gdbarch
, pc
))
7037 *pcptr
= unmake_compact_addr (pc
);
7038 return MIPS_BP_KIND_MIPS16
;
7040 else if (mips_pc_is_micromips (gdbarch
, pc
))
7045 *pcptr
= unmake_compact_addr (pc
);
7046 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7047 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7048 return MIPS_BP_KIND_MICROMIPS16
;
7050 return MIPS_BP_KIND_MICROMIPS32
;
7053 return MIPS_BP_KIND_MIPS32
;
7056 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7058 static const gdb_byte
*
7059 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7061 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7065 case MIPS_BP_KIND_MIPS16
:
7067 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7068 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7071 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7072 return mips16_big_breakpoint
;
7074 return mips16_little_breakpoint
;
7076 case MIPS_BP_KIND_MICROMIPS16
:
7078 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7079 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7083 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7084 return micromips16_big_breakpoint
;
7086 return micromips16_little_breakpoint
;
7088 case MIPS_BP_KIND_MICROMIPS32
:
7090 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7091 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7094 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7095 return micromips32_big_breakpoint
;
7097 return micromips32_little_breakpoint
;
7099 case MIPS_BP_KIND_MIPS32
:
7101 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7102 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7105 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7106 return big_breakpoint
;
7108 return little_breakpoint
;
7111 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7115 /* Return non-zero if the standard MIPS instruction INST has a branch
7116 delay slot (i.e. it is a jump or branch instruction). This function
7117 is based on mips32_next_pc. */
7120 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7126 op
= itype_op (inst
);
7127 if ((inst
& 0xe0000000) != 0)
7129 rs
= itype_rs (inst
);
7130 rt
= itype_rt (inst
);
7131 return (is_octeon_bbit_op (op
, gdbarch
)
7132 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7133 || op
== 29 /* JALX: bits 011101 */
7136 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7137 || (rs
== 9 && (rt
& 0x2) == 0)
7138 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7139 || (rs
== 10 && (rt
& 0x2) == 0))));
7140 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7143 switch (op
& 0x07) /* extract bits 28,27,26 */
7145 case 0: /* SPECIAL */
7146 op
= rtype_funct (inst
);
7147 return (op
== 8 /* JR */
7148 || op
== 9); /* JALR */
7149 break; /* end SPECIAL */
7150 case 1: /* REGIMM */
7151 rs
= itype_rs (inst
);
7152 rt
= itype_rt (inst
); /* branch condition */
7153 return ((rt
& 0xc) == 0
7154 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7155 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7156 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7157 /* BPOSGE32, BPOSGE64: bits 1110x */
7158 break; /* end REGIMM */
7159 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7165 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7166 delay slot (i.e. it is a jump or branch instruction). */
7169 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7174 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7178 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7181 /* Return non-zero if the microMIPS instruction INSN, comprising the
7182 16-bit major opcode word in the high 16 bits and any second word
7183 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7184 jump or branch instruction). The instruction must be 32-bit if
7185 MUSTBE32 is set or can be any instruction otherwise. */
7188 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7190 ULONGEST major
= insn
>> 16;
7192 switch (micromips_op (major
))
7194 /* 16-bit instructions. */
7195 case 0x33: /* B16: bits 110011 */
7196 case 0x2b: /* BNEZ16: bits 101011 */
7197 case 0x23: /* BEQZ16: bits 100011 */
7199 case 0x11: /* POOL16C: bits 010001 */
7201 && ((b5s5_op (major
) == 0xc
7202 /* JR16: bits 010001 01100 */
7203 || (b5s5_op (major
) & 0x1e) == 0xe)));
7204 /* JALR16, JALRS16: bits 010001 0111x */
7205 /* 32-bit instructions. */
7206 case 0x3d: /* JAL: bits 111101 */
7207 case 0x3c: /* JALX: bits 111100 */
7208 case 0x35: /* J: bits 110101 */
7209 case 0x2d: /* BNE: bits 101101 */
7210 case 0x25: /* BEQ: bits 100101 */
7211 case 0x1d: /* JALS: bits 011101 */
7213 case 0x10: /* POOL32I: bits 010000 */
7214 return ((b5s5_op (major
) & 0x1c) == 0x0
7215 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7216 || (b5s5_op (major
) & 0x1d) == 0x4
7217 /* BLEZ, BGTZ: bits 010000 001x0 */
7218 || (b5s5_op (major
) & 0x1d) == 0x11
7219 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7220 || ((b5s5_op (major
) & 0x1e) == 0x14
7221 && (major
& 0x3) == 0x0)
7222 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7223 || (b5s5_op (major
) & 0x1e) == 0x1a
7224 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7225 || ((b5s5_op (major
) & 0x1e) == 0x1c
7226 && (major
& 0x3) == 0x0)
7227 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7228 || ((b5s5_op (major
) & 0x1c) == 0x1c
7229 && (major
& 0x3) == 0x1));
7230 /* BC1ANY*: bits 010000 111xx xxx01 */
7231 case 0x0: /* POOL32A: bits 000000 */
7232 return (b0s6_op (insn
) == 0x3c
7233 /* POOL32Axf: bits 000000 ... 111100 */
7234 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7235 /* JALR, JALR.HB: 000000 000x111100 111100 */
7236 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7242 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7243 slot (i.e. it is a non-compact jump instruction). The instruction
7244 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7247 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7248 CORE_ADDR addr
, int mustbe32
)
7254 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7257 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7259 if (size
== 2 * MIPS_INSN16_SIZE
)
7261 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7266 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7269 /* Return non-zero if the MIPS16 instruction INST, which must be
7270 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7271 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7272 instruction). This function is based on mips16_next_pc. */
7275 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7277 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7279 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7282 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7283 slot (i.e. it is a non-compact jump instruction). The instruction
7284 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7287 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7288 CORE_ADDR addr
, int mustbe32
)
7290 unsigned short insn
;
7293 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7297 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7300 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7301 This assumes KSSEG exists. */
7304 mips_segment_boundary (CORE_ADDR bpaddr
)
7306 CORE_ADDR mask
= CORE_ADDR_MAX
;
7309 if (sizeof (CORE_ADDR
) == 8)
7310 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7311 a compiler warning produced where CORE_ADDR is a 32-bit type even
7312 though in that case this is dead code). */
7313 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7316 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7317 segsize
= 29; /* 32-bit compatibility segment */
7319 segsize
= 62; /* xkseg */
7321 case 2: /* xkphys */
7324 default: /* xksseg (1), xkuseg/kuseg (0) */
7328 else if (bpaddr
& 0x80000000) /* kernel segment */
7331 segsize
= 31; /* user segment */
7333 return bpaddr
& mask
;
7336 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7337 it backwards if necessary. Return the address of the new location. */
7340 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7342 CORE_ADDR prev_addr
;
7344 CORE_ADDR func_addr
;
7346 /* If a breakpoint is set on the instruction in a branch delay slot,
7347 GDB gets confused. When the breakpoint is hit, the PC isn't on
7348 the instruction in the branch delay slot, the PC will point to
7349 the branch instruction. Since the PC doesn't match any known
7350 breakpoints, GDB reports a trap exception.
7352 There are two possible fixes for this problem.
7354 1) When the breakpoint gets hit, see if the BD bit is set in the
7355 Cause register (which indicates the last exception occurred in a
7356 branch delay slot). If the BD bit is set, fix the PC to point to
7357 the instruction in the branch delay slot.
7359 2) When the user sets the breakpoint, don't allow him to set the
7360 breakpoint on the instruction in the branch delay slot. Instead
7361 move the breakpoint to the branch instruction (which will have
7364 The problem with the first solution is that if the user then
7365 single-steps the processor, the branch instruction will get
7366 skipped (since GDB thinks the PC is on the instruction in the
7369 So, we'll use the second solution. To do this we need to know if
7370 the instruction we're trying to set the breakpoint on is in the
7371 branch delay slot. */
7373 boundary
= mips_segment_boundary (bpaddr
);
7375 /* Make sure we don't scan back before the beginning of the current
7376 function, since we may fetch constant data or insns that look like
7377 a jump. Of course we might do that anyway if the compiler has
7378 moved constants inline. :-( */
7379 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7380 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7381 boundary
= func_addr
;
7383 if (mips_pc_is_mips (bpaddr
))
7385 if (bpaddr
== boundary
)
7388 /* If the previous instruction has a branch delay slot, we have
7389 to move the breakpoint to the branch instruction. */
7390 prev_addr
= bpaddr
- 4;
7391 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7396 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7397 CORE_ADDR addr
, jmpaddr
;
7400 boundary
= unmake_compact_addr (boundary
);
7402 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7403 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7404 so try for that first, then try the 2 byte JALR/JR.
7405 The microMIPS ASE has a whole range of jumps and branches
7406 with delay slots, some of which take 4 bytes and some take
7407 2 bytes, so the idea is the same.
7408 FIXME: We have to assume that bpaddr is not the second half
7409 of an extended instruction. */
7410 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7411 ? micromips_insn_at_pc_has_delay_slot
7412 : mips16_insn_at_pc_has_delay_slot
);
7416 for (i
= 1; i
< 4; i
++)
7418 if (unmake_compact_addr (addr
) == boundary
)
7420 addr
-= MIPS_INSN16_SIZE
;
7421 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7422 /* Looks like a JR/JALR at [target-1], but it could be
7423 the second word of a previous JAL/JALX, so record it
7424 and check back one more. */
7426 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7429 /* Looks like a JAL/JALX at [target-2], but it could also
7430 be the second word of a previous JAL/JALX, record it,
7431 and check back one more. */
7434 /* Looks like a JAL/JALX at [target-3], so any previously
7435 recorded JAL/JALX or JR/JALR must be wrong, because:
7438 -2: JAL-ext (can't be JAL/JALX)
7439 -1: bdslot (can't be JR/JALR)
7442 Of course it could be another JAL-ext which looks
7443 like a JAL, but in that case we'd have broken out
7444 of this loop at [target-2]:
7448 -2: bdslot (can't be jmp)
7455 /* Not a jump instruction: if we're at [target-1] this
7456 could be the second word of a JAL/JALX, so continue;
7457 otherwise we're done. */
7470 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7471 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7474 mips_is_stub_suffix (const char *suffix
, int zero
)
7479 return zero
&& suffix
[1] == '\0';
7481 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7486 return suffix
[1] == '\0';
7492 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7493 call stubs, one of sf, df, sc, or dc. */
7496 mips_is_stub_mode (const char *mode
)
7498 return ((mode
[0] == 's' || mode
[0] == 'd')
7499 && (mode
[1] == 'f' || mode
[1] == 'c'));
7502 /* Code at PC is a compiler-generated stub. Such a stub for a function
7503 bar might have a name like __fn_stub_bar, and might look like this:
7510 followed by (or interspersed with):
7517 addiu $25, $25, %lo(bar)
7520 ($1 may be used in old code; for robustness we accept any register)
7523 lui $28, %hi(_gp_disp)
7524 addiu $28, $28, %lo(_gp_disp)
7527 addiu $25, $25, %lo(bar)
7530 In the case of a __call_stub_bar stub, the sequence to set up
7531 arguments might look like this:
7538 followed by (or interspersed with) one of the jump sequences above.
7540 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7541 of J or JR, respectively, followed by:
7547 We are at the beginning of the stub here, and scan down and extract
7548 the target address from the jump immediate instruction or, if a jump
7549 register instruction is used, from the register referred. Return
7550 the value of PC calculated or 0 if inconclusive.
7552 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7555 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7557 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7558 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7559 int addrreg
= MIPS_ZERO_REGNUM
;
7560 CORE_ADDR start_pc
= pc
;
7561 CORE_ADDR target_pc
= 0;
7568 status
== 0 && target_pc
== 0 && i
< 20;
7569 i
++, pc
+= MIPS_INSN32_SIZE
)
7571 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7577 switch (itype_op (inst
))
7579 case 0: /* SPECIAL */
7580 switch (rtype_funct (inst
))
7584 rs
= rtype_rs (inst
);
7585 if (rs
== MIPS_GP_REGNUM
)
7586 target_pc
= gp
; /* Hmm... */
7587 else if (rs
== addrreg
)
7591 case 0x21: /* ADDU */
7592 rt
= rtype_rt (inst
);
7593 rs
= rtype_rs (inst
);
7594 rd
= rtype_rd (inst
);
7595 if (rd
== MIPS_GP_REGNUM
7596 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7597 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7605 target_pc
= jtype_target (inst
) << 2;
7606 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7610 rt
= itype_rt (inst
);
7611 rs
= itype_rs (inst
);
7614 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7615 if (rt
== MIPS_GP_REGNUM
)
7617 else if (rt
== addrreg
)
7623 rt
= itype_rt (inst
);
7624 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7625 if (rt
== MIPS_GP_REGNUM
)
7627 else if (rt
!= MIPS_ZERO_REGNUM
)
7635 rt
= itype_rt (inst
);
7636 rs
= itype_rs (inst
);
7637 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7638 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7642 memset (buf
, 0, sizeof (buf
));
7643 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7645 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7654 /* If PC is in a MIPS16 call or return stub, return the address of the
7655 target PC, which is either the callee or the caller. There are several
7656 cases which must be handled:
7658 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7659 and the target PC is in $31 ($ra).
7660 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7661 and the target PC is in $2.
7662 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7663 i.e. before the JALR instruction, this is effectively a call stub
7664 and the target PC is in $2. Otherwise this is effectively
7665 a return stub and the target PC is in $18.
7666 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7667 JAL or JALR instruction, this is effectively a call stub and the
7668 target PC is buried in the instruction stream. Otherwise this
7669 is effectively a return stub and the target PC is in $18.
7670 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7671 stub and the target PC is buried in the instruction stream.
7673 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7674 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7678 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7680 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7681 CORE_ADDR start_addr
;
7685 /* Find the starting address and name of the function containing the PC. */
7686 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7689 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7690 and the target PC is in $31 ($ra). */
7691 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7692 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7693 && mips_is_stub_mode (name
+ prefixlen
)
7694 && name
[prefixlen
+ 2] == '\0')
7695 return get_frame_register_signed
7696 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7698 /* If the PC is in __mips16_call_stub_*, this is one of the call
7699 call/return stubs. */
7700 prefixlen
= strlen (mips_str_mips16_call_stub
);
7701 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7703 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7704 and the target PC is in $2. */
7705 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7706 return get_frame_register_signed
7707 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7709 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7710 i.e. before the JALR instruction, this is effectively a call stub
7711 and the target PC is in $2. Otherwise this is effectively
7712 a return stub and the target PC is in $18. */
7713 else if (mips_is_stub_mode (name
+ prefixlen
)
7714 && name
[prefixlen
+ 2] == '_'
7715 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7717 if (pc
== start_addr
)
7718 /* This is the 'call' part of a call stub. The return
7719 address is in $2. */
7720 return get_frame_register_signed
7721 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7723 /* This is the 'return' part of a call stub. The return
7724 address is in $18. */
7725 return get_frame_register_signed
7726 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7729 return 0; /* Not a stub. */
7732 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7733 compiler-generated call or call/return stubs. */
7734 if (startswith (name
, mips_str_fn_stub
)
7735 || startswith (name
, mips_str_call_stub
))
7737 if (pc
== start_addr
)
7738 /* This is the 'call' part of a call stub. Call this helper
7739 to scan through this code for interesting instructions
7740 and determine the final PC. */
7741 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7743 /* This is the 'return' part of a call stub. The return address
7745 return get_frame_register_signed
7746 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7749 return 0; /* Not a stub. */
7752 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7753 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7756 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7758 CORE_ADDR start_addr
;
7761 /* Find the starting address of the function containing the PC. */
7762 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7765 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7766 the start, i.e. after the JALR instruction, this is effectively
7768 prefixlen
= strlen (mips_str_mips16_call_stub
);
7769 if (pc
!= start_addr
7770 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7771 && mips_is_stub_mode (name
+ prefixlen
)
7772 && name
[prefixlen
+ 2] == '_'
7773 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7776 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7777 the JAL or JALR instruction, this is effectively a return stub. */
7778 prefixlen
= strlen (mips_str_call_fp_stub
);
7779 if (pc
!= start_addr
7780 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7783 /* Consume the .pic. prefix of any PIC stub, this function must return
7784 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7785 or the call stub path will trigger in handle_inferior_event causing
7787 prefixlen
= strlen (mips_str_pic
);
7788 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7791 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7792 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7793 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7794 && mips_is_stub_mode (name
+ prefixlen
)
7795 && name
[prefixlen
+ 2] == '\0')
7798 return 0; /* Not a stub. */
7801 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7802 PC of the stub target. The stub just loads $t9 and jumps to it,
7803 so that $t9 has the correct value at function entry. */
7806 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7808 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7809 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7810 struct bound_minimal_symbol msym
;
7812 gdb_byte stub_code
[16];
7813 int32_t stub_words
[4];
7815 /* The stub for foo is named ".pic.foo", and is either two
7816 instructions inserted before foo or a three instruction sequence
7817 which jumps to foo. */
7818 msym
= lookup_minimal_symbol_by_pc (pc
);
7819 if (msym
.minsym
== NULL
7820 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7821 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7822 || !startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
7825 /* A two-instruction header. */
7826 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7829 /* A three-instruction (plus delay slot) trampoline. */
7830 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7832 if (target_read_memory (pc
, stub_code
, 16) != 0)
7834 for (i
= 0; i
< 4; i
++)
7835 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7838 /* A stub contains these instructions:
7841 addiu t9, t9, %lo(target)
7844 This works even for N64, since stubs are only generated with
7846 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7847 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7848 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7849 && stub_words
[3] == 0x00000000)
7850 return ((((stub_words
[0] & 0x0000ffff) << 16)
7851 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7854 /* Not a recognized stub. */
7859 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7861 CORE_ADDR requested_pc
= pc
;
7862 CORE_ADDR target_pc
;
7869 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7873 new_pc
= find_solib_trampoline_target (frame
, pc
);
7877 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7881 while (pc
!= target_pc
);
7883 return pc
!= requested_pc
? pc
: 0;
7886 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7887 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7890 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7893 if (num
>= 0 && num
< 32)
7895 else if (num
>= 38 && num
< 70)
7896 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7898 regnum
= mips_regnum (gdbarch
)->hi
;
7900 regnum
= mips_regnum (gdbarch
)->lo
;
7901 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7902 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7905 return gdbarch_num_regs (gdbarch
) + regnum
;
7909 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7910 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7913 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7916 if (num
>= 0 && num
< 32)
7918 else if (num
>= 32 && num
< 64)
7919 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7921 regnum
= mips_regnum (gdbarch
)->hi
;
7923 regnum
= mips_regnum (gdbarch
)->lo
;
7924 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7925 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7928 return gdbarch_num_regs (gdbarch
) + regnum
;
7932 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7934 /* Only makes sense to supply raw registers. */
7935 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7936 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7937 decide if it is valid. Should instead define a standard sim/gdb
7938 register numbering scheme. */
7939 if (gdbarch_register_name (gdbarch
,
7940 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7941 && gdbarch_register_name (gdbarch
,
7942 gdbarch_num_regs (gdbarch
)
7943 + regnum
)[0] != '\0')
7946 return LEGACY_SIM_REGNO_IGNORE
;
7950 /* Convert an integer into an address. Extracting the value signed
7951 guarantees a correctly sign extended address. */
7954 mips_integer_to_address (struct gdbarch
*gdbarch
,
7955 struct type
*type
, const gdb_byte
*buf
)
7957 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7958 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7961 /* Dummy virtual frame pointer method. This is no more or less accurate
7962 than most other architectures; we just need to be explicit about it,
7963 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7964 an assertion failure. */
7967 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7968 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7970 *reg
= MIPS_SP_REGNUM
;
7975 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7977 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7978 const char *name
= bfd_get_section_name (abfd
, sect
);
7980 if (*abip
!= MIPS_ABI_UNKNOWN
)
7983 if (!startswith (name
, ".mdebug."))
7986 if (strcmp (name
, ".mdebug.abi32") == 0)
7987 *abip
= MIPS_ABI_O32
;
7988 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7989 *abip
= MIPS_ABI_N32
;
7990 else if (strcmp (name
, ".mdebug.abi64") == 0)
7991 *abip
= MIPS_ABI_N64
;
7992 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7993 *abip
= MIPS_ABI_O64
;
7994 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7995 *abip
= MIPS_ABI_EABI32
;
7996 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7997 *abip
= MIPS_ABI_EABI64
;
7999 warning (_("unsupported ABI %s."), name
+ 8);
8003 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8005 int *lbp
= (int *) obj
;
8006 const char *name
= bfd_get_section_name (abfd
, sect
);
8008 if (startswith (name
, ".gcc_compiled_long32"))
8010 else if (startswith (name
, ".gcc_compiled_long64"))
8012 else if (startswith (name
, ".gcc_compiled_long"))
8013 warning (_("unrecognized .gcc_compiled_longXX"));
8016 static enum mips_abi
8017 global_mips_abi (void)
8021 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8022 if (mips_abi_strings
[i
] == mips_abi_string
)
8023 return (enum mips_abi
) i
;
8025 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8028 /* Return the default compressed instruction set, either of MIPS16
8029 or microMIPS, selected when none could have been determined from
8030 the ELF header of the binary being executed (or no binary has been
8033 static enum mips_isa
8034 global_mips_compression (void)
8038 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8039 if (mips_compression_strings
[i
] == mips_compression_string
)
8040 return (enum mips_isa
) i
;
8042 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8046 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8048 /* If the size matches the set of 32-bit or 64-bit integer registers,
8049 assume that's what we've got. */
8050 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8051 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8053 /* If the size matches the full set of registers GDB traditionally
8054 knows about, including floating point, for either 32-bit or
8055 64-bit, assume that's what we've got. */
8056 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8057 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8059 /* Otherwise we don't have a useful guess. */
8062 static struct value
*
8063 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8065 const int *reg_p
= (const int *) baton
;
8066 return value_of_register (*reg_p
, frame
);
8069 static struct gdbarch
*
8070 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8072 struct gdbarch
*gdbarch
;
8073 struct gdbarch_tdep
*tdep
;
8075 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8077 enum mips_fpu_type fpu_type
;
8078 struct tdesc_arch_data
*tdesc_data
= NULL
;
8079 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8080 const char **reg_names
;
8081 struct mips_regnum mips_regnum
, *regnum
;
8082 enum mips_isa mips_isa
;
8086 /* First of all, extract the elf_flags, if available. */
8087 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8088 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8089 else if (arches
!= NULL
)
8090 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8094 fprintf_unfiltered (gdb_stdlog
,
8095 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8097 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8098 switch ((elf_flags
& EF_MIPS_ABI
))
8100 case E_MIPS_ABI_O32
:
8101 found_abi
= MIPS_ABI_O32
;
8103 case E_MIPS_ABI_O64
:
8104 found_abi
= MIPS_ABI_O64
;
8106 case E_MIPS_ABI_EABI32
:
8107 found_abi
= MIPS_ABI_EABI32
;
8109 case E_MIPS_ABI_EABI64
:
8110 found_abi
= MIPS_ABI_EABI64
;
8113 if ((elf_flags
& EF_MIPS_ABI2
))
8114 found_abi
= MIPS_ABI_N32
;
8116 found_abi
= MIPS_ABI_UNKNOWN
;
8120 /* GCC creates a pseudo-section whose name describes the ABI. */
8121 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8122 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8124 /* If we have no useful BFD information, use the ABI from the last
8125 MIPS architecture (if there is one). */
8126 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8127 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8129 /* Try the architecture for any hint of the correct ABI. */
8130 if (found_abi
== MIPS_ABI_UNKNOWN
8131 && info
.bfd_arch_info
!= NULL
8132 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8134 switch (info
.bfd_arch_info
->mach
)
8136 case bfd_mach_mips3900
:
8137 found_abi
= MIPS_ABI_EABI32
;
8139 case bfd_mach_mips4100
:
8140 case bfd_mach_mips5000
:
8141 found_abi
= MIPS_ABI_EABI64
;
8143 case bfd_mach_mips8000
:
8144 case bfd_mach_mips10000
:
8145 /* On Irix, ELF64 executables use the N64 ABI. The
8146 pseudo-sections which describe the ABI aren't present
8147 on IRIX. (Even for executables created by gcc.) */
8148 if (info
.abfd
!= NULL
8149 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8150 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8151 found_abi
= MIPS_ABI_N64
;
8153 found_abi
= MIPS_ABI_N32
;
8158 /* Default 64-bit objects to N64 instead of O32. */
8159 if (found_abi
== MIPS_ABI_UNKNOWN
8160 && info
.abfd
!= NULL
8161 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8162 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8163 found_abi
= MIPS_ABI_N64
;
8166 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8169 /* What has the user specified from the command line? */
8170 wanted_abi
= global_mips_abi ();
8172 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8175 /* Now that we have found what the ABI for this binary would be,
8176 check whether the user is overriding it. */
8177 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8178 mips_abi
= wanted_abi
;
8179 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8180 mips_abi
= found_abi
;
8182 mips_abi
= MIPS_ABI_O32
;
8184 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8187 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8188 if (mips_abi
!= MIPS_ABI_EABI32
8189 && mips_abi
!= MIPS_ABI_O32
8190 && info
.bfd_arch_info
!= NULL
8191 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8192 && info
.bfd_arch_info
->bits_per_word
< 64)
8193 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8195 /* Determine the default compressed ISA. */
8196 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8197 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8198 mips_isa
= ISA_MICROMIPS
;
8199 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8200 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8201 mips_isa
= ISA_MIPS16
;
8203 mips_isa
= global_mips_compression ();
8204 mips_compression_string
= mips_compression_strings
[mips_isa
];
8206 /* Also used when doing an architecture lookup. */
8208 fprintf_unfiltered (gdb_stdlog
,
8209 "mips_gdbarch_init: "
8210 "mips64_transfers_32bit_regs_p = %d\n",
8211 mips64_transfers_32bit_regs_p
);
8213 /* Determine the MIPS FPU type. */
8216 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8217 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8218 Tag_GNU_MIPS_ABI_FP
);
8219 #endif /* HAVE_ELF */
8221 if (!mips_fpu_type_auto
)
8222 fpu_type
= mips_fpu_type
;
8223 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8225 switch (elf_fpu_type
)
8227 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8228 fpu_type
= MIPS_FPU_DOUBLE
;
8230 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8231 fpu_type
= MIPS_FPU_SINGLE
;
8233 case Val_GNU_MIPS_ABI_FP_SOFT
:
8235 /* Soft float or unknown. */
8236 fpu_type
= MIPS_FPU_NONE
;
8240 else if (info
.bfd_arch_info
!= NULL
8241 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8242 switch (info
.bfd_arch_info
->mach
)
8244 case bfd_mach_mips3900
:
8245 case bfd_mach_mips4100
:
8246 case bfd_mach_mips4111
:
8247 case bfd_mach_mips4120
:
8248 fpu_type
= MIPS_FPU_NONE
;
8250 case bfd_mach_mips4650
:
8251 fpu_type
= MIPS_FPU_SINGLE
;
8254 fpu_type
= MIPS_FPU_DOUBLE
;
8257 else if (arches
!= NULL
)
8258 fpu_type
= MIPS_FPU_TYPE (arches
->gdbarch
);
8260 fpu_type
= MIPS_FPU_DOUBLE
;
8262 fprintf_unfiltered (gdb_stdlog
,
8263 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8265 /* Check for blatant incompatibilities. */
8267 /* If we have only 32-bit registers, then we can't debug a 64-bit
8269 if (info
.target_desc
8270 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8271 && mips_abi
!= MIPS_ABI_EABI32
8272 && mips_abi
!= MIPS_ABI_O32
)
8275 /* Fill in the OS dependent register numbers and names. */
8276 if (info
.osabi
== GDB_OSABI_LINUX
)
8278 mips_regnum
.fp0
= 38;
8279 mips_regnum
.pc
= 37;
8280 mips_regnum
.cause
= 36;
8281 mips_regnum
.badvaddr
= 35;
8282 mips_regnum
.hi
= 34;
8283 mips_regnum
.lo
= 33;
8284 mips_regnum
.fp_control_status
= 70;
8285 mips_regnum
.fp_implementation_revision
= 71;
8286 mips_regnum
.dspacc
= -1;
8287 mips_regnum
.dspctl
= -1;
8291 reg_names
= mips_linux_reg_names
;
8295 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8296 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8297 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8298 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8299 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8300 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8301 mips_regnum
.fp_control_status
= 70;
8302 mips_regnum
.fp_implementation_revision
= 71;
8303 mips_regnum
.dspacc
= dspacc
= -1;
8304 mips_regnum
.dspctl
= dspctl
= -1;
8305 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8306 if (info
.bfd_arch_info
!= NULL
8307 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8308 reg_names
= mips_tx39_reg_names
;
8310 reg_names
= mips_generic_reg_names
;
8313 /* Check any target description for validity. */
8314 if (tdesc_has_registers (info
.target_desc
))
8316 static const char *const mips_gprs
[] = {
8317 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8318 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8319 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8320 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8322 static const char *const mips_fprs
[] = {
8323 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8324 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8325 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8326 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8329 const struct tdesc_feature
*feature
;
8332 feature
= tdesc_find_feature (info
.target_desc
,
8333 "org.gnu.gdb.mips.cpu");
8334 if (feature
== NULL
)
8337 tdesc_data
= tdesc_data_alloc ();
8340 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8341 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8345 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8346 mips_regnum
.lo
, "lo");
8347 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8348 mips_regnum
.hi
, "hi");
8349 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8350 mips_regnum
.pc
, "pc");
8354 tdesc_data_cleanup (tdesc_data
);
8358 feature
= tdesc_find_feature (info
.target_desc
,
8359 "org.gnu.gdb.mips.cp0");
8360 if (feature
== NULL
)
8362 tdesc_data_cleanup (tdesc_data
);
8367 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8368 mips_regnum
.badvaddr
, "badvaddr");
8369 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8370 MIPS_PS_REGNUM
, "status");
8371 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8372 mips_regnum
.cause
, "cause");
8376 tdesc_data_cleanup (tdesc_data
);
8380 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8381 backend is not prepared for that, though. */
8382 feature
= tdesc_find_feature (info
.target_desc
,
8383 "org.gnu.gdb.mips.fpu");
8384 if (feature
== NULL
)
8386 tdesc_data_cleanup (tdesc_data
);
8391 for (i
= 0; i
< 32; i
++)
8392 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8393 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8395 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8396 mips_regnum
.fp_control_status
,
8399 &= tdesc_numbered_register (feature
, tdesc_data
,
8400 mips_regnum
.fp_implementation_revision
,
8405 tdesc_data_cleanup (tdesc_data
);
8409 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8413 feature
= tdesc_find_feature (info
.target_desc
,
8414 "org.gnu.gdb.mips.dsp");
8415 /* The DSP registers are optional; it's OK if they are absent. */
8416 if (feature
!= NULL
)
8420 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8421 dspacc
+ i
++, "hi1");
8422 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8423 dspacc
+ i
++, "lo1");
8424 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8425 dspacc
+ i
++, "hi2");
8426 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8427 dspacc
+ i
++, "lo2");
8428 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8429 dspacc
+ i
++, "hi3");
8430 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8431 dspacc
+ i
++, "lo3");
8433 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8438 tdesc_data_cleanup (tdesc_data
);
8442 mips_regnum
.dspacc
= dspacc
;
8443 mips_regnum
.dspctl
= dspctl
;
8445 num_regs
= mips_regnum
.dspctl
+ 1;
8449 /* It would be nice to detect an attempt to use a 64-bit ABI
8450 when only 32-bit registers are provided. */
8454 /* Try to find a pre-existing architecture. */
8455 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8457 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8459 /* MIPS needs to be pedantic about which ABI and the compressed
8460 ISA variation the object is using. */
8461 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8463 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8465 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8467 /* Need to be pedantic about which register virtual size is
8469 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8470 != mips64_transfers_32bit_regs_p
)
8472 /* Be pedantic about which FPU is selected. */
8473 if (MIPS_FPU_TYPE (arches
->gdbarch
) != fpu_type
)
8476 if (tdesc_data
!= NULL
)
8477 tdesc_data_cleanup (tdesc_data
);
8478 return arches
->gdbarch
;
8481 /* Need a new architecture. Fill in a target specific vector. */
8482 tdep
= XCNEW (struct gdbarch_tdep
);
8483 gdbarch
= gdbarch_alloc (&info
, tdep
);
8484 tdep
->elf_flags
= elf_flags
;
8485 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8486 tdep
->found_abi
= found_abi
;
8487 tdep
->mips_abi
= mips_abi
;
8488 tdep
->mips_isa
= mips_isa
;
8489 tdep
->mips_fpu_type
= fpu_type
;
8490 tdep
->register_size_valid_p
= 0;
8491 tdep
->register_size
= 0;
8493 if (info
.target_desc
)
8495 /* Some useful properties can be inferred from the target. */
8496 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8498 tdep
->register_size_valid_p
= 1;
8499 tdep
->register_size
= 4;
8501 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8503 tdep
->register_size_valid_p
= 1;
8504 tdep
->register_size
= 8;
8508 /* Initially set everything according to the default ABI/ISA. */
8509 set_gdbarch_short_bit (gdbarch
, 16);
8510 set_gdbarch_int_bit (gdbarch
, 32);
8511 set_gdbarch_float_bit (gdbarch
, 32);
8512 set_gdbarch_double_bit (gdbarch
, 64);
8513 set_gdbarch_long_double_bit (gdbarch
, 64);
8514 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8515 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8516 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8518 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8519 mips_ax_pseudo_register_collect
);
8520 set_gdbarch_ax_pseudo_register_push_stack
8521 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8523 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8524 mips_elf_make_msymbol_special
);
8525 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8526 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8527 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8529 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8530 *regnum
= mips_regnum
;
8531 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8532 set_gdbarch_num_regs (gdbarch
, num_regs
);
8533 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8534 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8535 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8536 tdep
->mips_processor_reg_names
= reg_names
;
8537 tdep
->regnum
= regnum
;
8542 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8543 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8544 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8545 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8546 tdep
->default_mask_address_p
= 0;
8547 set_gdbarch_long_bit (gdbarch
, 32);
8548 set_gdbarch_ptr_bit (gdbarch
, 32);
8549 set_gdbarch_long_long_bit (gdbarch
, 64);
8552 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8553 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8554 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8555 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8556 tdep
->default_mask_address_p
= 0;
8557 set_gdbarch_long_bit (gdbarch
, 32);
8558 set_gdbarch_ptr_bit (gdbarch
, 32);
8559 set_gdbarch_long_long_bit (gdbarch
, 64);
8561 case MIPS_ABI_EABI32
:
8562 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8563 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8564 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8565 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8566 tdep
->default_mask_address_p
= 0;
8567 set_gdbarch_long_bit (gdbarch
, 32);
8568 set_gdbarch_ptr_bit (gdbarch
, 32);
8569 set_gdbarch_long_long_bit (gdbarch
, 64);
8571 case MIPS_ABI_EABI64
:
8572 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8573 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8574 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8575 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8576 tdep
->default_mask_address_p
= 0;
8577 set_gdbarch_long_bit (gdbarch
, 64);
8578 set_gdbarch_ptr_bit (gdbarch
, 64);
8579 set_gdbarch_long_long_bit (gdbarch
, 64);
8582 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8583 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8584 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8585 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8586 tdep
->default_mask_address_p
= 0;
8587 set_gdbarch_long_bit (gdbarch
, 32);
8588 set_gdbarch_ptr_bit (gdbarch
, 32);
8589 set_gdbarch_long_long_bit (gdbarch
, 64);
8590 set_gdbarch_long_double_bit (gdbarch
, 128);
8591 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8594 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8595 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8596 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8597 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8598 tdep
->default_mask_address_p
= 0;
8599 set_gdbarch_long_bit (gdbarch
, 64);
8600 set_gdbarch_ptr_bit (gdbarch
, 64);
8601 set_gdbarch_long_long_bit (gdbarch
, 64);
8602 set_gdbarch_long_double_bit (gdbarch
, 128);
8603 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8606 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8609 /* GCC creates a pseudo-section whose name specifies the size of
8610 longs, since -mlong32 or -mlong64 may be used independent of
8611 other options. How those options affect pointer sizes is ABI and
8612 architecture dependent, so use them to override the default sizes
8613 set by the ABI. This table shows the relationship between ABI,
8614 -mlongXX, and size of pointers:
8616 ABI -mlongXX ptr bits
8617 --- -------- --------
8631 Note that for o32 and eabi32, pointers are always 32 bits
8632 regardless of any -mlongXX option. For all others, pointers and
8633 longs are the same, as set by -mlongXX or set by defaults. */
8635 if (info
.abfd
!= NULL
)
8639 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8642 set_gdbarch_long_bit (gdbarch
, long_bit
);
8646 case MIPS_ABI_EABI32
:
8651 case MIPS_ABI_EABI64
:
8652 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8655 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8660 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8661 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8664 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8665 flag in object files because to do so would make it impossible to
8666 link with libraries compiled without "-gp32". This is
8667 unnecessarily restrictive.
8669 We could solve this problem by adding "-gp32" multilibs to gcc,
8670 but to set this flag before gcc is built with such multilibs will
8671 break too many systems.''
8673 But even more unhelpfully, the default linker output target for
8674 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8675 for 64-bit programs - you need to change the ABI to change this,
8676 and not all gcc targets support that currently. Therefore using
8677 this flag to detect 32-bit mode would do the wrong thing given
8678 the current gcc - it would make GDB treat these 64-bit programs
8679 as 32-bit programs by default. */
8681 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8682 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8684 /* Add/remove bits from an address. The MIPS needs be careful to
8685 ensure that all 32 bit addresses are sign extended to 64 bits. */
8686 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8688 /* Unwind the frame. */
8689 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8690 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8691 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8693 /* Map debug register numbers onto internal register numbers. */
8694 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8695 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8696 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8697 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8698 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8699 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8701 /* MIPS version of CALL_DUMMY. */
8703 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8704 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8705 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8707 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8709 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8710 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8711 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8713 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8714 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8715 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8716 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8717 mips_adjust_breakpoint_address
);
8719 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8721 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8723 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8724 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8725 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8727 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8729 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8731 if (mips_abi
== MIPS_ABI_N32
)
8732 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8733 else if (mips_abi
== MIPS_ABI_N64
)
8734 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8736 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8738 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8739 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8740 need to all be folded into the target vector. Since they are
8741 being used as guards for target_stopped_by_watchpoint, why not have
8742 target_stopped_by_watchpoint return the type of watchpoint that the code
8744 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8746 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8748 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8749 to support MIPS16. This is a bad thing. Make sure not to do it
8750 if we have an OS ABI that actually supports shared libraries, since
8751 shared library support is more important. If we have an OS someday
8752 that supports both shared libraries and MIPS16, we'll have to find
8753 a better place for these.
8754 macro/2012-04-25: But that applies to return trampolines only and
8755 currently no MIPS OS ABI uses shared libraries that have them. */
8756 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8758 set_gdbarch_single_step_through_delay (gdbarch
,
8759 mips_single_step_through_delay
);
8761 /* Virtual tables. */
8762 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8764 mips_register_g_packet_guesses (gdbarch
);
8766 /* Hook in OS ABI-specific overrides, if they have been registered. */
8767 info
.tdesc_data
= tdesc_data
;
8768 gdbarch_init_osabi (info
, gdbarch
);
8770 /* The hook may have adjusted num_regs, fetch the final value and
8771 set pc_regnum and sp_regnum now that it has been fixed. */
8772 num_regs
= gdbarch_num_regs (gdbarch
);
8773 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8774 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8776 /* Unwind the frame. */
8777 dwarf2_append_unwinders (gdbarch
);
8778 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8779 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8780 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8781 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8782 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8783 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8784 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8785 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8786 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8790 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8791 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8793 /* Override the normal target description methods to handle our
8794 dual real and pseudo registers. */
8795 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8796 set_gdbarch_register_reggroup_p (gdbarch
,
8797 mips_tdesc_register_reggroup_p
);
8799 num_regs
= gdbarch_num_regs (gdbarch
);
8800 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8801 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8802 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8805 /* Add ABI-specific aliases for the registers. */
8806 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8807 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8808 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8809 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8811 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8812 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8813 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8815 /* Add some other standard aliases. */
8816 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8817 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8818 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8820 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8821 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8822 value_of_mips_user_reg
,
8823 &mips_numeric_register_aliases
[i
].regnum
);
8829 mips_abi_update (const char *ignore_args
,
8830 int from_tty
, struct cmd_list_element
*c
)
8832 struct gdbarch_info info
;
8834 /* Force the architecture to update, and (if it's a MIPS architecture)
8835 mips_gdbarch_init will take care of the rest. */
8836 gdbarch_info_init (&info
);
8837 gdbarch_update_p (info
);
8840 /* Print out which MIPS ABI is in use. */
8843 show_mips_abi (struct ui_file
*file
,
8845 struct cmd_list_element
*ignored_cmd
,
8846 const char *ignored_value
)
8848 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8851 "The MIPS ABI is unknown because the current architecture "
8855 enum mips_abi global_abi
= global_mips_abi ();
8856 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8857 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8859 if (global_abi
== MIPS_ABI_UNKNOWN
)
8862 "The MIPS ABI is set automatically (currently \"%s\").\n",
8864 else if (global_abi
== actual_abi
)
8867 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8871 /* Probably shouldn't happen... */
8872 fprintf_filtered (file
,
8873 "The (auto detected) MIPS ABI \"%s\" is in use "
8874 "even though the user setting was \"%s\".\n",
8875 actual_abi_str
, mips_abi_strings
[global_abi
]);
8880 /* Print out which MIPS compressed ISA encoding is used. */
8883 show_mips_compression (struct ui_file
*file
, int from_tty
,
8884 struct cmd_list_element
*c
, const char *value
)
8886 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8890 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8893 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8899 case MIPS_FPU_SINGLE
:
8901 case MIPS_FPU_DOUBLE
:
8909 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8911 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8915 int ef_mips_32bitmode
;
8916 /* Determine the ISA. */
8917 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8935 /* Determine the size of a pointer. */
8936 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8937 fprintf_unfiltered (file
,
8938 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8940 fprintf_unfiltered (file
,
8941 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8943 fprintf_unfiltered (file
,
8944 "mips_dump_tdep: ef_mips_arch = %d\n",
8946 fprintf_unfiltered (file
,
8947 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8948 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8949 fprintf_unfiltered (file
,
8951 "mips_mask_address_p() %d (default %d)\n",
8952 mips_mask_address_p (tdep
),
8953 tdep
->default_mask_address_p
);
8955 fprintf_unfiltered (file
,
8956 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8957 MIPS_DEFAULT_FPU_TYPE
,
8958 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8959 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8960 MIPS_EABI (gdbarch
));
8961 fprintf_unfiltered (file
,
8962 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8963 MIPS_FPU_TYPE (gdbarch
),
8964 mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch
)));
8968 _initialize_mips_tdep (void)
8970 static struct cmd_list_element
*mipsfpulist
= NULL
;
8972 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8973 if (MIPS_ABI_LAST
+ 1
8974 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8975 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8977 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8979 mips_pdr_data
= register_objfile_data ();
8981 /* Create feature sets with the appropriate properties. The values
8982 are not important. */
8983 mips_tdesc_gp32
= allocate_target_description ();
8984 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8986 mips_tdesc_gp64
= allocate_target_description ();
8987 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8989 /* Add root prefix command for all "set mips"/"show mips" commands. */
8990 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8991 _("Various MIPS specific commands."),
8992 &setmipscmdlist
, "set mips ", 0, &setlist
);
8994 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8995 _("Various MIPS specific commands."),
8996 &showmipscmdlist
, "show mips ", 0, &showlist
);
8998 /* Allow the user to override the ABI. */
8999 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9000 &mips_abi_string
, _("\
9001 Set the MIPS ABI used by this program."), _("\
9002 Show the MIPS ABI used by this program."), _("\
9003 This option can be set to one of:\n\
9004 auto - the default ABI associated with the current binary\n\
9013 &setmipscmdlist
, &showmipscmdlist
);
9015 /* Allow the user to set the ISA to assume for compressed code if ELF
9016 file flags don't tell or there is no program file selected. This
9017 setting is updated whenever unambiguous ELF file flags are interpreted,
9018 and carried over to subsequent sessions. */
9019 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9020 &mips_compression_string
, _("\
9021 Set the compressed ISA encoding used by MIPS code."), _("\
9022 Show the compressed ISA encoding used by MIPS code."), _("\
9023 Select the compressed ISA encoding used in functions that have no symbol\n\
9024 information available. The encoding can be set to either of:\n\
9027 and is updated automatically from ELF file flags if available."),
9029 show_mips_compression
,
9030 &setmipscmdlist
, &showmipscmdlist
);
9032 /* Let the user turn off floating point and set the fence post for
9033 heuristic_proc_start. */
9035 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9036 _("Set use of MIPS floating-point coprocessor."),
9037 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9038 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9039 _("Select single-precision MIPS floating-point coprocessor."),
9041 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9042 _("Select double-precision MIPS floating-point coprocessor."),
9044 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9045 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9046 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9047 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9048 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9049 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9050 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9051 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9052 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9053 _("Select MIPS floating-point coprocessor automatically."),
9055 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9056 _("Show current use of MIPS floating-point coprocessor target."),
9059 /* We really would like to have both "0" and "unlimited" work, but
9060 command.c doesn't deal with that. So make it a var_zinteger
9061 because the user can always use "999999" or some such for unlimited. */
9062 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9063 &heuristic_fence_post
, _("\
9064 Set the distance searched for the start of a function."), _("\
9065 Show the distance searched for the start of a function."), _("\
9066 If you are debugging a stripped executable, GDB needs to search through the\n\
9067 program for the start of a function. This command sets the distance of the\n\
9068 search. The only need to set it is when debugging a stripped executable."),
9069 reinit_frame_cache_sfunc
,
9070 NULL
, /* FIXME: i18n: The distance searched for
9071 the start of a function is %s. */
9072 &setlist
, &showlist
);
9074 /* Allow the user to control whether the upper bits of 64-bit
9075 addresses should be zeroed. */
9076 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9077 &mask_address_var
, _("\
9078 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9079 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9080 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9081 allow GDB to determine the correct value."),
9082 NULL
, show_mask_address
,
9083 &setmipscmdlist
, &showmipscmdlist
);
9085 /* Allow the user to control the size of 32 bit registers within the
9086 raw remote packet. */
9087 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9088 &mips64_transfers_32bit_regs_p
, _("\
9089 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9091 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9093 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9094 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9095 64 bits for others. Use \"off\" to disable compatibility mode"),
9096 set_mips64_transfers_32bit_regs
,
9097 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9098 MIPS target that transfers 32-bit
9099 quantities is %s. */
9100 &setlist
, &showlist
);
9102 /* Debug this files internals. */
9103 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9105 Set mips debugging."), _("\
9106 Show mips debugging."), _("\
9107 When non-zero, mips specific debugging is enabled."),
9109 NULL
, /* FIXME: i18n: Mips debugging is
9111 &setdebuglist
, &showdebuglist
);