1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
54 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
55 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
57 /* A useful bit in the CP0 status register (PS_REGNUM). */
58 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
59 #define ST0_FR (1 << 26)
61 /* The sizes of floating point registers. */
65 MIPS_FPU_SINGLE_REGSIZE
= 4,
66 MIPS_FPU_DOUBLE_REGSIZE
= 8
70 static const char *mips_abi_string
;
72 static const char *mips_abi_strings
[] = {
83 struct frame_extra_info
85 mips_extra_func_info_t proc_desc
;
89 /* Various MIPS ISA options (related to stack analysis) can be
90 overridden dynamically. Establish an enum/array for managing
93 static const char size_auto
[] = "auto";
94 static const char size_32
[] = "32";
95 static const char size_64
[] = "64";
97 static const char *size_enums
[] = {
104 /* Some MIPS boards don't support floating point while others only
105 support single-precision floating-point operations. See also
106 FP_REGISTER_DOUBLE. */
110 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
111 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
112 MIPS_FPU_NONE
/* No floating point. */
115 #ifndef MIPS_DEFAULT_FPU_TYPE
116 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
118 static int mips_fpu_type_auto
= 1;
119 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
121 static int mips_debug
= 0;
123 /* MIPS specific per-architecture information */
126 /* from the elf header */
130 enum mips_abi mips_abi
;
131 enum mips_abi found_abi
;
132 enum mips_fpu_type mips_fpu_type
;
133 int mips_last_arg_regnum
;
134 int mips_last_fp_arg_regnum
;
135 int mips_default_saved_regsize
;
136 int mips_fp_register_double
;
137 int mips_default_stack_argsize
;
138 int default_mask_address_p
;
139 /* Is the target using 64-bit raw integer registers but only
140 storing a left-aligned 32-bit value in each? */
141 int mips64_transfers_32bit_regs_p
;
142 /* Indexes for various registers. IRIX and embedded have
143 different values. This contains the "public" fields. Don't
144 add any that do not need to be public. */
145 const struct mips_regnum
*regnum
;
146 /* Register names table for the current register set. */
147 const char **mips_processor_reg_names
;
150 const struct mips_regnum
*
151 mips_regnum (struct gdbarch
*gdbarch
)
153 return gdbarch_tdep (gdbarch
)->regnum
;
157 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
159 return mips_regnum (gdbarch
)->fp0
+ 12;
162 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
163 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
165 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
167 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
169 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
171 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
172 functions to test, set, or clear bit 0 of addresses. */
175 is_mips16_addr (CORE_ADDR addr
)
181 make_mips16_addr (CORE_ADDR addr
)
187 unmake_mips16_addr (CORE_ADDR addr
)
189 return ((addr
) & ~1);
192 /* Return the contents of register REGNUM as a signed integer. */
195 read_signed_register (int regnum
)
197 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
198 deprecated_read_register_gen (regnum
, buf
);
199 return (extract_signed_integer (buf
, register_size (current_gdbarch
, regnum
)));
203 read_signed_register_pid (int regnum
, ptid_t ptid
)
208 if (ptid_equal (ptid
, inferior_ptid
))
209 return read_signed_register (regnum
);
211 save_ptid
= inferior_ptid
;
213 inferior_ptid
= ptid
;
215 retval
= read_signed_register (regnum
);
217 inferior_ptid
= save_ptid
;
222 /* Return the MIPS ABI associated with GDBARCH. */
224 mips_abi (struct gdbarch
*gdbarch
)
226 return gdbarch_tdep (gdbarch
)->mips_abi
;
230 mips_regsize (struct gdbarch
*gdbarch
)
232 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
233 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
236 /* Return the currently configured (or set) saved register size. */
238 static const char *mips_saved_regsize_string
= size_auto
;
241 mips_saved_regsize (struct gdbarch_tdep
*tdep
)
243 if (mips_saved_regsize_string
== size_auto
)
244 return tdep
->mips_default_saved_regsize
;
245 else if (mips_saved_regsize_string
== size_64
)
247 else /* if (mips_saved_regsize_string == size_32) */
251 /* Functions for setting and testing a bit in a minimal symbol that
252 marks it as 16-bit function. The MSB of the minimal symbol's
253 "info" field is used for this purpose.
255 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
256 i.e. refers to a 16-bit function, and sets a "special" bit in a
257 minimal symbol to mark it as a 16-bit function
259 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
262 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
264 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
266 MSYMBOL_INFO (msym
) = (char *)
267 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
268 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
273 msymbol_is_special (struct minimal_symbol
*msym
)
275 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
278 /* XFER a value from the big/little/left end of the register.
279 Depending on the size of the value it might occupy the entire
280 register or just part of it. Make an allowance for this, aligning
281 things accordingly. */
284 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
285 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
288 bfd_byte reg
[MAX_REGISTER_SIZE
];
290 gdb_assert (reg_num
>= NUM_REGS
);
291 /* Need to transfer the left or right part of the register, based on
292 the targets byte order. */
296 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
298 case BFD_ENDIAN_LITTLE
:
301 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
305 internal_error (__FILE__
, __LINE__
, "bad switch");
308 fprintf_unfiltered (gdb_stderr
,
309 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
310 reg_num
, reg_offset
, buf_offset
, length
);
311 if (mips_debug
&& out
!= NULL
)
314 fprintf_unfiltered (gdb_stdlog
, "out ");
315 for (i
= 0; i
< length
; i
++)
316 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
319 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
321 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
322 if (mips_debug
&& in
!= NULL
)
325 fprintf_unfiltered (gdb_stdlog
, "in ");
326 for (i
= 0; i
< length
; i
++)
327 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
330 fprintf_unfiltered (gdb_stdlog
, "\n");
333 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
334 compatiblity mode. A return value of 1 means that we have
335 physical 64-bit registers, but should treat them as 32-bit registers. */
338 mips2_fp_compat (void)
340 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
342 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 4)
346 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
347 in all the places we deal with FP registers. PR gdb/413. */
348 /* Otherwise check the FR bit in the status register - it controls
349 the FP compatiblity mode. If it is clear we are in compatibility
351 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
358 /* Indicate that the ABI makes use of double-precision registers
359 provided by the FPU (rather than combining pairs of registers to
360 form double-precision values). See also MIPS_FPU_TYPE. */
361 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
363 /* The amount of space reserved on the stack for registers. This is
364 different to MIPS_SAVED_REGSIZE as it determines the alignment of
365 data allocated after the registers have run out. */
367 static const char *mips_stack_argsize_string
= size_auto
;
370 mips_stack_argsize (struct gdbarch_tdep
*tdep
)
372 if (mips_stack_argsize_string
== size_auto
)
373 return tdep
->mips_default_stack_argsize
;
374 else if (mips_stack_argsize_string
== size_64
)
376 else /* if (mips_stack_argsize_string == size_32) */
380 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
382 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
383 struct frame_info
*, int);
385 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
387 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
389 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
391 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
392 struct frame_info
*next_frame
,
395 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
396 mips_extra_func_info_t proc_desc
);
398 static struct type
*mips_float_register_type (void);
399 static struct type
*mips_double_register_type (void);
401 /* The list of available "set mips " and "show mips " commands */
403 static struct cmd_list_element
*setmipscmdlist
= NULL
;
404 static struct cmd_list_element
*showmipscmdlist
= NULL
;
406 /* Integer registers 0 thru 31 are handled explicitly by
407 mips_register_name(). Processor specific registers 32 and above
408 are listed in the followign tables. */
410 enum { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
414 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
415 "sr", "lo", "hi", "bad", "cause","pc",
416 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
417 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
418 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
419 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
420 "fsr", "fir", ""/*"fp"*/, "",
421 "", "", "", "", "", "", "", "",
422 "", "", "", "", "", "", "", "",
425 /* Names of IDT R3041 registers. */
427 static const char *mips_r3041_reg_names
[] = {
428 "sr", "lo", "hi", "bad", "cause","pc",
429 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
430 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
431 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
432 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
433 "fsr", "fir", "",/*"fp"*/ "",
434 "", "", "bus", "ccfg", "", "", "", "",
435 "", "", "port", "cmp", "", "", "epc", "prid",
438 /* Names of tx39 registers. */
440 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
441 "sr", "lo", "hi", "bad", "cause","pc",
442 "", "", "", "", "", "", "", "",
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
447 "", "", "", "", "", "", "", "",
448 "", "", "config", "cache", "debug", "depc", "epc", ""
451 /* Names of IRIX registers. */
452 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
453 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
454 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
455 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
456 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
457 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
461 /* Return the name of the register corresponding to REGNO. */
463 mips_register_name (int regno
)
465 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
466 /* GPR names for all ABIs other than n32/n64. */
467 static char *mips_gpr_names
[] = {
468 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
469 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
470 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
471 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
474 /* GPR names for n32 and n64 ABIs. */
475 static char *mips_n32_n64_gpr_names
[] = {
476 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
477 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
478 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
479 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
482 enum mips_abi abi
= mips_abi (current_gdbarch
);
484 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
485 don't make the raw register names visible. */
486 int rawnum
= regno
% NUM_REGS
;
487 if (regno
< NUM_REGS
)
490 /* The MIPS integer registers are always mapped from 0 to 31. The
491 names of the registers (which reflects the conventions regarding
492 register use) vary depending on the ABI. */
493 if (0 <= rawnum
&& rawnum
< 32)
495 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
496 return mips_n32_n64_gpr_names
[rawnum
];
498 return mips_gpr_names
[rawnum
];
500 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
502 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
503 return tdep
->mips_processor_reg_names
[rawnum
- 32];
506 internal_error (__FILE__
, __LINE__
,
507 "mips_register_name: bad register number %d", rawnum
);
510 /* Return the groups that a MIPS register can be categorised into. */
513 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
514 struct reggroup
*reggroup
)
519 int rawnum
= regnum
% NUM_REGS
;
520 int pseudo
= regnum
/ NUM_REGS
;
521 if (reggroup
== all_reggroup
)
523 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
524 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
525 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
526 (gdbarch), as not all architectures are multi-arch. */
527 raw_p
= rawnum
< NUM_REGS
;
528 if (REGISTER_NAME (regnum
) == NULL
529 || REGISTER_NAME (regnum
)[0] == '\0')
531 if (reggroup
== float_reggroup
)
532 return float_p
&& pseudo
;
533 if (reggroup
== vector_reggroup
)
534 return vector_p
&& pseudo
;
535 if (reggroup
== general_reggroup
)
536 return (!vector_p
&& !float_p
) && pseudo
;
537 /* Save the pseudo registers. Need to make certain that any code
538 extracting register values from a saved register cache also uses
540 if (reggroup
== save_reggroup
)
541 return raw_p
&& pseudo
;
542 /* Restore the same pseudo register. */
543 if (reggroup
== restore_reggroup
)
544 return raw_p
&& pseudo
;
548 /* Map the symbol table registers which live in the range [1 *
549 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
550 registers. Take care of alignment and size problems. */
553 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
554 int cookednum
, void *buf
)
556 int rawnum
= cookednum
% NUM_REGS
;
557 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
558 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
559 regcache_raw_read (regcache
, rawnum
, buf
);
560 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
562 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
563 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
564 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
566 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
569 internal_error (__FILE__
, __LINE__
, "bad register size");
573 mips_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
574 int cookednum
, const void *buf
)
576 int rawnum
= cookednum
% NUM_REGS
;
577 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
578 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
579 regcache_raw_write (regcache
, rawnum
, buf
);
580 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
582 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
583 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
584 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
586 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
589 internal_error (__FILE__
, __LINE__
, "bad register size");
592 /* Table to translate MIPS16 register field to actual register number. */
593 static int mips16_to_32_reg
[8] =
594 {16, 17, 2, 3, 4, 5, 6, 7};
596 /* Heuristic_proc_start may hunt through the text section for a long
597 time across a 2400 baud serial line. Allows the user to limit this
600 static unsigned int heuristic_fence_post
= 0;
602 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
603 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
604 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
605 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
606 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
607 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
608 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
609 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
610 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
611 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
612 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
613 this will corrupt pdr.iline. Fortunately we don't use it. */
614 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
615 #define _PROC_MAGIC_ 0x0F0F0F0F
616 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
617 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
619 struct linked_proc_info
621 struct mips_extra_func_info info
;
622 struct linked_proc_info
*next
;
624 *linked_proc_desc_table
= NULL
;
626 /* Number of bytes of storage in the actual machine representation for
627 register N. NOTE: This defines the pseudo register type so need to
628 rebuild the architecture vector. */
630 static int mips64_transfers_32bit_regs_p
= 0;
633 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
634 struct cmd_list_element
*c
)
636 struct gdbarch_info info
;
637 gdbarch_info_init (&info
);
638 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
639 instead of relying on globals. Doing that would let generic code
640 handle the search for this specific architecture. */
641 if (!gdbarch_update_p (info
))
643 mips64_transfers_32bit_regs_p
= 0;
644 error ("32-bit compatibility mode not supported");
648 /* Convert to/from a register and the corresponding memory value. */
651 mips_convert_register_p (int regnum
, struct type
*type
)
653 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
654 && register_size (current_gdbarch
, regnum
) == 4
655 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
656 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
657 && TYPE_CODE(type
) == TYPE_CODE_FLT
658 && TYPE_LENGTH(type
) == 8);
662 mips_register_to_value (struct frame_info
*frame
, int regnum
,
663 struct type
*type
, void *to
)
665 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
666 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
670 mips_value_to_register (struct frame_info
*frame
, int regnum
,
671 struct type
*type
, const void *from
)
673 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
674 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
677 /* Return the GDB type object for the "standard" data type of data in
681 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
683 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
684 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
685 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
687 /* The floating-point registers raw, or cooked, always match
688 mips_regsize(), and also map 1:1, byte for byte. */
689 switch (gdbarch_byte_order (gdbarch
))
692 if (mips_regsize (gdbarch
) == 4)
693 return builtin_type_ieee_single_big
;
695 return builtin_type_ieee_double_big
;
696 case BFD_ENDIAN_LITTLE
:
697 if (mips_regsize (gdbarch
) == 4)
698 return builtin_type_ieee_single_little
;
700 return builtin_type_ieee_double_little
;
701 case BFD_ENDIAN_UNKNOWN
:
703 internal_error (__FILE__
, __LINE__
, "bad switch");
706 else if (regnum
>= (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
707 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
708 /* The pseudo/cooked view of the embedded registers is always
709 32-bit. The raw view is handled below. */
710 return builtin_type_int32
;
711 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
712 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
713 /* The target, while using a 64-bit register buffer, is only
714 transfering 32-bits of each integer register. Reflect this in
715 the cooked/pseudo register value. */
716 return builtin_type_int32
;
717 else if (mips_regsize (gdbarch
) == 8)
719 return builtin_type_int64
;
722 return builtin_type_int32
;
725 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
730 return read_signed_register (SP_REGNUM
);
733 /* Should the upper word of 64-bit addresses be zeroed? */
734 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
737 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
739 switch (mask_address_var
)
741 case AUTO_BOOLEAN_TRUE
:
743 case AUTO_BOOLEAN_FALSE
:
746 case AUTO_BOOLEAN_AUTO
:
747 return tdep
->default_mask_address_p
;
749 internal_error (__FILE__
, __LINE__
,
750 "mips_mask_address_p: bad switch");
756 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
758 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
759 switch (mask_address_var
)
761 case AUTO_BOOLEAN_TRUE
:
762 printf_filtered ("The 32 bit mips address mask is enabled\n");
764 case AUTO_BOOLEAN_FALSE
:
765 printf_filtered ("The 32 bit mips address mask is disabled\n");
767 case AUTO_BOOLEAN_AUTO
:
768 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
769 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
772 internal_error (__FILE__
, __LINE__
,
773 "show_mask_address: bad switch");
778 /* Should call_function allocate stack space for a struct return? */
781 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
783 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
784 return (TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
));
787 /* Should call_function pass struct by reference?
788 For each architecture, structs are passed either by
789 value or by reference, depending on their size. */
792 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
794 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
795 int len
= TYPE_LENGTH (check_typedef (type
));
796 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
798 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
799 return (len
> mips_saved_regsize (tdep
));
804 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
807 pc_is_mips16 (bfd_vma memaddr
)
809 struct minimal_symbol
*sym
;
811 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
812 if (is_mips16_addr (memaddr
))
815 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
816 the high bit of the info field. Use this to decide if the function is
817 MIPS16 or normal MIPS. */
818 sym
= lookup_minimal_symbol_by_pc (memaddr
);
820 return msymbol_is_special (sym
);
825 /* MIPS believes that the PC has a sign extended value. Perhaphs the
826 all registers should be sign extended for simplicity? */
829 mips_read_pc (ptid_t ptid
)
831 return read_signed_register_pid (PC_REGNUM
, ptid
);
834 /* This returns the PC of the first inst after the prologue. If we can't
835 find the prologue, then return 0. */
838 after_prologue (CORE_ADDR pc
,
839 mips_extra_func_info_t proc_desc
)
841 struct symtab_and_line sal
;
842 CORE_ADDR func_addr
, func_end
;
844 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
845 to read the stack pointer from the current machine state, because
846 the current machine state has nothing to do with the information
847 we need from the proc_desc; and the process may or may not exist
850 proc_desc
= find_proc_desc (pc
, NULL
, 0);
854 /* If function is frameless, then we need to do it the hard way. I
855 strongly suspect that frameless always means prologueless... */
856 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
857 && PROC_FRAME_OFFSET (proc_desc
) == 0)
861 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
862 return 0; /* Unknown */
864 sal
= find_pc_line (func_addr
, 0);
866 if (sal
.end
< func_end
)
869 /* The line after the prologue is after the end of the function. In this
870 case, tell the caller to find the prologue the hard way. */
875 /* Decode a MIPS32 instruction that saves a register in the stack, and
876 set the appropriate bit in the general register mask or float register mask
877 to indicate which register is saved. This is a helper function
878 for mips_find_saved_regs. */
881 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
882 unsigned long *float_mask
)
886 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
887 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
888 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
890 /* It might be possible to use the instruction to
891 find the offset, rather than the code below which
892 is based on things being in a certain order in the
893 frame, but figuring out what the instruction's offset
894 is relative to might be a little tricky. */
895 reg
= (inst
& 0x001f0000) >> 16;
896 *gen_mask
|= (1 << reg
);
898 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
899 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
900 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
903 reg
= ((inst
& 0x001f0000) >> 16);
904 *float_mask
|= (1 << reg
);
908 /* Decode a MIPS16 instruction that saves a register in the stack, and
909 set the appropriate bit in the general register or float register mask
910 to indicate which register is saved. This is a helper function
911 for mips_find_saved_regs. */
914 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
916 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
918 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
919 *gen_mask
|= (1 << reg
);
921 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
923 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
924 *gen_mask
|= (1 << reg
);
926 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
927 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
928 *gen_mask
|= (1 << RA_REGNUM
);
932 /* Fetch and return instruction from the specified location. If the PC
933 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
936 mips_fetch_instruction (CORE_ADDR addr
)
938 char buf
[MIPS_INSTLEN
];
942 if (pc_is_mips16 (addr
))
944 instlen
= MIPS16_INSTLEN
;
945 addr
= unmake_mips16_addr (addr
);
948 instlen
= MIPS_INSTLEN
;
949 status
= read_memory_nobpt (addr
, buf
, instlen
);
951 memory_error (status
, addr
);
952 return extract_unsigned_integer (buf
, instlen
);
956 /* These the fields of 32 bit mips instructions */
957 #define mips32_op(x) (x >> 26)
958 #define itype_op(x) (x >> 26)
959 #define itype_rs(x) ((x >> 21) & 0x1f)
960 #define itype_rt(x) ((x >> 16) & 0x1f)
961 #define itype_immediate(x) (x & 0xffff)
963 #define jtype_op(x) (x >> 26)
964 #define jtype_target(x) (x & 0x03ffffff)
966 #define rtype_op(x) (x >> 26)
967 #define rtype_rs(x) ((x >> 21) & 0x1f)
968 #define rtype_rt(x) ((x >> 16) & 0x1f)
969 #define rtype_rd(x) ((x >> 11) & 0x1f)
970 #define rtype_shamt(x) ((x >> 6) & 0x1f)
971 #define rtype_funct(x) (x & 0x3f)
974 mips32_relative_offset (unsigned long inst
)
977 x
= itype_immediate (inst
);
978 if (x
& 0x8000) /* sign bit set */
980 x
|= 0xffff0000; /* sign extension */
986 /* Determine whate to set a single step breakpoint while considering
989 mips32_next_pc (CORE_ADDR pc
)
993 inst
= mips_fetch_instruction (pc
);
994 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
996 if (itype_op (inst
) >> 2 == 5)
997 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
999 op
= (itype_op (inst
) & 0x03);
1009 goto greater_branch
;
1014 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1015 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1017 int tf
= itype_rt (inst
) & 0x01;
1018 int cnum
= itype_rt (inst
) >> 2;
1019 int fcrcs
= read_signed_register (mips_regnum (current_gdbarch
)->fp_control_status
);
1020 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1022 if (((cond
>> cnum
) & 0x01) == tf
)
1023 pc
+= mips32_relative_offset (inst
) + 4;
1028 pc
+= 4; /* Not a branch, next instruction is easy */
1031 { /* This gets way messy */
1033 /* Further subdivide into SPECIAL, REGIMM and other */
1034 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1036 case 0: /* SPECIAL */
1037 op
= rtype_funct (inst
);
1042 /* Set PC to that address */
1043 pc
= read_signed_register (rtype_rs (inst
));
1049 break; /* end SPECIAL */
1050 case 1: /* REGIMM */
1052 op
= itype_rt (inst
); /* branch condition */
1057 case 16: /* BLTZAL */
1058 case 18: /* BLTZALL */
1060 if (read_signed_register (itype_rs (inst
)) < 0)
1061 pc
+= mips32_relative_offset (inst
) + 4;
1063 pc
+= 8; /* after the delay slot */
1067 case 17: /* BGEZAL */
1068 case 19: /* BGEZALL */
1069 if (read_signed_register (itype_rs (inst
)) >= 0)
1070 pc
+= mips32_relative_offset (inst
) + 4;
1072 pc
+= 8; /* after the delay slot */
1074 /* All of the other instructions in the REGIMM category */
1079 break; /* end REGIMM */
1084 reg
= jtype_target (inst
) << 2;
1085 /* Upper four bits get never changed... */
1086 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1089 /* FIXME case JALX : */
1092 reg
= jtype_target (inst
) << 2;
1093 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1094 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1096 break; /* The new PC will be alternate mode */
1097 case 4: /* BEQ, BEQL */
1099 if (read_signed_register (itype_rs (inst
)) ==
1100 read_signed_register (itype_rt (inst
)))
1101 pc
+= mips32_relative_offset (inst
) + 4;
1105 case 5: /* BNE, BNEL */
1107 if (read_signed_register (itype_rs (inst
)) !=
1108 read_signed_register (itype_rt (inst
)))
1109 pc
+= mips32_relative_offset (inst
) + 4;
1113 case 6: /* BLEZ, BLEZL */
1114 if (read_signed_register (itype_rs (inst
) <= 0))
1115 pc
+= mips32_relative_offset (inst
) + 4;
1121 greater_branch
: /* BGTZ, BGTZL */
1122 if (read_signed_register (itype_rs (inst
) > 0))
1123 pc
+= mips32_relative_offset (inst
) + 4;
1130 } /* mips32_next_pc */
1132 /* Decoding the next place to set a breakpoint is irregular for the
1133 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1134 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1135 We dont want to set a single step instruction on the extend instruction
1139 /* Lots of mips16 instruction formats */
1140 /* Predicting jumps requires itype,ritype,i8type
1141 and their extensions extItype,extritype,extI8type
1143 enum mips16_inst_fmts
1145 itype
, /* 0 immediate 5,10 */
1146 ritype
, /* 1 5,3,8 */
1147 rrtype
, /* 2 5,3,3,5 */
1148 rritype
, /* 3 5,3,3,5 */
1149 rrrtype
, /* 4 5,3,3,3,2 */
1150 rriatype
, /* 5 5,3,3,1,4 */
1151 shifttype
, /* 6 5,3,3,3,2 */
1152 i8type
, /* 7 5,3,8 */
1153 i8movtype
, /* 8 5,3,3,5 */
1154 i8mov32rtype
, /* 9 5,3,5,3 */
1155 i64type
, /* 10 5,3,8 */
1156 ri64type
, /* 11 5,3,3,5 */
1157 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1158 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1159 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1160 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1161 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1162 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1163 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1164 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1165 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1166 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1168 /* I am heaping all the fields of the formats into one structure and
1169 then, only the fields which are involved in instruction extension */
1173 unsigned int regx
; /* Function in i8 type */
1178 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1179 for the bits which make up the immediatate extension. */
1182 extended_offset (unsigned int extension
)
1185 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1187 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1189 value
|= extension
& 0x01f; /* extract 4:0 */
1193 /* Only call this function if you know that this is an extendable
1194 instruction, It wont malfunction, but why make excess remote memory references?
1195 If the immediate operands get sign extended or somthing, do it after
1196 the extension is performed.
1198 /* FIXME: Every one of these cases needs to worry about sign extension
1199 when the offset is to be used in relative addressing */
1203 fetch_mips_16 (CORE_ADDR pc
)
1206 pc
&= 0xfffffffe; /* clear the low order bit */
1207 target_read_memory (pc
, buf
, 2);
1208 return extract_unsigned_integer (buf
, 2);
1212 unpack_mips16 (CORE_ADDR pc
,
1213 unsigned int extension
,
1215 enum mips16_inst_fmts insn_format
,
1216 struct upk_mips16
*upk
)
1221 switch (insn_format
)
1228 value
= extended_offset (extension
);
1229 value
= value
<< 11; /* rom for the original value */
1230 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1234 value
= inst
& 0x7ff;
1235 /* FIXME : Consider sign extension */
1244 { /* A register identifier and an offset */
1245 /* Most of the fields are the same as I type but the
1246 immediate value is of a different length */
1250 value
= extended_offset (extension
);
1251 value
= value
<< 8; /* from the original instruction */
1252 value
|= inst
& 0xff; /* eleven bits from instruction */
1253 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1254 if (value
& 0x4000) /* test the sign bit , bit 26 */
1256 value
&= ~0x3fff; /* remove the sign bit */
1262 value
= inst
& 0xff; /* 8 bits */
1263 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1264 /* FIXME: Do sign extension , this format needs it */
1265 if (value
& 0x80) /* THIS CONFUSES ME */
1267 value
&= 0xef; /* remove the sign bit */
1277 unsigned long value
;
1278 unsigned int nexthalf
;
1279 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1280 value
= value
<< 16;
1281 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1289 internal_error (__FILE__
, __LINE__
,
1292 upk
->offset
= offset
;
1299 add_offset_16 (CORE_ADDR pc
, int offset
)
1301 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1305 extended_mips16_next_pc (CORE_ADDR pc
,
1306 unsigned int extension
,
1309 int op
= (insn
>> 11);
1312 case 2: /* Branch */
1315 struct upk_mips16 upk
;
1316 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1317 offset
= upk
.offset
;
1323 pc
+= (offset
<< 1) + 2;
1326 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1328 struct upk_mips16 upk
;
1329 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1330 pc
= add_offset_16 (pc
, upk
.offset
);
1331 if ((insn
>> 10) & 0x01) /* Exchange mode */
1332 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1339 struct upk_mips16 upk
;
1341 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1342 reg
= read_signed_register (upk
.regx
);
1344 pc
+= (upk
.offset
<< 1) + 2;
1351 struct upk_mips16 upk
;
1353 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1354 reg
= read_signed_register (upk
.regx
);
1356 pc
+= (upk
.offset
<< 1) + 2;
1361 case 12: /* I8 Formats btez btnez */
1363 struct upk_mips16 upk
;
1365 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1366 /* upk.regx contains the opcode */
1367 reg
= read_signed_register (24); /* Test register is 24 */
1368 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1369 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1370 /* pc = add_offset_16(pc,upk.offset) ; */
1371 pc
+= (upk
.offset
<< 1) + 2;
1376 case 29: /* RR Formats JR, JALR, JALR-RA */
1378 struct upk_mips16 upk
;
1379 /* upk.fmt = rrtype; */
1384 upk
.regx
= (insn
>> 8) & 0x07;
1385 upk
.regy
= (insn
>> 5) & 0x07;
1393 break; /* Function return instruction */
1399 break; /* BOGUS Guess */
1401 pc
= read_signed_register (reg
);
1408 /* This is an instruction extension. Fetch the real instruction
1409 (which follows the extension) and decode things based on
1413 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1426 mips16_next_pc (CORE_ADDR pc
)
1428 unsigned int insn
= fetch_mips_16 (pc
);
1429 return extended_mips16_next_pc (pc
, 0, insn
);
1432 /* The mips_next_pc function supports single_step when the remote
1433 target monitor or stub is not developed enough to do a single_step.
1434 It works by decoding the current instruction and predicting where a
1435 branch will go. This isnt hard because all the data is available.
1436 The MIPS32 and MIPS16 variants are quite different */
1438 mips_next_pc (CORE_ADDR pc
)
1441 return mips16_next_pc (pc
);
1443 return mips32_next_pc (pc
);
1446 /* Set up the 'saved_regs' array. This is a data structure containing
1447 the addresses on the stack where each register has been saved, for
1448 each stack frame. Registers that have not been saved will have
1449 zero here. The stack pointer register is special: rather than the
1450 address where the stack register has been saved,
1451 saved_regs[SP_REGNUM] will have the actual value of the previous
1452 frame's stack register. */
1455 mips_find_saved_regs (struct frame_info
*fci
)
1458 /* r0 bit means kernel trap */
1460 /* What registers have been saved? Bitmasks. */
1461 unsigned long gen_mask
, float_mask
;
1462 mips_extra_func_info_t proc_desc
;
1464 CORE_ADDR
*saved_regs
;
1465 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1467 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1469 saved_regs
= frame_saved_regs_zalloc (fci
);
1471 /* If it is the frame for sigtramp, the saved registers are located
1472 in a sigcontext structure somewhere on the stack. If the stack
1473 layout for sigtramp changes we might have to change these
1474 constants and the companion fixup_sigtramp in mdebugread.c */
1475 #ifndef SIGFRAME_BASE
1476 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1477 above the sigtramp frame. */
1478 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1479 /* FIXME! Are these correct?? */
1480 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1481 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1482 #define SIGFRAME_FPREGSAVE_OFF \
1483 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1485 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1487 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1489 CORE_ADDR reg_position
= (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
1490 + ireg
* mips_regsize (current_gdbarch
));
1491 set_reg_offset (saved_regs
, ireg
, reg_position
);
1493 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1495 CORE_ADDR reg_position
= (get_frame_base (fci
)
1496 + SIGFRAME_FPREGSAVE_OFF
1497 + ireg
* mips_regsize (current_gdbarch
));
1498 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1501 set_reg_offset (saved_regs
, PC_REGNUM
, get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1502 /* SP_REGNUM, contains the value and not the address. */
1503 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1507 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1508 if (proc_desc
== NULL
)
1509 /* I'm not sure how/whether this can happen. Normally when we
1510 can't find a proc_desc, we "synthesize" one using
1511 heuristic_proc_desc and set the saved_regs right away. */
1514 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1515 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1516 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1518 if (/* In any frame other than the innermost or a frame interrupted
1519 by a signal, we assume that all registers have been saved.
1520 This assumes that all register saves in a function happen
1521 before the first function call. */
1522 (get_next_frame (fci
) == NULL
1523 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1525 /* In a dummy frame we know exactly where things are saved. */
1526 && !PROC_DESC_IS_DUMMY (proc_desc
)
1528 /* Don't bother unless we are inside a function prologue.
1529 Outside the prologue, we know where everything is. */
1531 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1533 /* Not sure exactly what kernel_trap means, but if it means the
1534 kernel saves the registers without a prologue doing it, we
1535 better not examine the prologue to see whether registers
1536 have been saved yet. */
1539 /* We need to figure out whether the registers that the
1540 proc_desc claims are saved have been saved yet. */
1544 /* Bitmasks; set if we have found a save for the register. */
1545 unsigned long gen_save_found
= 0;
1546 unsigned long float_save_found
= 0;
1549 /* If the address is odd, assume this is MIPS16 code. */
1550 addr
= PROC_LOW_ADDR (proc_desc
);
1551 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1553 /* Scan through this function's instructions preceding the
1554 current PC, and look for those that save registers. */
1555 while (addr
< get_frame_pc (fci
))
1557 inst
= mips_fetch_instruction (addr
);
1558 if (pc_is_mips16 (addr
))
1559 mips16_decode_reg_save (inst
, &gen_save_found
);
1561 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1564 gen_mask
= gen_save_found
;
1565 float_mask
= float_save_found
;
1568 /* Fill in the offsets for the registers which gen_mask says were
1571 CORE_ADDR reg_position
= (get_frame_base (fci
)
1572 + PROC_REG_OFFSET (proc_desc
));
1573 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1574 if (gen_mask
& 0x80000000)
1576 set_reg_offset (saved_regs
, ireg
, reg_position
);
1577 reg_position
-= mips_saved_regsize (tdep
);
1581 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1582 order of that normally used by gcc. Therefore, we have to fetch
1583 the first instruction of the function, and if it's an entry
1584 instruction that saves $s0 or $s1, correct their saved addresses. */
1585 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1587 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1588 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1592 int sreg_count
= (inst
>> 6) & 3;
1594 /* Check if the ra register was pushed on the stack. */
1595 CORE_ADDR reg_position
= (get_frame_base (fci
)
1596 + PROC_REG_OFFSET (proc_desc
));
1598 reg_position
-= mips_saved_regsize (tdep
);
1600 /* Check if the s0 and s1 registers were pushed on the
1602 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1604 set_reg_offset (saved_regs
, reg
, reg_position
);
1605 reg_position
-= mips_saved_regsize (tdep
);
1610 /* Fill in the offsets for the registers which float_mask says were
1613 CORE_ADDR reg_position
= (get_frame_base (fci
)
1614 + PROC_FREG_OFFSET (proc_desc
));
1616 /* Fill in the offsets for the float registers which float_mask
1618 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1619 if (float_mask
& 0x80000000)
1621 if (mips_saved_regsize (tdep
) == 4
1622 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1624 /* On a big endian 32 bit ABI, floating point registers
1625 are paired to form doubles such that the most
1626 significant part is in $f[N+1] and the least
1627 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1628 registers are also spilled as a pair and stored as a
1631 When little-endian the least significant part is
1632 stored first leading to the memory order $f[N] and
1635 Unfortunately, when big-endian the most significant
1636 part of the double is stored first, and the least
1637 significant is stored second. This leads to the
1638 registers being ordered in memory as firt $f[N+1] and
1641 For the big-endian case make certain that the
1642 addresses point at the correct (swapped) locations
1643 $f[N] and $f[N+1] pair (keep in mind that
1644 reg_position is decremented each time through the
1647 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1648 reg_position
- mips_saved_regsize (tdep
));
1650 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1651 reg_position
+ mips_saved_regsize (tdep
));
1654 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1655 reg_position
-= mips_saved_regsize (tdep
);
1658 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1661 /* SP_REGNUM, contains the value and not the address. */
1662 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1666 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1668 /* Always a pseudo. */
1669 gdb_assert (regno
>= NUM_REGS
);
1673 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1676 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1677 /* The SP_REGNUM is special, its value is stored in saved_regs.
1678 In fact, it is so special that it can even only be fetched
1679 using a raw register number! Once this code as been converted
1680 to frame-unwind the problem goes away. */
1681 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1683 return frame_unwind_register_signed (fi
, regno
);
1687 /* mips_addr_bits_remove - remove useless address bits */
1690 mips_addr_bits_remove (CORE_ADDR addr
)
1692 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1693 if (mips_mask_address_p (tdep
)
1694 && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1695 /* This hack is a work-around for existing boards using PMON, the
1696 simulator, and any other 64-bit targets that doesn't have true
1697 64-bit addressing. On these targets, the upper 32 bits of
1698 addresses are ignored by the hardware. Thus, the PC or SP are
1699 likely to have been sign extended to all 1s by instruction
1700 sequences that load 32-bit addresses. For example, a typical
1701 piece of code that loads an address is this:
1703 lui $r2, <upper 16 bits>
1704 ori $r2, <lower 16 bits>
1706 But the lui sign-extends the value such that the upper 32 bits
1707 may be all 1s. The workaround is simply to mask off these
1708 bits. In the future, gcc may be changed to support true 64-bit
1709 addressing, and this masking will have to be disabled. */
1710 return addr
&= 0xffffffffUL
;
1715 /* mips_software_single_step() is called just before we want to resume
1716 the inferior, if we want to single-step it but there is no hardware
1717 or kernel single-step support (MIPS on GNU/Linux for example). We find
1718 the target of the coming instruction and breakpoint it.
1720 single_step is also called just after the inferior stops. If we had
1721 set up a simulated single-step, we undo our damage. */
1724 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1726 static CORE_ADDR next_pc
;
1727 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1728 static binsn_quantum break_mem
;
1731 if (insert_breakpoints_p
)
1733 pc
= read_register (PC_REGNUM
);
1734 next_pc
= mips_next_pc (pc
);
1736 target_insert_breakpoint (next_pc
, break_mem
);
1739 target_remove_breakpoint (next_pc
, break_mem
);
1743 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1748 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1749 : get_next_frame (prev
)
1750 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
))
1752 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1753 return tmp
? tmp
: pc
;
1758 mips_frame_saved_pc (struct frame_info
*frame
)
1761 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1763 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1765 /* Always unwind the cooked PC register value. */
1766 saved_pc
= frame_unwind_register_signed (frame
, NUM_REGS
+ PC_REGNUM
);
1770 mips_extra_func_info_t proc_desc
1771 = get_frame_extra_info (frame
)->proc_desc
;
1772 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1773 saved_pc
= read_memory_integer ((get_frame_base (frame
)
1774 - mips_saved_regsize (tdep
))
1775 , mips_saved_regsize (tdep
));
1778 /* We have to get the saved pc from the sigcontext if it is
1779 a signal handler frame. */
1780 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1781 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1782 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1785 return ADDR_BITS_REMOVE (saved_pc
);
1788 static struct mips_extra_func_info temp_proc_desc
;
1790 /* This hack will go away once the get_prev_frame() code has been
1791 modified to set the frame's type first. That is BEFORE init extra
1792 frame info et.al. is called. This is because it will become
1793 possible to skip the init extra info call for sigtramp and dummy
1795 static CORE_ADDR
*temp_saved_regs
;
1797 /* Set a register's saved stack address in temp_saved_regs. If an
1798 address has already been set for this register, do nothing; this
1799 way we will only recognize the first save of a given register in a
1802 For simplicity, save the address in both [0 .. NUM_REGS) and
1803 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1804 is used as it is only second range (the ABI instead of ISA
1805 registers) that comes into play when finding saved registers in a
1809 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1811 if (saved_regs
[regno
] == 0)
1813 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1814 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1819 /* Test whether the PC points to the return instruction at the
1820 end of a function. */
1823 mips_about_to_return (CORE_ADDR pc
)
1825 if (pc_is_mips16 (pc
))
1826 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1827 generates a "jr $ra"; other times it generates code to load
1828 the return address from the stack to an accessible register (such
1829 as $a3), then a "jr" using that register. This second case
1830 is almost impossible to distinguish from an indirect jump
1831 used for switch statements, so we don't even try. */
1832 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1834 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1838 /* This fencepost looks highly suspicious to me. Removing it also
1839 seems suspicious as it could affect remote debugging across serial
1843 heuristic_proc_start (CORE_ADDR pc
)
1850 pc
= ADDR_BITS_REMOVE (pc
);
1852 fence
= start_pc
- heuristic_fence_post
;
1856 if (heuristic_fence_post
== UINT_MAX
1857 || fence
< VM_MIN_ADDRESS
)
1858 fence
= VM_MIN_ADDRESS
;
1860 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1862 /* search back for previous return */
1863 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1864 if (start_pc
< fence
)
1866 /* It's not clear to me why we reach this point when
1867 stop_soon, but with this test, at least we
1868 don't print out warnings for every child forked (eg, on
1869 decstation). 22apr93 rich@cygnus.com. */
1870 if (stop_soon
== NO_STOP_QUIETLY
)
1872 static int blurb_printed
= 0;
1874 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1879 /* This actually happens frequently in embedded
1880 development, when you first connect to a board
1881 and your stack pointer and pc are nowhere in
1882 particular. This message needs to give people
1883 in that situation enough information to
1884 determine that it's no big deal. */
1885 printf_filtered ("\n\
1886 GDB is unable to find the start of the function at 0x%s\n\
1887 and thus can't determine the size of that function's stack frame.\n\
1888 This means that GDB may be unable to access that stack frame, or\n\
1889 the frames below it.\n\
1890 This problem is most likely caused by an invalid program counter or\n\
1892 However, if you think GDB should simply search farther back\n\
1893 from 0x%s for code which looks like the beginning of a\n\
1894 function, you can increase the range of the search using the `set\n\
1895 heuristic-fence-post' command.\n",
1896 paddr_nz (pc
), paddr_nz (pc
));
1903 else if (pc_is_mips16 (start_pc
))
1905 unsigned short inst
;
1907 /* On MIPS16, any one of the following is likely to be the
1908 start of a function:
1912 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1913 inst
= mips_fetch_instruction (start_pc
);
1914 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1915 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1916 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1917 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1919 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1920 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1925 else if (mips_about_to_return (start_pc
))
1927 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1934 /* Fetch the immediate value from a MIPS16 instruction.
1935 If the previous instruction was an EXTEND, use it to extend
1936 the upper bits of the immediate value. This is a helper function
1937 for mips16_heuristic_proc_desc. */
1940 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1941 unsigned short inst
, /* current instruction */
1942 int nbits
, /* number of bits in imm field */
1943 int scale
, /* scale factor to be applied to imm */
1944 int is_signed
) /* is the imm field signed? */
1948 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1950 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1951 if (offset
& 0x8000) /* check for negative extend */
1952 offset
= 0 - (0x10000 - (offset
& 0xffff));
1953 return offset
| (inst
& 0x1f);
1957 int max_imm
= 1 << nbits
;
1958 int mask
= max_imm
- 1;
1959 int sign_bit
= max_imm
>> 1;
1961 offset
= inst
& mask
;
1962 if (is_signed
&& (offset
& sign_bit
))
1963 offset
= 0 - (max_imm
- offset
);
1964 return offset
* scale
;
1969 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1970 stream from start_pc to limit_pc. */
1973 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1974 struct frame_info
*next_frame
, CORE_ADDR sp
)
1977 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1978 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1979 unsigned inst
= 0; /* current instruction */
1980 unsigned entry_inst
= 0; /* the entry instruction */
1982 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1984 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1985 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1987 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1989 /* Save the previous instruction. If it's an EXTEND, we'll extract
1990 the immediate offset extension from it in mips16_get_imm. */
1993 /* Fetch and decode the instruction. */
1994 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1995 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1996 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1998 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1999 if (offset
< 0) /* negative stack adjustment? */
2000 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2002 /* Exit loop if a positive stack adjustment is found, which
2003 usually means that the stack cleanup code in the function
2004 epilogue is reached. */
2007 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2009 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2010 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2011 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2012 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2014 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2016 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2017 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2018 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2019 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2021 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2023 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2024 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2025 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2027 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2029 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2030 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2031 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2033 else if (inst
== 0x673d) /* move $s1, $sp */
2036 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2038 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2040 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2041 frame_addr
= sp
+ offset
;
2042 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2043 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2045 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2047 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2048 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2049 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2050 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2052 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2054 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2055 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2056 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2057 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2059 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2060 entry_inst
= inst
; /* save for later processing */
2061 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2062 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2065 /* The entry instruction is typically the first instruction in a function,
2066 and it stores registers at offsets relative to the value of the old SP
2067 (before the prologue). But the value of the sp parameter to this
2068 function is the new SP (after the prologue has been executed). So we
2069 can't calculate those offsets until we've seen the entire prologue,
2070 and can calculate what the old SP must have been. */
2071 if (entry_inst
!= 0)
2073 int areg_count
= (entry_inst
>> 8) & 7;
2074 int sreg_count
= (entry_inst
>> 6) & 3;
2076 /* The entry instruction always subtracts 32 from the SP. */
2077 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2079 /* Now we can calculate what the SP must have been at the
2080 start of the function prologue. */
2081 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2083 /* Check if a0-a3 were saved in the caller's argument save area. */
2084 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2086 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2087 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2088 offset
+= mips_saved_regsize (tdep
);
2091 /* Check if the ra register was pushed on the stack. */
2093 if (entry_inst
& 0x20)
2095 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2096 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2097 offset
-= mips_saved_regsize (tdep
);
2100 /* Check if the s0 and s1 registers were pushed on the stack. */
2101 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2103 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2104 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2105 offset
-= mips_saved_regsize (tdep
);
2111 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2112 struct frame_info
*next_frame
, CORE_ADDR sp
)
2115 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2117 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2118 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2119 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2120 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2121 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2123 unsigned long inst
, high_word
, low_word
;
2126 /* Fetch the instruction. */
2127 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2129 /* Save some code by pre-extracting some useful fields. */
2130 high_word
= (inst
>> 16) & 0xffff;
2131 low_word
= inst
& 0xffff;
2132 reg
= high_word
& 0x1f;
2134 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2135 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2136 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2138 if (low_word
& 0x8000) /* negative stack adjustment? */
2139 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2141 /* Exit loop if a positive stack adjustment is found, which
2142 usually means that the stack cleanup code in the function
2143 epilogue is reached. */
2146 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2148 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2149 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2151 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2153 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2154 but the register size used is only 32 bits. Make the address
2155 for the saved register point to the lower 32 bits. */
2156 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2157 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2159 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2161 /* Old gcc frame, r30 is virtual frame pointer. */
2162 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2163 frame_addr
= sp
+ low_word
;
2164 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2166 unsigned alloca_adjust
;
2167 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2168 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2169 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2170 if (alloca_adjust
> 0)
2172 /* FP > SP + frame_size. This may be because
2173 * of an alloca or somethings similar.
2174 * Fix sp to "pre-alloca" value, and try again.
2176 sp
+= alloca_adjust
;
2181 /* move $30,$sp. With different versions of gas this will be either
2182 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2183 Accept any one of these. */
2184 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2186 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2187 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2189 unsigned alloca_adjust
;
2190 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2191 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2192 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2193 if (alloca_adjust
> 0)
2195 /* FP > SP + frame_size. This may be because
2196 * of an alloca or somethings similar.
2197 * Fix sp to "pre-alloca" value, and try again.
2199 sp
+= alloca_adjust
;
2204 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2206 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2207 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2212 static mips_extra_func_info_t
2213 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2214 struct frame_info
*next_frame
, int cur_frame
)
2219 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2225 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2226 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2227 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2228 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2229 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2230 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2232 if (start_pc
+ 200 < limit_pc
)
2233 limit_pc
= start_pc
+ 200;
2234 if (pc_is_mips16 (start_pc
))
2235 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2237 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2238 return &temp_proc_desc
;
2241 struct mips_objfile_private
2247 /* Global used to communicate between non_heuristic_proc_desc and
2248 compare_pdr_entries within qsort (). */
2249 static bfd
*the_bfd
;
2252 compare_pdr_entries (const void *a
, const void *b
)
2254 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2255 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2259 else if (lhs
== rhs
)
2265 static mips_extra_func_info_t
2266 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2268 CORE_ADDR startaddr
;
2269 mips_extra_func_info_t proc_desc
;
2270 struct block
*b
= block_for_pc (pc
);
2272 struct obj_section
*sec
;
2273 struct mips_objfile_private
*priv
;
2275 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2278 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2280 *addrptr
= startaddr
;
2284 sec
= find_pc_section (pc
);
2287 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2289 /* Search the ".pdr" section generated by GAS. This includes most of
2290 the information normally found in ECOFF PDRs. */
2292 the_bfd
= sec
->objfile
->obfd
;
2294 && (the_bfd
->format
== bfd_object
2295 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2296 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2298 /* Right now GAS only outputs the address as a four-byte sequence.
2299 This means that we should not bother with this method on 64-bit
2300 targets (until that is fixed). */
2302 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2303 sizeof (struct mips_objfile_private
));
2305 sec
->objfile
->obj_private
= priv
;
2307 else if (priv
== NULL
)
2311 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2312 sizeof (struct mips_objfile_private
));
2314 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2317 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2318 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2320 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2321 priv
->contents
, 0, priv
->size
);
2323 /* In general, the .pdr section is sorted. However, in the
2324 presence of multiple code sections (and other corner cases)
2325 it can become unsorted. Sort it so that we can use a faster
2327 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2332 sec
->objfile
->obj_private
= priv
;
2336 if (priv
->size
!= 0)
2342 high
= priv
->size
/ 32;
2348 mid
= (low
+ high
) / 2;
2350 ptr
= priv
->contents
+ mid
* 32;
2351 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2352 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2353 SECT_OFF_TEXT (sec
->objfile
));
2354 if (pdr_pc
== startaddr
)
2356 if (pdr_pc
> startaddr
)
2361 while (low
!= high
);
2365 struct symbol
*sym
= find_pc_function (pc
);
2367 /* Fill in what we need of the proc_desc. */
2368 proc_desc
= (mips_extra_func_info_t
)
2369 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2370 sizeof (struct mips_extra_func_info
));
2371 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2373 /* Only used for dummy frames. */
2374 PROC_HIGH_ADDR (proc_desc
) = 0;
2376 PROC_FRAME_OFFSET (proc_desc
)
2377 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2378 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2380 PROC_FRAME_ADJUST (proc_desc
) = 0;
2381 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2383 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2385 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2387 PROC_FREG_OFFSET (proc_desc
)
2388 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2389 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2391 proc_desc
->pdr
.isym
= (long) sym
;
2401 if (startaddr
> BLOCK_START (b
))
2403 /* This is the "pathological" case referred to in a comment in
2404 print_frame_info. It might be better to move this check into
2409 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2411 /* If we never found a PDR for this function in symbol reading, then
2412 examine prologues to find the information. */
2415 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2416 if (PROC_FRAME_REG (proc_desc
) == -1)
2426 static mips_extra_func_info_t
2427 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2429 mips_extra_func_info_t proc_desc
;
2430 CORE_ADDR startaddr
= 0;
2432 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2436 /* IF this is the topmost frame AND
2437 * (this proc does not have debugging information OR
2438 * the PC is in the procedure prologue)
2439 * THEN create a "heuristic" proc_desc (by analyzing
2440 * the actual code) to replace the "official" proc_desc.
2442 if (next_frame
== NULL
)
2444 struct symtab_and_line val
;
2445 struct symbol
*proc_symbol
=
2446 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2450 val
= find_pc_line (BLOCK_START
2451 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2453 val
.pc
= val
.end
? val
.end
: pc
;
2455 if (!proc_symbol
|| pc
< val
.pc
)
2457 mips_extra_func_info_t found_heuristic
=
2458 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2459 pc
, next_frame
, cur_frame
);
2460 if (found_heuristic
)
2461 proc_desc
= found_heuristic
;
2467 /* Is linked_proc_desc_table really necessary? It only seems to be used
2468 by procedure call dummys. However, the procedures being called ought
2469 to have their own proc_descs, and even if they don't,
2470 heuristic_proc_desc knows how to create them! */
2472 struct linked_proc_info
*link
;
2474 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2475 if (PROC_LOW_ADDR (&link
->info
) <= pc
2476 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2480 startaddr
= heuristic_proc_start (pc
);
2483 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2489 get_frame_pointer (struct frame_info
*frame
,
2490 mips_extra_func_info_t proc_desc
)
2492 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2493 + PROC_FRAME_OFFSET (proc_desc
)
2494 - PROC_FRAME_ADJUST (proc_desc
));
2497 static mips_extra_func_info_t cached_proc_desc
;
2500 mips_frame_chain (struct frame_info
*frame
)
2502 mips_extra_func_info_t proc_desc
;
2504 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2506 /* Check if the PC is inside a call stub. If it is, fetch the
2507 PC of the caller of that stub. */
2508 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2511 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2513 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2514 is well, frame->frame the bottom of the current frame will
2515 contain that value. */
2516 return get_frame_base (frame
);
2519 /* Look up the procedure descriptor for this PC. */
2520 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2524 cached_proc_desc
= proc_desc
;
2526 /* If no frame pointer and frame size is zero, we must be at end
2527 of stack (or otherwise hosed). If we don't check frame size,
2528 we loop forever if we see a zero size frame. */
2529 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2530 && PROC_FRAME_OFFSET (proc_desc
) == 0
2531 /* The previous frame from a sigtramp frame might be frameless
2532 and have frame size zero. */
2533 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2534 /* For a generic dummy frame, let get_frame_pointer() unwind a
2535 register value saved as part of the dummy frame call. */
2536 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2539 return get_frame_pointer (frame
, proc_desc
);
2543 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2546 mips_extra_func_info_t proc_desc
;
2548 if (get_frame_type (fci
) == DUMMY_FRAME
)
2551 /* Use proc_desc calculated in frame_chain. When there is no
2552 next frame, i.e, get_next_frame (fci) == NULL, we call
2553 find_proc_desc () to calculate it, passing an explicit
2554 NULL as the frame parameter. */
2556 get_next_frame (fci
)
2558 : find_proc_desc (get_frame_pc (fci
),
2559 NULL
/* i.e, get_next_frame (fci) */,
2562 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2564 get_frame_extra_info (fci
)->proc_desc
=
2565 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2568 /* Fixup frame-pointer - only needed for top frame */
2569 /* This may not be quite right, if proc has a real frame register.
2570 Get the value of the frame relative sp, procedure might have been
2571 interrupted by a signal at it's very start. */
2572 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2573 && !PROC_DESC_IS_DUMMY (proc_desc
))
2574 deprecated_update_frame_base_hack (fci
, read_next_frame_reg (get_next_frame (fci
), NUM_REGS
+ SP_REGNUM
));
2575 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2576 /* Do not ``fix'' fci->frame. It will have the value of the
2577 generic dummy frame's top-of-stack (since the draft
2578 fci->frame is obtained by returning the unwound stack
2579 pointer) and that is what we want. That way the fci->frame
2580 value will match the top-of-stack value that was saved as
2581 part of the dummy frames data. */
2584 deprecated_update_frame_base_hack (fci
, get_frame_pointer (get_next_frame (fci
), proc_desc
));
2586 if (proc_desc
== &temp_proc_desc
)
2590 /* Do not set the saved registers for a sigtramp frame,
2591 mips_find_saved_registers will do that for us. We can't
2592 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2594 /* FIXME: cagney/2002-11-18: This problem will go away once
2595 frame.c:get_prev_frame() is modified to set the frame's
2596 type before calling functions like this. */
2597 find_pc_partial_function (get_frame_pc (fci
), &name
,
2598 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2599 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2601 frame_saved_regs_zalloc (fci
);
2602 /* Set value of previous frame's stack pointer.
2603 Remember that saved_regs[SP_REGNUM] is special in
2604 that it contains the value of the stack pointer
2605 register. The other saved_regs values are addresses
2606 (in the inferior) at which a given register's value
2608 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2609 get_frame_base (fci
));
2610 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2611 temp_saved_regs
[RA_REGNUM
]);
2612 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2613 SIZEOF_FRAME_SAVED_REGS
);
2617 /* hack: if argument regs are saved, guess these contain args */
2618 /* assume we can't tell how many args for now */
2619 get_frame_extra_info (fci
)->num_args
= -1;
2620 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2622 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2624 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2631 /* MIPS stack frames are almost impenetrable. When execution stops,
2632 we basically have to look at symbol information for the function
2633 that we stopped in, which tells us *which* register (if any) is
2634 the base of the frame pointer, and what offset from that register
2635 the frame itself is at.
2637 This presents a problem when trying to examine a stack in memory
2638 (that isn't executing at the moment), using the "frame" command. We
2639 don't have a PC, nor do we have any registers except SP.
2641 This routine takes two arguments, SP and PC, and tries to make the
2642 cached frames look as if these two arguments defined a frame on the
2643 cache. This allows the rest of info frame to extract the important
2644 arguments without difficulty. */
2647 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2650 error ("MIPS frame specifications require two arguments: sp and pc");
2652 return create_new_frame (argv
[0], argv
[1]);
2655 /* According to the current ABI, should the type be passed in a
2656 floating-point register (assuming that there is space)? When there
2657 is no FPU, FP are not even considered as possibile candidates for
2658 FP registers and, consequently this returns false - forces FP
2659 arguments into integer registers. */
2662 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2664 return ((typecode
== TYPE_CODE_FLT
2666 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2667 && TYPE_NFIELDS (arg_type
) == 1
2668 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2669 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2672 /* On o32, argument passing in GPRs depends on the alignment of the type being
2673 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2676 mips_type_needs_double_align (struct type
*type
)
2678 enum type_code typecode
= TYPE_CODE (type
);
2680 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2682 else if (typecode
== TYPE_CODE_STRUCT
)
2684 if (TYPE_NFIELDS (type
) < 1)
2686 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2688 else if (typecode
== TYPE_CODE_UNION
)
2692 n
= TYPE_NFIELDS (type
);
2693 for (i
= 0; i
< n
; i
++)
2694 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2701 /* Adjust the address downward (direction of stack growth) so that it
2702 is correctly aligned for a new stack frame. */
2704 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2706 return align_down (addr
, 16);
2710 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2711 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2712 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2713 CORE_ADDR struct_addr
)
2719 int stack_offset
= 0;
2720 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2722 /* For shared libraries, "t9" needs to point at the function
2724 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2726 /* Set the return address register to point to the entry point of
2727 the program, where a breakpoint lies in wait. */
2728 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2730 /* First ensure that the stack and structure return address (if any)
2731 are properly aligned. The stack has to be at least 64-bit
2732 aligned even on 32-bit machines, because doubles must be 64-bit
2733 aligned. For n32 and n64, stack frames need to be 128-bit
2734 aligned, so we round to this widest known alignment. */
2736 sp
= align_down (sp
, 16);
2737 struct_addr
= align_down (struct_addr
, 16);
2739 /* Now make space on the stack for the args. We allocate more
2740 than necessary for EABI, because the first few arguments are
2741 passed in registers, but that's OK. */
2742 for (argnum
= 0; argnum
< nargs
; argnum
++)
2743 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2744 mips_stack_argsize (tdep
));
2745 sp
-= align_up (len
, 16);
2748 fprintf_unfiltered (gdb_stdlog
,
2749 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2750 paddr_nz (sp
), (long) align_up (len
, 16));
2752 /* Initialize the integer and float register pointers. */
2754 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2756 /* The struct_return pointer occupies the first parameter-passing reg. */
2760 fprintf_unfiltered (gdb_stdlog
,
2761 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2762 argreg
, paddr_nz (struct_addr
));
2763 write_register (argreg
++, struct_addr
);
2766 /* Now load as many as possible of the first arguments into
2767 registers, and push the rest onto the stack. Loop thru args
2768 from first to last. */
2769 for (argnum
= 0; argnum
< nargs
; argnum
++)
2772 char valbuf
[MAX_REGISTER_SIZE
];
2773 struct value
*arg
= args
[argnum
];
2774 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2775 int len
= TYPE_LENGTH (arg_type
);
2776 enum type_code typecode
= TYPE_CODE (arg_type
);
2779 fprintf_unfiltered (gdb_stdlog
,
2780 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2781 argnum
+ 1, len
, (int) typecode
);
2783 /* The EABI passes structures that do not fit in a register by
2785 if (len
> mips_saved_regsize (tdep
)
2786 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2788 store_unsigned_integer (valbuf
, mips_saved_regsize (tdep
),
2789 VALUE_ADDRESS (arg
));
2790 typecode
= TYPE_CODE_PTR
;
2791 len
= mips_saved_regsize (tdep
);
2794 fprintf_unfiltered (gdb_stdlog
, " push");
2797 val
= (char *) VALUE_CONTENTS (arg
);
2799 /* 32-bit ABIs always start floating point arguments in an
2800 even-numbered floating point register. Round the FP register
2801 up before the check to see if there are any FP registers
2802 left. Non MIPS_EABI targets also pass the FP in the integer
2803 registers so also round up normal registers. */
2804 if (!FP_REGISTER_DOUBLE
2805 && fp_register_arg_p (typecode
, arg_type
))
2807 if ((float_argreg
& 1))
2811 /* Floating point arguments passed in registers have to be
2812 treated specially. On 32-bit architectures, doubles
2813 are passed in register pairs; the even register gets
2814 the low word, and the odd register gets the high word.
2815 On non-EABI processors, the first two floating point arguments are
2816 also copied to general registers, because MIPS16 functions
2817 don't use float registers for arguments. This duplication of
2818 arguments in general registers can't hurt non-MIPS16 functions
2819 because those registers are normally skipped. */
2820 /* MIPS_EABI squeezes a struct that contains a single floating
2821 point value into an FP register instead of pushing it onto the
2823 if (fp_register_arg_p (typecode
, arg_type
)
2824 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2826 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2828 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2829 unsigned long regval
;
2831 /* Write the low word of the double to the even register(s). */
2832 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2834 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2835 float_argreg
, phex (regval
, 4));
2836 write_register (float_argreg
++, regval
);
2838 /* Write the high word of the double to the odd register(s). */
2839 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2841 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2842 float_argreg
, phex (regval
, 4));
2843 write_register (float_argreg
++, regval
);
2847 /* This is a floating point value that fits entirely
2848 in a single register. */
2849 /* On 32 bit ABI's the float_argreg is further adjusted
2850 above to ensure that it is even register aligned. */
2851 LONGEST regval
= extract_unsigned_integer (val
, len
);
2853 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2854 float_argreg
, phex (regval
, len
));
2855 write_register (float_argreg
++, regval
);
2860 /* Copy the argument to general registers or the stack in
2861 register-sized pieces. Large arguments are split between
2862 registers and stack. */
2863 /* Note: structs whose size is not a multiple of
2864 mips_regsize() are treated specially: Irix cc passes them
2865 in registers where gcc sometimes puts them on the stack.
2866 For maximum compatibility, we will put them in both
2868 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
2869 && (len
% mips_saved_regsize (tdep
) != 0));
2871 /* Note: Floating-point values that didn't fit into an FP
2872 register are only written to memory. */
2875 /* Remember if the argument was written to the stack. */
2876 int stack_used_p
= 0;
2877 int partial_len
= (len
< mips_saved_regsize (tdep
)
2878 ? len
: mips_saved_regsize (tdep
));
2881 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2884 /* Write this portion of the argument to the stack. */
2885 if (argreg
> MIPS_LAST_ARG_REGNUM
2887 || fp_register_arg_p (typecode
, arg_type
))
2889 /* Should shorter than int integer values be
2890 promoted to int before being stored? */
2891 int longword_offset
= 0;
2894 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2896 if (mips_stack_argsize (tdep
) == 8
2897 && (typecode
== TYPE_CODE_INT
2898 || typecode
== TYPE_CODE_PTR
2899 || typecode
== TYPE_CODE_FLT
)
2901 longword_offset
= mips_stack_argsize (tdep
) - len
;
2902 else if ((typecode
== TYPE_CODE_STRUCT
2903 || typecode
== TYPE_CODE_UNION
)
2904 && (TYPE_LENGTH (arg_type
)
2905 < mips_stack_argsize (tdep
)))
2906 longword_offset
= mips_stack_argsize (tdep
) - len
;
2911 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2912 paddr_nz (stack_offset
));
2913 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2914 paddr_nz (longword_offset
));
2917 addr
= sp
+ stack_offset
+ longword_offset
;
2922 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2924 for (i
= 0; i
< partial_len
; i
++)
2926 fprintf_unfiltered (gdb_stdlog
, "%02x",
2930 write_memory (addr
, val
, partial_len
);
2933 /* Note!!! This is NOT an else clause. Odd sized
2934 structs may go thru BOTH paths. Floating point
2935 arguments will not. */
2936 /* Write this portion of the argument to a general
2937 purpose register. */
2938 if (argreg
<= MIPS_LAST_ARG_REGNUM
2939 && !fp_register_arg_p (typecode
, arg_type
))
2941 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2944 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2946 phex (regval
, mips_saved_regsize (tdep
)));
2947 write_register (argreg
, regval
);
2954 /* Compute the the offset into the stack at which we
2955 will copy the next parameter.
2957 In the new EABI (and the NABI32), the stack_offset
2958 only needs to be adjusted when it has been used. */
2961 stack_offset
+= align_up (partial_len
,
2962 mips_stack_argsize (tdep
));
2966 fprintf_unfiltered (gdb_stdlog
, "\n");
2969 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
2971 /* Return adjusted stack pointer. */
2975 /* N32/N64 version of push_dummy_call. */
2978 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2979 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2980 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2981 CORE_ADDR struct_addr
)
2987 int stack_offset
= 0;
2988 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2990 /* For shared libraries, "t9" needs to point at the function
2992 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2994 /* Set the return address register to point to the entry point of
2995 the program, where a breakpoint lies in wait. */
2996 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2998 /* First ensure that the stack and structure return address (if any)
2999 are properly aligned. The stack has to be at least 64-bit
3000 aligned even on 32-bit machines, because doubles must be 64-bit
3001 aligned. For n32 and n64, stack frames need to be 128-bit
3002 aligned, so we round to this widest known alignment. */
3004 sp
= align_down (sp
, 16);
3005 struct_addr
= align_down (struct_addr
, 16);
3007 /* Now make space on the stack for the args. */
3008 for (argnum
= 0; argnum
< nargs
; argnum
++)
3009 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3010 mips_stack_argsize (tdep
));
3011 sp
-= align_up (len
, 16);
3014 fprintf_unfiltered (gdb_stdlog
,
3015 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3016 paddr_nz (sp
), (long) align_up (len
, 16));
3018 /* Initialize the integer and float register pointers. */
3020 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3022 /* The struct_return pointer occupies the first parameter-passing reg. */
3026 fprintf_unfiltered (gdb_stdlog
,
3027 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3028 argreg
, paddr_nz (struct_addr
));
3029 write_register (argreg
++, struct_addr
);
3032 /* Now load as many as possible of the first arguments into
3033 registers, and push the rest onto the stack. Loop thru args
3034 from first to last. */
3035 for (argnum
= 0; argnum
< nargs
; argnum
++)
3038 char valbuf
[MAX_REGISTER_SIZE
];
3039 struct value
*arg
= args
[argnum
];
3040 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3041 int len
= TYPE_LENGTH (arg_type
);
3042 enum type_code typecode
= TYPE_CODE (arg_type
);
3045 fprintf_unfiltered (gdb_stdlog
,
3046 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3047 argnum
+ 1, len
, (int) typecode
);
3049 val
= (char *) VALUE_CONTENTS (arg
);
3051 if (fp_register_arg_p (typecode
, arg_type
)
3052 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3054 /* This is a floating point value that fits entirely
3055 in a single register. */
3056 /* On 32 bit ABI's the float_argreg is further adjusted
3057 above to ensure that it is even register aligned. */
3058 LONGEST regval
= extract_unsigned_integer (val
, len
);
3060 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3061 float_argreg
, phex (regval
, len
));
3062 write_register (float_argreg
++, regval
);
3065 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3066 argreg
, phex (regval
, len
));
3067 write_register (argreg
, regval
);
3072 /* Copy the argument to general registers or the stack in
3073 register-sized pieces. Large arguments are split between
3074 registers and stack. */
3075 /* Note: structs whose size is not a multiple of
3076 mips_regsize() are treated specially: Irix cc passes them
3077 in registers where gcc sometimes puts them on the stack.
3078 For maximum compatibility, we will put them in both
3080 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3081 && (len
% mips_saved_regsize (tdep
) != 0));
3082 /* Note: Floating-point values that didn't fit into an FP
3083 register are only written to memory. */
3086 /* Rememer if the argument was written to the stack. */
3087 int stack_used_p
= 0;
3088 int partial_len
= (len
< mips_saved_regsize (tdep
)
3089 ? len
: mips_saved_regsize (tdep
));
3092 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3095 /* Write this portion of the argument to the stack. */
3096 if (argreg
> MIPS_LAST_ARG_REGNUM
3098 || fp_register_arg_p (typecode
, arg_type
))
3100 /* Should shorter than int integer values be
3101 promoted to int before being stored? */
3102 int longword_offset
= 0;
3105 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3107 if (mips_stack_argsize (tdep
) == 8
3108 && (typecode
== TYPE_CODE_INT
3109 || typecode
== TYPE_CODE_PTR
3110 || typecode
== TYPE_CODE_FLT
)
3112 longword_offset
= mips_stack_argsize (tdep
) - len
;
3117 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3118 paddr_nz (stack_offset
));
3119 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3120 paddr_nz (longword_offset
));
3123 addr
= sp
+ stack_offset
+ longword_offset
;
3128 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3130 for (i
= 0; i
< partial_len
; i
++)
3132 fprintf_unfiltered (gdb_stdlog
, "%02x",
3136 write_memory (addr
, val
, partial_len
);
3139 /* Note!!! This is NOT an else clause. Odd sized
3140 structs may go thru BOTH paths. Floating point
3141 arguments will not. */
3142 /* Write this portion of the argument to a general
3143 purpose register. */
3144 if (argreg
<= MIPS_LAST_ARG_REGNUM
3145 && !fp_register_arg_p (typecode
, arg_type
))
3147 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3149 /* A non-floating-point argument being passed in a
3150 general register. If a struct or union, and if
3151 the remaining length is smaller than the register
3152 size, we have to adjust the register value on
3155 It does not seem to be necessary to do the
3156 same for integral types.
3158 cagney/2001-07-23: gdb/179: Also, GCC, when
3159 outputting LE O32 with sizeof (struct) <
3160 mips_saved_regsize(), generates a left shift as
3161 part of storing the argument in a register a
3162 register (the left shift isn't generated when
3163 sizeof (struct) >= mips_saved_regsize()). Since
3164 it is quite possible that this is GCC
3165 contradicting the LE/O32 ABI, GDB has not been
3166 adjusted to accommodate this. Either someone
3167 needs to demonstrate that the LE/O32 ABI
3168 specifies such a left shift OR this new ABI gets
3169 identified as such and GDB gets tweaked
3172 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3173 && partial_len
< mips_saved_regsize (tdep
)
3174 && (typecode
== TYPE_CODE_STRUCT
||
3175 typecode
== TYPE_CODE_UNION
))
3176 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3180 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3182 phex (regval
, mips_saved_regsize (tdep
)));
3183 write_register (argreg
, regval
);
3190 /* Compute the the offset into the stack at which we
3191 will copy the next parameter.
3193 In N32 (N64?), the stack_offset only needs to be
3194 adjusted when it has been used. */
3197 stack_offset
+= align_up (partial_len
,
3198 mips_stack_argsize (tdep
));
3202 fprintf_unfiltered (gdb_stdlog
, "\n");
3205 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3207 /* Return adjusted stack pointer. */
3211 /* O32 version of push_dummy_call. */
3214 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3215 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3216 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3217 CORE_ADDR struct_addr
)
3223 int stack_offset
= 0;
3224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3226 /* For shared libraries, "t9" needs to point at the function
3228 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3230 /* Set the return address register to point to the entry point of
3231 the program, where a breakpoint lies in wait. */
3232 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3234 /* First ensure that the stack and structure return address (if any)
3235 are properly aligned. The stack has to be at least 64-bit
3236 aligned even on 32-bit machines, because doubles must be 64-bit
3237 aligned. For n32 and n64, stack frames need to be 128-bit
3238 aligned, so we round to this widest known alignment. */
3240 sp
= align_down (sp
, 16);
3241 struct_addr
= align_down (struct_addr
, 16);
3243 /* Now make space on the stack for the args. */
3244 for (argnum
= 0; argnum
< nargs
; argnum
++)
3245 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3246 mips_stack_argsize (tdep
));
3247 sp
-= align_up (len
, 16);
3250 fprintf_unfiltered (gdb_stdlog
,
3251 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3252 paddr_nz (sp
), (long) align_up (len
, 16));
3254 /* Initialize the integer and float register pointers. */
3256 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3258 /* The struct_return pointer occupies the first parameter-passing reg. */
3262 fprintf_unfiltered (gdb_stdlog
,
3263 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3264 argreg
, paddr_nz (struct_addr
));
3265 write_register (argreg
++, struct_addr
);
3266 stack_offset
+= mips_stack_argsize (tdep
);
3269 /* Now load as many as possible of the first arguments into
3270 registers, and push the rest onto the stack. Loop thru args
3271 from first to last. */
3272 for (argnum
= 0; argnum
< nargs
; argnum
++)
3275 char valbuf
[MAX_REGISTER_SIZE
];
3276 struct value
*arg
= args
[argnum
];
3277 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3278 int len
= TYPE_LENGTH (arg_type
);
3279 enum type_code typecode
= TYPE_CODE (arg_type
);
3282 fprintf_unfiltered (gdb_stdlog
,
3283 "mips_o32_push_dummy_call: %d len=%d type=%d",
3284 argnum
+ 1, len
, (int) typecode
);
3286 val
= (char *) VALUE_CONTENTS (arg
);
3288 /* 32-bit ABIs always start floating point arguments in an
3289 even-numbered floating point register. Round the FP register
3290 up before the check to see if there are any FP registers
3291 left. O32/O64 targets also pass the FP in the integer
3292 registers so also round up normal registers. */
3293 if (!FP_REGISTER_DOUBLE
3294 && fp_register_arg_p (typecode
, arg_type
))
3296 if ((float_argreg
& 1))
3300 /* Floating point arguments passed in registers have to be
3301 treated specially. On 32-bit architectures, doubles
3302 are passed in register pairs; the even register gets
3303 the low word, and the odd register gets the high word.
3304 On O32/O64, the first two floating point arguments are
3305 also copied to general registers, because MIPS16 functions
3306 don't use float registers for arguments. This duplication of
3307 arguments in general registers can't hurt non-MIPS16 functions
3308 because those registers are normally skipped. */
3310 if (fp_register_arg_p (typecode
, arg_type
)
3311 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3313 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3315 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3316 unsigned long regval
;
3318 /* Write the low word of the double to the even register(s). */
3319 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3321 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3322 float_argreg
, phex (regval
, 4));
3323 write_register (float_argreg
++, regval
);
3325 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3326 argreg
, phex (regval
, 4));
3327 write_register (argreg
++, regval
);
3329 /* Write the high word of the double to the odd register(s). */
3330 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3332 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3333 float_argreg
, phex (regval
, 4));
3334 write_register (float_argreg
++, regval
);
3337 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3338 argreg
, phex (regval
, 4));
3339 write_register (argreg
++, regval
);
3343 /* This is a floating point value that fits entirely
3344 in a single register. */
3345 /* On 32 bit ABI's the float_argreg is further adjusted
3346 above to ensure that it is even register aligned. */
3347 LONGEST regval
= extract_unsigned_integer (val
, len
);
3349 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3350 float_argreg
, phex (regval
, len
));
3351 write_register (float_argreg
++, regval
);
3352 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3353 registers for each argument. The below is (my
3354 guess) to ensure that the corresponding integer
3355 register has reserved the same space. */
3357 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3358 argreg
, phex (regval
, len
));
3359 write_register (argreg
, regval
);
3360 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3362 /* Reserve space for the FP register. */
3363 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3367 /* Copy the argument to general registers or the stack in
3368 register-sized pieces. Large arguments are split between
3369 registers and stack. */
3370 /* Note: structs whose size is not a multiple of
3371 mips_regsize() are treated specially: Irix cc passes them
3372 in registers where gcc sometimes puts them on the stack.
3373 For maximum compatibility, we will put them in both
3375 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3376 && (len
% mips_saved_regsize (tdep
) != 0));
3377 /* Structures should be aligned to eight bytes (even arg registers)
3378 on MIPS_ABI_O32, if their first member has double precision. */
3379 if (mips_saved_regsize (tdep
) < 8
3380 && mips_type_needs_double_align (arg_type
))
3385 /* Note: Floating-point values that didn't fit into an FP
3386 register are only written to memory. */
3389 /* Remember if the argument was written to the stack. */
3390 int stack_used_p
= 0;
3391 int partial_len
= (len
< mips_saved_regsize (tdep
)
3392 ? len
: mips_saved_regsize (tdep
));
3395 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3398 /* Write this portion of the argument to the stack. */
3399 if (argreg
> MIPS_LAST_ARG_REGNUM
3401 || fp_register_arg_p (typecode
, arg_type
))
3403 /* Should shorter than int integer values be
3404 promoted to int before being stored? */
3405 int longword_offset
= 0;
3408 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3410 if (mips_stack_argsize (tdep
) == 8
3411 && (typecode
== TYPE_CODE_INT
3412 || typecode
== TYPE_CODE_PTR
3413 || typecode
== TYPE_CODE_FLT
)
3415 longword_offset
= mips_stack_argsize (tdep
) - len
;
3420 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3421 paddr_nz (stack_offset
));
3422 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3423 paddr_nz (longword_offset
));
3426 addr
= sp
+ stack_offset
+ longword_offset
;
3431 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3433 for (i
= 0; i
< partial_len
; i
++)
3435 fprintf_unfiltered (gdb_stdlog
, "%02x",
3439 write_memory (addr
, val
, partial_len
);
3442 /* Note!!! This is NOT an else clause. Odd sized
3443 structs may go thru BOTH paths. Floating point
3444 arguments will not. */
3445 /* Write this portion of the argument to a general
3446 purpose register. */
3447 if (argreg
<= MIPS_LAST_ARG_REGNUM
3448 && !fp_register_arg_p (typecode
, arg_type
))
3450 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3451 /* Value may need to be sign extended, because
3452 mips_regsize() != mips_saved_regsize(). */
3454 /* A non-floating-point argument being passed in a
3455 general register. If a struct or union, and if
3456 the remaining length is smaller than the register
3457 size, we have to adjust the register value on
3460 It does not seem to be necessary to do the
3461 same for integral types.
3463 Also don't do this adjustment on O64 binaries.
3465 cagney/2001-07-23: gdb/179: Also, GCC, when
3466 outputting LE O32 with sizeof (struct) <
3467 mips_saved_regsize(), generates a left shift as
3468 part of storing the argument in a register a
3469 register (the left shift isn't generated when
3470 sizeof (struct) >= mips_saved_regsize()). Since
3471 it is quite possible that this is GCC
3472 contradicting the LE/O32 ABI, GDB has not been
3473 adjusted to accommodate this. Either someone
3474 needs to demonstrate that the LE/O32 ABI
3475 specifies such a left shift OR this new ABI gets
3476 identified as such and GDB gets tweaked
3479 if (mips_saved_regsize (tdep
) < 8
3480 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3481 && partial_len
< mips_saved_regsize (tdep
)
3482 && (typecode
== TYPE_CODE_STRUCT
||
3483 typecode
== TYPE_CODE_UNION
))
3484 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3488 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3490 phex (regval
, mips_saved_regsize (tdep
)));
3491 write_register (argreg
, regval
);
3494 /* Prevent subsequent floating point arguments from
3495 being passed in floating point registers. */
3496 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3502 /* Compute the the offset into the stack at which we
3503 will copy the next parameter.
3505 In older ABIs, the caller reserved space for
3506 registers that contained arguments. This was loosely
3507 refered to as their "home". Consequently, space is
3508 always allocated. */
3510 stack_offset
+= align_up (partial_len
,
3511 mips_stack_argsize (tdep
));
3515 fprintf_unfiltered (gdb_stdlog
, "\n");
3518 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3520 /* Return adjusted stack pointer. */
3524 /* O64 version of push_dummy_call. */
3527 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3528 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3529 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3530 CORE_ADDR struct_addr
)
3536 int stack_offset
= 0;
3537 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3539 /* For shared libraries, "t9" needs to point at the function
3541 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3543 /* Set the return address register to point to the entry point of
3544 the program, where a breakpoint lies in wait. */
3545 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3547 /* First ensure that the stack and structure return address (if any)
3548 are properly aligned. The stack has to be at least 64-bit
3549 aligned even on 32-bit machines, because doubles must be 64-bit
3550 aligned. For n32 and n64, stack frames need to be 128-bit
3551 aligned, so we round to this widest known alignment. */
3553 sp
= align_down (sp
, 16);
3554 struct_addr
= align_down (struct_addr
, 16);
3556 /* Now make space on the stack for the args. */
3557 for (argnum
= 0; argnum
< nargs
; argnum
++)
3558 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3559 mips_stack_argsize (tdep
));
3560 sp
-= align_up (len
, 16);
3563 fprintf_unfiltered (gdb_stdlog
,
3564 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3565 paddr_nz (sp
), (long) align_up (len
, 16));
3567 /* Initialize the integer and float register pointers. */
3569 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3571 /* The struct_return pointer occupies the first parameter-passing reg. */
3575 fprintf_unfiltered (gdb_stdlog
,
3576 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3577 argreg
, paddr_nz (struct_addr
));
3578 write_register (argreg
++, struct_addr
);
3579 stack_offset
+= mips_stack_argsize (tdep
);
3582 /* Now load as many as possible of the first arguments into
3583 registers, and push the rest onto the stack. Loop thru args
3584 from first to last. */
3585 for (argnum
= 0; argnum
< nargs
; argnum
++)
3588 char valbuf
[MAX_REGISTER_SIZE
];
3589 struct value
*arg
= args
[argnum
];
3590 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3591 int len
= TYPE_LENGTH (arg_type
);
3592 enum type_code typecode
= TYPE_CODE (arg_type
);
3595 fprintf_unfiltered (gdb_stdlog
,
3596 "mips_o64_push_dummy_call: %d len=%d type=%d",
3597 argnum
+ 1, len
, (int) typecode
);
3599 val
= (char *) VALUE_CONTENTS (arg
);
3601 /* 32-bit ABIs always start floating point arguments in an
3602 even-numbered floating point register. Round the FP register
3603 up before the check to see if there are any FP registers
3604 left. O32/O64 targets also pass the FP in the integer
3605 registers so also round up normal registers. */
3606 if (!FP_REGISTER_DOUBLE
3607 && fp_register_arg_p (typecode
, arg_type
))
3609 if ((float_argreg
& 1))
3613 /* Floating point arguments passed in registers have to be
3614 treated specially. On 32-bit architectures, doubles
3615 are passed in register pairs; the even register gets
3616 the low word, and the odd register gets the high word.
3617 On O32/O64, the first two floating point arguments are
3618 also copied to general registers, because MIPS16 functions
3619 don't use float registers for arguments. This duplication of
3620 arguments in general registers can't hurt non-MIPS16 functions
3621 because those registers are normally skipped. */
3623 if (fp_register_arg_p (typecode
, arg_type
)
3624 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3626 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3628 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3629 unsigned long regval
;
3631 /* Write the low word of the double to the even register(s). */
3632 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3634 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3635 float_argreg
, phex (regval
, 4));
3636 write_register (float_argreg
++, regval
);
3638 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3639 argreg
, phex (regval
, 4));
3640 write_register (argreg
++, regval
);
3642 /* Write the high word of the double to the odd register(s). */
3643 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3645 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3646 float_argreg
, phex (regval
, 4));
3647 write_register (float_argreg
++, regval
);
3650 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3651 argreg
, phex (regval
, 4));
3652 write_register (argreg
++, regval
);
3656 /* This is a floating point value that fits entirely
3657 in a single register. */
3658 /* On 32 bit ABI's the float_argreg is further adjusted
3659 above to ensure that it is even register aligned. */
3660 LONGEST regval
= extract_unsigned_integer (val
, len
);
3662 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3663 float_argreg
, phex (regval
, len
));
3664 write_register (float_argreg
++, regval
);
3665 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3666 registers for each argument. The below is (my
3667 guess) to ensure that the corresponding integer
3668 register has reserved the same space. */
3670 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3671 argreg
, phex (regval
, len
));
3672 write_register (argreg
, regval
);
3673 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3675 /* Reserve space for the FP register. */
3676 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3680 /* Copy the argument to general registers or the stack in
3681 register-sized pieces. Large arguments are split between
3682 registers and stack. */
3683 /* Note: structs whose size is not a multiple of
3684 mips_regsize() are treated specially: Irix cc passes them
3685 in registers where gcc sometimes puts them on the stack.
3686 For maximum compatibility, we will put them in both
3688 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3689 && (len
% mips_saved_regsize (tdep
) != 0));
3690 /* Structures should be aligned to eight bytes (even arg registers)
3691 on MIPS_ABI_O32, if their first member has double precision. */
3692 if (mips_saved_regsize (tdep
) < 8
3693 && mips_type_needs_double_align (arg_type
))
3698 /* Note: Floating-point values that didn't fit into an FP
3699 register are only written to memory. */
3702 /* Remember if the argument was written to the stack. */
3703 int stack_used_p
= 0;
3704 int partial_len
= (len
< mips_saved_regsize (tdep
)
3705 ? len
: mips_saved_regsize (tdep
));
3708 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3711 /* Write this portion of the argument to the stack. */
3712 if (argreg
> MIPS_LAST_ARG_REGNUM
3714 || fp_register_arg_p (typecode
, arg_type
))
3716 /* Should shorter than int integer values be
3717 promoted to int before being stored? */
3718 int longword_offset
= 0;
3721 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3723 if (mips_stack_argsize (tdep
) == 8
3724 && (typecode
== TYPE_CODE_INT
3725 || typecode
== TYPE_CODE_PTR
3726 || typecode
== TYPE_CODE_FLT
)
3728 longword_offset
= mips_stack_argsize (tdep
) - len
;
3733 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3734 paddr_nz (stack_offset
));
3735 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3736 paddr_nz (longword_offset
));
3739 addr
= sp
+ stack_offset
+ longword_offset
;
3744 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3746 for (i
= 0; i
< partial_len
; i
++)
3748 fprintf_unfiltered (gdb_stdlog
, "%02x",
3752 write_memory (addr
, val
, partial_len
);
3755 /* Note!!! This is NOT an else clause. Odd sized
3756 structs may go thru BOTH paths. Floating point
3757 arguments will not. */
3758 /* Write this portion of the argument to a general
3759 purpose register. */
3760 if (argreg
<= MIPS_LAST_ARG_REGNUM
3761 && !fp_register_arg_p (typecode
, arg_type
))
3763 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3764 /* Value may need to be sign extended, because
3765 mips_regsize() != mips_saved_regsize(). */
3767 /* A non-floating-point argument being passed in a
3768 general register. If a struct or union, and if
3769 the remaining length is smaller than the register
3770 size, we have to adjust the register value on
3773 It does not seem to be necessary to do the
3774 same for integral types.
3776 Also don't do this adjustment on O64 binaries.
3778 cagney/2001-07-23: gdb/179: Also, GCC, when
3779 outputting LE O32 with sizeof (struct) <
3780 mips_saved_regsize(), generates a left shift as
3781 part of storing the argument in a register a
3782 register (the left shift isn't generated when
3783 sizeof (struct) >= mips_saved_regsize()). Since
3784 it is quite possible that this is GCC
3785 contradicting the LE/O32 ABI, GDB has not been
3786 adjusted to accommodate this. Either someone
3787 needs to demonstrate that the LE/O32 ABI
3788 specifies such a left shift OR this new ABI gets
3789 identified as such and GDB gets tweaked
3792 if (mips_saved_regsize (tdep
) < 8
3793 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3794 && partial_len
< mips_saved_regsize (tdep
)
3795 && (typecode
== TYPE_CODE_STRUCT
||
3796 typecode
== TYPE_CODE_UNION
))
3797 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3801 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3803 phex (regval
, mips_saved_regsize (tdep
)));
3804 write_register (argreg
, regval
);
3807 /* Prevent subsequent floating point arguments from
3808 being passed in floating point registers. */
3809 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3815 /* Compute the the offset into the stack at which we
3816 will copy the next parameter.
3818 In older ABIs, the caller reserved space for
3819 registers that contained arguments. This was loosely
3820 refered to as their "home". Consequently, space is
3821 always allocated. */
3823 stack_offset
+= align_up (partial_len
,
3824 mips_stack_argsize (tdep
));
3828 fprintf_unfiltered (gdb_stdlog
, "\n");
3831 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3833 /* Return adjusted stack pointer. */
3838 mips_pop_frame (void)
3841 struct frame_info
*frame
= get_current_frame ();
3842 CORE_ADDR new_sp
= get_frame_base (frame
);
3843 mips_extra_func_info_t proc_desc
;
3844 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3846 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
3848 generic_pop_dummy_frame ();
3849 flush_cached_frames ();
3853 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
3854 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
3855 mips_find_saved_regs (frame
);
3856 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3857 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3858 && deprecated_get_frame_saved_regs (frame
)[regnum
])
3860 /* Floating point registers must not be sign extended, in case
3861 mips_saved_regsize() = 4 but sizeof (FP0_REGNUM) == 8. */
3863 if (mips_regnum (current_gdbarch
)->fp0
<= regnum
&& regnum
< mips_regnum (current_gdbarch
)->fp0
+ 32)
3864 write_register (regnum
,
3865 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3866 mips_saved_regsize (tdep
)));
3868 write_register (regnum
,
3869 read_memory_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3870 mips_saved_regsize (tdep
)));
3873 write_register (SP_REGNUM
, new_sp
);
3874 flush_cached_frames ();
3876 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3878 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3880 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3882 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3884 if (&pi_ptr
->info
== proc_desc
)
3889 error ("Can't locate dummy extra frame info\n");
3891 if (prev_ptr
!= NULL
)
3892 prev_ptr
->next
= pi_ptr
->next
;
3894 linked_proc_desc_table
= pi_ptr
->next
;
3898 write_register (mips_regnum (current_gdbarch
)->hi
,
3899 read_memory_integer ((new_sp
3900 - 2 * mips_saved_regsize (tdep
)),
3901 mips_saved_regsize (tdep
)));
3902 write_register (mips_regnum (current_gdbarch
)->lo
,
3903 read_memory_integer ((new_sp
3904 - 3 * mips_saved_regsize (tdep
)),
3905 mips_saved_regsize (tdep
)));
3906 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3907 write_register (mips_regnum (current_gdbarch
)->fp_control_status
,
3908 read_memory_integer ((new_sp
3909 - 4 * mips_saved_regsize (tdep
)),
3910 mips_saved_regsize (tdep
)));
3914 /* Floating point register management.
3916 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3917 64bit operations, these early MIPS cpus treat fp register pairs
3918 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3919 registers and offer a compatibility mode that emulates the MIPS2 fp
3920 model. When operating in MIPS2 fp compat mode, later cpu's split
3921 double precision floats into two 32-bit chunks and store them in
3922 consecutive fp regs. To display 64-bit floats stored in this
3923 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3924 Throw in user-configurable endianness and you have a real mess.
3926 The way this works is:
3927 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3928 double-precision value will be split across two logical registers.
3929 The lower-numbered logical register will hold the low-order bits,
3930 regardless of the processor's endianness.
3931 - If we are on a 64-bit processor, and we are looking for a
3932 single-precision value, it will be in the low ordered bits
3933 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3934 save slot in memory.
3935 - If we are in 64-bit mode, everything is straightforward.
3937 Note that this code only deals with "live" registers at the top of the
3938 stack. We will attempt to deal with saved registers later, when
3939 the raw/cooked register interface is in place. (We need a general
3940 interface that can deal with dynamic saved register sizes -- fp
3941 regs could be 32 bits wide in one frame and 64 on the frame above
3944 static struct type
*
3945 mips_float_register_type (void)
3947 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3948 return builtin_type_ieee_single_big
;
3950 return builtin_type_ieee_single_little
;
3953 static struct type
*
3954 mips_double_register_type (void)
3956 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3957 return builtin_type_ieee_double_big
;
3959 return builtin_type_ieee_double_little
;
3962 /* Copy a 32-bit single-precision value from the current frame
3963 into rare_buffer. */
3966 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3969 int raw_size
= register_size (current_gdbarch
, regno
);
3970 char *raw_buffer
= alloca (raw_size
);
3972 if (!frame_register_read (frame
, regno
, raw_buffer
))
3973 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3976 /* We have a 64-bit value for this register. Find the low-order
3980 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3985 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3989 memcpy (rare_buffer
, raw_buffer
, 4);
3993 /* Copy a 64-bit double-precision value from the current frame into
3994 rare_buffer. This may include getting half of it from the next
3998 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4001 int raw_size
= register_size (current_gdbarch
, regno
);
4003 if (raw_size
== 8 && !mips2_fp_compat ())
4005 /* We have a 64-bit value for this register, and we should use
4007 if (!frame_register_read (frame
, regno
, rare_buffer
))
4008 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4012 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4013 internal_error (__FILE__
, __LINE__
,
4014 "mips_read_fp_register_double: bad access to "
4015 "odd-numbered FP register");
4017 /* mips_read_fp_register_single will find the correct 32 bits from
4019 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4021 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4022 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4026 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4027 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4033 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4035 { /* do values for FP (float) regs */
4037 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4038 int inv1
, inv2
, namelen
;
4040 raw_buffer
= (char *) alloca (2 * register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
));
4042 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4043 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4046 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4048 /* 4-byte registers: Print hex and floating. Also print even
4049 numbered registers as doubles. */
4050 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4051 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4053 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w', file
);
4055 fprintf_filtered (file
, " flt: ");
4057 fprintf_filtered (file
, " <invalid float> ");
4059 fprintf_filtered (file
, "%-17.9g", flt1
);
4061 if (regnum
% 2 == 0)
4063 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4064 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4067 fprintf_filtered (file
, " dbl: ");
4069 fprintf_filtered (file
, "<invalid double>");
4071 fprintf_filtered (file
, "%-24.17g", doub
);
4076 /* Eight byte registers: print each one as hex, float and double. */
4077 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4078 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4080 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4081 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4084 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g', file
);
4086 fprintf_filtered (file
, " flt: ");
4088 fprintf_filtered (file
, "<invalid float>");
4090 fprintf_filtered (file
, "%-17.9g", flt1
);
4092 fprintf_filtered (file
, " dbl: ");
4094 fprintf_filtered (file
, "<invalid double>");
4096 fprintf_filtered (file
, "%-24.17g", doub
);
4101 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4102 int regnum
, int all
)
4104 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4105 char raw_buffer
[MAX_REGISTER_SIZE
];
4108 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4110 mips_print_fp_register (file
, frame
, regnum
);
4114 /* Get the data in raw format. */
4115 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4117 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4121 fputs_filtered (REGISTER_NAME (regnum
), file
);
4123 /* The problem with printing numeric register names (r26, etc.) is that
4124 the user can't use them on input. Probably the best solution is to
4125 fix it so that either the numeric or the funky (a2, etc.) names
4126 are accepted on input. */
4127 if (regnum
< MIPS_NUMREGS
)
4128 fprintf_filtered (file
, "(r%d): ", regnum
);
4130 fprintf_filtered (file
, ": ");
4132 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4133 offset
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4137 print_scalar_formatted (raw_buffer
+ offset
, gdbarch_register_type (gdbarch
, regnum
),
4141 /* Replacement for generic do_registers_info.
4142 Print regs in pretty columns. */
4145 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4148 fprintf_filtered (file
, " ");
4149 mips_print_fp_register (file
, frame
, regnum
);
4150 fprintf_filtered (file
, "\n");
4155 /* Print a row's worth of GP (int) registers, with name labels above */
4158 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4161 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4162 /* do values for GP (int) regs */
4163 char raw_buffer
[MAX_REGISTER_SIZE
];
4164 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4168 /* For GP registers, we print a separate row of names above the vals */
4169 fprintf_filtered (file
, " ");
4170 for (col
= 0, regnum
= start_regnum
;
4171 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4174 if (*REGISTER_NAME (regnum
) == '\0')
4175 continue; /* unused register */
4176 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4177 break; /* end the row: reached FP register */
4178 fprintf_filtered (file
, mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4179 REGISTER_NAME (regnum
));
4182 /* print the R0 to R31 names */
4183 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4184 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4186 fprintf_filtered (file
, "\n ");
4188 /* now print the values in hex, 4 or 8 to the row */
4189 for (col
= 0, regnum
= start_regnum
;
4190 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4193 if (*REGISTER_NAME (regnum
) == '\0')
4194 continue; /* unused register */
4195 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4196 break; /* end row: reached FP register */
4197 /* OK: get the data in raw format. */
4198 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4199 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4200 /* pad small registers */
4202 byte
< (mips_regsize (current_gdbarch
)
4203 - register_size (current_gdbarch
, regnum
));
4205 printf_filtered (" ");
4206 /* Now print the register value in hex, endian order. */
4207 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4208 for (byte
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4209 byte
< register_size (current_gdbarch
, regnum
);
4211 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4213 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4216 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4217 fprintf_filtered (file
, " ");
4220 if (col
> 0) /* ie. if we actually printed anything... */
4221 fprintf_filtered (file
, "\n");
4226 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4229 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4230 struct frame_info
*frame
, int regnum
, int all
)
4232 if (regnum
!= -1) /* do one specified register */
4234 gdb_assert (regnum
>= NUM_REGS
);
4235 if (*(REGISTER_NAME (regnum
)) == '\0')
4236 error ("Not a valid register for the current processor type");
4238 mips_print_register (file
, frame
, regnum
, 0);
4239 fprintf_filtered (file
, "\n");
4242 /* do all (or most) registers */
4245 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4247 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4249 if (all
) /* true for "INFO ALL-REGISTERS" command */
4250 regnum
= print_fp_register_row (file
, frame
, regnum
);
4252 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4255 regnum
= print_gp_register_row (file
, frame
, regnum
);
4260 /* Is this a branch with a delay slot? */
4262 static int is_delayed (unsigned long);
4265 is_delayed (unsigned long insn
)
4268 for (i
= 0; i
< NUMOPCODES
; ++i
)
4269 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4270 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4272 return (i
< NUMOPCODES
4273 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4274 | INSN_COND_BRANCH_DELAY
4275 | INSN_COND_BRANCH_LIKELY
)));
4279 mips_step_skips_delay (CORE_ADDR pc
)
4281 char buf
[MIPS_INSTLEN
];
4283 /* There is no branch delay slot on MIPS16. */
4284 if (pc_is_mips16 (pc
))
4287 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4288 /* If error reading memory, guess that it is not a delayed branch. */
4290 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4294 /* Given PC at the function's start address, attempt to find the
4295 prologue end using SAL information. Return zero if the skip fails.
4297 A non-optimized prologue traditionally has one SAL for the function
4298 and a second for the function body. A single line function has
4299 them both pointing at the same line.
4301 An optimized prologue is similar but the prologue may contain
4302 instructions (SALs) from the instruction body. Need to skip those
4303 while not getting into the function body.
4305 The functions end point and an increasing SAL line are used as
4306 indicators of the prologue's endpoint.
4308 This code is based on the function refine_prologue_limit (versions
4309 found in both ia64 and ppc). */
4312 skip_prologue_using_sal (CORE_ADDR func_addr
)
4314 struct symtab_and_line prologue_sal
;
4318 /* Get an initial range for the function. */
4319 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
4320 start_pc
+= FUNCTION_START_OFFSET
;
4322 prologue_sal
= find_pc_line (start_pc
, 0);
4323 if (prologue_sal
.line
!= 0)
4325 while (prologue_sal
.end
< end_pc
)
4327 struct symtab_and_line sal
;
4329 sal
= find_pc_line (prologue_sal
.end
, 0);
4332 /* Assume that a consecutive SAL for the same (or larger)
4333 line mark the prologue -> body transition. */
4334 if (sal
.line
>= prologue_sal
.line
)
4336 /* The case in which compiler's optimizer/scheduler has
4337 moved instructions into the prologue. We look ahead in
4338 the function looking for address ranges whose
4339 corresponding line number is less the first one that we
4340 found for the function. This is more conservative then
4341 refine_prologue_limit which scans a large number of SALs
4342 looking for any in the prologue */
4346 return prologue_sal
.end
;
4349 /* Skip the PC past function prologue instructions (32-bit version).
4350 This is a helper function for mips_skip_prologue. */
4353 mips32_skip_prologue (CORE_ADDR pc
)
4357 int seen_sp_adjust
= 0;
4358 int load_immediate_bytes
= 0;
4360 /* Find an upper bound on the prologue. */
4361 end_pc
= skip_prologue_using_sal (pc
);
4363 end_pc
= pc
+ 100; /* Magic. */
4365 /* Skip the typical prologue instructions. These are the stack adjustment
4366 instruction and the instructions that save registers on the stack
4367 or in the gcc frame. */
4368 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4370 unsigned long high_word
;
4372 inst
= mips_fetch_instruction (pc
);
4373 high_word
= (inst
>> 16) & 0xffff;
4375 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4376 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4378 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4379 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4381 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4382 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4383 && (inst
& 0x001F0000)) /* reg != $zero */
4386 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4388 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4390 continue; /* reg != $zero */
4392 /* move $s8,$sp. With different versions of gas this will be either
4393 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4394 Accept any one of these. */
4395 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4398 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4400 else if (high_word
== 0x3c1c) /* lui $gp,n */
4402 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4404 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4405 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4407 /* The following instructions load $at or $t0 with an immediate
4408 value in preparation for a stack adjustment via
4409 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4410 a local variable, so we accept them only before a stack adjustment
4411 instruction was seen. */
4412 else if (!seen_sp_adjust
)
4414 if (high_word
== 0x3c01 || /* lui $at,n */
4415 high_word
== 0x3c08) /* lui $t0,n */
4417 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4420 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4421 high_word
== 0x3508 || /* ori $t0,$t0,n */
4422 high_word
== 0x3401 || /* ori $at,$zero,n */
4423 high_word
== 0x3408) /* ori $t0,$zero,n */
4425 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4435 /* In a frameless function, we might have incorrectly
4436 skipped some load immediate instructions. Undo the skipping
4437 if the load immediate was not followed by a stack adjustment. */
4438 if (load_immediate_bytes
&& !seen_sp_adjust
)
4439 pc
-= load_immediate_bytes
;
4443 /* Skip the PC past function prologue instructions (16-bit version).
4444 This is a helper function for mips_skip_prologue. */
4447 mips16_skip_prologue (CORE_ADDR pc
)
4450 int extend_bytes
= 0;
4451 int prev_extend_bytes
;
4453 /* Table of instructions likely to be found in a function prologue. */
4456 unsigned short inst
;
4457 unsigned short mask
;
4464 , /* addiu $sp,offset */
4468 , /* daddiu $sp,offset */
4472 , /* sw reg,n($sp) */
4476 , /* sd reg,n($sp) */
4480 , /* sw $ra,n($sp) */
4484 , /* sd $ra,n($sp) */
4492 , /* sw $a0-$a3,n($s1) */
4496 , /* move reg,$a0-$a3 */
4500 , /* entry pseudo-op */
4504 , /* addiu $s1,$sp,n */
4507 } /* end of table marker */
4510 /* Find an upper bound on the prologue. */
4511 end_pc
= skip_prologue_using_sal (pc
);
4513 end_pc
= pc
+ 100; /* Magic. */
4515 /* Skip the typical prologue instructions. These are the stack adjustment
4516 instruction and the instructions that save registers on the stack
4517 or in the gcc frame. */
4518 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4520 unsigned short inst
;
4523 inst
= mips_fetch_instruction (pc
);
4525 /* Normally we ignore an extend instruction. However, if it is
4526 not followed by a valid prologue instruction, we must adjust
4527 the pc back over the extend so that it won't be considered
4528 part of the prologue. */
4529 if ((inst
& 0xf800) == 0xf000) /* extend */
4531 extend_bytes
= MIPS16_INSTLEN
;
4534 prev_extend_bytes
= extend_bytes
;
4537 /* Check for other valid prologue instructions besides extend. */
4538 for (i
= 0; table
[i
].mask
!= 0; i
++)
4539 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4541 if (table
[i
].mask
!= 0) /* it was in table? */
4542 continue; /* ignore it */
4546 /* Return the current pc, adjusted backwards by 2 if
4547 the previous instruction was an extend. */
4548 return pc
- prev_extend_bytes
;
4554 /* To skip prologues, I use this predicate. Returns either PC itself
4555 if the code at PC does not look like a function prologue; otherwise
4556 returns an address that (if we're lucky) follows the prologue. If
4557 LENIENT, then we must skip everything which is involved in setting
4558 up the frame (it's OK to skip more, just so long as we don't skip
4559 anything which might clobber the registers which are being saved.
4560 We must skip more in the case where part of the prologue is in the
4561 delay slot of a non-prologue instruction). */
4564 mips_skip_prologue (CORE_ADDR pc
)
4566 /* See if we can determine the end of the prologue via the symbol table.
4567 If so, then return either PC, or the PC after the prologue, whichever
4570 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4572 if (post_prologue_pc
!= 0)
4573 return max (pc
, post_prologue_pc
);
4575 /* Can't determine prologue from the symbol table, need to examine
4578 if (pc_is_mips16 (pc
))
4579 return mips16_skip_prologue (pc
);
4581 return mips32_skip_prologue (pc
);
4584 /* Determine how a return value is stored within the MIPS register
4585 file, given the return type `valtype'. */
4587 struct return_value_word
4596 return_value_location (struct type
*valtype
,
4597 struct return_value_word
*hi
,
4598 struct return_value_word
*lo
)
4600 int len
= TYPE_LENGTH (valtype
);
4601 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4603 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4604 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4605 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4607 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4609 /* We need to break a 64bit float in two 32 bit halves and
4610 spread them across a floating-point register pair. */
4611 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4612 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4613 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4614 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8)
4616 hi
->reg_offset
= lo
->reg_offset
;
4617 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
4618 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
4624 /* The floating point value fits in a single floating-point
4626 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4627 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8
4630 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
4641 /* Locate a result possibly spread across two registers. */
4643 lo
->reg
= regnum
+ 0;
4644 hi
->reg
= regnum
+ 1;
4645 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4646 && len
< mips_saved_regsize (tdep
))
4648 /* "un-left-justify" the value in the low register */
4649 lo
->reg_offset
= mips_saved_regsize (tdep
) - len
;
4654 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4655 && len
> mips_saved_regsize (tdep
) /* odd-size structs */
4656 && len
< mips_saved_regsize (tdep
) * 2
4657 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4658 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4660 /* "un-left-justify" the value spread across two registers. */
4661 lo
->reg_offset
= 2 * mips_saved_regsize (tdep
) - len
;
4662 lo
->len
= mips_saved_regsize (tdep
) - lo
->reg_offset
;
4664 hi
->len
= len
- lo
->len
;
4668 /* Only perform a partial copy of the second register. */
4671 if (len
> mips_saved_regsize (tdep
))
4673 lo
->len
= mips_saved_regsize (tdep
);
4674 hi
->len
= len
- mips_saved_regsize (tdep
);
4682 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4683 && register_size (current_gdbarch
, regnum
) == 8
4684 && mips_saved_regsize (tdep
) == 4)
4686 /* Account for the fact that only the least-signficant part
4687 of the register is being used */
4688 lo
->reg_offset
+= 4;
4689 hi
->reg_offset
+= 4;
4692 hi
->buf_offset
= lo
->len
;
4696 /* Given a return value in `regbuf' with a type `valtype', extract and
4697 copy its value into `valbuf'. */
4700 mips_eabi_extract_return_value (struct type
*valtype
,
4704 struct return_value_word lo
;
4705 struct return_value_word hi
;
4706 return_value_location (valtype
, &hi
, &lo
);
4708 memcpy (valbuf
+ lo
.buf_offset
,
4709 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) + lo
.reg_offset
,
4713 memcpy (valbuf
+ hi
.buf_offset
,
4714 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) + hi
.reg_offset
,
4719 mips_o64_extract_return_value (struct type
*valtype
,
4723 struct return_value_word lo
;
4724 struct return_value_word hi
;
4725 return_value_location (valtype
, &hi
, &lo
);
4727 memcpy (valbuf
+ lo
.buf_offset
,
4728 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) + lo
.reg_offset
,
4732 memcpy (valbuf
+ hi
.buf_offset
,
4733 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) + hi
.reg_offset
,
4737 /* Given a return value in `valbuf' with a type `valtype', write it's
4738 value into the appropriate register. */
4741 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4743 char raw_buffer
[MAX_REGISTER_SIZE
];
4744 struct return_value_word lo
;
4745 struct return_value_word hi
;
4746 return_value_location (valtype
, &hi
, &lo
);
4748 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4749 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4750 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4751 register_size (current_gdbarch
, lo
.reg
));
4755 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4756 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4757 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4758 register_size (current_gdbarch
, hi
.reg
));
4763 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4765 char raw_buffer
[MAX_REGISTER_SIZE
];
4766 struct return_value_word lo
;
4767 struct return_value_word hi
;
4768 return_value_location (valtype
, &hi
, &lo
);
4770 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4771 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4772 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4773 register_size (current_gdbarch
, lo
.reg
));
4777 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4778 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4779 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4780 register_size (current_gdbarch
, hi
.reg
));
4784 /* O32 ABI stuff. */
4786 static enum return_value_convention
4787 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4788 struct regcache
*regcache
,
4789 void *readbuf
, const void *writebuf
)
4791 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4793 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4794 || TYPE_CODE (type
)== TYPE_CODE_UNION
4795 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
)
4796 return RETURN_VALUE_STRUCT_CONVENTION
;
4797 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4798 && TYPE_LENGTH (type
) == 4
4799 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4801 /* A single-precision floating-point value. It fits in the
4802 least significant part of FP0. */
4804 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4805 mips_xfer_register (regcache
,
4806 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4808 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4809 return RETURN_VALUE_REGISTER_CONVENTION
;
4811 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4812 && TYPE_LENGTH (type
) == 8
4813 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4815 /* A double-precision floating-point value. The most
4816 significant part goes in FP1, and the least significant in
4819 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4820 switch (TARGET_BYTE_ORDER
)
4822 case BFD_ENDIAN_LITTLE
:
4823 mips_xfer_register (regcache
,
4824 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4825 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4826 mips_xfer_register (regcache
,
4827 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4828 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4830 case BFD_ENDIAN_BIG
:
4831 mips_xfer_register (regcache
,
4832 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4833 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4834 mips_xfer_register (regcache
,
4835 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4836 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4839 internal_error (__FILE__
, __LINE__
, "bad switch");
4841 return RETURN_VALUE_REGISTER_CONVENTION
;
4844 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4845 && TYPE_NFIELDS (type
) <= 2
4846 && TYPE_NFIELDS (type
) >= 1
4847 && ((TYPE_NFIELDS (type
) == 1
4848 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4850 || (TYPE_NFIELDS (type
) == 2
4851 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4853 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4855 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4857 /* A struct that contains one or two floats. Each value is part
4858 in the least significant part of their floating point
4860 bfd_byte reg
[MAX_REGISTER_SIZE
];
4863 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4864 field
< TYPE_NFIELDS (type
);
4865 field
++, regnum
+= 2)
4867 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4870 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4871 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4872 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4873 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4875 return RETURN_VALUE_REGISTER_CONVENTION
;
4879 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4880 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4882 /* A structure or union. Extract the left justified value,
4883 regardless of the byte order. I.e. DO NOT USE
4887 for (offset
= 0, regnum
= V0_REGNUM
;
4888 offset
< TYPE_LENGTH (type
);
4889 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4891 int xfer
= register_size (current_gdbarch
, regnum
);
4892 if (offset
+ xfer
> TYPE_LENGTH (type
))
4893 xfer
= TYPE_LENGTH (type
) - offset
;
4895 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4896 offset
, xfer
, regnum
);
4897 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4898 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4900 return RETURN_VALUE_REGISTER_CONVENTION
;
4905 /* A scalar extract each part but least-significant-byte
4906 justified. o32 thinks registers are 4 byte, regardless of
4907 the ISA. mips_stack_argsize controls this. */
4910 for (offset
= 0, regnum
= V0_REGNUM
;
4911 offset
< TYPE_LENGTH (type
);
4912 offset
+= mips_stack_argsize (tdep
), regnum
++)
4914 int xfer
= mips_stack_argsize (tdep
);
4916 if (offset
+ xfer
> TYPE_LENGTH (type
))
4917 xfer
= TYPE_LENGTH (type
) - offset
;
4919 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4920 offset
, xfer
, regnum
);
4921 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4922 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4924 return RETURN_VALUE_REGISTER_CONVENTION
;
4928 /* N32/N44 ABI stuff. */
4930 static enum return_value_convention
4931 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
4932 struct type
*type
, struct regcache
*regcache
,
4933 void *readbuf
, const void *writebuf
)
4935 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4936 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4937 || TYPE_CODE (type
)== TYPE_CODE_UNION
4938 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
4939 || TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
))
4940 return RETURN_VALUE_STRUCT_CONVENTION
;
4941 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4942 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4944 /* A floating-point value belongs in the least significant part
4947 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4948 mips_xfer_register (regcache
,
4949 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4951 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4952 return RETURN_VALUE_REGISTER_CONVENTION
;
4954 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4955 && TYPE_NFIELDS (type
) <= 2
4956 && TYPE_NFIELDS (type
) >= 1
4957 && ((TYPE_NFIELDS (type
) == 1
4958 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4960 || (TYPE_NFIELDS (type
) == 2
4961 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4963 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4965 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4967 /* A struct that contains one or two floats. Each value is part
4968 in the least significant part of their floating point
4970 bfd_byte reg
[MAX_REGISTER_SIZE
];
4973 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4974 field
< TYPE_NFIELDS (type
);
4975 field
++, regnum
+= 2)
4977 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4980 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4981 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4982 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4983 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4985 return RETURN_VALUE_REGISTER_CONVENTION
;
4987 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4988 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4990 /* A structure or union. Extract the left justified value,
4991 regardless of the byte order. I.e. DO NOT USE
4995 for (offset
= 0, regnum
= V0_REGNUM
;
4996 offset
< TYPE_LENGTH (type
);
4997 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4999 int xfer
= register_size (current_gdbarch
, regnum
);
5000 if (offset
+ xfer
> TYPE_LENGTH (type
))
5001 xfer
= TYPE_LENGTH (type
) - offset
;
5003 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5004 offset
, xfer
, regnum
);
5005 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5006 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5008 return RETURN_VALUE_REGISTER_CONVENTION
;
5012 /* A scalar extract each part but least-significant-byte
5016 for (offset
= 0, regnum
= V0_REGNUM
;
5017 offset
< TYPE_LENGTH (type
);
5018 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
5020 int xfer
= register_size (current_gdbarch
, regnum
);
5022 if (offset
+ xfer
> TYPE_LENGTH (type
))
5023 xfer
= TYPE_LENGTH (type
) - offset
;
5025 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5026 offset
, xfer
, regnum
);
5027 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5028 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
5030 return RETURN_VALUE_REGISTER_CONVENTION
;
5034 /* Exported procedure: Is PC in the signal trampoline code */
5037 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5039 if (sigtramp_address
== 0)
5041 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5044 /* Root of all "set mips "/"show mips " commands. This will eventually be
5045 used for all MIPS-specific commands. */
5048 show_mips_command (char *args
, int from_tty
)
5050 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5054 set_mips_command (char *args
, int from_tty
)
5056 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5057 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5060 /* Commands to show/set the MIPS FPU type. */
5063 show_mipsfpu_command (char *args
, int from_tty
)
5066 switch (MIPS_FPU_TYPE
)
5068 case MIPS_FPU_SINGLE
:
5069 fpu
= "single-precision";
5071 case MIPS_FPU_DOUBLE
:
5072 fpu
= "double-precision";
5075 fpu
= "absent (none)";
5078 internal_error (__FILE__
, __LINE__
, "bad switch");
5080 if (mips_fpu_type_auto
)
5081 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5084 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5090 set_mipsfpu_command (char *args
, int from_tty
)
5092 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5093 show_mipsfpu_command (args
, from_tty
);
5097 set_mipsfpu_single_command (char *args
, int from_tty
)
5099 struct gdbarch_info info
;
5100 gdbarch_info_init (&info
);
5101 mips_fpu_type
= MIPS_FPU_SINGLE
;
5102 mips_fpu_type_auto
= 0;
5103 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5104 instead of relying on globals. Doing that would let generic code
5105 handle the search for this specific architecture. */
5106 if (!gdbarch_update_p (info
))
5107 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5111 set_mipsfpu_double_command (char *args
, int from_tty
)
5113 struct gdbarch_info info
;
5114 gdbarch_info_init (&info
);
5115 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5116 mips_fpu_type_auto
= 0;
5117 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5118 instead of relying on globals. Doing that would let generic code
5119 handle the search for this specific architecture. */
5120 if (!gdbarch_update_p (info
))
5121 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5125 set_mipsfpu_none_command (char *args
, int from_tty
)
5127 struct gdbarch_info info
;
5128 gdbarch_info_init (&info
);
5129 mips_fpu_type
= MIPS_FPU_NONE
;
5130 mips_fpu_type_auto
= 0;
5131 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5132 instead of relying on globals. Doing that would let generic code
5133 handle the search for this specific architecture. */
5134 if (!gdbarch_update_p (info
))
5135 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5139 set_mipsfpu_auto_command (char *args
, int from_tty
)
5141 mips_fpu_type_auto
= 1;
5144 /* Attempt to identify the particular processor model by reading the
5145 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5146 the relevant processor still exists (it dates back to '94) and
5147 secondly this is not the way to do this. The processor type should
5148 be set by forcing an architecture change. */
5151 deprecated_mips_set_processor_regs_hack (void)
5153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5156 prid
= read_register (PRID_REGNUM
);
5158 if ((prid
& ~0xf) == 0x700)
5159 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5162 /* Just like reinit_frame_cache, but with the right arguments to be
5163 callable as an sfunc. */
5166 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5167 struct cmd_list_element
*c
)
5169 reinit_frame_cache ();
5173 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5175 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5176 mips_extra_func_info_t proc_desc
;
5178 /* Search for the function containing this address. Set the low bit
5179 of the address when searching, in case we were given an even address
5180 that is the start of a 16-bit function. If we didn't do this,
5181 the search would fail because the symbol table says the function
5182 starts at an odd address, i.e. 1 byte past the given address. */
5183 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5184 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5186 /* Make an attempt to determine if this is a 16-bit function. If
5187 the procedure descriptor exists and the address therein is odd,
5188 it's definitely a 16-bit function. Otherwise, we have to just
5189 guess that if the address passed in is odd, it's 16-bits. */
5190 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5191 disassembler needs to be able to locally determine the ISA, and
5192 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5196 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5197 info
->mach
= bfd_mach_mips16
;
5201 if (pc_is_mips16 (memaddr
))
5202 info
->mach
= bfd_mach_mips16
;
5205 /* Round down the instruction address to the appropriate boundary. */
5206 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5208 /* Set the disassembler options. */
5209 if (tdep
->mips_abi
== MIPS_ABI_N32
5210 || tdep
->mips_abi
== MIPS_ABI_N64
)
5212 /* Set up the disassembler info, so that we get the right
5213 register names from libopcodes. */
5214 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5215 info
->disassembler_options
= "gpr-names=n32";
5217 info
->disassembler_options
= "gpr-names=64";
5218 info
->flavour
= bfd_target_elf_flavour
;
5221 /* This string is not recognized explicitly by the disassembler,
5222 but it tells the disassembler to not try to guess the ABI from
5223 the bfd elf headers, such that, if the user overrides the ABI
5224 of a program linked as NewABI, the disassembly will follow the
5225 register naming conventions specified by the user. */
5226 info
->disassembler_options
= "gpr-names=32";
5228 /* Call the appropriate disassembler based on the target endian-ness. */
5229 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5230 return print_insn_big_mips (memaddr
, info
);
5232 return print_insn_little_mips (memaddr
, info
);
5235 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5236 counter value to determine whether a 16- or 32-bit breakpoint should be
5237 used. It returns a pointer to a string of bytes that encode a breakpoint
5238 instruction, stores the length of the string to *lenptr, and adjusts pc
5239 (if necessary) to point to the actual memory location where the
5240 breakpoint should be inserted. */
5242 static const unsigned char *
5243 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5245 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5247 if (pc_is_mips16 (*pcptr
))
5249 static unsigned char mips16_big_breakpoint
[] = {0xe8, 0xa5};
5250 *pcptr
= unmake_mips16_addr (*pcptr
);
5251 *lenptr
= sizeof (mips16_big_breakpoint
);
5252 return mips16_big_breakpoint
;
5256 /* The IDT board uses an unusual breakpoint value, and
5257 sometimes gets confused when it sees the usual MIPS
5258 breakpoint instruction. */
5259 static unsigned char big_breakpoint
[] = {0, 0x5, 0, 0xd};
5260 static unsigned char pmon_big_breakpoint
[] = {0, 0, 0, 0xd};
5261 static unsigned char idt_big_breakpoint
[] = {0, 0, 0x0a, 0xd};
5263 *lenptr
= sizeof (big_breakpoint
);
5265 if (strcmp (target_shortname
, "mips") == 0)
5266 return idt_big_breakpoint
;
5267 else if (strcmp (target_shortname
, "ddb") == 0
5268 || strcmp (target_shortname
, "pmon") == 0
5269 || strcmp (target_shortname
, "lsi") == 0)
5270 return pmon_big_breakpoint
;
5272 return big_breakpoint
;
5277 if (pc_is_mips16 (*pcptr
))
5279 static unsigned char mips16_little_breakpoint
[] = {0xa5, 0xe8};
5280 *pcptr
= unmake_mips16_addr (*pcptr
);
5281 *lenptr
= sizeof (mips16_little_breakpoint
);
5282 return mips16_little_breakpoint
;
5286 static unsigned char little_breakpoint
[] = {0xd, 0, 0x5, 0};
5287 static unsigned char pmon_little_breakpoint
[] = {0xd, 0, 0, 0};
5288 static unsigned char idt_little_breakpoint
[] = {0xd, 0x0a, 0, 0};
5290 *lenptr
= sizeof (little_breakpoint
);
5292 if (strcmp (target_shortname
, "mips") == 0)
5293 return idt_little_breakpoint
;
5294 else if (strcmp (target_shortname
, "ddb") == 0
5295 || strcmp (target_shortname
, "pmon") == 0
5296 || strcmp (target_shortname
, "lsi") == 0)
5297 return pmon_little_breakpoint
;
5299 return little_breakpoint
;
5304 /* If PC is in a mips16 call or return stub, return the address of the target
5305 PC, which is either the callee or the caller. There are several
5306 cases which must be handled:
5308 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5309 target PC is in $31 ($ra).
5310 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5311 and the target PC is in $2.
5312 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5313 before the jal instruction, this is effectively a call stub
5314 and the the target PC is in $2. Otherwise this is effectively
5315 a return stub and the target PC is in $18.
5317 See the source code for the stubs in gcc/config/mips/mips16.S for
5320 This function implements the SKIP_TRAMPOLINE_CODE macro.
5324 mips_skip_stub (CORE_ADDR pc
)
5327 CORE_ADDR start_addr
;
5329 /* Find the starting address and name of the function containing the PC. */
5330 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5333 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5334 target PC is in $31 ($ra). */
5335 if (strcmp (name
, "__mips16_ret_sf") == 0
5336 || strcmp (name
, "__mips16_ret_df") == 0)
5337 return read_signed_register (RA_REGNUM
);
5339 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5341 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5342 and the target PC is in $2. */
5343 if (name
[19] >= '0' && name
[19] <= '9')
5344 return read_signed_register (2);
5346 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5347 before the jal instruction, this is effectively a call stub
5348 and the the target PC is in $2. Otherwise this is effectively
5349 a return stub and the target PC is in $18. */
5350 else if (name
[19] == 's' || name
[19] == 'd')
5352 if (pc
== start_addr
)
5354 /* Check if the target of the stub is a compiler-generated
5355 stub. Such a stub for a function bar might have a name
5356 like __fn_stub_bar, and might look like this:
5361 la $1,bar (becomes a lui/addiu pair)
5363 So scan down to the lui/addi and extract the target
5364 address from those two instructions. */
5366 CORE_ADDR target_pc
= read_signed_register (2);
5370 /* See if the name of the target function is __fn_stub_*. */
5371 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5373 if (strncmp (name
, "__fn_stub_", 10) != 0
5374 && strcmp (name
, "etext") != 0
5375 && strcmp (name
, "_etext") != 0)
5378 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5379 The limit on the search is arbitrarily set to 20
5380 instructions. FIXME. */
5381 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5383 inst
= mips_fetch_instruction (target_pc
);
5384 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5385 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5386 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5387 return pc
| (inst
& 0xffff); /* low word */
5390 /* Couldn't find the lui/addui pair, so return stub address. */
5394 /* This is the 'return' part of a call stub. The return
5395 address is in $r18. */
5396 return read_signed_register (18);
5399 return 0; /* not a stub */
5403 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5404 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5407 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5409 CORE_ADDR start_addr
;
5411 /* Find the starting address of the function containing the PC. If the
5412 caller didn't give us a name, look it up at the same time. */
5413 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5416 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5418 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5419 if (name
[19] >= '0' && name
[19] <= '9')
5421 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5422 before the jal instruction, this is effectively a call stub. */
5423 else if (name
[19] == 's' || name
[19] == 'd')
5424 return pc
== start_addr
;
5427 return 0; /* not a stub */
5431 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5432 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5435 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5437 CORE_ADDR start_addr
;
5439 /* Find the starting address of the function containing the PC. */
5440 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5443 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5444 if (strcmp (name
, "__mips16_ret_sf") == 0
5445 || strcmp (name
, "__mips16_ret_df") == 0)
5448 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5449 i.e. after the jal instruction, this is effectively a return stub. */
5450 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5451 && (name
[19] == 's' || name
[19] == 'd')
5452 && pc
!= start_addr
)
5455 return 0; /* not a stub */
5459 /* Return non-zero if the PC is in a library helper function that should
5460 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5463 mips_ignore_helper (CORE_ADDR pc
)
5467 /* Find the starting address and name of the function containing the PC. */
5468 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5471 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5472 that we want to ignore. */
5473 return (strcmp (name
, "__mips16_ret_sf") == 0
5474 || strcmp (name
, "__mips16_ret_df") == 0);
5478 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5479 the register stored on the stack (32) is different to its real raw
5480 size (64). The below ensures that registers are fetched from the
5481 stack using their ABI size and then stored into the RAW_BUFFER
5482 using their raw size.
5484 The alternative to adding this function would be to add an ABI
5485 macro - REGISTER_STACK_SIZE(). */
5488 mips_get_saved_register (char *raw_buffer
,
5491 struct frame_info
*frame
,
5493 enum lval_type
*lvalp
)
5496 enum lval_type lvalx
;
5500 /* Always a pseudo. */
5501 gdb_assert (regnum
>= NUM_REGS
);
5503 /* Make certain that all needed parameters are present. */
5508 if (optimizedp
== NULL
)
5509 optimizedp
= &optimizedx
;
5511 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5512 /* The SP_REGNUM is special, its value is stored in saved_regs.
5513 In fact, it is so special that it can even only be fetched
5514 using a raw register number! Once this code as been converted
5515 to frame-unwind the problem goes away. */
5516 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5517 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5518 &realnumx
, raw_buffer
);
5520 /* Get it from the next frame. */
5521 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5522 regnum
, optimizedp
, lvalp
, addrp
,
5523 &realnumx
, raw_buffer
);
5526 /* Immediately after a function call, return the saved pc.
5527 Can't always go through the frames for this because on some machines
5528 the new frame is not set up until the new function executes
5529 some instructions. */
5532 mips_saved_pc_after_call (struct frame_info
*frame
)
5534 return read_signed_register (RA_REGNUM
);
5538 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5539 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5542 mips_stab_reg_to_regnum (int num
)
5545 if (num
>= 0 && num
< 32)
5547 else if (num
>= 38 && num
< 70)
5548 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5550 regnum
= mips_regnum (current_gdbarch
)->hi
;
5552 regnum
= mips_regnum (current_gdbarch
)->lo
;
5554 /* This will hopefully (eventually) provoke a warning. Should
5555 we be calling complaint() here? */
5556 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5557 return NUM_REGS
+ regnum
;
5561 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5562 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5565 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5568 if (num
>= 0 && num
< 32)
5570 else if (num
>= 32 && num
< 64)
5571 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5573 regnum
= mips_regnum (current_gdbarch
)->hi
;
5575 regnum
= mips_regnum (current_gdbarch
)->lo
;
5577 /* This will hopefully (eventually) provoke a warning. Should we
5578 be calling complaint() here? */
5579 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5580 return NUM_REGS
+ regnum
;
5584 mips_register_sim_regno (int regnum
)
5586 /* Only makes sense to supply raw registers. */
5587 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5588 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5589 decide if it is valid. Should instead define a standard sim/gdb
5590 register numbering scheme. */
5591 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5592 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5595 return LEGACY_SIM_REGNO_IGNORE
;
5599 /* Convert an integer into an address. By first converting the value
5600 into a pointer and then extracting it signed, the address is
5601 guarenteed to be correctly sign extended. */
5604 mips_integer_to_address (struct type
*type
, void *buf
)
5606 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5607 LONGEST val
= unpack_long (type
, buf
);
5608 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5609 return extract_signed_integer (tmp
,
5610 TYPE_LENGTH (builtin_type_void_data_ptr
));
5614 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5616 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5617 const char *name
= bfd_get_section_name (abfd
, sect
);
5619 if (*abip
!= MIPS_ABI_UNKNOWN
)
5622 if (strncmp (name
, ".mdebug.", 8) != 0)
5625 if (strcmp (name
, ".mdebug.abi32") == 0)
5626 *abip
= MIPS_ABI_O32
;
5627 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5628 *abip
= MIPS_ABI_N32
;
5629 else if (strcmp (name
, ".mdebug.abi64") == 0)
5630 *abip
= MIPS_ABI_N64
;
5631 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5632 *abip
= MIPS_ABI_O64
;
5633 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5634 *abip
= MIPS_ABI_EABI32
;
5635 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5636 *abip
= MIPS_ABI_EABI64
;
5638 warning ("unsupported ABI %s.", name
+ 8);
5641 static enum mips_abi
5642 global_mips_abi (void)
5646 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5647 if (mips_abi_strings
[i
] == mips_abi_string
)
5648 return (enum mips_abi
) i
;
5650 internal_error (__FILE__
, __LINE__
,
5651 "unknown ABI string");
5654 static struct gdbarch
*
5655 mips_gdbarch_init (struct gdbarch_info info
,
5656 struct gdbarch_list
*arches
)
5658 struct gdbarch
*gdbarch
;
5659 struct gdbarch_tdep
*tdep
;
5661 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5663 enum mips_fpu_type fpu_type
;
5665 /* First of all, extract the elf_flags, if available. */
5666 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5667 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5668 else if (arches
!= NULL
)
5669 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5673 fprintf_unfiltered (gdb_stdlog
,
5674 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5677 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5678 switch ((elf_flags
& EF_MIPS_ABI
))
5680 case E_MIPS_ABI_O32
:
5681 found_abi
= MIPS_ABI_O32
;
5683 case E_MIPS_ABI_O64
:
5684 found_abi
= MIPS_ABI_O64
;
5686 case E_MIPS_ABI_EABI32
:
5687 found_abi
= MIPS_ABI_EABI32
;
5689 case E_MIPS_ABI_EABI64
:
5690 found_abi
= MIPS_ABI_EABI64
;
5693 if ((elf_flags
& EF_MIPS_ABI2
))
5694 found_abi
= MIPS_ABI_N32
;
5696 found_abi
= MIPS_ABI_UNKNOWN
;
5700 /* GCC creates a pseudo-section whose name describes the ABI. */
5701 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5702 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5704 /* If we have no usefu BFD information, use the ABI from the last
5705 MIPS architecture (if there is one). */
5706 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5707 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5709 /* Try the architecture for any hint of the correct ABI. */
5710 if (found_abi
== MIPS_ABI_UNKNOWN
5711 && info
.bfd_arch_info
!= NULL
5712 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5714 switch (info
.bfd_arch_info
->mach
)
5716 case bfd_mach_mips3900
:
5717 found_abi
= MIPS_ABI_EABI32
;
5719 case bfd_mach_mips4100
:
5720 case bfd_mach_mips5000
:
5721 found_abi
= MIPS_ABI_EABI64
;
5723 case bfd_mach_mips8000
:
5724 case bfd_mach_mips10000
:
5725 /* On Irix, ELF64 executables use the N64 ABI. The
5726 pseudo-sections which describe the ABI aren't present
5727 on IRIX. (Even for executables created by gcc.) */
5728 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5729 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5730 found_abi
= MIPS_ABI_N64
;
5732 found_abi
= MIPS_ABI_N32
;
5738 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5741 /* What has the user specified from the command line? */
5742 wanted_abi
= global_mips_abi ();
5744 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5747 /* Now that we have found what the ABI for this binary would be,
5748 check whether the user is overriding it. */
5749 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5750 mips_abi
= wanted_abi
;
5751 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5752 mips_abi
= found_abi
;
5754 mips_abi
= MIPS_ABI_O32
;
5756 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5759 /* Also used when doing an architecture lookup. */
5761 fprintf_unfiltered (gdb_stdlog
,
5762 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5763 mips64_transfers_32bit_regs_p
);
5765 /* Determine the MIPS FPU type. */
5766 if (!mips_fpu_type_auto
)
5767 fpu_type
= mips_fpu_type
;
5768 else if (info
.bfd_arch_info
!= NULL
5769 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5770 switch (info
.bfd_arch_info
->mach
)
5772 case bfd_mach_mips3900
:
5773 case bfd_mach_mips4100
:
5774 case bfd_mach_mips4111
:
5775 fpu_type
= MIPS_FPU_NONE
;
5777 case bfd_mach_mips4650
:
5778 fpu_type
= MIPS_FPU_SINGLE
;
5781 fpu_type
= MIPS_FPU_DOUBLE
;
5784 else if (arches
!= NULL
)
5785 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5787 fpu_type
= MIPS_FPU_DOUBLE
;
5789 fprintf_unfiltered (gdb_stdlog
,
5790 "mips_gdbarch_init: fpu_type = %d\n",
5793 /* try to find a pre-existing architecture */
5794 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5796 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5798 /* MIPS needs to be pedantic about which ABI the object is
5800 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5802 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5804 /* Need to be pedantic about which register virtual size is
5806 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5807 != mips64_transfers_32bit_regs_p
)
5809 /* Be pedantic about which FPU is selected. */
5810 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5812 return arches
->gdbarch
;
5815 /* Need a new architecture. Fill in a target specific vector. */
5816 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5817 gdbarch
= gdbarch_alloc (&info
, tdep
);
5818 tdep
->elf_flags
= elf_flags
;
5819 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5820 tdep
->found_abi
= found_abi
;
5821 tdep
->mips_abi
= mips_abi
;
5822 tdep
->mips_fpu_type
= fpu_type
;
5824 /* Initially set everything according to the default ABI/ISA. */
5825 set_gdbarch_short_bit (gdbarch
, 16);
5826 set_gdbarch_int_bit (gdbarch
, 32);
5827 set_gdbarch_float_bit (gdbarch
, 32);
5828 set_gdbarch_double_bit (gdbarch
, 64);
5829 set_gdbarch_long_double_bit (gdbarch
, 64);
5830 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5831 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5832 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5834 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5835 mips_elf_make_msymbol_special
);
5837 /* Fill in the OS dependant register numbers and names. */
5839 const char **reg_names
;
5840 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5841 struct mips_regnum
);
5842 if (info
.osabi
== GDB_OSABI_IRIX
)
5847 regnum
->badvaddr
= 66;
5850 regnum
->fp_control_status
= 69;
5851 regnum
->fp_implementation_revision
= 70;
5853 reg_names
= mips_irix_reg_names
;
5857 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5858 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5859 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5860 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5861 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5862 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5863 regnum
->fp_control_status
= 70;
5864 regnum
->fp_implementation_revision
= 71;
5866 if (info
.bfd_arch_info
!= NULL
5867 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5868 reg_names
= mips_tx39_reg_names
;
5870 reg_names
= mips_generic_reg_names
;
5872 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5873 replaced by read_pc? */
5874 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5875 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5876 set_gdbarch_num_regs (gdbarch
, num_regs
);
5877 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5878 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5879 tdep
->mips_processor_reg_names
= reg_names
;
5880 tdep
->regnum
= regnum
;
5886 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5887 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5888 tdep
->mips_default_saved_regsize
= 4;
5889 tdep
->mips_default_stack_argsize
= 4;
5890 tdep
->mips_fp_register_double
= 0;
5891 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5892 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5893 tdep
->default_mask_address_p
= 0;
5894 set_gdbarch_long_bit (gdbarch
, 32);
5895 set_gdbarch_ptr_bit (gdbarch
, 32);
5896 set_gdbarch_long_long_bit (gdbarch
, 64);
5899 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5900 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o64_store_return_value
);
5901 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5902 tdep
->mips_default_saved_regsize
= 8;
5903 tdep
->mips_default_stack_argsize
= 8;
5904 tdep
->mips_fp_register_double
= 1;
5905 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5906 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5907 tdep
->default_mask_address_p
= 0;
5908 set_gdbarch_long_bit (gdbarch
, 32);
5909 set_gdbarch_ptr_bit (gdbarch
, 32);
5910 set_gdbarch_long_long_bit (gdbarch
, 64);
5911 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
5913 case MIPS_ABI_EABI32
:
5914 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5915 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5916 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5917 tdep
->mips_default_saved_regsize
= 4;
5918 tdep
->mips_default_stack_argsize
= 4;
5919 tdep
->mips_fp_register_double
= 0;
5920 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5921 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5922 tdep
->default_mask_address_p
= 0;
5923 set_gdbarch_long_bit (gdbarch
, 32);
5924 set_gdbarch_ptr_bit (gdbarch
, 32);
5925 set_gdbarch_long_long_bit (gdbarch
, 64);
5926 set_gdbarch_deprecated_reg_struct_has_addr
5927 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5928 set_gdbarch_use_struct_convention (gdbarch
,
5929 mips_eabi_use_struct_convention
);
5931 case MIPS_ABI_EABI64
:
5932 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5933 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5934 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5935 tdep
->mips_default_saved_regsize
= 8;
5936 tdep
->mips_default_stack_argsize
= 8;
5937 tdep
->mips_fp_register_double
= 1;
5938 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5939 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5940 tdep
->default_mask_address_p
= 0;
5941 set_gdbarch_long_bit (gdbarch
, 64);
5942 set_gdbarch_ptr_bit (gdbarch
, 64);
5943 set_gdbarch_long_long_bit (gdbarch
, 64);
5944 set_gdbarch_deprecated_reg_struct_has_addr
5945 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5946 set_gdbarch_use_struct_convention (gdbarch
,
5947 mips_eabi_use_struct_convention
);
5950 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5951 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5952 tdep
->mips_default_saved_regsize
= 8;
5953 tdep
->mips_default_stack_argsize
= 8;
5954 tdep
->mips_fp_register_double
= 1;
5955 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5956 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5957 tdep
->default_mask_address_p
= 0;
5958 set_gdbarch_long_bit (gdbarch
, 32);
5959 set_gdbarch_ptr_bit (gdbarch
, 32);
5960 set_gdbarch_long_long_bit (gdbarch
, 64);
5963 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5964 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5965 tdep
->mips_default_saved_regsize
= 8;
5966 tdep
->mips_default_stack_argsize
= 8;
5967 tdep
->mips_fp_register_double
= 1;
5968 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5969 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5970 tdep
->default_mask_address_p
= 0;
5971 set_gdbarch_long_bit (gdbarch
, 64);
5972 set_gdbarch_ptr_bit (gdbarch
, 64);
5973 set_gdbarch_long_long_bit (gdbarch
, 64);
5976 internal_error (__FILE__
, __LINE__
,
5977 "unknown ABI in switch");
5980 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5981 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5984 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5985 flag in object files because to do so would make it impossible to
5986 link with libraries compiled without "-gp32". This is
5987 unnecessarily restrictive.
5989 We could solve this problem by adding "-gp32" multilibs to gcc,
5990 but to set this flag before gcc is built with such multilibs will
5991 break too many systems.''
5993 But even more unhelpfully, the default linker output target for
5994 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5995 for 64-bit programs - you need to change the ABI to change this,
5996 and not all gcc targets support that currently. Therefore using
5997 this flag to detect 32-bit mode would do the wrong thing given
5998 the current gcc - it would make GDB treat these 64-bit programs
5999 as 32-bit programs by default. */
6001 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6002 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
6003 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6004 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6006 /* Add/remove bits from an address. The MIPS needs be careful to
6007 ensure that all 32 bit addresses are sign extended to 64 bits. */
6008 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6010 /* There's a mess in stack frame creation. See comments in
6011 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6012 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
6014 /* Map debug register numbers onto internal register numbers. */
6015 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6016 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6017 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6018 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6019 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6021 /* Initialize a frame */
6022 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
, mips_find_saved_regs
);
6023 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
6025 /* MIPS version of CALL_DUMMY */
6027 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6028 replaced by a command, and all targets will default to on stack
6029 (regardless of the stack's execute status). */
6030 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6031 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6032 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6033 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
6035 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6036 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6037 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6039 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6040 set_gdbarch_frameless_function_invocation (gdbarch
,
6041 generic_frameless_function_invocation_not
);
6042 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6043 set_gdbarch_frame_args_skip (gdbarch
, 0);
6045 set_gdbarch_deprecated_get_saved_register (gdbarch
, mips_get_saved_register
);
6047 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6048 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6049 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
6051 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6052 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
6054 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6055 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6056 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6058 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6060 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6061 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6063 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6065 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6066 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6067 need to all be folded into the target vector. Since they are
6068 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6069 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6071 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6073 /* Hook in OS ABI-specific overrides, if they have been registered. */
6074 gdbarch_init_osabi (info
, gdbarch
);
6076 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6078 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6079 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6085 mips_abi_update (char *ignore_args
, int from_tty
,
6086 struct cmd_list_element
*c
)
6088 struct gdbarch_info info
;
6090 /* Force the architecture to update, and (if it's a MIPS architecture)
6091 mips_gdbarch_init will take care of the rest. */
6092 gdbarch_info_init (&info
);
6093 gdbarch_update_p (info
);
6096 /* Print out which MIPS ABI is in use. */
6099 show_mips_abi (char *ignore_args
, int from_tty
)
6101 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6103 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6106 enum mips_abi global_abi
= global_mips_abi ();
6107 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6108 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6110 if (global_abi
== MIPS_ABI_UNKNOWN
)
6111 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6113 else if (global_abi
== actual_abi
)
6115 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6119 /* Probably shouldn't happen... */
6121 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6123 mips_abi_strings
[global_abi
]);
6129 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6131 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6135 int ef_mips_32bitmode
;
6136 /* determine the ISA */
6137 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6155 /* determine the size of a pointer */
6156 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6157 fprintf_unfiltered (file
,
6158 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6160 fprintf_unfiltered (file
,
6161 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6163 fprintf_unfiltered (file
,
6164 "mips_dump_tdep: ef_mips_arch = %d\n",
6166 fprintf_unfiltered (file
,
6167 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6169 mips_abi_strings
[tdep
->mips_abi
]);
6170 fprintf_unfiltered (file
,
6171 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6172 mips_mask_address_p (tdep
),
6173 tdep
->default_mask_address_p
);
6175 fprintf_unfiltered (file
,
6176 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6177 FP_REGISTER_DOUBLE
);
6178 fprintf_unfiltered (file
,
6179 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6180 MIPS_DEFAULT_FPU_TYPE
,
6181 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6182 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6183 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6185 fprintf_unfiltered (file
,
6186 "mips_dump_tdep: MIPS_EABI = %d\n",
6188 fprintf_unfiltered (file
,
6189 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6191 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6192 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6193 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6195 fprintf_unfiltered (file
,
6196 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6197 FP_REGISTER_DOUBLE
);
6198 fprintf_unfiltered (file
,
6199 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6200 mips_stack_argsize (tdep
));
6201 fprintf_unfiltered (file
,
6202 "mips_dump_tdep: A0_REGNUM = %d\n",
6204 fprintf_unfiltered (file
,
6205 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6206 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6207 fprintf_unfiltered (file
,
6208 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6209 XSTRING (ATTACH_DETACH
));
6210 fprintf_unfiltered (file
,
6211 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6212 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6215 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6216 fprintf_unfiltered (file
,
6217 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6218 FIRST_EMBED_REGNUM
);
6219 fprintf_unfiltered (file
,
6220 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6221 XSTRING (IGNORE_HELPER_CALL (PC
)));
6222 fprintf_unfiltered (file
,
6223 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6224 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6225 fprintf_unfiltered (file
,
6226 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6227 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6228 fprintf_unfiltered (file
,
6229 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6231 #ifdef MACHINE_CPROC_FP_OFFSET
6232 fprintf_unfiltered (file
,
6233 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6234 MACHINE_CPROC_FP_OFFSET
);
6236 #ifdef MACHINE_CPROC_PC_OFFSET
6237 fprintf_unfiltered (file
,
6238 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6239 MACHINE_CPROC_PC_OFFSET
);
6241 #ifdef MACHINE_CPROC_SP_OFFSET
6242 fprintf_unfiltered (file
,
6243 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6244 MACHINE_CPROC_SP_OFFSET
);
6246 fprintf_unfiltered (file
,
6247 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6249 fprintf_unfiltered (file
,
6250 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6251 fprintf_unfiltered (file
,
6252 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6253 fprintf_unfiltered (file
,
6254 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6256 fprintf_unfiltered (file
,
6257 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6258 MIPS_LAST_ARG_REGNUM
,
6259 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6260 fprintf_unfiltered (file
,
6261 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6263 fprintf_unfiltered (file
,
6264 "mips_dump_tdep: mips_saved_regsize() = %d\n",
6265 mips_saved_regsize (tdep
));
6266 fprintf_unfiltered (file
,
6267 "mips_dump_tdep: PRID_REGNUM = %d\n",
6269 fprintf_unfiltered (file
,
6270 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6271 fprintf_unfiltered (file
,
6272 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6273 fprintf_unfiltered (file
,
6274 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6275 fprintf_unfiltered (file
,
6276 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6277 fprintf_unfiltered (file
,
6278 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6279 fprintf_unfiltered (file
,
6280 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6281 fprintf_unfiltered (file
,
6282 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6283 fprintf_unfiltered (file
,
6284 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6285 fprintf_unfiltered (file
,
6286 "mips_dump_tdep: PROC_PC_REG = function?\n");
6287 fprintf_unfiltered (file
,
6288 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6289 fprintf_unfiltered (file
,
6290 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6291 fprintf_unfiltered (file
,
6292 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6293 fprintf_unfiltered (file
,
6294 "mips_dump_tdep: PS_REGNUM = %d\n",
6296 fprintf_unfiltered (file
,
6297 "mips_dump_tdep: RA_REGNUM = %d\n",
6300 fprintf_unfiltered (file
,
6301 "mips_dump_tdep: SAVED_BYTES = %d\n",
6305 fprintf_unfiltered (file
,
6306 "mips_dump_tdep: SAVED_FP = %d\n",
6310 fprintf_unfiltered (file
,
6311 "mips_dump_tdep: SAVED_PC = %d\n",
6314 fprintf_unfiltered (file
,
6315 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6316 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6317 fprintf_unfiltered (file
,
6318 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6319 fprintf_unfiltered (file
,
6320 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6322 fprintf_unfiltered (file
,
6323 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6324 SIGFRAME_FPREGSAVE_OFF
);
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6328 fprintf_unfiltered (file
,
6329 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6330 SIGFRAME_REGSAVE_OFF
);
6331 fprintf_unfiltered (file
,
6332 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6333 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6334 fprintf_unfiltered (file
,
6335 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6336 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6337 fprintf_unfiltered (file
,
6338 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6339 SOFTWARE_SINGLE_STEP_P ());
6340 fprintf_unfiltered (file
,
6341 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6342 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6343 #ifdef STACK_END_ADDR
6344 fprintf_unfiltered (file
,
6345 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6348 fprintf_unfiltered (file
,
6349 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6350 XSTRING (STEP_SKIPS_DELAY (PC
)));
6351 fprintf_unfiltered (file
,
6352 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6353 STEP_SKIPS_DELAY_P
);
6354 fprintf_unfiltered (file
,
6355 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6356 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6357 fprintf_unfiltered (file
,
6358 "mips_dump_tdep: T9_REGNUM = %d\n",
6360 fprintf_unfiltered (file
,
6361 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6362 fprintf_unfiltered (file
,
6363 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6364 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6365 fprintf_unfiltered (file
,
6366 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6367 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6369 fprintf_unfiltered (file
,
6370 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6371 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6374 fprintf_unfiltered (file
,
6375 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6378 #ifdef TRACE_FLAVOR_SIZE
6379 fprintf_unfiltered (file
,
6380 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6384 fprintf_unfiltered (file
,
6385 "mips_dump_tdep: TRACE_SET # %s\n",
6386 XSTRING (TRACE_SET (X
,STATE
)));
6388 #ifdef UNUSED_REGNUM
6389 fprintf_unfiltered (file
,
6390 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6393 fprintf_unfiltered (file
,
6394 "mips_dump_tdep: V0_REGNUM = %d\n",
6396 fprintf_unfiltered (file
,
6397 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6398 (long) VM_MIN_ADDRESS
);
6399 fprintf_unfiltered (file
,
6400 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6402 fprintf_unfiltered (file
,
6403 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6407 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6410 _initialize_mips_tdep (void)
6412 static struct cmd_list_element
*mipsfpulist
= NULL
;
6413 struct cmd_list_element
*c
;
6415 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6416 if (MIPS_ABI_LAST
+ 1
6417 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6418 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6420 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6422 /* Add root prefix command for all "set mips"/"show mips" commands */
6423 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6424 "Various MIPS specific commands.",
6425 &setmipscmdlist
, "set mips ", 0, &setlist
);
6427 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6428 "Various MIPS specific commands.",
6429 &showmipscmdlist
, "show mips ", 0, &showlist
);
6431 /* Allow the user to override the saved register size. */
6432 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6435 &mips_saved_regsize_string
, "\
6436 Set size of general purpose registers saved on the stack.\n\
6437 This option can be set to one of:\n\
6438 32 - Force GDB to treat saved GP registers as 32-bit\n\
6439 64 - Force GDB to treat saved GP registers as 64-bit\n\
6440 auto - Allow GDB to use the target's default setting or autodetect the\n\
6441 saved GP register size from information contained in the executable.\n\
6446 /* Allow the user to override the argument stack size. */
6447 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6450 &mips_stack_argsize_string
, "\
6451 Set the amount of stack space reserved for each argument.\n\
6452 This option can be set to one of:\n\
6453 32 - Force GDB to allocate 32-bit chunks per argument\n\
6454 64 - Force GDB to allocate 64-bit chunks per argument\n\
6455 auto - Allow GDB to determine the correct setting from the current\n\
6456 target and executable (default)",
6460 /* Allow the user to override the ABI. */
6461 c
= add_set_enum_cmd
6462 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6463 "Set the ABI used by this program.\n"
6464 "This option can be set to one of:\n"
6465 " auto - the default ABI associated with the current binary\n"
6473 set_cmd_sfunc (c
, mips_abi_update
);
6474 add_cmd ("abi", class_obscure
, show_mips_abi
,
6475 "Show ABI in use by MIPS target", &showmipscmdlist
);
6477 /* Let the user turn off floating point and set the fence post for
6478 heuristic_proc_start. */
6480 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6481 "Set use of MIPS floating-point coprocessor.",
6482 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6483 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6484 "Select single-precision MIPS floating-point coprocessor.",
6486 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6487 "Select double-precision MIPS floating-point coprocessor.",
6489 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6490 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6491 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6492 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6493 "Select no MIPS floating-point coprocessor.",
6495 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6496 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6497 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6498 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6499 "Select MIPS floating-point coprocessor automatically.",
6501 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6502 "Show current use of MIPS floating-point coprocessor target.",
6505 /* We really would like to have both "0" and "unlimited" work, but
6506 command.c doesn't deal with that. So make it a var_zinteger
6507 because the user can always use "999999" or some such for unlimited. */
6508 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6509 (char *) &heuristic_fence_post
,
6511 Set the distance searched for the start of a function.\n\
6512 If you are debugging a stripped executable, GDB needs to search through the\n\
6513 program for the start of a function. This command sets the distance of the\n\
6514 search. The only need to set it is when debugging a stripped executable.",
6516 /* We need to throw away the frame cache when we set this, since it
6517 might change our ability to get backtraces. */
6518 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6519 add_show_from_set (c
, &showlist
);
6521 /* Allow the user to control whether the upper bits of 64-bit
6522 addresses should be zeroed. */
6523 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6524 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6525 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6526 allow GDB to determine the correct value.\n", "\
6527 Show zeroing of upper 32 bits of 64-bit addresses.",
6528 NULL
, show_mask_address
,
6529 &setmipscmdlist
, &showmipscmdlist
);
6531 /* Allow the user to control the size of 32 bit registers within the
6532 raw remote packet. */
6533 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6534 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6535 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6536 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6537 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6538 64 bits for others. Use \"off\" to disable compatibility mode", "\
6539 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6540 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6541 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6542 64 bits for others. Use \"off\" to disable compatibility mode",
6543 set_mips64_transfers_32bit_regs
, NULL
,
6544 &setlist
, &showlist
);
6546 /* Debug this files internals. */
6547 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6548 &mips_debug
, "Set mips debugging.\n\
6549 When non-zero, mips specific debugging is enabled.", &setdebuglist
),