1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
225 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
226 deprecated_read_register_gen (regnum
, buf
);
227 return (extract_signed_integer
228 (buf
, register_size (current_gdbarch
, regnum
)));
232 read_signed_register_pid (int regnum
, ptid_t ptid
)
237 if (ptid_equal (ptid
, inferior_ptid
))
238 return read_signed_register (regnum
);
240 save_ptid
= inferior_ptid
;
242 inferior_ptid
= ptid
;
244 retval
= read_signed_register (regnum
);
246 inferior_ptid
= save_ptid
;
251 /* Return the MIPS ABI associated with GDBARCH. */
253 mips_abi (struct gdbarch
*gdbarch
)
255 return gdbarch_tdep (gdbarch
)->mips_abi
;
259 mips_isa_regsize (struct gdbarch
*gdbarch
)
261 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
262 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
265 /* Return the currently configured (or set) saved register size. */
267 static const char *mips_abi_regsize_string
= size_auto
;
270 mips_abi_regsize (struct gdbarch
*gdbarch
)
272 if (mips_abi_regsize_string
== size_auto
)
273 switch (mips_abi (gdbarch
))
275 case MIPS_ABI_EABI32
:
281 case MIPS_ABI_EABI64
:
283 case MIPS_ABI_UNKNOWN
:
286 internal_error (__FILE__
, __LINE__
, "bad switch");
288 else if (mips_abi_regsize_string
== size_64
)
290 else /* if (mips_abi_regsize_string == size_32) */
294 /* Functions for setting and testing a bit in a minimal symbol that
295 marks it as 16-bit function. The MSB of the minimal symbol's
296 "info" field is used for this purpose.
298 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
299 i.e. refers to a 16-bit function, and sets a "special" bit in a
300 minimal symbol to mark it as a 16-bit function
302 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
305 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
307 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
309 MSYMBOL_INFO (msym
) = (char *)
310 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
311 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
316 msymbol_is_special (struct minimal_symbol
*msym
)
318 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
321 /* XFER a value from the big/little/left end of the register.
322 Depending on the size of the value it might occupy the entire
323 register or just part of it. Make an allowance for this, aligning
324 things accordingly. */
327 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
328 enum bfd_endian endian
, bfd_byte
* in
,
329 const bfd_byte
* out
, int buf_offset
)
332 gdb_assert (reg_num
>= NUM_REGS
);
333 /* Need to transfer the left or right part of the register, based on
334 the targets byte order. */
338 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
340 case BFD_ENDIAN_LITTLE
:
343 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
347 internal_error (__FILE__
, __LINE__
, "bad switch");
350 fprintf_unfiltered (gdb_stderr
,
351 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
352 reg_num
, reg_offset
, buf_offset
, length
);
353 if (mips_debug
&& out
!= NULL
)
356 fprintf_unfiltered (gdb_stdlog
, "out ");
357 for (i
= 0; i
< length
; i
++)
358 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
361 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
364 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
366 if (mips_debug
&& in
!= NULL
)
369 fprintf_unfiltered (gdb_stdlog
, "in ");
370 for (i
= 0; i
< length
; i
++)
371 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
374 fprintf_unfiltered (gdb_stdlog
, "\n");
377 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
378 compatiblity mode. A return value of 1 means that we have
379 physical 64-bit registers, but should treat them as 32-bit registers. */
382 mips2_fp_compat (void)
384 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
386 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
391 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
392 in all the places we deal with FP registers. PR gdb/413. */
393 /* Otherwise check the FR bit in the status register - it controls
394 the FP compatiblity mode. If it is clear we are in compatibility
396 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
403 /* The amount of space reserved on the stack for registers. This is
404 different to MIPS_ABI_REGSIZE as it determines the alignment of
405 data allocated after the registers have run out. */
407 static const char *mips_stack_argsize_string
= size_auto
;
410 mips_stack_argsize (struct gdbarch
*gdbarch
)
412 if (mips_stack_argsize_string
== size_auto
)
413 return mips_abi_regsize (gdbarch
);
414 else if (mips_stack_argsize_string
== size_64
)
416 else /* if (mips_stack_argsize_string == size_32) */
420 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
422 struct mips_frame_cache
;
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
425 struct mips_frame_cache
*);
426 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
429 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
431 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
433 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
435 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
437 static struct type
*mips_float_register_type (void);
438 static struct type
*mips_double_register_type (void);
440 /* The list of available "set mips " and "show mips " commands */
442 static struct cmd_list_element
*setmipscmdlist
= NULL
;
443 static struct cmd_list_element
*showmipscmdlist
= NULL
;
445 /* FIXME: brobecker/2004-10-15: I suspect these two declarations can
446 be removed by a better ordering of the functions below. But I want
447 to do that as a separate change later in order to separate real
448 changes and changes that just move some code around. */
449 static CORE_ADDR
mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
450 struct frame_info
*next_frame
,
451 struct mips_frame_cache
*this_cache
);
452 static CORE_ADDR
mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
453 struct frame_info
*next_frame
,
454 struct mips_frame_cache
*this_cache
);
456 /* Integer registers 0 thru 31 are handled explicitly by
457 mips_register_name(). Processor specific registers 32 and above
458 are listed in the followign tables. */
461 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
465 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
466 "sr", "lo", "hi", "bad", "cause", "pc",
467 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
468 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
469 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
470 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
471 "fsr", "fir", "" /*"fp" */ , "",
472 "", "", "", "", "", "", "", "",
473 "", "", "", "", "", "", "", "",
476 /* Names of IDT R3041 registers. */
478 static const char *mips_r3041_reg_names
[] = {
479 "sr", "lo", "hi", "bad", "cause", "pc",
480 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
481 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
482 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
483 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
484 "fsr", "fir", "", /*"fp" */ "",
485 "", "", "bus", "ccfg", "", "", "", "",
486 "", "", "port", "cmp", "", "", "epc", "prid",
489 /* Names of tx39 registers. */
491 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
492 "sr", "lo", "hi", "bad", "cause", "pc",
493 "", "", "", "", "", "", "", "",
494 "", "", "", "", "", "", "", "",
495 "", "", "", "", "", "", "", "",
496 "", "", "", "", "", "", "", "",
498 "", "", "", "", "", "", "", "",
499 "", "", "config", "cache", "debug", "depc", "epc", ""
502 /* Names of IRIX registers. */
503 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
504 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
505 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
506 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
507 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
508 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
512 /* Return the name of the register corresponding to REGNO. */
514 mips_register_name (int regno
)
516 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
517 /* GPR names for all ABIs other than n32/n64. */
518 static char *mips_gpr_names
[] = {
519 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
520 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
521 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
522 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
525 /* GPR names for n32 and n64 ABIs. */
526 static char *mips_n32_n64_gpr_names
[] = {
527 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
528 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
529 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
530 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
533 enum mips_abi abi
= mips_abi (current_gdbarch
);
535 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
536 don't make the raw register names visible. */
537 int rawnum
= regno
% NUM_REGS
;
538 if (regno
< NUM_REGS
)
541 /* The MIPS integer registers are always mapped from 0 to 31. The
542 names of the registers (which reflects the conventions regarding
543 register use) vary depending on the ABI. */
544 if (0 <= rawnum
&& rawnum
< 32)
546 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
547 return mips_n32_n64_gpr_names
[rawnum
];
549 return mips_gpr_names
[rawnum
];
551 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
553 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
554 return tdep
->mips_processor_reg_names
[rawnum
- 32];
557 internal_error (__FILE__
, __LINE__
,
558 "mips_register_name: bad register number %d", rawnum
);
561 /* Return the groups that a MIPS register can be categorised into. */
564 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
565 struct reggroup
*reggroup
)
570 int rawnum
= regnum
% NUM_REGS
;
571 int pseudo
= regnum
/ NUM_REGS
;
572 if (reggroup
== all_reggroup
)
574 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
575 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
576 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
577 (gdbarch), as not all architectures are multi-arch. */
578 raw_p
= rawnum
< NUM_REGS
;
579 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
581 if (reggroup
== float_reggroup
)
582 return float_p
&& pseudo
;
583 if (reggroup
== vector_reggroup
)
584 return vector_p
&& pseudo
;
585 if (reggroup
== general_reggroup
)
586 return (!vector_p
&& !float_p
) && pseudo
;
587 /* Save the pseudo registers. Need to make certain that any code
588 extracting register values from a saved register cache also uses
590 if (reggroup
== save_reggroup
)
591 return raw_p
&& pseudo
;
592 /* Restore the same pseudo register. */
593 if (reggroup
== restore_reggroup
)
594 return raw_p
&& pseudo
;
598 /* Map the symbol table registers which live in the range [1 *
599 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
600 registers. Take care of alignment and size problems. */
603 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
604 int cookednum
, void *buf
)
606 int rawnum
= cookednum
% NUM_REGS
;
607 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
608 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
609 regcache_raw_read (regcache
, rawnum
, buf
);
610 else if (register_size (gdbarch
, rawnum
) >
611 register_size (gdbarch
, cookednum
))
613 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
614 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
615 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
617 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
620 internal_error (__FILE__
, __LINE__
, "bad register size");
624 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
625 struct regcache
*regcache
, int cookednum
,
628 int rawnum
= cookednum
% NUM_REGS
;
629 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
630 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
631 regcache_raw_write (regcache
, rawnum
, buf
);
632 else if (register_size (gdbarch
, rawnum
) >
633 register_size (gdbarch
, cookednum
))
635 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
636 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
637 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
639 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
642 internal_error (__FILE__
, __LINE__
, "bad register size");
645 /* Table to translate MIPS16 register field to actual register number. */
646 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
648 /* Heuristic_proc_start may hunt through the text section for a long
649 time across a 2400 baud serial line. Allows the user to limit this
652 static unsigned int heuristic_fence_post
= 0;
654 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
655 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
656 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
657 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
658 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
659 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
660 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
661 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
662 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
663 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
664 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
665 this will corrupt pdr.iline. Fortunately we don't use it. */
666 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
667 #define _PROC_MAGIC_ 0x0F0F0F0F
669 /* Number of bytes of storage in the actual machine representation for
670 register N. NOTE: This defines the pseudo register type so need to
671 rebuild the architecture vector. */
673 static int mips64_transfers_32bit_regs_p
= 0;
676 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
677 struct cmd_list_element
*c
)
679 struct gdbarch_info info
;
680 gdbarch_info_init (&info
);
681 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
682 instead of relying on globals. Doing that would let generic code
683 handle the search for this specific architecture. */
684 if (!gdbarch_update_p (info
))
686 mips64_transfers_32bit_regs_p
= 0;
687 error ("32-bit compatibility mode not supported");
691 /* Convert to/from a register and the corresponding memory value. */
694 mips_convert_register_p (int regnum
, struct type
*type
)
696 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
697 && register_size (current_gdbarch
, regnum
) == 4
698 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
699 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
700 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
704 mips_register_to_value (struct frame_info
*frame
, int regnum
,
705 struct type
*type
, void *to
)
707 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
708 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
712 mips_value_to_register (struct frame_info
*frame
, int regnum
,
713 struct type
*type
, const void *from
)
715 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
716 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
719 /* Return the GDB type object for the "standard" data type of data in
723 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
725 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
726 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
727 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
729 /* The floating-point registers raw, or cooked, always match
730 mips_isa_regsize(), and also map 1:1, byte for byte. */
731 switch (gdbarch_byte_order (gdbarch
))
734 if (mips_isa_regsize (gdbarch
) == 4)
735 return builtin_type_ieee_single_big
;
737 return builtin_type_ieee_double_big
;
738 case BFD_ENDIAN_LITTLE
:
739 if (mips_isa_regsize (gdbarch
) == 4)
740 return builtin_type_ieee_single_little
;
742 return builtin_type_ieee_double_little
;
743 case BFD_ENDIAN_UNKNOWN
:
745 internal_error (__FILE__
, __LINE__
, "bad switch");
748 else if (regnum
< NUM_REGS
)
750 /* The raw or ISA registers. These are all sized according to
752 if (mips_isa_regsize (gdbarch
) == 4)
753 return builtin_type_int32
;
755 return builtin_type_int64
;
759 /* The cooked or ABI registers. These are sized according to
760 the ABI (with a few complications). */
761 if (regnum
>= (NUM_REGS
762 + mips_regnum (current_gdbarch
)->fp_control_status
)
763 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
764 /* The pseudo/cooked view of the embedded registers is always
765 32-bit. The raw view is handled below. */
766 return builtin_type_int32
;
767 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
768 /* The target, while possibly using a 64-bit register buffer,
769 is only transfering 32-bits of each integer register.
770 Reflect this in the cooked/pseudo (ABI) register value. */
771 return builtin_type_int32
;
772 else if (mips_abi_regsize (gdbarch
) == 4)
773 /* The ABI is restricted to 32-bit registers (the ISA could be
775 return builtin_type_int32
;
778 return builtin_type_int64
;
782 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
787 return read_signed_register (MIPS_SP_REGNUM
);
790 /* Should the upper word of 64-bit addresses be zeroed? */
791 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
794 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
796 switch (mask_address_var
)
798 case AUTO_BOOLEAN_TRUE
:
800 case AUTO_BOOLEAN_FALSE
:
803 case AUTO_BOOLEAN_AUTO
:
804 return tdep
->default_mask_address_p
;
806 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
812 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
814 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
815 switch (mask_address_var
)
817 case AUTO_BOOLEAN_TRUE
:
818 printf_filtered ("The 32 bit mips address mask is enabled\n");
820 case AUTO_BOOLEAN_FALSE
:
821 printf_filtered ("The 32 bit mips address mask is disabled\n");
823 case AUTO_BOOLEAN_AUTO
:
825 ("The 32 bit address mask is set automatically. Currently %s\n",
826 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
829 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
834 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
837 pc_is_mips16 (bfd_vma memaddr
)
839 struct minimal_symbol
*sym
;
841 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
842 if (is_mips16_addr (memaddr
))
845 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
846 the high bit of the info field. Use this to decide if the function is
847 MIPS16 or normal MIPS. */
848 sym
= lookup_minimal_symbol_by_pc (memaddr
);
850 return msymbol_is_special (sym
);
855 /* MIPS believes that the PC has a sign extended value. Perhaps the
856 all registers should be sign extended for simplicity? */
859 mips_read_pc (ptid_t ptid
)
861 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
865 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
867 return frame_unwind_register_signed (next_frame
,
868 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
871 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
872 dummy frame. The frame ID's base needs to match the TOS value
873 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
876 static struct frame_id
877 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
879 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
880 frame_pc_unwind (next_frame
));
884 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
886 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
889 /* This returns the PC of the first inst after the prologue. If we can't
890 find the prologue, then return 0. */
893 after_prologue (CORE_ADDR pc
)
895 mips_extra_func_info_t proc_desc
;
896 struct symtab_and_line sal
;
897 CORE_ADDR func_addr
, func_end
;
898 CORE_ADDR startaddr
= 0;
900 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
901 attempt to read the stack pointer from the current machine state,
902 because the current machine state has nothing to do with the
903 information we need from the proc_desc; and the process may or
904 may not exist right now. */
905 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
908 /* IF this is the topmost frame AND (this proc does not have
909 debugging information OR the PC is in the procedure prologue)
910 THEN create a "heuristic" proc_desc (by analyzing the actual
911 code) to replace the "official" proc_desc. */
912 struct symtab_and_line val
;
913 if (PROC_SYMBOL (proc_desc
))
915 val
= find_pc_line (BLOCK_START
916 (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc
))),
918 val
.pc
= val
.end
? val
.end
: pc
;
920 if (!PROC_SYMBOL (proc_desc
) || pc
< val
.pc
)
922 mips_extra_func_info_t found_heuristic
=
923 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
, NULL
);
925 proc_desc
= found_heuristic
;
931 startaddr
= heuristic_proc_start (pc
);
933 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
, NULL
);
938 /* If function is frameless, then we need to do it the hard way. I
939 strongly suspect that frameless always means prologueless... */
940 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
941 && PROC_FRAME_OFFSET (proc_desc
) == 0)
945 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
946 return 0; /* Unknown */
948 sal
= find_pc_line (func_addr
, 0);
950 if (sal
.end
< func_end
)
953 /* The line after the prologue is after the end of the function. In this
954 case, tell the caller to find the prologue the hard way. */
959 /* Fetch and return instruction from the specified location. If the PC
960 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
963 mips_fetch_instruction (CORE_ADDR addr
)
965 char buf
[MIPS_INSTLEN
];
969 if (pc_is_mips16 (addr
))
971 instlen
= MIPS16_INSTLEN
;
972 addr
= unmake_mips16_addr (addr
);
975 instlen
= MIPS_INSTLEN
;
976 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
978 memory_error (status
, addr
);
979 return extract_unsigned_integer (buf
, instlen
);
983 mips16_fetch_instruction (CORE_ADDR addr
)
985 char buf
[MIPS_INSTLEN
];
989 instlen
= MIPS16_INSTLEN
;
990 addr
= unmake_mips16_addr (addr
);
991 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
993 memory_error (status
, addr
);
994 return extract_unsigned_integer (buf
, instlen
);
997 /* These the fields of 32 bit mips instructions */
998 #define mips32_op(x) (x >> 26)
999 #define itype_op(x) (x >> 26)
1000 #define itype_rs(x) ((x >> 21) & 0x1f)
1001 #define itype_rt(x) ((x >> 16) & 0x1f)
1002 #define itype_immediate(x) (x & 0xffff)
1004 #define jtype_op(x) (x >> 26)
1005 #define jtype_target(x) (x & 0x03ffffff)
1007 #define rtype_op(x) (x >> 26)
1008 #define rtype_rs(x) ((x >> 21) & 0x1f)
1009 #define rtype_rt(x) ((x >> 16) & 0x1f)
1010 #define rtype_rd(x) ((x >> 11) & 0x1f)
1011 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1012 #define rtype_funct(x) (x & 0x3f)
1015 mips32_relative_offset (unsigned long inst
)
1018 x
= itype_immediate (inst
);
1019 if (x
& 0x8000) /* sign bit set */
1021 x
|= 0xffff0000; /* sign extension */
1027 /* Determine whate to set a single step breakpoint while considering
1028 branch prediction */
1030 mips32_next_pc (CORE_ADDR pc
)
1034 inst
= mips_fetch_instruction (pc
);
1035 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1037 if (itype_op (inst
) >> 2 == 5)
1038 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1040 op
= (itype_op (inst
) & 0x03);
1050 goto greater_branch
;
1055 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1056 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1058 int tf
= itype_rt (inst
) & 0x01;
1059 int cnum
= itype_rt (inst
) >> 2;
1061 read_signed_register (mips_regnum (current_gdbarch
)->
1063 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1065 if (((cond
>> cnum
) & 0x01) == tf
)
1066 pc
+= mips32_relative_offset (inst
) + 4;
1071 pc
+= 4; /* Not a branch, next instruction is easy */
1074 { /* This gets way messy */
1076 /* Further subdivide into SPECIAL, REGIMM and other */
1077 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1079 case 0: /* SPECIAL */
1080 op
= rtype_funct (inst
);
1085 /* Set PC to that address */
1086 pc
= read_signed_register (rtype_rs (inst
));
1092 break; /* end SPECIAL */
1093 case 1: /* REGIMM */
1095 op
= itype_rt (inst
); /* branch condition */
1100 case 16: /* BLTZAL */
1101 case 18: /* BLTZALL */
1103 if (read_signed_register (itype_rs (inst
)) < 0)
1104 pc
+= mips32_relative_offset (inst
) + 4;
1106 pc
+= 8; /* after the delay slot */
1110 case 17: /* BGEZAL */
1111 case 19: /* BGEZALL */
1112 if (read_signed_register (itype_rs (inst
)) >= 0)
1113 pc
+= mips32_relative_offset (inst
) + 4;
1115 pc
+= 8; /* after the delay slot */
1117 /* All of the other instructions in the REGIMM category */
1122 break; /* end REGIMM */
1127 reg
= jtype_target (inst
) << 2;
1128 /* Upper four bits get never changed... */
1129 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1132 /* FIXME case JALX : */
1135 reg
= jtype_target (inst
) << 2;
1136 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1137 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1139 break; /* The new PC will be alternate mode */
1140 case 4: /* BEQ, BEQL */
1142 if (read_signed_register (itype_rs (inst
)) ==
1143 read_signed_register (itype_rt (inst
)))
1144 pc
+= mips32_relative_offset (inst
) + 4;
1148 case 5: /* BNE, BNEL */
1150 if (read_signed_register (itype_rs (inst
)) !=
1151 read_signed_register (itype_rt (inst
)))
1152 pc
+= mips32_relative_offset (inst
) + 4;
1156 case 6: /* BLEZ, BLEZL */
1157 if (read_signed_register (itype_rs (inst
)) <= 0)
1158 pc
+= mips32_relative_offset (inst
) + 4;
1164 greater_branch
: /* BGTZ, BGTZL */
1165 if (read_signed_register (itype_rs (inst
)) > 0)
1166 pc
+= mips32_relative_offset (inst
) + 4;
1173 } /* mips32_next_pc */
1175 /* Decoding the next place to set a breakpoint is irregular for the
1176 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1177 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1178 We dont want to set a single step instruction on the extend instruction
1182 /* Lots of mips16 instruction formats */
1183 /* Predicting jumps requires itype,ritype,i8type
1184 and their extensions extItype,extritype,extI8type
1186 enum mips16_inst_fmts
1188 itype
, /* 0 immediate 5,10 */
1189 ritype
, /* 1 5,3,8 */
1190 rrtype
, /* 2 5,3,3,5 */
1191 rritype
, /* 3 5,3,3,5 */
1192 rrrtype
, /* 4 5,3,3,3,2 */
1193 rriatype
, /* 5 5,3,3,1,4 */
1194 shifttype
, /* 6 5,3,3,3,2 */
1195 i8type
, /* 7 5,3,8 */
1196 i8movtype
, /* 8 5,3,3,5 */
1197 i8mov32rtype
, /* 9 5,3,5,3 */
1198 i64type
, /* 10 5,3,8 */
1199 ri64type
, /* 11 5,3,3,5 */
1200 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1201 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1202 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1203 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1204 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1205 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1206 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1207 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1208 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1209 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1211 /* I am heaping all the fields of the formats into one structure and
1212 then, only the fields which are involved in instruction extension */
1216 unsigned int regx
; /* Function in i8 type */
1221 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1222 for the bits which make up the immediatate extension. */
1225 extended_offset (unsigned int extension
)
1228 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1230 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1232 value
|= extension
& 0x01f; /* extract 4:0 */
1236 /* Only call this function if you know that this is an extendable
1237 instruction, It wont malfunction, but why make excess remote memory references?
1238 If the immediate operands get sign extended or somthing, do it after
1239 the extension is performed.
1241 /* FIXME: Every one of these cases needs to worry about sign extension
1242 when the offset is to be used in relative addressing */
1246 fetch_mips_16 (CORE_ADDR pc
)
1249 pc
&= 0xfffffffe; /* clear the low order bit */
1250 target_read_memory (pc
, buf
, 2);
1251 return extract_unsigned_integer (buf
, 2);
1255 unpack_mips16 (CORE_ADDR pc
,
1256 unsigned int extension
,
1258 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1263 switch (insn_format
)
1270 value
= extended_offset (extension
);
1271 value
= value
<< 11; /* rom for the original value */
1272 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1276 value
= inst
& 0x7ff;
1277 /* FIXME : Consider sign extension */
1286 { /* A register identifier and an offset */
1287 /* Most of the fields are the same as I type but the
1288 immediate value is of a different length */
1292 value
= extended_offset (extension
);
1293 value
= value
<< 8; /* from the original instruction */
1294 value
|= inst
& 0xff; /* eleven bits from instruction */
1295 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1296 if (value
& 0x4000) /* test the sign bit , bit 26 */
1298 value
&= ~0x3fff; /* remove the sign bit */
1304 value
= inst
& 0xff; /* 8 bits */
1305 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1306 /* FIXME: Do sign extension , this format needs it */
1307 if (value
& 0x80) /* THIS CONFUSES ME */
1309 value
&= 0xef; /* remove the sign bit */
1319 unsigned long value
;
1320 unsigned int nexthalf
;
1321 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1322 value
= value
<< 16;
1323 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1331 internal_error (__FILE__
, __LINE__
, "bad switch");
1333 upk
->offset
= offset
;
1340 add_offset_16 (CORE_ADDR pc
, int offset
)
1342 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1346 extended_mips16_next_pc (CORE_ADDR pc
,
1347 unsigned int extension
, unsigned int insn
)
1349 int op
= (insn
>> 11);
1352 case 2: /* Branch */
1355 struct upk_mips16 upk
;
1356 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1357 offset
= upk
.offset
;
1363 pc
+= (offset
<< 1) + 2;
1366 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1368 struct upk_mips16 upk
;
1369 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1370 pc
= add_offset_16 (pc
, upk
.offset
);
1371 if ((insn
>> 10) & 0x01) /* Exchange mode */
1372 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1379 struct upk_mips16 upk
;
1381 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1382 reg
= read_signed_register (upk
.regx
);
1384 pc
+= (upk
.offset
<< 1) + 2;
1391 struct upk_mips16 upk
;
1393 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1394 reg
= read_signed_register (upk
.regx
);
1396 pc
+= (upk
.offset
<< 1) + 2;
1401 case 12: /* I8 Formats btez btnez */
1403 struct upk_mips16 upk
;
1405 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1406 /* upk.regx contains the opcode */
1407 reg
= read_signed_register (24); /* Test register is 24 */
1408 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1409 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1410 /* pc = add_offset_16(pc,upk.offset) ; */
1411 pc
+= (upk
.offset
<< 1) + 2;
1416 case 29: /* RR Formats JR, JALR, JALR-RA */
1418 struct upk_mips16 upk
;
1419 /* upk.fmt = rrtype; */
1424 upk
.regx
= (insn
>> 8) & 0x07;
1425 upk
.regy
= (insn
>> 5) & 0x07;
1433 break; /* Function return instruction */
1439 break; /* BOGUS Guess */
1441 pc
= read_signed_register (reg
);
1448 /* This is an instruction extension. Fetch the real instruction
1449 (which follows the extension) and decode things based on
1453 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1466 mips16_next_pc (CORE_ADDR pc
)
1468 unsigned int insn
= fetch_mips_16 (pc
);
1469 return extended_mips16_next_pc (pc
, 0, insn
);
1472 /* The mips_next_pc function supports single_step when the remote
1473 target monitor or stub is not developed enough to do a single_step.
1474 It works by decoding the current instruction and predicting where a
1475 branch will go. This isnt hard because all the data is available.
1476 The MIPS32 and MIPS16 variants are quite different */
1478 mips_next_pc (CORE_ADDR pc
)
1481 return mips16_next_pc (pc
);
1483 return mips32_next_pc (pc
);
1486 struct mips_frame_cache
1489 struct trad_frame_saved_reg
*saved_regs
;
1493 static struct mips_frame_cache
*
1494 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1496 CORE_ADDR startaddr
= 0;
1497 mips_extra_func_info_t proc_desc
;
1498 struct mips_frame_cache
*cache
;
1499 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1500 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1501 /* r0 bit means kernel trap */
1503 /* What registers have been saved? Bitmasks. */
1504 unsigned long gen_mask
, float_mask
;
1506 if ((*this_cache
) != NULL
)
1507 return (*this_cache
);
1508 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1509 (*this_cache
) = cache
;
1510 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1512 /* Get the mdebug proc descriptor. */
1513 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1515 /* Must be true. This is only called when the sniffer detected a
1517 gdb_assert (proc_desc
!= NULL
);
1519 /* Extract the frame's base. */
1520 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1521 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1523 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1524 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1525 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1527 /* Must be true. The in_prologue case is left for the heuristic
1528 unwinder. This is always used on kernel traps. */
1529 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1532 /* Fill in the offsets for the registers which gen_mask says were
1535 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1538 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1539 if (gen_mask
& 0x80000000)
1541 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1542 reg_position
-= mips_abi_regsize (gdbarch
);
1546 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1547 order of that normally used by gcc. Therefore, we have to fetch
1548 the first instruction of the function, and if it's an entry
1549 instruction that saves $s0 or $s1, correct their saved addresses. */
1550 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1552 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1553 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1557 int sreg_count
= (inst
>> 6) & 3;
1559 /* Check if the ra register was pushed on the stack. */
1560 CORE_ADDR reg_position
= (cache
->base
1561 + PROC_REG_OFFSET (proc_desc
));
1563 reg_position
-= mips_abi_regsize (gdbarch
);
1565 /* Check if the s0 and s1 registers were pushed on the
1567 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1569 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1571 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1572 reg_position
-= mips_abi_regsize (gdbarch
);
1577 /* Fill in the offsets for the registers which float_mask says were
1580 CORE_ADDR reg_position
= (cache
->base
1581 + PROC_FREG_OFFSET (proc_desc
));
1583 /* Fill in the offsets for the float registers which float_mask
1585 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1586 if (float_mask
& 0x80000000)
1588 if (mips_abi_regsize (gdbarch
) == 4
1589 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1591 /* On a big endian 32 bit ABI, floating point registers
1592 are paired to form doubles such that the most
1593 significant part is in $f[N+1] and the least
1594 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1595 registers are also spilled as a pair and stored as a
1598 When little-endian the least significant part is
1599 stored first leading to the memory order $f[N] and
1602 Unfortunately, when big-endian the most significant
1603 part of the double is stored first, and the least
1604 significant is stored second. This leads to the
1605 registers being ordered in memory as firt $f[N+1] and
1608 For the big-endian case make certain that the
1609 addresses point at the correct (swapped) locations
1610 $f[N] and $f[N+1] pair (keep in mind that
1611 reg_position is decremented each time through the
1614 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1615 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1617 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1618 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1621 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1622 .addr
= reg_position
;
1623 reg_position
-= mips_abi_regsize (gdbarch
);
1626 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1627 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1630 /* SP_REGNUM, contains the value and not the address. */
1631 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1633 return (*this_cache
);
1637 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1638 struct frame_id
*this_id
)
1640 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1642 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1646 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1648 int regnum
, int *optimizedp
,
1649 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1650 int *realnump
, void *valuep
)
1652 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1654 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1655 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1658 static const struct frame_unwind mips_mdebug_frame_unwind
=
1661 mips_mdebug_frame_this_id
,
1662 mips_mdebug_frame_prev_register
1665 static const struct frame_unwind
*
1666 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1668 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1669 CORE_ADDR startaddr
= 0;
1670 mips_extra_func_info_t proc_desc
;
1673 /* Only use the mdebug frame unwinder on mdebug frames where all the
1674 registers have been saved. Leave hard cases such as no mdebug or
1675 in prologue for the heuristic unwinders. */
1677 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1678 if (proc_desc
== NULL
)
1681 /* Not sure exactly what kernel_trap means, but if it means the
1682 kernel saves the registers without a prologue doing it, we better
1683 not examine the prologue to see whether registers have been saved
1685 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1687 return &mips_mdebug_frame_unwind
;
1689 /* In any frame other than the innermost or a frame interrupted by a
1690 signal, we assume that all registers have been saved. This
1691 assumes that all register saves in a function happen before the
1692 first function call. */
1693 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1694 return &mips_mdebug_frame_unwind
;
1700 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1703 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1708 static const struct frame_base mips_mdebug_frame_base
= {
1709 &mips_mdebug_frame_unwind
,
1710 mips_mdebug_frame_base_address
,
1711 mips_mdebug_frame_base_address
,
1712 mips_mdebug_frame_base_address
1715 static const struct frame_base
*
1716 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1718 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1719 return &mips_mdebug_frame_base
;
1724 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1725 Procedures that use the 32-bit instruction set are handled by the
1726 mips_insn32 unwinder. */
1728 static struct mips_frame_cache
*
1729 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1731 struct mips_frame_cache
*cache
;
1733 if ((*this_cache
) != NULL
)
1734 return (*this_cache
);
1735 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1736 (*this_cache
) = cache
;
1737 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1739 /* Analyze the function prologue. */
1741 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1742 CORE_ADDR start_addr
;
1744 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1745 if (start_addr
== 0)
1746 start_addr
= heuristic_proc_start (pc
);
1747 /* We can't analyze the prologue if we couldn't find the begining
1749 if (start_addr
== 0)
1752 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1755 /* SP_REGNUM, contains the value and not the address. */
1756 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1758 return (*this_cache
);
1762 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1763 struct frame_id
*this_id
)
1765 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1767 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1771 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1773 int regnum
, int *optimizedp
,
1774 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1775 int *realnump
, void *valuep
)
1777 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1779 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1780 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1783 static const struct frame_unwind mips_insn16_frame_unwind
=
1786 mips_insn16_frame_this_id
,
1787 mips_insn16_frame_prev_register
1790 static const struct frame_unwind
*
1791 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1793 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1794 if (pc_is_mips16 (pc
))
1795 return &mips_insn16_frame_unwind
;
1800 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1803 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1808 static const struct frame_base mips_insn16_frame_base
=
1810 &mips_insn16_frame_unwind
,
1811 mips_insn16_frame_base_address
,
1812 mips_insn16_frame_base_address
,
1813 mips_insn16_frame_base_address
1816 static const struct frame_base
*
1817 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1819 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1820 return &mips_insn16_frame_base
;
1825 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1826 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1827 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1830 static struct mips_frame_cache
*
1831 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1833 struct mips_frame_cache
*cache
;
1835 if ((*this_cache
) != NULL
)
1836 return (*this_cache
);
1838 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1839 (*this_cache
) = cache
;
1840 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1842 /* Analyze the function prologue. */
1844 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1845 CORE_ADDR start_addr
;
1847 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1848 if (start_addr
== 0)
1849 start_addr
= heuristic_proc_start (pc
);
1850 /* We can't analyze the prologue if we couldn't find the begining
1852 if (start_addr
== 0)
1855 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1858 /* SP_REGNUM, contains the value and not the address. */
1859 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1861 return (*this_cache
);
1865 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1866 struct frame_id
*this_id
)
1868 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1870 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1874 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1876 int regnum
, int *optimizedp
,
1877 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1878 int *realnump
, void *valuep
)
1880 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1882 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1883 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1886 static const struct frame_unwind mips_insn32_frame_unwind
=
1889 mips_insn32_frame_this_id
,
1890 mips_insn32_frame_prev_register
1893 static const struct frame_unwind
*
1894 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
1896 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1897 if (! pc_is_mips16 (pc
))
1898 return &mips_insn32_frame_unwind
;
1903 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
1906 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1911 static const struct frame_base mips_insn32_frame_base
=
1913 &mips_insn32_frame_unwind
,
1914 mips_insn32_frame_base_address
,
1915 mips_insn32_frame_base_address
,
1916 mips_insn32_frame_base_address
1919 static const struct frame_base
*
1920 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
1922 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
1923 return &mips_insn32_frame_base
;
1928 static struct trad_frame_cache
*
1929 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1932 CORE_ADDR start_addr
;
1933 CORE_ADDR stack_addr
;
1934 struct trad_frame_cache
*this_trad_cache
;
1936 if ((*this_cache
) != NULL
)
1937 return (*this_cache
);
1938 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
1939 (*this_cache
) = this_trad_cache
;
1941 /* The return address is in the link register. */
1942 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
1944 /* Frame ID, since it's a frameless / stackless function, no stack
1945 space is allocated and SP on entry is the current SP. */
1946 pc
= frame_pc_unwind (next_frame
);
1947 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1948 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
1949 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
1951 /* Assume that the frame's base is the same as the
1953 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
1955 return this_trad_cache
;
1959 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1960 struct frame_id
*this_id
)
1962 struct trad_frame_cache
*this_trad_cache
1963 = mips_stub_frame_cache (next_frame
, this_cache
);
1964 trad_frame_get_id (this_trad_cache
, this_id
);
1968 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
1970 int regnum
, int *optimizedp
,
1971 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1972 int *realnump
, void *valuep
)
1974 struct trad_frame_cache
*this_trad_cache
1975 = mips_stub_frame_cache (next_frame
, this_cache
);
1976 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
1977 lvalp
, addrp
, realnump
, valuep
);
1980 static const struct frame_unwind mips_stub_frame_unwind
=
1983 mips_stub_frame_this_id
,
1984 mips_stub_frame_prev_register
1987 static const struct frame_unwind
*
1988 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
1990 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1991 if (in_plt_section (pc
, NULL
))
1992 return &mips_stub_frame_unwind
;
1998 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2001 struct trad_frame_cache
*this_trad_cache
2002 = mips_stub_frame_cache (next_frame
, this_cache
);
2003 return trad_frame_get_this_base (this_trad_cache
);
2006 static const struct frame_base mips_stub_frame_base
=
2008 &mips_stub_frame_unwind
,
2009 mips_stub_frame_base_address
,
2010 mips_stub_frame_base_address
,
2011 mips_stub_frame_base_address
2014 static const struct frame_base
*
2015 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2017 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2018 return &mips_stub_frame_base
;
2024 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2026 /* Always a pseudo. */
2027 gdb_assert (regno
>= NUM_REGS
);
2031 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2035 return frame_unwind_register_signed (fi
, regno
);
2039 /* mips_addr_bits_remove - remove useless address bits */
2042 mips_addr_bits_remove (CORE_ADDR addr
)
2044 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2045 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2046 /* This hack is a work-around for existing boards using PMON, the
2047 simulator, and any other 64-bit targets that doesn't have true
2048 64-bit addressing. On these targets, the upper 32 bits of
2049 addresses are ignored by the hardware. Thus, the PC or SP are
2050 likely to have been sign extended to all 1s by instruction
2051 sequences that load 32-bit addresses. For example, a typical
2052 piece of code that loads an address is this:
2054 lui $r2, <upper 16 bits>
2055 ori $r2, <lower 16 bits>
2057 But the lui sign-extends the value such that the upper 32 bits
2058 may be all 1s. The workaround is simply to mask off these
2059 bits. In the future, gcc may be changed to support true 64-bit
2060 addressing, and this masking will have to be disabled. */
2061 return addr
&= 0xffffffffUL
;
2066 /* mips_software_single_step() is called just before we want to resume
2067 the inferior, if we want to single-step it but there is no hardware
2068 or kernel single-step support (MIPS on GNU/Linux for example). We find
2069 the target of the coming instruction and breakpoint it.
2071 single_step is also called just after the inferior stops. If we had
2072 set up a simulated single-step, we undo our damage. */
2075 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2077 static CORE_ADDR next_pc
;
2078 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2079 static binsn_quantum break_mem
;
2082 if (insert_breakpoints_p
)
2084 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2085 next_pc
= mips_next_pc (pc
);
2087 target_insert_breakpoint (next_pc
, break_mem
);
2090 target_remove_breakpoint (next_pc
, break_mem
);
2093 static struct mips_extra_func_info temp_proc_desc
;
2095 /* Set a register's saved stack address in temp_saved_regs. If an
2096 address has already been set for this register, do nothing; this
2097 way we will only recognize the first save of a given register in a
2100 For simplicity, save the address in both [0 .. NUM_REGS) and
2101 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2102 is used as it is only second range (the ABI instead of ISA
2103 registers) that comes into play when finding saved registers in a
2107 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
2110 if (this_cache
!= NULL
2111 && this_cache
->saved_regs
[regnum
].addr
== -1)
2113 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
2114 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
2119 /* Test whether the PC points to the return instruction at the
2120 end of a function. */
2123 mips_about_to_return (CORE_ADDR pc
)
2125 if (pc_is_mips16 (pc
))
2126 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2127 generates a "jr $ra"; other times it generates code to load
2128 the return address from the stack to an accessible register (such
2129 as $a3), then a "jr" using that register. This second case
2130 is almost impossible to distinguish from an indirect jump
2131 used for switch statements, so we don't even try. */
2132 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2134 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2138 /* This fencepost looks highly suspicious to me. Removing it also
2139 seems suspicious as it could affect remote debugging across serial
2143 heuristic_proc_start (CORE_ADDR pc
)
2150 pc
= ADDR_BITS_REMOVE (pc
);
2152 fence
= start_pc
- heuristic_fence_post
;
2156 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2157 fence
= VM_MIN_ADDRESS
;
2159 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2161 /* search back for previous return */
2162 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2163 if (start_pc
< fence
)
2165 /* It's not clear to me why we reach this point when
2166 stop_soon, but with this test, at least we
2167 don't print out warnings for every child forked (eg, on
2168 decstation). 22apr93 rich@cygnus.com. */
2169 if (stop_soon
== NO_STOP_QUIETLY
)
2171 static int blurb_printed
= 0;
2173 warning ("GDB can't find the start of the function at 0x%s.",
2178 /* This actually happens frequently in embedded
2179 development, when you first connect to a board
2180 and your stack pointer and pc are nowhere in
2181 particular. This message needs to give people
2182 in that situation enough information to
2183 determine that it's no big deal. */
2184 printf_filtered ("\n\
2185 GDB is unable to find the start of the function at 0x%s\n\
2186 and thus can't determine the size of that function's stack frame.\n\
2187 This means that GDB may be unable to access that stack frame, or\n\
2188 the frames below it.\n\
2189 This problem is most likely caused by an invalid program counter or\n\
2191 However, if you think GDB should simply search farther back\n\
2192 from 0x%s for code which looks like the beginning of a\n\
2193 function, you can increase the range of the search using the `set\n\
2194 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2201 else if (pc_is_mips16 (start_pc
))
2203 unsigned short inst
;
2205 /* On MIPS16, any one of the following is likely to be the
2206 start of a function:
2210 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2211 inst
= mips_fetch_instruction (start_pc
);
2212 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2213 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2214 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2215 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2217 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2218 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2223 else if (mips_about_to_return (start_pc
))
2225 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2232 /* Fetch the immediate value from a MIPS16 instruction.
2233 If the previous instruction was an EXTEND, use it to extend
2234 the upper bits of the immediate value. This is a helper function
2235 for mips16_scan_prologue. */
2238 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2239 unsigned short inst
, /* current instruction */
2240 int nbits
, /* number of bits in imm field */
2241 int scale
, /* scale factor to be applied to imm */
2242 int is_signed
) /* is the imm field signed? */
2246 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2248 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2249 if (offset
& 0x8000) /* check for negative extend */
2250 offset
= 0 - (0x10000 - (offset
& 0xffff));
2251 return offset
| (inst
& 0x1f);
2255 int max_imm
= 1 << nbits
;
2256 int mask
= max_imm
- 1;
2257 int sign_bit
= max_imm
>> 1;
2259 offset
= inst
& mask
;
2260 if (is_signed
&& (offset
& sign_bit
))
2261 offset
= 0 - (max_imm
- offset
);
2262 return offset
* scale
;
2267 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2268 the associated FRAME_CACHE if not null.
2269 Return the address of the first instruction past the prologue. */
2272 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2273 struct frame_info
*next_frame
,
2274 struct mips_frame_cache
*this_cache
)
2277 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2279 long frame_offset
= 0; /* Size of stack frame. */
2280 long frame_adjust
= 0; /* Offset of FP from SP. */
2281 int frame_reg
= MIPS_SP_REGNUM
;
2282 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2283 unsigned inst
= 0; /* current instruction */
2284 unsigned entry_inst
= 0; /* the entry instruction */
2287 int extend_bytes
= 0;
2288 int prev_extend_bytes
;
2289 CORE_ADDR end_prologue_addr
= 0;
2291 /* Can be called when there's no process, and hence when there's no
2293 if (next_frame
!= NULL
)
2294 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2298 if (limit_pc
> start_pc
+ 200)
2299 limit_pc
= start_pc
+ 200;
2301 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2303 /* Save the previous instruction. If it's an EXTEND, we'll extract
2304 the immediate offset extension from it in mips16_get_imm. */
2307 /* Fetch and decode the instruction. */
2308 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2310 /* Normally we ignore extend instructions. However, if it is
2311 not followed by a valid prologue instruction, then this
2312 instruction is not part of the prologue either. We must
2313 remember in this case to adjust the end_prologue_addr back
2315 if ((inst
& 0xf800) == 0xf000) /* extend */
2317 extend_bytes
= MIPS16_INSTLEN
;
2321 prev_extend_bytes
= extend_bytes
;
2324 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2325 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2327 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2328 if (offset
< 0) /* negative stack adjustment? */
2329 frame_offset
-= offset
;
2331 /* Exit loop if a positive stack adjustment is found, which
2332 usually means that the stack cleanup code in the function
2333 epilogue is reached. */
2336 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2338 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2339 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2340 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2342 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2344 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2345 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2346 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2348 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2350 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2351 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2353 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2355 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2356 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2358 else if (inst
== 0x673d) /* move $s1, $sp */
2363 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2365 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2366 frame_addr
= sp
+ offset
;
2368 frame_adjust
= offset
;
2370 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2372 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2373 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2374 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2376 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2378 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2379 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2380 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2382 else if ((inst
& 0xf81f) == 0xe809
2383 && (inst
& 0x700) != 0x700) /* entry */
2384 entry_inst
= inst
; /* save for later processing */
2385 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2386 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2387 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2389 /* This instruction is part of the prologue, but we don't
2390 need to do anything special to handle it. */
2394 /* This instruction is not an instruction typically found
2395 in a prologue, so we must have reached the end of the
2397 if (end_prologue_addr
== 0)
2398 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
2402 /* The entry instruction is typically the first instruction in a function,
2403 and it stores registers at offsets relative to the value of the old SP
2404 (before the prologue). But the value of the sp parameter to this
2405 function is the new SP (after the prologue has been executed). So we
2406 can't calculate those offsets until we've seen the entire prologue,
2407 and can calculate what the old SP must have been. */
2408 if (entry_inst
!= 0)
2410 int areg_count
= (entry_inst
>> 8) & 7;
2411 int sreg_count
= (entry_inst
>> 6) & 3;
2413 /* The entry instruction always subtracts 32 from the SP. */
2416 /* Now we can calculate what the SP must have been at the
2417 start of the function prologue. */
2420 /* Check if a0-a3 were saved in the caller's argument save area. */
2421 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2423 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2424 offset
+= mips_abi_regsize (current_gdbarch
);
2427 /* Check if the ra register was pushed on the stack. */
2429 if (entry_inst
& 0x20)
2431 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2432 offset
-= mips_abi_regsize (current_gdbarch
);
2435 /* Check if the s0 and s1 registers were pushed on the stack. */
2436 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2438 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2439 offset
-= mips_abi_regsize (current_gdbarch
);
2443 if (this_cache
!= NULL
)
2446 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2447 + frame_offset
- frame_adjust
);
2448 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2449 be able to get rid of the assignment below, evetually. But it's
2450 still needed for now. */
2451 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2452 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2455 /* If we didn't reach the end of the prologue when scanning the function
2456 instructions, then set end_prologue_addr to the address of the
2457 instruction immediately after the last one we scanned. */
2458 if (end_prologue_addr
== 0)
2459 end_prologue_addr
= cur_pc
;
2461 return end_prologue_addr
;
2464 /* Mark all the registers as unset in the saved_regs array
2465 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2468 reset_saved_regs (struct mips_frame_cache
*this_cache
)
2470 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2474 const int num_regs
= NUM_REGS
;
2477 for (i
= 0; i
< num_regs
; i
++)
2479 this_cache
->saved_regs
[i
].addr
= -1;
2484 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2485 the associated FRAME_CACHE if not null.
2486 Return the address of the first instruction past the prologue. */
2489 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2490 struct frame_info
*next_frame
,
2491 struct mips_frame_cache
*this_cache
)
2494 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2497 int frame_reg
= MIPS_SP_REGNUM
;
2499 CORE_ADDR end_prologue_addr
= 0;
2500 int seen_sp_adjust
= 0;
2501 int load_immediate_bytes
= 0;
2503 /* Can be called when there's no process, and hence when there's no
2505 if (next_frame
!= NULL
)
2506 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2510 if (limit_pc
> start_pc
+ 200)
2511 limit_pc
= start_pc
+ 200;
2516 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2518 unsigned long inst
, high_word
, low_word
;
2521 /* Fetch the instruction. */
2522 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2524 /* Save some code by pre-extracting some useful fields. */
2525 high_word
= (inst
>> 16) & 0xffff;
2526 low_word
= inst
& 0xffff;
2527 reg
= high_word
& 0x1f;
2529 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2530 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2531 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2533 if (low_word
& 0x8000) /* negative stack adjustment? */
2534 frame_offset
+= 0x10000 - low_word
;
2536 /* Exit loop if a positive stack adjustment is found, which
2537 usually means that the stack cleanup code in the function
2538 epilogue is reached. */
2542 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2544 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2546 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2548 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2549 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2551 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2553 /* Old gcc frame, r30 is virtual frame pointer. */
2554 if ((long) low_word
!= frame_offset
)
2555 frame_addr
= sp
+ low_word
;
2556 else if (frame_reg
== MIPS_SP_REGNUM
)
2558 unsigned alloca_adjust
;
2561 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2562 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2563 if (alloca_adjust
> 0)
2565 /* FP > SP + frame_size. This may be because of
2566 an alloca or somethings similar. Fix sp to
2567 "pre-alloca" value, and try again. */
2568 sp
+= alloca_adjust
;
2569 /* Need to reset the status of all registers. Otherwise,
2570 we will hit a guard that prevents the new address
2571 for each register to be recomputed during the second
2573 reset_saved_regs (this_cache
);
2578 /* move $30,$sp. With different versions of gas this will be either
2579 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2580 Accept any one of these. */
2581 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2583 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2584 if (frame_reg
== MIPS_SP_REGNUM
)
2586 unsigned alloca_adjust
;
2589 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2590 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2591 if (alloca_adjust
> 0)
2593 /* FP > SP + frame_size. This may be because of
2594 an alloca or somethings similar. Fix sp to
2595 "pre-alloca" value, and try again. */
2597 /* Need to reset the status of all registers. Otherwise,
2598 we will hit a guard that prevents the new address
2599 for each register to be recomputed during the second
2601 reset_saved_regs (this_cache
);
2606 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2608 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2610 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2611 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2612 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2613 || high_word
== 0x3c1c /* lui $gp,n */
2614 || high_word
== 0x279c /* addiu $gp,$gp,n */
2615 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2616 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2619 /* These instructions are part of the prologue, but we don't
2620 need to do anything special to handle them. */
2622 /* The instructions below load $at or $t0 with an immediate
2623 value in preparation for a stack adjustment via
2624 subu $sp,$sp,[$at,$t0]. These instructions could also
2625 initialize a local variable, so we accept them only before
2626 a stack adjustment instruction was seen. */
2627 else if (!seen_sp_adjust
2628 && (high_word
== 0x3c01 /* lui $at,n */
2629 || high_word
== 0x3c08 /* lui $t0,n */
2630 || high_word
== 0x3421 /* ori $at,$at,n */
2631 || high_word
== 0x3508 /* ori $t0,$t0,n */
2632 || high_word
== 0x3401 /* ori $at,$zero,n */
2633 || high_word
== 0x3408 /* ori $t0,$zero,n */
2636 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2640 /* This instruction is not an instruction typically found
2641 in a prologue, so we must have reached the end of the
2643 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2644 loop now? Why would we need to continue scanning the function
2646 if (end_prologue_addr
== 0)
2647 end_prologue_addr
= cur_pc
;
2651 if (this_cache
!= NULL
)
2654 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2656 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2657 this assignment below, eventually. But it's still needed
2659 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2660 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2663 /* If we didn't reach the end of the prologue when scanning the function
2664 instructions, then set end_prologue_addr to the address of the
2665 instruction immediately after the last one we scanned. */
2666 /* brobecker/2004-10-10: I don't think this would ever happen, but
2667 we may as well be careful and do our best if we have a null
2668 end_prologue_addr. */
2669 if (end_prologue_addr
== 0)
2670 end_prologue_addr
= cur_pc
;
2672 /* In a frameless function, we might have incorrectly
2673 skipped some load immediate instructions. Undo the skipping
2674 if the load immediate was not followed by a stack adjustment. */
2675 if (load_immediate_bytes
&& !seen_sp_adjust
)
2676 end_prologue_addr
-= load_immediate_bytes
;
2678 return end_prologue_addr
;
2681 static mips_extra_func_info_t
2682 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2683 struct frame_info
*next_frame
,
2684 struct mips_frame_cache
*this_cache
)
2689 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2690 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2691 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2692 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2694 if (pc_is_mips16 (start_pc
))
2695 mips16_scan_prologue (start_pc
, limit_pc
, next_frame
, this_cache
);
2697 mips32_scan_prologue (start_pc
, limit_pc
, next_frame
, this_cache
);
2699 return &temp_proc_desc
;
2702 struct mips_objfile_private
2708 /* Global used to communicate between non_heuristic_proc_desc and
2709 compare_pdr_entries within qsort (). */
2710 static bfd
*the_bfd
;
2713 compare_pdr_entries (const void *a
, const void *b
)
2715 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2716 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2720 else if (lhs
== rhs
)
2726 static mips_extra_func_info_t
2727 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2729 CORE_ADDR startaddr
;
2730 mips_extra_func_info_t proc_desc
;
2731 struct block
*b
= block_for_pc (pc
);
2733 struct obj_section
*sec
;
2734 struct mips_objfile_private
*priv
;
2736 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2738 *addrptr
= startaddr
;
2742 sec
= find_pc_section (pc
);
2745 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2747 /* Search the ".pdr" section generated by GAS. This includes most of
2748 the information normally found in ECOFF PDRs. */
2750 the_bfd
= sec
->objfile
->obfd
;
2752 && (the_bfd
->format
== bfd_object
2753 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2754 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2756 /* Right now GAS only outputs the address as a four-byte sequence.
2757 This means that we should not bother with this method on 64-bit
2758 targets (until that is fixed). */
2760 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2761 sizeof (struct mips_objfile_private
));
2763 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2765 else if (priv
== NULL
)
2769 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2770 sizeof (struct mips_objfile_private
));
2772 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2775 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2776 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2778 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2779 priv
->contents
, 0, priv
->size
);
2781 /* In general, the .pdr section is sorted. However, in the
2782 presence of multiple code sections (and other corner cases)
2783 it can become unsorted. Sort it so that we can use a faster
2785 qsort (priv
->contents
, priv
->size
/ 32, 32,
2786 compare_pdr_entries
);
2791 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2795 if (priv
->size
!= 0)
2802 high
= priv
->size
/ 32;
2804 /* We've found a .pdr section describing this objfile. We want to
2805 find the entry which describes this code address. The .pdr
2806 information is not very descriptive; we have only a function
2807 start address. We have to look for the closest entry, because
2808 the local symbol at the beginning of this function may have
2809 been stripped - so if we ask the symbol table for the start
2810 address we may get a preceding global function. */
2812 /* First, find the last .pdr entry starting at or before PC. */
2815 mid
= (low
+ high
) / 2;
2817 ptr
= priv
->contents
+ mid
* 32;
2818 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2819 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2820 SECT_OFF_TEXT (sec
->objfile
));
2827 while (low
!= high
);
2829 /* Both low and high point one past the PDR of interest. If
2830 both are zero, that means this PC is before any region
2831 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2835 ptr
= priv
->contents
+ (low
- 1) * 32;
2836 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2837 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2838 SECT_OFF_TEXT (sec
->objfile
));
2841 /* We don't have a range, so we have no way to know for sure
2842 whether we're in the correct PDR or a PDR for a preceding
2843 function and the current function was a stripped local
2844 symbol. But if the PDR's PC is at least as great as the
2845 best guess from the symbol table, assume that it does cover
2846 the right area; if a .pdr section is present at all then
2847 nearly every function will have an entry. The biggest exception
2848 will be the dynamic linker stubs; conveniently these are
2849 placed before .text instead of after. */
2851 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2853 struct symbol
*sym
= find_pc_function (pc
);
2858 /* Fill in what we need of the proc_desc. */
2859 proc_desc
= (mips_extra_func_info_t
)
2860 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2861 sizeof (struct mips_extra_func_info
));
2862 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2864 /* Only used for dummy frames. */
2865 PROC_HIGH_ADDR (proc_desc
) = 0;
2867 PROC_FRAME_OFFSET (proc_desc
)
2868 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2869 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2871 PROC_FRAME_ADJUST (proc_desc
) = 0;
2872 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2874 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2876 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2878 PROC_FREG_OFFSET (proc_desc
)
2879 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2880 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2882 proc_desc
->pdr
.isym
= (long) sym
;
2892 if (startaddr
> BLOCK_START (b
))
2894 /* This is the "pathological" case referred to in a comment in
2895 print_frame_info. It might be better to move this check into
2900 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2902 /* If we never found a PDR for this function in symbol reading, then
2903 examine prologues to find the information. */
2906 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2907 if (PROC_FRAME_REG (proc_desc
) == -1)
2916 /* MIPS stack frames are almost impenetrable. When execution stops,
2917 we basically have to look at symbol information for the function
2918 that we stopped in, which tells us *which* register (if any) is
2919 the base of the frame pointer, and what offset from that register
2920 the frame itself is at.
2922 This presents a problem when trying to examine a stack in memory
2923 (that isn't executing at the moment), using the "frame" command. We
2924 don't have a PC, nor do we have any registers except SP.
2926 This routine takes two arguments, SP and PC, and tries to make the
2927 cached frames look as if these two arguments defined a frame on the
2928 cache. This allows the rest of info frame to extract the important
2929 arguments without difficulty. */
2932 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2935 error ("MIPS frame specifications require two arguments: sp and pc");
2937 return create_new_frame (argv
[0], argv
[1]);
2940 /* According to the current ABI, should the type be passed in a
2941 floating-point register (assuming that there is space)? When there
2942 is no FPU, FP are not even considered as possibile candidates for
2943 FP registers and, consequently this returns false - forces FP
2944 arguments into integer registers. */
2947 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2949 return ((typecode
== TYPE_CODE_FLT
2951 && (typecode
== TYPE_CODE_STRUCT
2952 || typecode
== TYPE_CODE_UNION
)
2953 && TYPE_NFIELDS (arg_type
) == 1
2954 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2955 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2958 /* On o32, argument passing in GPRs depends on the alignment of the type being
2959 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2962 mips_type_needs_double_align (struct type
*type
)
2964 enum type_code typecode
= TYPE_CODE (type
);
2966 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2968 else if (typecode
== TYPE_CODE_STRUCT
)
2970 if (TYPE_NFIELDS (type
) < 1)
2972 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2974 else if (typecode
== TYPE_CODE_UNION
)
2978 n
= TYPE_NFIELDS (type
);
2979 for (i
= 0; i
< n
; i
++)
2980 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2987 /* Adjust the address downward (direction of stack growth) so that it
2988 is correctly aligned for a new stack frame. */
2990 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2992 return align_down (addr
, 16);
2995 /* Determine how a return value is stored within the MIPS register
2996 file, given the return type `valtype'. */
2998 struct return_value_word
3007 return_value_location (struct type
*valtype
,
3008 struct return_value_word
*hi
,
3009 struct return_value_word
*lo
)
3011 int len
= TYPE_LENGTH (valtype
);
3012 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3014 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3015 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3016 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3018 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3020 /* We need to break a 64bit float in two 32 bit halves and
3021 spread them across a floating-point register pair. */
3022 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3023 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3024 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3025 && register_size (current_gdbarch
,
3026 mips_regnum (current_gdbarch
)->
3027 fp0
) == 8) ? 4 : 0);
3028 hi
->reg_offset
= lo
->reg_offset
;
3029 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3030 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3036 /* The floating point value fits in a single floating-point
3038 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3039 && register_size (current_gdbarch
,
3040 mips_regnum (current_gdbarch
)->
3042 && len
== 4) ? 4 : 0);
3043 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3054 /* Locate a result possibly spread across two registers. */
3056 lo
->reg
= regnum
+ 0;
3057 hi
->reg
= regnum
+ 1;
3058 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3059 && len
< mips_abi_regsize (current_gdbarch
))
3061 /* "un-left-justify" the value in the low register */
3062 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3067 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3068 && len
< mips_abi_regsize (current_gdbarch
) * 2
3069 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3070 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3072 /* "un-left-justify" the value spread across two registers. */
3073 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3074 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3076 hi
->len
= len
- lo
->len
;
3080 /* Only perform a partial copy of the second register. */
3083 if (len
> mips_abi_regsize (current_gdbarch
))
3085 lo
->len
= mips_abi_regsize (current_gdbarch
);
3086 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3094 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3095 && register_size (current_gdbarch
, regnum
) == 8
3096 && mips_abi_regsize (current_gdbarch
) == 4)
3098 /* Account for the fact that only the least-signficant part
3099 of the register is being used */
3100 lo
->reg_offset
+= 4;
3101 hi
->reg_offset
+= 4;
3104 hi
->buf_offset
= lo
->len
;
3108 /* Should call_function allocate stack space for a struct return? */
3111 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3113 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3114 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3117 /* Should call_function pass struct by reference?
3118 For each architecture, structs are passed either by
3119 value or by reference, depending on their size. */
3122 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3124 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3125 int len
= TYPE_LENGTH (check_typedef (type
));
3126 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3128 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3129 return (len
> mips_abi_regsize (current_gdbarch
));
3135 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3136 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3137 int nargs
, struct value
**args
, CORE_ADDR sp
,
3138 int struct_return
, CORE_ADDR struct_addr
)
3144 int stack_offset
= 0;
3145 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3146 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3148 /* For shared libraries, "t9" needs to point at the function
3150 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3152 /* Set the return address register to point to the entry point of
3153 the program, where a breakpoint lies in wait. */
3154 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3156 /* First ensure that the stack and structure return address (if any)
3157 are properly aligned. The stack has to be at least 64-bit
3158 aligned even on 32-bit machines, because doubles must be 64-bit
3159 aligned. For n32 and n64, stack frames need to be 128-bit
3160 aligned, so we round to this widest known alignment. */
3162 sp
= align_down (sp
, 16);
3163 struct_addr
= align_down (struct_addr
, 16);
3165 /* Now make space on the stack for the args. We allocate more
3166 than necessary for EABI, because the first few arguments are
3167 passed in registers, but that's OK. */
3168 for (argnum
= 0; argnum
< nargs
; argnum
++)
3169 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3170 mips_stack_argsize (gdbarch
));
3171 sp
-= align_up (len
, 16);
3174 fprintf_unfiltered (gdb_stdlog
,
3175 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3176 paddr_nz (sp
), (long) align_up (len
, 16));
3178 /* Initialize the integer and float register pointers. */
3180 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3182 /* The struct_return pointer occupies the first parameter-passing reg. */
3186 fprintf_unfiltered (gdb_stdlog
,
3187 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3188 argreg
, paddr_nz (struct_addr
));
3189 write_register (argreg
++, struct_addr
);
3192 /* Now load as many as possible of the first arguments into
3193 registers, and push the rest onto the stack. Loop thru args
3194 from first to last. */
3195 for (argnum
= 0; argnum
< nargs
; argnum
++)
3198 char valbuf
[MAX_REGISTER_SIZE
];
3199 struct value
*arg
= args
[argnum
];
3200 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3201 int len
= TYPE_LENGTH (arg_type
);
3202 enum type_code typecode
= TYPE_CODE (arg_type
);
3205 fprintf_unfiltered (gdb_stdlog
,
3206 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3207 argnum
+ 1, len
, (int) typecode
);
3209 /* The EABI passes structures that do not fit in a register by
3211 if (len
> mips_abi_regsize (gdbarch
)
3212 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3214 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3215 VALUE_ADDRESS (arg
));
3216 typecode
= TYPE_CODE_PTR
;
3217 len
= mips_abi_regsize (gdbarch
);
3220 fprintf_unfiltered (gdb_stdlog
, " push");
3223 val
= (char *) VALUE_CONTENTS (arg
);
3225 /* 32-bit ABIs always start floating point arguments in an
3226 even-numbered floating point register. Round the FP register
3227 up before the check to see if there are any FP registers
3228 left. Non MIPS_EABI targets also pass the FP in the integer
3229 registers so also round up normal registers. */
3230 if (mips_abi_regsize (gdbarch
) < 8
3231 && fp_register_arg_p (typecode
, arg_type
))
3233 if ((float_argreg
& 1))
3237 /* Floating point arguments passed in registers have to be
3238 treated specially. On 32-bit architectures, doubles
3239 are passed in register pairs; the even register gets
3240 the low word, and the odd register gets the high word.
3241 On non-EABI processors, the first two floating point arguments are
3242 also copied to general registers, because MIPS16 functions
3243 don't use float registers for arguments. This duplication of
3244 arguments in general registers can't hurt non-MIPS16 functions
3245 because those registers are normally skipped. */
3246 /* MIPS_EABI squeezes a struct that contains a single floating
3247 point value into an FP register instead of pushing it onto the
3249 if (fp_register_arg_p (typecode
, arg_type
)
3250 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3252 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3254 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3255 unsigned long regval
;
3257 /* Write the low word of the double to the even register(s). */
3258 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3260 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3261 float_argreg
, phex (regval
, 4));
3262 write_register (float_argreg
++, regval
);
3264 /* Write the high word of the double to the odd register(s). */
3265 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3267 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3268 float_argreg
, phex (regval
, 4));
3269 write_register (float_argreg
++, regval
);
3273 /* This is a floating point value that fits entirely
3274 in a single register. */
3275 /* On 32 bit ABI's the float_argreg is further adjusted
3276 above to ensure that it is even register aligned. */
3277 LONGEST regval
= extract_unsigned_integer (val
, len
);
3279 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3280 float_argreg
, phex (regval
, len
));
3281 write_register (float_argreg
++, regval
);
3286 /* Copy the argument to general registers or the stack in
3287 register-sized pieces. Large arguments are split between
3288 registers and stack. */
3289 /* Note: structs whose size is not a multiple of
3290 mips_abi_regsize() are treated specially: Irix cc passes
3291 them in registers where gcc sometimes puts them on the
3292 stack. For maximum compatibility, we will put them in
3294 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3295 && (len
% mips_abi_regsize (gdbarch
) != 0));
3297 /* Note: Floating-point values that didn't fit into an FP
3298 register are only written to memory. */
3301 /* Remember if the argument was written to the stack. */
3302 int stack_used_p
= 0;
3303 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3304 ? len
: mips_abi_regsize (gdbarch
));
3307 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3310 /* Write this portion of the argument to the stack. */
3311 if (argreg
> MIPS_LAST_ARG_REGNUM
3313 || fp_register_arg_p (typecode
, arg_type
))
3315 /* Should shorter than int integer values be
3316 promoted to int before being stored? */
3317 int longword_offset
= 0;
3320 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3322 if (mips_stack_argsize (gdbarch
) == 8
3323 && (typecode
== TYPE_CODE_INT
3324 || typecode
== TYPE_CODE_PTR
3325 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3326 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3327 else if ((typecode
== TYPE_CODE_STRUCT
3328 || typecode
== TYPE_CODE_UNION
)
3329 && (TYPE_LENGTH (arg_type
)
3330 < mips_stack_argsize (gdbarch
)))
3331 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3336 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3337 paddr_nz (stack_offset
));
3338 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3339 paddr_nz (longword_offset
));
3342 addr
= sp
+ stack_offset
+ longword_offset
;
3347 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3349 for (i
= 0; i
< partial_len
; i
++)
3351 fprintf_unfiltered (gdb_stdlog
, "%02x",
3355 write_memory (addr
, val
, partial_len
);
3358 /* Note!!! This is NOT an else clause. Odd sized
3359 structs may go thru BOTH paths. Floating point
3360 arguments will not. */
3361 /* Write this portion of the argument to a general
3362 purpose register. */
3363 if (argreg
<= MIPS_LAST_ARG_REGNUM
3364 && !fp_register_arg_p (typecode
, arg_type
))
3367 extract_unsigned_integer (val
, partial_len
);
3370 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3373 mips_abi_regsize (gdbarch
)));
3374 write_register (argreg
, regval
);
3381 /* Compute the the offset into the stack at which we
3382 will copy the next parameter.
3384 In the new EABI (and the NABI32), the stack_offset
3385 only needs to be adjusted when it has been used. */
3388 stack_offset
+= align_up (partial_len
,
3389 mips_stack_argsize (gdbarch
));
3393 fprintf_unfiltered (gdb_stdlog
, "\n");
3396 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3398 /* Return adjusted stack pointer. */
3402 /* Given a return value in `regbuf' with a type `valtype', extract and
3403 copy its value into `valbuf'. */
3406 mips_eabi_extract_return_value (struct type
*valtype
,
3407 char regbuf
[], char *valbuf
)
3409 struct return_value_word lo
;
3410 struct return_value_word hi
;
3411 return_value_location (valtype
, &hi
, &lo
);
3413 memcpy (valbuf
+ lo
.buf_offset
,
3414 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3415 lo
.reg_offset
, lo
.len
);
3418 memcpy (valbuf
+ hi
.buf_offset
,
3419 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3420 hi
.reg_offset
, hi
.len
);
3423 /* Given a return value in `valbuf' with a type `valtype', write it's
3424 value into the appropriate register. */
3427 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3429 char raw_buffer
[MAX_REGISTER_SIZE
];
3430 struct return_value_word lo
;
3431 struct return_value_word hi
;
3432 return_value_location (valtype
, &hi
, &lo
);
3434 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3435 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3436 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3437 raw_buffer
, register_size (current_gdbarch
,
3442 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3443 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3444 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3446 register_size (current_gdbarch
,
3451 /* N32/N64 ABI stuff. */
3454 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3455 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3456 int nargs
, struct value
**args
, CORE_ADDR sp
,
3457 int struct_return
, CORE_ADDR struct_addr
)
3463 int stack_offset
= 0;
3464 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3465 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3467 /* For shared libraries, "t9" needs to point at the function
3469 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3471 /* Set the return address register to point to the entry point of
3472 the program, where a breakpoint lies in wait. */
3473 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3475 /* First ensure that the stack and structure return address (if any)
3476 are properly aligned. The stack has to be at least 64-bit
3477 aligned even on 32-bit machines, because doubles must be 64-bit
3478 aligned. For n32 and n64, stack frames need to be 128-bit
3479 aligned, so we round to this widest known alignment. */
3481 sp
= align_down (sp
, 16);
3482 struct_addr
= align_down (struct_addr
, 16);
3484 /* Now make space on the stack for the args. */
3485 for (argnum
= 0; argnum
< nargs
; argnum
++)
3486 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3487 mips_stack_argsize (gdbarch
));
3488 sp
-= align_up (len
, 16);
3491 fprintf_unfiltered (gdb_stdlog
,
3492 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3493 paddr_nz (sp
), (long) align_up (len
, 16));
3495 /* Initialize the integer and float register pointers. */
3497 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3499 /* The struct_return pointer occupies the first parameter-passing reg. */
3503 fprintf_unfiltered (gdb_stdlog
,
3504 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3505 argreg
, paddr_nz (struct_addr
));
3506 write_register (argreg
++, struct_addr
);
3509 /* Now load as many as possible of the first arguments into
3510 registers, and push the rest onto the stack. Loop thru args
3511 from first to last. */
3512 for (argnum
= 0; argnum
< nargs
; argnum
++)
3515 struct value
*arg
= args
[argnum
];
3516 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3517 int len
= TYPE_LENGTH (arg_type
);
3518 enum type_code typecode
= TYPE_CODE (arg_type
);
3521 fprintf_unfiltered (gdb_stdlog
,
3522 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3523 argnum
+ 1, len
, (int) typecode
);
3525 val
= (char *) VALUE_CONTENTS (arg
);
3527 if (fp_register_arg_p (typecode
, arg_type
)
3528 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3530 /* This is a floating point value that fits entirely
3531 in a single register. */
3532 /* On 32 bit ABI's the float_argreg is further adjusted
3533 above to ensure that it is even register aligned. */
3534 LONGEST regval
= extract_unsigned_integer (val
, len
);
3536 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3537 float_argreg
, phex (regval
, len
));
3538 write_register (float_argreg
++, regval
);
3541 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3542 argreg
, phex (regval
, len
));
3543 write_register (argreg
, regval
);
3548 /* Copy the argument to general registers or the stack in
3549 register-sized pieces. Large arguments are split between
3550 registers and stack. */
3551 /* Note: structs whose size is not a multiple of
3552 mips_abi_regsize() are treated specially: Irix cc passes
3553 them in registers where gcc sometimes puts them on the
3554 stack. For maximum compatibility, we will put them in
3556 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3557 && (len
% mips_abi_regsize (gdbarch
) != 0));
3558 /* Note: Floating-point values that didn't fit into an FP
3559 register are only written to memory. */
3562 /* Rememer if the argument was written to the stack. */
3563 int stack_used_p
= 0;
3564 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3565 ? len
: mips_abi_regsize (gdbarch
));
3568 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3571 /* Write this portion of the argument to the stack. */
3572 if (argreg
> MIPS_LAST_ARG_REGNUM
3574 || fp_register_arg_p (typecode
, arg_type
))
3576 /* Should shorter than int integer values be
3577 promoted to int before being stored? */
3578 int longword_offset
= 0;
3581 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3583 if (mips_stack_argsize (gdbarch
) == 8
3584 && (typecode
== TYPE_CODE_INT
3585 || typecode
== TYPE_CODE_PTR
3586 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3587 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3592 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3593 paddr_nz (stack_offset
));
3594 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3595 paddr_nz (longword_offset
));
3598 addr
= sp
+ stack_offset
+ longword_offset
;
3603 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3605 for (i
= 0; i
< partial_len
; i
++)
3607 fprintf_unfiltered (gdb_stdlog
, "%02x",
3611 write_memory (addr
, val
, partial_len
);
3614 /* Note!!! This is NOT an else clause. Odd sized
3615 structs may go thru BOTH paths. Floating point
3616 arguments will not. */
3617 /* Write this portion of the argument to a general
3618 purpose register. */
3619 if (argreg
<= MIPS_LAST_ARG_REGNUM
3620 && !fp_register_arg_p (typecode
, arg_type
))
3623 extract_unsigned_integer (val
, partial_len
);
3625 /* A non-floating-point argument being passed in a
3626 general register. If a struct or union, and if
3627 the remaining length is smaller than the register
3628 size, we have to adjust the register value on
3631 It does not seem to be necessary to do the
3632 same for integral types.
3634 cagney/2001-07-23: gdb/179: Also, GCC, when
3635 outputting LE O32 with sizeof (struct) <
3636 mips_abi_regsize(), generates a left shift as
3637 part of storing the argument in a register a
3638 register (the left shift isn't generated when
3639 sizeof (struct) >= mips_abi_regsize()). Since
3640 it is quite possible that this is GCC
3641 contradicting the LE/O32 ABI, GDB has not been
3642 adjusted to accommodate this. Either someone
3643 needs to demonstrate that the LE/O32 ABI
3644 specifies such a left shift OR this new ABI gets
3645 identified as such and GDB gets tweaked
3648 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3649 && partial_len
< mips_abi_regsize (gdbarch
)
3650 && (typecode
== TYPE_CODE_STRUCT
||
3651 typecode
== TYPE_CODE_UNION
))
3652 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3656 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3659 mips_abi_regsize (gdbarch
)));
3660 write_register (argreg
, regval
);
3667 /* Compute the the offset into the stack at which we
3668 will copy the next parameter.
3670 In N32 (N64?), the stack_offset only needs to be
3671 adjusted when it has been used. */
3674 stack_offset
+= align_up (partial_len
,
3675 mips_stack_argsize (gdbarch
));
3679 fprintf_unfiltered (gdb_stdlog
, "\n");
3682 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3684 /* Return adjusted stack pointer. */
3688 static enum return_value_convention
3689 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3690 struct type
*type
, struct regcache
*regcache
,
3691 void *readbuf
, const void *writebuf
)
3693 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3694 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3695 || TYPE_CODE (type
) == TYPE_CODE_UNION
3696 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3697 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3698 return RETURN_VALUE_STRUCT_CONVENTION
;
3699 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3700 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3702 /* A floating-point value belongs in the least significant part
3705 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3706 mips_xfer_register (regcache
,
3707 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3709 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3710 return RETURN_VALUE_REGISTER_CONVENTION
;
3712 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3713 && TYPE_NFIELDS (type
) <= 2
3714 && TYPE_NFIELDS (type
) >= 1
3715 && ((TYPE_NFIELDS (type
) == 1
3716 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3718 || (TYPE_NFIELDS (type
) == 2
3719 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3721 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3723 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3725 /* A struct that contains one or two floats. Each value is part
3726 in the least significant part of their floating point
3730 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3731 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3733 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3736 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3738 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3739 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3740 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3742 return RETURN_VALUE_REGISTER_CONVENTION
;
3744 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3745 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3747 /* A structure or union. Extract the left justified value,
3748 regardless of the byte order. I.e. DO NOT USE
3752 for (offset
= 0, regnum
= V0_REGNUM
;
3753 offset
< TYPE_LENGTH (type
);
3754 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3756 int xfer
= register_size (current_gdbarch
, regnum
);
3757 if (offset
+ xfer
> TYPE_LENGTH (type
))
3758 xfer
= TYPE_LENGTH (type
) - offset
;
3760 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3761 offset
, xfer
, regnum
);
3762 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3763 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3765 return RETURN_VALUE_REGISTER_CONVENTION
;
3769 /* A scalar extract each part but least-significant-byte
3773 for (offset
= 0, regnum
= V0_REGNUM
;
3774 offset
< TYPE_LENGTH (type
);
3775 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3777 int xfer
= register_size (current_gdbarch
, regnum
);
3778 if (offset
+ xfer
> TYPE_LENGTH (type
))
3779 xfer
= TYPE_LENGTH (type
) - offset
;
3781 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3782 offset
, xfer
, regnum
);
3783 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3784 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3786 return RETURN_VALUE_REGISTER_CONVENTION
;
3790 /* O32 ABI stuff. */
3793 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3794 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3795 int nargs
, struct value
**args
, CORE_ADDR sp
,
3796 int struct_return
, CORE_ADDR struct_addr
)
3802 int stack_offset
= 0;
3803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3804 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3806 /* For shared libraries, "t9" needs to point at the function
3808 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3810 /* Set the return address register to point to the entry point of
3811 the program, where a breakpoint lies in wait. */
3812 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3814 /* First ensure that the stack and structure return address (if any)
3815 are properly aligned. The stack has to be at least 64-bit
3816 aligned even on 32-bit machines, because doubles must be 64-bit
3817 aligned. For n32 and n64, stack frames need to be 128-bit
3818 aligned, so we round to this widest known alignment. */
3820 sp
= align_down (sp
, 16);
3821 struct_addr
= align_down (struct_addr
, 16);
3823 /* Now make space on the stack for the args. */
3824 for (argnum
= 0; argnum
< nargs
; argnum
++)
3825 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3826 mips_stack_argsize (gdbarch
));
3827 sp
-= align_up (len
, 16);
3830 fprintf_unfiltered (gdb_stdlog
,
3831 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3832 paddr_nz (sp
), (long) align_up (len
, 16));
3834 /* Initialize the integer and float register pointers. */
3836 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3838 /* The struct_return pointer occupies the first parameter-passing reg. */
3842 fprintf_unfiltered (gdb_stdlog
,
3843 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3844 argreg
, paddr_nz (struct_addr
));
3845 write_register (argreg
++, struct_addr
);
3846 stack_offset
+= mips_stack_argsize (gdbarch
);
3849 /* Now load as many as possible of the first arguments into
3850 registers, and push the rest onto the stack. Loop thru args
3851 from first to last. */
3852 for (argnum
= 0; argnum
< nargs
; argnum
++)
3855 struct value
*arg
= args
[argnum
];
3856 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3857 int len
= TYPE_LENGTH (arg_type
);
3858 enum type_code typecode
= TYPE_CODE (arg_type
);
3861 fprintf_unfiltered (gdb_stdlog
,
3862 "mips_o32_push_dummy_call: %d len=%d type=%d",
3863 argnum
+ 1, len
, (int) typecode
);
3865 val
= (char *) VALUE_CONTENTS (arg
);
3867 /* 32-bit ABIs always start floating point arguments in an
3868 even-numbered floating point register. Round the FP register
3869 up before the check to see if there are any FP registers
3870 left. O32/O64 targets also pass the FP in the integer
3871 registers so also round up normal registers. */
3872 if (mips_abi_regsize (gdbarch
) < 8
3873 && fp_register_arg_p (typecode
, arg_type
))
3875 if ((float_argreg
& 1))
3879 /* Floating point arguments passed in registers have to be
3880 treated specially. On 32-bit architectures, doubles
3881 are passed in register pairs; the even register gets
3882 the low word, and the odd register gets the high word.
3883 On O32/O64, the first two floating point arguments are
3884 also copied to general registers, because MIPS16 functions
3885 don't use float registers for arguments. This duplication of
3886 arguments in general registers can't hurt non-MIPS16 functions
3887 because those registers are normally skipped. */
3889 if (fp_register_arg_p (typecode
, arg_type
)
3890 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3892 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3894 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3895 unsigned long regval
;
3897 /* Write the low word of the double to the even register(s). */
3898 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3900 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3901 float_argreg
, phex (regval
, 4));
3902 write_register (float_argreg
++, regval
);
3904 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3905 argreg
, phex (regval
, 4));
3906 write_register (argreg
++, regval
);
3908 /* Write the high word of the double to the odd register(s). */
3909 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3911 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3912 float_argreg
, phex (regval
, 4));
3913 write_register (float_argreg
++, regval
);
3916 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3917 argreg
, phex (regval
, 4));
3918 write_register (argreg
++, regval
);
3922 /* This is a floating point value that fits entirely
3923 in a single register. */
3924 /* On 32 bit ABI's the float_argreg is further adjusted
3925 above to ensure that it is even register aligned. */
3926 LONGEST regval
= extract_unsigned_integer (val
, len
);
3928 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3929 float_argreg
, phex (regval
, len
));
3930 write_register (float_argreg
++, regval
);
3931 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3932 registers for each argument. The below is (my
3933 guess) to ensure that the corresponding integer
3934 register has reserved the same space. */
3936 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3937 argreg
, phex (regval
, len
));
3938 write_register (argreg
, regval
);
3939 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3941 /* Reserve space for the FP register. */
3942 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3946 /* Copy the argument to general registers or the stack in
3947 register-sized pieces. Large arguments are split between
3948 registers and stack. */
3949 /* Note: structs whose size is not a multiple of
3950 mips_abi_regsize() are treated specially: Irix cc passes
3951 them in registers where gcc sometimes puts them on the
3952 stack. For maximum compatibility, we will put them in
3954 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3955 && (len
% mips_abi_regsize (gdbarch
) != 0));
3956 /* Structures should be aligned to eight bytes (even arg registers)
3957 on MIPS_ABI_O32, if their first member has double precision. */
3958 if (mips_abi_regsize (gdbarch
) < 8
3959 && mips_type_needs_double_align (arg_type
))
3964 /* Note: Floating-point values that didn't fit into an FP
3965 register are only written to memory. */
3968 /* Remember if the argument was written to the stack. */
3969 int stack_used_p
= 0;
3970 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3971 ? len
: mips_abi_regsize (gdbarch
));
3974 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3977 /* Write this portion of the argument to the stack. */
3978 if (argreg
> MIPS_LAST_ARG_REGNUM
3980 || fp_register_arg_p (typecode
, arg_type
))
3982 /* Should shorter than int integer values be
3983 promoted to int before being stored? */
3984 int longword_offset
= 0;
3987 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3989 if (mips_stack_argsize (gdbarch
) == 8
3990 && (typecode
== TYPE_CODE_INT
3991 || typecode
== TYPE_CODE_PTR
3992 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3993 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3998 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3999 paddr_nz (stack_offset
));
4000 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4001 paddr_nz (longword_offset
));
4004 addr
= sp
+ stack_offset
+ longword_offset
;
4009 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4011 for (i
= 0; i
< partial_len
; i
++)
4013 fprintf_unfiltered (gdb_stdlog
, "%02x",
4017 write_memory (addr
, val
, partial_len
);
4020 /* Note!!! This is NOT an else clause. Odd sized
4021 structs may go thru BOTH paths. Floating point
4022 arguments will not. */
4023 /* Write this portion of the argument to a general
4024 purpose register. */
4025 if (argreg
<= MIPS_LAST_ARG_REGNUM
4026 && !fp_register_arg_p (typecode
, arg_type
))
4028 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4029 /* Value may need to be sign extended, because
4030 mips_isa_regsize() != mips_abi_regsize(). */
4032 /* A non-floating-point argument being passed in a
4033 general register. If a struct or union, and if
4034 the remaining length is smaller than the register
4035 size, we have to adjust the register value on
4038 It does not seem to be necessary to do the
4039 same for integral types.
4041 Also don't do this adjustment on O64 binaries.
4043 cagney/2001-07-23: gdb/179: Also, GCC, when
4044 outputting LE O32 with sizeof (struct) <
4045 mips_abi_regsize(), generates a left shift as
4046 part of storing the argument in a register a
4047 register (the left shift isn't generated when
4048 sizeof (struct) >= mips_abi_regsize()). Since
4049 it is quite possible that this is GCC
4050 contradicting the LE/O32 ABI, GDB has not been
4051 adjusted to accommodate this. Either someone
4052 needs to demonstrate that the LE/O32 ABI
4053 specifies such a left shift OR this new ABI gets
4054 identified as such and GDB gets tweaked
4057 if (mips_abi_regsize (gdbarch
) < 8
4058 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4059 && partial_len
< mips_abi_regsize (gdbarch
)
4060 && (typecode
== TYPE_CODE_STRUCT
||
4061 typecode
== TYPE_CODE_UNION
))
4062 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4066 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4069 mips_abi_regsize (gdbarch
)));
4070 write_register (argreg
, regval
);
4073 /* Prevent subsequent floating point arguments from
4074 being passed in floating point registers. */
4075 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4081 /* Compute the the offset into the stack at which we
4082 will copy the next parameter.
4084 In older ABIs, the caller reserved space for
4085 registers that contained arguments. This was loosely
4086 refered to as their "home". Consequently, space is
4087 always allocated. */
4089 stack_offset
+= align_up (partial_len
,
4090 mips_stack_argsize (gdbarch
));
4094 fprintf_unfiltered (gdb_stdlog
, "\n");
4097 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4099 /* Return adjusted stack pointer. */
4103 static enum return_value_convention
4104 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4105 struct regcache
*regcache
,
4106 void *readbuf
, const void *writebuf
)
4108 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4110 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4111 || TYPE_CODE (type
) == TYPE_CODE_UNION
4112 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4113 return RETURN_VALUE_STRUCT_CONVENTION
;
4114 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4115 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4117 /* A single-precision floating-point value. It fits in the
4118 least significant part of FP0. */
4120 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4121 mips_xfer_register (regcache
,
4122 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4124 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4125 return RETURN_VALUE_REGISTER_CONVENTION
;
4127 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4128 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4130 /* A double-precision floating-point value. The most
4131 significant part goes in FP1, and the least significant in
4134 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4135 switch (TARGET_BYTE_ORDER
)
4137 case BFD_ENDIAN_LITTLE
:
4138 mips_xfer_register (regcache
,
4139 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4140 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4141 mips_xfer_register (regcache
,
4142 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4143 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4145 case BFD_ENDIAN_BIG
:
4146 mips_xfer_register (regcache
,
4147 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4148 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4149 mips_xfer_register (regcache
,
4150 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4151 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4154 internal_error (__FILE__
, __LINE__
, "bad switch");
4156 return RETURN_VALUE_REGISTER_CONVENTION
;
4159 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4160 && TYPE_NFIELDS (type
) <= 2
4161 && TYPE_NFIELDS (type
) >= 1
4162 && ((TYPE_NFIELDS (type
) == 1
4163 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4165 || (TYPE_NFIELDS (type
) == 2
4166 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4168 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4170 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4172 /* A struct that contains one or two floats. Each value is part
4173 in the least significant part of their floating point
4175 bfd_byte reg
[MAX_REGISTER_SIZE
];
4178 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4179 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4181 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4184 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4186 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4187 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4188 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4190 return RETURN_VALUE_REGISTER_CONVENTION
;
4194 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4195 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4197 /* A structure or union. Extract the left justified value,
4198 regardless of the byte order. I.e. DO NOT USE
4202 for (offset
= 0, regnum
= V0_REGNUM
;
4203 offset
< TYPE_LENGTH (type
);
4204 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4206 int xfer
= register_size (current_gdbarch
, regnum
);
4207 if (offset
+ xfer
> TYPE_LENGTH (type
))
4208 xfer
= TYPE_LENGTH (type
) - offset
;
4210 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4211 offset
, xfer
, regnum
);
4212 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4213 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4215 return RETURN_VALUE_REGISTER_CONVENTION
;
4220 /* A scalar extract each part but least-significant-byte
4221 justified. o32 thinks registers are 4 byte, regardless of
4222 the ISA. mips_stack_argsize controls this. */
4225 for (offset
= 0, regnum
= V0_REGNUM
;
4226 offset
< TYPE_LENGTH (type
);
4227 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4229 int xfer
= mips_stack_argsize (gdbarch
);
4230 if (offset
+ xfer
> TYPE_LENGTH (type
))
4231 xfer
= TYPE_LENGTH (type
) - offset
;
4233 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4234 offset
, xfer
, regnum
);
4235 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4236 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4238 return RETURN_VALUE_REGISTER_CONVENTION
;
4242 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4246 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4247 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4249 struct value
**args
, CORE_ADDR sp
,
4250 int struct_return
, CORE_ADDR struct_addr
)
4256 int stack_offset
= 0;
4257 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4258 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4260 /* For shared libraries, "t9" needs to point at the function
4262 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4264 /* Set the return address register to point to the entry point of
4265 the program, where a breakpoint lies in wait. */
4266 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4268 /* First ensure that the stack and structure return address (if any)
4269 are properly aligned. The stack has to be at least 64-bit
4270 aligned even on 32-bit machines, because doubles must be 64-bit
4271 aligned. For n32 and n64, stack frames need to be 128-bit
4272 aligned, so we round to this widest known alignment. */
4274 sp
= align_down (sp
, 16);
4275 struct_addr
= align_down (struct_addr
, 16);
4277 /* Now make space on the stack for the args. */
4278 for (argnum
= 0; argnum
< nargs
; argnum
++)
4279 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4280 mips_stack_argsize (gdbarch
));
4281 sp
-= align_up (len
, 16);
4284 fprintf_unfiltered (gdb_stdlog
,
4285 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4286 paddr_nz (sp
), (long) align_up (len
, 16));
4288 /* Initialize the integer and float register pointers. */
4290 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4292 /* The struct_return pointer occupies the first parameter-passing reg. */
4296 fprintf_unfiltered (gdb_stdlog
,
4297 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4298 argreg
, paddr_nz (struct_addr
));
4299 write_register (argreg
++, struct_addr
);
4300 stack_offset
+= mips_stack_argsize (gdbarch
);
4303 /* Now load as many as possible of the first arguments into
4304 registers, and push the rest onto the stack. Loop thru args
4305 from first to last. */
4306 for (argnum
= 0; argnum
< nargs
; argnum
++)
4309 struct value
*arg
= args
[argnum
];
4310 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4311 int len
= TYPE_LENGTH (arg_type
);
4312 enum type_code typecode
= TYPE_CODE (arg_type
);
4315 fprintf_unfiltered (gdb_stdlog
,
4316 "mips_o64_push_dummy_call: %d len=%d type=%d",
4317 argnum
+ 1, len
, (int) typecode
);
4319 val
= (char *) VALUE_CONTENTS (arg
);
4321 /* 32-bit ABIs always start floating point arguments in an
4322 even-numbered floating point register. Round the FP register
4323 up before the check to see if there are any FP registers
4324 left. O32/O64 targets also pass the FP in the integer
4325 registers so also round up normal registers. */
4326 if (mips_abi_regsize (gdbarch
) < 8
4327 && fp_register_arg_p (typecode
, arg_type
))
4329 if ((float_argreg
& 1))
4333 /* Floating point arguments passed in registers have to be
4334 treated specially. On 32-bit architectures, doubles
4335 are passed in register pairs; the even register gets
4336 the low word, and the odd register gets the high word.
4337 On O32/O64, the first two floating point arguments are
4338 also copied to general registers, because MIPS16 functions
4339 don't use float registers for arguments. This duplication of
4340 arguments in general registers can't hurt non-MIPS16 functions
4341 because those registers are normally skipped. */
4343 if (fp_register_arg_p (typecode
, arg_type
)
4344 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4346 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4348 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4349 unsigned long regval
;
4351 /* Write the low word of the double to the even register(s). */
4352 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4354 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4355 float_argreg
, phex (regval
, 4));
4356 write_register (float_argreg
++, regval
);
4358 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4359 argreg
, phex (regval
, 4));
4360 write_register (argreg
++, regval
);
4362 /* Write the high word of the double to the odd register(s). */
4363 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4365 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4366 float_argreg
, phex (regval
, 4));
4367 write_register (float_argreg
++, regval
);
4370 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4371 argreg
, phex (regval
, 4));
4372 write_register (argreg
++, regval
);
4376 /* This is a floating point value that fits entirely
4377 in a single register. */
4378 /* On 32 bit ABI's the float_argreg is further adjusted
4379 above to ensure that it is even register aligned. */
4380 LONGEST regval
= extract_unsigned_integer (val
, len
);
4382 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4383 float_argreg
, phex (regval
, len
));
4384 write_register (float_argreg
++, regval
);
4385 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4386 registers for each argument. The below is (my
4387 guess) to ensure that the corresponding integer
4388 register has reserved the same space. */
4390 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4391 argreg
, phex (regval
, len
));
4392 write_register (argreg
, regval
);
4393 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4395 /* Reserve space for the FP register. */
4396 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4400 /* Copy the argument to general registers or the stack in
4401 register-sized pieces. Large arguments are split between
4402 registers and stack. */
4403 /* Note: structs whose size is not a multiple of
4404 mips_abi_regsize() are treated specially: Irix cc passes
4405 them in registers where gcc sometimes puts them on the
4406 stack. For maximum compatibility, we will put them in
4408 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4409 && (len
% mips_abi_regsize (gdbarch
) != 0));
4410 /* Structures should be aligned to eight bytes (even arg registers)
4411 on MIPS_ABI_O32, if their first member has double precision. */
4412 if (mips_abi_regsize (gdbarch
) < 8
4413 && mips_type_needs_double_align (arg_type
))
4418 /* Note: Floating-point values that didn't fit into an FP
4419 register are only written to memory. */
4422 /* Remember if the argument was written to the stack. */
4423 int stack_used_p
= 0;
4424 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4425 ? len
: mips_abi_regsize (gdbarch
));
4428 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4431 /* Write this portion of the argument to the stack. */
4432 if (argreg
> MIPS_LAST_ARG_REGNUM
4434 || fp_register_arg_p (typecode
, arg_type
))
4436 /* Should shorter than int integer values be
4437 promoted to int before being stored? */
4438 int longword_offset
= 0;
4441 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4443 if (mips_stack_argsize (gdbarch
) == 8
4444 && (typecode
== TYPE_CODE_INT
4445 || typecode
== TYPE_CODE_PTR
4446 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4447 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4452 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4453 paddr_nz (stack_offset
));
4454 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4455 paddr_nz (longword_offset
));
4458 addr
= sp
+ stack_offset
+ longword_offset
;
4463 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4465 for (i
= 0; i
< partial_len
; i
++)
4467 fprintf_unfiltered (gdb_stdlog
, "%02x",
4471 write_memory (addr
, val
, partial_len
);
4474 /* Note!!! This is NOT an else clause. Odd sized
4475 structs may go thru BOTH paths. Floating point
4476 arguments will not. */
4477 /* Write this portion of the argument to a general
4478 purpose register. */
4479 if (argreg
<= MIPS_LAST_ARG_REGNUM
4480 && !fp_register_arg_p (typecode
, arg_type
))
4482 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4483 /* Value may need to be sign extended, because
4484 mips_isa_regsize() != mips_abi_regsize(). */
4486 /* A non-floating-point argument being passed in a
4487 general register. If a struct or union, and if
4488 the remaining length is smaller than the register
4489 size, we have to adjust the register value on
4492 It does not seem to be necessary to do the
4493 same for integral types.
4495 Also don't do this adjustment on O64 binaries.
4497 cagney/2001-07-23: gdb/179: Also, GCC, when
4498 outputting LE O32 with sizeof (struct) <
4499 mips_abi_regsize(), generates a left shift as
4500 part of storing the argument in a register a
4501 register (the left shift isn't generated when
4502 sizeof (struct) >= mips_abi_regsize()). Since
4503 it is quite possible that this is GCC
4504 contradicting the LE/O32 ABI, GDB has not been
4505 adjusted to accommodate this. Either someone
4506 needs to demonstrate that the LE/O32 ABI
4507 specifies such a left shift OR this new ABI gets
4508 identified as such and GDB gets tweaked
4511 if (mips_abi_regsize (gdbarch
) < 8
4512 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4513 && partial_len
< mips_abi_regsize (gdbarch
)
4514 && (typecode
== TYPE_CODE_STRUCT
||
4515 typecode
== TYPE_CODE_UNION
))
4516 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4520 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4523 mips_abi_regsize (gdbarch
)));
4524 write_register (argreg
, regval
);
4527 /* Prevent subsequent floating point arguments from
4528 being passed in floating point registers. */
4529 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4535 /* Compute the the offset into the stack at which we
4536 will copy the next parameter.
4538 In older ABIs, the caller reserved space for
4539 registers that contained arguments. This was loosely
4540 refered to as their "home". Consequently, space is
4541 always allocated. */
4543 stack_offset
+= align_up (partial_len
,
4544 mips_stack_argsize (gdbarch
));
4548 fprintf_unfiltered (gdb_stdlog
, "\n");
4551 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4553 /* Return adjusted stack pointer. */
4558 mips_o64_extract_return_value (struct type
*valtype
,
4559 char regbuf
[], char *valbuf
)
4561 struct return_value_word lo
;
4562 struct return_value_word hi
;
4563 return_value_location (valtype
, &hi
, &lo
);
4565 memcpy (valbuf
+ lo
.buf_offset
,
4566 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4567 lo
.reg_offset
, lo
.len
);
4570 memcpy (valbuf
+ hi
.buf_offset
,
4571 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4572 hi
.reg_offset
, hi
.len
);
4576 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4578 char raw_buffer
[MAX_REGISTER_SIZE
];
4579 struct return_value_word lo
;
4580 struct return_value_word hi
;
4581 return_value_location (valtype
, &hi
, &lo
);
4583 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4584 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4585 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4586 raw_buffer
, register_size (current_gdbarch
,
4591 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4592 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4593 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4595 register_size (current_gdbarch
,
4600 /* Floating point register management.
4602 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4603 64bit operations, these early MIPS cpus treat fp register pairs
4604 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4605 registers and offer a compatibility mode that emulates the MIPS2 fp
4606 model. When operating in MIPS2 fp compat mode, later cpu's split
4607 double precision floats into two 32-bit chunks and store them in
4608 consecutive fp regs. To display 64-bit floats stored in this
4609 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4610 Throw in user-configurable endianness and you have a real mess.
4612 The way this works is:
4613 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4614 double-precision value will be split across two logical registers.
4615 The lower-numbered logical register will hold the low-order bits,
4616 regardless of the processor's endianness.
4617 - If we are on a 64-bit processor, and we are looking for a
4618 single-precision value, it will be in the low ordered bits
4619 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4620 save slot in memory.
4621 - If we are in 64-bit mode, everything is straightforward.
4623 Note that this code only deals with "live" registers at the top of the
4624 stack. We will attempt to deal with saved registers later, when
4625 the raw/cooked register interface is in place. (We need a general
4626 interface that can deal with dynamic saved register sizes -- fp
4627 regs could be 32 bits wide in one frame and 64 on the frame above
4630 static struct type
*
4631 mips_float_register_type (void)
4633 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4634 return builtin_type_ieee_single_big
;
4636 return builtin_type_ieee_single_little
;
4639 static struct type
*
4640 mips_double_register_type (void)
4642 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4643 return builtin_type_ieee_double_big
;
4645 return builtin_type_ieee_double_little
;
4648 /* Copy a 32-bit single-precision value from the current frame
4649 into rare_buffer. */
4652 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4655 int raw_size
= register_size (current_gdbarch
, regno
);
4656 char *raw_buffer
= alloca (raw_size
);
4658 if (!frame_register_read (frame
, regno
, raw_buffer
))
4659 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4662 /* We have a 64-bit value for this register. Find the low-order
4666 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4671 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4675 memcpy (rare_buffer
, raw_buffer
, 4);
4679 /* Copy a 64-bit double-precision value from the current frame into
4680 rare_buffer. This may include getting half of it from the next
4684 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4687 int raw_size
= register_size (current_gdbarch
, regno
);
4689 if (raw_size
== 8 && !mips2_fp_compat ())
4691 /* We have a 64-bit value for this register, and we should use
4693 if (!frame_register_read (frame
, regno
, rare_buffer
))
4694 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4698 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4699 internal_error (__FILE__
, __LINE__
,
4700 "mips_read_fp_register_double: bad access to "
4701 "odd-numbered FP register");
4703 /* mips_read_fp_register_single will find the correct 32 bits from
4705 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4707 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4708 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4712 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4713 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4719 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4721 { /* do values for FP (float) regs */
4723 double doub
, flt1
; /* doubles extracted from raw hex data */
4727 (char *) alloca (2 *
4728 register_size (current_gdbarch
,
4729 mips_regnum (current_gdbarch
)->fp0
));
4731 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4732 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4735 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4737 /* 4-byte registers: Print hex and floating. Also print even
4738 numbered registers as doubles. */
4739 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4740 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4742 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4745 fprintf_filtered (file
, " flt: ");
4747 fprintf_filtered (file
, " <invalid float> ");
4749 fprintf_filtered (file
, "%-17.9g", flt1
);
4751 if (regnum
% 2 == 0)
4753 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4754 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4757 fprintf_filtered (file
, " dbl: ");
4759 fprintf_filtered (file
, "<invalid double>");
4761 fprintf_filtered (file
, "%-24.17g", doub
);
4766 /* Eight byte registers: print each one as hex, float and double. */
4767 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4768 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4770 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4771 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4774 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4777 fprintf_filtered (file
, " flt: ");
4779 fprintf_filtered (file
, "<invalid float>");
4781 fprintf_filtered (file
, "%-17.9g", flt1
);
4783 fprintf_filtered (file
, " dbl: ");
4785 fprintf_filtered (file
, "<invalid double>");
4787 fprintf_filtered (file
, "%-24.17g", doub
);
4792 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4793 int regnum
, int all
)
4795 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4796 char raw_buffer
[MAX_REGISTER_SIZE
];
4799 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4801 mips_print_fp_register (file
, frame
, regnum
);
4805 /* Get the data in raw format. */
4806 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4808 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4812 fputs_filtered (REGISTER_NAME (regnum
), file
);
4814 /* The problem with printing numeric register names (r26, etc.) is that
4815 the user can't use them on input. Probably the best solution is to
4816 fix it so that either the numeric or the funky (a2, etc.) names
4817 are accepted on input. */
4818 if (regnum
< MIPS_NUMREGS
)
4819 fprintf_filtered (file
, "(r%d): ", regnum
);
4821 fprintf_filtered (file
, ": ");
4823 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4825 register_size (current_gdbarch
,
4826 regnum
) - register_size (current_gdbarch
, regnum
);
4830 print_scalar_formatted (raw_buffer
+ offset
,
4831 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4835 /* Replacement for generic do_registers_info.
4836 Print regs in pretty columns. */
4839 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4842 fprintf_filtered (file
, " ");
4843 mips_print_fp_register (file
, frame
, regnum
);
4844 fprintf_filtered (file
, "\n");
4849 /* Print a row's worth of GP (int) registers, with name labels above */
4852 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4855 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4856 /* do values for GP (int) regs */
4857 char raw_buffer
[MAX_REGISTER_SIZE
];
4858 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4862 /* For GP registers, we print a separate row of names above the vals */
4863 fprintf_filtered (file
, " ");
4864 for (col
= 0, regnum
= start_regnum
;
4865 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4867 if (*REGISTER_NAME (regnum
) == '\0')
4868 continue; /* unused register */
4869 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4871 break; /* end the row: reached FP register */
4872 fprintf_filtered (file
,
4873 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4874 REGISTER_NAME (regnum
));
4877 /* print the R0 to R31 names */
4878 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4879 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4881 fprintf_filtered (file
, "\n ");
4883 /* now print the values in hex, 4 or 8 to the row */
4884 for (col
= 0, regnum
= start_regnum
;
4885 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4887 if (*REGISTER_NAME (regnum
) == '\0')
4888 continue; /* unused register */
4889 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4891 break; /* end row: reached FP register */
4892 /* OK: get the data in raw format. */
4893 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4894 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4895 /* pad small registers */
4897 byte
< (mips_abi_regsize (current_gdbarch
)
4898 - register_size (current_gdbarch
, regnum
)); byte
++)
4899 printf_filtered (" ");
4900 /* Now print the register value in hex, endian order. */
4901 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4903 register_size (current_gdbarch
,
4904 regnum
) - register_size (current_gdbarch
, regnum
);
4905 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4906 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4908 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4910 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4911 fprintf_filtered (file
, " ");
4914 if (col
> 0) /* ie. if we actually printed anything... */
4915 fprintf_filtered (file
, "\n");
4920 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4923 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4924 struct frame_info
*frame
, int regnum
, int all
)
4926 if (regnum
!= -1) /* do one specified register */
4928 gdb_assert (regnum
>= NUM_REGS
);
4929 if (*(REGISTER_NAME (regnum
)) == '\0')
4930 error ("Not a valid register for the current processor type");
4932 mips_print_register (file
, frame
, regnum
, 0);
4933 fprintf_filtered (file
, "\n");
4936 /* do all (or most) registers */
4939 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4941 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4944 if (all
) /* true for "INFO ALL-REGISTERS" command */
4945 regnum
= print_fp_register_row (file
, frame
, regnum
);
4947 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4950 regnum
= print_gp_register_row (file
, frame
, regnum
);
4955 /* Is this a branch with a delay slot? */
4957 static int is_delayed (unsigned long);
4960 is_delayed (unsigned long insn
)
4963 for (i
= 0; i
< NUMOPCODES
; ++i
)
4964 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4965 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4967 return (i
< NUMOPCODES
4968 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4969 | INSN_COND_BRANCH_DELAY
4970 | INSN_COND_BRANCH_LIKELY
)));
4974 mips_step_skips_delay (CORE_ADDR pc
)
4976 char buf
[MIPS_INSTLEN
];
4978 /* There is no branch delay slot on MIPS16. */
4979 if (pc_is_mips16 (pc
))
4982 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4983 /* If error reading memory, guess that it is not a delayed branch. */
4985 return is_delayed ((unsigned long)
4986 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4989 /* To skip prologues, I use this predicate. Returns either PC itself
4990 if the code at PC does not look like a function prologue; otherwise
4991 returns an address that (if we're lucky) follows the prologue. If
4992 LENIENT, then we must skip everything which is involved in setting
4993 up the frame (it's OK to skip more, just so long as we don't skip
4994 anything which might clobber the registers which are being saved.
4995 We must skip more in the case where part of the prologue is in the
4996 delay slot of a non-prologue instruction). */
4999 mips_skip_prologue (CORE_ADDR pc
)
5001 /* See if we can determine the end of the prologue via the symbol table.
5002 If so, then return either PC, or the PC after the prologue, whichever
5005 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
5008 if (post_prologue_pc
!= 0)
5009 return max (pc
, post_prologue_pc
);
5011 /* Can't determine prologue from the symbol table, need to examine
5014 /* Find an upper limit on the function prologue using the debug
5015 information. If the debug information could not be used to provide
5016 that bound, then use an arbitrary large number as the upper bound. */
5017 limit_pc
= skip_prologue_using_sal (pc
);
5019 limit_pc
= pc
+ 100; /* Magic. */
5021 if (pc_is_mips16 (pc
))
5022 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
5024 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
5027 /* Root of all "set mips "/"show mips " commands. This will eventually be
5028 used for all MIPS-specific commands. */
5031 show_mips_command (char *args
, int from_tty
)
5033 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5037 set_mips_command (char *args
, int from_tty
)
5040 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5041 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5044 /* Commands to show/set the MIPS FPU type. */
5047 show_mipsfpu_command (char *args
, int from_tty
)
5050 switch (MIPS_FPU_TYPE
)
5052 case MIPS_FPU_SINGLE
:
5053 fpu
= "single-precision";
5055 case MIPS_FPU_DOUBLE
:
5056 fpu
= "double-precision";
5059 fpu
= "absent (none)";
5062 internal_error (__FILE__
, __LINE__
, "bad switch");
5064 if (mips_fpu_type_auto
)
5066 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5070 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5075 set_mipsfpu_command (char *args
, int from_tty
)
5078 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5079 show_mipsfpu_command (args
, from_tty
);
5083 set_mipsfpu_single_command (char *args
, int from_tty
)
5085 struct gdbarch_info info
;
5086 gdbarch_info_init (&info
);
5087 mips_fpu_type
= MIPS_FPU_SINGLE
;
5088 mips_fpu_type_auto
= 0;
5089 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5090 instead of relying on globals. Doing that would let generic code
5091 handle the search for this specific architecture. */
5092 if (!gdbarch_update_p (info
))
5093 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5097 set_mipsfpu_double_command (char *args
, int from_tty
)
5099 struct gdbarch_info info
;
5100 gdbarch_info_init (&info
);
5101 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5102 mips_fpu_type_auto
= 0;
5103 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5104 instead of relying on globals. Doing that would let generic code
5105 handle the search for this specific architecture. */
5106 if (!gdbarch_update_p (info
))
5107 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5111 set_mipsfpu_none_command (char *args
, int from_tty
)
5113 struct gdbarch_info info
;
5114 gdbarch_info_init (&info
);
5115 mips_fpu_type
= MIPS_FPU_NONE
;
5116 mips_fpu_type_auto
= 0;
5117 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5118 instead of relying on globals. Doing that would let generic code
5119 handle the search for this specific architecture. */
5120 if (!gdbarch_update_p (info
))
5121 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5125 set_mipsfpu_auto_command (char *args
, int from_tty
)
5127 mips_fpu_type_auto
= 1;
5130 /* Attempt to identify the particular processor model by reading the
5131 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5132 the relevant processor still exists (it dates back to '94) and
5133 secondly this is not the way to do this. The processor type should
5134 be set by forcing an architecture change. */
5137 deprecated_mips_set_processor_regs_hack (void)
5139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5142 prid
= read_register (PRID_REGNUM
);
5144 if ((prid
& ~0xf) == 0x700)
5145 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5148 /* Just like reinit_frame_cache, but with the right arguments to be
5149 callable as an sfunc. */
5152 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5153 struct cmd_list_element
*c
)
5155 reinit_frame_cache ();
5159 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5162 mips_extra_func_info_t proc_desc
;
5164 /* Search for the function containing this address. Set the low bit
5165 of the address when searching, in case we were given an even address
5166 that is the start of a 16-bit function. If we didn't do this,
5167 the search would fail because the symbol table says the function
5168 starts at an odd address, i.e. 1 byte past the given address. */
5169 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5170 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5172 /* Make an attempt to determine if this is a 16-bit function. If
5173 the procedure descriptor exists and the address therein is odd,
5174 it's definitely a 16-bit function. Otherwise, we have to just
5175 guess that if the address passed in is odd, it's 16-bits. */
5176 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5177 disassembler needs to be able to locally determine the ISA, and
5178 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5182 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5183 info
->mach
= bfd_mach_mips16
;
5187 if (pc_is_mips16 (memaddr
))
5188 info
->mach
= bfd_mach_mips16
;
5191 /* Round down the instruction address to the appropriate boundary. */
5192 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5194 /* Set the disassembler options. */
5195 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5197 /* Set up the disassembler info, so that we get the right
5198 register names from libopcodes. */
5199 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5200 info
->disassembler_options
= "gpr-names=n32";
5202 info
->disassembler_options
= "gpr-names=64";
5203 info
->flavour
= bfd_target_elf_flavour
;
5206 /* This string is not recognized explicitly by the disassembler,
5207 but it tells the disassembler to not try to guess the ABI from
5208 the bfd elf headers, such that, if the user overrides the ABI
5209 of a program linked as NewABI, the disassembly will follow the
5210 register naming conventions specified by the user. */
5211 info
->disassembler_options
= "gpr-names=32";
5213 /* Call the appropriate disassembler based on the target endian-ness. */
5214 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5215 return print_insn_big_mips (memaddr
, info
);
5217 return print_insn_little_mips (memaddr
, info
);
5220 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5221 counter value to determine whether a 16- or 32-bit breakpoint should be
5222 used. It returns a pointer to a string of bytes that encode a breakpoint
5223 instruction, stores the length of the string to *lenptr, and adjusts pc
5224 (if necessary) to point to the actual memory location where the
5225 breakpoint should be inserted. */
5227 static const unsigned char *
5228 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5230 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5232 if (pc_is_mips16 (*pcptr
))
5234 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5235 *pcptr
= unmake_mips16_addr (*pcptr
);
5236 *lenptr
= sizeof (mips16_big_breakpoint
);
5237 return mips16_big_breakpoint
;
5241 /* The IDT board uses an unusual breakpoint value, and
5242 sometimes gets confused when it sees the usual MIPS
5243 breakpoint instruction. */
5244 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5245 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5246 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5248 *lenptr
= sizeof (big_breakpoint
);
5250 if (strcmp (target_shortname
, "mips") == 0)
5251 return idt_big_breakpoint
;
5252 else if (strcmp (target_shortname
, "ddb") == 0
5253 || strcmp (target_shortname
, "pmon") == 0
5254 || strcmp (target_shortname
, "lsi") == 0)
5255 return pmon_big_breakpoint
;
5257 return big_breakpoint
;
5262 if (pc_is_mips16 (*pcptr
))
5264 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5265 *pcptr
= unmake_mips16_addr (*pcptr
);
5266 *lenptr
= sizeof (mips16_little_breakpoint
);
5267 return mips16_little_breakpoint
;
5271 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5272 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5273 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5275 *lenptr
= sizeof (little_breakpoint
);
5277 if (strcmp (target_shortname
, "mips") == 0)
5278 return idt_little_breakpoint
;
5279 else if (strcmp (target_shortname
, "ddb") == 0
5280 || strcmp (target_shortname
, "pmon") == 0
5281 || strcmp (target_shortname
, "lsi") == 0)
5282 return pmon_little_breakpoint
;
5284 return little_breakpoint
;
5289 /* If PC is in a mips16 call or return stub, return the address of the target
5290 PC, which is either the callee or the caller. There are several
5291 cases which must be handled:
5293 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5294 target PC is in $31 ($ra).
5295 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5296 and the target PC is in $2.
5297 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5298 before the jal instruction, this is effectively a call stub
5299 and the the target PC is in $2. Otherwise this is effectively
5300 a return stub and the target PC is in $18.
5302 See the source code for the stubs in gcc/config/mips/mips16.S for
5305 This function implements the SKIP_TRAMPOLINE_CODE macro.
5309 mips_skip_stub (CORE_ADDR pc
)
5312 CORE_ADDR start_addr
;
5314 /* Find the starting address and name of the function containing the PC. */
5315 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5318 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5319 target PC is in $31 ($ra). */
5320 if (strcmp (name
, "__mips16_ret_sf") == 0
5321 || strcmp (name
, "__mips16_ret_df") == 0)
5322 return read_signed_register (RA_REGNUM
);
5324 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5326 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5327 and the target PC is in $2. */
5328 if (name
[19] >= '0' && name
[19] <= '9')
5329 return read_signed_register (2);
5331 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5332 before the jal instruction, this is effectively a call stub
5333 and the the target PC is in $2. Otherwise this is effectively
5334 a return stub and the target PC is in $18. */
5335 else if (name
[19] == 's' || name
[19] == 'd')
5337 if (pc
== start_addr
)
5339 /* Check if the target of the stub is a compiler-generated
5340 stub. Such a stub for a function bar might have a name
5341 like __fn_stub_bar, and might look like this:
5346 la $1,bar (becomes a lui/addiu pair)
5348 So scan down to the lui/addi and extract the target
5349 address from those two instructions. */
5351 CORE_ADDR target_pc
= read_signed_register (2);
5355 /* See if the name of the target function is __fn_stub_*. */
5356 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5359 if (strncmp (name
, "__fn_stub_", 10) != 0
5360 && strcmp (name
, "etext") != 0
5361 && strcmp (name
, "_etext") != 0)
5364 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5365 The limit on the search is arbitrarily set to 20
5366 instructions. FIXME. */
5367 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5369 inst
= mips_fetch_instruction (target_pc
);
5370 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5371 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5372 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5373 return pc
| (inst
& 0xffff); /* low word */
5376 /* Couldn't find the lui/addui pair, so return stub address. */
5380 /* This is the 'return' part of a call stub. The return
5381 address is in $r18. */
5382 return read_signed_register (18);
5385 return 0; /* not a stub */
5389 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5390 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5393 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5395 CORE_ADDR start_addr
;
5397 /* Find the starting address of the function containing the PC. If the
5398 caller didn't give us a name, look it up at the same time. */
5399 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5403 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5405 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5406 if (name
[19] >= '0' && name
[19] <= '9')
5408 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5409 before the jal instruction, this is effectively a call stub. */
5410 else if (name
[19] == 's' || name
[19] == 'd')
5411 return pc
== start_addr
;
5414 return 0; /* not a stub */
5418 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5419 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5422 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5424 CORE_ADDR start_addr
;
5426 /* Find the starting address of the function containing the PC. */
5427 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5430 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5431 if (strcmp (name
, "__mips16_ret_sf") == 0
5432 || strcmp (name
, "__mips16_ret_df") == 0)
5435 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5436 i.e. after the jal instruction, this is effectively a return stub. */
5437 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5438 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5441 return 0; /* not a stub */
5445 /* Return non-zero if the PC is in a library helper function that
5446 should be ignored. This implements the
5447 DEPRECATED_IGNORE_HELPER_CALL macro. */
5450 mips_ignore_helper (CORE_ADDR pc
)
5454 /* Find the starting address and name of the function containing the PC. */
5455 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5458 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5459 that we want to ignore. */
5460 return (strcmp (name
, "__mips16_ret_sf") == 0
5461 || strcmp (name
, "__mips16_ret_df") == 0);
5465 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5466 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5469 mips_stab_reg_to_regnum (int num
)
5472 if (num
>= 0 && num
< 32)
5474 else if (num
>= 38 && num
< 70)
5475 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5477 regnum
= mips_regnum (current_gdbarch
)->hi
;
5479 regnum
= mips_regnum (current_gdbarch
)->lo
;
5481 /* This will hopefully (eventually) provoke a warning. Should
5482 we be calling complaint() here? */
5483 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5484 return NUM_REGS
+ regnum
;
5488 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5489 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5492 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5495 if (num
>= 0 && num
< 32)
5497 else if (num
>= 32 && num
< 64)
5498 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5500 regnum
= mips_regnum (current_gdbarch
)->hi
;
5502 regnum
= mips_regnum (current_gdbarch
)->lo
;
5504 /* This will hopefully (eventually) provoke a warning. Should we
5505 be calling complaint() here? */
5506 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5507 return NUM_REGS
+ regnum
;
5511 mips_register_sim_regno (int regnum
)
5513 /* Only makes sense to supply raw registers. */
5514 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5515 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5516 decide if it is valid. Should instead define a standard sim/gdb
5517 register numbering scheme. */
5518 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5519 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5522 return LEGACY_SIM_REGNO_IGNORE
;
5526 /* Convert an integer into an address. By first converting the value
5527 into a pointer and then extracting it signed, the address is
5528 guarenteed to be correctly sign extended. */
5531 mips_integer_to_address (struct type
*type
, void *buf
)
5533 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5534 LONGEST val
= unpack_long (type
, buf
);
5535 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5536 return extract_signed_integer (tmp
,
5537 TYPE_LENGTH (builtin_type_void_data_ptr
));
5541 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5543 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5544 const char *name
= bfd_get_section_name (abfd
, sect
);
5546 if (*abip
!= MIPS_ABI_UNKNOWN
)
5549 if (strncmp (name
, ".mdebug.", 8) != 0)
5552 if (strcmp (name
, ".mdebug.abi32") == 0)
5553 *abip
= MIPS_ABI_O32
;
5554 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5555 *abip
= MIPS_ABI_N32
;
5556 else if (strcmp (name
, ".mdebug.abi64") == 0)
5557 *abip
= MIPS_ABI_N64
;
5558 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5559 *abip
= MIPS_ABI_O64
;
5560 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5561 *abip
= MIPS_ABI_EABI32
;
5562 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5563 *abip
= MIPS_ABI_EABI64
;
5565 warning ("unsupported ABI %s.", name
+ 8);
5568 static enum mips_abi
5569 global_mips_abi (void)
5573 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5574 if (mips_abi_strings
[i
] == mips_abi_string
)
5575 return (enum mips_abi
) i
;
5577 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5580 static struct gdbarch
*
5581 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5583 struct gdbarch
*gdbarch
;
5584 struct gdbarch_tdep
*tdep
;
5586 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5588 enum mips_fpu_type fpu_type
;
5590 /* First of all, extract the elf_flags, if available. */
5591 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5592 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5593 else if (arches
!= NULL
)
5594 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5598 fprintf_unfiltered (gdb_stdlog
,
5599 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5601 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5602 switch ((elf_flags
& EF_MIPS_ABI
))
5604 case E_MIPS_ABI_O32
:
5605 found_abi
= MIPS_ABI_O32
;
5607 case E_MIPS_ABI_O64
:
5608 found_abi
= MIPS_ABI_O64
;
5610 case E_MIPS_ABI_EABI32
:
5611 found_abi
= MIPS_ABI_EABI32
;
5613 case E_MIPS_ABI_EABI64
:
5614 found_abi
= MIPS_ABI_EABI64
;
5617 if ((elf_flags
& EF_MIPS_ABI2
))
5618 found_abi
= MIPS_ABI_N32
;
5620 found_abi
= MIPS_ABI_UNKNOWN
;
5624 /* GCC creates a pseudo-section whose name describes the ABI. */
5625 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5626 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5628 /* If we have no useful BFD information, use the ABI from the last
5629 MIPS architecture (if there is one). */
5630 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5631 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5633 /* Try the architecture for any hint of the correct ABI. */
5634 if (found_abi
== MIPS_ABI_UNKNOWN
5635 && info
.bfd_arch_info
!= NULL
5636 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5638 switch (info
.bfd_arch_info
->mach
)
5640 case bfd_mach_mips3900
:
5641 found_abi
= MIPS_ABI_EABI32
;
5643 case bfd_mach_mips4100
:
5644 case bfd_mach_mips5000
:
5645 found_abi
= MIPS_ABI_EABI64
;
5647 case bfd_mach_mips8000
:
5648 case bfd_mach_mips10000
:
5649 /* On Irix, ELF64 executables use the N64 ABI. The
5650 pseudo-sections which describe the ABI aren't present
5651 on IRIX. (Even for executables created by gcc.) */
5652 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5653 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5654 found_abi
= MIPS_ABI_N64
;
5656 found_abi
= MIPS_ABI_N32
;
5662 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5665 /* What has the user specified from the command line? */
5666 wanted_abi
= global_mips_abi ();
5668 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5671 /* Now that we have found what the ABI for this binary would be,
5672 check whether the user is overriding it. */
5673 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5674 mips_abi
= wanted_abi
;
5675 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5676 mips_abi
= found_abi
;
5678 mips_abi
= MIPS_ABI_O32
;
5680 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5683 /* Also used when doing an architecture lookup. */
5685 fprintf_unfiltered (gdb_stdlog
,
5686 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5687 mips64_transfers_32bit_regs_p
);
5689 /* Determine the MIPS FPU type. */
5690 if (!mips_fpu_type_auto
)
5691 fpu_type
= mips_fpu_type
;
5692 else if (info
.bfd_arch_info
!= NULL
5693 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5694 switch (info
.bfd_arch_info
->mach
)
5696 case bfd_mach_mips3900
:
5697 case bfd_mach_mips4100
:
5698 case bfd_mach_mips4111
:
5699 case bfd_mach_mips4120
:
5700 fpu_type
= MIPS_FPU_NONE
;
5702 case bfd_mach_mips4650
:
5703 fpu_type
= MIPS_FPU_SINGLE
;
5706 fpu_type
= MIPS_FPU_DOUBLE
;
5709 else if (arches
!= NULL
)
5710 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5712 fpu_type
= MIPS_FPU_DOUBLE
;
5714 fprintf_unfiltered (gdb_stdlog
,
5715 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5717 /* try to find a pre-existing architecture */
5718 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5720 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5722 /* MIPS needs to be pedantic about which ABI the object is
5724 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5726 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5728 /* Need to be pedantic about which register virtual size is
5730 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5731 != mips64_transfers_32bit_regs_p
)
5733 /* Be pedantic about which FPU is selected. */
5734 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5736 return arches
->gdbarch
;
5739 /* Need a new architecture. Fill in a target specific vector. */
5740 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5741 gdbarch
= gdbarch_alloc (&info
, tdep
);
5742 tdep
->elf_flags
= elf_flags
;
5743 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5744 tdep
->found_abi
= found_abi
;
5745 tdep
->mips_abi
= mips_abi
;
5746 tdep
->mips_fpu_type
= fpu_type
;
5748 /* Initially set everything according to the default ABI/ISA. */
5749 set_gdbarch_short_bit (gdbarch
, 16);
5750 set_gdbarch_int_bit (gdbarch
, 32);
5751 set_gdbarch_float_bit (gdbarch
, 32);
5752 set_gdbarch_double_bit (gdbarch
, 64);
5753 set_gdbarch_long_double_bit (gdbarch
, 64);
5754 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5755 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5756 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5758 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5759 mips_elf_make_msymbol_special
);
5761 /* Fill in the OS dependant register numbers and names. */
5763 const char **reg_names
;
5764 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5765 struct mips_regnum
);
5766 if (info
.osabi
== GDB_OSABI_IRIX
)
5771 regnum
->badvaddr
= 66;
5774 regnum
->fp_control_status
= 69;
5775 regnum
->fp_implementation_revision
= 70;
5777 reg_names
= mips_irix_reg_names
;
5781 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5782 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5783 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5784 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5785 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5786 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5787 regnum
->fp_control_status
= 70;
5788 regnum
->fp_implementation_revision
= 71;
5790 if (info
.bfd_arch_info
!= NULL
5791 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5792 reg_names
= mips_tx39_reg_names
;
5794 reg_names
= mips_generic_reg_names
;
5796 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5797 replaced by read_pc? */
5798 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5799 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5800 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5801 set_gdbarch_num_regs (gdbarch
, num_regs
);
5802 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5803 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5804 tdep
->mips_processor_reg_names
= reg_names
;
5805 tdep
->regnum
= regnum
;
5811 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5812 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5813 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5814 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5815 tdep
->default_mask_address_p
= 0;
5816 set_gdbarch_long_bit (gdbarch
, 32);
5817 set_gdbarch_ptr_bit (gdbarch
, 32);
5818 set_gdbarch_long_long_bit (gdbarch
, 64);
5821 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5822 set_gdbarch_deprecated_store_return_value (gdbarch
,
5823 mips_o64_store_return_value
);
5824 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5825 mips_o64_extract_return_value
);
5826 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5827 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5828 tdep
->default_mask_address_p
= 0;
5829 set_gdbarch_long_bit (gdbarch
, 32);
5830 set_gdbarch_ptr_bit (gdbarch
, 32);
5831 set_gdbarch_long_long_bit (gdbarch
, 64);
5832 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
5834 case MIPS_ABI_EABI32
:
5835 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5836 set_gdbarch_deprecated_store_return_value (gdbarch
,
5837 mips_eabi_store_return_value
);
5838 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5839 mips_eabi_extract_return_value
);
5840 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5841 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5842 tdep
->default_mask_address_p
= 0;
5843 set_gdbarch_long_bit (gdbarch
, 32);
5844 set_gdbarch_ptr_bit (gdbarch
, 32);
5845 set_gdbarch_long_long_bit (gdbarch
, 64);
5846 set_gdbarch_deprecated_reg_struct_has_addr
5847 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5848 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
5850 case MIPS_ABI_EABI64
:
5851 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5852 set_gdbarch_deprecated_store_return_value (gdbarch
,
5853 mips_eabi_store_return_value
);
5854 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5855 mips_eabi_extract_return_value
);
5856 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5857 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5858 tdep
->default_mask_address_p
= 0;
5859 set_gdbarch_long_bit (gdbarch
, 64);
5860 set_gdbarch_ptr_bit (gdbarch
, 64);
5861 set_gdbarch_long_long_bit (gdbarch
, 64);
5862 set_gdbarch_deprecated_reg_struct_has_addr
5863 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5864 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
5867 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5868 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5869 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5870 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5871 tdep
->default_mask_address_p
= 0;
5872 set_gdbarch_long_bit (gdbarch
, 32);
5873 set_gdbarch_ptr_bit (gdbarch
, 32);
5874 set_gdbarch_long_long_bit (gdbarch
, 64);
5875 set_gdbarch_long_double_bit (gdbarch
, 128);
5876 set_gdbarch_long_double_format (gdbarch
,
5877 &floatformat_n32n64_long_double_big
);
5880 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5881 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5882 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5883 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5884 tdep
->default_mask_address_p
= 0;
5885 set_gdbarch_long_bit (gdbarch
, 64);
5886 set_gdbarch_ptr_bit (gdbarch
, 64);
5887 set_gdbarch_long_long_bit (gdbarch
, 64);
5888 set_gdbarch_long_double_bit (gdbarch
, 128);
5889 set_gdbarch_long_double_format (gdbarch
,
5890 &floatformat_n32n64_long_double_big
);
5893 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5896 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5897 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5900 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5901 flag in object files because to do so would make it impossible to
5902 link with libraries compiled without "-gp32". This is
5903 unnecessarily restrictive.
5905 We could solve this problem by adding "-gp32" multilibs to gcc,
5906 but to set this flag before gcc is built with such multilibs will
5907 break too many systems.''
5909 But even more unhelpfully, the default linker output target for
5910 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5911 for 64-bit programs - you need to change the ABI to change this,
5912 and not all gcc targets support that currently. Therefore using
5913 this flag to detect 32-bit mode would do the wrong thing given
5914 the current gcc - it would make GDB treat these 64-bit programs
5915 as 32-bit programs by default. */
5917 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5918 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5919 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5921 /* Add/remove bits from an address. The MIPS needs be careful to
5922 ensure that all 32 bit addresses are sign extended to 64 bits. */
5923 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5925 /* Unwind the frame. */
5926 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5927 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5929 /* Map debug register numbers onto internal register numbers. */
5930 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5931 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5932 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5933 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5934 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5935 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5936 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5937 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5939 /* MIPS version of CALL_DUMMY */
5941 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5942 replaced by a command, and all targets will default to on stack
5943 (regardless of the stack's execute status). */
5944 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5945 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5947 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5948 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5949 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5951 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5952 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5954 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5956 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5957 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5958 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5960 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5962 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5964 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5966 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5967 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5968 need to all be folded into the target vector. Since they are
5969 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5970 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5972 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5974 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
5976 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5977 to support MIPS16. This is a bad thing. Make sure not to do it
5978 if we have an OS ABI that actually supports shared libraries, since
5979 shared library support is more important. If we have an OS someday
5980 that supports both shared libraries and MIPS16, we'll have to find
5981 a better place for these. */
5982 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5984 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5985 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
5988 /* Hook in OS ABI-specific overrides, if they have been registered. */
5989 gdbarch_init_osabi (info
, gdbarch
);
5991 /* Unwind the frame. */
5992 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5993 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
5994 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5995 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5996 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5997 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
5998 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5999 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6005 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6007 struct gdbarch_info info
;
6009 /* Force the architecture to update, and (if it's a MIPS architecture)
6010 mips_gdbarch_init will take care of the rest. */
6011 gdbarch_info_init (&info
);
6012 gdbarch_update_p (info
);
6015 /* Print out which MIPS ABI is in use. */
6018 show_mips_abi (char *ignore_args
, int from_tty
)
6020 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6022 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6025 enum mips_abi global_abi
= global_mips_abi ();
6026 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6027 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6029 if (global_abi
== MIPS_ABI_UNKNOWN
)
6031 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6033 else if (global_abi
== actual_abi
)
6035 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6039 /* Probably shouldn't happen... */
6041 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6042 actual_abi_str
, mips_abi_strings
[global_abi
]);
6048 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6050 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6054 int ef_mips_32bitmode
;
6055 /* determine the ISA */
6056 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6074 /* determine the size of a pointer */
6075 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6076 fprintf_unfiltered (file
,
6077 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6079 fprintf_unfiltered (file
,
6080 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6082 fprintf_unfiltered (file
,
6083 "mips_dump_tdep: ef_mips_arch = %d\n",
6085 fprintf_unfiltered (file
,
6086 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6087 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6088 fprintf_unfiltered (file
,
6089 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6090 mips_mask_address_p (tdep
),
6091 tdep
->default_mask_address_p
);
6093 fprintf_unfiltered (file
,
6094 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6095 MIPS_DEFAULT_FPU_TYPE
,
6096 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6097 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6098 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6100 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6101 fprintf_unfiltered (file
,
6102 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6104 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6105 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6106 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6108 fprintf_unfiltered (file
,
6109 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6110 mips_stack_argsize (current_gdbarch
));
6111 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6112 fprintf_unfiltered (file
,
6113 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6114 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6115 fprintf_unfiltered (file
,
6116 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6117 XSTRING (ATTACH_DETACH
));
6118 fprintf_unfiltered (file
,
6119 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6120 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6121 fprintf_unfiltered (file
,
6122 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6123 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6124 fprintf_unfiltered (file
,
6125 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6126 FIRST_EMBED_REGNUM
);
6127 fprintf_unfiltered (file
,
6128 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6129 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6130 fprintf_unfiltered (file
,
6131 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6132 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6133 fprintf_unfiltered (file
,
6134 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6135 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6136 fprintf_unfiltered (file
,
6137 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6139 #ifdef MACHINE_CPROC_FP_OFFSET
6140 fprintf_unfiltered (file
,
6141 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6142 MACHINE_CPROC_FP_OFFSET
);
6144 #ifdef MACHINE_CPROC_PC_OFFSET
6145 fprintf_unfiltered (file
,
6146 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6147 MACHINE_CPROC_PC_OFFSET
);
6149 #ifdef MACHINE_CPROC_SP_OFFSET
6150 fprintf_unfiltered (file
,
6151 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6152 MACHINE_CPROC_SP_OFFSET
);
6154 fprintf_unfiltered (file
,
6155 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6157 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6158 fprintf_unfiltered (file
,
6159 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6160 fprintf_unfiltered (file
,
6161 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6162 fprintf_unfiltered (file
,
6163 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6164 MIPS_LAST_ARG_REGNUM
,
6165 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6166 fprintf_unfiltered (file
,
6167 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6168 fprintf_unfiltered (file
,
6169 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6170 mips_abi_regsize (current_gdbarch
));
6171 fprintf_unfiltered (file
,
6172 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6173 fprintf_unfiltered (file
,
6174 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6175 fprintf_unfiltered (file
,
6176 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6177 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6178 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6179 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6180 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6181 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6182 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6183 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6184 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6185 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6186 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6187 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6189 fprintf_unfiltered (file
,
6190 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6193 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6196 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6198 fprintf_unfiltered (file
,
6199 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6200 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6201 fprintf_unfiltered (file
,
6202 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6203 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6204 fprintf_unfiltered (file
,
6205 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6206 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6207 fprintf_unfiltered (file
,
6208 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6209 SOFTWARE_SINGLE_STEP_P ());
6210 fprintf_unfiltered (file
,
6211 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6212 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6213 #ifdef STACK_END_ADDR
6214 fprintf_unfiltered (file
,
6215 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6218 fprintf_unfiltered (file
,
6219 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6220 XSTRING (STEP_SKIPS_DELAY (PC
)));
6221 fprintf_unfiltered (file
,
6222 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6223 STEP_SKIPS_DELAY_P
);
6224 fprintf_unfiltered (file
,
6225 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6226 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6227 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6228 fprintf_unfiltered (file
,
6229 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6232 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6233 (TYPE
, CNT
, OTHERTYPE
)));
6235 fprintf_unfiltered (file
,
6236 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6237 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6240 fprintf_unfiltered (file
,
6241 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6243 #ifdef TRACE_FLAVOR_SIZE
6244 fprintf_unfiltered (file
,
6245 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6249 fprintf_unfiltered (file
,
6250 "mips_dump_tdep: TRACE_SET # %s\n",
6251 XSTRING (TRACE_SET (X
, STATE
)));
6253 #ifdef UNUSED_REGNUM
6254 fprintf_unfiltered (file
,
6255 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6257 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6258 fprintf_unfiltered (file
,
6259 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6260 (long) VM_MIN_ADDRESS
);
6261 fprintf_unfiltered (file
,
6262 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6265 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6268 _initialize_mips_tdep (void)
6270 static struct cmd_list_element
*mipsfpulist
= NULL
;
6271 struct cmd_list_element
*c
;
6273 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6274 if (MIPS_ABI_LAST
+ 1
6275 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6276 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6278 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6280 mips_pdr_data
= register_objfile_data ();
6282 /* Add root prefix command for all "set mips"/"show mips" commands */
6283 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6284 "Various MIPS specific commands.",
6285 &setmipscmdlist
, "set mips ", 0, &setlist
);
6287 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6288 "Various MIPS specific commands.",
6289 &showmipscmdlist
, "show mips ", 0, &showlist
);
6291 /* Allow the user to override the saved register size. */
6292 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6295 &mips_abi_regsize_string
, "\
6296 Set size of general purpose registers saved on the stack.\n\
6297 This option can be set to one of:\n\
6298 32 - Force GDB to treat saved GP registers as 32-bit\n\
6299 64 - Force GDB to treat saved GP registers as 64-bit\n\
6300 auto - Allow GDB to use the target's default setting or autodetect the\n\
6301 saved GP register size from information contained in the executable.\n\
6302 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6304 /* Allow the user to override the argument stack size. */
6305 deprecated_add_show_from_set
6306 (add_set_enum_cmd ("stack-arg-size",
6309 &mips_stack_argsize_string
, "\
6310 Set the amount of stack space reserved for each argument.\n\
6311 This option can be set to one of:\n\
6312 32 - Force GDB to allocate 32-bit chunks per argument\n\
6313 64 - Force GDB to allocate 64-bit chunks per argument\n\
6314 auto - Allow GDB to determine the correct setting from the current\n\
6315 target and executable (default)", &setmipscmdlist
),
6318 /* Allow the user to override the ABI. */
6319 c
= add_set_enum_cmd
6320 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6321 "Set the ABI used by this program.\n"
6322 "This option can be set to one of:\n"
6323 " auto - the default ABI associated with the current binary\n"
6325 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6326 set_cmd_sfunc (c
, mips_abi_update
);
6327 add_cmd ("abi", class_obscure
, show_mips_abi
,
6328 "Show ABI in use by MIPS target", &showmipscmdlist
);
6330 /* Let the user turn off floating point and set the fence post for
6331 heuristic_proc_start. */
6333 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6334 "Set use of MIPS floating-point coprocessor.",
6335 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6336 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6337 "Select single-precision MIPS floating-point coprocessor.",
6339 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6340 "Select double-precision MIPS floating-point coprocessor.",
6342 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6343 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6344 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6345 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6346 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6347 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6348 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6349 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6350 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6351 "Select MIPS floating-point coprocessor automatically.",
6353 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6354 "Show current use of MIPS floating-point coprocessor target.",
6357 /* We really would like to have both "0" and "unlimited" work, but
6358 command.c doesn't deal with that. So make it a var_zinteger
6359 because the user can always use "999999" or some such for unlimited. */
6360 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6361 (char *) &heuristic_fence_post
, "\
6362 Set the distance searched for the start of a function.\n\
6363 If you are debugging a stripped executable, GDB needs to search through the\n\
6364 program for the start of a function. This command sets the distance of the\n\
6365 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6366 /* We need to throw away the frame cache when we set this, since it
6367 might change our ability to get backtraces. */
6368 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6369 deprecated_add_show_from_set (c
, &showlist
);
6371 /* Allow the user to control whether the upper bits of 64-bit
6372 addresses should be zeroed. */
6373 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6374 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6375 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6376 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6377 allow GDB to determine the correct value.\n", "\
6378 Zerroing of upper 32 bits of 64-bit address is %s.",
6379 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6381 /* Allow the user to control the size of 32 bit registers within the
6382 raw remote packet. */
6383 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6384 &mips64_transfers_32bit_regs_p
, "\
6385 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6386 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6387 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6388 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6389 64 bits for others. Use \"off\" to disable compatibility mode", "\
6390 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6391 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6393 /* Debug this files internals. */
6394 deprecated_add_show_from_set
6395 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6396 &mips_debug
, "Set mips debugging.\n\
6397 When non-zero, mips specific debugging is enabled.", &setdebuglist
),