1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
225 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
226 deprecated_read_register_gen (regnum
, buf
);
227 return (extract_signed_integer
228 (buf
, register_size (current_gdbarch
, regnum
)));
232 read_signed_register_pid (int regnum
, ptid_t ptid
)
237 if (ptid_equal (ptid
, inferior_ptid
))
238 return read_signed_register (regnum
);
240 save_ptid
= inferior_ptid
;
242 inferior_ptid
= ptid
;
244 retval
= read_signed_register (regnum
);
246 inferior_ptid
= save_ptid
;
251 /* Return the MIPS ABI associated with GDBARCH. */
253 mips_abi (struct gdbarch
*gdbarch
)
255 return gdbarch_tdep (gdbarch
)->mips_abi
;
259 mips_isa_regsize (struct gdbarch
*gdbarch
)
261 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
262 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
265 /* Return the currently configured (or set) saved register size. */
267 static const char *mips_abi_regsize_string
= size_auto
;
270 mips_abi_regsize (struct gdbarch
*gdbarch
)
272 if (mips_abi_regsize_string
== size_auto
)
273 switch (mips_abi (gdbarch
))
275 case MIPS_ABI_EABI32
:
281 case MIPS_ABI_EABI64
:
283 case MIPS_ABI_UNKNOWN
:
286 internal_error (__FILE__
, __LINE__
, "bad switch");
288 else if (mips_abi_regsize_string
== size_64
)
290 else /* if (mips_abi_regsize_string == size_32) */
294 /* Functions for setting and testing a bit in a minimal symbol that
295 marks it as 16-bit function. The MSB of the minimal symbol's
296 "info" field is used for this purpose.
298 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
299 i.e. refers to a 16-bit function, and sets a "special" bit in a
300 minimal symbol to mark it as a 16-bit function
302 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
305 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
307 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
309 MSYMBOL_INFO (msym
) = (char *)
310 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
311 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
316 msymbol_is_special (struct minimal_symbol
*msym
)
318 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
321 /* XFER a value from the big/little/left end of the register.
322 Depending on the size of the value it might occupy the entire
323 register or just part of it. Make an allowance for this, aligning
324 things accordingly. */
327 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
328 enum bfd_endian endian
, bfd_byte
* in
,
329 const bfd_byte
* out
, int buf_offset
)
332 gdb_assert (reg_num
>= NUM_REGS
);
333 /* Need to transfer the left or right part of the register, based on
334 the targets byte order. */
338 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
340 case BFD_ENDIAN_LITTLE
:
343 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
347 internal_error (__FILE__
, __LINE__
, "bad switch");
350 fprintf_unfiltered (gdb_stderr
,
351 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
352 reg_num
, reg_offset
, buf_offset
, length
);
353 if (mips_debug
&& out
!= NULL
)
356 fprintf_unfiltered (gdb_stdlog
, "out ");
357 for (i
= 0; i
< length
; i
++)
358 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
361 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
364 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
366 if (mips_debug
&& in
!= NULL
)
369 fprintf_unfiltered (gdb_stdlog
, "in ");
370 for (i
= 0; i
< length
; i
++)
371 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
374 fprintf_unfiltered (gdb_stdlog
, "\n");
377 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
378 compatiblity mode. A return value of 1 means that we have
379 physical 64-bit registers, but should treat them as 32-bit registers. */
382 mips2_fp_compat (void)
384 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
386 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
391 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
392 in all the places we deal with FP registers. PR gdb/413. */
393 /* Otherwise check the FR bit in the status register - it controls
394 the FP compatiblity mode. If it is clear we are in compatibility
396 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
403 /* The amount of space reserved on the stack for registers. This is
404 different to MIPS_ABI_REGSIZE as it determines the alignment of
405 data allocated after the registers have run out. */
407 static const char *mips_stack_argsize_string
= size_auto
;
410 mips_stack_argsize (struct gdbarch
*gdbarch
)
412 if (mips_stack_argsize_string
== size_auto
)
413 return mips_abi_regsize (gdbarch
);
414 else if (mips_stack_argsize_string
== size_64
)
416 else /* if (mips_stack_argsize_string == size_32) */
420 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
422 struct mips_frame_cache
;
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
425 struct mips_frame_cache
*);
426 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
429 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
431 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
433 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
435 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
437 static struct type
*mips_float_register_type (void);
438 static struct type
*mips_double_register_type (void);
440 /* The list of available "set mips " and "show mips " commands */
442 static struct cmd_list_element
*setmipscmdlist
= NULL
;
443 static struct cmd_list_element
*showmipscmdlist
= NULL
;
445 /* Integer registers 0 thru 31 are handled explicitly by
446 mips_register_name(). Processor specific registers 32 and above
447 are listed in the followign tables. */
450 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
454 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
455 "sr", "lo", "hi", "bad", "cause", "pc",
456 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
457 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
458 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
459 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
460 "fsr", "fir", "" /*"fp" */ , "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
465 /* Names of IDT R3041 registers. */
467 static const char *mips_r3041_reg_names
[] = {
468 "sr", "lo", "hi", "bad", "cause", "pc",
469 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
470 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
471 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
472 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
473 "fsr", "fir", "", /*"fp" */ "",
474 "", "", "bus", "ccfg", "", "", "", "",
475 "", "", "port", "cmp", "", "", "epc", "prid",
478 /* Names of tx39 registers. */
480 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
481 "sr", "lo", "hi", "bad", "cause", "pc",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
485 "", "", "", "", "", "", "", "",
487 "", "", "", "", "", "", "", "",
488 "", "", "config", "cache", "debug", "depc", "epc", ""
491 /* Names of IRIX registers. */
492 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
493 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
494 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
495 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
496 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
497 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
501 /* Return the name of the register corresponding to REGNO. */
503 mips_register_name (int regno
)
505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
506 /* GPR names for all ABIs other than n32/n64. */
507 static char *mips_gpr_names
[] = {
508 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
509 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
510 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
511 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
514 /* GPR names for n32 and n64 ABIs. */
515 static char *mips_n32_n64_gpr_names
[] = {
516 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
517 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
518 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
519 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
522 enum mips_abi abi
= mips_abi (current_gdbarch
);
524 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
525 don't make the raw register names visible. */
526 int rawnum
= regno
% NUM_REGS
;
527 if (regno
< NUM_REGS
)
530 /* The MIPS integer registers are always mapped from 0 to 31. The
531 names of the registers (which reflects the conventions regarding
532 register use) vary depending on the ABI. */
533 if (0 <= rawnum
&& rawnum
< 32)
535 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
536 return mips_n32_n64_gpr_names
[rawnum
];
538 return mips_gpr_names
[rawnum
];
540 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
542 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
543 return tdep
->mips_processor_reg_names
[rawnum
- 32];
546 internal_error (__FILE__
, __LINE__
,
547 "mips_register_name: bad register number %d", rawnum
);
550 /* Return the groups that a MIPS register can be categorised into. */
553 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
554 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% NUM_REGS
;
560 int pseudo
= regnum
/ NUM_REGS
;
561 if (reggroup
== all_reggroup
)
563 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
564 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
565 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
566 (gdbarch), as not all architectures are multi-arch. */
567 raw_p
= rawnum
< NUM_REGS
;
568 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
570 if (reggroup
== float_reggroup
)
571 return float_p
&& pseudo
;
572 if (reggroup
== vector_reggroup
)
573 return vector_p
&& pseudo
;
574 if (reggroup
== general_reggroup
)
575 return (!vector_p
&& !float_p
) && pseudo
;
576 /* Save the pseudo registers. Need to make certain that any code
577 extracting register values from a saved register cache also uses
579 if (reggroup
== save_reggroup
)
580 return raw_p
&& pseudo
;
581 /* Restore the same pseudo register. */
582 if (reggroup
== restore_reggroup
)
583 return raw_p
&& pseudo
;
587 /* Map the symbol table registers which live in the range [1 *
588 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
589 registers. Take care of alignment and size problems. */
592 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
593 int cookednum
, void *buf
)
595 int rawnum
= cookednum
% NUM_REGS
;
596 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
597 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
598 regcache_raw_read (regcache
, rawnum
, buf
);
599 else if (register_size (gdbarch
, rawnum
) >
600 register_size (gdbarch
, cookednum
))
602 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
603 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
604 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
606 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
609 internal_error (__FILE__
, __LINE__
, "bad register size");
613 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
614 struct regcache
*regcache
, int cookednum
,
617 int rawnum
= cookednum
% NUM_REGS
;
618 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
619 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
620 regcache_raw_write (regcache
, rawnum
, buf
);
621 else if (register_size (gdbarch
, rawnum
) >
622 register_size (gdbarch
, cookednum
))
624 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
625 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
626 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
628 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
631 internal_error (__FILE__
, __LINE__
, "bad register size");
634 /* Table to translate MIPS16 register field to actual register number. */
635 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
637 /* Heuristic_proc_start may hunt through the text section for a long
638 time across a 2400 baud serial line. Allows the user to limit this
641 static unsigned int heuristic_fence_post
= 0;
643 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
644 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
645 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
646 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
647 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
648 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
649 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
650 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
651 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
652 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
653 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
654 this will corrupt pdr.iline. Fortunately we don't use it. */
655 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
656 #define _PROC_MAGIC_ 0x0F0F0F0F
657 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
658 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
660 /* Number of bytes of storage in the actual machine representation for
661 register N. NOTE: This defines the pseudo register type so need to
662 rebuild the architecture vector. */
664 static int mips64_transfers_32bit_regs_p
= 0;
667 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
668 struct cmd_list_element
*c
)
670 struct gdbarch_info info
;
671 gdbarch_info_init (&info
);
672 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
673 instead of relying on globals. Doing that would let generic code
674 handle the search for this specific architecture. */
675 if (!gdbarch_update_p (info
))
677 mips64_transfers_32bit_regs_p
= 0;
678 error ("32-bit compatibility mode not supported");
682 /* Convert to/from a register and the corresponding memory value. */
685 mips_convert_register_p (int regnum
, struct type
*type
)
687 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
688 && register_size (current_gdbarch
, regnum
) == 4
689 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
690 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
691 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
695 mips_register_to_value (struct frame_info
*frame
, int regnum
,
696 struct type
*type
, void *to
)
698 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
699 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
703 mips_value_to_register (struct frame_info
*frame
, int regnum
,
704 struct type
*type
, const void *from
)
706 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
707 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
710 /* Return the GDB type object for the "standard" data type of data in
714 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
716 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
717 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
718 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
720 /* The floating-point registers raw, or cooked, always match
721 mips_isa_regsize(), and also map 1:1, byte for byte. */
722 switch (gdbarch_byte_order (gdbarch
))
725 if (mips_isa_regsize (gdbarch
) == 4)
726 return builtin_type_ieee_single_big
;
728 return builtin_type_ieee_double_big
;
729 case BFD_ENDIAN_LITTLE
:
730 if (mips_isa_regsize (gdbarch
) == 4)
731 return builtin_type_ieee_single_little
;
733 return builtin_type_ieee_double_little
;
734 case BFD_ENDIAN_UNKNOWN
:
736 internal_error (__FILE__
, __LINE__
, "bad switch");
739 else if (regnum
< NUM_REGS
)
741 /* The raw or ISA registers. These are all sized according to
743 if (mips_isa_regsize (gdbarch
) == 4)
744 return builtin_type_int32
;
746 return builtin_type_int64
;
750 /* The cooked or ABI registers. These are sized according to
751 the ABI (with a few complications). */
752 if (regnum
>= (NUM_REGS
753 + mips_regnum (current_gdbarch
)->fp_control_status
)
754 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
755 /* The pseudo/cooked view of the embedded registers is always
756 32-bit. The raw view is handled below. */
757 return builtin_type_int32
;
758 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
759 /* The target, while possibly using a 64-bit register buffer,
760 is only transfering 32-bits of each integer register.
761 Reflect this in the cooked/pseudo (ABI) register value. */
762 return builtin_type_int32
;
763 else if (mips_abi_regsize (gdbarch
) == 4)
764 /* The ABI is restricted to 32-bit registers (the ISA could be
766 return builtin_type_int32
;
769 return builtin_type_int64
;
773 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
778 return read_signed_register (MIPS_SP_REGNUM
);
781 /* Should the upper word of 64-bit addresses be zeroed? */
782 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
785 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
787 switch (mask_address_var
)
789 case AUTO_BOOLEAN_TRUE
:
791 case AUTO_BOOLEAN_FALSE
:
794 case AUTO_BOOLEAN_AUTO
:
795 return tdep
->default_mask_address_p
;
797 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
803 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
805 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
806 switch (mask_address_var
)
808 case AUTO_BOOLEAN_TRUE
:
809 printf_filtered ("The 32 bit mips address mask is enabled\n");
811 case AUTO_BOOLEAN_FALSE
:
812 printf_filtered ("The 32 bit mips address mask is disabled\n");
814 case AUTO_BOOLEAN_AUTO
:
816 ("The 32 bit address mask is set automatically. Currently %s\n",
817 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
820 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
825 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
828 pc_is_mips16 (bfd_vma memaddr
)
830 struct minimal_symbol
*sym
;
832 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
833 if (is_mips16_addr (memaddr
))
836 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
837 the high bit of the info field. Use this to decide if the function is
838 MIPS16 or normal MIPS. */
839 sym
= lookup_minimal_symbol_by_pc (memaddr
);
841 return msymbol_is_special (sym
);
846 /* MIPS believes that the PC has a sign extended value. Perhaps the
847 all registers should be sign extended for simplicity? */
850 mips_read_pc (ptid_t ptid
)
852 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
856 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
858 return frame_unwind_register_signed (next_frame
,
859 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
862 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
863 dummy frame. The frame ID's base needs to match the TOS value
864 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
867 static struct frame_id
868 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
870 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
871 frame_pc_unwind (next_frame
));
875 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
877 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
880 /* This returns the PC of the first inst after the prologue. If we can't
881 find the prologue, then return 0. */
884 after_prologue (CORE_ADDR pc
)
886 mips_extra_func_info_t proc_desc
;
887 struct symtab_and_line sal
;
888 CORE_ADDR func_addr
, func_end
;
889 CORE_ADDR startaddr
= 0;
891 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
892 attempt to read the stack pointer from the current machine state,
893 because the current machine state has nothing to do with the
894 information we need from the proc_desc; and the process may or
895 may not exist right now. */
896 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
899 /* IF this is the topmost frame AND (this proc does not have
900 debugging information OR the PC is in the procedure prologue)
901 THEN create a "heuristic" proc_desc (by analyzing the actual
902 code) to replace the "official" proc_desc. */
903 struct symtab_and_line val
;
904 struct symbol
*proc_symbol
=
905 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
909 val
= find_pc_line (BLOCK_START
910 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
911 val
.pc
= val
.end
? val
.end
: pc
;
913 if (!proc_symbol
|| pc
< val
.pc
)
915 mips_extra_func_info_t found_heuristic
=
916 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
, NULL
);
918 proc_desc
= found_heuristic
;
924 startaddr
= heuristic_proc_start (pc
);
926 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
, NULL
);
931 /* If function is frameless, then we need to do it the hard way. I
932 strongly suspect that frameless always means prologueless... */
933 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
934 && PROC_FRAME_OFFSET (proc_desc
) == 0)
938 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
939 return 0; /* Unknown */
941 sal
= find_pc_line (func_addr
, 0);
943 if (sal
.end
< func_end
)
946 /* The line after the prologue is after the end of the function. In this
947 case, tell the caller to find the prologue the hard way. */
952 /* Decode a MIPS32 instruction that saves a register in the stack, and
953 set the appropriate bit in the general register mask or float register mask
954 to indicate which register is saved. This is a helper function
955 for mips_find_saved_regs. */
958 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
959 unsigned long *float_mask
)
963 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
964 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
965 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
967 /* It might be possible to use the instruction to
968 find the offset, rather than the code below which
969 is based on things being in a certain order in the
970 frame, but figuring out what the instruction's offset
971 is relative to might be a little tricky. */
972 reg
= (inst
& 0x001f0000) >> 16;
973 *gen_mask
|= (1 << reg
);
975 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
976 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
977 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
980 reg
= ((inst
& 0x001f0000) >> 16);
981 *float_mask
|= (1 << reg
);
985 /* Decode a MIPS16 instruction that saves a register in the stack, and
986 set the appropriate bit in the general register or float register mask
987 to indicate which register is saved. This is a helper function
988 for mips_find_saved_regs. */
991 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
993 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
995 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
996 *gen_mask
|= (1 << reg
);
998 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1000 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1001 *gen_mask
|= (1 << reg
);
1003 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
1004 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1005 *gen_mask
|= (1 << RA_REGNUM
);
1009 /* Fetch and return instruction from the specified location. If the PC
1010 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1013 mips_fetch_instruction (CORE_ADDR addr
)
1015 char buf
[MIPS_INSTLEN
];
1019 if (pc_is_mips16 (addr
))
1021 instlen
= MIPS16_INSTLEN
;
1022 addr
= unmake_mips16_addr (addr
);
1025 instlen
= MIPS_INSTLEN
;
1026 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1028 memory_error (status
, addr
);
1029 return extract_unsigned_integer (buf
, instlen
);
1033 mips16_fetch_instruction (CORE_ADDR addr
)
1035 char buf
[MIPS_INSTLEN
];
1039 instlen
= MIPS16_INSTLEN
;
1040 addr
= unmake_mips16_addr (addr
);
1041 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1043 memory_error (status
, addr
);
1044 return extract_unsigned_integer (buf
, instlen
);
1048 mips32_fetch_instruction (CORE_ADDR addr
)
1050 char buf
[MIPS_INSTLEN
];
1053 instlen
= MIPS_INSTLEN
;
1054 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1056 memory_error (status
, addr
);
1057 return extract_unsigned_integer (buf
, instlen
);
1061 /* These the fields of 32 bit mips instructions */
1062 #define mips32_op(x) (x >> 26)
1063 #define itype_op(x) (x >> 26)
1064 #define itype_rs(x) ((x >> 21) & 0x1f)
1065 #define itype_rt(x) ((x >> 16) & 0x1f)
1066 #define itype_immediate(x) (x & 0xffff)
1068 #define jtype_op(x) (x >> 26)
1069 #define jtype_target(x) (x & 0x03ffffff)
1071 #define rtype_op(x) (x >> 26)
1072 #define rtype_rs(x) ((x >> 21) & 0x1f)
1073 #define rtype_rt(x) ((x >> 16) & 0x1f)
1074 #define rtype_rd(x) ((x >> 11) & 0x1f)
1075 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1076 #define rtype_funct(x) (x & 0x3f)
1079 mips32_relative_offset (unsigned long inst
)
1082 x
= itype_immediate (inst
);
1083 if (x
& 0x8000) /* sign bit set */
1085 x
|= 0xffff0000; /* sign extension */
1091 /* Determine whate to set a single step breakpoint while considering
1092 branch prediction */
1094 mips32_next_pc (CORE_ADDR pc
)
1098 inst
= mips_fetch_instruction (pc
);
1099 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1101 if (itype_op (inst
) >> 2 == 5)
1102 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1104 op
= (itype_op (inst
) & 0x03);
1114 goto greater_branch
;
1119 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1120 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1122 int tf
= itype_rt (inst
) & 0x01;
1123 int cnum
= itype_rt (inst
) >> 2;
1125 read_signed_register (mips_regnum (current_gdbarch
)->
1127 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1129 if (((cond
>> cnum
) & 0x01) == tf
)
1130 pc
+= mips32_relative_offset (inst
) + 4;
1135 pc
+= 4; /* Not a branch, next instruction is easy */
1138 { /* This gets way messy */
1140 /* Further subdivide into SPECIAL, REGIMM and other */
1141 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1143 case 0: /* SPECIAL */
1144 op
= rtype_funct (inst
);
1149 /* Set PC to that address */
1150 pc
= read_signed_register (rtype_rs (inst
));
1156 break; /* end SPECIAL */
1157 case 1: /* REGIMM */
1159 op
= itype_rt (inst
); /* branch condition */
1164 case 16: /* BLTZAL */
1165 case 18: /* BLTZALL */
1167 if (read_signed_register (itype_rs (inst
)) < 0)
1168 pc
+= mips32_relative_offset (inst
) + 4;
1170 pc
+= 8; /* after the delay slot */
1174 case 17: /* BGEZAL */
1175 case 19: /* BGEZALL */
1176 if (read_signed_register (itype_rs (inst
)) >= 0)
1177 pc
+= mips32_relative_offset (inst
) + 4;
1179 pc
+= 8; /* after the delay slot */
1181 /* All of the other instructions in the REGIMM category */
1186 break; /* end REGIMM */
1191 reg
= jtype_target (inst
) << 2;
1192 /* Upper four bits get never changed... */
1193 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1196 /* FIXME case JALX : */
1199 reg
= jtype_target (inst
) << 2;
1200 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1201 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1203 break; /* The new PC will be alternate mode */
1204 case 4: /* BEQ, BEQL */
1206 if (read_signed_register (itype_rs (inst
)) ==
1207 read_signed_register (itype_rt (inst
)))
1208 pc
+= mips32_relative_offset (inst
) + 4;
1212 case 5: /* BNE, BNEL */
1214 if (read_signed_register (itype_rs (inst
)) !=
1215 read_signed_register (itype_rt (inst
)))
1216 pc
+= mips32_relative_offset (inst
) + 4;
1220 case 6: /* BLEZ, BLEZL */
1221 if (read_signed_register (itype_rs (inst
) <= 0))
1222 pc
+= mips32_relative_offset (inst
) + 4;
1228 greater_branch
: /* BGTZ, BGTZL */
1229 if (read_signed_register (itype_rs (inst
) > 0))
1230 pc
+= mips32_relative_offset (inst
) + 4;
1237 } /* mips32_next_pc */
1239 /* Decoding the next place to set a breakpoint is irregular for the
1240 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1241 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1242 We dont want to set a single step instruction on the extend instruction
1246 /* Lots of mips16 instruction formats */
1247 /* Predicting jumps requires itype,ritype,i8type
1248 and their extensions extItype,extritype,extI8type
1250 enum mips16_inst_fmts
1252 itype
, /* 0 immediate 5,10 */
1253 ritype
, /* 1 5,3,8 */
1254 rrtype
, /* 2 5,3,3,5 */
1255 rritype
, /* 3 5,3,3,5 */
1256 rrrtype
, /* 4 5,3,3,3,2 */
1257 rriatype
, /* 5 5,3,3,1,4 */
1258 shifttype
, /* 6 5,3,3,3,2 */
1259 i8type
, /* 7 5,3,8 */
1260 i8movtype
, /* 8 5,3,3,5 */
1261 i8mov32rtype
, /* 9 5,3,5,3 */
1262 i64type
, /* 10 5,3,8 */
1263 ri64type
, /* 11 5,3,3,5 */
1264 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1265 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1266 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1267 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1268 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1269 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1270 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1271 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1272 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1273 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1275 /* I am heaping all the fields of the formats into one structure and
1276 then, only the fields which are involved in instruction extension */
1280 unsigned int regx
; /* Function in i8 type */
1285 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1286 for the bits which make up the immediatate extension. */
1289 extended_offset (unsigned int extension
)
1292 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1294 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1296 value
|= extension
& 0x01f; /* extract 4:0 */
1300 /* Only call this function if you know that this is an extendable
1301 instruction, It wont malfunction, but why make excess remote memory references?
1302 If the immediate operands get sign extended or somthing, do it after
1303 the extension is performed.
1305 /* FIXME: Every one of these cases needs to worry about sign extension
1306 when the offset is to be used in relative addressing */
1310 fetch_mips_16 (CORE_ADDR pc
)
1313 pc
&= 0xfffffffe; /* clear the low order bit */
1314 target_read_memory (pc
, buf
, 2);
1315 return extract_unsigned_integer (buf
, 2);
1319 unpack_mips16 (CORE_ADDR pc
,
1320 unsigned int extension
,
1322 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1327 switch (insn_format
)
1334 value
= extended_offset (extension
);
1335 value
= value
<< 11; /* rom for the original value */
1336 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1340 value
= inst
& 0x7ff;
1341 /* FIXME : Consider sign extension */
1350 { /* A register identifier and an offset */
1351 /* Most of the fields are the same as I type but the
1352 immediate value is of a different length */
1356 value
= extended_offset (extension
);
1357 value
= value
<< 8; /* from the original instruction */
1358 value
|= inst
& 0xff; /* eleven bits from instruction */
1359 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1360 if (value
& 0x4000) /* test the sign bit , bit 26 */
1362 value
&= ~0x3fff; /* remove the sign bit */
1368 value
= inst
& 0xff; /* 8 bits */
1369 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1370 /* FIXME: Do sign extension , this format needs it */
1371 if (value
& 0x80) /* THIS CONFUSES ME */
1373 value
&= 0xef; /* remove the sign bit */
1383 unsigned long value
;
1384 unsigned int nexthalf
;
1385 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1386 value
= value
<< 16;
1387 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1395 internal_error (__FILE__
, __LINE__
, "bad switch");
1397 upk
->offset
= offset
;
1404 add_offset_16 (CORE_ADDR pc
, int offset
)
1406 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1410 extended_mips16_next_pc (CORE_ADDR pc
,
1411 unsigned int extension
, unsigned int insn
)
1413 int op
= (insn
>> 11);
1416 case 2: /* Branch */
1419 struct upk_mips16 upk
;
1420 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1421 offset
= upk
.offset
;
1427 pc
+= (offset
<< 1) + 2;
1430 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1432 struct upk_mips16 upk
;
1433 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1434 pc
= add_offset_16 (pc
, upk
.offset
);
1435 if ((insn
>> 10) & 0x01) /* Exchange mode */
1436 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1443 struct upk_mips16 upk
;
1445 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1446 reg
= read_signed_register (upk
.regx
);
1448 pc
+= (upk
.offset
<< 1) + 2;
1455 struct upk_mips16 upk
;
1457 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1458 reg
= read_signed_register (upk
.regx
);
1460 pc
+= (upk
.offset
<< 1) + 2;
1465 case 12: /* I8 Formats btez btnez */
1467 struct upk_mips16 upk
;
1469 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1470 /* upk.regx contains the opcode */
1471 reg
= read_signed_register (24); /* Test register is 24 */
1472 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1473 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1474 /* pc = add_offset_16(pc,upk.offset) ; */
1475 pc
+= (upk
.offset
<< 1) + 2;
1480 case 29: /* RR Formats JR, JALR, JALR-RA */
1482 struct upk_mips16 upk
;
1483 /* upk.fmt = rrtype; */
1488 upk
.regx
= (insn
>> 8) & 0x07;
1489 upk
.regy
= (insn
>> 5) & 0x07;
1497 break; /* Function return instruction */
1503 break; /* BOGUS Guess */
1505 pc
= read_signed_register (reg
);
1512 /* This is an instruction extension. Fetch the real instruction
1513 (which follows the extension) and decode things based on
1517 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1530 mips16_next_pc (CORE_ADDR pc
)
1532 unsigned int insn
= fetch_mips_16 (pc
);
1533 return extended_mips16_next_pc (pc
, 0, insn
);
1536 /* The mips_next_pc function supports single_step when the remote
1537 target monitor or stub is not developed enough to do a single_step.
1538 It works by decoding the current instruction and predicting where a
1539 branch will go. This isnt hard because all the data is available.
1540 The MIPS32 and MIPS16 variants are quite different */
1542 mips_next_pc (CORE_ADDR pc
)
1545 return mips16_next_pc (pc
);
1547 return mips32_next_pc (pc
);
1550 struct mips_frame_cache
1553 struct trad_frame_saved_reg
*saved_regs
;
1557 static struct mips_frame_cache
*
1558 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1560 CORE_ADDR startaddr
= 0;
1561 mips_extra_func_info_t proc_desc
;
1562 struct mips_frame_cache
*cache
;
1563 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1564 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1565 /* r0 bit means kernel trap */
1567 /* What registers have been saved? Bitmasks. */
1568 unsigned long gen_mask
, float_mask
;
1570 if ((*this_cache
) != NULL
)
1571 return (*this_cache
);
1572 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1573 (*this_cache
) = cache
;
1574 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1576 /* Get the mdebug proc descriptor. */
1577 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1579 /* Must be true. This is only called when the sniffer detected a
1581 gdb_assert (proc_desc
!= NULL
);
1583 /* Extract the frame's base. */
1584 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1585 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1587 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1588 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1589 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1591 /* Must be true. The in_prologue case is left for the heuristic
1592 unwinder. This is always used on kernel traps. */
1593 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1596 /* Fill in the offsets for the registers which gen_mask says were
1599 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1602 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1603 if (gen_mask
& 0x80000000)
1605 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1606 reg_position
-= mips_abi_regsize (gdbarch
);
1610 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1611 order of that normally used by gcc. Therefore, we have to fetch
1612 the first instruction of the function, and if it's an entry
1613 instruction that saves $s0 or $s1, correct their saved addresses. */
1614 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1616 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1617 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1621 int sreg_count
= (inst
>> 6) & 3;
1623 /* Check if the ra register was pushed on the stack. */
1624 CORE_ADDR reg_position
= (cache
->base
1625 + PROC_REG_OFFSET (proc_desc
));
1627 reg_position
-= mips_abi_regsize (gdbarch
);
1629 /* Check if the s0 and s1 registers were pushed on the
1631 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1633 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1635 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1636 reg_position
-= mips_abi_regsize (gdbarch
);
1641 /* Fill in the offsets for the registers which float_mask says were
1644 CORE_ADDR reg_position
= (cache
->base
1645 + PROC_FREG_OFFSET (proc_desc
));
1647 /* Fill in the offsets for the float registers which float_mask
1649 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1650 if (float_mask
& 0x80000000)
1652 if (mips_abi_regsize (gdbarch
) == 4
1653 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1655 /* On a big endian 32 bit ABI, floating point registers
1656 are paired to form doubles such that the most
1657 significant part is in $f[N+1] and the least
1658 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1659 registers are also spilled as a pair and stored as a
1662 When little-endian the least significant part is
1663 stored first leading to the memory order $f[N] and
1666 Unfortunately, when big-endian the most significant
1667 part of the double is stored first, and the least
1668 significant is stored second. This leads to the
1669 registers being ordered in memory as firt $f[N+1] and
1672 For the big-endian case make certain that the
1673 addresses point at the correct (swapped) locations
1674 $f[N] and $f[N+1] pair (keep in mind that
1675 reg_position is decremented each time through the
1678 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1679 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1681 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1682 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1685 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1686 .addr
= reg_position
;
1687 reg_position
-= mips_abi_regsize (gdbarch
);
1690 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1691 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1694 /* SP_REGNUM, contains the value and not the address. */
1695 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1697 return (*this_cache
);
1701 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1702 struct frame_id
*this_id
)
1704 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1706 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1710 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1712 int regnum
, int *optimizedp
,
1713 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1714 int *realnump
, void *valuep
)
1716 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1718 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1719 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1722 static const struct frame_unwind mips_mdebug_frame_unwind
=
1725 mips_mdebug_frame_this_id
,
1726 mips_mdebug_frame_prev_register
1729 static const struct frame_unwind
*
1730 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1732 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1733 CORE_ADDR startaddr
= 0;
1734 mips_extra_func_info_t proc_desc
;
1737 /* Only use the mdebug frame unwinder on mdebug frames where all the
1738 registers have been saved. Leave hard cases such as no mdebug or
1739 in prologue for the heuristic unwinders. */
1741 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1742 if (proc_desc
== NULL
)
1745 /* Not sure exactly what kernel_trap means, but if it means the
1746 kernel saves the registers without a prologue doing it, we better
1747 not examine the prologue to see whether registers have been saved
1749 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1751 return &mips_mdebug_frame_unwind
;
1753 /* In any frame other than the innermost or a frame interrupted by a
1754 signal, we assume that all registers have been saved. This
1755 assumes that all register saves in a function happen before the
1756 first function call. */
1757 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1758 return &mips_mdebug_frame_unwind
;
1764 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1767 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1772 static const struct frame_base mips_mdebug_frame_base
= {
1773 &mips_mdebug_frame_unwind
,
1774 mips_mdebug_frame_base_address
,
1775 mips_mdebug_frame_base_address
,
1776 mips_mdebug_frame_base_address
1779 static const struct frame_base
*
1780 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1782 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1783 return &mips_mdebug_frame_base
;
1788 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1789 Procedures that use the 32-bit instruction set are handled by the
1790 mips_insn32 unwinder. */
1792 static struct mips_frame_cache
*
1793 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1795 mips_extra_func_info_t proc_desc
;
1796 struct mips_frame_cache
*cache
;
1797 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1798 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1799 /* r0 bit means kernel trap */
1801 /* What registers have been saved? Bitmasks. */
1802 unsigned long gen_mask
, float_mask
;
1804 if ((*this_cache
) != NULL
)
1805 return (*this_cache
);
1806 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1807 (*this_cache
) = cache
;
1808 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1810 /* Synthesize a proc descriptor. */
1812 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1813 CORE_ADDR start_addr
;
1815 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1816 if (start_addr
== 0)
1817 start_addr
= heuristic_proc_start (pc
);
1820 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, this_cache
);
1822 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, NULL
);
1826 /* Extract the frame's base. */
1827 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1828 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1830 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1831 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1832 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1834 /* In any frame other than the innermost or a frame interrupted by a
1835 signal, we assume that all registers have been saved. This
1836 assumes that all register saves in a function happen before the
1837 first function call. */
1838 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1839 /* Not sure exactly what kernel_trap means, but if it means the
1840 kernel saves the registers without a prologue doing it, we
1841 better not examine the prologue to see whether registers
1842 have been saved yet. */
1845 /* We need to figure out whether the registers that the
1846 proc_desc claims are saved have been saved yet. */
1850 /* Bitmasks; set if we have found a save for the register. */
1851 unsigned long gen_save_found
= 0;
1852 unsigned long float_save_found
= 0;
1855 /* If the address is odd, assume this is MIPS16 code. */
1856 addr
= PROC_LOW_ADDR (proc_desc
);
1857 mips16
= pc_is_mips16 (addr
);
1859 /* Scan through this function's instructions preceding the
1860 current PC, and look for those that save registers. */
1861 while (addr
< frame_pc_unwind (next_frame
))
1865 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1867 addr
+= MIPS16_INSTLEN
;
1871 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1872 &gen_save_found
, &float_save_found
);
1873 addr
+= MIPS_INSTLEN
;
1876 gen_mask
= gen_save_found
;
1877 float_mask
= float_save_found
;
1880 /* Fill in the offsets for the registers which gen_mask says were
1883 CORE_ADDR reg_position
= (cache
->base
1884 + PROC_REG_OFFSET (proc_desc
));
1886 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1887 if (gen_mask
& 0x80000000)
1889 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1890 reg_position
-= mips_abi_regsize (gdbarch
);
1894 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1895 order of that normally used by gcc. Therefore, we have to fetch
1896 the first instruction of the function, and if it's an entry
1897 instruction that saves $s0 or $s1, correct their saved addresses. */
1898 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1900 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1901 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1905 int sreg_count
= (inst
>> 6) & 3;
1907 /* Check if the ra register was pushed on the stack. */
1908 CORE_ADDR reg_position
= (cache
->base
1909 + PROC_REG_OFFSET (proc_desc
));
1911 reg_position
-= mips_abi_regsize (gdbarch
);
1913 /* Check if the s0 and s1 registers were pushed on the
1915 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1917 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1919 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1920 reg_position
-= mips_abi_regsize (gdbarch
);
1925 /* Fill in the offsets for the registers which float_mask says were
1928 CORE_ADDR reg_position
= (cache
->base
1929 + PROC_FREG_OFFSET (proc_desc
));
1931 /* Fill in the offsets for the float registers which float_mask
1933 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1934 if (float_mask
& 0x80000000)
1936 if (mips_abi_regsize (gdbarch
) == 4
1937 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1939 /* On a big endian 32 bit ABI, floating point registers
1940 are paired to form doubles such that the most
1941 significant part is in $f[N+1] and the least
1942 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1943 registers are also spilled as a pair and stored as a
1946 When little-endian the least significant part is
1947 stored first leading to the memory order $f[N] and
1950 Unfortunately, when big-endian the most significant
1951 part of the double is stored first, and the least
1952 significant is stored second. This leads to the
1953 registers being ordered in memory as firt $f[N+1] and
1956 For the big-endian case make certain that the
1957 addresses point at the correct (swapped) locations
1958 $f[N] and $f[N+1] pair (keep in mind that
1959 reg_position is decremented each time through the
1962 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1963 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1965 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1966 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1969 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1970 .addr
= reg_position
;
1971 reg_position
-= mips_abi_regsize (gdbarch
);
1974 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1975 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1978 /* SP_REGNUM, contains the value and not the address. */
1979 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1981 return (*this_cache
);
1985 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1986 struct frame_id
*this_id
)
1988 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1990 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1994 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1996 int regnum
, int *optimizedp
,
1997 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1998 int *realnump
, void *valuep
)
2000 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2002 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2003 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2006 static const struct frame_unwind mips_insn16_frame_unwind
=
2009 mips_insn16_frame_this_id
,
2010 mips_insn16_frame_prev_register
2013 static const struct frame_unwind
*
2014 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
2016 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2017 if (pc_is_mips16 (pc
))
2018 return &mips_insn16_frame_unwind
;
2023 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
2026 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2031 static const struct frame_base mips_insn16_frame_base
=
2033 &mips_insn16_frame_unwind
,
2034 mips_insn16_frame_base_address
,
2035 mips_insn16_frame_base_address
,
2036 mips_insn16_frame_base_address
2039 static const struct frame_base
*
2040 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
2042 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
2043 return &mips_insn16_frame_base
;
2048 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2049 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2050 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2053 static struct mips_frame_cache
*
2054 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2056 mips_extra_func_info_t proc_desc
;
2057 struct mips_frame_cache
*cache
;
2058 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2059 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2060 /* r0 bit means kernel trap */
2062 /* What registers have been saved? Bitmasks. */
2063 unsigned long gen_mask
, float_mask
;
2065 if ((*this_cache
) != NULL
)
2066 return (*this_cache
);
2067 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2068 (*this_cache
) = cache
;
2069 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2071 /* Synthesize a proc descriptor. */
2073 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2074 CORE_ADDR start_addr
;
2076 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2077 if (start_addr
== 0)
2078 start_addr
= heuristic_proc_start (pc
);
2081 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, this_cache
);
2083 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, NULL
);
2087 if (proc_desc
== NULL
)
2088 /* I'm not sure how/whether this can happen. Normally when we
2089 can't find a proc_desc, we "synthesize" one using
2090 heuristic_proc_desc and set the saved_regs right away. */
2093 /* Extract the frame's base. */
2094 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2095 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2097 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
2098 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
2099 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
2101 /* In any frame other than the innermost or a frame interrupted by a
2102 signal, we assume that all registers have been saved. This
2103 assumes that all register saves in a function happen before the
2104 first function call. */
2105 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
2106 /* Not sure exactly what kernel_trap means, but if it means the
2107 kernel saves the registers without a prologue doing it, we
2108 better not examine the prologue to see whether registers
2109 have been saved yet. */
2112 /* We need to figure out whether the registers that the
2113 proc_desc claims are saved have been saved yet. */
2117 /* Bitmasks; set if we have found a save for the register. */
2118 unsigned long gen_save_found
= 0;
2119 unsigned long float_save_found
= 0;
2121 addr
= PROC_LOW_ADDR (proc_desc
);
2123 /* Scan through this function's instructions preceding the
2124 current PC, and look for those that save registers. */
2125 while (addr
< frame_pc_unwind (next_frame
))
2127 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
2128 &gen_save_found
, &float_save_found
);
2129 addr
+= MIPS_INSTLEN
;
2131 gen_mask
= gen_save_found
;
2132 float_mask
= float_save_found
;
2135 /* Fill in the offsets for the registers which gen_mask says were
2138 CORE_ADDR reg_position
= (cache
->base
2139 + PROC_REG_OFFSET (proc_desc
));
2141 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
2142 if (gen_mask
& 0x80000000)
2144 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
2145 reg_position
-= mips_abi_regsize (gdbarch
);
2149 /* Fill in the offsets for the registers which float_mask says were
2152 CORE_ADDR reg_position
= (cache
->base
+ PROC_FREG_OFFSET (proc_desc
));
2155 /* Fill in the offsets for the float registers which float_mask
2157 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
2158 if (float_mask
& 0x80000000)
2161 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
;
2163 if (mips_abi_regsize (gdbarch
) == 4
2164 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2166 /* On a big endian 32 bit ABI, floating point registers
2167 are paired to form doubles such that the most
2168 significant part is in $f[N+1] and the least
2169 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
2170 registers are also spilled as a pair and stored as a
2173 When little-endian the least significant part is
2174 stored first leading to the memory order $f[N] and
2177 Unfortunately, when big-endian the most significant
2178 part of the double is stored first, and the least
2179 significant is stored second. This leads to the
2180 registers being ordered in memory as firt $f[N+1] and
2183 For the big-endian case make certain that the
2184 addresses point at the correct (swapped) locations
2185 $f[N] and $f[N+1] pair (keep in mind that
2186 reg_position is decremented each time through the
2189 cache
->saved_regs
[regno
].addr
=
2190 reg_position
- mips_abi_regsize (gdbarch
);
2192 cache
->saved_regs
[regno
].addr
=
2193 reg_position
+ mips_abi_regsize (gdbarch
);
2196 cache
->saved_regs
[regno
].addr
= reg_position
;
2197 reg_position
-= mips_abi_regsize (gdbarch
);
2200 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2201 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2204 /* SP_REGNUM, contains the value and not the address. */
2205 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2207 return (*this_cache
);
2211 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2212 struct frame_id
*this_id
)
2214 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2216 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2220 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2222 int regnum
, int *optimizedp
,
2223 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2224 int *realnump
, void *valuep
)
2226 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2228 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2229 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2232 static const struct frame_unwind mips_insn32_frame_unwind
=
2235 mips_insn32_frame_this_id
,
2236 mips_insn32_frame_prev_register
2239 static const struct frame_unwind
*
2240 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2242 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2243 if (! pc_is_mips16 (pc
))
2244 return &mips_insn32_frame_unwind
;
2249 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2252 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2257 static const struct frame_base mips_insn32_frame_base
=
2259 &mips_insn32_frame_unwind
,
2260 mips_insn32_frame_base_address
,
2261 mips_insn32_frame_base_address
,
2262 mips_insn32_frame_base_address
2265 static const struct frame_base
*
2266 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2268 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2269 return &mips_insn32_frame_base
;
2274 static struct trad_frame_cache
*
2275 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2278 CORE_ADDR start_addr
;
2279 CORE_ADDR stack_addr
;
2280 struct trad_frame_cache
*this_trad_cache
;
2282 if ((*this_cache
) != NULL
)
2283 return (*this_cache
);
2284 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2285 (*this_cache
) = this_trad_cache
;
2287 /* The return address is in the link register. */
2288 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2290 /* Frame ID, since it's a frameless / stackless function, no stack
2291 space is allocated and SP on entry is the current SP. */
2292 pc
= frame_pc_unwind (next_frame
);
2293 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2294 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2295 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2297 /* Assume that the frame's base is the same as the
2299 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2301 return this_trad_cache
;
2305 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2306 struct frame_id
*this_id
)
2308 struct trad_frame_cache
*this_trad_cache
2309 = mips_stub_frame_cache (next_frame
, this_cache
);
2310 trad_frame_get_id (this_trad_cache
, this_id
);
2314 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2316 int regnum
, int *optimizedp
,
2317 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2318 int *realnump
, void *valuep
)
2320 struct trad_frame_cache
*this_trad_cache
2321 = mips_stub_frame_cache (next_frame
, this_cache
);
2322 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2323 lvalp
, addrp
, realnump
, valuep
);
2326 static const struct frame_unwind mips_stub_frame_unwind
=
2329 mips_stub_frame_this_id
,
2330 mips_stub_frame_prev_register
2333 static const struct frame_unwind
*
2334 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2336 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2337 if (in_plt_section (pc
, NULL
))
2338 return &mips_stub_frame_unwind
;
2344 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2347 struct trad_frame_cache
*this_trad_cache
2348 = mips_stub_frame_cache (next_frame
, this_cache
);
2349 return trad_frame_get_this_base (this_trad_cache
);
2352 static const struct frame_base mips_stub_frame_base
=
2354 &mips_stub_frame_unwind
,
2355 mips_stub_frame_base_address
,
2356 mips_stub_frame_base_address
,
2357 mips_stub_frame_base_address
2360 static const struct frame_base
*
2361 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2363 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2364 return &mips_stub_frame_base
;
2370 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2372 /* Always a pseudo. */
2373 gdb_assert (regno
>= NUM_REGS
);
2377 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2380 else if ((regno
% NUM_REGS
) == MIPS_SP_REGNUM
)
2381 /* MIPS_SP_REGNUM is special, its value is stored in saved_regs.
2382 In fact, it is so special that it can even only be fetched
2383 using a raw register number! Once this code as been converted
2384 to frame-unwind the problem goes away. */
2385 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
2387 return frame_unwind_register_signed (fi
, regno
);
2391 /* mips_addr_bits_remove - remove useless address bits */
2394 mips_addr_bits_remove (CORE_ADDR addr
)
2396 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2397 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2398 /* This hack is a work-around for existing boards using PMON, the
2399 simulator, and any other 64-bit targets that doesn't have true
2400 64-bit addressing. On these targets, the upper 32 bits of
2401 addresses are ignored by the hardware. Thus, the PC or SP are
2402 likely to have been sign extended to all 1s by instruction
2403 sequences that load 32-bit addresses. For example, a typical
2404 piece of code that loads an address is this:
2406 lui $r2, <upper 16 bits>
2407 ori $r2, <lower 16 bits>
2409 But the lui sign-extends the value such that the upper 32 bits
2410 may be all 1s. The workaround is simply to mask off these
2411 bits. In the future, gcc may be changed to support true 64-bit
2412 addressing, and this masking will have to be disabled. */
2413 return addr
&= 0xffffffffUL
;
2418 /* mips_software_single_step() is called just before we want to resume
2419 the inferior, if we want to single-step it but there is no hardware
2420 or kernel single-step support (MIPS on GNU/Linux for example). We find
2421 the target of the coming instruction and breakpoint it.
2423 single_step is also called just after the inferior stops. If we had
2424 set up a simulated single-step, we undo our damage. */
2427 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2429 static CORE_ADDR next_pc
;
2430 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2431 static binsn_quantum break_mem
;
2434 if (insert_breakpoints_p
)
2436 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2437 next_pc
= mips_next_pc (pc
);
2439 target_insert_breakpoint (next_pc
, break_mem
);
2442 target_remove_breakpoint (next_pc
, break_mem
);
2445 static struct mips_extra_func_info temp_proc_desc
;
2447 /* Set a register's saved stack address in temp_saved_regs. If an
2448 address has already been set for this register, do nothing; this
2449 way we will only recognize the first save of a given register in a
2452 For simplicity, save the address in both [0 .. NUM_REGS) and
2453 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2454 is used as it is only second range (the ABI instead of ISA
2455 registers) that comes into play when finding saved registers in a
2459 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
2462 if (this_cache
!= NULL
2463 && this_cache
->saved_regs
[regnum
].addr
== 0)
2465 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
2466 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
2471 /* Test whether the PC points to the return instruction at the
2472 end of a function. */
2475 mips_about_to_return (CORE_ADDR pc
)
2477 if (pc_is_mips16 (pc
))
2478 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2479 generates a "jr $ra"; other times it generates code to load
2480 the return address from the stack to an accessible register (such
2481 as $a3), then a "jr" using that register. This second case
2482 is almost impossible to distinguish from an indirect jump
2483 used for switch statements, so we don't even try. */
2484 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2486 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2490 /* This fencepost looks highly suspicious to me. Removing it also
2491 seems suspicious as it could affect remote debugging across serial
2495 heuristic_proc_start (CORE_ADDR pc
)
2502 pc
= ADDR_BITS_REMOVE (pc
);
2504 fence
= start_pc
- heuristic_fence_post
;
2508 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2509 fence
= VM_MIN_ADDRESS
;
2511 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2513 /* search back for previous return */
2514 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2515 if (start_pc
< fence
)
2517 /* It's not clear to me why we reach this point when
2518 stop_soon, but with this test, at least we
2519 don't print out warnings for every child forked (eg, on
2520 decstation). 22apr93 rich@cygnus.com. */
2521 if (stop_soon
== NO_STOP_QUIETLY
)
2523 static int blurb_printed
= 0;
2525 warning ("GDB can't find the start of the function at 0x%s.",
2530 /* This actually happens frequently in embedded
2531 development, when you first connect to a board
2532 and your stack pointer and pc are nowhere in
2533 particular. This message needs to give people
2534 in that situation enough information to
2535 determine that it's no big deal. */
2536 printf_filtered ("\n\
2537 GDB is unable to find the start of the function at 0x%s\n\
2538 and thus can't determine the size of that function's stack frame.\n\
2539 This means that GDB may be unable to access that stack frame, or\n\
2540 the frames below it.\n\
2541 This problem is most likely caused by an invalid program counter or\n\
2543 However, if you think GDB should simply search farther back\n\
2544 from 0x%s for code which looks like the beginning of a\n\
2545 function, you can increase the range of the search using the `set\n\
2546 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2553 else if (pc_is_mips16 (start_pc
))
2555 unsigned short inst
;
2557 /* On MIPS16, any one of the following is likely to be the
2558 start of a function:
2562 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2563 inst
= mips_fetch_instruction (start_pc
);
2564 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2565 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2566 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2567 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2569 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2570 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2575 else if (mips_about_to_return (start_pc
))
2577 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2584 /* Fetch the immediate value from a MIPS16 instruction.
2585 If the previous instruction was an EXTEND, use it to extend
2586 the upper bits of the immediate value. This is a helper function
2587 for mips16_heuristic_proc_desc. */
2590 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2591 unsigned short inst
, /* current instruction */
2592 int nbits
, /* number of bits in imm field */
2593 int scale
, /* scale factor to be applied to imm */
2594 int is_signed
) /* is the imm field signed? */
2598 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2600 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2601 if (offset
& 0x8000) /* check for negative extend */
2602 offset
= 0 - (0x10000 - (offset
& 0xffff));
2603 return offset
| (inst
& 0x1f);
2607 int max_imm
= 1 << nbits
;
2608 int mask
= max_imm
- 1;
2609 int sign_bit
= max_imm
>> 1;
2611 offset
= inst
& mask
;
2612 if (is_signed
&& (offset
& sign_bit
))
2613 offset
= 0 - (max_imm
- offset
);
2614 return offset
* scale
;
2619 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2620 stream from start_pc to limit_pc. */
2623 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2625 struct frame_info
*next_frame
,
2626 struct mips_frame_cache
*this_cache
)
2629 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2630 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2631 unsigned inst
= 0; /* current instruction */
2632 unsigned entry_inst
= 0; /* the entry instruction */
2634 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2636 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2637 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2639 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2641 /* Save the previous instruction. If it's an EXTEND, we'll extract
2642 the immediate offset extension from it in mips16_get_imm. */
2645 /* Fetch and decode the instruction. */
2646 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2647 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2648 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2650 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2651 if (offset
< 0) /* negative stack adjustment? */
2652 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2654 /* Exit loop if a positive stack adjustment is found, which
2655 usually means that the stack cleanup code in the function
2656 epilogue is reached. */
2659 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2661 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2662 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2663 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2664 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2666 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2668 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2669 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2670 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2671 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2673 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2675 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2676 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2677 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2679 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2681 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2682 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2683 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2685 else if (inst
== 0x673d) /* move $s1, $sp */
2688 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2690 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2692 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2693 frame_addr
= sp
+ offset
;
2694 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2695 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2697 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2699 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2700 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2701 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2702 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2704 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2706 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2707 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2708 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2709 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2711 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2712 entry_inst
= inst
; /* save for later processing */
2713 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2714 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2717 /* The entry instruction is typically the first instruction in a function,
2718 and it stores registers at offsets relative to the value of the old SP
2719 (before the prologue). But the value of the sp parameter to this
2720 function is the new SP (after the prologue has been executed). So we
2721 can't calculate those offsets until we've seen the entire prologue,
2722 and can calculate what the old SP must have been. */
2723 if (entry_inst
!= 0)
2725 int areg_count
= (entry_inst
>> 8) & 7;
2726 int sreg_count
= (entry_inst
>> 6) & 3;
2728 /* The entry instruction always subtracts 32 from the SP. */
2729 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2731 /* Now we can calculate what the SP must have been at the
2732 start of the function prologue. */
2733 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2735 /* Check if a0-a3 were saved in the caller's argument save area. */
2736 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2738 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2739 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2740 offset
+= mips_abi_regsize (current_gdbarch
);
2743 /* Check if the ra register was pushed on the stack. */
2745 if (entry_inst
& 0x20)
2747 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2748 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2749 offset
-= mips_abi_regsize (current_gdbarch
);
2752 /* Check if the s0 and s1 registers were pushed on the stack. */
2753 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2755 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2756 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2757 offset
-= mips_abi_regsize (current_gdbarch
);
2763 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2764 CORE_ADDR sp
, struct frame_info
*next_frame
,
2765 struct mips_frame_cache
*this_cache
)
2768 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2770 this_cache
= xrealloc (this_cache
, SIZEOF_FRAME_SAVED_REGS
);
2771 memset (this_cache
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2772 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2773 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2774 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2776 unsigned long inst
, high_word
, low_word
;
2779 /* Fetch the instruction. */
2780 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2782 /* Save some code by pre-extracting some useful fields. */
2783 high_word
= (inst
>> 16) & 0xffff;
2784 low_word
= inst
& 0xffff;
2785 reg
= high_word
& 0x1f;
2787 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2788 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2789 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2791 if (low_word
& 0x8000) /* negative stack adjustment? */
2792 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2794 /* Exit loop if a positive stack adjustment is found, which
2795 usually means that the stack cleanup code in the function
2796 epilogue is reached. */
2799 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2801 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2802 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2804 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2806 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2808 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2809 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2811 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2813 /* Old gcc frame, r30 is virtual frame pointer. */
2814 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2815 frame_addr
= sp
+ low_word
;
2816 else if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2818 unsigned alloca_adjust
;
2819 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2820 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2821 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2822 if (alloca_adjust
> 0)
2824 /* FP > SP + frame_size. This may be because
2825 * of an alloca or somethings similar.
2826 * Fix sp to "pre-alloca" value, and try again.
2828 sp
+= alloca_adjust
;
2833 /* move $30,$sp. With different versions of gas this will be either
2834 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2835 Accept any one of these. */
2836 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2838 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2839 if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2841 unsigned alloca_adjust
;
2842 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2843 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2844 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2845 if (alloca_adjust
> 0)
2847 /* FP > SP + frame_size. This may be because
2848 * of an alloca or somethings similar.
2849 * Fix sp to "pre-alloca" value, and try again.
2851 sp
+= alloca_adjust
;
2856 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2858 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2859 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2864 static mips_extra_func_info_t
2865 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2866 struct frame_info
*next_frame
,
2867 struct mips_frame_cache
*this_cache
)
2871 /* Can be called when there's no process, and hence when there's no
2873 if (next_frame
!= NULL
)
2874 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2880 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2881 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2882 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2883 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2885 if (start_pc
+ 200 < limit_pc
)
2886 limit_pc
= start_pc
+ 200;
2887 if (pc_is_mips16 (start_pc
))
2888 mips16_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2889 next_frame
, this_cache
);
2891 mips32_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2892 next_frame
, this_cache
);
2893 return &temp_proc_desc
;
2896 struct mips_objfile_private
2902 /* Global used to communicate between non_heuristic_proc_desc and
2903 compare_pdr_entries within qsort (). */
2904 static bfd
*the_bfd
;
2907 compare_pdr_entries (const void *a
, const void *b
)
2909 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2910 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2914 else if (lhs
== rhs
)
2920 static mips_extra_func_info_t
2921 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2923 CORE_ADDR startaddr
;
2924 mips_extra_func_info_t proc_desc
;
2925 struct block
*b
= block_for_pc (pc
);
2927 struct obj_section
*sec
;
2928 struct mips_objfile_private
*priv
;
2930 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2932 *addrptr
= startaddr
;
2936 sec
= find_pc_section (pc
);
2939 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2941 /* Search the ".pdr" section generated by GAS. This includes most of
2942 the information normally found in ECOFF PDRs. */
2944 the_bfd
= sec
->objfile
->obfd
;
2946 && (the_bfd
->format
== bfd_object
2947 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2948 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2950 /* Right now GAS only outputs the address as a four-byte sequence.
2951 This means that we should not bother with this method on 64-bit
2952 targets (until that is fixed). */
2954 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2955 sizeof (struct mips_objfile_private
));
2957 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2959 else if (priv
== NULL
)
2963 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2964 sizeof (struct mips_objfile_private
));
2966 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2969 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2970 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2972 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2973 priv
->contents
, 0, priv
->size
);
2975 /* In general, the .pdr section is sorted. However, in the
2976 presence of multiple code sections (and other corner cases)
2977 it can become unsorted. Sort it so that we can use a faster
2979 qsort (priv
->contents
, priv
->size
/ 32, 32,
2980 compare_pdr_entries
);
2985 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2989 if (priv
->size
!= 0)
2996 high
= priv
->size
/ 32;
2998 /* We've found a .pdr section describing this objfile. We want to
2999 find the entry which describes this code address. The .pdr
3000 information is not very descriptive; we have only a function
3001 start address. We have to look for the closest entry, because
3002 the local symbol at the beginning of this function may have
3003 been stripped - so if we ask the symbol table for the start
3004 address we may get a preceding global function. */
3006 /* First, find the last .pdr entry starting at or before PC. */
3009 mid
= (low
+ high
) / 2;
3011 ptr
= priv
->contents
+ mid
* 32;
3012 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3013 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3014 SECT_OFF_TEXT (sec
->objfile
));
3021 while (low
!= high
);
3023 /* Both low and high point one past the PDR of interest. If
3024 both are zero, that means this PC is before any region
3025 covered by a PDR, i.e. pdr_pc for the first PDR entry is
3029 ptr
= priv
->contents
+ (low
- 1) * 32;
3030 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3031 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3032 SECT_OFF_TEXT (sec
->objfile
));
3035 /* We don't have a range, so we have no way to know for sure
3036 whether we're in the correct PDR or a PDR for a preceding
3037 function and the current function was a stripped local
3038 symbol. But if the PDR's PC is at least as great as the
3039 best guess from the symbol table, assume that it does cover
3040 the right area; if a .pdr section is present at all then
3041 nearly every function will have an entry. The biggest exception
3042 will be the dynamic linker stubs; conveniently these are
3043 placed before .text instead of after. */
3045 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
3047 struct symbol
*sym
= find_pc_function (pc
);
3052 /* Fill in what we need of the proc_desc. */
3053 proc_desc
= (mips_extra_func_info_t
)
3054 obstack_alloc (&sec
->objfile
->objfile_obstack
,
3055 sizeof (struct mips_extra_func_info
));
3056 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
3058 /* Only used for dummy frames. */
3059 PROC_HIGH_ADDR (proc_desc
) = 0;
3061 PROC_FRAME_OFFSET (proc_desc
)
3062 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
3063 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3065 PROC_FRAME_ADJUST (proc_desc
) = 0;
3066 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3068 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3070 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3072 PROC_FREG_OFFSET (proc_desc
)
3073 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
3074 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3076 proc_desc
->pdr
.isym
= (long) sym
;
3086 if (startaddr
> BLOCK_START (b
))
3088 /* This is the "pathological" case referred to in a comment in
3089 print_frame_info. It might be better to move this check into
3094 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
3096 /* If we never found a PDR for this function in symbol reading, then
3097 examine prologues to find the information. */
3100 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
3101 if (PROC_FRAME_REG (proc_desc
) == -1)
3110 /* MIPS stack frames are almost impenetrable. When execution stops,
3111 we basically have to look at symbol information for the function
3112 that we stopped in, which tells us *which* register (if any) is
3113 the base of the frame pointer, and what offset from that register
3114 the frame itself is at.
3116 This presents a problem when trying to examine a stack in memory
3117 (that isn't executing at the moment), using the "frame" command. We
3118 don't have a PC, nor do we have any registers except SP.
3120 This routine takes two arguments, SP and PC, and tries to make the
3121 cached frames look as if these two arguments defined a frame on the
3122 cache. This allows the rest of info frame to extract the important
3123 arguments without difficulty. */
3126 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
3129 error ("MIPS frame specifications require two arguments: sp and pc");
3131 return create_new_frame (argv
[0], argv
[1]);
3134 /* According to the current ABI, should the type be passed in a
3135 floating-point register (assuming that there is space)? When there
3136 is no FPU, FP are not even considered as possibile candidates for
3137 FP registers and, consequently this returns false - forces FP
3138 arguments into integer registers. */
3141 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
3143 return ((typecode
== TYPE_CODE_FLT
3145 && (typecode
== TYPE_CODE_STRUCT
3146 || typecode
== TYPE_CODE_UNION
)
3147 && TYPE_NFIELDS (arg_type
) == 1
3148 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
3149 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
3152 /* On o32, argument passing in GPRs depends on the alignment of the type being
3153 passed. Return 1 if this type must be aligned to a doubleword boundary. */
3156 mips_type_needs_double_align (struct type
*type
)
3158 enum type_code typecode
= TYPE_CODE (type
);
3160 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
3162 else if (typecode
== TYPE_CODE_STRUCT
)
3164 if (TYPE_NFIELDS (type
) < 1)
3166 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
3168 else if (typecode
== TYPE_CODE_UNION
)
3172 n
= TYPE_NFIELDS (type
);
3173 for (i
= 0; i
< n
; i
++)
3174 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3181 /* Adjust the address downward (direction of stack growth) so that it
3182 is correctly aligned for a new stack frame. */
3184 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3186 return align_down (addr
, 16);
3189 /* Determine how a return value is stored within the MIPS register
3190 file, given the return type `valtype'. */
3192 struct return_value_word
3201 return_value_location (struct type
*valtype
,
3202 struct return_value_word
*hi
,
3203 struct return_value_word
*lo
)
3205 int len
= TYPE_LENGTH (valtype
);
3206 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3208 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3209 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3210 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3212 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3214 /* We need to break a 64bit float in two 32 bit halves and
3215 spread them across a floating-point register pair. */
3216 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3217 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3218 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3219 && register_size (current_gdbarch
,
3220 mips_regnum (current_gdbarch
)->
3221 fp0
) == 8) ? 4 : 0);
3222 hi
->reg_offset
= lo
->reg_offset
;
3223 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3224 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3230 /* The floating point value fits in a single floating-point
3232 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3233 && register_size (current_gdbarch
,
3234 mips_regnum (current_gdbarch
)->
3236 && len
== 4) ? 4 : 0);
3237 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3248 /* Locate a result possibly spread across two registers. */
3250 lo
->reg
= regnum
+ 0;
3251 hi
->reg
= regnum
+ 1;
3252 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3253 && len
< mips_abi_regsize (current_gdbarch
))
3255 /* "un-left-justify" the value in the low register */
3256 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3261 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3262 && len
< mips_abi_regsize (current_gdbarch
) * 2
3263 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3264 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3266 /* "un-left-justify" the value spread across two registers. */
3267 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3268 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3270 hi
->len
= len
- lo
->len
;
3274 /* Only perform a partial copy of the second register. */
3277 if (len
> mips_abi_regsize (current_gdbarch
))
3279 lo
->len
= mips_abi_regsize (current_gdbarch
);
3280 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3288 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3289 && register_size (current_gdbarch
, regnum
) == 8
3290 && mips_abi_regsize (current_gdbarch
) == 4)
3292 /* Account for the fact that only the least-signficant part
3293 of the register is being used */
3294 lo
->reg_offset
+= 4;
3295 hi
->reg_offset
+= 4;
3298 hi
->buf_offset
= lo
->len
;
3302 /* Should call_function allocate stack space for a struct return? */
3305 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3307 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3308 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3311 /* Should call_function pass struct by reference?
3312 For each architecture, structs are passed either by
3313 value or by reference, depending on their size. */
3316 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3318 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3319 int len
= TYPE_LENGTH (check_typedef (type
));
3320 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3322 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3323 return (len
> mips_abi_regsize (current_gdbarch
));
3329 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3330 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3331 int nargs
, struct value
**args
, CORE_ADDR sp
,
3332 int struct_return
, CORE_ADDR struct_addr
)
3338 int stack_offset
= 0;
3339 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3340 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3342 /* For shared libraries, "t9" needs to point at the function
3344 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3346 /* Set the return address register to point to the entry point of
3347 the program, where a breakpoint lies in wait. */
3348 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3350 /* First ensure that the stack and structure return address (if any)
3351 are properly aligned. The stack has to be at least 64-bit
3352 aligned even on 32-bit machines, because doubles must be 64-bit
3353 aligned. For n32 and n64, stack frames need to be 128-bit
3354 aligned, so we round to this widest known alignment. */
3356 sp
= align_down (sp
, 16);
3357 struct_addr
= align_down (struct_addr
, 16);
3359 /* Now make space on the stack for the args. We allocate more
3360 than necessary for EABI, because the first few arguments are
3361 passed in registers, but that's OK. */
3362 for (argnum
= 0; argnum
< nargs
; argnum
++)
3363 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3364 mips_stack_argsize (gdbarch
));
3365 sp
-= align_up (len
, 16);
3368 fprintf_unfiltered (gdb_stdlog
,
3369 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3370 paddr_nz (sp
), (long) align_up (len
, 16));
3372 /* Initialize the integer and float register pointers. */
3374 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3376 /* The struct_return pointer occupies the first parameter-passing reg. */
3380 fprintf_unfiltered (gdb_stdlog
,
3381 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3382 argreg
, paddr_nz (struct_addr
));
3383 write_register (argreg
++, struct_addr
);
3386 /* Now load as many as possible of the first arguments into
3387 registers, and push the rest onto the stack. Loop thru args
3388 from first to last. */
3389 for (argnum
= 0; argnum
< nargs
; argnum
++)
3392 char valbuf
[MAX_REGISTER_SIZE
];
3393 struct value
*arg
= args
[argnum
];
3394 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3395 int len
= TYPE_LENGTH (arg_type
);
3396 enum type_code typecode
= TYPE_CODE (arg_type
);
3399 fprintf_unfiltered (gdb_stdlog
,
3400 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3401 argnum
+ 1, len
, (int) typecode
);
3403 /* The EABI passes structures that do not fit in a register by
3405 if (len
> mips_abi_regsize (gdbarch
)
3406 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3408 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3409 VALUE_ADDRESS (arg
));
3410 typecode
= TYPE_CODE_PTR
;
3411 len
= mips_abi_regsize (gdbarch
);
3414 fprintf_unfiltered (gdb_stdlog
, " push");
3417 val
= (char *) VALUE_CONTENTS (arg
);
3419 /* 32-bit ABIs always start floating point arguments in an
3420 even-numbered floating point register. Round the FP register
3421 up before the check to see if there are any FP registers
3422 left. Non MIPS_EABI targets also pass the FP in the integer
3423 registers so also round up normal registers. */
3424 if (mips_abi_regsize (gdbarch
) < 8
3425 && fp_register_arg_p (typecode
, arg_type
))
3427 if ((float_argreg
& 1))
3431 /* Floating point arguments passed in registers have to be
3432 treated specially. On 32-bit architectures, doubles
3433 are passed in register pairs; the even register gets
3434 the low word, and the odd register gets the high word.
3435 On non-EABI processors, the first two floating point arguments are
3436 also copied to general registers, because MIPS16 functions
3437 don't use float registers for arguments. This duplication of
3438 arguments in general registers can't hurt non-MIPS16 functions
3439 because those registers are normally skipped. */
3440 /* MIPS_EABI squeezes a struct that contains a single floating
3441 point value into an FP register instead of pushing it onto the
3443 if (fp_register_arg_p (typecode
, arg_type
)
3444 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3446 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3448 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3449 unsigned long regval
;
3451 /* Write the low word of the double to the even register(s). */
3452 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3454 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3455 float_argreg
, phex (regval
, 4));
3456 write_register (float_argreg
++, regval
);
3458 /* Write the high word of the double to the odd register(s). */
3459 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3461 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3462 float_argreg
, phex (regval
, 4));
3463 write_register (float_argreg
++, regval
);
3467 /* This is a floating point value that fits entirely
3468 in a single register. */
3469 /* On 32 bit ABI's the float_argreg is further adjusted
3470 above to ensure that it is even register aligned. */
3471 LONGEST regval
= extract_unsigned_integer (val
, len
);
3473 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3474 float_argreg
, phex (regval
, len
));
3475 write_register (float_argreg
++, regval
);
3480 /* Copy the argument to general registers or the stack in
3481 register-sized pieces. Large arguments are split between
3482 registers and stack. */
3483 /* Note: structs whose size is not a multiple of
3484 mips_abi_regsize() are treated specially: Irix cc passes
3485 them in registers where gcc sometimes puts them on the
3486 stack. For maximum compatibility, we will put them in
3488 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3489 && (len
% mips_abi_regsize (gdbarch
) != 0));
3491 /* Note: Floating-point values that didn't fit into an FP
3492 register are only written to memory. */
3495 /* Remember if the argument was written to the stack. */
3496 int stack_used_p
= 0;
3497 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3498 ? len
: mips_abi_regsize (gdbarch
));
3501 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3504 /* Write this portion of the argument to the stack. */
3505 if (argreg
> MIPS_LAST_ARG_REGNUM
3507 || fp_register_arg_p (typecode
, arg_type
))
3509 /* Should shorter than int integer values be
3510 promoted to int before being stored? */
3511 int longword_offset
= 0;
3514 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3516 if (mips_stack_argsize (gdbarch
) == 8
3517 && (typecode
== TYPE_CODE_INT
3518 || typecode
== TYPE_CODE_PTR
3519 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3520 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3521 else if ((typecode
== TYPE_CODE_STRUCT
3522 || typecode
== TYPE_CODE_UNION
)
3523 && (TYPE_LENGTH (arg_type
)
3524 < mips_stack_argsize (gdbarch
)))
3525 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3530 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3531 paddr_nz (stack_offset
));
3532 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3533 paddr_nz (longword_offset
));
3536 addr
= sp
+ stack_offset
+ longword_offset
;
3541 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3543 for (i
= 0; i
< partial_len
; i
++)
3545 fprintf_unfiltered (gdb_stdlog
, "%02x",
3549 write_memory (addr
, val
, partial_len
);
3552 /* Note!!! This is NOT an else clause. Odd sized
3553 structs may go thru BOTH paths. Floating point
3554 arguments will not. */
3555 /* Write this portion of the argument to a general
3556 purpose register. */
3557 if (argreg
<= MIPS_LAST_ARG_REGNUM
3558 && !fp_register_arg_p (typecode
, arg_type
))
3561 extract_unsigned_integer (val
, partial_len
);
3564 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3567 mips_abi_regsize (gdbarch
)));
3568 write_register (argreg
, regval
);
3575 /* Compute the the offset into the stack at which we
3576 will copy the next parameter.
3578 In the new EABI (and the NABI32), the stack_offset
3579 only needs to be adjusted when it has been used. */
3582 stack_offset
+= align_up (partial_len
,
3583 mips_stack_argsize (gdbarch
));
3587 fprintf_unfiltered (gdb_stdlog
, "\n");
3590 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3592 /* Return adjusted stack pointer. */
3596 /* Given a return value in `regbuf' with a type `valtype', extract and
3597 copy its value into `valbuf'. */
3600 mips_eabi_extract_return_value (struct type
*valtype
,
3601 char regbuf
[], char *valbuf
)
3603 struct return_value_word lo
;
3604 struct return_value_word hi
;
3605 return_value_location (valtype
, &hi
, &lo
);
3607 memcpy (valbuf
+ lo
.buf_offset
,
3608 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3609 lo
.reg_offset
, lo
.len
);
3612 memcpy (valbuf
+ hi
.buf_offset
,
3613 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3614 hi
.reg_offset
, hi
.len
);
3617 /* Given a return value in `valbuf' with a type `valtype', write it's
3618 value into the appropriate register. */
3621 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3623 char raw_buffer
[MAX_REGISTER_SIZE
];
3624 struct return_value_word lo
;
3625 struct return_value_word hi
;
3626 return_value_location (valtype
, &hi
, &lo
);
3628 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3629 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3630 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3631 raw_buffer
, register_size (current_gdbarch
,
3636 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3637 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3638 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3640 register_size (current_gdbarch
,
3645 /* N32/N64 ABI stuff. */
3648 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3649 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3650 int nargs
, struct value
**args
, CORE_ADDR sp
,
3651 int struct_return
, CORE_ADDR struct_addr
)
3657 int stack_offset
= 0;
3658 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3659 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3661 /* For shared libraries, "t9" needs to point at the function
3663 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3665 /* Set the return address register to point to the entry point of
3666 the program, where a breakpoint lies in wait. */
3667 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3669 /* First ensure that the stack and structure return address (if any)
3670 are properly aligned. The stack has to be at least 64-bit
3671 aligned even on 32-bit machines, because doubles must be 64-bit
3672 aligned. For n32 and n64, stack frames need to be 128-bit
3673 aligned, so we round to this widest known alignment. */
3675 sp
= align_down (sp
, 16);
3676 struct_addr
= align_down (struct_addr
, 16);
3678 /* Now make space on the stack for the args. */
3679 for (argnum
= 0; argnum
< nargs
; argnum
++)
3680 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3681 mips_stack_argsize (gdbarch
));
3682 sp
-= align_up (len
, 16);
3685 fprintf_unfiltered (gdb_stdlog
,
3686 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3687 paddr_nz (sp
), (long) align_up (len
, 16));
3689 /* Initialize the integer and float register pointers. */
3691 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3693 /* The struct_return pointer occupies the first parameter-passing reg. */
3697 fprintf_unfiltered (gdb_stdlog
,
3698 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3699 argreg
, paddr_nz (struct_addr
));
3700 write_register (argreg
++, struct_addr
);
3703 /* Now load as many as possible of the first arguments into
3704 registers, and push the rest onto the stack. Loop thru args
3705 from first to last. */
3706 for (argnum
= 0; argnum
< nargs
; argnum
++)
3709 struct value
*arg
= args
[argnum
];
3710 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3711 int len
= TYPE_LENGTH (arg_type
);
3712 enum type_code typecode
= TYPE_CODE (arg_type
);
3715 fprintf_unfiltered (gdb_stdlog
,
3716 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3717 argnum
+ 1, len
, (int) typecode
);
3719 val
= (char *) VALUE_CONTENTS (arg
);
3721 if (fp_register_arg_p (typecode
, arg_type
)
3722 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3724 /* This is a floating point value that fits entirely
3725 in a single register. */
3726 /* On 32 bit ABI's the float_argreg is further adjusted
3727 above to ensure that it is even register aligned. */
3728 LONGEST regval
= extract_unsigned_integer (val
, len
);
3730 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3731 float_argreg
, phex (regval
, len
));
3732 write_register (float_argreg
++, regval
);
3735 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3736 argreg
, phex (regval
, len
));
3737 write_register (argreg
, regval
);
3742 /* Copy the argument to general registers or the stack in
3743 register-sized pieces. Large arguments are split between
3744 registers and stack. */
3745 /* Note: structs whose size is not a multiple of
3746 mips_abi_regsize() are treated specially: Irix cc passes
3747 them in registers where gcc sometimes puts them on the
3748 stack. For maximum compatibility, we will put them in
3750 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3751 && (len
% mips_abi_regsize (gdbarch
) != 0));
3752 /* Note: Floating-point values that didn't fit into an FP
3753 register are only written to memory. */
3756 /* Rememer if the argument was written to the stack. */
3757 int stack_used_p
= 0;
3758 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3759 ? len
: mips_abi_regsize (gdbarch
));
3762 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3765 /* Write this portion of the argument to the stack. */
3766 if (argreg
> MIPS_LAST_ARG_REGNUM
3768 || fp_register_arg_p (typecode
, arg_type
))
3770 /* Should shorter than int integer values be
3771 promoted to int before being stored? */
3772 int longword_offset
= 0;
3775 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3777 if (mips_stack_argsize (gdbarch
) == 8
3778 && (typecode
== TYPE_CODE_INT
3779 || typecode
== TYPE_CODE_PTR
3780 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3781 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3786 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3787 paddr_nz (stack_offset
));
3788 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3789 paddr_nz (longword_offset
));
3792 addr
= sp
+ stack_offset
+ longword_offset
;
3797 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3799 for (i
= 0; i
< partial_len
; i
++)
3801 fprintf_unfiltered (gdb_stdlog
, "%02x",
3805 write_memory (addr
, val
, partial_len
);
3808 /* Note!!! This is NOT an else clause. Odd sized
3809 structs may go thru BOTH paths. Floating point
3810 arguments will not. */
3811 /* Write this portion of the argument to a general
3812 purpose register. */
3813 if (argreg
<= MIPS_LAST_ARG_REGNUM
3814 && !fp_register_arg_p (typecode
, arg_type
))
3817 extract_unsigned_integer (val
, partial_len
);
3819 /* A non-floating-point argument being passed in a
3820 general register. If a struct or union, and if
3821 the remaining length is smaller than the register
3822 size, we have to adjust the register value on
3825 It does not seem to be necessary to do the
3826 same for integral types.
3828 cagney/2001-07-23: gdb/179: Also, GCC, when
3829 outputting LE O32 with sizeof (struct) <
3830 mips_abi_regsize(), generates a left shift as
3831 part of storing the argument in a register a
3832 register (the left shift isn't generated when
3833 sizeof (struct) >= mips_abi_regsize()). Since
3834 it is quite possible that this is GCC
3835 contradicting the LE/O32 ABI, GDB has not been
3836 adjusted to accommodate this. Either someone
3837 needs to demonstrate that the LE/O32 ABI
3838 specifies such a left shift OR this new ABI gets
3839 identified as such and GDB gets tweaked
3842 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3843 && partial_len
< mips_abi_regsize (gdbarch
)
3844 && (typecode
== TYPE_CODE_STRUCT
||
3845 typecode
== TYPE_CODE_UNION
))
3846 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3850 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3853 mips_abi_regsize (gdbarch
)));
3854 write_register (argreg
, regval
);
3861 /* Compute the the offset into the stack at which we
3862 will copy the next parameter.
3864 In N32 (N64?), the stack_offset only needs to be
3865 adjusted when it has been used. */
3868 stack_offset
+= align_up (partial_len
,
3869 mips_stack_argsize (gdbarch
));
3873 fprintf_unfiltered (gdb_stdlog
, "\n");
3876 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3878 /* Return adjusted stack pointer. */
3882 static enum return_value_convention
3883 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3884 struct type
*type
, struct regcache
*regcache
,
3885 void *readbuf
, const void *writebuf
)
3887 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3888 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3889 || TYPE_CODE (type
) == TYPE_CODE_UNION
3890 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3891 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3892 return RETURN_VALUE_STRUCT_CONVENTION
;
3893 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3894 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3896 /* A floating-point value belongs in the least significant part
3899 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3900 mips_xfer_register (regcache
,
3901 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3903 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3904 return RETURN_VALUE_REGISTER_CONVENTION
;
3906 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3907 && TYPE_NFIELDS (type
) <= 2
3908 && TYPE_NFIELDS (type
) >= 1
3909 && ((TYPE_NFIELDS (type
) == 1
3910 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3912 || (TYPE_NFIELDS (type
) == 2
3913 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3915 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3917 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3919 /* A struct that contains one or two floats. Each value is part
3920 in the least significant part of their floating point
3924 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3925 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3927 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3930 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3932 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3933 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3934 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3936 return RETURN_VALUE_REGISTER_CONVENTION
;
3938 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3939 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3941 /* A structure or union. Extract the left justified value,
3942 regardless of the byte order. I.e. DO NOT USE
3946 for (offset
= 0, regnum
= V0_REGNUM
;
3947 offset
< TYPE_LENGTH (type
);
3948 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3950 int xfer
= register_size (current_gdbarch
, regnum
);
3951 if (offset
+ xfer
> TYPE_LENGTH (type
))
3952 xfer
= TYPE_LENGTH (type
) - offset
;
3954 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3955 offset
, xfer
, regnum
);
3956 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3957 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3959 return RETURN_VALUE_REGISTER_CONVENTION
;
3963 /* A scalar extract each part but least-significant-byte
3967 for (offset
= 0, regnum
= V0_REGNUM
;
3968 offset
< TYPE_LENGTH (type
);
3969 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3971 int xfer
= register_size (current_gdbarch
, regnum
);
3972 if (offset
+ xfer
> TYPE_LENGTH (type
))
3973 xfer
= TYPE_LENGTH (type
) - offset
;
3975 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3976 offset
, xfer
, regnum
);
3977 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3978 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3980 return RETURN_VALUE_REGISTER_CONVENTION
;
3984 /* O32 ABI stuff. */
3987 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3988 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3989 int nargs
, struct value
**args
, CORE_ADDR sp
,
3990 int struct_return
, CORE_ADDR struct_addr
)
3996 int stack_offset
= 0;
3997 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3998 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4000 /* For shared libraries, "t9" needs to point at the function
4002 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4004 /* Set the return address register to point to the entry point of
4005 the program, where a breakpoint lies in wait. */
4006 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4008 /* First ensure that the stack and structure return address (if any)
4009 are properly aligned. The stack has to be at least 64-bit
4010 aligned even on 32-bit machines, because doubles must be 64-bit
4011 aligned. For n32 and n64, stack frames need to be 128-bit
4012 aligned, so we round to this widest known alignment. */
4014 sp
= align_down (sp
, 16);
4015 struct_addr
= align_down (struct_addr
, 16);
4017 /* Now make space on the stack for the args. */
4018 for (argnum
= 0; argnum
< nargs
; argnum
++)
4019 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4020 mips_stack_argsize (gdbarch
));
4021 sp
-= align_up (len
, 16);
4024 fprintf_unfiltered (gdb_stdlog
,
4025 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
4026 paddr_nz (sp
), (long) align_up (len
, 16));
4028 /* Initialize the integer and float register pointers. */
4030 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4032 /* The struct_return pointer occupies the first parameter-passing reg. */
4036 fprintf_unfiltered (gdb_stdlog
,
4037 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
4038 argreg
, paddr_nz (struct_addr
));
4039 write_register (argreg
++, struct_addr
);
4040 stack_offset
+= mips_stack_argsize (gdbarch
);
4043 /* Now load as many as possible of the first arguments into
4044 registers, and push the rest onto the stack. Loop thru args
4045 from first to last. */
4046 for (argnum
= 0; argnum
< nargs
; argnum
++)
4049 struct value
*arg
= args
[argnum
];
4050 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4051 int len
= TYPE_LENGTH (arg_type
);
4052 enum type_code typecode
= TYPE_CODE (arg_type
);
4055 fprintf_unfiltered (gdb_stdlog
,
4056 "mips_o32_push_dummy_call: %d len=%d type=%d",
4057 argnum
+ 1, len
, (int) typecode
);
4059 val
= (char *) VALUE_CONTENTS (arg
);
4061 /* 32-bit ABIs always start floating point arguments in an
4062 even-numbered floating point register. Round the FP register
4063 up before the check to see if there are any FP registers
4064 left. O32/O64 targets also pass the FP in the integer
4065 registers so also round up normal registers. */
4066 if (mips_abi_regsize (gdbarch
) < 8
4067 && fp_register_arg_p (typecode
, arg_type
))
4069 if ((float_argreg
& 1))
4073 /* Floating point arguments passed in registers have to be
4074 treated specially. On 32-bit architectures, doubles
4075 are passed in register pairs; the even register gets
4076 the low word, and the odd register gets the high word.
4077 On O32/O64, the first two floating point arguments are
4078 also copied to general registers, because MIPS16 functions
4079 don't use float registers for arguments. This duplication of
4080 arguments in general registers can't hurt non-MIPS16 functions
4081 because those registers are normally skipped. */
4083 if (fp_register_arg_p (typecode
, arg_type
)
4084 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4086 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4088 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4089 unsigned long regval
;
4091 /* Write the low word of the double to the even register(s). */
4092 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4094 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4095 float_argreg
, phex (regval
, 4));
4096 write_register (float_argreg
++, regval
);
4098 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4099 argreg
, phex (regval
, 4));
4100 write_register (argreg
++, regval
);
4102 /* Write the high word of the double to the odd register(s). */
4103 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4105 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4106 float_argreg
, phex (regval
, 4));
4107 write_register (float_argreg
++, regval
);
4110 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4111 argreg
, phex (regval
, 4));
4112 write_register (argreg
++, regval
);
4116 /* This is a floating point value that fits entirely
4117 in a single register. */
4118 /* On 32 bit ABI's the float_argreg is further adjusted
4119 above to ensure that it is even register aligned. */
4120 LONGEST regval
= extract_unsigned_integer (val
, len
);
4122 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4123 float_argreg
, phex (regval
, len
));
4124 write_register (float_argreg
++, regval
);
4125 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4126 registers for each argument. The below is (my
4127 guess) to ensure that the corresponding integer
4128 register has reserved the same space. */
4130 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4131 argreg
, phex (regval
, len
));
4132 write_register (argreg
, regval
);
4133 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4135 /* Reserve space for the FP register. */
4136 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4140 /* Copy the argument to general registers or the stack in
4141 register-sized pieces. Large arguments are split between
4142 registers and stack. */
4143 /* Note: structs whose size is not a multiple of
4144 mips_abi_regsize() are treated specially: Irix cc passes
4145 them in registers where gcc sometimes puts them on the
4146 stack. For maximum compatibility, we will put them in
4148 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4149 && (len
% mips_abi_regsize (gdbarch
) != 0));
4150 /* Structures should be aligned to eight bytes (even arg registers)
4151 on MIPS_ABI_O32, if their first member has double precision. */
4152 if (mips_abi_regsize (gdbarch
) < 8
4153 && mips_type_needs_double_align (arg_type
))
4158 /* Note: Floating-point values that didn't fit into an FP
4159 register are only written to memory. */
4162 /* Remember if the argument was written to the stack. */
4163 int stack_used_p
= 0;
4164 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4165 ? len
: mips_abi_regsize (gdbarch
));
4168 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4171 /* Write this portion of the argument to the stack. */
4172 if (argreg
> MIPS_LAST_ARG_REGNUM
4174 || fp_register_arg_p (typecode
, arg_type
))
4176 /* Should shorter than int integer values be
4177 promoted to int before being stored? */
4178 int longword_offset
= 0;
4181 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4183 if (mips_stack_argsize (gdbarch
) == 8
4184 && (typecode
== TYPE_CODE_INT
4185 || typecode
== TYPE_CODE_PTR
4186 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4187 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4192 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4193 paddr_nz (stack_offset
));
4194 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4195 paddr_nz (longword_offset
));
4198 addr
= sp
+ stack_offset
+ longword_offset
;
4203 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4205 for (i
= 0; i
< partial_len
; i
++)
4207 fprintf_unfiltered (gdb_stdlog
, "%02x",
4211 write_memory (addr
, val
, partial_len
);
4214 /* Note!!! This is NOT an else clause. Odd sized
4215 structs may go thru BOTH paths. Floating point
4216 arguments will not. */
4217 /* Write this portion of the argument to a general
4218 purpose register. */
4219 if (argreg
<= MIPS_LAST_ARG_REGNUM
4220 && !fp_register_arg_p (typecode
, arg_type
))
4222 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4223 /* Value may need to be sign extended, because
4224 mips_isa_regsize() != mips_abi_regsize(). */
4226 /* A non-floating-point argument being passed in a
4227 general register. If a struct or union, and if
4228 the remaining length is smaller than the register
4229 size, we have to adjust the register value on
4232 It does not seem to be necessary to do the
4233 same for integral types.
4235 Also don't do this adjustment on O64 binaries.
4237 cagney/2001-07-23: gdb/179: Also, GCC, when
4238 outputting LE O32 with sizeof (struct) <
4239 mips_abi_regsize(), generates a left shift as
4240 part of storing the argument in a register a
4241 register (the left shift isn't generated when
4242 sizeof (struct) >= mips_abi_regsize()). Since
4243 it is quite possible that this is GCC
4244 contradicting the LE/O32 ABI, GDB has not been
4245 adjusted to accommodate this. Either someone
4246 needs to demonstrate that the LE/O32 ABI
4247 specifies such a left shift OR this new ABI gets
4248 identified as such and GDB gets tweaked
4251 if (mips_abi_regsize (gdbarch
) < 8
4252 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4253 && partial_len
< mips_abi_regsize (gdbarch
)
4254 && (typecode
== TYPE_CODE_STRUCT
||
4255 typecode
== TYPE_CODE_UNION
))
4256 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4260 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4263 mips_abi_regsize (gdbarch
)));
4264 write_register (argreg
, regval
);
4267 /* Prevent subsequent floating point arguments from
4268 being passed in floating point registers. */
4269 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4275 /* Compute the the offset into the stack at which we
4276 will copy the next parameter.
4278 In older ABIs, the caller reserved space for
4279 registers that contained arguments. This was loosely
4280 refered to as their "home". Consequently, space is
4281 always allocated. */
4283 stack_offset
+= align_up (partial_len
,
4284 mips_stack_argsize (gdbarch
));
4288 fprintf_unfiltered (gdb_stdlog
, "\n");
4291 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4293 /* Return adjusted stack pointer. */
4297 static enum return_value_convention
4298 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4299 struct regcache
*regcache
,
4300 void *readbuf
, const void *writebuf
)
4302 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4304 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4305 || TYPE_CODE (type
) == TYPE_CODE_UNION
4306 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4307 return RETURN_VALUE_STRUCT_CONVENTION
;
4308 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4309 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4311 /* A single-precision floating-point value. It fits in the
4312 least significant part of FP0. */
4314 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4315 mips_xfer_register (regcache
,
4316 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4318 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4319 return RETURN_VALUE_REGISTER_CONVENTION
;
4321 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4322 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4324 /* A double-precision floating-point value. The most
4325 significant part goes in FP1, and the least significant in
4328 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4329 switch (TARGET_BYTE_ORDER
)
4331 case BFD_ENDIAN_LITTLE
:
4332 mips_xfer_register (regcache
,
4333 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4334 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4335 mips_xfer_register (regcache
,
4336 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4337 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4339 case BFD_ENDIAN_BIG
:
4340 mips_xfer_register (regcache
,
4341 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4342 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4343 mips_xfer_register (regcache
,
4344 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4345 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4348 internal_error (__FILE__
, __LINE__
, "bad switch");
4350 return RETURN_VALUE_REGISTER_CONVENTION
;
4353 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4354 && TYPE_NFIELDS (type
) <= 2
4355 && TYPE_NFIELDS (type
) >= 1
4356 && ((TYPE_NFIELDS (type
) == 1
4357 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4359 || (TYPE_NFIELDS (type
) == 2
4360 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4362 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4364 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4366 /* A struct that contains one or two floats. Each value is part
4367 in the least significant part of their floating point
4369 bfd_byte reg
[MAX_REGISTER_SIZE
];
4372 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4373 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4375 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4378 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4380 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4381 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4382 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4384 return RETURN_VALUE_REGISTER_CONVENTION
;
4388 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4389 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4391 /* A structure or union. Extract the left justified value,
4392 regardless of the byte order. I.e. DO NOT USE
4396 for (offset
= 0, regnum
= V0_REGNUM
;
4397 offset
< TYPE_LENGTH (type
);
4398 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4400 int xfer
= register_size (current_gdbarch
, regnum
);
4401 if (offset
+ xfer
> TYPE_LENGTH (type
))
4402 xfer
= TYPE_LENGTH (type
) - offset
;
4404 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4405 offset
, xfer
, regnum
);
4406 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4407 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4409 return RETURN_VALUE_REGISTER_CONVENTION
;
4414 /* A scalar extract each part but least-significant-byte
4415 justified. o32 thinks registers are 4 byte, regardless of
4416 the ISA. mips_stack_argsize controls this. */
4419 for (offset
= 0, regnum
= V0_REGNUM
;
4420 offset
< TYPE_LENGTH (type
);
4421 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4423 int xfer
= mips_stack_argsize (gdbarch
);
4424 if (offset
+ xfer
> TYPE_LENGTH (type
))
4425 xfer
= TYPE_LENGTH (type
) - offset
;
4427 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4428 offset
, xfer
, regnum
);
4429 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4430 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4432 return RETURN_VALUE_REGISTER_CONVENTION
;
4436 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4440 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4441 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4443 struct value
**args
, CORE_ADDR sp
,
4444 int struct_return
, CORE_ADDR struct_addr
)
4450 int stack_offset
= 0;
4451 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4452 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4454 /* For shared libraries, "t9" needs to point at the function
4456 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4458 /* Set the return address register to point to the entry point of
4459 the program, where a breakpoint lies in wait. */
4460 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4462 /* First ensure that the stack and structure return address (if any)
4463 are properly aligned. The stack has to be at least 64-bit
4464 aligned even on 32-bit machines, because doubles must be 64-bit
4465 aligned. For n32 and n64, stack frames need to be 128-bit
4466 aligned, so we round to this widest known alignment. */
4468 sp
= align_down (sp
, 16);
4469 struct_addr
= align_down (struct_addr
, 16);
4471 /* Now make space on the stack for the args. */
4472 for (argnum
= 0; argnum
< nargs
; argnum
++)
4473 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4474 mips_stack_argsize (gdbarch
));
4475 sp
-= align_up (len
, 16);
4478 fprintf_unfiltered (gdb_stdlog
,
4479 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4480 paddr_nz (sp
), (long) align_up (len
, 16));
4482 /* Initialize the integer and float register pointers. */
4484 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4486 /* The struct_return pointer occupies the first parameter-passing reg. */
4490 fprintf_unfiltered (gdb_stdlog
,
4491 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4492 argreg
, paddr_nz (struct_addr
));
4493 write_register (argreg
++, struct_addr
);
4494 stack_offset
+= mips_stack_argsize (gdbarch
);
4497 /* Now load as many as possible of the first arguments into
4498 registers, and push the rest onto the stack. Loop thru args
4499 from first to last. */
4500 for (argnum
= 0; argnum
< nargs
; argnum
++)
4503 struct value
*arg
= args
[argnum
];
4504 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4505 int len
= TYPE_LENGTH (arg_type
);
4506 enum type_code typecode
= TYPE_CODE (arg_type
);
4509 fprintf_unfiltered (gdb_stdlog
,
4510 "mips_o64_push_dummy_call: %d len=%d type=%d",
4511 argnum
+ 1, len
, (int) typecode
);
4513 val
= (char *) VALUE_CONTENTS (arg
);
4515 /* 32-bit ABIs always start floating point arguments in an
4516 even-numbered floating point register. Round the FP register
4517 up before the check to see if there are any FP registers
4518 left. O32/O64 targets also pass the FP in the integer
4519 registers so also round up normal registers. */
4520 if (mips_abi_regsize (gdbarch
) < 8
4521 && fp_register_arg_p (typecode
, arg_type
))
4523 if ((float_argreg
& 1))
4527 /* Floating point arguments passed in registers have to be
4528 treated specially. On 32-bit architectures, doubles
4529 are passed in register pairs; the even register gets
4530 the low word, and the odd register gets the high word.
4531 On O32/O64, the first two floating point arguments are
4532 also copied to general registers, because MIPS16 functions
4533 don't use float registers for arguments. This duplication of
4534 arguments in general registers can't hurt non-MIPS16 functions
4535 because those registers are normally skipped. */
4537 if (fp_register_arg_p (typecode
, arg_type
)
4538 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4540 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4542 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4543 unsigned long regval
;
4545 /* Write the low word of the double to the even register(s). */
4546 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4548 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4549 float_argreg
, phex (regval
, 4));
4550 write_register (float_argreg
++, regval
);
4552 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4553 argreg
, phex (regval
, 4));
4554 write_register (argreg
++, regval
);
4556 /* Write the high word of the double to the odd register(s). */
4557 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4559 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4560 float_argreg
, phex (regval
, 4));
4561 write_register (float_argreg
++, regval
);
4564 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4565 argreg
, phex (regval
, 4));
4566 write_register (argreg
++, regval
);
4570 /* This is a floating point value that fits entirely
4571 in a single register. */
4572 /* On 32 bit ABI's the float_argreg is further adjusted
4573 above to ensure that it is even register aligned. */
4574 LONGEST regval
= extract_unsigned_integer (val
, len
);
4576 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4577 float_argreg
, phex (regval
, len
));
4578 write_register (float_argreg
++, regval
);
4579 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4580 registers for each argument. The below is (my
4581 guess) to ensure that the corresponding integer
4582 register has reserved the same space. */
4584 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4585 argreg
, phex (regval
, len
));
4586 write_register (argreg
, regval
);
4587 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4589 /* Reserve space for the FP register. */
4590 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4594 /* Copy the argument to general registers or the stack in
4595 register-sized pieces. Large arguments are split between
4596 registers and stack. */
4597 /* Note: structs whose size is not a multiple of
4598 mips_abi_regsize() are treated specially: Irix cc passes
4599 them in registers where gcc sometimes puts them on the
4600 stack. For maximum compatibility, we will put them in
4602 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4603 && (len
% mips_abi_regsize (gdbarch
) != 0));
4604 /* Structures should be aligned to eight bytes (even arg registers)
4605 on MIPS_ABI_O32, if their first member has double precision. */
4606 if (mips_abi_regsize (gdbarch
) < 8
4607 && mips_type_needs_double_align (arg_type
))
4612 /* Note: Floating-point values that didn't fit into an FP
4613 register are only written to memory. */
4616 /* Remember if the argument was written to the stack. */
4617 int stack_used_p
= 0;
4618 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4619 ? len
: mips_abi_regsize (gdbarch
));
4622 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4625 /* Write this portion of the argument to the stack. */
4626 if (argreg
> MIPS_LAST_ARG_REGNUM
4628 || fp_register_arg_p (typecode
, arg_type
))
4630 /* Should shorter than int integer values be
4631 promoted to int before being stored? */
4632 int longword_offset
= 0;
4635 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4637 if (mips_stack_argsize (gdbarch
) == 8
4638 && (typecode
== TYPE_CODE_INT
4639 || typecode
== TYPE_CODE_PTR
4640 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4641 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4646 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4647 paddr_nz (stack_offset
));
4648 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4649 paddr_nz (longword_offset
));
4652 addr
= sp
+ stack_offset
+ longword_offset
;
4657 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4659 for (i
= 0; i
< partial_len
; i
++)
4661 fprintf_unfiltered (gdb_stdlog
, "%02x",
4665 write_memory (addr
, val
, partial_len
);
4668 /* Note!!! This is NOT an else clause. Odd sized
4669 structs may go thru BOTH paths. Floating point
4670 arguments will not. */
4671 /* Write this portion of the argument to a general
4672 purpose register. */
4673 if (argreg
<= MIPS_LAST_ARG_REGNUM
4674 && !fp_register_arg_p (typecode
, arg_type
))
4676 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4677 /* Value may need to be sign extended, because
4678 mips_isa_regsize() != mips_abi_regsize(). */
4680 /* A non-floating-point argument being passed in a
4681 general register. If a struct or union, and if
4682 the remaining length is smaller than the register
4683 size, we have to adjust the register value on
4686 It does not seem to be necessary to do the
4687 same for integral types.
4689 Also don't do this adjustment on O64 binaries.
4691 cagney/2001-07-23: gdb/179: Also, GCC, when
4692 outputting LE O32 with sizeof (struct) <
4693 mips_abi_regsize(), generates a left shift as
4694 part of storing the argument in a register a
4695 register (the left shift isn't generated when
4696 sizeof (struct) >= mips_abi_regsize()). Since
4697 it is quite possible that this is GCC
4698 contradicting the LE/O32 ABI, GDB has not been
4699 adjusted to accommodate this. Either someone
4700 needs to demonstrate that the LE/O32 ABI
4701 specifies such a left shift OR this new ABI gets
4702 identified as such and GDB gets tweaked
4705 if (mips_abi_regsize (gdbarch
) < 8
4706 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4707 && partial_len
< mips_abi_regsize (gdbarch
)
4708 && (typecode
== TYPE_CODE_STRUCT
||
4709 typecode
== TYPE_CODE_UNION
))
4710 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4714 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4717 mips_abi_regsize (gdbarch
)));
4718 write_register (argreg
, regval
);
4721 /* Prevent subsequent floating point arguments from
4722 being passed in floating point registers. */
4723 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4729 /* Compute the the offset into the stack at which we
4730 will copy the next parameter.
4732 In older ABIs, the caller reserved space for
4733 registers that contained arguments. This was loosely
4734 refered to as their "home". Consequently, space is
4735 always allocated. */
4737 stack_offset
+= align_up (partial_len
,
4738 mips_stack_argsize (gdbarch
));
4742 fprintf_unfiltered (gdb_stdlog
, "\n");
4745 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4747 /* Return adjusted stack pointer. */
4752 mips_o64_extract_return_value (struct type
*valtype
,
4753 char regbuf
[], char *valbuf
)
4755 struct return_value_word lo
;
4756 struct return_value_word hi
;
4757 return_value_location (valtype
, &hi
, &lo
);
4759 memcpy (valbuf
+ lo
.buf_offset
,
4760 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4761 lo
.reg_offset
, lo
.len
);
4764 memcpy (valbuf
+ hi
.buf_offset
,
4765 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4766 hi
.reg_offset
, hi
.len
);
4770 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4772 char raw_buffer
[MAX_REGISTER_SIZE
];
4773 struct return_value_word lo
;
4774 struct return_value_word hi
;
4775 return_value_location (valtype
, &hi
, &lo
);
4777 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4778 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4779 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4780 raw_buffer
, register_size (current_gdbarch
,
4785 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4786 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4787 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4789 register_size (current_gdbarch
,
4794 /* Floating point register management.
4796 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4797 64bit operations, these early MIPS cpus treat fp register pairs
4798 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4799 registers and offer a compatibility mode that emulates the MIPS2 fp
4800 model. When operating in MIPS2 fp compat mode, later cpu's split
4801 double precision floats into two 32-bit chunks and store them in
4802 consecutive fp regs. To display 64-bit floats stored in this
4803 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4804 Throw in user-configurable endianness and you have a real mess.
4806 The way this works is:
4807 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4808 double-precision value will be split across two logical registers.
4809 The lower-numbered logical register will hold the low-order bits,
4810 regardless of the processor's endianness.
4811 - If we are on a 64-bit processor, and we are looking for a
4812 single-precision value, it will be in the low ordered bits
4813 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4814 save slot in memory.
4815 - If we are in 64-bit mode, everything is straightforward.
4817 Note that this code only deals with "live" registers at the top of the
4818 stack. We will attempt to deal with saved registers later, when
4819 the raw/cooked register interface is in place. (We need a general
4820 interface that can deal with dynamic saved register sizes -- fp
4821 regs could be 32 bits wide in one frame and 64 on the frame above
4824 static struct type
*
4825 mips_float_register_type (void)
4827 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4828 return builtin_type_ieee_single_big
;
4830 return builtin_type_ieee_single_little
;
4833 static struct type
*
4834 mips_double_register_type (void)
4836 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4837 return builtin_type_ieee_double_big
;
4839 return builtin_type_ieee_double_little
;
4842 /* Copy a 32-bit single-precision value from the current frame
4843 into rare_buffer. */
4846 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4849 int raw_size
= register_size (current_gdbarch
, regno
);
4850 char *raw_buffer
= alloca (raw_size
);
4852 if (!frame_register_read (frame
, regno
, raw_buffer
))
4853 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4856 /* We have a 64-bit value for this register. Find the low-order
4860 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4865 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4869 memcpy (rare_buffer
, raw_buffer
, 4);
4873 /* Copy a 64-bit double-precision value from the current frame into
4874 rare_buffer. This may include getting half of it from the next
4878 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4881 int raw_size
= register_size (current_gdbarch
, regno
);
4883 if (raw_size
== 8 && !mips2_fp_compat ())
4885 /* We have a 64-bit value for this register, and we should use
4887 if (!frame_register_read (frame
, regno
, rare_buffer
))
4888 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4892 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4893 internal_error (__FILE__
, __LINE__
,
4894 "mips_read_fp_register_double: bad access to "
4895 "odd-numbered FP register");
4897 /* mips_read_fp_register_single will find the correct 32 bits from
4899 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4901 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4902 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4906 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4907 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4913 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4915 { /* do values for FP (float) regs */
4917 double doub
, flt1
; /* doubles extracted from raw hex data */
4921 (char *) alloca (2 *
4922 register_size (current_gdbarch
,
4923 mips_regnum (current_gdbarch
)->fp0
));
4925 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4926 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4929 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4931 /* 4-byte registers: Print hex and floating. Also print even
4932 numbered registers as doubles. */
4933 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4934 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4936 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4939 fprintf_filtered (file
, " flt: ");
4941 fprintf_filtered (file
, " <invalid float> ");
4943 fprintf_filtered (file
, "%-17.9g", flt1
);
4945 if (regnum
% 2 == 0)
4947 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4948 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4951 fprintf_filtered (file
, " dbl: ");
4953 fprintf_filtered (file
, "<invalid double>");
4955 fprintf_filtered (file
, "%-24.17g", doub
);
4960 /* Eight byte registers: print each one as hex, float and double. */
4961 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4962 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4964 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4965 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4968 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4971 fprintf_filtered (file
, " flt: ");
4973 fprintf_filtered (file
, "<invalid float>");
4975 fprintf_filtered (file
, "%-17.9g", flt1
);
4977 fprintf_filtered (file
, " dbl: ");
4979 fprintf_filtered (file
, "<invalid double>");
4981 fprintf_filtered (file
, "%-24.17g", doub
);
4986 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4987 int regnum
, int all
)
4989 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4990 char raw_buffer
[MAX_REGISTER_SIZE
];
4993 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4995 mips_print_fp_register (file
, frame
, regnum
);
4999 /* Get the data in raw format. */
5000 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5002 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
5006 fputs_filtered (REGISTER_NAME (regnum
), file
);
5008 /* The problem with printing numeric register names (r26, etc.) is that
5009 the user can't use them on input. Probably the best solution is to
5010 fix it so that either the numeric or the funky (a2, etc.) names
5011 are accepted on input. */
5012 if (regnum
< MIPS_NUMREGS
)
5013 fprintf_filtered (file
, "(r%d): ", regnum
);
5015 fprintf_filtered (file
, ": ");
5017 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5019 register_size (current_gdbarch
,
5020 regnum
) - register_size (current_gdbarch
, regnum
);
5024 print_scalar_formatted (raw_buffer
+ offset
,
5025 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
5029 /* Replacement for generic do_registers_info.
5030 Print regs in pretty columns. */
5033 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5036 fprintf_filtered (file
, " ");
5037 mips_print_fp_register (file
, frame
, regnum
);
5038 fprintf_filtered (file
, "\n");
5043 /* Print a row's worth of GP (int) registers, with name labels above */
5046 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5049 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5050 /* do values for GP (int) regs */
5051 char raw_buffer
[MAX_REGISTER_SIZE
];
5052 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
5056 /* For GP registers, we print a separate row of names above the vals */
5057 fprintf_filtered (file
, " ");
5058 for (col
= 0, regnum
= start_regnum
;
5059 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5061 if (*REGISTER_NAME (regnum
) == '\0')
5062 continue; /* unused register */
5063 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5065 break; /* end the row: reached FP register */
5066 fprintf_filtered (file
,
5067 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
5068 REGISTER_NAME (regnum
));
5071 /* print the R0 to R31 names */
5072 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
5073 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
5075 fprintf_filtered (file
, "\n ");
5077 /* now print the values in hex, 4 or 8 to the row */
5078 for (col
= 0, regnum
= start_regnum
;
5079 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5081 if (*REGISTER_NAME (regnum
) == '\0')
5082 continue; /* unused register */
5083 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5085 break; /* end row: reached FP register */
5086 /* OK: get the data in raw format. */
5087 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5088 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
5089 /* pad small registers */
5091 byte
< (mips_abi_regsize (current_gdbarch
)
5092 - register_size (current_gdbarch
, regnum
)); byte
++)
5093 printf_filtered (" ");
5094 /* Now print the register value in hex, endian order. */
5095 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5097 register_size (current_gdbarch
,
5098 regnum
) - register_size (current_gdbarch
, regnum
);
5099 byte
< register_size (current_gdbarch
, regnum
); byte
++)
5100 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5102 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
5104 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5105 fprintf_filtered (file
, " ");
5108 if (col
> 0) /* ie. if we actually printed anything... */
5109 fprintf_filtered (file
, "\n");
5114 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
5117 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5118 struct frame_info
*frame
, int regnum
, int all
)
5120 if (regnum
!= -1) /* do one specified register */
5122 gdb_assert (regnum
>= NUM_REGS
);
5123 if (*(REGISTER_NAME (regnum
)) == '\0')
5124 error ("Not a valid register for the current processor type");
5126 mips_print_register (file
, frame
, regnum
, 0);
5127 fprintf_filtered (file
, "\n");
5130 /* do all (or most) registers */
5133 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
5135 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5138 if (all
) /* true for "INFO ALL-REGISTERS" command */
5139 regnum
= print_fp_register_row (file
, frame
, regnum
);
5141 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5144 regnum
= print_gp_register_row (file
, frame
, regnum
);
5149 /* Is this a branch with a delay slot? */
5151 static int is_delayed (unsigned long);
5154 is_delayed (unsigned long insn
)
5157 for (i
= 0; i
< NUMOPCODES
; ++i
)
5158 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5159 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5161 return (i
< NUMOPCODES
5162 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5163 | INSN_COND_BRANCH_DELAY
5164 | INSN_COND_BRANCH_LIKELY
)));
5168 mips_step_skips_delay (CORE_ADDR pc
)
5170 char buf
[MIPS_INSTLEN
];
5172 /* There is no branch delay slot on MIPS16. */
5173 if (pc_is_mips16 (pc
))
5176 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5177 /* If error reading memory, guess that it is not a delayed branch. */
5179 return is_delayed ((unsigned long)
5180 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5183 /* Skip the PC past function prologue instructions (32-bit version).
5184 This is a helper function for mips_skip_prologue. */
5187 mips32_skip_prologue (CORE_ADDR pc
)
5191 int seen_sp_adjust
= 0;
5192 int load_immediate_bytes
= 0;
5194 /* Find an upper bound on the prologue. */
5195 end_pc
= skip_prologue_using_sal (pc
);
5197 end_pc
= pc
+ 100; /* Magic. */
5199 /* Skip the typical prologue instructions. These are the stack adjustment
5200 instruction and the instructions that save registers on the stack
5201 or in the gcc frame. */
5202 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5204 unsigned long high_word
;
5206 inst
= mips_fetch_instruction (pc
);
5207 high_word
= (inst
>> 16) & 0xffff;
5209 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5210 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5212 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5213 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5215 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5216 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5217 && (inst
& 0x001F0000)) /* reg != $zero */
5220 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5222 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5224 continue; /* reg != $zero */
5226 /* move $s8,$sp. With different versions of gas this will be either
5227 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5228 Accept any one of these. */
5229 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5232 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5234 else if (high_word
== 0x3c1c) /* lui $gp,n */
5236 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5238 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5239 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5241 /* The following instructions load $at or $t0 with an immediate
5242 value in preparation for a stack adjustment via
5243 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5244 a local variable, so we accept them only before a stack adjustment
5245 instruction was seen. */
5246 else if (!seen_sp_adjust
)
5248 if (high_word
== 0x3c01 || /* lui $at,n */
5249 high_word
== 0x3c08) /* lui $t0,n */
5251 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5254 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5255 high_word
== 0x3508 || /* ori $t0,$t0,n */
5256 high_word
== 0x3401 || /* ori $at,$zero,n */
5257 high_word
== 0x3408) /* ori $t0,$zero,n */
5259 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5269 /* In a frameless function, we might have incorrectly
5270 skipped some load immediate instructions. Undo the skipping
5271 if the load immediate was not followed by a stack adjustment. */
5272 if (load_immediate_bytes
&& !seen_sp_adjust
)
5273 pc
-= load_immediate_bytes
;
5277 /* Skip the PC past function prologue instructions (16-bit version).
5278 This is a helper function for mips_skip_prologue. */
5281 mips16_skip_prologue (CORE_ADDR pc
)
5284 int extend_bytes
= 0;
5285 int prev_extend_bytes
;
5287 /* Table of instructions likely to be found in a function prologue. */
5290 unsigned short inst
;
5291 unsigned short mask
;
5297 , /* addiu $sp,offset */
5300 , /* daddiu $sp,offset */
5303 , /* sw reg,n($sp) */
5306 , /* sd reg,n($sp) */
5309 , /* sw $ra,n($sp) */
5312 , /* sd $ra,n($sp) */
5318 , /* sw $a0-$a3,n($s1) */
5321 , /* move reg,$a0-$a3 */
5324 , /* entry pseudo-op */
5327 , /* addiu $s1,$sp,n */
5329 0, 0} /* end of table marker */
5332 /* Find an upper bound on the prologue. */
5333 end_pc
= skip_prologue_using_sal (pc
);
5335 end_pc
= pc
+ 100; /* Magic. */
5337 /* Skip the typical prologue instructions. These are the stack adjustment
5338 instruction and the instructions that save registers on the stack
5339 or in the gcc frame. */
5340 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5342 unsigned short inst
;
5345 inst
= mips_fetch_instruction (pc
);
5347 /* Normally we ignore an extend instruction. However, if it is
5348 not followed by a valid prologue instruction, we must adjust
5349 the pc back over the extend so that it won't be considered
5350 part of the prologue. */
5351 if ((inst
& 0xf800) == 0xf000) /* extend */
5353 extend_bytes
= MIPS16_INSTLEN
;
5356 prev_extend_bytes
= extend_bytes
;
5359 /* Check for other valid prologue instructions besides extend. */
5360 for (i
= 0; table
[i
].mask
!= 0; i
++)
5361 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5363 if (table
[i
].mask
!= 0) /* it was in table? */
5364 continue; /* ignore it */
5368 /* Return the current pc, adjusted backwards by 2 if
5369 the previous instruction was an extend. */
5370 return pc
- prev_extend_bytes
;
5376 /* To skip prologues, I use this predicate. Returns either PC itself
5377 if the code at PC does not look like a function prologue; otherwise
5378 returns an address that (if we're lucky) follows the prologue. If
5379 LENIENT, then we must skip everything which is involved in setting
5380 up the frame (it's OK to skip more, just so long as we don't skip
5381 anything which might clobber the registers which are being saved.
5382 We must skip more in the case where part of the prologue is in the
5383 delay slot of a non-prologue instruction). */
5386 mips_skip_prologue (CORE_ADDR pc
)
5388 /* See if we can determine the end of the prologue via the symbol table.
5389 If so, then return either PC, or the PC after the prologue, whichever
5392 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
5394 if (post_prologue_pc
!= 0)
5395 return max (pc
, post_prologue_pc
);
5397 /* Can't determine prologue from the symbol table, need to examine
5400 if (pc_is_mips16 (pc
))
5401 return mips16_skip_prologue (pc
);
5403 return mips32_skip_prologue (pc
);
5406 /* Root of all "set mips "/"show mips " commands. This will eventually be
5407 used for all MIPS-specific commands. */
5410 show_mips_command (char *args
, int from_tty
)
5412 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5416 set_mips_command (char *args
, int from_tty
)
5419 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5420 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5423 /* Commands to show/set the MIPS FPU type. */
5426 show_mipsfpu_command (char *args
, int from_tty
)
5429 switch (MIPS_FPU_TYPE
)
5431 case MIPS_FPU_SINGLE
:
5432 fpu
= "single-precision";
5434 case MIPS_FPU_DOUBLE
:
5435 fpu
= "double-precision";
5438 fpu
= "absent (none)";
5441 internal_error (__FILE__
, __LINE__
, "bad switch");
5443 if (mips_fpu_type_auto
)
5445 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5449 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5454 set_mipsfpu_command (char *args
, int from_tty
)
5457 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5458 show_mipsfpu_command (args
, from_tty
);
5462 set_mipsfpu_single_command (char *args
, int from_tty
)
5464 struct gdbarch_info info
;
5465 gdbarch_info_init (&info
);
5466 mips_fpu_type
= MIPS_FPU_SINGLE
;
5467 mips_fpu_type_auto
= 0;
5468 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5469 instead of relying on globals. Doing that would let generic code
5470 handle the search for this specific architecture. */
5471 if (!gdbarch_update_p (info
))
5472 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5476 set_mipsfpu_double_command (char *args
, int from_tty
)
5478 struct gdbarch_info info
;
5479 gdbarch_info_init (&info
);
5480 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5481 mips_fpu_type_auto
= 0;
5482 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5483 instead of relying on globals. Doing that would let generic code
5484 handle the search for this specific architecture. */
5485 if (!gdbarch_update_p (info
))
5486 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5490 set_mipsfpu_none_command (char *args
, int from_tty
)
5492 struct gdbarch_info info
;
5493 gdbarch_info_init (&info
);
5494 mips_fpu_type
= MIPS_FPU_NONE
;
5495 mips_fpu_type_auto
= 0;
5496 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5497 instead of relying on globals. Doing that would let generic code
5498 handle the search for this specific architecture. */
5499 if (!gdbarch_update_p (info
))
5500 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5504 set_mipsfpu_auto_command (char *args
, int from_tty
)
5506 mips_fpu_type_auto
= 1;
5509 /* Attempt to identify the particular processor model by reading the
5510 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5511 the relevant processor still exists (it dates back to '94) and
5512 secondly this is not the way to do this. The processor type should
5513 be set by forcing an architecture change. */
5516 deprecated_mips_set_processor_regs_hack (void)
5518 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5521 prid
= read_register (PRID_REGNUM
);
5523 if ((prid
& ~0xf) == 0x700)
5524 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5527 /* Just like reinit_frame_cache, but with the right arguments to be
5528 callable as an sfunc. */
5531 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5532 struct cmd_list_element
*c
)
5534 reinit_frame_cache ();
5538 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5540 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5541 mips_extra_func_info_t proc_desc
;
5543 /* Search for the function containing this address. Set the low bit
5544 of the address when searching, in case we were given an even address
5545 that is the start of a 16-bit function. If we didn't do this,
5546 the search would fail because the symbol table says the function
5547 starts at an odd address, i.e. 1 byte past the given address. */
5548 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5549 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5551 /* Make an attempt to determine if this is a 16-bit function. If
5552 the procedure descriptor exists and the address therein is odd,
5553 it's definitely a 16-bit function. Otherwise, we have to just
5554 guess that if the address passed in is odd, it's 16-bits. */
5555 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5556 disassembler needs to be able to locally determine the ISA, and
5557 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5561 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5562 info
->mach
= bfd_mach_mips16
;
5566 if (pc_is_mips16 (memaddr
))
5567 info
->mach
= bfd_mach_mips16
;
5570 /* Round down the instruction address to the appropriate boundary. */
5571 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5573 /* Set the disassembler options. */
5574 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5576 /* Set up the disassembler info, so that we get the right
5577 register names from libopcodes. */
5578 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5579 info
->disassembler_options
= "gpr-names=n32";
5581 info
->disassembler_options
= "gpr-names=64";
5582 info
->flavour
= bfd_target_elf_flavour
;
5585 /* This string is not recognized explicitly by the disassembler,
5586 but it tells the disassembler to not try to guess the ABI from
5587 the bfd elf headers, such that, if the user overrides the ABI
5588 of a program linked as NewABI, the disassembly will follow the
5589 register naming conventions specified by the user. */
5590 info
->disassembler_options
= "gpr-names=32";
5592 /* Call the appropriate disassembler based on the target endian-ness. */
5593 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5594 return print_insn_big_mips (memaddr
, info
);
5596 return print_insn_little_mips (memaddr
, info
);
5599 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5600 counter value to determine whether a 16- or 32-bit breakpoint should be
5601 used. It returns a pointer to a string of bytes that encode a breakpoint
5602 instruction, stores the length of the string to *lenptr, and adjusts pc
5603 (if necessary) to point to the actual memory location where the
5604 breakpoint should be inserted. */
5606 static const unsigned char *
5607 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5609 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5611 if (pc_is_mips16 (*pcptr
))
5613 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5614 *pcptr
= unmake_mips16_addr (*pcptr
);
5615 *lenptr
= sizeof (mips16_big_breakpoint
);
5616 return mips16_big_breakpoint
;
5620 /* The IDT board uses an unusual breakpoint value, and
5621 sometimes gets confused when it sees the usual MIPS
5622 breakpoint instruction. */
5623 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5624 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5625 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5627 *lenptr
= sizeof (big_breakpoint
);
5629 if (strcmp (target_shortname
, "mips") == 0)
5630 return idt_big_breakpoint
;
5631 else if (strcmp (target_shortname
, "ddb") == 0
5632 || strcmp (target_shortname
, "pmon") == 0
5633 || strcmp (target_shortname
, "lsi") == 0)
5634 return pmon_big_breakpoint
;
5636 return big_breakpoint
;
5641 if (pc_is_mips16 (*pcptr
))
5643 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5644 *pcptr
= unmake_mips16_addr (*pcptr
);
5645 *lenptr
= sizeof (mips16_little_breakpoint
);
5646 return mips16_little_breakpoint
;
5650 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5651 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5652 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5654 *lenptr
= sizeof (little_breakpoint
);
5656 if (strcmp (target_shortname
, "mips") == 0)
5657 return idt_little_breakpoint
;
5658 else if (strcmp (target_shortname
, "ddb") == 0
5659 || strcmp (target_shortname
, "pmon") == 0
5660 || strcmp (target_shortname
, "lsi") == 0)
5661 return pmon_little_breakpoint
;
5663 return little_breakpoint
;
5668 /* If PC is in a mips16 call or return stub, return the address of the target
5669 PC, which is either the callee or the caller. There are several
5670 cases which must be handled:
5672 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5673 target PC is in $31 ($ra).
5674 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5675 and the target PC is in $2.
5676 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5677 before the jal instruction, this is effectively a call stub
5678 and the the target PC is in $2. Otherwise this is effectively
5679 a return stub and the target PC is in $18.
5681 See the source code for the stubs in gcc/config/mips/mips16.S for
5684 This function implements the SKIP_TRAMPOLINE_CODE macro.
5688 mips_skip_stub (CORE_ADDR pc
)
5691 CORE_ADDR start_addr
;
5693 /* Find the starting address and name of the function containing the PC. */
5694 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5697 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5698 target PC is in $31 ($ra). */
5699 if (strcmp (name
, "__mips16_ret_sf") == 0
5700 || strcmp (name
, "__mips16_ret_df") == 0)
5701 return read_signed_register (RA_REGNUM
);
5703 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5705 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5706 and the target PC is in $2. */
5707 if (name
[19] >= '0' && name
[19] <= '9')
5708 return read_signed_register (2);
5710 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5711 before the jal instruction, this is effectively a call stub
5712 and the the target PC is in $2. Otherwise this is effectively
5713 a return stub and the target PC is in $18. */
5714 else if (name
[19] == 's' || name
[19] == 'd')
5716 if (pc
== start_addr
)
5718 /* Check if the target of the stub is a compiler-generated
5719 stub. Such a stub for a function bar might have a name
5720 like __fn_stub_bar, and might look like this:
5725 la $1,bar (becomes a lui/addiu pair)
5727 So scan down to the lui/addi and extract the target
5728 address from those two instructions. */
5730 CORE_ADDR target_pc
= read_signed_register (2);
5734 /* See if the name of the target function is __fn_stub_*. */
5735 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5738 if (strncmp (name
, "__fn_stub_", 10) != 0
5739 && strcmp (name
, "etext") != 0
5740 && strcmp (name
, "_etext") != 0)
5743 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5744 The limit on the search is arbitrarily set to 20
5745 instructions. FIXME. */
5746 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5748 inst
= mips_fetch_instruction (target_pc
);
5749 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5750 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5751 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5752 return pc
| (inst
& 0xffff); /* low word */
5755 /* Couldn't find the lui/addui pair, so return stub address. */
5759 /* This is the 'return' part of a call stub. The return
5760 address is in $r18. */
5761 return read_signed_register (18);
5764 return 0; /* not a stub */
5768 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5769 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5772 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5774 CORE_ADDR start_addr
;
5776 /* Find the starting address of the function containing the PC. If the
5777 caller didn't give us a name, look it up at the same time. */
5778 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5782 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5784 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5785 if (name
[19] >= '0' && name
[19] <= '9')
5787 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5788 before the jal instruction, this is effectively a call stub. */
5789 else if (name
[19] == 's' || name
[19] == 'd')
5790 return pc
== start_addr
;
5793 return 0; /* not a stub */
5797 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5798 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5801 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5803 CORE_ADDR start_addr
;
5805 /* Find the starting address of the function containing the PC. */
5806 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5809 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5810 if (strcmp (name
, "__mips16_ret_sf") == 0
5811 || strcmp (name
, "__mips16_ret_df") == 0)
5814 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5815 i.e. after the jal instruction, this is effectively a return stub. */
5816 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5817 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5820 return 0; /* not a stub */
5824 /* Return non-zero if the PC is in a library helper function that
5825 should be ignored. This implements the
5826 DEPRECATED_IGNORE_HELPER_CALL macro. */
5829 mips_ignore_helper (CORE_ADDR pc
)
5833 /* Find the starting address and name of the function containing the PC. */
5834 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5837 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5838 that we want to ignore. */
5839 return (strcmp (name
, "__mips16_ret_sf") == 0
5840 || strcmp (name
, "__mips16_ret_df") == 0);
5844 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5845 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5848 mips_stab_reg_to_regnum (int num
)
5851 if (num
>= 0 && num
< 32)
5853 else if (num
>= 38 && num
< 70)
5854 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5856 regnum
= mips_regnum (current_gdbarch
)->hi
;
5858 regnum
= mips_regnum (current_gdbarch
)->lo
;
5860 /* This will hopefully (eventually) provoke a warning. Should
5861 we be calling complaint() here? */
5862 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5863 return NUM_REGS
+ regnum
;
5867 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5868 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5871 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5874 if (num
>= 0 && num
< 32)
5876 else if (num
>= 32 && num
< 64)
5877 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5879 regnum
= mips_regnum (current_gdbarch
)->hi
;
5881 regnum
= mips_regnum (current_gdbarch
)->lo
;
5883 /* This will hopefully (eventually) provoke a warning. Should we
5884 be calling complaint() here? */
5885 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5886 return NUM_REGS
+ regnum
;
5890 mips_register_sim_regno (int regnum
)
5892 /* Only makes sense to supply raw registers. */
5893 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5894 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5895 decide if it is valid. Should instead define a standard sim/gdb
5896 register numbering scheme. */
5897 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5898 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5901 return LEGACY_SIM_REGNO_IGNORE
;
5905 /* Convert an integer into an address. By first converting the value
5906 into a pointer and then extracting it signed, the address is
5907 guarenteed to be correctly sign extended. */
5910 mips_integer_to_address (struct type
*type
, void *buf
)
5912 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5913 LONGEST val
= unpack_long (type
, buf
);
5914 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5915 return extract_signed_integer (tmp
,
5916 TYPE_LENGTH (builtin_type_void_data_ptr
));
5920 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5922 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5923 const char *name
= bfd_get_section_name (abfd
, sect
);
5925 if (*abip
!= MIPS_ABI_UNKNOWN
)
5928 if (strncmp (name
, ".mdebug.", 8) != 0)
5931 if (strcmp (name
, ".mdebug.abi32") == 0)
5932 *abip
= MIPS_ABI_O32
;
5933 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5934 *abip
= MIPS_ABI_N32
;
5935 else if (strcmp (name
, ".mdebug.abi64") == 0)
5936 *abip
= MIPS_ABI_N64
;
5937 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5938 *abip
= MIPS_ABI_O64
;
5939 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5940 *abip
= MIPS_ABI_EABI32
;
5941 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5942 *abip
= MIPS_ABI_EABI64
;
5944 warning ("unsupported ABI %s.", name
+ 8);
5947 static enum mips_abi
5948 global_mips_abi (void)
5952 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5953 if (mips_abi_strings
[i
] == mips_abi_string
)
5954 return (enum mips_abi
) i
;
5956 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5959 static struct gdbarch
*
5960 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5962 struct gdbarch
*gdbarch
;
5963 struct gdbarch_tdep
*tdep
;
5965 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5967 enum mips_fpu_type fpu_type
;
5969 /* First of all, extract the elf_flags, if available. */
5970 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5971 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5972 else if (arches
!= NULL
)
5973 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5977 fprintf_unfiltered (gdb_stdlog
,
5978 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5980 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5981 switch ((elf_flags
& EF_MIPS_ABI
))
5983 case E_MIPS_ABI_O32
:
5984 found_abi
= MIPS_ABI_O32
;
5986 case E_MIPS_ABI_O64
:
5987 found_abi
= MIPS_ABI_O64
;
5989 case E_MIPS_ABI_EABI32
:
5990 found_abi
= MIPS_ABI_EABI32
;
5992 case E_MIPS_ABI_EABI64
:
5993 found_abi
= MIPS_ABI_EABI64
;
5996 if ((elf_flags
& EF_MIPS_ABI2
))
5997 found_abi
= MIPS_ABI_N32
;
5999 found_abi
= MIPS_ABI_UNKNOWN
;
6003 /* GCC creates a pseudo-section whose name describes the ABI. */
6004 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6005 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6007 /* If we have no useful BFD information, use the ABI from the last
6008 MIPS architecture (if there is one). */
6009 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6010 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6012 /* Try the architecture for any hint of the correct ABI. */
6013 if (found_abi
== MIPS_ABI_UNKNOWN
6014 && info
.bfd_arch_info
!= NULL
6015 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6017 switch (info
.bfd_arch_info
->mach
)
6019 case bfd_mach_mips3900
:
6020 found_abi
= MIPS_ABI_EABI32
;
6022 case bfd_mach_mips4100
:
6023 case bfd_mach_mips5000
:
6024 found_abi
= MIPS_ABI_EABI64
;
6026 case bfd_mach_mips8000
:
6027 case bfd_mach_mips10000
:
6028 /* On Irix, ELF64 executables use the N64 ABI. The
6029 pseudo-sections which describe the ABI aren't present
6030 on IRIX. (Even for executables created by gcc.) */
6031 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6032 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6033 found_abi
= MIPS_ABI_N64
;
6035 found_abi
= MIPS_ABI_N32
;
6041 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6044 /* What has the user specified from the command line? */
6045 wanted_abi
= global_mips_abi ();
6047 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6050 /* Now that we have found what the ABI for this binary would be,
6051 check whether the user is overriding it. */
6052 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6053 mips_abi
= wanted_abi
;
6054 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6055 mips_abi
= found_abi
;
6057 mips_abi
= MIPS_ABI_O32
;
6059 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6062 /* Also used when doing an architecture lookup. */
6064 fprintf_unfiltered (gdb_stdlog
,
6065 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
6066 mips64_transfers_32bit_regs_p
);
6068 /* Determine the MIPS FPU type. */
6069 if (!mips_fpu_type_auto
)
6070 fpu_type
= mips_fpu_type
;
6071 else if (info
.bfd_arch_info
!= NULL
6072 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6073 switch (info
.bfd_arch_info
->mach
)
6075 case bfd_mach_mips3900
:
6076 case bfd_mach_mips4100
:
6077 case bfd_mach_mips4111
:
6078 case bfd_mach_mips4120
:
6079 fpu_type
= MIPS_FPU_NONE
;
6081 case bfd_mach_mips4650
:
6082 fpu_type
= MIPS_FPU_SINGLE
;
6085 fpu_type
= MIPS_FPU_DOUBLE
;
6088 else if (arches
!= NULL
)
6089 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6091 fpu_type
= MIPS_FPU_DOUBLE
;
6093 fprintf_unfiltered (gdb_stdlog
,
6094 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6096 /* try to find a pre-existing architecture */
6097 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6099 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6101 /* MIPS needs to be pedantic about which ABI the object is
6103 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6105 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6107 /* Need to be pedantic about which register virtual size is
6109 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6110 != mips64_transfers_32bit_regs_p
)
6112 /* Be pedantic about which FPU is selected. */
6113 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6115 return arches
->gdbarch
;
6118 /* Need a new architecture. Fill in a target specific vector. */
6119 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6120 gdbarch
= gdbarch_alloc (&info
, tdep
);
6121 tdep
->elf_flags
= elf_flags
;
6122 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6123 tdep
->found_abi
= found_abi
;
6124 tdep
->mips_abi
= mips_abi
;
6125 tdep
->mips_fpu_type
= fpu_type
;
6127 /* Initially set everything according to the default ABI/ISA. */
6128 set_gdbarch_short_bit (gdbarch
, 16);
6129 set_gdbarch_int_bit (gdbarch
, 32);
6130 set_gdbarch_float_bit (gdbarch
, 32);
6131 set_gdbarch_double_bit (gdbarch
, 64);
6132 set_gdbarch_long_double_bit (gdbarch
, 64);
6133 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6134 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6135 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6137 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6138 mips_elf_make_msymbol_special
);
6140 /* Fill in the OS dependant register numbers and names. */
6142 const char **reg_names
;
6143 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6144 struct mips_regnum
);
6145 if (info
.osabi
== GDB_OSABI_IRIX
)
6150 regnum
->badvaddr
= 66;
6153 regnum
->fp_control_status
= 69;
6154 regnum
->fp_implementation_revision
= 70;
6156 reg_names
= mips_irix_reg_names
;
6160 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6161 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6162 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6163 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6164 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6165 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6166 regnum
->fp_control_status
= 70;
6167 regnum
->fp_implementation_revision
= 71;
6169 if (info
.bfd_arch_info
!= NULL
6170 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6171 reg_names
= mips_tx39_reg_names
;
6173 reg_names
= mips_generic_reg_names
;
6175 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6176 replaced by read_pc? */
6177 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6178 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6179 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6180 set_gdbarch_num_regs (gdbarch
, num_regs
);
6181 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6182 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6183 tdep
->mips_processor_reg_names
= reg_names
;
6184 tdep
->regnum
= regnum
;
6190 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6191 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6192 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6193 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6194 tdep
->default_mask_address_p
= 0;
6195 set_gdbarch_long_bit (gdbarch
, 32);
6196 set_gdbarch_ptr_bit (gdbarch
, 32);
6197 set_gdbarch_long_long_bit (gdbarch
, 64);
6200 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6201 set_gdbarch_deprecated_store_return_value (gdbarch
,
6202 mips_o64_store_return_value
);
6203 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6204 mips_o64_extract_return_value
);
6205 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6206 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6207 tdep
->default_mask_address_p
= 0;
6208 set_gdbarch_long_bit (gdbarch
, 32);
6209 set_gdbarch_ptr_bit (gdbarch
, 32);
6210 set_gdbarch_long_long_bit (gdbarch
, 64);
6211 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
6213 case MIPS_ABI_EABI32
:
6214 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6215 set_gdbarch_deprecated_store_return_value (gdbarch
,
6216 mips_eabi_store_return_value
);
6217 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6218 mips_eabi_extract_return_value
);
6219 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6220 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6221 tdep
->default_mask_address_p
= 0;
6222 set_gdbarch_long_bit (gdbarch
, 32);
6223 set_gdbarch_ptr_bit (gdbarch
, 32);
6224 set_gdbarch_long_long_bit (gdbarch
, 64);
6225 set_gdbarch_deprecated_reg_struct_has_addr
6226 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6227 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6229 case MIPS_ABI_EABI64
:
6230 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6231 set_gdbarch_deprecated_store_return_value (gdbarch
,
6232 mips_eabi_store_return_value
);
6233 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6234 mips_eabi_extract_return_value
);
6235 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6236 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6237 tdep
->default_mask_address_p
= 0;
6238 set_gdbarch_long_bit (gdbarch
, 64);
6239 set_gdbarch_ptr_bit (gdbarch
, 64);
6240 set_gdbarch_long_long_bit (gdbarch
, 64);
6241 set_gdbarch_deprecated_reg_struct_has_addr
6242 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6243 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6246 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6247 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6248 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6249 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6250 tdep
->default_mask_address_p
= 0;
6251 set_gdbarch_long_bit (gdbarch
, 32);
6252 set_gdbarch_ptr_bit (gdbarch
, 32);
6253 set_gdbarch_long_long_bit (gdbarch
, 64);
6254 set_gdbarch_long_double_bit (gdbarch
, 128);
6255 set_gdbarch_long_double_format (gdbarch
,
6256 &floatformat_n32n64_long_double_big
);
6259 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6260 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6261 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6262 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6263 tdep
->default_mask_address_p
= 0;
6264 set_gdbarch_long_bit (gdbarch
, 64);
6265 set_gdbarch_ptr_bit (gdbarch
, 64);
6266 set_gdbarch_long_long_bit (gdbarch
, 64);
6267 set_gdbarch_long_double_bit (gdbarch
, 128);
6268 set_gdbarch_long_double_format (gdbarch
,
6269 &floatformat_n32n64_long_double_big
);
6272 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6275 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6276 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6279 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6280 flag in object files because to do so would make it impossible to
6281 link with libraries compiled without "-gp32". This is
6282 unnecessarily restrictive.
6284 We could solve this problem by adding "-gp32" multilibs to gcc,
6285 but to set this flag before gcc is built with such multilibs will
6286 break too many systems.''
6288 But even more unhelpfully, the default linker output target for
6289 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6290 for 64-bit programs - you need to change the ABI to change this,
6291 and not all gcc targets support that currently. Therefore using
6292 this flag to detect 32-bit mode would do the wrong thing given
6293 the current gcc - it would make GDB treat these 64-bit programs
6294 as 32-bit programs by default. */
6296 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6297 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6298 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6300 /* Add/remove bits from an address. The MIPS needs be careful to
6301 ensure that all 32 bit addresses are sign extended to 64 bits. */
6302 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6304 /* Unwind the frame. */
6305 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6306 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6308 /* Map debug register numbers onto internal register numbers. */
6309 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6310 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6311 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6312 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6313 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6314 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6315 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6316 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6318 /* MIPS version of CALL_DUMMY */
6320 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6321 replaced by a command, and all targets will default to on stack
6322 (regardless of the stack's execute status). */
6323 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6324 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6326 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6327 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6328 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6330 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6331 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6333 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6335 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6336 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6337 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6339 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6341 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6343 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6345 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6346 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6347 need to all be folded into the target vector. Since they are
6348 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6349 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6351 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6353 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6355 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6356 to support MIPS16. This is a bad thing. Make sure not to do it
6357 if we have an OS ABI that actually supports shared libraries, since
6358 shared library support is more important. If we have an OS someday
6359 that supports both shared libraries and MIPS16, we'll have to find
6360 a better place for these. */
6361 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6363 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6364 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6367 /* Hook in OS ABI-specific overrides, if they have been registered. */
6368 gdbarch_init_osabi (info
, gdbarch
);
6370 /* Unwind the frame. */
6371 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6372 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6373 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6374 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6375 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6376 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6377 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6378 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6384 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6386 struct gdbarch_info info
;
6388 /* Force the architecture to update, and (if it's a MIPS architecture)
6389 mips_gdbarch_init will take care of the rest. */
6390 gdbarch_info_init (&info
);
6391 gdbarch_update_p (info
);
6394 /* Print out which MIPS ABI is in use. */
6397 show_mips_abi (char *ignore_args
, int from_tty
)
6399 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6401 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6404 enum mips_abi global_abi
= global_mips_abi ();
6405 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6406 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6408 if (global_abi
== MIPS_ABI_UNKNOWN
)
6410 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6412 else if (global_abi
== actual_abi
)
6414 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6418 /* Probably shouldn't happen... */
6420 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6421 actual_abi_str
, mips_abi_strings
[global_abi
]);
6427 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6429 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6433 int ef_mips_32bitmode
;
6434 /* determine the ISA */
6435 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6453 /* determine the size of a pointer */
6454 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6455 fprintf_unfiltered (file
,
6456 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6458 fprintf_unfiltered (file
,
6459 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6461 fprintf_unfiltered (file
,
6462 "mips_dump_tdep: ef_mips_arch = %d\n",
6464 fprintf_unfiltered (file
,
6465 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6466 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6467 fprintf_unfiltered (file
,
6468 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6469 mips_mask_address_p (tdep
),
6470 tdep
->default_mask_address_p
);
6472 fprintf_unfiltered (file
,
6473 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6474 MIPS_DEFAULT_FPU_TYPE
,
6475 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6476 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6477 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6479 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6480 fprintf_unfiltered (file
,
6481 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6483 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6484 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6485 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6487 fprintf_unfiltered (file
,
6488 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6489 mips_stack_argsize (current_gdbarch
));
6490 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6491 fprintf_unfiltered (file
,
6492 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6493 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6494 fprintf_unfiltered (file
,
6495 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6496 XSTRING (ATTACH_DETACH
));
6497 fprintf_unfiltered (file
,
6498 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6499 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6500 fprintf_unfiltered (file
,
6501 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6502 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6503 fprintf_unfiltered (file
,
6504 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6505 FIRST_EMBED_REGNUM
);
6506 fprintf_unfiltered (file
,
6507 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6508 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6509 fprintf_unfiltered (file
,
6510 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6511 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6512 fprintf_unfiltered (file
,
6513 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6514 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6515 fprintf_unfiltered (file
,
6516 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6518 #ifdef MACHINE_CPROC_FP_OFFSET
6519 fprintf_unfiltered (file
,
6520 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6521 MACHINE_CPROC_FP_OFFSET
);
6523 #ifdef MACHINE_CPROC_PC_OFFSET
6524 fprintf_unfiltered (file
,
6525 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6526 MACHINE_CPROC_PC_OFFSET
);
6528 #ifdef MACHINE_CPROC_SP_OFFSET
6529 fprintf_unfiltered (file
,
6530 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6531 MACHINE_CPROC_SP_OFFSET
);
6533 fprintf_unfiltered (file
,
6534 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6536 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6537 fprintf_unfiltered (file
,
6538 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6539 fprintf_unfiltered (file
,
6540 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6541 fprintf_unfiltered (file
,
6542 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6543 MIPS_LAST_ARG_REGNUM
,
6544 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6545 fprintf_unfiltered (file
,
6546 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6547 fprintf_unfiltered (file
,
6548 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6549 mips_abi_regsize (current_gdbarch
));
6550 fprintf_unfiltered (file
,
6551 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6552 fprintf_unfiltered (file
,
6553 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6554 fprintf_unfiltered (file
,
6555 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6556 fprintf_unfiltered (file
,
6557 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6558 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6559 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6560 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6561 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6562 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6563 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6564 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6565 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6566 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6567 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6568 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6570 fprintf_unfiltered (file
,
6571 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6574 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6577 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6579 fprintf_unfiltered (file
,
6580 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6581 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6582 fprintf_unfiltered (file
,
6583 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6584 fprintf_unfiltered (file
,
6585 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6586 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6587 fprintf_unfiltered (file
,
6588 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6589 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6590 fprintf_unfiltered (file
,
6591 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6592 SOFTWARE_SINGLE_STEP_P ());
6593 fprintf_unfiltered (file
,
6594 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6595 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6596 #ifdef STACK_END_ADDR
6597 fprintf_unfiltered (file
,
6598 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6601 fprintf_unfiltered (file
,
6602 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6603 XSTRING (STEP_SKIPS_DELAY (PC
)));
6604 fprintf_unfiltered (file
,
6605 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6606 STEP_SKIPS_DELAY_P
);
6607 fprintf_unfiltered (file
,
6608 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6609 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6610 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6611 fprintf_unfiltered (file
,
6612 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6613 fprintf_unfiltered (file
,
6614 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6615 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6616 (TYPE
, CNT
, OTHERTYPE
)));
6617 fprintf_unfiltered (file
,
6618 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6619 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6621 fprintf_unfiltered (file
,
6622 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6623 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6626 fprintf_unfiltered (file
,
6627 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6629 #ifdef TRACE_FLAVOR_SIZE
6630 fprintf_unfiltered (file
,
6631 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6635 fprintf_unfiltered (file
,
6636 "mips_dump_tdep: TRACE_SET # %s\n",
6637 XSTRING (TRACE_SET (X
, STATE
)));
6639 #ifdef UNUSED_REGNUM
6640 fprintf_unfiltered (file
,
6641 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6643 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6644 fprintf_unfiltered (file
,
6645 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6646 (long) VM_MIN_ADDRESS
);
6647 fprintf_unfiltered (file
,
6648 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6649 fprintf_unfiltered (file
,
6650 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6653 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6656 _initialize_mips_tdep (void)
6658 static struct cmd_list_element
*mipsfpulist
= NULL
;
6659 struct cmd_list_element
*c
;
6661 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6662 if (MIPS_ABI_LAST
+ 1
6663 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6664 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6666 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6668 mips_pdr_data
= register_objfile_data ();
6670 /* Add root prefix command for all "set mips"/"show mips" commands */
6671 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6672 "Various MIPS specific commands.",
6673 &setmipscmdlist
, "set mips ", 0, &setlist
);
6675 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6676 "Various MIPS specific commands.",
6677 &showmipscmdlist
, "show mips ", 0, &showlist
);
6679 /* Allow the user to override the saved register size. */
6680 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6683 &mips_abi_regsize_string
, "\
6684 Set size of general purpose registers saved on the stack.\n\
6685 This option can be set to one of:\n\
6686 32 - Force GDB to treat saved GP registers as 32-bit\n\
6687 64 - Force GDB to treat saved GP registers as 64-bit\n\
6688 auto - Allow GDB to use the target's default setting or autodetect the\n\
6689 saved GP register size from information contained in the executable.\n\
6690 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6692 /* Allow the user to override the argument stack size. */
6693 deprecated_add_show_from_set
6694 (add_set_enum_cmd ("stack-arg-size",
6697 &mips_stack_argsize_string
, "\
6698 Set the amount of stack space reserved for each argument.\n\
6699 This option can be set to one of:\n\
6700 32 - Force GDB to allocate 32-bit chunks per argument\n\
6701 64 - Force GDB to allocate 64-bit chunks per argument\n\
6702 auto - Allow GDB to determine the correct setting from the current\n\
6703 target and executable (default)", &setmipscmdlist
),
6706 /* Allow the user to override the ABI. */
6707 c
= add_set_enum_cmd
6708 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6709 "Set the ABI used by this program.\n"
6710 "This option can be set to one of:\n"
6711 " auto - the default ABI associated with the current binary\n"
6713 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6714 set_cmd_sfunc (c
, mips_abi_update
);
6715 add_cmd ("abi", class_obscure
, show_mips_abi
,
6716 "Show ABI in use by MIPS target", &showmipscmdlist
);
6718 /* Let the user turn off floating point and set the fence post for
6719 heuristic_proc_start. */
6721 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6722 "Set use of MIPS floating-point coprocessor.",
6723 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6724 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6725 "Select single-precision MIPS floating-point coprocessor.",
6727 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6728 "Select double-precision MIPS floating-point coprocessor.",
6730 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6731 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6732 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6733 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6734 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6735 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6736 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6737 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6738 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6739 "Select MIPS floating-point coprocessor automatically.",
6741 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6742 "Show current use of MIPS floating-point coprocessor target.",
6745 /* We really would like to have both "0" and "unlimited" work, but
6746 command.c doesn't deal with that. So make it a var_zinteger
6747 because the user can always use "999999" or some such for unlimited. */
6748 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6749 (char *) &heuristic_fence_post
, "\
6750 Set the distance searched for the start of a function.\n\
6751 If you are debugging a stripped executable, GDB needs to search through the\n\
6752 program for the start of a function. This command sets the distance of the\n\
6753 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6754 /* We need to throw away the frame cache when we set this, since it
6755 might change our ability to get backtraces. */
6756 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6757 deprecated_add_show_from_set (c
, &showlist
);
6759 /* Allow the user to control whether the upper bits of 64-bit
6760 addresses should be zeroed. */
6761 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6762 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6763 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6764 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6765 allow GDB to determine the correct value.\n", "\
6766 Zerroing of upper 32 bits of 64-bit address is %s.",
6767 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6769 /* Allow the user to control the size of 32 bit registers within the
6770 raw remote packet. */
6771 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6772 &mips64_transfers_32bit_regs_p
, "\
6773 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6774 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6775 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6776 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6777 64 bits for others. Use \"off\" to disable compatibility mode", "\
6778 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6779 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6781 /* Debug this files internals. */
6782 deprecated_add_show_from_set
6783 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6784 &mips_debug
, "Set mips debugging.\n\
6785 When non-zero, mips specific debugging is enabled.", &setdebuglist
),