1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
40 #include "arch-utils.h"
43 #include "mips-tdep.h"
45 #include "reggroups.h"
46 #include "opcode/mips.h"
50 #include "sim-regno.h"
53 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
54 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
56 /* A useful bit in the CP0 status register (PS_REGNUM). */
57 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
58 #define ST0_FR (1 << 26)
60 /* The sizes of floating point registers. */
64 MIPS_FPU_SINGLE_REGSIZE
= 4,
65 MIPS_FPU_DOUBLE_REGSIZE
= 8
69 static const char *mips_abi_string
;
71 static const char *mips_abi_strings
[] = {
82 struct frame_extra_info
84 mips_extra_func_info_t proc_desc
;
88 /* Various MIPS ISA options (related to stack analysis) can be
89 overridden dynamically. Establish an enum/array for managing
92 static const char size_auto
[] = "auto";
93 static const char size_32
[] = "32";
94 static const char size_64
[] = "64";
96 static const char *size_enums
[] = {
103 /* Some MIPS boards don't support floating point while others only
104 support single-precision floating-point operations. See also
105 FP_REGISTER_DOUBLE. */
109 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
110 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
111 MIPS_FPU_NONE
/* No floating point. */
114 #ifndef MIPS_DEFAULT_FPU_TYPE
115 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
117 static int mips_fpu_type_auto
= 1;
118 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
120 static int mips_debug
= 0;
122 /* MIPS specific per-architecture information */
125 /* from the elf header */
129 enum mips_abi mips_abi
;
130 enum mips_abi found_abi
;
131 enum mips_fpu_type mips_fpu_type
;
132 int mips_last_arg_regnum
;
133 int mips_last_fp_arg_regnum
;
134 int mips_default_saved_regsize
;
135 int mips_fp_register_double
;
136 int mips_default_stack_argsize
;
137 int default_mask_address_p
;
140 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
141 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
143 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
145 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
147 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
149 /* Return the currently configured (or set) saved register size. */
151 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
153 static const char *mips_saved_regsize_string
= size_auto
;
155 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
157 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
158 functions to test, set, or clear bit 0 of addresses. */
161 is_mips16_addr (CORE_ADDR addr
)
167 make_mips16_addr (CORE_ADDR addr
)
173 unmake_mips16_addr (CORE_ADDR addr
)
175 return ((addr
) & ~1);
178 /* Return the contents of register REGNUM as a signed integer. */
181 read_signed_register (int regnum
)
183 void *buf
= alloca (DEPRECATED_REGISTER_RAW_SIZE (regnum
));
184 deprecated_read_register_gen (regnum
, buf
);
185 return (extract_signed_integer (buf
, DEPRECATED_REGISTER_RAW_SIZE (regnum
)));
189 read_signed_register_pid (int regnum
, ptid_t ptid
)
194 if (ptid_equal (ptid
, inferior_ptid
))
195 return read_signed_register (regnum
);
197 save_ptid
= inferior_ptid
;
199 inferior_ptid
= ptid
;
201 retval
= read_signed_register (regnum
);
203 inferior_ptid
= save_ptid
;
208 /* Return the MIPS ABI associated with GDBARCH. */
210 mips_abi (struct gdbarch
*gdbarch
)
212 return gdbarch_tdep (gdbarch
)->mips_abi
;
216 mips_regsize (struct gdbarch
*gdbarch
)
218 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
219 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
223 mips_saved_regsize (void)
225 if (mips_saved_regsize_string
== size_auto
)
226 return MIPS_DEFAULT_SAVED_REGSIZE
;
227 else if (mips_saved_regsize_string
== size_64
)
229 else /* if (mips_saved_regsize_string == size_32) */
233 /* Functions for setting and testing a bit in a minimal symbol that
234 marks it as 16-bit function. The MSB of the minimal symbol's
235 "info" field is used for this purpose.
237 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
238 i.e. refers to a 16-bit function, and sets a "special" bit in a
239 minimal symbol to mark it as a 16-bit function
241 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
244 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
246 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
248 MSYMBOL_INFO (msym
) = (char *)
249 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
250 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
255 msymbol_is_special (struct minimal_symbol
*msym
)
257 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
260 /* XFER a value from the big/little/left end of the register.
261 Depending on the size of the value it might occupy the entire
262 register or just part of it. Make an allowance for this, aligning
263 things accordingly. */
266 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
267 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
270 bfd_byte reg
[MAX_REGISTER_SIZE
];
272 gdb_assert (reg_num
>= NUM_REGS
);
273 /* Need to transfer the left or right part of the register, based on
274 the targets byte order. */
278 reg_offset
= DEPRECATED_REGISTER_RAW_SIZE (reg_num
) - length
;
280 case BFD_ENDIAN_LITTLE
:
283 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
287 internal_error (__FILE__
, __LINE__
, "bad switch");
290 fprintf_unfiltered (gdb_stderr
,
291 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
292 reg_num
, reg_offset
, buf_offset
, length
);
293 if (mips_debug
&& out
!= NULL
)
296 fprintf_unfiltered (gdb_stdlog
, "out ");
297 for (i
= 0; i
< length
; i
++)
298 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
301 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
303 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
304 if (mips_debug
&& in
!= NULL
)
307 fprintf_unfiltered (gdb_stdlog
, "in ");
308 for (i
= 0; i
< length
; i
++)
309 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
312 fprintf_unfiltered (gdb_stdlog
, "\n");
315 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
316 compatiblity mode. A return value of 1 means that we have
317 physical 64-bit registers, but should treat them as 32-bit registers. */
320 mips2_fp_compat (void)
322 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
324 if (DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
328 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
329 in all the places we deal with FP registers. PR gdb/413. */
330 /* Otherwise check the FR bit in the status register - it controls
331 the FP compatiblity mode. If it is clear we are in compatibility
333 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
340 /* Indicate that the ABI makes use of double-precision registers
341 provided by the FPU (rather than combining pairs of registers to
342 form double-precision values). See also MIPS_FPU_TYPE. */
343 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
345 /* The amount of space reserved on the stack for registers. This is
346 different to MIPS_SAVED_REGSIZE as it determines the alignment of
347 data allocated after the registers have run out. */
349 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
351 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
353 static const char *mips_stack_argsize_string
= size_auto
;
356 mips_stack_argsize (void)
358 if (mips_stack_argsize_string
== size_auto
)
359 return MIPS_DEFAULT_STACK_ARGSIZE
;
360 else if (mips_stack_argsize_string
== size_64
)
362 else /* if (mips_stack_argsize_string == size_32) */
366 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
368 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
370 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
371 struct frame_info
*, int);
373 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
375 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
377 static int mips_set_processor_type (char *);
379 static void mips_show_processor_type_command (char *, int);
381 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
383 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
384 struct frame_info
*next_frame
,
387 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
388 mips_extra_func_info_t proc_desc
);
390 static struct type
*mips_float_register_type (void);
391 static struct type
*mips_double_register_type (void);
393 /* This value is the model of MIPS in use. It is derived from the value
394 of the PrID register. */
396 char *mips_processor_type
;
398 char *tmp_mips_processor_type
;
400 /* The list of available "set mips " and "show mips " commands */
402 static struct cmd_list_element
*setmipscmdlist
= NULL
;
403 static struct cmd_list_element
*showmipscmdlist
= NULL
;
405 /* A set of original names, to be used when restoring back to generic
406 registers from a specific set. */
407 static char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
409 /* Integer registers 0 thru 31 are handled explicitly by
410 mips_register_name(). Processor specific registers 32 and above
411 are listed in the sets of register names assigned to
412 mips_processor_reg_names. */
413 static char **mips_processor_reg_names
= mips_generic_reg_names
;
415 /* Return the name of the register corresponding to REGNO. */
417 mips_register_name (int regno
)
419 /* GPR names for all ABIs other than n32/n64. */
420 static char *mips_gpr_names
[] = {
421 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
422 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
423 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
424 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
427 /* GPR names for n32 and n64 ABIs. */
428 static char *mips_n32_n64_gpr_names
[] = {
429 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
430 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
431 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
432 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
435 enum mips_abi abi
= mips_abi (current_gdbarch
);
437 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
438 don't make the raw register names visible. */
439 int rawnum
= regno
% NUM_REGS
;
440 if (regno
< NUM_REGS
)
443 /* The MIPS integer registers are always mapped from 0 to 31. The
444 names of the registers (which reflects the conventions regarding
445 register use) vary depending on the ABI. */
446 if (0 <= rawnum
&& rawnum
< 32)
448 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
449 return mips_n32_n64_gpr_names
[rawnum
];
451 return mips_gpr_names
[rawnum
];
453 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
454 return mips_processor_reg_names
[rawnum
- 32];
456 internal_error (__FILE__
, __LINE__
,
457 "mips_register_name: bad register number %d", rawnum
);
461 /* Names of IDT R3041 registers. */
463 char *mips_r3041_reg_names
[] = {
464 "sr", "lo", "hi", "bad", "cause","pc",
465 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
466 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
467 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
468 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
469 "fsr", "fir", "",/*"fp"*/ "",
470 "", "", "bus", "ccfg", "", "", "", "",
471 "", "", "port", "cmp", "", "", "epc", "prid",
474 /* Names of IDT R3051 registers. */
476 char *mips_r3051_reg_names
[] = {
477 "sr", "lo", "hi", "bad", "cause","pc",
478 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
479 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
480 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
481 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
482 "fsr", "fir", ""/*"fp"*/, "",
483 "inx", "rand", "elo", "", "ctxt", "", "", "",
484 "", "", "ehi", "", "", "", "epc", "prid",
487 /* Names of IDT R3081 registers. */
489 char *mips_r3081_reg_names
[] = {
490 "sr", "lo", "hi", "bad", "cause","pc",
491 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
492 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
493 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
494 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
495 "fsr", "fir", ""/*"fp"*/, "",
496 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
497 "", "", "ehi", "", "", "", "epc", "prid",
500 /* Names of LSI 33k registers. */
502 char *mips_lsi33k_reg_names
[] = {
503 "epc", "hi", "lo", "sr", "cause","badvaddr",
504 "dcic", "bpc", "bda", "", "", "", "", "",
505 "", "", "", "", "", "", "", "",
506 "", "", "", "", "", "", "", "",
507 "", "", "", "", "", "", "", "",
509 "", "", "", "", "", "", "", "",
510 "", "", "", "", "", "", "", "",
516 } mips_processor_type_table
[] = {
517 { "generic", mips_generic_reg_names
},
518 { "r3041", mips_r3041_reg_names
},
519 { "r3051", mips_r3051_reg_names
},
520 { "r3071", mips_r3081_reg_names
},
521 { "r3081", mips_r3081_reg_names
},
522 { "lsi33k", mips_lsi33k_reg_names
},
527 /* Return the groups that a MIPS register can be categorised into. */
530 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
531 struct reggroup
*reggroup
)
536 int rawnum
= regnum
% NUM_REGS
;
537 int pseudo
= regnum
/ NUM_REGS
;
538 if (reggroup
== all_reggroup
)
540 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
541 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
542 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
543 (gdbarch), as not all architectures are multi-arch. */
544 raw_p
= rawnum
< NUM_REGS
;
545 if (REGISTER_NAME (regnum
) == NULL
546 || REGISTER_NAME (regnum
)[0] == '\0')
548 if (reggroup
== float_reggroup
)
549 return float_p
&& pseudo
;
550 if (reggroup
== vector_reggroup
)
551 return vector_p
&& pseudo
;
552 if (reggroup
== general_reggroup
)
553 return (!vector_p
&& !float_p
) && pseudo
;
554 /* Save the pseudo registers. Need to make certain that any code
555 extracting register values from a saved register cache also uses
557 if (reggroup
== save_reggroup
)
558 return raw_p
&& pseudo
;
559 /* Restore the same pseudo register. */
560 if (reggroup
== restore_reggroup
)
561 return raw_p
&& pseudo
;
565 /* Map the symbol table registers which live in the range [1 *
566 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
570 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
571 int cookednum
, void *buf
)
573 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
574 return regcache_raw_read (regcache
, cookednum
% NUM_REGS
, buf
);
578 mips_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
579 int cookednum
, const void *buf
)
581 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
582 return regcache_raw_write (regcache
, cookednum
% NUM_REGS
, buf
);
585 /* Table to translate MIPS16 register field to actual register number. */
586 static int mips16_to_32_reg
[8] =
587 {16, 17, 2, 3, 4, 5, 6, 7};
589 /* Heuristic_proc_start may hunt through the text section for a long
590 time across a 2400 baud serial line. Allows the user to limit this
593 static unsigned int heuristic_fence_post
= 0;
595 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
596 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
597 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
598 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
599 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
600 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
601 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
602 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
603 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
604 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
605 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
606 this will corrupt pdr.iline. Fortunately we don't use it. */
607 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
608 #define _PROC_MAGIC_ 0x0F0F0F0F
609 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
610 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
612 struct linked_proc_info
614 struct mips_extra_func_info info
;
615 struct linked_proc_info
*next
;
617 *linked_proc_desc_table
= NULL
;
619 /* Number of bytes of storage in the actual machine representation for
620 register N. NOTE: This indirectly defines the register size
621 transfered by the GDB protocol. */
623 static int mips64_transfers_32bit_regs_p
= 0;
626 mips_register_raw_size (int regnum
)
628 gdb_assert (regnum
>= 0);
629 if (regnum
< NUM_REGS
)
631 /* For compatibility with old code, implemnt the broken register raw
632 size map for the raw registers.
634 NOTE: cagney/2003-06-15: This is so bogus. The register's
635 raw size is changing according to the ABI
636 (FP_REGISTER_DOUBLE). Also, GDB's protocol is defined by a
637 combination of DEPRECATED_REGISTER_RAW_SIZE and
638 DEPRECATED_REGISTER_BYTE. */
639 if (mips64_transfers_32bit_regs_p
)
640 return register_size (current_gdbarch
, regnum
);
641 else if (regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32
642 && FP_REGISTER_DOUBLE
)
643 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
647 return mips_regsize (current_gdbarch
);
649 else if (regnum
< 2 * NUM_REGS
)
651 /* For the moment map [NUM_REGS .. 2*NUM_REGS) onto the same raw
652 registers, but return the register's virtual size. */
653 return TYPE_LENGTH (gdbarch_register_type (current_gdbarch
, regnum
));
656 internal_error (__FILE__
, __LINE__
, "Register %d out of range", regnum
);
659 /* Register offset in a buffer for each register.
661 FIXME: cagney/2003-06-15: This is so bogus. Instead REGISTER_TYPE
662 should strictly return the layout of the buffer. Unfortunately
663 remote.c and the MIPS have come to rely on a custom layout that
664 doesn't 1:1 map onto the register type. */
667 mips_register_byte (int regnum
)
669 gdb_assert (regnum
>= 0);
670 if (regnum
< NUM_REGS
)
671 /* Pick up the relevant per-tm file register byte method. */
672 return MIPS_REGISTER_BYTE (regnum
);
673 else if (regnum
< 2 * NUM_REGS
)
677 /* Start with the end of the raw register buffer - assum that
678 MIPS_REGISTER_BYTE (NUM_REGS) returns that end. */
679 byte
= MIPS_REGISTER_BYTE (NUM_REGS
);
680 /* Add space for all the proceeding registers based on their
682 for (reg
= NUM_REGS
; reg
< regnum
; reg
++)
683 byte
+= TYPE_LENGTH (gdbarch_register_type (current_gdbarch
, reg
));
687 internal_error (__FILE__
, __LINE__
, "Register %d out of range", regnum
);
690 /* Convert between RAW and VIRTUAL registers. The RAW register size
691 defines the remote-gdb packet. */
694 mips_register_convertible (int reg_nr
)
696 if (mips64_transfers_32bit_regs_p
)
699 return (DEPRECATED_REGISTER_RAW_SIZE (reg_nr
) > register_size (current_gdbarch
, reg_nr
));
703 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
704 char *raw_buf
, char *virt_buf
)
706 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
708 raw_buf
+ (DEPRECATED_REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
709 TYPE_LENGTH (virtual_type
));
713 TYPE_LENGTH (virtual_type
));
717 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
718 const char *virt_buf
, char *raw_buf
)
720 memset (raw_buf
, 0, DEPRECATED_REGISTER_RAW_SIZE (n
));
721 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
722 memcpy (raw_buf
+ (DEPRECATED_REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
724 TYPE_LENGTH (virtual_type
));
728 TYPE_LENGTH (virtual_type
));
732 mips_convert_register_p (int regnum
, struct type
*type
)
734 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
735 && DEPRECATED_REGISTER_RAW_SIZE (regnum
) == 4
736 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
737 && TYPE_CODE(type
) == TYPE_CODE_FLT
738 && TYPE_LENGTH(type
) == 8);
742 mips_register_to_value (struct frame_info
*frame
, int regnum
,
743 struct type
*type
, void *to
)
745 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
746 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
750 mips_value_to_register (struct frame_info
*frame
, int regnum
,
751 struct type
*type
, const void *from
)
753 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
754 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
757 /* Return the GDB type object for the "standard" data type of data in
761 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
763 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
764 if ((regnum
% NUM_REGS
) >= FP0_REGNUM
765 && (regnum
% NUM_REGS
) < FP0_REGNUM
+ 32)
767 /* The floating-point registers raw, or cooked, always match
768 mips_regsize(), and also map 1:1, byte for byte. */
769 switch (gdbarch_byte_order (gdbarch
))
772 if (mips_regsize (gdbarch
) == 4)
773 return builtin_type_ieee_single_big
;
775 return builtin_type_ieee_double_big
;
776 case BFD_ENDIAN_LITTLE
:
777 if (mips_regsize (gdbarch
) == 4)
778 return builtin_type_ieee_single_little
;
780 return builtin_type_ieee_double_little
;
781 case BFD_ENDIAN_UNKNOWN
:
783 internal_error (__FILE__
, __LINE__
, "bad switch");
786 else if (regnum
>= (NUM_REGS
+ FCRCS_REGNUM
)
787 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
788 /* The pseudo/cooked view of the embedded registers is always
789 32-bit. The raw view is handled below. */
790 return builtin_type_int32
;
791 else if (mips_regsize (gdbarch
) == 8)
793 return builtin_type_int64
;
796 return builtin_type_int32
;
799 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
804 return read_signed_register (SP_REGNUM
);
807 /* Should the upper word of 64-bit addresses be zeroed? */
808 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
811 mips_mask_address_p (void)
813 switch (mask_address_var
)
815 case AUTO_BOOLEAN_TRUE
:
817 case AUTO_BOOLEAN_FALSE
:
820 case AUTO_BOOLEAN_AUTO
:
821 return MIPS_DEFAULT_MASK_ADDRESS_P
;
823 internal_error (__FILE__
, __LINE__
,
824 "mips_mask_address_p: bad switch");
830 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
832 switch (mask_address_var
)
834 case AUTO_BOOLEAN_TRUE
:
835 printf_filtered ("The 32 bit mips address mask is enabled\n");
837 case AUTO_BOOLEAN_FALSE
:
838 printf_filtered ("The 32 bit mips address mask is disabled\n");
840 case AUTO_BOOLEAN_AUTO
:
841 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
842 mips_mask_address_p () ? "enabled" : "disabled");
845 internal_error (__FILE__
, __LINE__
,
846 "show_mask_address: bad switch");
851 /* Should call_function allocate stack space for a struct return? */
854 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
856 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
860 mips_n32n64_use_struct_convention (int gcc_p
, struct type
*type
)
862 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
865 /* Should call_function pass struct by reference?
866 For each architecture, structs are passed either by
867 value or by reference, depending on their size. */
870 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
872 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
873 int len
= TYPE_LENGTH (check_typedef (type
));
875 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
876 return (len
> MIPS_SAVED_REGSIZE
);
882 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
884 return 0; /* Assumption: N32/N64 never passes struct by ref. */
888 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
890 return 0; /* Assumption: O32/O64 never passes struct by ref. */
893 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
896 pc_is_mips16 (bfd_vma memaddr
)
898 struct minimal_symbol
*sym
;
900 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
901 if (is_mips16_addr (memaddr
))
904 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
905 the high bit of the info field. Use this to decide if the function is
906 MIPS16 or normal MIPS. */
907 sym
= lookup_minimal_symbol_by_pc (memaddr
);
909 return msymbol_is_special (sym
);
914 /* MIPS believes that the PC has a sign extended value. Perhaphs the
915 all registers should be sign extended for simplicity? */
918 mips_read_pc (ptid_t ptid
)
920 return read_signed_register_pid (PC_REGNUM
, ptid
);
923 /* This returns the PC of the first inst after the prologue. If we can't
924 find the prologue, then return 0. */
927 after_prologue (CORE_ADDR pc
,
928 mips_extra_func_info_t proc_desc
)
930 struct symtab_and_line sal
;
931 CORE_ADDR func_addr
, func_end
;
933 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
934 to read the stack pointer from the current machine state, because
935 the current machine state has nothing to do with the information
936 we need from the proc_desc; and the process may or may not exist
939 proc_desc
= find_proc_desc (pc
, NULL
, 0);
943 /* If function is frameless, then we need to do it the hard way. I
944 strongly suspect that frameless always means prologueless... */
945 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
946 && PROC_FRAME_OFFSET (proc_desc
) == 0)
950 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
951 return 0; /* Unknown */
953 sal
= find_pc_line (func_addr
, 0);
955 if (sal
.end
< func_end
)
958 /* The line after the prologue is after the end of the function. In this
959 case, tell the caller to find the prologue the hard way. */
964 /* Decode a MIPS32 instruction that saves a register in the stack, and
965 set the appropriate bit in the general register mask or float register mask
966 to indicate which register is saved. This is a helper function
967 for mips_find_saved_regs. */
970 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
971 unsigned long *float_mask
)
975 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
976 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
977 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
979 /* It might be possible to use the instruction to
980 find the offset, rather than the code below which
981 is based on things being in a certain order in the
982 frame, but figuring out what the instruction's offset
983 is relative to might be a little tricky. */
984 reg
= (inst
& 0x001f0000) >> 16;
985 *gen_mask
|= (1 << reg
);
987 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
988 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
989 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
992 reg
= ((inst
& 0x001f0000) >> 16);
993 *float_mask
|= (1 << reg
);
997 /* Decode a MIPS16 instruction that saves a register in the stack, and
998 set the appropriate bit in the general register or float register mask
999 to indicate which register is saved. This is a helper function
1000 for mips_find_saved_regs. */
1003 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
1005 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1007 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1008 *gen_mask
|= (1 << reg
);
1010 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1012 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1013 *gen_mask
|= (1 << reg
);
1015 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
1016 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1017 *gen_mask
|= (1 << RA_REGNUM
);
1021 /* Fetch and return instruction from the specified location. If the PC
1022 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1025 mips_fetch_instruction (CORE_ADDR addr
)
1027 char buf
[MIPS_INSTLEN
];
1031 if (pc_is_mips16 (addr
))
1033 instlen
= MIPS16_INSTLEN
;
1034 addr
= unmake_mips16_addr (addr
);
1037 instlen
= MIPS_INSTLEN
;
1038 status
= read_memory_nobpt (addr
, buf
, instlen
);
1040 memory_error (status
, addr
);
1041 return extract_unsigned_integer (buf
, instlen
);
1045 /* These the fields of 32 bit mips instructions */
1046 #define mips32_op(x) (x >> 26)
1047 #define itype_op(x) (x >> 26)
1048 #define itype_rs(x) ((x >> 21) & 0x1f)
1049 #define itype_rt(x) ((x >> 16) & 0x1f)
1050 #define itype_immediate(x) (x & 0xffff)
1052 #define jtype_op(x) (x >> 26)
1053 #define jtype_target(x) (x & 0x03ffffff)
1055 #define rtype_op(x) (x >> 26)
1056 #define rtype_rs(x) ((x >> 21) & 0x1f)
1057 #define rtype_rt(x) ((x >> 16) & 0x1f)
1058 #define rtype_rd(x) ((x >> 11) & 0x1f)
1059 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1060 #define rtype_funct(x) (x & 0x3f)
1063 mips32_relative_offset (unsigned long inst
)
1066 x
= itype_immediate (inst
);
1067 if (x
& 0x8000) /* sign bit set */
1069 x
|= 0xffff0000; /* sign extension */
1075 /* Determine whate to set a single step breakpoint while considering
1076 branch prediction */
1078 mips32_next_pc (CORE_ADDR pc
)
1082 inst
= mips_fetch_instruction (pc
);
1083 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1085 if (itype_op (inst
) >> 2 == 5)
1086 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1088 op
= (itype_op (inst
) & 0x03);
1098 goto greater_branch
;
1103 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1104 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1106 int tf
= itype_rt (inst
) & 0x01;
1107 int cnum
= itype_rt (inst
) >> 2;
1108 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
1109 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1111 if (((cond
>> cnum
) & 0x01) == tf
)
1112 pc
+= mips32_relative_offset (inst
) + 4;
1117 pc
+= 4; /* Not a branch, next instruction is easy */
1120 { /* This gets way messy */
1122 /* Further subdivide into SPECIAL, REGIMM and other */
1123 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1125 case 0: /* SPECIAL */
1126 op
= rtype_funct (inst
);
1131 /* Set PC to that address */
1132 pc
= read_signed_register (rtype_rs (inst
));
1138 break; /* end SPECIAL */
1139 case 1: /* REGIMM */
1141 op
= itype_rt (inst
); /* branch condition */
1146 case 16: /* BLTZAL */
1147 case 18: /* BLTZALL */
1149 if (read_signed_register (itype_rs (inst
)) < 0)
1150 pc
+= mips32_relative_offset (inst
) + 4;
1152 pc
+= 8; /* after the delay slot */
1156 case 17: /* BGEZAL */
1157 case 19: /* BGEZALL */
1158 greater_equal_branch
:
1159 if (read_signed_register (itype_rs (inst
)) >= 0)
1160 pc
+= mips32_relative_offset (inst
) + 4;
1162 pc
+= 8; /* after the delay slot */
1164 /* All of the other instructions in the REGIMM category */
1169 break; /* end REGIMM */
1174 reg
= jtype_target (inst
) << 2;
1175 /* Upper four bits get never changed... */
1176 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1179 /* FIXME case JALX : */
1182 reg
= jtype_target (inst
) << 2;
1183 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1184 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1186 break; /* The new PC will be alternate mode */
1187 case 4: /* BEQ, BEQL */
1189 if (read_signed_register (itype_rs (inst
)) ==
1190 read_signed_register (itype_rt (inst
)))
1191 pc
+= mips32_relative_offset (inst
) + 4;
1195 case 5: /* BNE, BNEL */
1197 if (read_signed_register (itype_rs (inst
)) !=
1198 read_signed_register (itype_rt (inst
)))
1199 pc
+= mips32_relative_offset (inst
) + 4;
1203 case 6: /* BLEZ, BLEZL */
1205 if (read_signed_register (itype_rs (inst
) <= 0))
1206 pc
+= mips32_relative_offset (inst
) + 4;
1212 greater_branch
: /* BGTZ, BGTZL */
1213 if (read_signed_register (itype_rs (inst
) > 0))
1214 pc
+= mips32_relative_offset (inst
) + 4;
1221 } /* mips32_next_pc */
1223 /* Decoding the next place to set a breakpoint is irregular for the
1224 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1225 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1226 We dont want to set a single step instruction on the extend instruction
1230 /* Lots of mips16 instruction formats */
1231 /* Predicting jumps requires itype,ritype,i8type
1232 and their extensions extItype,extritype,extI8type
1234 enum mips16_inst_fmts
1236 itype
, /* 0 immediate 5,10 */
1237 ritype
, /* 1 5,3,8 */
1238 rrtype
, /* 2 5,3,3,5 */
1239 rritype
, /* 3 5,3,3,5 */
1240 rrrtype
, /* 4 5,3,3,3,2 */
1241 rriatype
, /* 5 5,3,3,1,4 */
1242 shifttype
, /* 6 5,3,3,3,2 */
1243 i8type
, /* 7 5,3,8 */
1244 i8movtype
, /* 8 5,3,3,5 */
1245 i8mov32rtype
, /* 9 5,3,5,3 */
1246 i64type
, /* 10 5,3,8 */
1247 ri64type
, /* 11 5,3,3,5 */
1248 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1249 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1250 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1251 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1252 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1253 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1254 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1255 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1256 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1257 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1259 /* I am heaping all the fields of the formats into one structure and
1260 then, only the fields which are involved in instruction extension */
1264 unsigned int regx
; /* Function in i8 type */
1269 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1270 for the bits which make up the immediatate extension. */
1273 extended_offset (unsigned int extension
)
1276 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1278 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1280 value
|= extension
& 0x01f; /* extract 4:0 */
1284 /* Only call this function if you know that this is an extendable
1285 instruction, It wont malfunction, but why make excess remote memory references?
1286 If the immediate operands get sign extended or somthing, do it after
1287 the extension is performed.
1289 /* FIXME: Every one of these cases needs to worry about sign extension
1290 when the offset is to be used in relative addressing */
1294 fetch_mips_16 (CORE_ADDR pc
)
1297 pc
&= 0xfffffffe; /* clear the low order bit */
1298 target_read_memory (pc
, buf
, 2);
1299 return extract_unsigned_integer (buf
, 2);
1303 unpack_mips16 (CORE_ADDR pc
,
1304 unsigned int extension
,
1306 enum mips16_inst_fmts insn_format
,
1307 struct upk_mips16
*upk
)
1312 switch (insn_format
)
1319 value
= extended_offset (extension
);
1320 value
= value
<< 11; /* rom for the original value */
1321 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1325 value
= inst
& 0x7ff;
1326 /* FIXME : Consider sign extension */
1335 { /* A register identifier and an offset */
1336 /* Most of the fields are the same as I type but the
1337 immediate value is of a different length */
1341 value
= extended_offset (extension
);
1342 value
= value
<< 8; /* from the original instruction */
1343 value
|= inst
& 0xff; /* eleven bits from instruction */
1344 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1345 if (value
& 0x4000) /* test the sign bit , bit 26 */
1347 value
&= ~0x3fff; /* remove the sign bit */
1353 value
= inst
& 0xff; /* 8 bits */
1354 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1355 /* FIXME: Do sign extension , this format needs it */
1356 if (value
& 0x80) /* THIS CONFUSES ME */
1358 value
&= 0xef; /* remove the sign bit */
1368 unsigned long value
;
1369 unsigned int nexthalf
;
1370 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1371 value
= value
<< 16;
1372 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1380 internal_error (__FILE__
, __LINE__
,
1383 upk
->offset
= offset
;
1390 add_offset_16 (CORE_ADDR pc
, int offset
)
1392 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1396 extended_mips16_next_pc (CORE_ADDR pc
,
1397 unsigned int extension
,
1400 int op
= (insn
>> 11);
1403 case 2: /* Branch */
1406 struct upk_mips16 upk
;
1407 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1408 offset
= upk
.offset
;
1414 pc
+= (offset
<< 1) + 2;
1417 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1419 struct upk_mips16 upk
;
1420 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1421 pc
= add_offset_16 (pc
, upk
.offset
);
1422 if ((insn
>> 10) & 0x01) /* Exchange mode */
1423 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1430 struct upk_mips16 upk
;
1432 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1433 reg
= read_signed_register (upk
.regx
);
1435 pc
+= (upk
.offset
<< 1) + 2;
1442 struct upk_mips16 upk
;
1444 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1445 reg
= read_signed_register (upk
.regx
);
1447 pc
+= (upk
.offset
<< 1) + 2;
1452 case 12: /* I8 Formats btez btnez */
1454 struct upk_mips16 upk
;
1456 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1457 /* upk.regx contains the opcode */
1458 reg
= read_signed_register (24); /* Test register is 24 */
1459 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1460 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1461 /* pc = add_offset_16(pc,upk.offset) ; */
1462 pc
+= (upk
.offset
<< 1) + 2;
1467 case 29: /* RR Formats JR, JALR, JALR-RA */
1469 struct upk_mips16 upk
;
1470 /* upk.fmt = rrtype; */
1475 upk
.regx
= (insn
>> 8) & 0x07;
1476 upk
.regy
= (insn
>> 5) & 0x07;
1484 break; /* Function return instruction */
1490 break; /* BOGUS Guess */
1492 pc
= read_signed_register (reg
);
1499 /* This is an instruction extension. Fetch the real instruction
1500 (which follows the extension) and decode things based on
1504 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1517 mips16_next_pc (CORE_ADDR pc
)
1519 unsigned int insn
= fetch_mips_16 (pc
);
1520 return extended_mips16_next_pc (pc
, 0, insn
);
1523 /* The mips_next_pc function supports single_step when the remote
1524 target monitor or stub is not developed enough to do a single_step.
1525 It works by decoding the current instruction and predicting where a
1526 branch will go. This isnt hard because all the data is available.
1527 The MIPS32 and MIPS16 variants are quite different */
1529 mips_next_pc (CORE_ADDR pc
)
1532 return mips16_next_pc (pc
);
1534 return mips32_next_pc (pc
);
1537 /* Set up the 'saved_regs' array. This is a data structure containing
1538 the addresses on the stack where each register has been saved, for
1539 each stack frame. Registers that have not been saved will have
1540 zero here. The stack pointer register is special: rather than the
1541 address where the stack register has been saved,
1542 saved_regs[SP_REGNUM] will have the actual value of the previous
1543 frame's stack register. */
1546 mips_find_saved_regs (struct frame_info
*fci
)
1549 /* r0 bit means kernel trap */
1551 /* What registers have been saved? Bitmasks. */
1552 unsigned long gen_mask
, float_mask
;
1553 mips_extra_func_info_t proc_desc
;
1555 CORE_ADDR
*saved_regs
;
1557 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1559 saved_regs
= frame_saved_regs_zalloc (fci
);
1561 /* If it is the frame for sigtramp, the saved registers are located
1562 in a sigcontext structure somewhere on the stack. If the stack
1563 layout for sigtramp changes we might have to change these
1564 constants and the companion fixup_sigtramp in mdebugread.c */
1565 #ifndef SIGFRAME_BASE
1566 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1567 above the sigtramp frame. */
1568 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1569 /* FIXME! Are these correct?? */
1570 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1571 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1572 #define SIGFRAME_FPREGSAVE_OFF \
1573 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1575 #ifndef SIGFRAME_REG_SIZE
1576 /* FIXME! Is this correct?? */
1577 #define SIGFRAME_REG_SIZE mips_regsize (current_gdbarch)
1579 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1581 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1583 CORE_ADDR reg_position
= (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
1584 + ireg
* SIGFRAME_REG_SIZE
);
1585 set_reg_offset (saved_regs
, ireg
, reg_position
);
1587 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1589 CORE_ADDR reg_position
= (get_frame_base (fci
)
1590 + SIGFRAME_FPREGSAVE_OFF
1591 + ireg
* SIGFRAME_REG_SIZE
);
1592 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
, reg_position
);
1595 set_reg_offset (saved_regs
, PC_REGNUM
, get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1596 /* SP_REGNUM, contains the value and not the address. */
1597 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1601 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1602 if (proc_desc
== NULL
)
1603 /* I'm not sure how/whether this can happen. Normally when we
1604 can't find a proc_desc, we "synthesize" one using
1605 heuristic_proc_desc and set the saved_regs right away. */
1608 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1609 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1610 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1612 if (/* In any frame other than the innermost or a frame interrupted
1613 by a signal, we assume that all registers have been saved.
1614 This assumes that all register saves in a function happen
1615 before the first function call. */
1616 (get_next_frame (fci
) == NULL
1617 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1619 /* In a dummy frame we know exactly where things are saved. */
1620 && !PROC_DESC_IS_DUMMY (proc_desc
)
1622 /* Don't bother unless we are inside a function prologue.
1623 Outside the prologue, we know where everything is. */
1625 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1627 /* Not sure exactly what kernel_trap means, but if it means the
1628 kernel saves the registers without a prologue doing it, we
1629 better not examine the prologue to see whether registers
1630 have been saved yet. */
1633 /* We need to figure out whether the registers that the
1634 proc_desc claims are saved have been saved yet. */
1638 /* Bitmasks; set if we have found a save for the register. */
1639 unsigned long gen_save_found
= 0;
1640 unsigned long float_save_found
= 0;
1643 /* If the address is odd, assume this is MIPS16 code. */
1644 addr
= PROC_LOW_ADDR (proc_desc
);
1645 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1647 /* Scan through this function's instructions preceding the
1648 current PC, and look for those that save registers. */
1649 while (addr
< get_frame_pc (fci
))
1651 inst
= mips_fetch_instruction (addr
);
1652 if (pc_is_mips16 (addr
))
1653 mips16_decode_reg_save (inst
, &gen_save_found
);
1655 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1658 gen_mask
= gen_save_found
;
1659 float_mask
= float_save_found
;
1662 /* Fill in the offsets for the registers which gen_mask says were
1665 CORE_ADDR reg_position
= (get_frame_base (fci
)
1666 + PROC_REG_OFFSET (proc_desc
));
1667 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1668 if (gen_mask
& 0x80000000)
1670 set_reg_offset (saved_regs
, ireg
, reg_position
);
1671 reg_position
-= MIPS_SAVED_REGSIZE
;
1675 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1676 order of that normally used by gcc. Therefore, we have to fetch
1677 the first instruction of the function, and if it's an entry
1678 instruction that saves $s0 or $s1, correct their saved addresses. */
1679 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1681 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1682 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1686 int sreg_count
= (inst
>> 6) & 3;
1688 /* Check if the ra register was pushed on the stack. */
1689 CORE_ADDR reg_position
= (get_frame_base (fci
)
1690 + PROC_REG_OFFSET (proc_desc
));
1692 reg_position
-= MIPS_SAVED_REGSIZE
;
1694 /* Check if the s0 and s1 registers were pushed on the
1696 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1698 set_reg_offset (saved_regs
, reg
, reg_position
);
1699 reg_position
-= MIPS_SAVED_REGSIZE
;
1704 /* Fill in the offsets for the registers which float_mask says were
1707 CORE_ADDR reg_position
= (get_frame_base (fci
)
1708 + PROC_FREG_OFFSET (proc_desc
));
1710 /* Fill in the offsets for the float registers which float_mask
1712 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1713 if (float_mask
& 0x80000000)
1715 if (MIPS_SAVED_REGSIZE
== 4 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1717 /* On a big endian 32 bit ABI, floating point registers
1718 are paired to form doubles such that the most
1719 significant part is in $f[N+1] and the least
1720 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1721 registers are also spilled as a pair and stored as a
1724 When little-endian the least significant part is
1725 stored first leading to the memory order $f[N] and
1728 Unfortunately, when big-endian the most significant
1729 part of the double is stored first, and the least
1730 significant is stored second. This leads to the
1731 registers being ordered in memory as firt $f[N+1] and
1734 For the big-endian case make certain that the
1735 addresses point at the correct (swapped) locations
1736 $f[N] and $f[N+1] pair (keep in mind that
1737 reg_position is decremented each time through the
1740 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
,
1741 reg_position
- MIPS_SAVED_REGSIZE
);
1743 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
,
1744 reg_position
+ MIPS_SAVED_REGSIZE
);
1747 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
, reg_position
);
1748 reg_position
-= MIPS_SAVED_REGSIZE
;
1751 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1754 /* SP_REGNUM, contains the value and not the address. */
1755 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1759 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1761 /* Always a pseudo. */
1762 gdb_assert (regno
>= NUM_REGS
);
1766 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1769 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1770 /* The SP_REGNUM is special, its value is stored in saved_regs.
1771 In fact, it is so special that it can even only be fetched
1772 using a raw register number! Once this code as been converted
1773 to frame-unwind the problem goes away. */
1774 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1776 return frame_unwind_register_signed (fi
, regno
);
1780 /* mips_addr_bits_remove - remove useless address bits */
1783 mips_addr_bits_remove (CORE_ADDR addr
)
1785 if (mips_mask_address_p ()
1786 && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1787 /* This hack is a work-around for existing boards using PMON, the
1788 simulator, and any other 64-bit targets that doesn't have true
1789 64-bit addressing. On these targets, the upper 32 bits of
1790 addresses are ignored by the hardware. Thus, the PC or SP are
1791 likely to have been sign extended to all 1s by instruction
1792 sequences that load 32-bit addresses. For example, a typical
1793 piece of code that loads an address is this:
1795 lui $r2, <upper 16 bits>
1796 ori $r2, <lower 16 bits>
1798 But the lui sign-extends the value such that the upper 32 bits
1799 may be all 1s. The workaround is simply to mask off these
1800 bits. In the future, gcc may be changed to support true 64-bit
1801 addressing, and this masking will have to be disabled. */
1802 return addr
&= 0xffffffffUL
;
1807 /* mips_software_single_step() is called just before we want to resume
1808 the inferior, if we want to single-step it but there is no hardware
1809 or kernel single-step support (MIPS on GNU/Linux for example). We find
1810 the target of the coming instruction and breakpoint it.
1812 single_step is also called just after the inferior stops. If we had
1813 set up a simulated single-step, we undo our damage. */
1816 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1818 static CORE_ADDR next_pc
;
1819 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1820 static binsn_quantum break_mem
;
1823 if (insert_breakpoints_p
)
1825 pc
= read_register (PC_REGNUM
);
1826 next_pc
= mips_next_pc (pc
);
1828 target_insert_breakpoint (next_pc
, break_mem
);
1831 target_remove_breakpoint (next_pc
, break_mem
);
1835 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1840 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1841 : get_next_frame (prev
)
1842 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
))
1844 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1845 return tmp
? tmp
: pc
;
1850 mips_frame_saved_pc (struct frame_info
*frame
)
1854 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1857 /* Always unwind the cooked PC register value. */
1858 frame_unwind_signed_register (frame
, NUM_REGS
+ PC_REGNUM
, &tmp
);
1863 mips_extra_func_info_t proc_desc
1864 = get_frame_extra_info (frame
)->proc_desc
;
1865 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1866 saved_pc
= read_memory_integer (get_frame_base (frame
) - MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1869 /* We have to get the saved pc from the sigcontext if it is
1870 a signal handler frame. */
1871 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1872 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1873 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1876 return ADDR_BITS_REMOVE (saved_pc
);
1879 static struct mips_extra_func_info temp_proc_desc
;
1881 /* This hack will go away once the get_prev_frame() code has been
1882 modified to set the frame's type first. That is BEFORE init extra
1883 frame info et.al. is called. This is because it will become
1884 possible to skip the init extra info call for sigtramp and dummy
1886 static CORE_ADDR
*temp_saved_regs
;
1888 /* Set a register's saved stack address in temp_saved_regs. If an
1889 address has already been set for this register, do nothing; this
1890 way we will only recognize the first save of a given register in a
1893 For simplicity, save the address in both [0 .. NUM_REGS) and
1894 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1895 is used as it is only second range (the ABI instead of ISA
1896 registers) that comes into play when finding saved registers in a
1900 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1902 if (saved_regs
[regno
] == 0)
1904 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1905 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1910 /* Test whether the PC points to the return instruction at the
1911 end of a function. */
1914 mips_about_to_return (CORE_ADDR pc
)
1916 if (pc_is_mips16 (pc
))
1917 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1918 generates a "jr $ra"; other times it generates code to load
1919 the return address from the stack to an accessible register (such
1920 as $a3), then a "jr" using that register. This second case
1921 is almost impossible to distinguish from an indirect jump
1922 used for switch statements, so we don't even try. */
1923 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1925 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1929 /* This fencepost looks highly suspicious to me. Removing it also
1930 seems suspicious as it could affect remote debugging across serial
1934 heuristic_proc_start (CORE_ADDR pc
)
1941 pc
= ADDR_BITS_REMOVE (pc
);
1943 fence
= start_pc
- heuristic_fence_post
;
1947 if (heuristic_fence_post
== UINT_MAX
1948 || fence
< VM_MIN_ADDRESS
)
1949 fence
= VM_MIN_ADDRESS
;
1951 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1953 /* search back for previous return */
1954 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1955 if (start_pc
< fence
)
1957 /* It's not clear to me why we reach this point when
1958 stop_soon, but with this test, at least we
1959 don't print out warnings for every child forked (eg, on
1960 decstation). 22apr93 rich@cygnus.com. */
1961 if (stop_soon
== NO_STOP_QUIETLY
)
1963 static int blurb_printed
= 0;
1965 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1970 /* This actually happens frequently in embedded
1971 development, when you first connect to a board
1972 and your stack pointer and pc are nowhere in
1973 particular. This message needs to give people
1974 in that situation enough information to
1975 determine that it's no big deal. */
1976 printf_filtered ("\n\
1977 GDB is unable to find the start of the function at 0x%s\n\
1978 and thus can't determine the size of that function's stack frame.\n\
1979 This means that GDB may be unable to access that stack frame, or\n\
1980 the frames below it.\n\
1981 This problem is most likely caused by an invalid program counter or\n\
1983 However, if you think GDB should simply search farther back\n\
1984 from 0x%s for code which looks like the beginning of a\n\
1985 function, you can increase the range of the search using the `set\n\
1986 heuristic-fence-post' command.\n",
1987 paddr_nz (pc
), paddr_nz (pc
));
1994 else if (pc_is_mips16 (start_pc
))
1996 unsigned short inst
;
1998 /* On MIPS16, any one of the following is likely to be the
1999 start of a function:
2003 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2004 inst
= mips_fetch_instruction (start_pc
);
2005 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2006 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2007 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2008 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2010 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2011 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2016 else if (mips_about_to_return (start_pc
))
2018 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2025 /* Fetch the immediate value from a MIPS16 instruction.
2026 If the previous instruction was an EXTEND, use it to extend
2027 the upper bits of the immediate value. This is a helper function
2028 for mips16_heuristic_proc_desc. */
2031 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2032 unsigned short inst
, /* current instruction */
2033 int nbits
, /* number of bits in imm field */
2034 int scale
, /* scale factor to be applied to imm */
2035 int is_signed
) /* is the imm field signed? */
2039 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2041 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2042 if (offset
& 0x8000) /* check for negative extend */
2043 offset
= 0 - (0x10000 - (offset
& 0xffff));
2044 return offset
| (inst
& 0x1f);
2048 int max_imm
= 1 << nbits
;
2049 int mask
= max_imm
- 1;
2050 int sign_bit
= max_imm
>> 1;
2052 offset
= inst
& mask
;
2053 if (is_signed
&& (offset
& sign_bit
))
2054 offset
= 0 - (max_imm
- offset
);
2055 return offset
* scale
;
2060 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2061 stream from start_pc to limit_pc. */
2064 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2065 struct frame_info
*next_frame
, CORE_ADDR sp
)
2068 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2069 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2070 unsigned inst
= 0; /* current instruction */
2071 unsigned entry_inst
= 0; /* the entry instruction */
2074 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2075 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2077 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2079 /* Save the previous instruction. If it's an EXTEND, we'll extract
2080 the immediate offset extension from it in mips16_get_imm. */
2083 /* Fetch and decode the instruction. */
2084 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2085 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2086 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2088 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2089 if (offset
< 0) /* negative stack adjustment? */
2090 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2092 /* Exit loop if a positive stack adjustment is found, which
2093 usually means that the stack cleanup code in the function
2094 epilogue is reached. */
2097 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2099 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2100 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2101 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2102 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2104 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2106 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2107 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2108 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2109 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2111 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2113 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2114 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2115 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2117 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2119 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2120 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2121 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2123 else if (inst
== 0x673d) /* move $s1, $sp */
2126 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2128 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2130 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2131 frame_addr
= sp
+ offset
;
2132 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2133 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2135 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2137 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2138 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2139 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2140 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2142 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2144 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2145 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2146 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2147 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2149 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2150 entry_inst
= inst
; /* save for later processing */
2151 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2152 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2155 /* The entry instruction is typically the first instruction in a function,
2156 and it stores registers at offsets relative to the value of the old SP
2157 (before the prologue). But the value of the sp parameter to this
2158 function is the new SP (after the prologue has been executed). So we
2159 can't calculate those offsets until we've seen the entire prologue,
2160 and can calculate what the old SP must have been. */
2161 if (entry_inst
!= 0)
2163 int areg_count
= (entry_inst
>> 8) & 7;
2164 int sreg_count
= (entry_inst
>> 6) & 3;
2166 /* The entry instruction always subtracts 32 from the SP. */
2167 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2169 /* Now we can calculate what the SP must have been at the
2170 start of the function prologue. */
2171 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2173 /* Check if a0-a3 were saved in the caller's argument save area. */
2174 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2176 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2177 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2178 offset
+= MIPS_SAVED_REGSIZE
;
2181 /* Check if the ra register was pushed on the stack. */
2183 if (entry_inst
& 0x20)
2185 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2186 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2187 offset
-= MIPS_SAVED_REGSIZE
;
2190 /* Check if the s0 and s1 registers were pushed on the stack. */
2191 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2193 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2194 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2195 offset
-= MIPS_SAVED_REGSIZE
;
2201 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2202 struct frame_info
*next_frame
, CORE_ADDR sp
)
2205 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2207 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2208 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2209 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2210 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2211 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2213 unsigned long inst
, high_word
, low_word
;
2216 /* Fetch the instruction. */
2217 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2219 /* Save some code by pre-extracting some useful fields. */
2220 high_word
= (inst
>> 16) & 0xffff;
2221 low_word
= inst
& 0xffff;
2222 reg
= high_word
& 0x1f;
2224 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2225 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2226 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2228 if (low_word
& 0x8000) /* negative stack adjustment? */
2229 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2231 /* Exit loop if a positive stack adjustment is found, which
2232 usually means that the stack cleanup code in the function
2233 epilogue is reached. */
2236 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2238 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2239 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2241 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2243 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2244 but the register size used is only 32 bits. Make the address
2245 for the saved register point to the lower 32 bits. */
2246 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2247 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2249 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2251 /* Old gcc frame, r30 is virtual frame pointer. */
2252 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2253 frame_addr
= sp
+ low_word
;
2254 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2256 unsigned alloca_adjust
;
2257 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2258 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2259 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2260 if (alloca_adjust
> 0)
2262 /* FP > SP + frame_size. This may be because
2263 * of an alloca or somethings similar.
2264 * Fix sp to "pre-alloca" value, and try again.
2266 sp
+= alloca_adjust
;
2271 /* move $30,$sp. With different versions of gas this will be either
2272 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2273 Accept any one of these. */
2274 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2276 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2277 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2279 unsigned alloca_adjust
;
2280 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2281 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2282 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2283 if (alloca_adjust
> 0)
2285 /* FP > SP + frame_size. This may be because
2286 * of an alloca or somethings similar.
2287 * Fix sp to "pre-alloca" value, and try again.
2289 sp
+= alloca_adjust
;
2294 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2296 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2297 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2302 static mips_extra_func_info_t
2303 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2304 struct frame_info
*next_frame
, int cur_frame
)
2309 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2315 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2316 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2317 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2318 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2319 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2320 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2322 if (start_pc
+ 200 < limit_pc
)
2323 limit_pc
= start_pc
+ 200;
2324 if (pc_is_mips16 (start_pc
))
2325 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2327 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2328 return &temp_proc_desc
;
2331 struct mips_objfile_private
2337 /* Global used to communicate between non_heuristic_proc_desc and
2338 compare_pdr_entries within qsort (). */
2339 static bfd
*the_bfd
;
2342 compare_pdr_entries (const void *a
, const void *b
)
2344 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2345 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2349 else if (lhs
== rhs
)
2355 static mips_extra_func_info_t
2356 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2358 CORE_ADDR startaddr
;
2359 mips_extra_func_info_t proc_desc
;
2360 struct block
*b
= block_for_pc (pc
);
2362 struct obj_section
*sec
;
2363 struct mips_objfile_private
*priv
;
2365 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2368 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2370 *addrptr
= startaddr
;
2374 sec
= find_pc_section (pc
);
2377 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2379 /* Search the ".pdr" section generated by GAS. This includes most of
2380 the information normally found in ECOFF PDRs. */
2382 the_bfd
= sec
->objfile
->obfd
;
2384 && (the_bfd
->format
== bfd_object
2385 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2386 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2388 /* Right now GAS only outputs the address as a four-byte sequence.
2389 This means that we should not bother with this method on 64-bit
2390 targets (until that is fixed). */
2392 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2393 sizeof (struct mips_objfile_private
));
2395 sec
->objfile
->obj_private
= priv
;
2397 else if (priv
== NULL
)
2401 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2402 sizeof (struct mips_objfile_private
));
2404 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2407 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2408 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2410 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2411 priv
->contents
, 0, priv
->size
);
2413 /* In general, the .pdr section is sorted. However, in the
2414 presence of multiple code sections (and other corner cases)
2415 it can become unsorted. Sort it so that we can use a faster
2417 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2422 sec
->objfile
->obj_private
= priv
;
2426 if (priv
->size
!= 0)
2432 high
= priv
->size
/ 32;
2438 mid
= (low
+ high
) / 2;
2440 ptr
= priv
->contents
+ mid
* 32;
2441 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2442 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2443 SECT_OFF_TEXT (sec
->objfile
));
2444 if (pdr_pc
== startaddr
)
2446 if (pdr_pc
> startaddr
)
2451 while (low
!= high
);
2455 struct symbol
*sym
= find_pc_function (pc
);
2457 /* Fill in what we need of the proc_desc. */
2458 proc_desc
= (mips_extra_func_info_t
)
2459 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2460 sizeof (struct mips_extra_func_info
));
2461 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2463 /* Only used for dummy frames. */
2464 PROC_HIGH_ADDR (proc_desc
) = 0;
2466 PROC_FRAME_OFFSET (proc_desc
)
2467 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2468 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2470 PROC_FRAME_ADJUST (proc_desc
) = 0;
2471 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2473 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2475 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2477 PROC_FREG_OFFSET (proc_desc
)
2478 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2479 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2481 proc_desc
->pdr
.isym
= (long) sym
;
2491 if (startaddr
> BLOCK_START (b
))
2493 /* This is the "pathological" case referred to in a comment in
2494 print_frame_info. It might be better to move this check into
2499 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2501 /* If we never found a PDR for this function in symbol reading, then
2502 examine prologues to find the information. */
2505 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2506 if (PROC_FRAME_REG (proc_desc
) == -1)
2516 static mips_extra_func_info_t
2517 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2519 mips_extra_func_info_t proc_desc
;
2520 CORE_ADDR startaddr
= 0;
2522 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2526 /* IF this is the topmost frame AND
2527 * (this proc does not have debugging information OR
2528 * the PC is in the procedure prologue)
2529 * THEN create a "heuristic" proc_desc (by analyzing
2530 * the actual code) to replace the "official" proc_desc.
2532 if (next_frame
== NULL
)
2534 struct symtab_and_line val
;
2535 struct symbol
*proc_symbol
=
2536 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2540 val
= find_pc_line (BLOCK_START
2541 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2543 val
.pc
= val
.end
? val
.end
: pc
;
2545 if (!proc_symbol
|| pc
< val
.pc
)
2547 mips_extra_func_info_t found_heuristic
=
2548 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2549 pc
, next_frame
, cur_frame
);
2550 if (found_heuristic
)
2551 proc_desc
= found_heuristic
;
2557 /* Is linked_proc_desc_table really necessary? It only seems to be used
2558 by procedure call dummys. However, the procedures being called ought
2559 to have their own proc_descs, and even if they don't,
2560 heuristic_proc_desc knows how to create them! */
2562 struct linked_proc_info
*link
;
2564 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2565 if (PROC_LOW_ADDR (&link
->info
) <= pc
2566 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2570 startaddr
= heuristic_proc_start (pc
);
2573 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2579 get_frame_pointer (struct frame_info
*frame
,
2580 mips_extra_func_info_t proc_desc
)
2582 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2583 + PROC_FRAME_OFFSET (proc_desc
)
2584 - PROC_FRAME_ADJUST (proc_desc
));
2587 static mips_extra_func_info_t cached_proc_desc
;
2590 mips_frame_chain (struct frame_info
*frame
)
2592 mips_extra_func_info_t proc_desc
;
2594 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2596 if (saved_pc
== 0 || deprecated_inside_entry_file (saved_pc
))
2599 /* Check if the PC is inside a call stub. If it is, fetch the
2600 PC of the caller of that stub. */
2601 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2604 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2606 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2607 is well, frame->frame the bottom of the current frame will
2608 contain that value. */
2609 return get_frame_base (frame
);
2612 /* Look up the procedure descriptor for this PC. */
2613 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2617 cached_proc_desc
= proc_desc
;
2619 /* If no frame pointer and frame size is zero, we must be at end
2620 of stack (or otherwise hosed). If we don't check frame size,
2621 we loop forever if we see a zero size frame. */
2622 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2623 && PROC_FRAME_OFFSET (proc_desc
) == 0
2624 /* The previous frame from a sigtramp frame might be frameless
2625 and have frame size zero. */
2626 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2627 /* For a generic dummy frame, let get_frame_pointer() unwind a
2628 register value saved as part of the dummy frame call. */
2629 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2632 return get_frame_pointer (frame
, proc_desc
);
2636 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2639 mips_extra_func_info_t proc_desc
;
2641 if (get_frame_type (fci
) == DUMMY_FRAME
)
2644 /* Use proc_desc calculated in frame_chain. When there is no
2645 next frame, i.e, get_next_frame (fci) == NULL, we call
2646 find_proc_desc () to calculate it, passing an explicit
2647 NULL as the frame parameter. */
2649 get_next_frame (fci
)
2651 : find_proc_desc (get_frame_pc (fci
),
2652 NULL
/* i.e, get_next_frame (fci) */,
2655 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2657 deprecated_set_frame_saved_regs_hack (fci
, NULL
);
2658 get_frame_extra_info (fci
)->proc_desc
=
2659 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2662 /* Fixup frame-pointer - only needed for top frame */
2663 /* This may not be quite right, if proc has a real frame register.
2664 Get the value of the frame relative sp, procedure might have been
2665 interrupted by a signal at it's very start. */
2666 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2667 && !PROC_DESC_IS_DUMMY (proc_desc
))
2668 deprecated_update_frame_base_hack (fci
, read_next_frame_reg (get_next_frame (fci
), NUM_REGS
+ SP_REGNUM
));
2669 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2670 /* Do not ``fix'' fci->frame. It will have the value of the
2671 generic dummy frame's top-of-stack (since the draft
2672 fci->frame is obtained by returning the unwound stack
2673 pointer) and that is what we want. That way the fci->frame
2674 value will match the top-of-stack value that was saved as
2675 part of the dummy frames data. */
2678 deprecated_update_frame_base_hack (fci
, get_frame_pointer (get_next_frame (fci
), proc_desc
));
2680 if (proc_desc
== &temp_proc_desc
)
2684 /* Do not set the saved registers for a sigtramp frame,
2685 mips_find_saved_registers will do that for us. We can't
2686 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2688 /* FIXME: cagney/2002-11-18: This problem will go away once
2689 frame.c:get_prev_frame() is modified to set the frame's
2690 type before calling functions like this. */
2691 find_pc_partial_function (get_frame_pc (fci
), &name
,
2692 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2693 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2695 frame_saved_regs_zalloc (fci
);
2696 /* Set value of previous frame's stack pointer.
2697 Remember that saved_regs[SP_REGNUM] is special in
2698 that it contains the value of the stack pointer
2699 register. The other saved_regs values are addresses
2700 (in the inferior) at which a given register's value
2702 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2703 get_frame_base (fci
));
2704 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2705 temp_saved_regs
[RA_REGNUM
]);
2706 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2707 SIZEOF_FRAME_SAVED_REGS
);
2711 /* hack: if argument regs are saved, guess these contain args */
2712 /* assume we can't tell how many args for now */
2713 get_frame_extra_info (fci
)->num_args
= -1;
2714 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2716 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2718 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2725 /* MIPS stack frames are almost impenetrable. When execution stops,
2726 we basically have to look at symbol information for the function
2727 that we stopped in, which tells us *which* register (if any) is
2728 the base of the frame pointer, and what offset from that register
2729 the frame itself is at.
2731 This presents a problem when trying to examine a stack in memory
2732 (that isn't executing at the moment), using the "frame" command. We
2733 don't have a PC, nor do we have any registers except SP.
2735 This routine takes two arguments, SP and PC, and tries to make the
2736 cached frames look as if these two arguments defined a frame on the
2737 cache. This allows the rest of info frame to extract the important
2738 arguments without difficulty. */
2741 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2744 error ("MIPS frame specifications require two arguments: sp and pc");
2746 return create_new_frame (argv
[0], argv
[1]);
2749 /* According to the current ABI, should the type be passed in a
2750 floating-point register (assuming that there is space)? When there
2751 is no FPU, FP are not even considered as possibile candidates for
2752 FP registers and, consequently this returns false - forces FP
2753 arguments into integer registers. */
2756 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2758 return ((typecode
== TYPE_CODE_FLT
2760 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2761 && TYPE_NFIELDS (arg_type
) == 1
2762 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2763 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2766 /* On o32, argument passing in GPRs depends on the alignment of the type being
2767 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2770 mips_type_needs_double_align (struct type
*type
)
2772 enum type_code typecode
= TYPE_CODE (type
);
2774 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2776 else if (typecode
== TYPE_CODE_STRUCT
)
2778 if (TYPE_NFIELDS (type
) < 1)
2780 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2782 else if (typecode
== TYPE_CODE_UNION
)
2786 n
= TYPE_NFIELDS (type
);
2787 for (i
= 0; i
< n
; i
++)
2788 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2795 /* Adjust the address downward (direction of stack growth) so that it
2796 is correctly aligned for a new stack frame. */
2798 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2800 return align_down (addr
, 16);
2804 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2805 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2806 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2807 CORE_ADDR struct_addr
)
2813 int stack_offset
= 0;
2815 /* For shared libraries, "t9" needs to point at the function
2817 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2819 /* Set the return address register to point to the entry point of
2820 the program, where a breakpoint lies in wait. */
2821 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2823 /* First ensure that the stack and structure return address (if any)
2824 are properly aligned. The stack has to be at least 64-bit
2825 aligned even on 32-bit machines, because doubles must be 64-bit
2826 aligned. For n32 and n64, stack frames need to be 128-bit
2827 aligned, so we round to this widest known alignment. */
2829 sp
= align_down (sp
, 16);
2830 struct_addr
= align_down (struct_addr
, 16);
2832 /* Now make space on the stack for the args. We allocate more
2833 than necessary for EABI, because the first few arguments are
2834 passed in registers, but that's OK. */
2835 for (argnum
= 0; argnum
< nargs
; argnum
++)
2836 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2837 MIPS_STACK_ARGSIZE
);
2838 sp
-= align_up (len
, 16);
2841 fprintf_unfiltered (gdb_stdlog
,
2842 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2843 paddr_nz (sp
), (long) align_up (len
, 16));
2845 /* Initialize the integer and float register pointers. */
2847 float_argreg
= FPA0_REGNUM
;
2849 /* The struct_return pointer occupies the first parameter-passing reg. */
2853 fprintf_unfiltered (gdb_stdlog
,
2854 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2855 argreg
, paddr_nz (struct_addr
));
2856 write_register (argreg
++, struct_addr
);
2859 /* Now load as many as possible of the first arguments into
2860 registers, and push the rest onto the stack. Loop thru args
2861 from first to last. */
2862 for (argnum
= 0; argnum
< nargs
; argnum
++)
2865 char valbuf
[MAX_REGISTER_SIZE
];
2866 struct value
*arg
= args
[argnum
];
2867 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2868 int len
= TYPE_LENGTH (arg_type
);
2869 enum type_code typecode
= TYPE_CODE (arg_type
);
2872 fprintf_unfiltered (gdb_stdlog
,
2873 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2874 argnum
+ 1, len
, (int) typecode
);
2876 /* The EABI passes structures that do not fit in a register by
2878 if (len
> MIPS_SAVED_REGSIZE
2879 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2881 store_unsigned_integer (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2882 typecode
= TYPE_CODE_PTR
;
2883 len
= MIPS_SAVED_REGSIZE
;
2886 fprintf_unfiltered (gdb_stdlog
, " push");
2889 val
= (char *) VALUE_CONTENTS (arg
);
2891 /* 32-bit ABIs always start floating point arguments in an
2892 even-numbered floating point register. Round the FP register
2893 up before the check to see if there are any FP registers
2894 left. Non MIPS_EABI targets also pass the FP in the integer
2895 registers so also round up normal registers. */
2896 if (!FP_REGISTER_DOUBLE
2897 && fp_register_arg_p (typecode
, arg_type
))
2899 if ((float_argreg
& 1))
2903 /* Floating point arguments passed in registers have to be
2904 treated specially. On 32-bit architectures, doubles
2905 are passed in register pairs; the even register gets
2906 the low word, and the odd register gets the high word.
2907 On non-EABI processors, the first two floating point arguments are
2908 also copied to general registers, because MIPS16 functions
2909 don't use float registers for arguments. This duplication of
2910 arguments in general registers can't hurt non-MIPS16 functions
2911 because those registers are normally skipped. */
2912 /* MIPS_EABI squeezes a struct that contains a single floating
2913 point value into an FP register instead of pushing it onto the
2915 if (fp_register_arg_p (typecode
, arg_type
)
2916 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2918 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2920 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2921 unsigned long regval
;
2923 /* Write the low word of the double to the even register(s). */
2924 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2926 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2927 float_argreg
, phex (regval
, 4));
2928 write_register (float_argreg
++, regval
);
2930 /* Write the high word of the double to the odd register(s). */
2931 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2933 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2934 float_argreg
, phex (regval
, 4));
2935 write_register (float_argreg
++, regval
);
2939 /* This is a floating point value that fits entirely
2940 in a single register. */
2941 /* On 32 bit ABI's the float_argreg is further adjusted
2942 above to ensure that it is even register aligned. */
2943 LONGEST regval
= extract_unsigned_integer (val
, len
);
2945 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2946 float_argreg
, phex (regval
, len
));
2947 write_register (float_argreg
++, regval
);
2952 /* Copy the argument to general registers or the stack in
2953 register-sized pieces. Large arguments are split between
2954 registers and stack. */
2955 /* Note: structs whose size is not a multiple of
2956 mips_regsize() are treated specially: Irix cc passes them
2957 in registers where gcc sometimes puts them on the stack.
2958 For maximum compatibility, we will put them in both
2960 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2961 (len
% MIPS_SAVED_REGSIZE
!= 0));
2963 /* Note: Floating-point values that didn't fit into an FP
2964 register are only written to memory. */
2967 /* Remember if the argument was written to the stack. */
2968 int stack_used_p
= 0;
2970 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2973 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2976 /* Write this portion of the argument to the stack. */
2977 if (argreg
> MIPS_LAST_ARG_REGNUM
2979 || fp_register_arg_p (typecode
, arg_type
))
2981 /* Should shorter than int integer values be
2982 promoted to int before being stored? */
2983 int longword_offset
= 0;
2986 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2988 if (MIPS_STACK_ARGSIZE
== 8 &&
2989 (typecode
== TYPE_CODE_INT
||
2990 typecode
== TYPE_CODE_PTR
||
2991 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2992 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2993 else if ((typecode
== TYPE_CODE_STRUCT
||
2994 typecode
== TYPE_CODE_UNION
) &&
2995 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2996 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3001 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3002 paddr_nz (stack_offset
));
3003 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3004 paddr_nz (longword_offset
));
3007 addr
= sp
+ stack_offset
+ longword_offset
;
3012 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3014 for (i
= 0; i
< partial_len
; i
++)
3016 fprintf_unfiltered (gdb_stdlog
, "%02x",
3020 write_memory (addr
, val
, partial_len
);
3023 /* Note!!! This is NOT an else clause. Odd sized
3024 structs may go thru BOTH paths. Floating point
3025 arguments will not. */
3026 /* Write this portion of the argument to a general
3027 purpose register. */
3028 if (argreg
<= MIPS_LAST_ARG_REGNUM
3029 && !fp_register_arg_p (typecode
, arg_type
))
3031 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3034 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3036 phex (regval
, MIPS_SAVED_REGSIZE
));
3037 write_register (argreg
, regval
);
3044 /* Compute the the offset into the stack at which we
3045 will copy the next parameter.
3047 In the new EABI (and the NABI32), the stack_offset
3048 only needs to be adjusted when it has been used. */
3051 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3055 fprintf_unfiltered (gdb_stdlog
, "\n");
3058 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3060 /* Return adjusted stack pointer. */
3064 /* N32/N64 version of push_dummy_call. */
3067 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3068 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3069 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3070 CORE_ADDR struct_addr
)
3076 int stack_offset
= 0;
3078 /* For shared libraries, "t9" needs to point at the function
3080 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3082 /* Set the return address register to point to the entry point of
3083 the program, where a breakpoint lies in wait. */
3084 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3086 /* First ensure that the stack and structure return address (if any)
3087 are properly aligned. The stack has to be at least 64-bit
3088 aligned even on 32-bit machines, because doubles must be 64-bit
3089 aligned. For n32 and n64, stack frames need to be 128-bit
3090 aligned, so we round to this widest known alignment. */
3092 sp
= align_down (sp
, 16);
3093 struct_addr
= align_down (struct_addr
, 16);
3095 /* Now make space on the stack for the args. */
3096 for (argnum
= 0; argnum
< nargs
; argnum
++)
3097 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3098 MIPS_STACK_ARGSIZE
);
3099 sp
-= align_up (len
, 16);
3102 fprintf_unfiltered (gdb_stdlog
,
3103 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3104 paddr_nz (sp
), (long) align_up (len
, 16));
3106 /* Initialize the integer and float register pointers. */
3108 float_argreg
= FPA0_REGNUM
;
3110 /* The struct_return pointer occupies the first parameter-passing reg. */
3114 fprintf_unfiltered (gdb_stdlog
,
3115 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3116 argreg
, paddr_nz (struct_addr
));
3117 write_register (argreg
++, struct_addr
);
3120 /* Now load as many as possible of the first arguments into
3121 registers, and push the rest onto the stack. Loop thru args
3122 from first to last. */
3123 for (argnum
= 0; argnum
< nargs
; argnum
++)
3126 char valbuf
[MAX_REGISTER_SIZE
];
3127 struct value
*arg
= args
[argnum
];
3128 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3129 int len
= TYPE_LENGTH (arg_type
);
3130 enum type_code typecode
= TYPE_CODE (arg_type
);
3133 fprintf_unfiltered (gdb_stdlog
,
3134 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3135 argnum
+ 1, len
, (int) typecode
);
3137 val
= (char *) VALUE_CONTENTS (arg
);
3139 if (fp_register_arg_p (typecode
, arg_type
)
3140 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3142 /* This is a floating point value that fits entirely
3143 in a single register. */
3144 /* On 32 bit ABI's the float_argreg is further adjusted
3145 above to ensure that it is even register aligned. */
3146 LONGEST regval
= extract_unsigned_integer (val
, len
);
3148 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3149 float_argreg
, phex (regval
, len
));
3150 write_register (float_argreg
++, regval
);
3153 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3154 argreg
, phex (regval
, len
));
3155 write_register (argreg
, regval
);
3160 /* Copy the argument to general registers or the stack in
3161 register-sized pieces. Large arguments are split between
3162 registers and stack. */
3163 /* Note: structs whose size is not a multiple of
3164 mips_regsize() are treated specially: Irix cc passes them
3165 in registers where gcc sometimes puts them on the stack.
3166 For maximum compatibility, we will put them in both
3168 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3169 (len
% MIPS_SAVED_REGSIZE
!= 0));
3170 /* Note: Floating-point values that didn't fit into an FP
3171 register are only written to memory. */
3174 /* Rememer if the argument was written to the stack. */
3175 int stack_used_p
= 0;
3176 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
3177 len
: MIPS_SAVED_REGSIZE
;
3180 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3183 /* Write this portion of the argument to the stack. */
3184 if (argreg
> MIPS_LAST_ARG_REGNUM
3186 || fp_register_arg_p (typecode
, arg_type
))
3188 /* Should shorter than int integer values be
3189 promoted to int before being stored? */
3190 int longword_offset
= 0;
3193 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3195 if (MIPS_STACK_ARGSIZE
== 8 &&
3196 (typecode
== TYPE_CODE_INT
||
3197 typecode
== TYPE_CODE_PTR
||
3198 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3199 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3204 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3205 paddr_nz (stack_offset
));
3206 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3207 paddr_nz (longword_offset
));
3210 addr
= sp
+ stack_offset
+ longword_offset
;
3215 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3217 for (i
= 0; i
< partial_len
; i
++)
3219 fprintf_unfiltered (gdb_stdlog
, "%02x",
3223 write_memory (addr
, val
, partial_len
);
3226 /* Note!!! This is NOT an else clause. Odd sized
3227 structs may go thru BOTH paths. Floating point
3228 arguments will not. */
3229 /* Write this portion of the argument to a general
3230 purpose register. */
3231 if (argreg
<= MIPS_LAST_ARG_REGNUM
3232 && !fp_register_arg_p (typecode
, arg_type
))
3234 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3236 /* A non-floating-point argument being passed in a
3237 general register. If a struct or union, and if
3238 the remaining length is smaller than the register
3239 size, we have to adjust the register value on
3242 It does not seem to be necessary to do the
3243 same for integral types.
3245 cagney/2001-07-23: gdb/179: Also, GCC, when
3246 outputting LE O32 with sizeof (struct) <
3247 MIPS_SAVED_REGSIZE, generates a left shift as
3248 part of storing the argument in a register a
3249 register (the left shift isn't generated when
3250 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3251 is quite possible that this is GCC contradicting
3252 the LE/O32 ABI, GDB has not been adjusted to
3253 accommodate this. Either someone needs to
3254 demonstrate that the LE/O32 ABI specifies such a
3255 left shift OR this new ABI gets identified as
3256 such and GDB gets tweaked accordingly. */
3258 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3259 && partial_len
< MIPS_SAVED_REGSIZE
3260 && (typecode
== TYPE_CODE_STRUCT
||
3261 typecode
== TYPE_CODE_UNION
))
3262 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3266 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3268 phex (regval
, MIPS_SAVED_REGSIZE
));
3269 write_register (argreg
, regval
);
3276 /* Compute the the offset into the stack at which we
3277 will copy the next parameter.
3279 In N32 (N64?), the stack_offset only needs to be
3280 adjusted when it has been used. */
3283 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3287 fprintf_unfiltered (gdb_stdlog
, "\n");
3290 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3292 /* Return adjusted stack pointer. */
3296 /* O32 version of push_dummy_call. */
3299 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3300 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3301 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3302 CORE_ADDR struct_addr
)
3308 int stack_offset
= 0;
3310 /* For shared libraries, "t9" needs to point at the function
3312 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3314 /* Set the return address register to point to the entry point of
3315 the program, where a breakpoint lies in wait. */
3316 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3318 /* First ensure that the stack and structure return address (if any)
3319 are properly aligned. The stack has to be at least 64-bit
3320 aligned even on 32-bit machines, because doubles must be 64-bit
3321 aligned. For n32 and n64, stack frames need to be 128-bit
3322 aligned, so we round to this widest known alignment. */
3324 sp
= align_down (sp
, 16);
3325 struct_addr
= align_down (struct_addr
, 16);
3327 /* Now make space on the stack for the args. */
3328 for (argnum
= 0; argnum
< nargs
; argnum
++)
3329 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3330 MIPS_STACK_ARGSIZE
);
3331 sp
-= align_up (len
, 16);
3334 fprintf_unfiltered (gdb_stdlog
,
3335 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3336 paddr_nz (sp
), (long) align_up (len
, 16));
3338 /* Initialize the integer and float register pointers. */
3340 float_argreg
= FPA0_REGNUM
;
3342 /* The struct_return pointer occupies the first parameter-passing reg. */
3346 fprintf_unfiltered (gdb_stdlog
,
3347 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3348 argreg
, paddr_nz (struct_addr
));
3349 write_register (argreg
++, struct_addr
);
3350 stack_offset
+= MIPS_STACK_ARGSIZE
;
3353 /* Now load as many as possible of the first arguments into
3354 registers, and push the rest onto the stack. Loop thru args
3355 from first to last. */
3356 for (argnum
= 0; argnum
< nargs
; argnum
++)
3359 char valbuf
[MAX_REGISTER_SIZE
];
3360 struct value
*arg
= args
[argnum
];
3361 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3362 int len
= TYPE_LENGTH (arg_type
);
3363 enum type_code typecode
= TYPE_CODE (arg_type
);
3366 fprintf_unfiltered (gdb_stdlog
,
3367 "mips_o32_push_dummy_call: %d len=%d type=%d",
3368 argnum
+ 1, len
, (int) typecode
);
3370 val
= (char *) VALUE_CONTENTS (arg
);
3372 /* 32-bit ABIs always start floating point arguments in an
3373 even-numbered floating point register. Round the FP register
3374 up before the check to see if there are any FP registers
3375 left. O32/O64 targets also pass the FP in the integer
3376 registers so also round up normal registers. */
3377 if (!FP_REGISTER_DOUBLE
3378 && fp_register_arg_p (typecode
, arg_type
))
3380 if ((float_argreg
& 1))
3384 /* Floating point arguments passed in registers have to be
3385 treated specially. On 32-bit architectures, doubles
3386 are passed in register pairs; the even register gets
3387 the low word, and the odd register gets the high word.
3388 On O32/O64, the first two floating point arguments are
3389 also copied to general registers, because MIPS16 functions
3390 don't use float registers for arguments. This duplication of
3391 arguments in general registers can't hurt non-MIPS16 functions
3392 because those registers are normally skipped. */
3394 if (fp_register_arg_p (typecode
, arg_type
)
3395 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3397 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3399 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3400 unsigned long regval
;
3402 /* Write the low word of the double to the even register(s). */
3403 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3405 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3406 float_argreg
, phex (regval
, 4));
3407 write_register (float_argreg
++, regval
);
3409 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3410 argreg
, phex (regval
, 4));
3411 write_register (argreg
++, regval
);
3413 /* Write the high word of the double to the odd register(s). */
3414 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3416 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3417 float_argreg
, phex (regval
, 4));
3418 write_register (float_argreg
++, regval
);
3421 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3422 argreg
, phex (regval
, 4));
3423 write_register (argreg
++, regval
);
3427 /* This is a floating point value that fits entirely
3428 in a single register. */
3429 /* On 32 bit ABI's the float_argreg is further adjusted
3430 above to ensure that it is even register aligned. */
3431 LONGEST regval
= extract_unsigned_integer (val
, len
);
3433 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3434 float_argreg
, phex (regval
, len
));
3435 write_register (float_argreg
++, regval
);
3436 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3437 registers for each argument. The below is (my
3438 guess) to ensure that the corresponding integer
3439 register has reserved the same space. */
3441 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3442 argreg
, phex (regval
, len
));
3443 write_register (argreg
, regval
);
3444 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3446 /* Reserve space for the FP register. */
3447 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3451 /* Copy the argument to general registers or the stack in
3452 register-sized pieces. Large arguments are split between
3453 registers and stack. */
3454 /* Note: structs whose size is not a multiple of
3455 mips_regsize() are treated specially: Irix cc passes them
3456 in registers where gcc sometimes puts them on the stack.
3457 For maximum compatibility, we will put them in both
3459 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3460 (len
% MIPS_SAVED_REGSIZE
!= 0));
3461 /* Structures should be aligned to eight bytes (even arg registers)
3462 on MIPS_ABI_O32, if their first member has double precision. */
3463 if (MIPS_SAVED_REGSIZE
< 8
3464 && mips_type_needs_double_align (arg_type
))
3469 /* Note: Floating-point values that didn't fit into an FP
3470 register are only written to memory. */
3473 /* Remember if the argument was written to the stack. */
3474 int stack_used_p
= 0;
3476 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3479 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3482 /* Write this portion of the argument to the stack. */
3483 if (argreg
> MIPS_LAST_ARG_REGNUM
3485 || fp_register_arg_p (typecode
, arg_type
))
3487 /* Should shorter than int integer values be
3488 promoted to int before being stored? */
3489 int longword_offset
= 0;
3492 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3494 if (MIPS_STACK_ARGSIZE
== 8 &&
3495 (typecode
== TYPE_CODE_INT
||
3496 typecode
== TYPE_CODE_PTR
||
3497 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3498 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3503 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3504 paddr_nz (stack_offset
));
3505 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3506 paddr_nz (longword_offset
));
3509 addr
= sp
+ stack_offset
+ longword_offset
;
3514 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3516 for (i
= 0; i
< partial_len
; i
++)
3518 fprintf_unfiltered (gdb_stdlog
, "%02x",
3522 write_memory (addr
, val
, partial_len
);
3525 /* Note!!! This is NOT an else clause. Odd sized
3526 structs may go thru BOTH paths. Floating point
3527 arguments will not. */
3528 /* Write this portion of the argument to a general
3529 purpose register. */
3530 if (argreg
<= MIPS_LAST_ARG_REGNUM
3531 && !fp_register_arg_p (typecode
, arg_type
))
3533 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3534 /* Value may need to be sign extended, because
3535 mips_regsize() != MIPS_SAVED_REGSIZE. */
3537 /* A non-floating-point argument being passed in a
3538 general register. If a struct or union, and if
3539 the remaining length is smaller than the register
3540 size, we have to adjust the register value on
3543 It does not seem to be necessary to do the
3544 same for integral types.
3546 Also don't do this adjustment on O64 binaries.
3548 cagney/2001-07-23: gdb/179: Also, GCC, when
3549 outputting LE O32 with sizeof (struct) <
3550 MIPS_SAVED_REGSIZE, generates a left shift as
3551 part of storing the argument in a register a
3552 register (the left shift isn't generated when
3553 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3554 is quite possible that this is GCC contradicting
3555 the LE/O32 ABI, GDB has not been adjusted to
3556 accommodate this. Either someone needs to
3557 demonstrate that the LE/O32 ABI specifies such a
3558 left shift OR this new ABI gets identified as
3559 such and GDB gets tweaked accordingly. */
3561 if (MIPS_SAVED_REGSIZE
< 8
3562 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3563 && partial_len
< MIPS_SAVED_REGSIZE
3564 && (typecode
== TYPE_CODE_STRUCT
||
3565 typecode
== TYPE_CODE_UNION
))
3566 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3570 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3572 phex (regval
, MIPS_SAVED_REGSIZE
));
3573 write_register (argreg
, regval
);
3576 /* Prevent subsequent floating point arguments from
3577 being passed in floating point registers. */
3578 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3584 /* Compute the the offset into the stack at which we
3585 will copy the next parameter.
3587 In older ABIs, the caller reserved space for
3588 registers that contained arguments. This was loosely
3589 refered to as their "home". Consequently, space is
3590 always allocated. */
3592 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3596 fprintf_unfiltered (gdb_stdlog
, "\n");
3599 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3601 /* Return adjusted stack pointer. */
3605 /* O64 version of push_dummy_call. */
3608 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3609 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3610 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3611 CORE_ADDR struct_addr
)
3617 int stack_offset
= 0;
3619 /* For shared libraries, "t9" needs to point at the function
3621 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3623 /* Set the return address register to point to the entry point of
3624 the program, where a breakpoint lies in wait. */
3625 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3627 /* First ensure that the stack and structure return address (if any)
3628 are properly aligned. The stack has to be at least 64-bit
3629 aligned even on 32-bit machines, because doubles must be 64-bit
3630 aligned. For n32 and n64, stack frames need to be 128-bit
3631 aligned, so we round to this widest known alignment. */
3633 sp
= align_down (sp
, 16);
3634 struct_addr
= align_down (struct_addr
, 16);
3636 /* Now make space on the stack for the args. */
3637 for (argnum
= 0; argnum
< nargs
; argnum
++)
3638 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3639 MIPS_STACK_ARGSIZE
);
3640 sp
-= align_up (len
, 16);
3643 fprintf_unfiltered (gdb_stdlog
,
3644 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3645 paddr_nz (sp
), (long) align_up (len
, 16));
3647 /* Initialize the integer and float register pointers. */
3649 float_argreg
= FPA0_REGNUM
;
3651 /* The struct_return pointer occupies the first parameter-passing reg. */
3655 fprintf_unfiltered (gdb_stdlog
,
3656 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3657 argreg
, paddr_nz (struct_addr
));
3658 write_register (argreg
++, struct_addr
);
3659 stack_offset
+= MIPS_STACK_ARGSIZE
;
3662 /* Now load as many as possible of the first arguments into
3663 registers, and push the rest onto the stack. Loop thru args
3664 from first to last. */
3665 for (argnum
= 0; argnum
< nargs
; argnum
++)
3668 char valbuf
[MAX_REGISTER_SIZE
];
3669 struct value
*arg
= args
[argnum
];
3670 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3671 int len
= TYPE_LENGTH (arg_type
);
3672 enum type_code typecode
= TYPE_CODE (arg_type
);
3675 fprintf_unfiltered (gdb_stdlog
,
3676 "mips_o64_push_dummy_call: %d len=%d type=%d",
3677 argnum
+ 1, len
, (int) typecode
);
3679 val
= (char *) VALUE_CONTENTS (arg
);
3681 /* 32-bit ABIs always start floating point arguments in an
3682 even-numbered floating point register. Round the FP register
3683 up before the check to see if there are any FP registers
3684 left. O32/O64 targets also pass the FP in the integer
3685 registers so also round up normal registers. */
3686 if (!FP_REGISTER_DOUBLE
3687 && fp_register_arg_p (typecode
, arg_type
))
3689 if ((float_argreg
& 1))
3693 /* Floating point arguments passed in registers have to be
3694 treated specially. On 32-bit architectures, doubles
3695 are passed in register pairs; the even register gets
3696 the low word, and the odd register gets the high word.
3697 On O32/O64, the first two floating point arguments are
3698 also copied to general registers, because MIPS16 functions
3699 don't use float registers for arguments. This duplication of
3700 arguments in general registers can't hurt non-MIPS16 functions
3701 because those registers are normally skipped. */
3703 if (fp_register_arg_p (typecode
, arg_type
)
3704 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3706 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3708 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3709 unsigned long regval
;
3711 /* Write the low word of the double to the even register(s). */
3712 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3714 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3715 float_argreg
, phex (regval
, 4));
3716 write_register (float_argreg
++, regval
);
3718 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3719 argreg
, phex (regval
, 4));
3720 write_register (argreg
++, regval
);
3722 /* Write the high word of the double to the odd register(s). */
3723 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3725 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3726 float_argreg
, phex (regval
, 4));
3727 write_register (float_argreg
++, regval
);
3730 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3731 argreg
, phex (regval
, 4));
3732 write_register (argreg
++, regval
);
3736 /* This is a floating point value that fits entirely
3737 in a single register. */
3738 /* On 32 bit ABI's the float_argreg is further adjusted
3739 above to ensure that it is even register aligned. */
3740 LONGEST regval
= extract_unsigned_integer (val
, len
);
3742 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3743 float_argreg
, phex (regval
, len
));
3744 write_register (float_argreg
++, regval
);
3745 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3746 registers for each argument. The below is (my
3747 guess) to ensure that the corresponding integer
3748 register has reserved the same space. */
3750 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3751 argreg
, phex (regval
, len
));
3752 write_register (argreg
, regval
);
3753 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3755 /* Reserve space for the FP register. */
3756 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3760 /* Copy the argument to general registers or the stack in
3761 register-sized pieces. Large arguments are split between
3762 registers and stack. */
3763 /* Note: structs whose size is not a multiple of
3764 mips_regsize() are treated specially: Irix cc passes them
3765 in registers where gcc sometimes puts them on the stack.
3766 For maximum compatibility, we will put them in both
3768 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3769 (len
% MIPS_SAVED_REGSIZE
!= 0));
3770 /* Structures should be aligned to eight bytes (even arg registers)
3771 on MIPS_ABI_O32, if their first member has double precision. */
3772 if (MIPS_SAVED_REGSIZE
< 8
3773 && mips_type_needs_double_align (arg_type
))
3778 /* Note: Floating-point values that didn't fit into an FP
3779 register are only written to memory. */
3782 /* Remember if the argument was written to the stack. */
3783 int stack_used_p
= 0;
3785 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3788 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3791 /* Write this portion of the argument to the stack. */
3792 if (argreg
> MIPS_LAST_ARG_REGNUM
3794 || fp_register_arg_p (typecode
, arg_type
))
3796 /* Should shorter than int integer values be
3797 promoted to int before being stored? */
3798 int longword_offset
= 0;
3801 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3803 if (MIPS_STACK_ARGSIZE
== 8 &&
3804 (typecode
== TYPE_CODE_INT
||
3805 typecode
== TYPE_CODE_PTR
||
3806 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3807 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3812 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3813 paddr_nz (stack_offset
));
3814 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3815 paddr_nz (longword_offset
));
3818 addr
= sp
+ stack_offset
+ longword_offset
;
3823 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3825 for (i
= 0; i
< partial_len
; i
++)
3827 fprintf_unfiltered (gdb_stdlog
, "%02x",
3831 write_memory (addr
, val
, partial_len
);
3834 /* Note!!! This is NOT an else clause. Odd sized
3835 structs may go thru BOTH paths. Floating point
3836 arguments will not. */
3837 /* Write this portion of the argument to a general
3838 purpose register. */
3839 if (argreg
<= MIPS_LAST_ARG_REGNUM
3840 && !fp_register_arg_p (typecode
, arg_type
))
3842 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3843 /* Value may need to be sign extended, because
3844 mips_regsize() != MIPS_SAVED_REGSIZE. */
3846 /* A non-floating-point argument being passed in a
3847 general register. If a struct or union, and if
3848 the remaining length is smaller than the register
3849 size, we have to adjust the register value on
3852 It does not seem to be necessary to do the
3853 same for integral types.
3855 Also don't do this adjustment on O64 binaries.
3857 cagney/2001-07-23: gdb/179: Also, GCC, when
3858 outputting LE O32 with sizeof (struct) <
3859 MIPS_SAVED_REGSIZE, generates a left shift as
3860 part of storing the argument in a register a
3861 register (the left shift isn't generated when
3862 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3863 is quite possible that this is GCC contradicting
3864 the LE/O32 ABI, GDB has not been adjusted to
3865 accommodate this. Either someone needs to
3866 demonstrate that the LE/O32 ABI specifies such a
3867 left shift OR this new ABI gets identified as
3868 such and GDB gets tweaked accordingly. */
3870 if (MIPS_SAVED_REGSIZE
< 8
3871 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3872 && partial_len
< MIPS_SAVED_REGSIZE
3873 && (typecode
== TYPE_CODE_STRUCT
||
3874 typecode
== TYPE_CODE_UNION
))
3875 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3879 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3881 phex (regval
, MIPS_SAVED_REGSIZE
));
3882 write_register (argreg
, regval
);
3885 /* Prevent subsequent floating point arguments from
3886 being passed in floating point registers. */
3887 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3893 /* Compute the the offset into the stack at which we
3894 will copy the next parameter.
3896 In older ABIs, the caller reserved space for
3897 registers that contained arguments. This was loosely
3898 refered to as their "home". Consequently, space is
3899 always allocated. */
3901 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3905 fprintf_unfiltered (gdb_stdlog
, "\n");
3908 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3910 /* Return adjusted stack pointer. */
3915 mips_pop_frame (void)
3918 struct frame_info
*frame
= get_current_frame ();
3919 CORE_ADDR new_sp
= get_frame_base (frame
);
3920 mips_extra_func_info_t proc_desc
;
3922 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
3924 generic_pop_dummy_frame ();
3925 flush_cached_frames ();
3929 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
3930 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
3931 mips_find_saved_regs (frame
);
3932 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3933 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3934 && deprecated_get_frame_saved_regs (frame
)[regnum
])
3936 /* Floating point registers must not be sign extended,
3937 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3939 if (FP0_REGNUM
<= regnum
&& regnum
< FP0_REGNUM
+ 32)
3940 write_register (regnum
,
3941 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3942 MIPS_SAVED_REGSIZE
));
3944 write_register (regnum
,
3945 read_memory_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3946 MIPS_SAVED_REGSIZE
));
3949 write_register (SP_REGNUM
, new_sp
);
3950 flush_cached_frames ();
3952 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3954 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3956 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3958 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3960 if (&pi_ptr
->info
== proc_desc
)
3965 error ("Can't locate dummy extra frame info\n");
3967 if (prev_ptr
!= NULL
)
3968 prev_ptr
->next
= pi_ptr
->next
;
3970 linked_proc_desc_table
= pi_ptr
->next
;
3974 write_register (HI_REGNUM
,
3975 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3976 MIPS_SAVED_REGSIZE
));
3977 write_register (LO_REGNUM
,
3978 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3979 MIPS_SAVED_REGSIZE
));
3980 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3981 write_register (FCRCS_REGNUM
,
3982 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3983 MIPS_SAVED_REGSIZE
));
3987 /* Floating point register management.
3989 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3990 64bit operations, these early MIPS cpus treat fp register pairs
3991 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3992 registers and offer a compatibility mode that emulates the MIPS2 fp
3993 model. When operating in MIPS2 fp compat mode, later cpu's split
3994 double precision floats into two 32-bit chunks and store them in
3995 consecutive fp regs. To display 64-bit floats stored in this
3996 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3997 Throw in user-configurable endianness and you have a real mess.
3999 The way this works is:
4000 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4001 double-precision value will be split across two logical registers.
4002 The lower-numbered logical register will hold the low-order bits,
4003 regardless of the processor's endianness.
4004 - If we are on a 64-bit processor, and we are looking for a
4005 single-precision value, it will be in the low ordered bits
4006 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4007 save slot in memory.
4008 - If we are in 64-bit mode, everything is straightforward.
4010 Note that this code only deals with "live" registers at the top of the
4011 stack. We will attempt to deal with saved registers later, when
4012 the raw/cooked register interface is in place. (We need a general
4013 interface that can deal with dynamic saved register sizes -- fp
4014 regs could be 32 bits wide in one frame and 64 on the frame above
4017 static struct type
*
4018 mips_float_register_type (void)
4020 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4021 return builtin_type_ieee_single_big
;
4023 return builtin_type_ieee_single_little
;
4026 static struct type
*
4027 mips_double_register_type (void)
4029 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4030 return builtin_type_ieee_double_big
;
4032 return builtin_type_ieee_double_little
;
4035 /* Copy a 32-bit single-precision value from the current frame
4036 into rare_buffer. */
4039 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4042 int raw_size
= DEPRECATED_REGISTER_RAW_SIZE (regno
);
4043 char *raw_buffer
= alloca (raw_size
);
4045 if (!frame_register_read (frame
, regno
, raw_buffer
))
4046 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4049 /* We have a 64-bit value for this register. Find the low-order
4053 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4058 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4062 memcpy (rare_buffer
, raw_buffer
, 4);
4066 /* Copy a 64-bit double-precision value from the current frame into
4067 rare_buffer. This may include getting half of it from the next
4071 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4074 int raw_size
= DEPRECATED_REGISTER_RAW_SIZE (regno
);
4076 if (raw_size
== 8 && !mips2_fp_compat ())
4078 /* We have a 64-bit value for this register, and we should use
4080 if (!frame_register_read (frame
, regno
, rare_buffer
))
4081 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4085 if ((regno
- FP0_REGNUM
) & 1)
4086 internal_error (__FILE__
, __LINE__
,
4087 "mips_read_fp_register_double: bad access to "
4088 "odd-numbered FP register");
4090 /* mips_read_fp_register_single will find the correct 32 bits from
4092 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4094 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4095 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4099 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4100 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4106 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4108 { /* do values for FP (float) regs */
4110 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4111 int inv1
, inv2
, namelen
;
4113 raw_buffer
= (char *) alloca (2 * DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
));
4115 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4116 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4119 if (DEPRECATED_REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
4121 /* 4-byte registers: Print hex and floating. Also print even
4122 numbered registers as doubles. */
4123 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4124 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4126 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w', file
);
4128 fprintf_filtered (file
, " flt: ");
4130 fprintf_filtered (file
, " <invalid float> ");
4132 fprintf_filtered (file
, "%-17.9g", flt1
);
4134 if (regnum
% 2 == 0)
4136 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4137 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4140 fprintf_filtered (file
, " dbl: ");
4142 fprintf_filtered (file
, "<invalid double>");
4144 fprintf_filtered (file
, "%-24.17g", doub
);
4149 /* Eight byte registers: print each one as hex, float and double. */
4150 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4151 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4153 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4154 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4157 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g', file
);
4159 fprintf_filtered (file
, " flt: ");
4161 fprintf_filtered (file
, "<invalid float>");
4163 fprintf_filtered (file
, "%-17.9g", flt1
);
4165 fprintf_filtered (file
, " dbl: ");
4167 fprintf_filtered (file
, "<invalid double>");
4169 fprintf_filtered (file
, "%-24.17g", doub
);
4174 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4175 int regnum
, int all
)
4177 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4178 char raw_buffer
[MAX_REGISTER_SIZE
];
4181 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4183 mips_print_fp_register (file
, frame
, regnum
);
4187 /* Get the data in raw format. */
4188 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4190 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4194 fputs_filtered (REGISTER_NAME (regnum
), file
);
4196 /* The problem with printing numeric register names (r26, etc.) is that
4197 the user can't use them on input. Probably the best solution is to
4198 fix it so that either the numeric or the funky (a2, etc.) names
4199 are accepted on input. */
4200 if (regnum
< MIPS_NUMREGS
)
4201 fprintf_filtered (file
, "(r%d): ", regnum
);
4203 fprintf_filtered (file
, ": ");
4205 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4206 offset
= DEPRECATED_REGISTER_RAW_SIZE (regnum
) - register_size (current_gdbarch
, regnum
);
4210 print_scalar_formatted (raw_buffer
+ offset
, gdbarch_register_type (gdbarch
, regnum
),
4214 /* Replacement for generic do_registers_info.
4215 Print regs in pretty columns. */
4218 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4221 fprintf_filtered (file
, " ");
4222 mips_print_fp_register (file
, frame
, regnum
);
4223 fprintf_filtered (file
, "\n");
4228 /* Print a row's worth of GP (int) registers, with name labels above */
4231 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4234 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4235 /* do values for GP (int) regs */
4236 char raw_buffer
[MAX_REGISTER_SIZE
];
4237 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4241 /* For GP registers, we print a separate row of names above the vals */
4242 fprintf_filtered (file
, " ");
4243 for (col
= 0, regnum
= start_regnum
;
4244 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4247 if (*REGISTER_NAME (regnum
) == '\0')
4248 continue; /* unused register */
4249 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4250 break; /* end the row: reached FP register */
4251 fprintf_filtered (file
, mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4252 REGISTER_NAME (regnum
));
4255 /* print the R0 to R31 names */
4256 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4257 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4259 fprintf_filtered (file
, "\n ");
4261 /* now print the values in hex, 4 or 8 to the row */
4262 for (col
= 0, regnum
= start_regnum
;
4263 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4266 if (*REGISTER_NAME (regnum
) == '\0')
4267 continue; /* unused register */
4268 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4269 break; /* end row: reached FP register */
4270 /* OK: get the data in raw format. */
4271 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4272 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4273 /* pad small registers */
4275 byte
< (mips_regsize (current_gdbarch
)
4276 - register_size (current_gdbarch
, regnum
));
4278 printf_filtered (" ");
4279 /* Now print the register value in hex, endian order. */
4280 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4281 for (byte
= DEPRECATED_REGISTER_RAW_SIZE (regnum
) - register_size (current_gdbarch
, regnum
);
4282 byte
< DEPRECATED_REGISTER_RAW_SIZE (regnum
);
4284 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4286 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4289 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4290 fprintf_filtered (file
, " ");
4293 if (col
> 0) /* ie. if we actually printed anything... */
4294 fprintf_filtered (file
, "\n");
4299 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4302 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4303 struct frame_info
*frame
, int regnum
, int all
)
4305 if (regnum
!= -1) /* do one specified register */
4307 gdb_assert (regnum
>= NUM_REGS
);
4308 if (*(REGISTER_NAME (regnum
)) == '\0')
4309 error ("Not a valid register for the current processor type");
4311 mips_print_register (file
, frame
, regnum
, 0);
4312 fprintf_filtered (file
, "\n");
4315 /* do all (or most) registers */
4318 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4320 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4322 if (all
) /* true for "INFO ALL-REGISTERS" command */
4323 regnum
= print_fp_register_row (file
, frame
, regnum
);
4325 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4328 regnum
= print_gp_register_row (file
, frame
, regnum
);
4333 /* Is this a branch with a delay slot? */
4335 static int is_delayed (unsigned long);
4338 is_delayed (unsigned long insn
)
4341 for (i
= 0; i
< NUMOPCODES
; ++i
)
4342 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4343 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4345 return (i
< NUMOPCODES
4346 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4347 | INSN_COND_BRANCH_DELAY
4348 | INSN_COND_BRANCH_LIKELY
)));
4352 mips_step_skips_delay (CORE_ADDR pc
)
4354 char buf
[MIPS_INSTLEN
];
4356 /* There is no branch delay slot on MIPS16. */
4357 if (pc_is_mips16 (pc
))
4360 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4361 /* If error reading memory, guess that it is not a delayed branch. */
4363 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4367 /* Skip the PC past function prologue instructions (32-bit version).
4368 This is a helper function for mips_skip_prologue. */
4371 mips32_skip_prologue (CORE_ADDR pc
)
4375 int seen_sp_adjust
= 0;
4376 int load_immediate_bytes
= 0;
4378 /* Skip the typical prologue instructions. These are the stack adjustment
4379 instruction and the instructions that save registers on the stack
4380 or in the gcc frame. */
4381 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4383 unsigned long high_word
;
4385 inst
= mips_fetch_instruction (pc
);
4386 high_word
= (inst
>> 16) & 0xffff;
4388 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4389 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4391 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4392 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4394 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4395 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4396 && (inst
& 0x001F0000)) /* reg != $zero */
4399 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4401 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4403 continue; /* reg != $zero */
4405 /* move $s8,$sp. With different versions of gas this will be either
4406 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4407 Accept any one of these. */
4408 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4411 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4413 else if (high_word
== 0x3c1c) /* lui $gp,n */
4415 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4417 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4418 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4420 /* The following instructions load $at or $t0 with an immediate
4421 value in preparation for a stack adjustment via
4422 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4423 a local variable, so we accept them only before a stack adjustment
4424 instruction was seen. */
4425 else if (!seen_sp_adjust
)
4427 if (high_word
== 0x3c01 || /* lui $at,n */
4428 high_word
== 0x3c08) /* lui $t0,n */
4430 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4433 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4434 high_word
== 0x3508 || /* ori $t0,$t0,n */
4435 high_word
== 0x3401 || /* ori $at,$zero,n */
4436 high_word
== 0x3408) /* ori $t0,$zero,n */
4438 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4448 /* In a frameless function, we might have incorrectly
4449 skipped some load immediate instructions. Undo the skipping
4450 if the load immediate was not followed by a stack adjustment. */
4451 if (load_immediate_bytes
&& !seen_sp_adjust
)
4452 pc
-= load_immediate_bytes
;
4456 /* Skip the PC past function prologue instructions (16-bit version).
4457 This is a helper function for mips_skip_prologue. */
4460 mips16_skip_prologue (CORE_ADDR pc
)
4463 int extend_bytes
= 0;
4464 int prev_extend_bytes
;
4466 /* Table of instructions likely to be found in a function prologue. */
4469 unsigned short inst
;
4470 unsigned short mask
;
4477 , /* addiu $sp,offset */
4481 , /* daddiu $sp,offset */
4485 , /* sw reg,n($sp) */
4489 , /* sd reg,n($sp) */
4493 , /* sw $ra,n($sp) */
4497 , /* sd $ra,n($sp) */
4505 , /* sw $a0-$a3,n($s1) */
4509 , /* move reg,$a0-$a3 */
4513 , /* entry pseudo-op */
4517 , /* addiu $s1,$sp,n */
4520 } /* end of table marker */
4523 /* Skip the typical prologue instructions. These are the stack adjustment
4524 instruction and the instructions that save registers on the stack
4525 or in the gcc frame. */
4526 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4528 unsigned short inst
;
4531 inst
= mips_fetch_instruction (pc
);
4533 /* Normally we ignore an extend instruction. However, if it is
4534 not followed by a valid prologue instruction, we must adjust
4535 the pc back over the extend so that it won't be considered
4536 part of the prologue. */
4537 if ((inst
& 0xf800) == 0xf000) /* extend */
4539 extend_bytes
= MIPS16_INSTLEN
;
4542 prev_extend_bytes
= extend_bytes
;
4545 /* Check for other valid prologue instructions besides extend. */
4546 for (i
= 0; table
[i
].mask
!= 0; i
++)
4547 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4549 if (table
[i
].mask
!= 0) /* it was in table? */
4550 continue; /* ignore it */
4554 /* Return the current pc, adjusted backwards by 2 if
4555 the previous instruction was an extend. */
4556 return pc
- prev_extend_bytes
;
4562 /* To skip prologues, I use this predicate. Returns either PC itself
4563 if the code at PC does not look like a function prologue; otherwise
4564 returns an address that (if we're lucky) follows the prologue. If
4565 LENIENT, then we must skip everything which is involved in setting
4566 up the frame (it's OK to skip more, just so long as we don't skip
4567 anything which might clobber the registers which are being saved.
4568 We must skip more in the case where part of the prologue is in the
4569 delay slot of a non-prologue instruction). */
4572 mips_skip_prologue (CORE_ADDR pc
)
4574 /* See if we can determine the end of the prologue via the symbol table.
4575 If so, then return either PC, or the PC after the prologue, whichever
4578 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4580 if (post_prologue_pc
!= 0)
4581 return max (pc
, post_prologue_pc
);
4583 /* Can't determine prologue from the symbol table, need to examine
4586 if (pc_is_mips16 (pc
))
4587 return mips16_skip_prologue (pc
);
4589 return mips32_skip_prologue (pc
);
4592 /* Determine how a return value is stored within the MIPS register
4593 file, given the return type `valtype'. */
4595 struct return_value_word
4604 return_value_location (struct type
*valtype
,
4605 struct return_value_word
*hi
,
4606 struct return_value_word
*lo
)
4608 int len
= TYPE_LENGTH (valtype
);
4610 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4611 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4612 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4614 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4616 /* We need to break a 64bit float in two 32 bit halves and
4617 spread them across a floating-point register pair. */
4618 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4619 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4620 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4621 && DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
4623 hi
->reg_offset
= lo
->reg_offset
;
4624 lo
->reg
= FP0_REGNUM
+ 0;
4625 hi
->reg
= FP0_REGNUM
+ 1;
4631 /* The floating point value fits in a single floating-point
4633 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4634 && DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
4637 lo
->reg
= FP0_REGNUM
;
4648 /* Locate a result possibly spread across two registers. */
4650 lo
->reg
= regnum
+ 0;
4651 hi
->reg
= regnum
+ 1;
4652 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4653 && len
< MIPS_SAVED_REGSIZE
)
4655 /* "un-left-justify" the value in the low register */
4656 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4661 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4662 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4663 && len
< MIPS_SAVED_REGSIZE
* 2
4664 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4665 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4667 /* "un-left-justify" the value spread across two registers. */
4668 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4669 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4671 hi
->len
= len
- lo
->len
;
4675 /* Only perform a partial copy of the second register. */
4678 if (len
> MIPS_SAVED_REGSIZE
)
4680 lo
->len
= MIPS_SAVED_REGSIZE
;
4681 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4689 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4690 && DEPRECATED_REGISTER_RAW_SIZE (regnum
) == 8
4691 && MIPS_SAVED_REGSIZE
== 4)
4693 /* Account for the fact that only the least-signficant part
4694 of the register is being used */
4695 lo
->reg_offset
+= 4;
4696 hi
->reg_offset
+= 4;
4699 hi
->buf_offset
= lo
->len
;
4703 /* Given a return value in `regbuf' with a type `valtype', extract and
4704 copy its value into `valbuf'. */
4707 mips_eabi_extract_return_value (struct type
*valtype
,
4711 struct return_value_word lo
;
4712 struct return_value_word hi
;
4713 return_value_location (valtype
, &hi
, &lo
);
4715 memcpy (valbuf
+ lo
.buf_offset
,
4716 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4720 memcpy (valbuf
+ hi
.buf_offset
,
4721 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4726 mips_o64_extract_return_value (struct type
*valtype
,
4730 struct return_value_word lo
;
4731 struct return_value_word hi
;
4732 return_value_location (valtype
, &hi
, &lo
);
4734 memcpy (valbuf
+ lo
.buf_offset
,
4735 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4739 memcpy (valbuf
+ hi
.buf_offset
,
4740 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4744 /* Given a return value in `valbuf' with a type `valtype', write it's
4745 value into the appropriate register. */
4748 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4750 char raw_buffer
[MAX_REGISTER_SIZE
];
4751 struct return_value_word lo
;
4752 struct return_value_word hi
;
4753 return_value_location (valtype
, &hi
, &lo
);
4755 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4756 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4757 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4758 DEPRECATED_REGISTER_RAW_SIZE (lo
.reg
));
4762 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4763 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4764 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4765 DEPRECATED_REGISTER_RAW_SIZE (hi
.reg
));
4770 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4772 char raw_buffer
[MAX_REGISTER_SIZE
];
4773 struct return_value_word lo
;
4774 struct return_value_word hi
;
4775 return_value_location (valtype
, &hi
, &lo
);
4777 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4778 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4779 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4780 DEPRECATED_REGISTER_RAW_SIZE (lo
.reg
));
4784 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4785 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4786 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4787 DEPRECATED_REGISTER_RAW_SIZE (hi
.reg
));
4791 /* O32 ABI stuff. */
4794 mips_o32_xfer_return_value (struct type
*type
,
4795 struct regcache
*regcache
,
4796 bfd_byte
*in
, const bfd_byte
*out
)
4798 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4799 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4800 && TYPE_LENGTH (type
) == 4
4801 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4803 /* A single-precision floating-point value. It fits in the
4804 least significant part of FP0. */
4806 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4807 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
, TYPE_LENGTH (type
),
4808 TARGET_BYTE_ORDER
, in
, out
, 0);
4810 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4811 && TYPE_LENGTH (type
) == 8
4812 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4814 /* A double-precision floating-point value. The most
4815 significant part goes in FP1, and the least significant in
4818 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4819 switch (TARGET_BYTE_ORDER
)
4821 case BFD_ENDIAN_LITTLE
:
4822 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 0, 4,
4823 TARGET_BYTE_ORDER
, in
, out
, 0);
4824 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 1, 4,
4825 TARGET_BYTE_ORDER
, in
, out
, 4);
4827 case BFD_ENDIAN_BIG
:
4828 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 1, 4,
4829 TARGET_BYTE_ORDER
, in
, out
, 0);
4830 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 0, 4,
4831 TARGET_BYTE_ORDER
, in
, out
, 4);
4834 internal_error (__FILE__
, __LINE__
, "bad switch");
4838 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4839 && TYPE_NFIELDS (type
) <= 2
4840 && TYPE_NFIELDS (type
) >= 1
4841 && ((TYPE_NFIELDS (type
) == 1
4842 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4844 || (TYPE_NFIELDS (type
) == 2
4845 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4847 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4849 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4851 /* A struct that contains one or two floats. Each value is part
4852 in the least significant part of their floating point
4854 bfd_byte reg
[MAX_REGISTER_SIZE
];
4857 for (field
= 0, regnum
= FP0_REGNUM
;
4858 field
< TYPE_NFIELDS (type
);
4859 field
++, regnum
+= 2)
4861 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4864 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4865 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4866 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4867 TARGET_BYTE_ORDER
, in
, out
, offset
);
4872 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4873 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4875 /* A structure or union. Extract the left justified value,
4876 regardless of the byte order. I.e. DO NOT USE
4880 for (offset
= 0, regnum
= V0_REGNUM
;
4881 offset
< TYPE_LENGTH (type
);
4882 offset
+= DEPRECATED_REGISTER_RAW_SIZE (regnum
), regnum
++)
4884 int xfer
= DEPRECATED_REGISTER_RAW_SIZE (regnum
);
4885 if (offset
+ xfer
> TYPE_LENGTH (type
))
4886 xfer
= TYPE_LENGTH (type
) - offset
;
4888 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4889 offset
, xfer
, regnum
);
4890 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4891 BFD_ENDIAN_UNKNOWN
, in
, out
, offset
);
4897 /* A scalar extract each part but least-significant-byte
4898 justified. o32 thinks registers are 4 byte, regardless of
4899 the ISA. mips_stack_argsize controls this. */
4902 for (offset
= 0, regnum
= V0_REGNUM
;
4903 offset
< TYPE_LENGTH (type
);
4904 offset
+= mips_stack_argsize (), regnum
++)
4906 int xfer
= mips_stack_argsize ();
4908 if (offset
+ xfer
> TYPE_LENGTH (type
))
4909 xfer
= TYPE_LENGTH (type
) - offset
;
4911 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4912 offset
, xfer
, regnum
);
4913 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4914 TARGET_BYTE_ORDER
, in
, out
, offset
);
4920 mips_o32_extract_return_value (struct type
*type
,
4921 struct regcache
*regcache
,
4924 mips_o32_xfer_return_value (type
, regcache
, valbuf
, NULL
);
4928 mips_o32_store_return_value (struct type
*type
, char *valbuf
)
4930 mips_o32_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
4933 /* N32/N44 ABI stuff. */
4936 mips_n32n64_xfer_return_value (struct type
*type
,
4937 struct regcache
*regcache
,
4938 bfd_byte
*in
, const bfd_byte
*out
)
4940 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4941 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4942 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4944 /* A floating-point value belongs in the least significant part
4947 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4948 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
, TYPE_LENGTH (type
),
4949 TARGET_BYTE_ORDER
, in
, out
, 0);
4951 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4952 && TYPE_NFIELDS (type
) <= 2
4953 && TYPE_NFIELDS (type
) >= 1
4954 && ((TYPE_NFIELDS (type
) == 1
4955 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4957 || (TYPE_NFIELDS (type
) == 2
4958 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4960 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4962 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4964 /* A struct that contains one or two floats. Each value is part
4965 in the least significant part of their floating point
4967 bfd_byte reg
[MAX_REGISTER_SIZE
];
4970 for (field
= 0, regnum
= FP0_REGNUM
;
4971 field
< TYPE_NFIELDS (type
);
4972 field
++, regnum
+= 2)
4974 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4977 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4978 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4979 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4980 TARGET_BYTE_ORDER
, in
, out
, offset
);
4983 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4984 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4986 /* A structure or union. Extract the left justified value,
4987 regardless of the byte order. I.e. DO NOT USE
4991 for (offset
= 0, regnum
= V0_REGNUM
;
4992 offset
< TYPE_LENGTH (type
);
4993 offset
+= DEPRECATED_REGISTER_RAW_SIZE (regnum
), regnum
++)
4995 int xfer
= DEPRECATED_REGISTER_RAW_SIZE (regnum
);
4996 if (offset
+ xfer
> TYPE_LENGTH (type
))
4997 xfer
= TYPE_LENGTH (type
) - offset
;
4999 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5000 offset
, xfer
, regnum
);
5001 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5002 BFD_ENDIAN_UNKNOWN
, in
, out
, offset
);
5007 /* A scalar extract each part but least-significant-byte
5011 for (offset
= 0, regnum
= V0_REGNUM
;
5012 offset
< TYPE_LENGTH (type
);
5013 offset
+= DEPRECATED_REGISTER_RAW_SIZE (regnum
), regnum
++)
5015 int xfer
= DEPRECATED_REGISTER_RAW_SIZE (regnum
);
5017 if (offset
+ xfer
> TYPE_LENGTH (type
))
5018 xfer
= TYPE_LENGTH (type
) - offset
;
5020 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5021 offset
, xfer
, regnum
);
5022 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5023 TARGET_BYTE_ORDER
, in
, out
, offset
);
5029 mips_n32n64_extract_return_value (struct type
*type
,
5030 struct regcache
*regcache
,
5033 mips_n32n64_xfer_return_value (type
, regcache
, valbuf
, NULL
);
5037 mips_n32n64_store_return_value (struct type
*type
, char *valbuf
)
5039 mips_n32n64_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
5043 mips_extract_struct_value_address (struct regcache
*regcache
)
5045 /* FIXME: This will only work at random. The caller passes the
5046 struct_return address in V0, but it is not preserved. It may
5047 still be there, or this may be a random value. */
5050 regcache_cooked_read_signed (regcache
, V0_REGNUM
, &val
);
5054 /* Exported procedure: Is PC in the signal trampoline code */
5057 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5059 if (sigtramp_address
== 0)
5061 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5064 /* Root of all "set mips "/"show mips " commands. This will eventually be
5065 used for all MIPS-specific commands. */
5068 show_mips_command (char *args
, int from_tty
)
5070 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5074 set_mips_command (char *args
, int from_tty
)
5076 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5077 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5080 /* Commands to show/set the MIPS FPU type. */
5083 show_mipsfpu_command (char *args
, int from_tty
)
5086 switch (MIPS_FPU_TYPE
)
5088 case MIPS_FPU_SINGLE
:
5089 fpu
= "single-precision";
5091 case MIPS_FPU_DOUBLE
:
5092 fpu
= "double-precision";
5095 fpu
= "absent (none)";
5098 internal_error (__FILE__
, __LINE__
, "bad switch");
5100 if (mips_fpu_type_auto
)
5101 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5104 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5110 set_mipsfpu_command (char *args
, int from_tty
)
5112 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5113 show_mipsfpu_command (args
, from_tty
);
5117 set_mipsfpu_single_command (char *args
, int from_tty
)
5119 mips_fpu_type
= MIPS_FPU_SINGLE
;
5120 mips_fpu_type_auto
= 0;
5121 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
5125 set_mipsfpu_double_command (char *args
, int from_tty
)
5127 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5128 mips_fpu_type_auto
= 0;
5129 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5133 set_mipsfpu_none_command (char *args
, int from_tty
)
5135 mips_fpu_type
= MIPS_FPU_NONE
;
5136 mips_fpu_type_auto
= 0;
5137 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
5141 set_mipsfpu_auto_command (char *args
, int from_tty
)
5143 mips_fpu_type_auto
= 1;
5146 /* Command to set the processor type. */
5149 mips_set_processor_type_command (char *args
, int from_tty
)
5153 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
5155 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5156 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5157 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
5159 /* Restore the value. */
5160 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5165 if (!mips_set_processor_type (tmp_mips_processor_type
))
5167 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
5168 /* Restore its value. */
5169 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5174 mips_show_processor_type_command (char *args
, int from_tty
)
5178 /* Modify the actual processor type. */
5181 mips_set_processor_type (char *str
)
5188 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5190 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
5192 mips_processor_type
= str
;
5193 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
5195 /* FIXME tweak fpu flag too */
5202 /* Attempt to identify the particular processor model by reading the
5206 mips_read_processor_type (void)
5210 prid
= read_register (PRID_REGNUM
);
5212 if ((prid
& ~0xf) == 0x700)
5213 return savestring ("r3041", strlen ("r3041"));
5218 /* Just like reinit_frame_cache, but with the right arguments to be
5219 callable as an sfunc. */
5222 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5223 struct cmd_list_element
*c
)
5225 reinit_frame_cache ();
5229 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5232 mips_extra_func_info_t proc_desc
;
5234 /* Search for the function containing this address. Set the low bit
5235 of the address when searching, in case we were given an even address
5236 that is the start of a 16-bit function. If we didn't do this,
5237 the search would fail because the symbol table says the function
5238 starts at an odd address, i.e. 1 byte past the given address. */
5239 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5240 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5242 /* Make an attempt to determine if this is a 16-bit function. If
5243 the procedure descriptor exists and the address therein is odd,
5244 it's definitely a 16-bit function. Otherwise, we have to just
5245 guess that if the address passed in is odd, it's 16-bits. */
5246 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5247 disassembler needs to be able to locally determine the ISA, and
5248 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5252 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5253 info
->mach
= bfd_mach_mips16
;
5257 if (pc_is_mips16 (memaddr
))
5258 info
->mach
= bfd_mach_mips16
;
5261 /* Round down the instruction address to the appropriate boundary. */
5262 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5264 /* Set the disassembler options. */
5265 if (tdep
->mips_abi
== MIPS_ABI_N32
5266 || tdep
->mips_abi
== MIPS_ABI_N64
)
5268 /* Set up the disassembler info, so that we get the right
5269 register names from libopcodes. */
5270 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5271 info
->disassembler_options
= "gpr-names=n32";
5273 info
->disassembler_options
= "gpr-names=64";
5274 info
->flavour
= bfd_target_elf_flavour
;
5277 /* This string is not recognized explicitly by the disassembler,
5278 but it tells the disassembler to not try to guess the ABI from
5279 the bfd elf headers, such that, if the user overrides the ABI
5280 of a program linked as NewABI, the disassembly will follow the
5281 register naming conventions specified by the user. */
5282 info
->disassembler_options
= "gpr-names=32";
5284 /* Call the appropriate disassembler based on the target endian-ness. */
5285 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5286 return print_insn_big_mips (memaddr
, info
);
5288 return print_insn_little_mips (memaddr
, info
);
5291 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5292 counter value to determine whether a 16- or 32-bit breakpoint should be
5293 used. It returns a pointer to a string of bytes that encode a breakpoint
5294 instruction, stores the length of the string to *lenptr, and adjusts pc
5295 (if necessary) to point to the actual memory location where the
5296 breakpoint should be inserted. */
5298 static const unsigned char *
5299 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5301 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5303 if (pc_is_mips16 (*pcptr
))
5305 static unsigned char mips16_big_breakpoint
[] = {0xe8, 0xa5};
5306 *pcptr
= unmake_mips16_addr (*pcptr
);
5307 *lenptr
= sizeof (mips16_big_breakpoint
);
5308 return mips16_big_breakpoint
;
5312 /* The IDT board uses an unusual breakpoint value, and
5313 sometimes gets confused when it sees the usual MIPS
5314 breakpoint instruction. */
5315 static unsigned char big_breakpoint
[] = {0, 0x5, 0, 0xd};
5316 static unsigned char pmon_big_breakpoint
[] = {0, 0, 0, 0xd};
5317 static unsigned char idt_big_breakpoint
[] = {0, 0, 0x0a, 0xd};
5319 *lenptr
= sizeof (big_breakpoint
);
5321 if (strcmp (target_shortname
, "mips") == 0)
5322 return idt_big_breakpoint
;
5323 else if (strcmp (target_shortname
, "ddb") == 0
5324 || strcmp (target_shortname
, "pmon") == 0
5325 || strcmp (target_shortname
, "lsi") == 0)
5326 return pmon_big_breakpoint
;
5328 return big_breakpoint
;
5333 if (pc_is_mips16 (*pcptr
))
5335 static unsigned char mips16_little_breakpoint
[] = {0xa5, 0xe8};
5336 *pcptr
= unmake_mips16_addr (*pcptr
);
5337 *lenptr
= sizeof (mips16_little_breakpoint
);
5338 return mips16_little_breakpoint
;
5342 static unsigned char little_breakpoint
[] = {0xd, 0, 0x5, 0};
5343 static unsigned char pmon_little_breakpoint
[] = {0xd, 0, 0, 0};
5344 static unsigned char idt_little_breakpoint
[] = {0xd, 0x0a, 0, 0};
5346 *lenptr
= sizeof (little_breakpoint
);
5348 if (strcmp (target_shortname
, "mips") == 0)
5349 return idt_little_breakpoint
;
5350 else if (strcmp (target_shortname
, "ddb") == 0
5351 || strcmp (target_shortname
, "pmon") == 0
5352 || strcmp (target_shortname
, "lsi") == 0)
5353 return pmon_little_breakpoint
;
5355 return little_breakpoint
;
5360 /* If PC is in a mips16 call or return stub, return the address of the target
5361 PC, which is either the callee or the caller. There are several
5362 cases which must be handled:
5364 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5365 target PC is in $31 ($ra).
5366 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5367 and the target PC is in $2.
5368 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5369 before the jal instruction, this is effectively a call stub
5370 and the the target PC is in $2. Otherwise this is effectively
5371 a return stub and the target PC is in $18.
5373 See the source code for the stubs in gcc/config/mips/mips16.S for
5376 This function implements the SKIP_TRAMPOLINE_CODE macro.
5380 mips_skip_stub (CORE_ADDR pc
)
5383 CORE_ADDR start_addr
;
5385 /* Find the starting address and name of the function containing the PC. */
5386 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5389 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5390 target PC is in $31 ($ra). */
5391 if (strcmp (name
, "__mips16_ret_sf") == 0
5392 || strcmp (name
, "__mips16_ret_df") == 0)
5393 return read_signed_register (RA_REGNUM
);
5395 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5397 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5398 and the target PC is in $2. */
5399 if (name
[19] >= '0' && name
[19] <= '9')
5400 return read_signed_register (2);
5402 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5403 before the jal instruction, this is effectively a call stub
5404 and the the target PC is in $2. Otherwise this is effectively
5405 a return stub and the target PC is in $18. */
5406 else if (name
[19] == 's' || name
[19] == 'd')
5408 if (pc
== start_addr
)
5410 /* Check if the target of the stub is a compiler-generated
5411 stub. Such a stub for a function bar might have a name
5412 like __fn_stub_bar, and might look like this:
5417 la $1,bar (becomes a lui/addiu pair)
5419 So scan down to the lui/addi and extract the target
5420 address from those two instructions. */
5422 CORE_ADDR target_pc
= read_signed_register (2);
5426 /* See if the name of the target function is __fn_stub_*. */
5427 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5429 if (strncmp (name
, "__fn_stub_", 10) != 0
5430 && strcmp (name
, "etext") != 0
5431 && strcmp (name
, "_etext") != 0)
5434 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5435 The limit on the search is arbitrarily set to 20
5436 instructions. FIXME. */
5437 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5439 inst
= mips_fetch_instruction (target_pc
);
5440 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5441 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5442 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5443 return pc
| (inst
& 0xffff); /* low word */
5446 /* Couldn't find the lui/addui pair, so return stub address. */
5450 /* This is the 'return' part of a call stub. The return
5451 address is in $r18. */
5452 return read_signed_register (18);
5455 return 0; /* not a stub */
5459 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5460 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5463 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5465 CORE_ADDR start_addr
;
5467 /* Find the starting address of the function containing the PC. If the
5468 caller didn't give us a name, look it up at the same time. */
5469 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5472 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5474 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5475 if (name
[19] >= '0' && name
[19] <= '9')
5477 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5478 before the jal instruction, this is effectively a call stub. */
5479 else if (name
[19] == 's' || name
[19] == 'd')
5480 return pc
== start_addr
;
5483 return 0; /* not a stub */
5487 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5488 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5491 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5493 CORE_ADDR start_addr
;
5495 /* Find the starting address of the function containing the PC. */
5496 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5499 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5500 if (strcmp (name
, "__mips16_ret_sf") == 0
5501 || strcmp (name
, "__mips16_ret_df") == 0)
5504 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5505 i.e. after the jal instruction, this is effectively a return stub. */
5506 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5507 && (name
[19] == 's' || name
[19] == 'd')
5508 && pc
!= start_addr
)
5511 return 0; /* not a stub */
5515 /* Return non-zero if the PC is in a library helper function that should
5516 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5519 mips_ignore_helper (CORE_ADDR pc
)
5523 /* Find the starting address and name of the function containing the PC. */
5524 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5527 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5528 that we want to ignore. */
5529 return (strcmp (name
, "__mips16_ret_sf") == 0
5530 || strcmp (name
, "__mips16_ret_df") == 0);
5534 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5535 the register stored on the stack (32) is different to its real raw
5536 size (64). The below ensures that registers are fetched from the
5537 stack using their ABI size and then stored into the RAW_BUFFER
5538 using their raw size.
5540 The alternative to adding this function would be to add an ABI
5541 macro - REGISTER_STACK_SIZE(). */
5544 mips_get_saved_register (char *raw_buffer
,
5547 struct frame_info
*frame
,
5549 enum lval_type
*lvalp
)
5552 enum lval_type lvalx
;
5556 /* Always a pseudo. */
5557 gdb_assert (regnum
>= NUM_REGS
);
5559 /* Make certain that all needed parameters are present. */
5564 if (optimizedp
== NULL
)
5565 optimizedp
= &optimizedx
;
5567 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5568 /* The SP_REGNUM is special, its value is stored in saved_regs.
5569 In fact, it is so special that it can even only be fetched
5570 using a raw register number! Once this code as been converted
5571 to frame-unwind the problem goes away. */
5572 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5573 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5574 &realnumx
, raw_buffer
);
5576 /* Get it from the next frame. */
5577 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5578 regnum
, optimizedp
, lvalp
, addrp
,
5579 &realnumx
, raw_buffer
);
5582 /* Immediately after a function call, return the saved pc.
5583 Can't always go through the frames for this because on some machines
5584 the new frame is not set up until the new function executes
5585 some instructions. */
5588 mips_saved_pc_after_call (struct frame_info
*frame
)
5590 return read_signed_register (RA_REGNUM
);
5594 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5595 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5598 mips_stab_reg_to_regnum (int num
)
5601 if (num
>= 0 && num
< 32)
5603 else if (num
>= 38 && num
< 70)
5604 regnum
= num
+ FP0_REGNUM
- 38;
5610 /* This will hopefully (eventually) provoke a warning. Should
5611 we be calling complaint() here? */
5612 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5613 return NUM_REGS
+ regnum
;
5617 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5618 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5621 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5624 if (num
>= 0 && num
< 32)
5626 else if (num
>= 32 && num
< 64)
5627 regnum
= num
+ FP0_REGNUM
- 32;
5633 /* This will hopefully (eventually) provoke a warning. Should we
5634 be calling complaint() here? */
5635 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5636 return NUM_REGS
+ regnum
;
5640 mips_register_sim_regno (int regnum
)
5642 /* Only makes sense to supply raw registers. */
5643 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5644 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5645 decide if it is valid. Should instead define a standard sim/gdb
5646 register numbering scheme. */
5647 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5648 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5651 return LEGACY_SIM_REGNO_IGNORE
;
5655 /* Convert an integer into an address. By first converting the value
5656 into a pointer and then extracting it signed, the address is
5657 guarenteed to be correctly sign extended. */
5660 mips_integer_to_address (struct type
*type
, void *buf
)
5662 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5663 LONGEST val
= unpack_long (type
, buf
);
5664 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5665 return extract_signed_integer (tmp
,
5666 TYPE_LENGTH (builtin_type_void_data_ptr
));
5670 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5672 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5673 const char *name
= bfd_get_section_name (abfd
, sect
);
5675 if (*abip
!= MIPS_ABI_UNKNOWN
)
5678 if (strncmp (name
, ".mdebug.", 8) != 0)
5681 if (strcmp (name
, ".mdebug.abi32") == 0)
5682 *abip
= MIPS_ABI_O32
;
5683 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5684 *abip
= MIPS_ABI_N32
;
5685 else if (strcmp (name
, ".mdebug.abi64") == 0)
5686 *abip
= MIPS_ABI_N64
;
5687 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5688 *abip
= MIPS_ABI_O64
;
5689 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5690 *abip
= MIPS_ABI_EABI32
;
5691 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5692 *abip
= MIPS_ABI_EABI64
;
5694 warning ("unsupported ABI %s.", name
+ 8);
5697 static enum mips_abi
5698 global_mips_abi (void)
5702 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5703 if (mips_abi_strings
[i
] == mips_abi_string
)
5704 return (enum mips_abi
) i
;
5706 internal_error (__FILE__
, __LINE__
,
5707 "unknown ABI string");
5710 static struct gdbarch
*
5711 mips_gdbarch_init (struct gdbarch_info info
,
5712 struct gdbarch_list
*arches
)
5714 struct gdbarch
*gdbarch
;
5715 struct gdbarch_tdep
*tdep
;
5717 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5724 /* First of all, extract the elf_flags, if available. */
5725 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5726 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5729 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5730 switch ((elf_flags
& EF_MIPS_ABI
))
5732 case E_MIPS_ABI_O32
:
5733 mips_abi
= MIPS_ABI_O32
;
5735 case E_MIPS_ABI_O64
:
5736 mips_abi
= MIPS_ABI_O64
;
5738 case E_MIPS_ABI_EABI32
:
5739 mips_abi
= MIPS_ABI_EABI32
;
5741 case E_MIPS_ABI_EABI64
:
5742 mips_abi
= MIPS_ABI_EABI64
;
5745 if ((elf_flags
& EF_MIPS_ABI2
))
5746 mips_abi
= MIPS_ABI_N32
;
5748 mips_abi
= MIPS_ABI_UNKNOWN
;
5752 /* GCC creates a pseudo-section whose name describes the ABI. */
5753 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5754 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
5756 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5757 Use the ABI from the last architecture if there is one. */
5758 if (info
.abfd
== NULL
&& arches
!= NULL
)
5759 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5761 /* Try the architecture for any hint of the correct ABI. */
5762 if (mips_abi
== MIPS_ABI_UNKNOWN
5763 && info
.bfd_arch_info
!= NULL
5764 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5766 switch (info
.bfd_arch_info
->mach
)
5768 case bfd_mach_mips3900
:
5769 mips_abi
= MIPS_ABI_EABI32
;
5771 case bfd_mach_mips4100
:
5772 case bfd_mach_mips5000
:
5773 mips_abi
= MIPS_ABI_EABI64
;
5775 case bfd_mach_mips8000
:
5776 case bfd_mach_mips10000
:
5777 /* On Irix, ELF64 executables use the N64 ABI. The
5778 pseudo-sections which describe the ABI aren't present
5779 on IRIX. (Even for executables created by gcc.) */
5780 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5781 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5782 mips_abi
= MIPS_ABI_N64
;
5784 mips_abi
= MIPS_ABI_N32
;
5789 if (mips_abi
== MIPS_ABI_UNKNOWN
)
5790 mips_abi
= MIPS_ABI_O32
;
5792 /* Now that we have found what the ABI for this binary would be,
5793 check whether the user is overriding it. */
5794 found_abi
= mips_abi
;
5795 wanted_abi
= global_mips_abi ();
5796 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5797 mips_abi
= wanted_abi
;
5801 fprintf_unfiltered (gdb_stdlog
,
5802 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5804 fprintf_unfiltered (gdb_stdlog
,
5805 "mips_gdbarch_init: mips_abi = %d\n",
5807 fprintf_unfiltered (gdb_stdlog
,
5808 "mips_gdbarch_init: found_mips_abi = %d\n",
5812 /* try to find a pre-existing architecture */
5813 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5815 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5817 /* MIPS needs to be pedantic about which ABI the object is
5819 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5821 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5823 return arches
->gdbarch
;
5826 /* Need a new architecture. Fill in a target specific vector. */
5827 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5828 gdbarch
= gdbarch_alloc (&info
, tdep
);
5829 tdep
->elf_flags
= elf_flags
;
5831 /* Initially set everything according to the default ABI/ISA. */
5832 set_gdbarch_short_bit (gdbarch
, 16);
5833 set_gdbarch_int_bit (gdbarch
, 32);
5834 set_gdbarch_float_bit (gdbarch
, 32);
5835 set_gdbarch_double_bit (gdbarch
, 64);
5836 set_gdbarch_long_double_bit (gdbarch
, 64);
5837 set_gdbarch_deprecated_register_raw_size (gdbarch
, mips_register_raw_size
);
5838 set_gdbarch_deprecated_register_byte (gdbarch
, mips_register_byte
);
5839 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5840 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5841 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5842 tdep
->found_abi
= found_abi
;
5843 tdep
->mips_abi
= mips_abi
;
5845 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5846 mips_elf_make_msymbol_special
);
5849 if (info
.osabi
== GDB_OSABI_IRIX
)
5853 set_gdbarch_num_regs (gdbarch
, num_regs
);
5854 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5859 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5860 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o32_store_return_value
);
5861 set_gdbarch_extract_return_value (gdbarch
, mips_o32_extract_return_value
);
5862 tdep
->mips_default_saved_regsize
= 4;
5863 tdep
->mips_default_stack_argsize
= 4;
5864 tdep
->mips_fp_register_double
= 0;
5865 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5866 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5867 tdep
->default_mask_address_p
= 0;
5868 set_gdbarch_long_bit (gdbarch
, 32);
5869 set_gdbarch_ptr_bit (gdbarch
, 32);
5870 set_gdbarch_long_long_bit (gdbarch
, 64);
5871 set_gdbarch_deprecated_reg_struct_has_addr
5872 (gdbarch
, mips_o32_reg_struct_has_addr
);
5873 set_gdbarch_use_struct_convention (gdbarch
,
5874 always_use_struct_convention
);
5877 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5878 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o64_store_return_value
);
5879 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5880 tdep
->mips_default_saved_regsize
= 8;
5881 tdep
->mips_default_stack_argsize
= 8;
5882 tdep
->mips_fp_register_double
= 1;
5883 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5884 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5885 tdep
->default_mask_address_p
= 0;
5886 set_gdbarch_long_bit (gdbarch
, 32);
5887 set_gdbarch_ptr_bit (gdbarch
, 32);
5888 set_gdbarch_long_long_bit (gdbarch
, 64);
5889 set_gdbarch_deprecated_reg_struct_has_addr
5890 (gdbarch
, mips_o32_reg_struct_has_addr
);
5891 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
5893 case MIPS_ABI_EABI32
:
5894 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5895 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5896 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5897 tdep
->mips_default_saved_regsize
= 4;
5898 tdep
->mips_default_stack_argsize
= 4;
5899 tdep
->mips_fp_register_double
= 0;
5900 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5901 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5902 tdep
->default_mask_address_p
= 0;
5903 set_gdbarch_long_bit (gdbarch
, 32);
5904 set_gdbarch_ptr_bit (gdbarch
, 32);
5905 set_gdbarch_long_long_bit (gdbarch
, 64);
5906 set_gdbarch_deprecated_reg_struct_has_addr
5907 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5908 set_gdbarch_use_struct_convention (gdbarch
,
5909 mips_eabi_use_struct_convention
);
5911 case MIPS_ABI_EABI64
:
5912 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5913 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5914 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5915 tdep
->mips_default_saved_regsize
= 8;
5916 tdep
->mips_default_stack_argsize
= 8;
5917 tdep
->mips_fp_register_double
= 1;
5918 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5919 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5920 tdep
->default_mask_address_p
= 0;
5921 set_gdbarch_long_bit (gdbarch
, 64);
5922 set_gdbarch_ptr_bit (gdbarch
, 64);
5923 set_gdbarch_long_long_bit (gdbarch
, 64);
5924 set_gdbarch_deprecated_reg_struct_has_addr
5925 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5926 set_gdbarch_use_struct_convention (gdbarch
,
5927 mips_eabi_use_struct_convention
);
5930 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5931 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5932 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5933 tdep
->mips_default_saved_regsize
= 8;
5934 tdep
->mips_default_stack_argsize
= 8;
5935 tdep
->mips_fp_register_double
= 1;
5936 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5937 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5938 tdep
->default_mask_address_p
= 0;
5939 set_gdbarch_long_bit (gdbarch
, 32);
5940 set_gdbarch_ptr_bit (gdbarch
, 32);
5941 set_gdbarch_long_long_bit (gdbarch
, 64);
5942 set_gdbarch_use_struct_convention (gdbarch
,
5943 mips_n32n64_use_struct_convention
);
5944 set_gdbarch_deprecated_reg_struct_has_addr
5945 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5948 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5949 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5950 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5951 tdep
->mips_default_saved_regsize
= 8;
5952 tdep
->mips_default_stack_argsize
= 8;
5953 tdep
->mips_fp_register_double
= 1;
5954 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5955 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5956 tdep
->default_mask_address_p
= 0;
5957 set_gdbarch_long_bit (gdbarch
, 64);
5958 set_gdbarch_ptr_bit (gdbarch
, 64);
5959 set_gdbarch_long_long_bit (gdbarch
, 64);
5960 set_gdbarch_use_struct_convention (gdbarch
,
5961 mips_n32n64_use_struct_convention
);
5962 set_gdbarch_deprecated_reg_struct_has_addr
5963 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5966 internal_error (__FILE__
, __LINE__
,
5967 "unknown ABI in switch");
5970 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5971 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5974 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5975 flag in object files because to do so would make it impossible to
5976 link with libraries compiled without "-gp32". This is
5977 unnecessarily restrictive.
5979 We could solve this problem by adding "-gp32" multilibs to gcc,
5980 but to set this flag before gcc is built with such multilibs will
5981 break too many systems.''
5983 But even more unhelpfully, the default linker output target for
5984 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5985 for 64-bit programs - you need to change the ABI to change this,
5986 and not all gcc targets support that currently. Therefore using
5987 this flag to detect 32-bit mode would do the wrong thing given
5988 the current gcc - it would make GDB treat these 64-bit programs
5989 as 32-bit programs by default. */
5991 /* enable/disable the MIPS FPU */
5992 if (!mips_fpu_type_auto
)
5993 tdep
->mips_fpu_type
= mips_fpu_type
;
5994 else if (info
.bfd_arch_info
!= NULL
5995 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5996 switch (info
.bfd_arch_info
->mach
)
5998 case bfd_mach_mips3900
:
5999 case bfd_mach_mips4100
:
6000 case bfd_mach_mips4111
:
6001 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
6003 case bfd_mach_mips4650
:
6004 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
6007 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
6011 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
6013 /* MIPS version of register names. NOTE: At present the MIPS
6014 register name management is part way between the old -
6015 #undef/#define MIPS_REGISTER_NAMES and the new REGISTER_NAME(nr).
6016 Further work on it is required. */
6017 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6018 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6019 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
6020 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6021 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6023 /* Add/remove bits from an address. The MIPS needs be careful to
6024 ensure that all 32 bit addresses are sign extended to 64 bits. */
6025 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6027 /* There's a mess in stack frame creation. See comments in
6028 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6029 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
6031 /* Map debug register numbers onto internal register numbers. */
6032 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6033 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6034 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6035 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6036 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6038 /* Initialize a frame */
6039 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
, mips_find_saved_regs
);
6040 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
6042 /* MIPS version of CALL_DUMMY */
6044 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6045 replaced by a command, and all targets will default to on stack
6046 (regardless of the stack's execute status). */
6047 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6048 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6049 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6050 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
6051 set_gdbarch_deprecated_register_convertible (gdbarch
, mips_register_convertible
);
6052 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch
, mips_register_convert_to_virtual
);
6053 set_gdbarch_deprecated_register_convert_to_raw (gdbarch
, mips_register_convert_to_raw
);
6055 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6056 set_gdbarch_frameless_function_invocation (gdbarch
,
6057 generic_frameless_function_invocation_not
);
6058 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6059 set_gdbarch_frame_args_skip (gdbarch
, 0);
6061 set_gdbarch_deprecated_get_saved_register (gdbarch
, mips_get_saved_register
);
6063 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6064 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6065 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
6067 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6068 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
6070 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6071 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6072 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6074 set_gdbarch_function_start_offset (gdbarch
, 0);
6076 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6078 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6079 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6081 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6083 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6084 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6085 need to all be folded into the target vector. Since they are
6086 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6087 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6089 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6091 /* Hook in OS ABI-specific overrides, if they have been registered. */
6092 gdbarch_init_osabi (info
, gdbarch
);
6094 set_gdbarch_extract_struct_value_address (gdbarch
,
6095 mips_extract_struct_value_address
);
6097 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6099 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6100 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6106 mips_abi_update (char *ignore_args
, int from_tty
,
6107 struct cmd_list_element
*c
)
6109 struct gdbarch_info info
;
6111 /* Force the architecture to update, and (if it's a MIPS architecture)
6112 mips_gdbarch_init will take care of the rest. */
6113 gdbarch_info_init (&info
);
6114 gdbarch_update_p (info
);
6117 /* Print out which MIPS ABI is in use. */
6120 show_mips_abi (char *ignore_args
, int from_tty
)
6122 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6124 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6127 enum mips_abi global_abi
= global_mips_abi ();
6128 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6129 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6131 if (global_abi
== MIPS_ABI_UNKNOWN
)
6132 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6134 else if (global_abi
== actual_abi
)
6136 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6140 /* Probably shouldn't happen... */
6142 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6144 mips_abi_strings
[global_abi
]);
6150 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6156 int ef_mips_32bitmode
;
6157 /* determine the ISA */
6158 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6176 /* determine the size of a pointer */
6177 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6178 fprintf_unfiltered (file
,
6179 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6181 fprintf_unfiltered (file
,
6182 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6184 fprintf_unfiltered (file
,
6185 "mips_dump_tdep: ef_mips_arch = %d\n",
6187 fprintf_unfiltered (file
,
6188 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6190 mips_abi_strings
[tdep
->mips_abi
]);
6191 fprintf_unfiltered (file
,
6192 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6193 mips_mask_address_p (),
6194 tdep
->default_mask_address_p
);
6196 fprintf_unfiltered (file
,
6197 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6198 FP_REGISTER_DOUBLE
);
6199 fprintf_unfiltered (file
,
6200 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6201 MIPS_DEFAULT_FPU_TYPE
,
6202 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6203 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6204 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6206 fprintf_unfiltered (file
,
6207 "mips_dump_tdep: MIPS_EABI = %d\n",
6209 fprintf_unfiltered (file
,
6210 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6211 MIPS_LAST_FP_ARG_REGNUM
,
6212 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6216 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6217 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6218 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6220 fprintf_unfiltered (file
,
6221 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6222 MIPS_DEFAULT_SAVED_REGSIZE
);
6223 fprintf_unfiltered (file
,
6224 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6225 FP_REGISTER_DOUBLE
);
6226 fprintf_unfiltered (file
,
6227 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6228 MIPS_DEFAULT_STACK_ARGSIZE
);
6229 fprintf_unfiltered (file
,
6230 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6231 MIPS_STACK_ARGSIZE
);
6232 fprintf_unfiltered (file
,
6233 "mips_dump_tdep: A0_REGNUM = %d\n",
6235 fprintf_unfiltered (file
,
6236 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6237 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6238 fprintf_unfiltered (file
,
6239 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6240 XSTRING (ATTACH_DETACH
));
6241 fprintf_unfiltered (file
,
6242 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6244 fprintf_unfiltered (file
,
6245 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6247 fprintf_unfiltered (file
,
6248 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6249 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6250 fprintf_unfiltered (file
,
6251 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6252 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6253 fprintf_unfiltered (file
,
6254 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6256 fprintf_unfiltered (file
,
6257 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6259 fprintf_unfiltered (file
,
6260 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6261 FIRST_EMBED_REGNUM
);
6262 fprintf_unfiltered (file
,
6263 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6265 fprintf_unfiltered (file
,
6266 "mips_dump_tdep: HI_REGNUM = %d\n",
6268 fprintf_unfiltered (file
,
6269 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6270 XSTRING (IGNORE_HELPER_CALL (PC
)));
6271 fprintf_unfiltered (file
,
6272 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6273 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6274 fprintf_unfiltered (file
,
6275 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6276 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6277 fprintf_unfiltered (file
,
6278 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6280 fprintf_unfiltered (file
,
6281 "mips_dump_tdep: LO_REGNUM = %d\n",
6283 #ifdef MACHINE_CPROC_FP_OFFSET
6284 fprintf_unfiltered (file
,
6285 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6286 MACHINE_CPROC_FP_OFFSET
);
6288 #ifdef MACHINE_CPROC_PC_OFFSET
6289 fprintf_unfiltered (file
,
6290 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6291 MACHINE_CPROC_PC_OFFSET
);
6293 #ifdef MACHINE_CPROC_SP_OFFSET
6294 fprintf_unfiltered (file
,
6295 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6296 MACHINE_CPROC_SP_OFFSET
);
6298 fprintf_unfiltered (file
,
6299 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6301 fprintf_unfiltered (file
,
6302 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6303 fprintf_unfiltered (file
,
6304 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6305 fprintf_unfiltered (file
,
6306 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6308 fprintf_unfiltered (file
,
6309 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6310 MIPS_LAST_ARG_REGNUM
,
6311 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6312 fprintf_unfiltered (file
,
6313 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6315 fprintf_unfiltered (file
,
6316 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6317 fprintf_unfiltered (file
,
6318 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6319 MIPS_SAVED_REGSIZE
);
6320 fprintf_unfiltered (file
,
6321 "mips_dump_tdep: PRID_REGNUM = %d\n",
6323 fprintf_unfiltered (file
,
6324 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6327 fprintf_unfiltered (file
,
6328 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6329 fprintf_unfiltered (file
,
6330 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6331 fprintf_unfiltered (file
,
6332 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6333 fprintf_unfiltered (file
,
6334 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6335 fprintf_unfiltered (file
,
6336 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6337 fprintf_unfiltered (file
,
6338 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6339 fprintf_unfiltered (file
,
6340 "mips_dump_tdep: PROC_PC_REG = function?\n");
6341 fprintf_unfiltered (file
,
6342 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6343 fprintf_unfiltered (file
,
6344 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6345 fprintf_unfiltered (file
,
6346 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6347 fprintf_unfiltered (file
,
6348 "mips_dump_tdep: PS_REGNUM = %d\n",
6350 fprintf_unfiltered (file
,
6351 "mips_dump_tdep: RA_REGNUM = %d\n",
6354 fprintf_unfiltered (file
,
6355 "mips_dump_tdep: SAVED_BYTES = %d\n",
6359 fprintf_unfiltered (file
,
6360 "mips_dump_tdep: SAVED_FP = %d\n",
6364 fprintf_unfiltered (file
,
6365 "mips_dump_tdep: SAVED_PC = %d\n",
6368 fprintf_unfiltered (file
,
6369 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6370 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6371 fprintf_unfiltered (file
,
6372 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6373 fprintf_unfiltered (file
,
6374 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6376 fprintf_unfiltered (file
,
6377 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6378 SIGFRAME_FPREGSAVE_OFF
);
6379 fprintf_unfiltered (file
,
6380 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6382 fprintf_unfiltered (file
,
6383 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6384 SIGFRAME_REGSAVE_OFF
);
6385 fprintf_unfiltered (file
,
6386 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6388 fprintf_unfiltered (file
,
6389 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6390 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6391 fprintf_unfiltered (file
,
6392 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6393 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6394 fprintf_unfiltered (file
,
6395 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6396 SOFTWARE_SINGLE_STEP_P ());
6397 fprintf_unfiltered (file
,
6398 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6399 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6400 #ifdef STACK_END_ADDR
6401 fprintf_unfiltered (file
,
6402 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6405 fprintf_unfiltered (file
,
6406 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6407 XSTRING (STEP_SKIPS_DELAY (PC
)));
6408 fprintf_unfiltered (file
,
6409 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6410 STEP_SKIPS_DELAY_P
);
6411 fprintf_unfiltered (file
,
6412 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6413 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6414 fprintf_unfiltered (file
,
6415 "mips_dump_tdep: T9_REGNUM = %d\n",
6417 fprintf_unfiltered (file
,
6418 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6419 fprintf_unfiltered (file
,
6420 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6421 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6422 fprintf_unfiltered (file
,
6423 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6424 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6426 fprintf_unfiltered (file
,
6427 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6428 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6431 fprintf_unfiltered (file
,
6432 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6435 #ifdef TRACE_FLAVOR_SIZE
6436 fprintf_unfiltered (file
,
6437 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6441 fprintf_unfiltered (file
,
6442 "mips_dump_tdep: TRACE_SET # %s\n",
6443 XSTRING (TRACE_SET (X
,STATE
)));
6445 #ifdef UNUSED_REGNUM
6446 fprintf_unfiltered (file
,
6447 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6450 fprintf_unfiltered (file
,
6451 "mips_dump_tdep: V0_REGNUM = %d\n",
6453 fprintf_unfiltered (file
,
6454 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6455 (long) VM_MIN_ADDRESS
);
6456 fprintf_unfiltered (file
,
6457 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6459 fprintf_unfiltered (file
,
6460 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6464 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6467 _initialize_mips_tdep (void)
6469 static struct cmd_list_element
*mipsfpulist
= NULL
;
6470 struct cmd_list_element
*c
;
6472 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6473 if (MIPS_ABI_LAST
+ 1
6474 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6475 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6477 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6479 /* Add root prefix command for all "set mips"/"show mips" commands */
6480 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6481 "Various MIPS specific commands.",
6482 &setmipscmdlist
, "set mips ", 0, &setlist
);
6484 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6485 "Various MIPS specific commands.",
6486 &showmipscmdlist
, "show mips ", 0, &showlist
);
6488 /* Allow the user to override the saved register size. */
6489 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6492 &mips_saved_regsize_string
, "\
6493 Set size of general purpose registers saved on the stack.\n\
6494 This option can be set to one of:\n\
6495 32 - Force GDB to treat saved GP registers as 32-bit\n\
6496 64 - Force GDB to treat saved GP registers as 64-bit\n\
6497 auto - Allow GDB to use the target's default setting or autodetect the\n\
6498 saved GP register size from information contained in the executable.\n\
6503 /* Allow the user to override the argument stack size. */
6504 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6507 &mips_stack_argsize_string
, "\
6508 Set the amount of stack space reserved for each argument.\n\
6509 This option can be set to one of:\n\
6510 32 - Force GDB to allocate 32-bit chunks per argument\n\
6511 64 - Force GDB to allocate 64-bit chunks per argument\n\
6512 auto - Allow GDB to determine the correct setting from the current\n\
6513 target and executable (default)",
6517 /* Allow the user to override the ABI. */
6518 c
= add_set_enum_cmd
6519 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6520 "Set the ABI used by this program.\n"
6521 "This option can be set to one of:\n"
6522 " auto - the default ABI associated with the current binary\n"
6530 set_cmd_sfunc (c
, mips_abi_update
);
6531 add_cmd ("abi", class_obscure
, show_mips_abi
,
6532 "Show ABI in use by MIPS target", &showmipscmdlist
);
6534 /* Let the user turn off floating point and set the fence post for
6535 heuristic_proc_start. */
6537 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6538 "Set use of MIPS floating-point coprocessor.",
6539 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6540 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6541 "Select single-precision MIPS floating-point coprocessor.",
6543 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6544 "Select double-precision MIPS floating-point coprocessor.",
6546 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6547 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6548 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6549 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6550 "Select no MIPS floating-point coprocessor.",
6552 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6553 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6554 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6555 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6556 "Select MIPS floating-point coprocessor automatically.",
6558 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6559 "Show current use of MIPS floating-point coprocessor target.",
6562 /* We really would like to have both "0" and "unlimited" work, but
6563 command.c doesn't deal with that. So make it a var_zinteger
6564 because the user can always use "999999" or some such for unlimited. */
6565 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6566 (char *) &heuristic_fence_post
,
6568 Set the distance searched for the start of a function.\n\
6569 If you are debugging a stripped executable, GDB needs to search through the\n\
6570 program for the start of a function. This command sets the distance of the\n\
6571 search. The only need to set it is when debugging a stripped executable.",
6573 /* We need to throw away the frame cache when we set this, since it
6574 might change our ability to get backtraces. */
6575 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6576 add_show_from_set (c
, &showlist
);
6578 /* Allow the user to control whether the upper bits of 64-bit
6579 addresses should be zeroed. */
6580 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6581 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6582 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6583 allow GDB to determine the correct value.\n", "\
6584 Show zeroing of upper 32 bits of 64-bit addresses.",
6585 NULL
, show_mask_address
,
6586 &setmipscmdlist
, &showmipscmdlist
);
6588 /* Allow the user to control the size of 32 bit registers within the
6589 raw remote packet. */
6590 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6593 (char *)&mips64_transfers_32bit_regs_p
, "\
6594 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6595 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6596 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6597 64 bits for others. Use \"off\" to disable compatibility mode",
6601 /* Debug this files internals. */
6602 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6603 &mips_debug
, "Set mips debugging.\n\
6604 When non-zero, mips specific debugging is enabled.", &setdebuglist
),