1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988-1999, Free Software Foundation, Inc.
3 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
4 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
36 #include "arch-utils.h"
38 #include "opcode/mips.h"
43 struct frame_extra_info
45 mips_extra_func_info_t proc_desc
;
49 /* Various MIPS ISA options (related to stack analysis) can be
50 overridden dynamically. Establish an enum/array for managing
53 static char size_auto
[] = "auto";
54 static char size_32
[] = "32";
55 static char size_64
[] = "64";
57 static char *size_enums
[] = {
64 /* Some MIPS boards don't support floating point while others only
65 support single-precision floating-point operations. See also
66 FP_REGISTER_DOUBLE. */
70 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
71 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
72 MIPS_FPU_NONE
/* No floating point. */
75 #ifndef MIPS_DEFAULT_FPU_TYPE
76 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
78 static int mips_fpu_type_auto
= 1;
79 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
80 #define MIPS_FPU_TYPE mips_fpu_type
82 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
83 #ifndef FP_REGISTER_DOUBLE
84 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
88 /* MIPS specific per-architecture information */
91 /* from the elf header */
95 enum mips_fpu_type mips_fpu_type
;
96 int mips_last_arg_regnum
;
97 int mips_last_fp_arg_regnum
;
98 int mips_default_saved_regsize
;
99 int mips_fp_register_double
;
100 int mips_regs_have_home_p
;
101 int mips_default_stack_argsize
;
106 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_eabi)
110 #undef MIPS_LAST_FP_ARG_REGNUM
111 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
115 #undef MIPS_LAST_ARG_REGNUM
116 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
121 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
124 /* Return the currently configured (or set) saved register size. */
127 #undef MIPS_DEFAULT_SAVED_REGSIZE
128 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
129 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
130 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
133 static char *mips_saved_regsize_string
= size_auto
;
135 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
138 mips_saved_regsize ()
140 if (mips_saved_regsize_string
== size_auto
)
141 return MIPS_DEFAULT_SAVED_REGSIZE
;
142 else if (mips_saved_regsize_string
== size_64
)
144 else /* if (mips_saved_regsize_string == size_32) */
148 /* Indicate that the ABI makes use of double-precision registers
149 provided by the FPU (rather than combining pairs of registers to
150 form double-precision values). Do not use "TARGET_IS_MIPS64" to
151 determine if the ABI is using double-precision registers. See also
154 #undef FP_REGISTER_DOUBLE
155 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
158 /* Does the caller allocate a ``home'' for each register used in the
159 function call? The N32 ABI and MIPS_EABI do not, the others do. */
162 #undef MIPS_REGS_HAVE_HOME_P
163 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
164 #elif !defined (MIPS_REGS_HAVE_HOME_P)
165 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
168 /* The amount of space reserved on the stack for registers. This is
169 different to MIPS_SAVED_REGSIZE as it determines the alignment of
170 data allocated after the registers have run out. */
173 #undef MIPS_DEFAULT_STACK_ARGSIZE
174 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_statck_argsize)
175 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
176 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
179 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
181 static char *mips_stack_argsize_string
= size_auto
;
184 mips_stack_argsize (void)
186 if (mips_stack_argsize_string
== size_auto
)
187 return MIPS_DEFAULT_STACK_ARGSIZE
;
188 else if (mips_stack_argsize_string
== size_64
)
190 else /* if (mips_stack_argsize_string == size_32) */
196 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
199 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
202 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
204 static void mips_print_register
PARAMS ((int, int));
206 static mips_extra_func_info_t
207 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
209 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
211 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
213 int mips_set_processor_type
PARAMS ((char *));
215 static void mips_show_processor_type_command
PARAMS ((char *, int));
217 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
218 struct cmd_list_element
*));
220 static mips_extra_func_info_t
221 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
* next_frame
));
223 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
224 mips_extra_func_info_t proc_desc
));
226 /* This value is the model of MIPS in use. It is derived from the value
227 of the PrID register. */
229 char *mips_processor_type
;
231 char *tmp_mips_processor_type
;
233 /* A set of original names, to be used when restoring back to generic
234 registers from a specific set. */
236 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
237 char **mips_processor_reg_names
= mips_generic_reg_names
;
239 /* The list of available "set mips " and "show mips " commands */
240 static struct cmd_list_element
*setmipscmdlist
= NULL
;
241 static struct cmd_list_element
*showmipscmdlist
= NULL
;
244 mips_register_name (i
)
247 return mips_processor_reg_names
[i
];
250 /* Names of IDT R3041 registers. */
252 char *mips_r3041_reg_names
[] = {
253 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
254 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
255 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
256 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
257 "sr", "lo", "hi", "bad", "cause","pc",
258 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
259 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
260 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
261 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
262 "fsr", "fir", "fp", "",
263 "", "", "bus", "ccfg", "", "", "", "",
264 "", "", "port", "cmp", "", "", "epc", "prid",
267 /* Names of IDT R3051 registers. */
269 char *mips_r3051_reg_names
[] = {
270 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
271 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
272 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
273 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
274 "sr", "lo", "hi", "bad", "cause","pc",
275 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
276 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
277 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
278 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
279 "fsr", "fir", "fp", "",
280 "inx", "rand", "elo", "", "ctxt", "", "", "",
281 "", "", "ehi", "", "", "", "epc", "prid",
284 /* Names of IDT R3081 registers. */
286 char *mips_r3081_reg_names
[] = {
287 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
288 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
289 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
290 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
291 "sr", "lo", "hi", "bad", "cause","pc",
292 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
293 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
294 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
295 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
296 "fsr", "fir", "fp", "",
297 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
298 "", "", "ehi", "", "", "", "epc", "prid",
301 /* Names of LSI 33k registers. */
303 char *mips_lsi33k_reg_names
[] = {
304 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
305 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
306 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
307 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
308 "epc", "hi", "lo", "sr", "cause","badvaddr",
309 "dcic", "bpc", "bda", "", "", "", "", "",
310 "", "", "", "", "", "", "", "",
311 "", "", "", "", "", "", "", "",
312 "", "", "", "", "", "", "", "",
314 "", "", "", "", "", "", "", "",
315 "", "", "", "", "", "", "", "",
321 } mips_processor_type_table
[] = {
322 { "generic", mips_generic_reg_names
},
323 { "r3041", mips_r3041_reg_names
},
324 { "r3051", mips_r3051_reg_names
},
325 { "r3071", mips_r3081_reg_names
},
326 { "r3081", mips_r3081_reg_names
},
327 { "lsi33k", mips_lsi33k_reg_names
},
335 /* Table to translate MIPS16 register field to actual register number. */
336 static int mips16_to_32_reg
[8] =
337 {16, 17, 2, 3, 4, 5, 6, 7};
339 /* Heuristic_proc_start may hunt through the text section for a long
340 time across a 2400 baud serial line. Allows the user to limit this
343 static unsigned int heuristic_fence_post
= 0;
345 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
346 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
347 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
348 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
349 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
350 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
351 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
352 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
353 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
354 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
355 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
356 #define _PROC_MAGIC_ 0x0F0F0F0F
357 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
358 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
360 struct linked_proc_info
362 struct mips_extra_func_info info
;
363 struct linked_proc_info
*next
;
365 *linked_proc_desc_table
= NULL
;
368 mips_print_extra_frame_info (fi
)
369 struct frame_info
*fi
;
373 && fi
->extra_info
->proc_desc
374 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
375 printf_filtered (" frame pointer is at %s+%s\n",
376 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
377 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
380 /* Convert between RAW and VIRTUAL registers. The RAW register size
381 defines the remote-gdb packet. */
383 static int mips64_transfers_32bit_regs_p
= 0;
386 mips_register_raw_size (reg_nr
)
389 if (mips64_transfers_32bit_regs_p
)
390 return REGISTER_VIRTUAL_SIZE (reg_nr
);
396 mips_register_convertible (reg_nr
)
399 if (mips64_transfers_32bit_regs_p
)
402 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
406 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
408 struct type
*virtual_type
;
412 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
414 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
415 TYPE_LENGTH (virtual_type
));
419 TYPE_LENGTH (virtual_type
));
423 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
424 struct type
*virtual_type
;
429 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
430 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
431 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
433 TYPE_LENGTH (virtual_type
));
437 TYPE_LENGTH (virtual_type
));
440 /* Should the upper word of 64-bit addresses be zeroed? */
441 static int mask_address_p
= 1;
443 /* Should call_function allocate stack space for a struct return? */
445 mips_use_struct_convention (gcc_p
, type
)
450 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
452 return 1; /* Structures are returned by ref in extra arg0 */
455 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
458 pc_is_mips16 (bfd_vma memaddr
)
460 struct minimal_symbol
*sym
;
462 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
463 if (IS_MIPS16_ADDR (memaddr
))
466 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
467 the high bit of the info field. Use this to decide if the function is
468 MIPS16 or normal MIPS. */
469 sym
= lookup_minimal_symbol_by_pc (memaddr
);
471 return MSYMBOL_IS_SPECIAL (sym
);
477 /* This returns the PC of the first inst after the prologue. If we can't
478 find the prologue, then return 0. */
481 after_prologue (pc
, proc_desc
)
483 mips_extra_func_info_t proc_desc
;
485 struct symtab_and_line sal
;
486 CORE_ADDR func_addr
, func_end
;
489 proc_desc
= find_proc_desc (pc
, NULL
);
493 /* If function is frameless, then we need to do it the hard way. I
494 strongly suspect that frameless always means prologueless... */
495 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
496 && PROC_FRAME_OFFSET (proc_desc
) == 0)
500 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
501 return 0; /* Unknown */
503 sal
= find_pc_line (func_addr
, 0);
505 if (sal
.end
< func_end
)
508 /* The line after the prologue is after the end of the function. In this
509 case, tell the caller to find the prologue the hard way. */
514 /* Decode a MIPS32 instruction that saves a register in the stack, and
515 set the appropriate bit in the general register mask or float register mask
516 to indicate which register is saved. This is a helper function
517 for mips_find_saved_regs. */
520 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
522 unsigned long *gen_mask
;
523 unsigned long *float_mask
;
527 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
528 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
529 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
531 /* It might be possible to use the instruction to
532 find the offset, rather than the code below which
533 is based on things being in a certain order in the
534 frame, but figuring out what the instruction's offset
535 is relative to might be a little tricky. */
536 reg
= (inst
& 0x001f0000) >> 16;
537 *gen_mask
|= (1 << reg
);
539 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
540 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
541 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
544 reg
= ((inst
& 0x001f0000) >> 16);
545 *float_mask
|= (1 << reg
);
549 /* Decode a MIPS16 instruction that saves a register in the stack, and
550 set the appropriate bit in the general register or float register mask
551 to indicate which register is saved. This is a helper function
552 for mips_find_saved_regs. */
555 mips16_decode_reg_save (inst
, gen_mask
)
557 unsigned long *gen_mask
;
559 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
561 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
562 *gen_mask
|= (1 << reg
);
564 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
566 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
567 *gen_mask
|= (1 << reg
);
569 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
570 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
571 *gen_mask
|= (1 << RA_REGNUM
);
575 /* Fetch and return instruction from the specified location. If the PC
576 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
579 mips_fetch_instruction (addr
)
582 char buf
[MIPS_INSTLEN
];
586 if (pc_is_mips16 (addr
))
588 instlen
= MIPS16_INSTLEN
;
589 addr
= UNMAKE_MIPS16_ADDR (addr
);
592 instlen
= MIPS_INSTLEN
;
593 status
= read_memory_nobpt (addr
, buf
, instlen
);
595 memory_error (status
, addr
);
596 return extract_unsigned_integer (buf
, instlen
);
600 /* These the fields of 32 bit mips instructions */
601 #define mips32_op(x) (x >> 25)
602 #define itype_op(x) (x >> 25)
603 #define itype_rs(x) ((x >> 21)& 0x1f)
604 #define itype_rt(x) ((x >> 16) & 0x1f)
605 #define itype_immediate(x) ( x & 0xffff)
607 #define jtype_op(x) (x >> 25)
608 #define jtype_target(x) ( x & 0x03fffff)
610 #define rtype_op(x) (x >>25)
611 #define rtype_rs(x) ((x>>21) & 0x1f)
612 #define rtype_rt(x) ((x>>16) & 0x1f)
613 #define rtype_rd(x) ((x>>11) & 0x1f)
614 #define rtype_shamt(x) ((x>>6) & 0x1f)
615 #define rtype_funct(x) (x & 0x3f )
618 mips32_relative_offset (unsigned long inst
)
621 x
= itype_immediate (inst
);
622 if (x
& 0x8000) /* sign bit set */
624 x
|= 0xffff0000; /* sign extension */
630 /* Determine whate to set a single step breakpoint while considering
633 mips32_next_pc (CORE_ADDR pc
)
637 inst
= mips_fetch_instruction (pc
);
638 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
640 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
642 op
= ((inst
>> 25) & 0x03);
646 goto equal_branch
; /* BEQL */
648 goto neq_branch
; /* BNEZ */
650 goto less_branch
; /* BLEZ */
652 goto greater_branch
; /* BGTZ */
658 pc
+= 4; /* Not a branch, next instruction is easy */
661 { /* This gets way messy */
663 /* Further subdivide into SPECIAL, REGIMM and other */
664 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
666 case 0: /* SPECIAL */
667 op
= rtype_funct (inst
);
672 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
678 break; /* end special */
681 op
= jtype_op (inst
); /* branch condition */
682 switch (jtype_op (inst
))
686 case 16: /* BLTZALL */
687 case 18: /* BLTZALL */
689 if (read_register (itype_rs (inst
)) < 0)
690 pc
+= mips32_relative_offset (inst
) + 4;
692 pc
+= 8; /* after the delay slot */
696 case 17: /* BGEZAL */
697 case 19: /* BGEZALL */
698 greater_equal_branch
:
699 if (read_register (itype_rs (inst
)) >= 0)
700 pc
+= mips32_relative_offset (inst
) + 4;
702 pc
+= 8; /* after the delay slot */
704 /* All of the other intructions in the REGIMM catagory */
709 break; /* end REGIMM */
714 reg
= jtype_target (inst
) << 2;
715 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
716 /* Whats this mysterious 0xf000000 adjustment ??? */
719 /* FIXME case JALX : */
722 reg
= jtype_target (inst
) << 2;
723 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
724 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
726 break; /* The new PC will be alternate mode */
727 case 4: /* BEQ , BEQL */
729 if (read_register (itype_rs (inst
)) ==
730 read_register (itype_rt (inst
)))
731 pc
+= mips32_relative_offset (inst
) + 4;
735 case 5: /* BNE , BNEL */
737 if (read_register (itype_rs (inst
)) !=
738 read_register (itype_rs (inst
)))
739 pc
+= mips32_relative_offset (inst
) + 4;
743 case 6: /* BLEZ , BLEZL */
745 if (read_register (itype_rs (inst
) <= 0))
746 pc
+= mips32_relative_offset (inst
) + 4;
751 greater_branch
: /* BGTZ BGTZL */
752 if (read_register (itype_rs (inst
) > 0))
753 pc
+= mips32_relative_offset (inst
) + 4;
762 } /* mips32_next_pc */
764 /* Decoding the next place to set a breakpoint is irregular for the
765 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
766 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
767 We dont want to set a single step instruction on the extend instruction
771 /* Lots of mips16 instruction formats */
772 /* Predicting jumps requires itype,ritype,i8type
773 and their extensions extItype,extritype,extI8type
775 enum mips16_inst_fmts
777 itype
, /* 0 immediate 5,10 */
778 ritype
, /* 1 5,3,8 */
779 rrtype
, /* 2 5,3,3,5 */
780 rritype
, /* 3 5,3,3,5 */
781 rrrtype
, /* 4 5,3,3,3,2 */
782 rriatype
, /* 5 5,3,3,1,4 */
783 shifttype
, /* 6 5,3,3,3,2 */
784 i8type
, /* 7 5,3,8 */
785 i8movtype
, /* 8 5,3,3,5 */
786 i8mov32rtype
, /* 9 5,3,5,3 */
787 i64type
, /* 10 5,3,8 */
788 ri64type
, /* 11 5,3,3,5 */
789 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
790 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
791 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
792 extRRItype
, /* 15 5,5,5,5,3,3,5 */
793 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
794 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
795 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
796 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
797 extRi64type
, /* 20 5,6,5,5,3,3,5 */
798 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
800 /* I am heaping all the fields of the formats into one structure and then,
801 only the fields which are involved in instruction extension */
805 enum mips16_inst_fmts fmt
;
806 unsigned long offset
;
807 unsigned int regx
; /* Function in i8 type */
814 print_unpack (char *comment
,
815 struct upk_mips16
*u
)
817 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
818 comment
, u
->inst
, u
->fmt
, paddr (u
->offset
), u
->regx
, u
->regy
);
821 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
822 format for the bits which make up the immediatate extension.
825 extended_offset (unsigned long extension
)
828 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
830 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
832 value
|= extension
& 0x01f; /* extract 4:0 */
836 /* Only call this function if you know that this is an extendable
837 instruction, It wont malfunction, but why make excess remote memory references?
838 If the immediate operands get sign extended or somthing, do it after
839 the extension is performed.
841 /* FIXME: Every one of these cases needs to worry about sign extension
842 when the offset is to be used in relative addressing */
845 static unsigned short
846 fetch_mips_16 (CORE_ADDR pc
)
849 pc
&= 0xfffffffe; /* clear the low order bit */
850 target_read_memory (pc
, buf
, 2);
851 return extract_unsigned_integer (buf
, 2);
855 unpack_mips16 (CORE_ADDR pc
,
856 struct upk_mips16
*upk
)
859 unsigned long extension
;
861 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
862 /* Decrement to previous address and loose the 16bit mode flag */
863 /* return if the instruction was extendable, but not actually extended */
864 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
867 extension
= mips_fetch_instruction (extpc
);
876 value
= extended_offset (extension
);
877 value
= value
<< 11; /* rom for the original value */
878 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
882 value
= upk
->inst
& 0x7ff;
883 /* FIXME : Consider sign extension */
890 { /* A register identifier and an offset */
891 /* Most of the fields are the same as I type but the
892 immediate value is of a different length */
896 value
= extended_offset (extension
);
897 value
= value
<< 8; /* from the original instruction */
898 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
899 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
900 if (value
& 0x4000) /* test the sign bit , bit 26 */
902 value
&= ~0x3fff; /* remove the sign bit */
908 value
= upk
->inst
& 0xff; /* 8 bits */
909 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
910 /* FIXME: Do sign extension , this format needs it */
911 if (value
& 0x80) /* THIS CONFUSES ME */
913 value
&= 0xef; /* remove the sign bit */
924 unsigned short nexthalf
;
925 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
927 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
933 printf_filtered ("Decoding unimplemented instruction format type\n");
936 /* print_unpack("UPK",upk) ; */
940 #define mips16_op(x) (x >> 11)
942 /* This is a map of the opcodes which ae known to perform branches */
943 static unsigned char map16
[32] =
944 {0, 0, 1, 1, 1, 1, 0, 0,
945 0, 0, 0, 0, 1, 0, 0, 0,
946 0, 0, 0, 0, 0, 0, 0, 0,
947 0, 0, 0, 0, 0, 1, 1, 0
951 add_offset_16 (CORE_ADDR pc
, int offset
)
953 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
959 static struct upk_mips16 upk
;
962 mips16_next_pc (CORE_ADDR pc
)
966 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
967 inst
= fetch_mips_16 (pc
);
969 op
= mips16_op (upk
.inst
);
977 unpack_mips16 (pc
, &upk
);
986 pc
+= (offset
<< 1) + 2;
989 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
991 unpack_mips16 (pc
, &upk
);
992 pc
= add_offset_16 (pc
, upk
.offset
);
993 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
994 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1000 unpack_mips16 (pc
, &upk
);
1001 reg
= read_register (upk
.regx
);
1003 pc
+= (upk
.offset
<< 1) + 2;
1009 unpack_mips16 (pc
, &upk
);
1010 reg
= read_register (upk
.regx
);
1012 pc
+= (upk
.offset
<< 1) + 2;
1016 case 12: /* I8 Formats btez btnez */
1018 unpack_mips16 (pc
, &upk
);
1019 /* upk.regx contains the opcode */
1020 reg
= read_register (24); /* Test register is 24 */
1021 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1022 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1023 /* pc = add_offset_16(pc,upk.offset) ; */
1024 pc
+= (upk
.offset
<< 1) + 2;
1028 case 29: /* RR Formats JR, JALR, JALR-RA */
1030 op
= upk
.inst
& 0x1f;
1033 upk
.regx
= (upk
.inst
>> 8) & 0x07;
1034 upk
.regy
= (upk
.inst
>> 5) & 0x07;
1042 break; /* Function return instruction */
1048 break; /* BOGUS Guess */
1050 pc
= read_register (reg
);
1055 case 30: /* This is an extend instruction */
1056 pc
+= 4; /* Dont be setting breakpints on the second half */
1059 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
1065 pc
+= 2; /* just a good old instruction */
1066 /* See if we CAN actually break on the next instruction */
1067 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
1069 } /* mips16_next_pc */
1071 /* The mips_next_pc function supports single_tep when the remote target monitor or
1072 stub is not developed enough to so a single_step.
1073 It works by decoding the current instruction and predicting where a branch
1074 will go. This isnt hard because all the data is available.
1075 The MIPS32 and MIPS16 variants are quite different
1078 mips_next_pc (CORE_ADDR pc
)
1081 /* inst = mips_fetch_instruction(pc) ; */
1082 /* if (pc_is_mips16) <----- This is failing */
1084 return mips16_next_pc (pc
);
1086 return mips32_next_pc (pc
);
1087 } /* mips_next_pc */
1089 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1093 mips_find_saved_regs (fci
)
1094 struct frame_info
*fci
;
1097 CORE_ADDR reg_position
;
1098 /* r0 bit means kernel trap */
1100 /* What registers have been saved? Bitmasks. */
1101 unsigned long gen_mask
, float_mask
;
1102 mips_extra_func_info_t proc_desc
;
1105 frame_saved_regs_zalloc (fci
);
1107 /* If it is the frame for sigtramp, the saved registers are located
1108 in a sigcontext structure somewhere on the stack.
1109 If the stack layout for sigtramp changes we might have to change these
1110 constants and the companion fixup_sigtramp in mdebugread.c */
1111 #ifndef SIGFRAME_BASE
1112 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1113 above the sigtramp frame. */
1114 #define SIGFRAME_BASE MIPS_REGSIZE
1115 /* FIXME! Are these correct?? */
1116 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1117 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1118 #define SIGFRAME_FPREGSAVE_OFF \
1119 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1121 #ifndef SIGFRAME_REG_SIZE
1122 /* FIXME! Is this correct?? */
1123 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1125 if (fci
->signal_handler_caller
)
1127 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1129 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1130 + ireg
* SIGFRAME_REG_SIZE
;
1131 fci
->saved_regs
[ireg
] = reg_position
;
1133 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1135 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1136 + ireg
* SIGFRAME_REG_SIZE
;
1137 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1139 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1143 proc_desc
= fci
->extra_info
->proc_desc
;
1144 if (proc_desc
== NULL
)
1145 /* I'm not sure how/whether this can happen. Normally when we can't
1146 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1147 and set the saved_regs right away. */
1150 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1151 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1152 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1154 if ( /* In any frame other than the innermost or a frame interrupted by
1155 a signal, we assume that all registers have been saved.
1156 This assumes that all register saves in a function happen before
1157 the first function call. */
1158 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1160 /* In a dummy frame we know exactly where things are saved. */
1161 && !PROC_DESC_IS_DUMMY (proc_desc
)
1163 /* Don't bother unless we are inside a function prologue. Outside the
1164 prologue, we know where everything is. */
1166 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1168 /* Not sure exactly what kernel_trap means, but if it means
1169 the kernel saves the registers without a prologue doing it,
1170 we better not examine the prologue to see whether registers
1171 have been saved yet. */
1174 /* We need to figure out whether the registers that the proc_desc
1175 claims are saved have been saved yet. */
1179 /* Bitmasks; set if we have found a save for the register. */
1180 unsigned long gen_save_found
= 0;
1181 unsigned long float_save_found
= 0;
1184 /* If the address is odd, assume this is MIPS16 code. */
1185 addr
= PROC_LOW_ADDR (proc_desc
);
1186 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1188 /* Scan through this function's instructions preceding the current
1189 PC, and look for those that save registers. */
1190 while (addr
< fci
->pc
)
1192 inst
= mips_fetch_instruction (addr
);
1193 if (pc_is_mips16 (addr
))
1194 mips16_decode_reg_save (inst
, &gen_save_found
);
1196 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1199 gen_mask
= gen_save_found
;
1200 float_mask
= float_save_found
;
1203 /* Fill in the offsets for the registers which gen_mask says
1205 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1206 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1207 if (gen_mask
& 0x80000000)
1209 fci
->saved_regs
[ireg
] = reg_position
;
1210 reg_position
-= MIPS_SAVED_REGSIZE
;
1213 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1214 of that normally used by gcc. Therefore, we have to fetch the first
1215 instruction of the function, and if it's an entry instruction that
1216 saves $s0 or $s1, correct their saved addresses. */
1217 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1219 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1220 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1223 int sreg_count
= (inst
>> 6) & 3;
1225 /* Check if the ra register was pushed on the stack. */
1226 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1228 reg_position
-= MIPS_SAVED_REGSIZE
;
1230 /* Check if the s0 and s1 registers were pushed on the stack. */
1231 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1233 fci
->saved_regs
[reg
] = reg_position
;
1234 reg_position
-= MIPS_SAVED_REGSIZE
;
1239 /* Fill in the offsets for the registers which float_mask says
1241 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1243 /* The freg_offset points to where the first *double* register
1244 is saved. So skip to the high-order word. */
1245 if (!GDB_TARGET_IS_MIPS64
)
1246 reg_position
+= MIPS_SAVED_REGSIZE
;
1248 /* Fill in the offsets for the float registers which float_mask says
1250 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1251 if (float_mask
& 0x80000000)
1253 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1254 reg_position
-= MIPS_SAVED_REGSIZE
;
1257 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1261 read_next_frame_reg (fi
, regno
)
1262 struct frame_info
*fi
;
1265 for (; fi
; fi
= fi
->next
)
1267 /* We have to get the saved sp from the sigcontext
1268 if it is a signal handler frame. */
1269 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1273 if (fi
->saved_regs
== NULL
)
1274 mips_find_saved_regs (fi
);
1275 if (fi
->saved_regs
[regno
])
1276 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1279 return read_register (regno
);
1282 /* mips_addr_bits_remove - remove useless address bits */
1285 mips_addr_bits_remove (addr
)
1288 #if GDB_TARGET_IS_MIPS64
1289 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1291 /* This hack is a work-around for existing boards using PMON,
1292 the simulator, and any other 64-bit targets that doesn't have
1293 true 64-bit addressing. On these targets, the upper 32 bits
1294 of addresses are ignored by the hardware. Thus, the PC or SP
1295 are likely to have been sign extended to all 1s by instruction
1296 sequences that load 32-bit addresses. For example, a typical
1297 piece of code that loads an address is this:
1298 lui $r2, <upper 16 bits>
1299 ori $r2, <lower 16 bits>
1300 But the lui sign-extends the value such that the upper 32 bits
1301 may be all 1s. The workaround is simply to mask off these bits.
1302 In the future, gcc may be changed to support true 64-bit
1303 addressing, and this masking will have to be disabled. */
1304 addr
&= (CORE_ADDR
) 0xffffffff;
1307 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1308 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1309 So we still have to mask off useless bits from addresses. */
1310 addr
&= (CORE_ADDR
) 0xffffffff;
1317 mips_init_frame_pc_first (fromleaf
, prev
)
1319 struct frame_info
*prev
;
1323 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1324 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1325 tmp
= mips_skip_stub (pc
);
1326 prev
->pc
= tmp
? tmp
: pc
;
1331 mips_frame_saved_pc (frame
)
1332 struct frame_info
*frame
;
1335 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1336 /* We have to get the saved pc from the sigcontext
1337 if it is a signal handler frame. */
1338 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1339 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1341 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1342 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1344 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1346 return ADDR_BITS_REMOVE (saved_pc
);
1349 static struct mips_extra_func_info temp_proc_desc
;
1350 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1352 /* Set a register's saved stack address in temp_saved_regs. If an address
1353 has already been set for this register, do nothing; this way we will
1354 only recognize the first save of a given register in a function prologue.
1355 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1358 set_reg_offset (regno
, offset
)
1362 if (temp_saved_regs
[regno
] == 0)
1363 temp_saved_regs
[regno
] = offset
;
1367 /* Test whether the PC points to the return instruction at the
1368 end of a function. */
1371 mips_about_to_return (pc
)
1374 if (pc_is_mips16 (pc
))
1375 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1376 generates a "jr $ra"; other times it generates code to load
1377 the return address from the stack to an accessible register (such
1378 as $a3), then a "jr" using that register. This second case
1379 is almost impossible to distinguish from an indirect jump
1380 used for switch statements, so we don't even try. */
1381 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1383 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1387 /* This fencepost looks highly suspicious to me. Removing it also
1388 seems suspicious as it could affect remote debugging across serial
1392 heuristic_proc_start (pc
)
1400 pc
= ADDR_BITS_REMOVE (pc
);
1402 fence
= start_pc
- heuristic_fence_post
;
1406 if (heuristic_fence_post
== UINT_MAX
1407 || fence
< VM_MIN_ADDRESS
)
1408 fence
= VM_MIN_ADDRESS
;
1410 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1412 /* search back for previous return */
1413 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1414 if (start_pc
< fence
)
1416 /* It's not clear to me why we reach this point when
1417 stop_soon_quietly, but with this test, at least we
1418 don't print out warnings for every child forked (eg, on
1419 decstation). 22apr93 rich@cygnus.com. */
1420 if (!stop_soon_quietly
)
1422 static int blurb_printed
= 0;
1424 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1429 /* This actually happens frequently in embedded
1430 development, when you first connect to a board
1431 and your stack pointer and pc are nowhere in
1432 particular. This message needs to give people
1433 in that situation enough information to
1434 determine that it's no big deal. */
1435 printf_filtered ("\n\
1436 GDB is unable to find the start of the function at 0x%s\n\
1437 and thus can't determine the size of that function's stack frame.\n\
1438 This means that GDB may be unable to access that stack frame, or\n\
1439 the frames below it.\n\
1440 This problem is most likely caused by an invalid program counter or\n\
1442 However, if you think GDB should simply search farther back\n\
1443 from 0x%s for code which looks like the beginning of a\n\
1444 function, you can increase the range of the search using the `set\n\
1445 heuristic-fence-post' command.\n",
1446 paddr_nz (pc
), paddr_nz (pc
));
1453 else if (pc_is_mips16 (start_pc
))
1455 unsigned short inst
;
1457 /* On MIPS16, any one of the following is likely to be the
1458 start of a function:
1462 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1463 inst
= mips_fetch_instruction (start_pc
);
1464 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1465 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1466 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1467 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1469 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1470 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1475 else if (mips_about_to_return (start_pc
))
1477 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1482 /* skip nops (usually 1) 0 - is this */
1483 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1484 start_pc
+= MIPS_INSTLEN
;
1489 /* Fetch the immediate value from a MIPS16 instruction.
1490 If the previous instruction was an EXTEND, use it to extend
1491 the upper bits of the immediate value. This is a helper function
1492 for mips16_heuristic_proc_desc. */
1495 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1496 unsigned short prev_inst
; /* previous instruction */
1497 unsigned short inst
; /* current instruction */
1498 int nbits
; /* number of bits in imm field */
1499 int scale
; /* scale factor to be applied to imm */
1500 int is_signed
; /* is the imm field signed? */
1504 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1506 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1507 if (offset
& 0x8000) /* check for negative extend */
1508 offset
= 0 - (0x10000 - (offset
& 0xffff));
1509 return offset
| (inst
& 0x1f);
1513 int max_imm
= 1 << nbits
;
1514 int mask
= max_imm
- 1;
1515 int sign_bit
= max_imm
>> 1;
1517 offset
= inst
& mask
;
1518 if (is_signed
&& (offset
& sign_bit
))
1519 offset
= 0 - (max_imm
- offset
);
1520 return offset
* scale
;
1525 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1526 stream from start_pc to limit_pc. */
1529 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1530 CORE_ADDR start_pc
, limit_pc
;
1531 struct frame_info
*next_frame
;
1535 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1536 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1537 unsigned inst
= 0; /* current instruction */
1538 unsigned entry_inst
= 0; /* the entry instruction */
1541 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1542 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1544 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1546 /* Save the previous instruction. If it's an EXTEND, we'll extract
1547 the immediate offset extension from it in mips16_get_imm. */
1550 /* Fetch and decode the instruction. */
1551 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1552 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1553 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1555 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1556 if (offset
< 0) /* negative stack adjustment? */
1557 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1559 /* Exit loop if a positive stack adjustment is found, which
1560 usually means that the stack cleanup code in the function
1561 epilogue is reached. */
1564 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1566 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1567 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1568 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1569 set_reg_offset (reg
, sp
+ offset
);
1571 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1573 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1574 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1575 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1576 set_reg_offset (reg
, sp
+ offset
);
1578 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1580 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1581 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1582 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1584 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1586 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1587 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1588 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1590 else if (inst
== 0x673d) /* move $s1, $sp */
1593 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1595 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1597 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1598 frame_addr
= sp
+ offset
;
1599 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1600 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1602 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1604 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1605 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1606 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1607 set_reg_offset (reg
, frame_addr
+ offset
);
1609 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1611 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1612 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1613 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1614 set_reg_offset (reg
, frame_addr
+ offset
);
1616 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1617 entry_inst
= inst
; /* save for later processing */
1618 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1619 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1622 /* The entry instruction is typically the first instruction in a function,
1623 and it stores registers at offsets relative to the value of the old SP
1624 (before the prologue). But the value of the sp parameter to this
1625 function is the new SP (after the prologue has been executed). So we
1626 can't calculate those offsets until we've seen the entire prologue,
1627 and can calculate what the old SP must have been. */
1628 if (entry_inst
!= 0)
1630 int areg_count
= (entry_inst
>> 8) & 7;
1631 int sreg_count
= (entry_inst
>> 6) & 3;
1633 /* The entry instruction always subtracts 32 from the SP. */
1634 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1636 /* Now we can calculate what the SP must have been at the
1637 start of the function prologue. */
1638 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1640 /* Check if a0-a3 were saved in the caller's argument save area. */
1641 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1643 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1644 set_reg_offset (reg
, sp
+ offset
);
1645 offset
+= MIPS_SAVED_REGSIZE
;
1648 /* Check if the ra register was pushed on the stack. */
1650 if (entry_inst
& 0x20)
1652 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1653 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1654 offset
-= MIPS_SAVED_REGSIZE
;
1657 /* Check if the s0 and s1 registers were pushed on the stack. */
1658 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1660 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1661 set_reg_offset (reg
, sp
+ offset
);
1662 offset
-= MIPS_SAVED_REGSIZE
;
1668 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1669 CORE_ADDR start_pc
, limit_pc
;
1670 struct frame_info
*next_frame
;
1674 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1676 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1677 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1678 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1679 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1681 unsigned long inst
, high_word
, low_word
;
1684 /* Fetch the instruction. */
1685 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1687 /* Save some code by pre-extracting some useful fields. */
1688 high_word
= (inst
>> 16) & 0xffff;
1689 low_word
= inst
& 0xffff;
1690 reg
= high_word
& 0x1f;
1692 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1693 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1694 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1696 if (low_word
& 0x8000) /* negative stack adjustment? */
1697 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1699 /* Exit loop if a positive stack adjustment is found, which
1700 usually means that the stack cleanup code in the function
1701 epilogue is reached. */
1704 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1706 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1707 set_reg_offset (reg
, sp
+ low_word
);
1709 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1711 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1712 but the register size used is only 32 bits. Make the address
1713 for the saved register point to the lower 32 bits. */
1714 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1715 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1717 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1719 /* Old gcc frame, r30 is virtual frame pointer. */
1720 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1721 frame_addr
= sp
+ low_word
;
1722 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1724 unsigned alloca_adjust
;
1725 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1726 frame_addr
= read_next_frame_reg (next_frame
, 30);
1727 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1728 if (alloca_adjust
> 0)
1730 /* FP > SP + frame_size. This may be because
1731 * of an alloca or somethings similar.
1732 * Fix sp to "pre-alloca" value, and try again.
1734 sp
+= alloca_adjust
;
1739 /* move $30,$sp. With different versions of gas this will be either
1740 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1741 Accept any one of these. */
1742 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1744 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1745 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1747 unsigned alloca_adjust
;
1748 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1749 frame_addr
= read_next_frame_reg (next_frame
, 30);
1750 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1751 if (alloca_adjust
> 0)
1753 /* FP > SP + frame_size. This may be because
1754 * of an alloca or somethings similar.
1755 * Fix sp to "pre-alloca" value, and try again.
1757 sp
+= alloca_adjust
;
1762 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1764 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1765 set_reg_offset (reg
, frame_addr
+ low_word
);
1770 static mips_extra_func_info_t
1771 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1772 CORE_ADDR start_pc
, limit_pc
;
1773 struct frame_info
*next_frame
;
1775 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1779 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1780 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1781 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1782 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1783 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1785 if (start_pc
+ 200 < limit_pc
)
1786 limit_pc
= start_pc
+ 200;
1787 if (pc_is_mips16 (start_pc
))
1788 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1790 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1791 return &temp_proc_desc
;
1794 static mips_extra_func_info_t
1795 non_heuristic_proc_desc (pc
, addrptr
)
1799 CORE_ADDR startaddr
;
1800 mips_extra_func_info_t proc_desc
;
1801 struct block
*b
= block_for_pc (pc
);
1804 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1806 *addrptr
= startaddr
;
1807 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1811 if (startaddr
> BLOCK_START (b
))
1812 /* This is the "pathological" case referred to in a comment in
1813 print_frame_info. It might be better to move this check into
1817 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1820 /* If we never found a PDR for this function in symbol reading, then
1821 examine prologues to find the information. */
1824 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1825 if (PROC_FRAME_REG (proc_desc
) == -1)
1835 static mips_extra_func_info_t
1836 find_proc_desc (pc
, next_frame
)
1838 struct frame_info
*next_frame
;
1840 mips_extra_func_info_t proc_desc
;
1841 CORE_ADDR startaddr
;
1843 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1847 /* IF this is the topmost frame AND
1848 * (this proc does not have debugging information OR
1849 * the PC is in the procedure prologue)
1850 * THEN create a "heuristic" proc_desc (by analyzing
1851 * the actual code) to replace the "official" proc_desc.
1853 if (next_frame
== NULL
)
1855 struct symtab_and_line val
;
1856 struct symbol
*proc_symbol
=
1857 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1861 val
= find_pc_line (BLOCK_START
1862 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1864 val
.pc
= val
.end
? val
.end
: pc
;
1866 if (!proc_symbol
|| pc
< val
.pc
)
1868 mips_extra_func_info_t found_heuristic
=
1869 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1871 if (found_heuristic
)
1872 proc_desc
= found_heuristic
;
1878 /* Is linked_proc_desc_table really necessary? It only seems to be used
1879 by procedure call dummys. However, the procedures being called ought
1880 to have their own proc_descs, and even if they don't,
1881 heuristic_proc_desc knows how to create them! */
1883 register struct linked_proc_info
*link
;
1885 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1886 if (PROC_LOW_ADDR (&link
->info
) <= pc
1887 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1891 startaddr
= heuristic_proc_start (pc
);
1894 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1900 get_frame_pointer (frame
, proc_desc
)
1901 struct frame_info
*frame
;
1902 mips_extra_func_info_t proc_desc
;
1904 return ADDR_BITS_REMOVE (
1905 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1906 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1909 mips_extra_func_info_t cached_proc_desc
;
1912 mips_frame_chain (frame
)
1913 struct frame_info
*frame
;
1915 mips_extra_func_info_t proc_desc
;
1917 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1919 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1922 /* Check if the PC is inside a call stub. If it is, fetch the
1923 PC of the caller of that stub. */
1924 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1927 /* Look up the procedure descriptor for this PC. */
1928 proc_desc
= find_proc_desc (saved_pc
, frame
);
1932 cached_proc_desc
= proc_desc
;
1934 /* If no frame pointer and frame size is zero, we must be at end
1935 of stack (or otherwise hosed). If we don't check frame size,
1936 we loop forever if we see a zero size frame. */
1937 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1938 && PROC_FRAME_OFFSET (proc_desc
) == 0
1939 /* The previous frame from a sigtramp frame might be frameless
1940 and have frame size zero. */
1941 && !frame
->signal_handler_caller
)
1944 return get_frame_pointer (frame
, proc_desc
);
1948 mips_init_extra_frame_info (fromleaf
, fci
)
1950 struct frame_info
*fci
;
1954 /* Use proc_desc calculated in frame_chain */
1955 mips_extra_func_info_t proc_desc
=
1956 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1958 fci
->extra_info
= (struct frame_extra_info
*)
1959 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1961 fci
->saved_regs
= NULL
;
1962 fci
->extra_info
->proc_desc
=
1963 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1966 /* Fixup frame-pointer - only needed for top frame */
1967 /* This may not be quite right, if proc has a real frame register.
1968 Get the value of the frame relative sp, procedure might have been
1969 interrupted by a signal at it's very start. */
1970 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1971 && !PROC_DESC_IS_DUMMY (proc_desc
))
1972 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1974 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1976 if (proc_desc
== &temp_proc_desc
)
1980 /* Do not set the saved registers for a sigtramp frame,
1981 mips_find_saved_registers will do that for us.
1982 We can't use fci->signal_handler_caller, it is not yet set. */
1983 find_pc_partial_function (fci
->pc
, &name
,
1984 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
1985 if (!IN_SIGTRAMP (fci
->pc
, name
))
1987 frame_saved_regs_zalloc (fci
);
1988 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
1989 fci
->saved_regs
[PC_REGNUM
]
1990 = fci
->saved_regs
[RA_REGNUM
];
1994 /* hack: if argument regs are saved, guess these contain args */
1995 /* assume we can't tell how many args for now */
1996 fci
->extra_info
->num_args
= -1;
1997 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1999 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2001 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2008 /* MIPS stack frames are almost impenetrable. When execution stops,
2009 we basically have to look at symbol information for the function
2010 that we stopped in, which tells us *which* register (if any) is
2011 the base of the frame pointer, and what offset from that register
2012 the frame itself is at.
2014 This presents a problem when trying to examine a stack in memory
2015 (that isn't executing at the moment), using the "frame" command. We
2016 don't have a PC, nor do we have any registers except SP.
2018 This routine takes two arguments, SP and PC, and tries to make the
2019 cached frames look as if these two arguments defined a frame on the
2020 cache. This allows the rest of info frame to extract the important
2021 arguments without difficulty. */
2024 setup_arbitrary_frame (argc
, argv
)
2029 error ("MIPS frame specifications require two arguments: sp and pc");
2031 return create_new_frame (argv
[0], argv
[1]);
2035 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
2040 CORE_ADDR struct_addr
;
2046 int stack_offset
= 0;
2048 /* Macros to round N up or down to the next A boundary; A must be
2050 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2051 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2053 /* First ensure that the stack and structure return address (if any)
2054 are properly aligned. The stack has to be at least 64-bit aligned
2055 even on 32-bit machines, because doubles must be 64-bit aligned.
2056 On at least one MIPS variant, stack frames need to be 128-bit
2057 aligned, so we round to this widest known alignment. */
2058 sp
= ROUND_DOWN (sp
, 16);
2059 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
2061 /* Now make space on the stack for the args. We allocate more
2062 than necessary for EABI, because the first few arguments are
2063 passed in registers, but that's OK. */
2064 for (argnum
= 0; argnum
< nargs
; argnum
++)
2065 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_SAVED_REGSIZE
);
2066 sp
-= ROUND_UP (len
, 16);
2068 /* Initialize the integer and float register pointers. */
2070 float_argreg
= FPA0_REGNUM
;
2072 /* the struct_return pointer occupies the first parameter-passing reg */
2074 write_register (argreg
++, struct_addr
);
2076 /* Now load as many as possible of the first arguments into
2077 registers, and push the rest onto the stack. Loop thru args
2078 from first to last. */
2079 for (argnum
= 0; argnum
< nargs
; argnum
++)
2082 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2083 value_ptr arg
= args
[argnum
];
2084 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2085 int len
= TYPE_LENGTH (arg_type
);
2086 enum type_code typecode
= TYPE_CODE (arg_type
);
2088 /* The EABI passes structures that do not fit in a register by
2089 reference. In all other cases, pass the structure by value. */
2090 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
2091 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2093 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2094 typecode
= TYPE_CODE_PTR
;
2095 len
= MIPS_SAVED_REGSIZE
;
2099 val
= (char *) VALUE_CONTENTS (arg
);
2101 /* 32-bit ABIs always start floating point arguments in an
2102 even-numbered floating point register. */
2103 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
2104 && (float_argreg
& 1))
2107 /* Floating point arguments passed in registers have to be
2108 treated specially. On 32-bit architectures, doubles
2109 are passed in register pairs; the even register gets
2110 the low word, and the odd register gets the high word.
2111 On non-EABI processors, the first two floating point arguments are
2112 also copied to general registers, because MIPS16 functions
2113 don't use float registers for arguments. This duplication of
2114 arguments in general registers can't hurt non-MIPS16 functions
2115 because those registers are normally skipped. */
2116 if (typecode
== TYPE_CODE_FLT
2117 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
2118 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2120 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2122 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2123 unsigned long regval
;
2125 /* Write the low word of the double to the even register(s). */
2126 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2127 write_register (float_argreg
++, regval
);
2129 write_register (argreg
+ 1, regval
);
2131 /* Write the high word of the double to the odd register(s). */
2132 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2133 write_register (float_argreg
++, regval
);
2136 write_register (argreg
, regval
);
2143 /* This is a floating point value that fits entirely
2144 in a single register. */
2145 /* On 32 bit ABI's the float_argreg is further adjusted
2146 above to ensure that it is even register aligned. */
2147 CORE_ADDR regval
= extract_address (val
, len
);
2148 write_register (float_argreg
++, regval
);
2151 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2152 registers for each argument. The below is (my
2153 guess) to ensure that the corresponding integer
2154 register has reserved the same space. */
2155 write_register (argreg
, regval
);
2156 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2162 /* Copy the argument to general registers or the stack in
2163 register-sized pieces. Large arguments are split between
2164 registers and stack. */
2165 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2166 are treated specially: Irix cc passes them in registers
2167 where gcc sometimes puts them on the stack. For maximum
2168 compatibility, we will put them in both places. */
2170 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2171 (len
% MIPS_SAVED_REGSIZE
!= 0));
2174 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2176 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
2178 /* Write this portion of the argument to the stack. */
2179 /* Should shorter than int integer values be
2180 promoted to int before being stored? */
2182 int longword_offset
= 0;
2183 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2185 if (MIPS_STACK_ARGSIZE
== 8 &&
2186 (typecode
== TYPE_CODE_INT
||
2187 typecode
== TYPE_CODE_PTR
||
2188 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2189 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2190 else if ((typecode
== TYPE_CODE_STRUCT
||
2191 typecode
== TYPE_CODE_UNION
) &&
2192 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2193 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2196 write_memory (sp
+ stack_offset
+ longword_offset
,
2200 /* Note!!! This is NOT an else clause.
2201 Odd sized structs may go thru BOTH paths. */
2202 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
2204 CORE_ADDR regval
= extract_address (val
, partial_len
);
2206 /* A non-floating-point argument being passed in a
2207 general register. If a struct or union, and if
2208 the remaining length is smaller than the register
2209 size, we have to adjust the register value on
2212 It does not seem to be necessary to do the
2213 same for integral types.
2215 Also don't do this adjustment on EABI and O64
2219 && MIPS_SAVED_REGSIZE
< 8
2220 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2221 && partial_len
< MIPS_SAVED_REGSIZE
2222 && (typecode
== TYPE_CODE_STRUCT
||
2223 typecode
== TYPE_CODE_UNION
))
2224 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2227 write_register (argreg
, regval
);
2230 /* If this is the old ABI, prevent subsequent floating
2231 point arguments from being passed in floating point
2234 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2240 /* The offset onto the stack at which we will start
2241 copying parameters (after the registers are used up)
2242 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2243 leaves room for the "home" area for register parameters.
2245 In the new EABI (and the NABI32), the 8 register parameters
2246 do not have "home" stack space reserved for them, so the
2247 stack offset does not get incremented until after
2248 we have used up the 8 parameter registers. */
2250 if (MIPS_REGS_HAVE_HOME_P
|| argnum
>= 8)
2251 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2256 /* Return adjusted stack pointer. */
2261 mips_push_return_address (pc
, sp
)
2265 /* Set the return address register to point to the entry
2266 point of the program, where a breakpoint lies in wait. */
2267 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2272 mips_push_register (CORE_ADDR
* sp
, int regno
)
2274 char buffer
[MAX_REGISTER_RAW_SIZE
];
2277 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2279 regsize
= MIPS_SAVED_REGSIZE
;
2280 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2281 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2286 regsize
= REGISTER_RAW_SIZE (regno
);
2290 read_register_gen (regno
, buffer
);
2291 write_memory (*sp
, buffer
+ offset
, regsize
);
2294 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2295 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2298 mips_push_dummy_frame ()
2301 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2302 xmalloc (sizeof (struct linked_proc_info
));
2303 mips_extra_func_info_t proc_desc
= &link
->info
;
2304 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2305 CORE_ADDR old_sp
= sp
;
2306 link
->next
= linked_proc_desc_table
;
2307 linked_proc_desc_table
= link
;
2309 /* FIXME! are these correct ? */
2310 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2311 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2312 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2313 #define FLOAT_SINGLE_REG_SAVE_MASK \
2314 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2316 * The registers we must save are all those not preserved across
2317 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2318 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2319 * and FP Control/Status registers.
2322 * Dummy frame layout:
2325 * Saved MMHI, MMLO, FPC_CSR
2330 * Saved D18 (i.e. F19, F18)
2332 * Saved D0 (i.e. F1, F0)
2333 * Argument build area and stack arguments written via mips_push_arguments
2337 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2338 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2339 PROC_FRAME_OFFSET (proc_desc
) = 0;
2340 PROC_FRAME_ADJUST (proc_desc
) = 0;
2341 mips_push_register (&sp
, PC_REGNUM
);
2342 mips_push_register (&sp
, HI_REGNUM
);
2343 mips_push_register (&sp
, LO_REGNUM
);
2344 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2346 /* Save general CPU registers */
2347 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2348 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2349 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2350 for (ireg
= 32; --ireg
>= 0;)
2351 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2352 mips_push_register (&sp
, ireg
);
2354 /* Save floating point registers starting with high order word */
2355 PROC_FREG_MASK (proc_desc
) =
2356 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2357 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2358 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2360 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2361 for (ireg
= 32; --ireg
>= 0;)
2362 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2363 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2365 /* Update the frame pointer for the call dummy and the stack pointer.
2366 Set the procedure's starting and ending addresses to point to the
2367 call dummy address at the entry point. */
2368 write_register (PUSH_FP_REGNUM
, old_sp
);
2369 write_register (SP_REGNUM
, sp
);
2370 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2371 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2372 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2373 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2379 register int regnum
;
2380 struct frame_info
*frame
= get_current_frame ();
2381 CORE_ADDR new_sp
= FRAME_FP (frame
);
2383 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2385 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2386 if (frame
->saved_regs
== NULL
)
2387 mips_find_saved_regs (frame
);
2388 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2390 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2391 && frame
->saved_regs
[regnum
])
2392 write_register (regnum
,
2393 read_memory_integer (frame
->saved_regs
[regnum
],
2394 MIPS_SAVED_REGSIZE
));
2396 write_register (SP_REGNUM
, new_sp
);
2397 flush_cached_frames ();
2399 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2401 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2403 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2405 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2407 if (&pi_ptr
->info
== proc_desc
)
2412 error ("Can't locate dummy extra frame info\n");
2414 if (prev_ptr
!= NULL
)
2415 prev_ptr
->next
= pi_ptr
->next
;
2417 linked_proc_desc_table
= pi_ptr
->next
;
2421 write_register (HI_REGNUM
,
2422 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2423 MIPS_SAVED_REGSIZE
));
2424 write_register (LO_REGNUM
,
2425 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2426 MIPS_SAVED_REGSIZE
));
2427 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2428 write_register (FCRCS_REGNUM
,
2429 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2430 MIPS_SAVED_REGSIZE
));
2435 mips_print_register (regnum
, all
)
2438 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2440 /* Get the data in raw format. */
2441 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2443 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2447 /* If an even floating point register, also print as double. */
2448 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2449 && !((regnum
- FP0_REGNUM
) & 1))
2450 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2452 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2454 read_relative_register_raw_bytes (regnum
, dbuffer
);
2455 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2456 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2458 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2459 val_print (builtin_type_double
, dbuffer
, 0, 0,
2460 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2461 printf_filtered ("); ");
2463 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2465 /* The problem with printing numeric register names (r26, etc.) is that
2466 the user can't use them on input. Probably the best solution is to
2467 fix it so that either the numeric or the funky (a2, etc.) names
2468 are accepted on input. */
2469 if (regnum
< MIPS_NUMREGS
)
2470 printf_filtered ("(r%d): ", regnum
);
2472 printf_filtered (": ");
2474 /* If virtual format is floating, print it that way. */
2475 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2476 if (FP_REGISTER_DOUBLE
)
2477 { /* show 8-byte floats as float AND double: */
2478 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2480 printf_filtered (" (float) ");
2481 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2482 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2483 printf_filtered (", (double) ");
2484 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2485 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2488 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2489 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2490 /* Else print as integer in hex. */
2495 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2496 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2500 print_scalar_formatted (raw_buffer
+ offset
,
2501 REGISTER_VIRTUAL_TYPE (regnum
),
2502 'x', 0, gdb_stdout
);
2506 /* Replacement for generic do_registers_info.
2507 Print regs in pretty columns. */
2510 do_fp_register_row (regnum
)
2512 { /* do values for FP (float) regs */
2513 char *raw_buffer
[2];
2515 /* use HI and LO to control the order of combining two flt regs */
2516 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2517 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2518 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2519 int inv1
, inv2
, inv3
;
2521 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2522 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2523 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2525 /* Get the data in raw format. */
2526 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2527 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2528 if (REGISTER_RAW_SIZE (regnum
) == 4)
2530 /* 4-byte registers: we can fit two registers per row. */
2531 /* Also print every pair of 4-byte regs as an 8-byte double. */
2532 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2533 error ("can't read register %d (%s)",
2534 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2536 /* copy the two floats into one double, and unpack both */
2537 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2538 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2539 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2540 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2542 printf_filtered (inv1
? " %-5s: <invalid float>" :
2543 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2544 printf_filtered (inv2
? " %-5s: <invalid float>" :
2545 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2546 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2547 " dbl: %-24.17g\n", doub
);
2548 /* may want to do hex display here (future enhancement) */
2552 { /* eight byte registers: print each one as float AND as double. */
2553 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2555 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2556 flt1
= unpack_double (builtin_type_float
,
2557 &raw_buffer
[HI
][offset
], &inv1
);
2558 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2560 printf_filtered (inv1
? " %-5s: <invalid float>" :
2561 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2562 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2563 " dbl: %-24.17g\n", doub
);
2564 /* may want to do hex display here (future enhancement) */
2570 /* Print a row's worth of GP (int) registers, with name labels above */
2573 do_gp_register_row (regnum
)
2576 /* do values for GP (int) regs */
2577 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2578 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2580 int start_regnum
= regnum
;
2581 int numregs
= NUM_REGS
;
2584 /* For GP registers, we print a separate row of names above the vals */
2585 printf_filtered (" ");
2586 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2588 if (*REGISTER_NAME (regnum
) == '\0')
2589 continue; /* unused register */
2590 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2591 break; /* end the row: reached FP register */
2592 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2593 REGISTER_NAME (regnum
));
2596 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2597 start_regnum
); /* print the R0 to R31 names */
2599 regnum
= start_regnum
; /* go back to start of row */
2600 /* now print the values in hex, 4 or 8 to the row */
2601 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2603 if (*REGISTER_NAME (regnum
) == '\0')
2604 continue; /* unused register */
2605 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2606 break; /* end row: reached FP register */
2607 /* OK: get the data in raw format. */
2608 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2609 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2610 /* pad small registers */
2611 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2612 printf_filtered (" ");
2613 /* Now print the register value in hex, endian order. */
2614 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2615 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2616 byte
< REGISTER_RAW_SIZE (regnum
);
2618 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2620 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2623 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2624 printf_filtered (" ");
2627 if (col
> 0) /* ie. if we actually printed anything... */
2628 printf_filtered ("\n");
2633 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2636 mips_do_registers_info (regnum
, fpregs
)
2640 if (regnum
!= -1) /* do one specified register */
2642 if (*(REGISTER_NAME (regnum
)) == '\0')
2643 error ("Not a valid register for the current processor type");
2645 mips_print_register (regnum
, 0);
2646 printf_filtered ("\n");
2649 /* do all (or most) registers */
2652 while (regnum
< NUM_REGS
)
2654 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2655 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2656 regnum
= do_fp_register_row (regnum
); /* FP regs */
2658 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2660 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2665 /* Return number of args passed to a frame. described by FIP.
2666 Can return -1, meaning no way to tell. */
2669 mips_frame_num_args (frame
)
2670 struct frame_info
*frame
;
2672 #if 0 /* FIXME Use or lose this! */
2673 struct chain_info_t
*p
;
2675 p
= mips_find_cached_frame (FRAME_FP (frame
));
2677 return p
->the_info
.numargs
;
2682 /* Is this a branch with a delay slot? */
2684 static int is_delayed
PARAMS ((unsigned long));
2691 for (i
= 0; i
< NUMOPCODES
; ++i
)
2692 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2693 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2695 return (i
< NUMOPCODES
2696 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2697 | INSN_COND_BRANCH_DELAY
2698 | INSN_COND_BRANCH_LIKELY
)));
2702 mips_step_skips_delay (pc
)
2705 char buf
[MIPS_INSTLEN
];
2707 /* There is no branch delay slot on MIPS16. */
2708 if (pc_is_mips16 (pc
))
2711 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2712 /* If error reading memory, guess that it is not a delayed branch. */
2714 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2718 /* Skip the PC past function prologue instructions (32-bit version).
2719 This is a helper function for mips_skip_prologue. */
2722 mips32_skip_prologue (pc
, lenient
)
2723 CORE_ADDR pc
; /* starting PC to search from */
2728 int seen_sp_adjust
= 0;
2729 int load_immediate_bytes
= 0;
2731 /* Skip the typical prologue instructions. These are the stack adjustment
2732 instruction and the instructions that save registers on the stack
2733 or in the gcc frame. */
2734 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2736 unsigned long high_word
;
2738 inst
= mips_fetch_instruction (pc
);
2739 high_word
= (inst
>> 16) & 0xffff;
2742 if (lenient
&& is_delayed (inst
))
2746 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2747 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2749 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2750 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2752 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2753 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2754 && (inst
& 0x001F0000)) /* reg != $zero */
2757 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2759 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2761 continue; /* reg != $zero */
2763 /* move $s8,$sp. With different versions of gas this will be either
2764 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2765 Accept any one of these. */
2766 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2769 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2771 else if (high_word
== 0x3c1c) /* lui $gp,n */
2773 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2775 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2776 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2778 /* The following instructions load $at or $t0 with an immediate
2779 value in preparation for a stack adjustment via
2780 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2781 a local variable, so we accept them only before a stack adjustment
2782 instruction was seen. */
2783 else if (!seen_sp_adjust
)
2785 if (high_word
== 0x3c01 || /* lui $at,n */
2786 high_word
== 0x3c08) /* lui $t0,n */
2788 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2791 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2792 high_word
== 0x3508 || /* ori $t0,$t0,n */
2793 high_word
== 0x3401 || /* ori $at,$zero,n */
2794 high_word
== 0x3408) /* ori $t0,$zero,n */
2796 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2806 /* In a frameless function, we might have incorrectly
2807 skipped some load immediate instructions. Undo the skipping
2808 if the load immediate was not followed by a stack adjustment. */
2809 if (load_immediate_bytes
&& !seen_sp_adjust
)
2810 pc
-= load_immediate_bytes
;
2814 /* Skip the PC past function prologue instructions (16-bit version).
2815 This is a helper function for mips_skip_prologue. */
2818 mips16_skip_prologue (pc
, lenient
)
2819 CORE_ADDR pc
; /* starting PC to search from */
2823 int extend_bytes
= 0;
2824 int prev_extend_bytes
;
2826 /* Table of instructions likely to be found in a function prologue. */
2829 unsigned short inst
;
2830 unsigned short mask
;
2837 , /* addiu $sp,offset */
2841 , /* daddiu $sp,offset */
2845 , /* sw reg,n($sp) */
2849 , /* sd reg,n($sp) */
2853 , /* sw $ra,n($sp) */
2857 , /* sd $ra,n($sp) */
2865 , /* sw $a0-$a3,n($s1) */
2869 , /* move reg,$a0-$a3 */
2873 , /* entry pseudo-op */
2877 , /* addiu $s1,$sp,n */
2880 } /* end of table marker */
2883 /* Skip the typical prologue instructions. These are the stack adjustment
2884 instruction and the instructions that save registers on the stack
2885 or in the gcc frame. */
2886 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2888 unsigned short inst
;
2891 inst
= mips_fetch_instruction (pc
);
2893 /* Normally we ignore an extend instruction. However, if it is
2894 not followed by a valid prologue instruction, we must adjust
2895 the pc back over the extend so that it won't be considered
2896 part of the prologue. */
2897 if ((inst
& 0xf800) == 0xf000) /* extend */
2899 extend_bytes
= MIPS16_INSTLEN
;
2902 prev_extend_bytes
= extend_bytes
;
2905 /* Check for other valid prologue instructions besides extend. */
2906 for (i
= 0; table
[i
].mask
!= 0; i
++)
2907 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2909 if (table
[i
].mask
!= 0) /* it was in table? */
2910 continue; /* ignore it */
2914 /* Return the current pc, adjusted backwards by 2 if
2915 the previous instruction was an extend. */
2916 return pc
- prev_extend_bytes
;
2922 /* To skip prologues, I use this predicate. Returns either PC itself
2923 if the code at PC does not look like a function prologue; otherwise
2924 returns an address that (if we're lucky) follows the prologue. If
2925 LENIENT, then we must skip everything which is involved in setting
2926 up the frame (it's OK to skip more, just so long as we don't skip
2927 anything which might clobber the registers which are being saved.
2928 We must skip more in the case where part of the prologue is in the
2929 delay slot of a non-prologue instruction). */
2932 mips_skip_prologue (pc
, lenient
)
2936 /* See if we can determine the end of the prologue via the symbol table.
2937 If so, then return either PC, or the PC after the prologue, whichever
2940 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2942 if (post_prologue_pc
!= 0)
2943 return max (pc
, post_prologue_pc
);
2945 /* Can't determine prologue from the symbol table, need to examine
2948 if (pc_is_mips16 (pc
))
2949 return mips16_skip_prologue (pc
, lenient
);
2951 return mips32_skip_prologue (pc
, lenient
);
2955 /* The lenient prologue stuff should be superseded by the code in
2956 init_extra_frame_info which looks to see whether the stores mentioned
2957 in the proc_desc have actually taken place. */
2959 /* Is address PC in the prologue (loosely defined) for function at
2963 mips_in_lenient_prologue (startaddr
, pc
)
2964 CORE_ADDR startaddr
;
2967 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2968 return pc
>= startaddr
&& pc
< end_prologue
;
2972 /* Determine how a return value is stored within the MIPS register
2973 file, given the return type `valtype'. */
2975 struct return_value_word
2983 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2986 return_value_location (valtype
, hi
, lo
)
2987 struct type
*valtype
;
2988 struct return_value_word
*hi
;
2989 struct return_value_word
*lo
;
2991 int len
= TYPE_LENGTH (valtype
);
2993 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2994 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2995 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2997 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2999 /* We need to break a 64bit float in two 32 bit halves and
3000 spread them across a floating-point register pair. */
3001 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3002 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3003 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3004 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3006 hi
->reg_offset
= lo
->reg_offset
;
3007 lo
->reg
= FP0_REGNUM
+ 0;
3008 hi
->reg
= FP0_REGNUM
+ 1;
3014 /* The floating point value fits in a single floating-point
3016 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3017 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3020 lo
->reg
= FP0_REGNUM
;
3031 /* Locate a result possibly spread across two registers. */
3033 lo
->reg
= regnum
+ 0;
3034 hi
->reg
= regnum
+ 1;
3035 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3036 && len
< MIPS_SAVED_REGSIZE
)
3038 /* "un-left-justify" the value in the low register */
3039 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3044 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3045 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3046 && len
< MIPS_SAVED_REGSIZE
* 2
3047 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3048 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3050 /* "un-left-justify" the value spread across two registers. */
3051 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3052 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3054 hi
->len
= len
- lo
->len
;
3058 /* Only perform a partial copy of the second register. */
3061 if (len
> MIPS_SAVED_REGSIZE
)
3063 lo
->len
= MIPS_SAVED_REGSIZE
;
3064 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3072 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3073 && REGISTER_RAW_SIZE (regnum
) == 8
3074 && MIPS_SAVED_REGSIZE
== 4)
3076 /* Account for the fact that only the least-signficant part
3077 of the register is being used */
3078 lo
->reg_offset
+= 4;
3079 hi
->reg_offset
+= 4;
3082 hi
->buf_offset
= lo
->len
;
3086 /* Given a return value in `regbuf' with a type `valtype', extract and
3087 copy its value into `valbuf'. */
3090 mips_extract_return_value (valtype
, regbuf
, valbuf
)
3091 struct type
*valtype
;
3092 char regbuf
[REGISTER_BYTES
];
3095 struct return_value_word lo
;
3096 struct return_value_word hi
;
3097 return_value_location (valtype
, &lo
, &hi
);
3099 memcpy (valbuf
+ lo
.buf_offset
,
3100 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3104 memcpy (valbuf
+ hi
.buf_offset
,
3105 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3111 int len
= TYPE_LENGTH (valtype
);
3114 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3115 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3116 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3117 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
3118 regnum
= FP0_REGNUM
;
3120 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3121 { /* "un-left-justify" the value from the register */
3122 if (len
< REGISTER_RAW_SIZE (regnum
))
3123 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3124 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3125 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3126 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3127 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3128 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3130 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3131 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3135 /* Given a return value in `valbuf' with a type `valtype', write it's
3136 value into the appropriate register. */
3139 mips_store_return_value (valtype
, valbuf
)
3140 struct type
*valtype
;
3143 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3144 struct return_value_word lo
;
3145 struct return_value_word hi
;
3146 return_value_location (valtype
, &lo
, &hi
);
3148 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3149 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3150 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3152 REGISTER_RAW_SIZE (lo
.reg
));
3156 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3157 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3158 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3160 REGISTER_RAW_SIZE (hi
.reg
));
3166 int len
= TYPE_LENGTH (valtype
);
3167 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3170 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3171 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3172 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3173 && len
<= MIPS_REGSIZE
)))
3174 regnum
= FP0_REGNUM
;
3176 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3177 { /* "left-justify" the value in the register */
3178 if (len
< REGISTER_RAW_SIZE (regnum
))
3179 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3180 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3181 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3182 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3183 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3184 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3186 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3187 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3188 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3189 len
> REGISTER_RAW_SIZE (regnum
) ?
3190 len
: REGISTER_RAW_SIZE (regnum
));
3194 /* Exported procedure: Is PC in the signal trampoline code */
3197 in_sigtramp (pc
, ignore
)
3199 char *ignore
; /* function name */
3201 if (sigtramp_address
== 0)
3203 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3206 /* Root of all "set mips "/"show mips " commands. This will eventually be
3207 used for all MIPS-specific commands. */
3209 static void show_mips_command
PARAMS ((char *, int));
3211 show_mips_command (args
, from_tty
)
3215 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3218 static void set_mips_command
PARAMS ((char *, int));
3220 set_mips_command (args
, from_tty
)
3224 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3225 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3228 /* Commands to show/set the MIPS FPU type. */
3230 static void show_mipsfpu_command
PARAMS ((char *, int));
3232 show_mipsfpu_command (args
, from_tty
)
3238 switch (MIPS_FPU_TYPE
)
3240 case MIPS_FPU_SINGLE
:
3241 fpu
= "single-precision";
3243 case MIPS_FPU_DOUBLE
:
3244 fpu
= "double-precision";
3247 fpu
= "absent (none)";
3250 if (mips_fpu_type_auto
)
3251 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3254 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3259 static void set_mipsfpu_command
PARAMS ((char *, int));
3261 set_mipsfpu_command (args
, from_tty
)
3265 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3266 show_mipsfpu_command (args
, from_tty
);
3269 static void set_mipsfpu_single_command
PARAMS ((char *, int));
3271 set_mipsfpu_single_command (args
, from_tty
)
3275 mips_fpu_type
= MIPS_FPU_SINGLE
;
3276 mips_fpu_type_auto
= 0;
3279 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3283 static void set_mipsfpu_double_command
PARAMS ((char *, int));
3285 set_mipsfpu_double_command (args
, from_tty
)
3289 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3290 mips_fpu_type_auto
= 0;
3293 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3297 static void set_mipsfpu_none_command
PARAMS ((char *, int));
3299 set_mipsfpu_none_command (args
, from_tty
)
3303 mips_fpu_type
= MIPS_FPU_NONE
;
3304 mips_fpu_type_auto
= 0;
3307 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3311 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
3313 set_mipsfpu_auto_command (args
, from_tty
)
3317 mips_fpu_type_auto
= 1;
3320 /* Command to set the processor type. */
3323 mips_set_processor_type_command (args
, from_tty
)
3329 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3331 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3332 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3333 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3335 /* Restore the value. */
3336 tmp_mips_processor_type
= strsave (mips_processor_type
);
3341 if (!mips_set_processor_type (tmp_mips_processor_type
))
3343 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3344 /* Restore its value. */
3345 tmp_mips_processor_type
= strsave (mips_processor_type
);
3350 mips_show_processor_type_command (args
, from_tty
)
3356 /* Modify the actual processor type. */
3359 mips_set_processor_type (str
)
3367 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3369 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3371 mips_processor_type
= str
;
3372 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3374 /* FIXME tweak fpu flag too */
3381 /* Attempt to identify the particular processor model by reading the
3385 mips_read_processor_type ()
3389 prid
= read_register (PRID_REGNUM
);
3391 if ((prid
& ~0xf) == 0x700)
3392 return savestring ("r3041", strlen ("r3041"));
3397 /* Just like reinit_frame_cache, but with the right arguments to be
3398 callable as an sfunc. */
3401 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3404 struct cmd_list_element
*c
;
3406 reinit_frame_cache ();
3410 gdb_print_insn_mips (memaddr
, info
)
3412 disassemble_info
*info
;
3414 mips_extra_func_info_t proc_desc
;
3416 /* Search for the function containing this address. Set the low bit
3417 of the address when searching, in case we were given an even address
3418 that is the start of a 16-bit function. If we didn't do this,
3419 the search would fail because the symbol table says the function
3420 starts at an odd address, i.e. 1 byte past the given address. */
3421 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3422 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3424 /* Make an attempt to determine if this is a 16-bit function. If
3425 the procedure descriptor exists and the address therein is odd,
3426 it's definitely a 16-bit function. Otherwise, we have to just
3427 guess that if the address passed in is odd, it's 16-bits. */
3429 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3431 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3433 /* Round down the instruction address to the appropriate boundary. */
3434 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3436 /* Call the appropriate disassembler based on the target endian-ness. */
3437 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3438 return print_insn_big_mips (memaddr
, info
);
3440 return print_insn_little_mips (memaddr
, info
);
3443 /* Old-style breakpoint macros.
3444 The IDT board uses an unusual breakpoint value, and sometimes gets
3445 confused when it sees the usual MIPS breakpoint instruction. */
3447 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3448 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3449 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3450 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3451 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3452 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3453 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3454 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3456 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3457 counter value to determine whether a 16- or 32-bit breakpoint should be
3458 used. It returns a pointer to a string of bytes that encode a breakpoint
3459 instruction, stores the length of the string to *lenptr, and adjusts pc
3460 (if necessary) to point to the actual memory location where the
3461 breakpoint should be inserted. */
3464 mips_breakpoint_from_pc (pcptr
, lenptr
)
3468 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3470 if (pc_is_mips16 (*pcptr
))
3472 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3473 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3474 *lenptr
= sizeof (mips16_big_breakpoint
);
3475 return mips16_big_breakpoint
;
3479 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3480 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3481 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3483 *lenptr
= sizeof (big_breakpoint
);
3485 if (strcmp (target_shortname
, "mips") == 0)
3486 return idt_big_breakpoint
;
3487 else if (strcmp (target_shortname
, "ddb") == 0
3488 || strcmp (target_shortname
, "pmon") == 0
3489 || strcmp (target_shortname
, "lsi") == 0)
3490 return pmon_big_breakpoint
;
3492 return big_breakpoint
;
3497 if (pc_is_mips16 (*pcptr
))
3499 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3500 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3501 *lenptr
= sizeof (mips16_little_breakpoint
);
3502 return mips16_little_breakpoint
;
3506 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3507 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3508 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3510 *lenptr
= sizeof (little_breakpoint
);
3512 if (strcmp (target_shortname
, "mips") == 0)
3513 return idt_little_breakpoint
;
3514 else if (strcmp (target_shortname
, "ddb") == 0
3515 || strcmp (target_shortname
, "pmon") == 0
3516 || strcmp (target_shortname
, "lsi") == 0)
3517 return pmon_little_breakpoint
;
3519 return little_breakpoint
;
3524 /* If PC is in a mips16 call or return stub, return the address of the target
3525 PC, which is either the callee or the caller. There are several
3526 cases which must be handled:
3528 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3529 target PC is in $31 ($ra).
3530 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3531 and the target PC is in $2.
3532 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3533 before the jal instruction, this is effectively a call stub
3534 and the the target PC is in $2. Otherwise this is effectively
3535 a return stub and the target PC is in $18.
3537 See the source code for the stubs in gcc/config/mips/mips16.S for
3540 This function implements the SKIP_TRAMPOLINE_CODE macro.
3548 CORE_ADDR start_addr
;
3550 /* Find the starting address and name of the function containing the PC. */
3551 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3554 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3555 target PC is in $31 ($ra). */
3556 if (strcmp (name
, "__mips16_ret_sf") == 0
3557 || strcmp (name
, "__mips16_ret_df") == 0)
3558 return read_register (RA_REGNUM
);
3560 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3562 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3563 and the target PC is in $2. */
3564 if (name
[19] >= '0' && name
[19] <= '9')
3565 return read_register (2);
3567 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3568 before the jal instruction, this is effectively a call stub
3569 and the the target PC is in $2. Otherwise this is effectively
3570 a return stub and the target PC is in $18. */
3571 else if (name
[19] == 's' || name
[19] == 'd')
3573 if (pc
== start_addr
)
3575 /* Check if the target of the stub is a compiler-generated
3576 stub. Such a stub for a function bar might have a name
3577 like __fn_stub_bar, and might look like this:
3582 la $1,bar (becomes a lui/addiu pair)
3584 So scan down to the lui/addi and extract the target
3585 address from those two instructions. */
3587 CORE_ADDR target_pc
= read_register (2);
3591 /* See if the name of the target function is __fn_stub_*. */
3592 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3594 if (strncmp (name
, "__fn_stub_", 10) != 0
3595 && strcmp (name
, "etext") != 0
3596 && strcmp (name
, "_etext") != 0)
3599 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3600 The limit on the search is arbitrarily set to 20
3601 instructions. FIXME. */
3602 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3604 inst
= mips_fetch_instruction (target_pc
);
3605 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3606 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3607 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3608 return pc
| (inst
& 0xffff); /* low word */
3611 /* Couldn't find the lui/addui pair, so return stub address. */
3615 /* This is the 'return' part of a call stub. The return
3616 address is in $r18. */
3617 return read_register (18);
3620 return 0; /* not a stub */
3624 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3625 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3628 mips_in_call_stub (pc
, name
)
3632 CORE_ADDR start_addr
;
3634 /* Find the starting address of the function containing the PC. If the
3635 caller didn't give us a name, look it up at the same time. */
3636 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3639 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3641 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3642 if (name
[19] >= '0' && name
[19] <= '9')
3644 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3645 before the jal instruction, this is effectively a call stub. */
3646 else if (name
[19] == 's' || name
[19] == 'd')
3647 return pc
== start_addr
;
3650 return 0; /* not a stub */
3654 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3655 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3658 mips_in_return_stub (pc
, name
)
3662 CORE_ADDR start_addr
;
3664 /* Find the starting address of the function containing the PC. */
3665 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3668 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3669 if (strcmp (name
, "__mips16_ret_sf") == 0
3670 || strcmp (name
, "__mips16_ret_df") == 0)
3673 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3674 i.e. after the jal instruction, this is effectively a return stub. */
3675 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3676 && (name
[19] == 's' || name
[19] == 'd')
3677 && pc
!= start_addr
)
3680 return 0; /* not a stub */
3684 /* Return non-zero if the PC is in a library helper function that should
3685 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3688 mips_ignore_helper (pc
)
3693 /* Find the starting address and name of the function containing the PC. */
3694 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3697 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3698 that we want to ignore. */
3699 return (strcmp (name
, "__mips16_ret_sf") == 0
3700 || strcmp (name
, "__mips16_ret_df") == 0);
3704 /* Return a location where we can set a breakpoint that will be hit
3705 when an inferior function call returns. This is normally the
3706 program's entry point. Executables that don't have an entry
3707 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3708 whose address is the location where the breakpoint should be placed. */
3711 mips_call_dummy_address ()
3713 struct minimal_symbol
*sym
;
3715 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3717 return SYMBOL_VALUE_ADDRESS (sym
);
3719 return entry_point_address ();
3723 /* If the current gcc for for this target does not produce correct debugging
3724 information for float parameters, both prototyped and unprototyped, then
3725 define this macro. This forces gdb to always assume that floats are
3726 passed as doubles and then converted in the callee.
3728 For the mips chip, it appears that the debug info marks the parameters as
3729 floats regardless of whether the function is prototyped, but the actual
3730 values are passed as doubles for the non-prototyped case and floats for
3731 the prototyped case. Thus we choose to make the non-prototyped case work
3732 for C and break the prototyped case, since the non-prototyped case is
3733 probably much more common. (FIXME). */
3736 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3738 return current_language
->la_language
== language_c
;
3742 static gdbarch_init_ftype mips_gdbarch_init
;
3743 static struct gdbarch
*
3744 mips_gdbarch_init (info
, arches
)
3745 struct gdbarch_info info
;
3746 struct gdbarch_list
*arches
;
3748 static LONGEST mips_call_dummy_words
[] =
3750 struct gdbarch
*gdbarch
;
3751 struct gdbarch_tdep
*tdep
;
3754 int ef_mips_bitptrs
;
3757 /* Extract the elf_flags if available */
3758 if (info
.abfd
!= NULL
3759 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3760 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3764 /* try to find a pre-existing architecture */
3765 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3767 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3769 /* MIPS needs to be pedantic about which ABI the object is
3771 if (gdbarch_tdep (current_gdbarch
)->elf_flags
!= elf_flags
)
3773 return arches
->gdbarch
;
3776 /* Need a new architecture. Fill in a target specific vector. */
3777 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3778 gdbarch
= gdbarch_alloc (&info
, tdep
);
3779 tdep
->elf_flags
= elf_flags
;
3781 /* Initially set everything according to the ABI. */
3782 set_gdbarch_short_bit (gdbarch
, 16);
3783 set_gdbarch_int_bit (gdbarch
, 32);
3784 set_gdbarch_float_bit (gdbarch
, 32);
3785 set_gdbarch_double_bit (gdbarch
, 64);
3786 set_gdbarch_long_double_bit (gdbarch
, 64);
3787 switch ((elf_flags
& EF_MIPS_ABI
))
3789 case E_MIPS_ABI_O32
:
3790 ef_mips_abi
= "o32";
3791 tdep
->mips_eabi
= 0;
3792 tdep
->mips_default_saved_regsize
= 4;
3793 tdep
->mips_fp_register_double
= 0;
3794 set_gdbarch_long_bit (gdbarch
, 32);
3795 set_gdbarch_ptr_bit (gdbarch
, 32);
3796 set_gdbarch_long_long_bit (gdbarch
, 64);
3798 case E_MIPS_ABI_O64
:
3799 ef_mips_abi
= "o64";
3800 tdep
->mips_eabi
= 0;
3801 tdep
->mips_default_saved_regsize
= 8;
3802 tdep
->mips_fp_register_double
= 1;
3803 set_gdbarch_long_bit (gdbarch
, 32);
3804 set_gdbarch_ptr_bit (gdbarch
, 32);
3805 set_gdbarch_long_long_bit (gdbarch
, 64);
3807 case E_MIPS_ABI_EABI32
:
3808 ef_mips_abi
= "eabi32";
3809 tdep
->mips_eabi
= 1;
3810 tdep
->mips_default_saved_regsize
= 4;
3811 tdep
->mips_fp_register_double
= 0;
3812 set_gdbarch_long_bit (gdbarch
, 32);
3813 set_gdbarch_ptr_bit (gdbarch
, 32);
3814 set_gdbarch_long_long_bit (gdbarch
, 64);
3816 case E_MIPS_ABI_EABI64
:
3817 ef_mips_abi
= "eabi64";
3818 tdep
->mips_eabi
= 1;
3819 tdep
->mips_default_saved_regsize
= 8;
3820 tdep
->mips_fp_register_double
= 1;
3821 set_gdbarch_long_bit (gdbarch
, 64);
3822 set_gdbarch_ptr_bit (gdbarch
, 64);
3823 set_gdbarch_long_long_bit (gdbarch
, 64);
3826 ef_mips_abi
= "default";
3827 tdep
->mips_eabi
= 0;
3828 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
3829 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
3830 set_gdbarch_long_bit (gdbarch
, 32);
3831 set_gdbarch_ptr_bit (gdbarch
, 32);
3832 set_gdbarch_long_long_bit (gdbarch
, 64);
3835 tdep
->mips_default_stack_argsize
= tdep
->mips_default_saved_regsize
;
3837 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
3838 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
3841 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
3842 flag in object files because to do so would make it impossible to
3843 link with libraries compiled without "-gp32". This is
3844 unnecessarily restrictive.
3846 We could solve this problem by adding "-gp32" multilibs to gcc,
3847 but to set this flag before gcc is built with such multilibs will
3848 break too many systems.''
3850 But even more unhelpfully, the default linker output target for
3851 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
3852 for 64-bit programs - you need to change the ABI to change this,
3853 and not all gcc targets support that currently. Therefore using
3854 this flag to detect 32-bit mode would do the wrong thing given
3855 the current gcc - it would make GDB treat these 64-bit programs
3856 as 32-bit programs by default. */
3858 /* determine the ISA */
3859 switch (elf_flags
& EF_MIPS_ARCH
)
3878 /* determine the size of a pointer */
3879 if ((elf_flags
& EF_MIPS_32BITPTRS
))
3881 ef_mips_bitptrs
= 32;
3883 else if ((elf_flags
& EF_MIPS_64BITPTRS
))
3885 ef_mips_bitptrs
= 64;
3889 ef_mips_bitptrs
= 0;
3893 /* Select either of the two alternative ABI's */
3894 if (tdep
->mips_eabi
)
3896 /* EABI uses R4 through R11 for args */
3897 tdep
->mips_last_arg_regnum
= 11;
3898 /* EABI uses F12 through F19 for args */
3899 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3900 /* EABI does not reserve home space for registers */
3901 tdep
->mips_regs_have_home_p
= 0;
3905 /* old ABI uses R4 through R7 for args */
3906 tdep
->mips_last_arg_regnum
= 7;
3907 /* old ABI uses F12 through F15 for args */
3908 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
3909 /* Old ABI reserves home space for registers */
3910 tdep
->mips_regs_have_home_p
= 1;
3913 /* enable/disable the MIPS FPU */
3914 if (!mips_fpu_type_auto
)
3915 tdep
->mips_fpu_type
= mips_fpu_type
;
3916 else if (info
.bfd_arch_info
!= NULL
3917 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3918 switch (info
.bfd_arch_info
->mach
)
3920 case bfd_mach_mips4100
:
3921 case bfd_mach_mips4111
:
3922 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
3925 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3929 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3931 /* MIPS version of register names. NOTE: At present the MIPS
3932 register name management is part way between the old -
3933 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
3934 Further work on it is required. */
3935 set_gdbarch_register_name (gdbarch
, mips_register_name
);
3936 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
3937 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3938 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3939 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
3940 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3941 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3943 /* Initialize a frame */
3944 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
3946 /* MIPS version of CALL_DUMMY */
3948 set_gdbarch_call_dummy_p (gdbarch
, 1);
3949 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
3950 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
3951 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3952 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
3953 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3954 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
3955 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3956 set_gdbarch_call_dummy_length (gdbarch
, 0);
3957 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3958 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
3959 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
3960 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
3961 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
3962 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
3963 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
3965 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3966 set_gdbarch_get_saved_register (gdbarch
, default_get_saved_register
);
3970 fprintf_unfiltered (gdb_stderr
,
3971 "mips_gdbarch_init: (info)elf_flags = 0x%x\n",
3973 fprintf_unfiltered (gdb_stderr
,
3974 "mips_gdbarch_init: (info)ef_mips_abi = %s\n",
3976 fprintf_unfiltered (gdb_stderr
,
3977 "mips_gdbarch_init: (info)ef_mips_arch = %d\n",
3979 fprintf_unfiltered (gdb_stderr
,
3980 "mips_gdbarch_init: (info)ef_mips_bitptrs = %d\n",
3982 fprintf_unfiltered (gdb_stderr
,
3983 "mips_gdbarch_init: MIPS_EABI = %d\n",
3985 fprintf_unfiltered (gdb_stderr
,
3986 "mips_gdbarch_init: MIPS_LAST_ARG_REGNUM = %d\n",
3987 tdep
->mips_last_arg_regnum
);
3988 fprintf_unfiltered (gdb_stderr
,
3989 "mips_gdbarch_init: MIPS_LAST_FP_ARG_REGNUM = %d (%d)\n",
3990 tdep
->mips_last_fp_arg_regnum
,
3991 tdep
->mips_last_fp_arg_regnum
- FP0_REGNUM
);
3992 fprintf_unfiltered (gdb_stderr
,
3993 "mips_gdbarch_init: tdep->mips_fpu_type = %d (%s)\n",
3994 tdep
->mips_fpu_type
,
3995 (tdep
->mips_fpu_type
== MIPS_FPU_NONE
? "none"
3996 : tdep
->mips_fpu_type
== MIPS_FPU_SINGLE
? "single"
3997 : tdep
->mips_fpu_type
== MIPS_FPU_DOUBLE
? "double"
3999 fprintf_unfiltered (gdb_stderr
,
4000 "mips_gdbarch_init: tdep->mips_default_saved_regsize = %d\n",
4001 tdep
->mips_default_saved_regsize
);
4002 fprintf_unfiltered (gdb_stderr
,
4003 "mips_gdbarch_init: tdep->mips_fp_register_double = %d (%s)\n",
4004 tdep
->mips_fp_register_double
,
4005 (tdep
->mips_fp_register_double
? "true" : "false"));
4013 _initialize_mips_tdep ()
4015 static struct cmd_list_element
*mipsfpulist
= NULL
;
4016 struct cmd_list_element
*c
;
4019 register_gdbarch_init (bfd_arch_mips
, mips_gdbarch_init
);
4020 if (!tm_print_insn
) /* Someone may have already set it */
4021 tm_print_insn
= gdb_print_insn_mips
;
4023 /* Add root prefix command for all "set mips"/"show mips" commands */
4024 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4025 "Various MIPS specific commands.",
4026 &setmipscmdlist
, "set mips ", 0, &setlist
);
4028 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4029 "Various MIPS specific commands.",
4030 &showmipscmdlist
, "show mips ", 0, &showlist
);
4032 /* Allow the user to override the saved register size. */
4033 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4036 (char *) &mips_saved_regsize_string
, "\
4037 Set size of general purpose registers saved on the stack.\n\
4038 This option can be set to one of:\n\
4039 32 - Force GDB to treat saved GP registers as 32-bit\n\
4040 64 - Force GDB to treat saved GP registers as 64-bit\n\
4041 auto - Allow GDB to use the target's default setting or autodetect the\n\
4042 saved GP register size from information contained in the executable.\n\
4047 /* Allow the user to override the argument stack size. */
4048 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4051 (char *) &mips_stack_argsize_string
, "\
4052 Set the amount of stack space reserved for each argument.\n\
4053 This option can be set to one of:\n\
4054 32 - Force GDB to allocate 32-bit chunks per argument\n\
4055 64 - Force GDB to allocate 64-bit chunks per argument\n\
4056 auto - Allow GDB to determine the correct setting from the current\n\
4057 target and executable (default)",
4061 /* Let the user turn off floating point and set the fence post for
4062 heuristic_proc_start. */
4064 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4065 "Set use of MIPS floating-point coprocessor.",
4066 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4067 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4068 "Select single-precision MIPS floating-point coprocessor.",
4070 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4071 "Select double-precision MIPS floating-point coprocessor .",
4073 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4074 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4075 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4076 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4077 "Select no MIPS floating-point coprocessor.",
4079 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4080 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4081 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4082 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4083 "Select MIPS floating-point coprocessor automatically.",
4085 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4086 "Show current use of MIPS floating-point coprocessor target.",
4090 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4091 (char *) &tmp_mips_processor_type
,
4092 "Set the type of MIPS processor in use.\n\
4093 Set this to be able to access processor-type-specific registers.\n\
4096 c
->function
.cfunc
= mips_set_processor_type_command
;
4097 c
= add_show_from_set (c
, &showlist
);
4098 c
->function
.cfunc
= mips_show_processor_type_command
;
4100 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
4101 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
4104 /* We really would like to have both "0" and "unlimited" work, but
4105 command.c doesn't deal with that. So make it a var_zinteger
4106 because the user can always use "999999" or some such for unlimited. */
4107 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4108 (char *) &heuristic_fence_post
,
4110 Set the distance searched for the start of a function.\n\
4111 If you are debugging a stripped executable, GDB needs to search through the\n\
4112 program for the start of a function. This command sets the distance of the\n\
4113 search. The only need to set it is when debugging a stripped executable.",
4115 /* We need to throw away the frame cache when we set this, since it
4116 might change our ability to get backtraces. */
4117 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4118 add_show_from_set (c
, &showlist
);
4120 /* Allow the user to control whether the upper bits of 64-bit
4121 addresses should be zeroed. */
4123 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
4124 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4125 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
4126 Without an argument, zeroing of upper address bits is enabled.", &setlist
),
4129 /* Allow the user to control the size of 32 bit registers within the
4130 raw remote packet. */
4131 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4134 (char *)&mips64_transfers_32bit_regs_p
, "\
4135 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4136 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4137 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4138 64 bits for others. Use \"off\" to disable compatibility mode",