1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
54 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
55 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
57 /* A useful bit in the CP0 status register (PS_REGNUM). */
58 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
59 #define ST0_FR (1 << 26)
61 /* The sizes of floating point registers. */
65 MIPS_FPU_SINGLE_REGSIZE
= 4,
66 MIPS_FPU_DOUBLE_REGSIZE
= 8
70 static const char *mips_abi_string
;
72 static const char *mips_abi_strings
[] = {
83 struct frame_extra_info
85 mips_extra_func_info_t proc_desc
;
89 /* Various MIPS ISA options (related to stack analysis) can be
90 overridden dynamically. Establish an enum/array for managing
93 static const char size_auto
[] = "auto";
94 static const char size_32
[] = "32";
95 static const char size_64
[] = "64";
97 static const char *size_enums
[] = {
104 /* Some MIPS boards don't support floating point while others only
105 support single-precision floating-point operations. See also
106 FP_REGISTER_DOUBLE. */
110 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
111 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
112 MIPS_FPU_NONE
/* No floating point. */
115 #ifndef MIPS_DEFAULT_FPU_TYPE
116 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
118 static int mips_fpu_type_auto
= 1;
119 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
121 static int mips_debug
= 0;
123 /* MIPS specific per-architecture information */
126 /* from the elf header */
130 enum mips_abi mips_abi
;
131 enum mips_abi found_abi
;
132 enum mips_fpu_type mips_fpu_type
;
133 int mips_last_arg_regnum
;
134 int mips_last_fp_arg_regnum
;
135 int mips_default_saved_regsize
;
136 int mips_fp_register_double
;
137 int mips_default_stack_argsize
;
138 int default_mask_address_p
;
139 /* Is the target using 64-bit raw integer registers but only
140 storing a left-aligned 32-bit value in each? */
141 int mips64_transfers_32bit_regs_p
;
142 /* Indexes for various registers. IRIX and embedded have
143 different values. This contains the "public" fields. Don't
144 add any that do not need to be public. */
145 const struct mips_regnum
*regnum
;
146 /* Register names table for the current register set. */
147 const char **mips_processor_reg_names
;
150 const struct mips_regnum
*
151 mips_regnum (struct gdbarch
*gdbarch
)
153 return gdbarch_tdep (gdbarch
)->regnum
;
157 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
159 return mips_regnum (gdbarch
)->fp0
+ 12;
162 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
163 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
165 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
167 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
169 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
171 /* Return the currently configured (or set) saved register size. */
173 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
175 static const char *mips_saved_regsize_string
= size_auto
;
177 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
179 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
180 functions to test, set, or clear bit 0 of addresses. */
183 is_mips16_addr (CORE_ADDR addr
)
189 make_mips16_addr (CORE_ADDR addr
)
195 unmake_mips16_addr (CORE_ADDR addr
)
197 return ((addr
) & ~1);
200 /* Return the contents of register REGNUM as a signed integer. */
203 read_signed_register (int regnum
)
205 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
206 deprecated_read_register_gen (regnum
, buf
);
207 return (extract_signed_integer (buf
, register_size (current_gdbarch
, regnum
)));
211 read_signed_register_pid (int regnum
, ptid_t ptid
)
216 if (ptid_equal (ptid
, inferior_ptid
))
217 return read_signed_register (regnum
);
219 save_ptid
= inferior_ptid
;
221 inferior_ptid
= ptid
;
223 retval
= read_signed_register (regnum
);
225 inferior_ptid
= save_ptid
;
230 /* Return the MIPS ABI associated with GDBARCH. */
232 mips_abi (struct gdbarch
*gdbarch
)
234 return gdbarch_tdep (gdbarch
)->mips_abi
;
238 mips_regsize (struct gdbarch
*gdbarch
)
240 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
241 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
245 mips_saved_regsize (void)
247 if (mips_saved_regsize_string
== size_auto
)
248 return MIPS_DEFAULT_SAVED_REGSIZE
;
249 else if (mips_saved_regsize_string
== size_64
)
251 else /* if (mips_saved_regsize_string == size_32) */
255 /* Functions for setting and testing a bit in a minimal symbol that
256 marks it as 16-bit function. The MSB of the minimal symbol's
257 "info" field is used for this purpose.
259 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
260 i.e. refers to a 16-bit function, and sets a "special" bit in a
261 minimal symbol to mark it as a 16-bit function
263 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
266 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
268 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
270 MSYMBOL_INFO (msym
) = (char *)
271 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
272 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
277 msymbol_is_special (struct minimal_symbol
*msym
)
279 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
282 /* XFER a value from the big/little/left end of the register.
283 Depending on the size of the value it might occupy the entire
284 register or just part of it. Make an allowance for this, aligning
285 things accordingly. */
288 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
289 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
292 bfd_byte reg
[MAX_REGISTER_SIZE
];
294 gdb_assert (reg_num
>= NUM_REGS
);
295 /* Need to transfer the left or right part of the register, based on
296 the targets byte order. */
300 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
302 case BFD_ENDIAN_LITTLE
:
305 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
309 internal_error (__FILE__
, __LINE__
, "bad switch");
312 fprintf_unfiltered (gdb_stderr
,
313 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
314 reg_num
, reg_offset
, buf_offset
, length
);
315 if (mips_debug
&& out
!= NULL
)
318 fprintf_unfiltered (gdb_stdlog
, "out ");
319 for (i
= 0; i
< length
; i
++)
320 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
323 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
325 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
326 if (mips_debug
&& in
!= NULL
)
329 fprintf_unfiltered (gdb_stdlog
, "in ");
330 for (i
= 0; i
< length
; i
++)
331 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
334 fprintf_unfiltered (gdb_stdlog
, "\n");
337 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
338 compatiblity mode. A return value of 1 means that we have
339 physical 64-bit registers, but should treat them as 32-bit registers. */
342 mips2_fp_compat (void)
344 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
346 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 4)
350 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
351 in all the places we deal with FP registers. PR gdb/413. */
352 /* Otherwise check the FR bit in the status register - it controls
353 the FP compatiblity mode. If it is clear we are in compatibility
355 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
362 /* Indicate that the ABI makes use of double-precision registers
363 provided by the FPU (rather than combining pairs of registers to
364 form double-precision values). See also MIPS_FPU_TYPE. */
365 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
367 /* The amount of space reserved on the stack for registers. This is
368 different to MIPS_SAVED_REGSIZE as it determines the alignment of
369 data allocated after the registers have run out. */
371 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
373 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
375 static const char *mips_stack_argsize_string
= size_auto
;
378 mips_stack_argsize (void)
380 if (mips_stack_argsize_string
== size_auto
)
381 return MIPS_DEFAULT_STACK_ARGSIZE
;
382 else if (mips_stack_argsize_string
== size_64
)
384 else /* if (mips_stack_argsize_string == size_32) */
388 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
390 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
392 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
393 struct frame_info
*, int);
395 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
397 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
399 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
401 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
402 struct frame_info
*next_frame
,
405 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
406 mips_extra_func_info_t proc_desc
);
408 static struct type
*mips_float_register_type (void);
409 static struct type
*mips_double_register_type (void);
411 /* The list of available "set mips " and "show mips " commands */
413 static struct cmd_list_element
*setmipscmdlist
= NULL
;
414 static struct cmd_list_element
*showmipscmdlist
= NULL
;
416 /* Integer registers 0 thru 31 are handled explicitly by
417 mips_register_name(). Processor specific registers 32 and above
418 are listed in the followign tables. */
420 enum { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
424 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
425 "sr", "lo", "hi", "bad", "cause","pc",
426 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
427 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
428 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
429 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
430 "fsr", "fir", ""/*"fp"*/, "",
431 "", "", "", "", "", "", "", "",
432 "", "", "", "", "", "", "", "",
435 /* Names of IDT R3041 registers. */
437 static const char *mips_r3041_reg_names
[] = {
438 "sr", "lo", "hi", "bad", "cause","pc",
439 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
440 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
441 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
442 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
443 "fsr", "fir", "",/*"fp"*/ "",
444 "", "", "bus", "ccfg", "", "", "", "",
445 "", "", "port", "cmp", "", "", "epc", "prid",
448 /* Names of tx39 registers. */
450 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
451 "sr", "lo", "hi", "bad", "cause","pc",
452 "", "", "", "", "", "", "", "",
453 "", "", "", "", "", "", "", "",
454 "", "", "", "", "", "", "", "",
455 "", "", "", "", "", "", "", "",
457 "", "", "", "", "", "", "", "",
458 "", "", "config", "cache", "debug", "depc", "epc", ""
461 /* Names of IRIX registers. */
462 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
463 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
464 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
465 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
466 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
467 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
471 /* Return the name of the register corresponding to REGNO. */
473 mips_register_name (int regno
)
475 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
476 /* GPR names for all ABIs other than n32/n64. */
477 static char *mips_gpr_names
[] = {
478 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
479 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
480 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
481 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
484 /* GPR names for n32 and n64 ABIs. */
485 static char *mips_n32_n64_gpr_names
[] = {
486 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
487 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
488 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
489 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
492 enum mips_abi abi
= mips_abi (current_gdbarch
);
494 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
495 don't make the raw register names visible. */
496 int rawnum
= regno
% NUM_REGS
;
497 if (regno
< NUM_REGS
)
500 /* The MIPS integer registers are always mapped from 0 to 31. The
501 names of the registers (which reflects the conventions regarding
502 register use) vary depending on the ABI. */
503 if (0 <= rawnum
&& rawnum
< 32)
505 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
506 return mips_n32_n64_gpr_names
[rawnum
];
508 return mips_gpr_names
[rawnum
];
510 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
512 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
513 return tdep
->mips_processor_reg_names
[rawnum
- 32];
516 internal_error (__FILE__
, __LINE__
,
517 "mips_register_name: bad register number %d", rawnum
);
520 /* Return the groups that a MIPS register can be categorised into. */
523 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
524 struct reggroup
*reggroup
)
529 int rawnum
= regnum
% NUM_REGS
;
530 int pseudo
= regnum
/ NUM_REGS
;
531 if (reggroup
== all_reggroup
)
533 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
534 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
535 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
536 (gdbarch), as not all architectures are multi-arch. */
537 raw_p
= rawnum
< NUM_REGS
;
538 if (REGISTER_NAME (regnum
) == NULL
539 || REGISTER_NAME (regnum
)[0] == '\0')
541 if (reggroup
== float_reggroup
)
542 return float_p
&& pseudo
;
543 if (reggroup
== vector_reggroup
)
544 return vector_p
&& pseudo
;
545 if (reggroup
== general_reggroup
)
546 return (!vector_p
&& !float_p
) && pseudo
;
547 /* Save the pseudo registers. Need to make certain that any code
548 extracting register values from a saved register cache also uses
550 if (reggroup
== save_reggroup
)
551 return raw_p
&& pseudo
;
552 /* Restore the same pseudo register. */
553 if (reggroup
== restore_reggroup
)
554 return raw_p
&& pseudo
;
558 /* Map the symbol table registers which live in the range [1 *
559 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
560 registers. Take care of alignment and size problems. */
563 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
564 int cookednum
, void *buf
)
566 int rawnum
= cookednum
% NUM_REGS
;
567 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
568 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
569 return regcache_raw_read (regcache
, rawnum
, buf
);
570 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
572 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
573 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
574 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
576 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
579 internal_error (__FILE__
, __LINE__
, "bad register size");
583 mips_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
584 int cookednum
, const void *buf
)
586 int rawnum
= cookednum
% NUM_REGS
;
587 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
588 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
589 return regcache_raw_write (regcache
, rawnum
, buf
);
590 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
592 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
593 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
594 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
596 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
599 internal_error (__FILE__
, __LINE__
, "bad register size");
602 /* Table to translate MIPS16 register field to actual register number. */
603 static int mips16_to_32_reg
[8] =
604 {16, 17, 2, 3, 4, 5, 6, 7};
606 /* Heuristic_proc_start may hunt through the text section for a long
607 time across a 2400 baud serial line. Allows the user to limit this
610 static unsigned int heuristic_fence_post
= 0;
612 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
613 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
614 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
615 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
616 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
617 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
618 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
619 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
620 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
621 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
622 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
623 this will corrupt pdr.iline. Fortunately we don't use it. */
624 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
625 #define _PROC_MAGIC_ 0x0F0F0F0F
626 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
627 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
629 struct linked_proc_info
631 struct mips_extra_func_info info
;
632 struct linked_proc_info
*next
;
634 *linked_proc_desc_table
= NULL
;
636 /* Number of bytes of storage in the actual machine representation for
637 register N. NOTE: This defines the pseudo register type so need to
638 rebuild the architecture vector. */
640 static int mips64_transfers_32bit_regs_p
= 0;
643 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
644 struct cmd_list_element
*c
)
646 struct gdbarch_info info
;
647 gdbarch_info_init (&info
);
648 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
649 instead of relying on globals. Doing that would let generic code
650 handle the search for this specific architecture. */
651 if (!gdbarch_update_p (info
))
653 mips64_transfers_32bit_regs_p
= 0;
654 error ("32-bit compatibility mode not supported");
658 /* Convert to/from a register and the corresponding memory value. */
661 mips_convert_register_p (int regnum
, struct type
*type
)
663 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
664 && register_size (current_gdbarch
, regnum
) == 4
665 && (regnum
) >= mips_regnum (current_gdbarch
)->fp0
&& (regnum
) < mips_regnum (current_gdbarch
)->fp0
+ 32
666 && TYPE_CODE(type
) == TYPE_CODE_FLT
667 && TYPE_LENGTH(type
) == 8);
671 mips_register_to_value (struct frame_info
*frame
, int regnum
,
672 struct type
*type
, void *to
)
674 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
675 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
679 mips_value_to_register (struct frame_info
*frame
, int regnum
,
680 struct type
*type
, const void *from
)
682 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
683 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
686 /* Return the GDB type object for the "standard" data type of data in
690 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
692 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
693 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
694 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
696 /* The floating-point registers raw, or cooked, always match
697 mips_regsize(), and also map 1:1, byte for byte. */
698 switch (gdbarch_byte_order (gdbarch
))
701 if (mips_regsize (gdbarch
) == 4)
702 return builtin_type_ieee_single_big
;
704 return builtin_type_ieee_double_big
;
705 case BFD_ENDIAN_LITTLE
:
706 if (mips_regsize (gdbarch
) == 4)
707 return builtin_type_ieee_single_little
;
709 return builtin_type_ieee_double_little
;
710 case BFD_ENDIAN_UNKNOWN
:
712 internal_error (__FILE__
, __LINE__
, "bad switch");
715 else if (regnum
>= (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
716 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
717 /* The pseudo/cooked view of the embedded registers is always
718 32-bit. The raw view is handled below. */
719 return builtin_type_int32
;
720 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
721 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
722 /* The target, while using a 64-bit register buffer, is only
723 transfering 32-bits of each integer register. Reflect this in
724 the cooked/pseudo register value. */
725 return builtin_type_int32
;
726 else if (mips_regsize (gdbarch
) == 8)
728 return builtin_type_int64
;
731 return builtin_type_int32
;
734 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
739 return read_signed_register (SP_REGNUM
);
742 /* Should the upper word of 64-bit addresses be zeroed? */
743 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
746 mips_mask_address_p (void)
748 switch (mask_address_var
)
750 case AUTO_BOOLEAN_TRUE
:
752 case AUTO_BOOLEAN_FALSE
:
755 case AUTO_BOOLEAN_AUTO
:
756 return MIPS_DEFAULT_MASK_ADDRESS_P
;
758 internal_error (__FILE__
, __LINE__
,
759 "mips_mask_address_p: bad switch");
765 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
767 switch (mask_address_var
)
769 case AUTO_BOOLEAN_TRUE
:
770 printf_filtered ("The 32 bit mips address mask is enabled\n");
772 case AUTO_BOOLEAN_FALSE
:
773 printf_filtered ("The 32 bit mips address mask is disabled\n");
775 case AUTO_BOOLEAN_AUTO
:
776 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
777 mips_mask_address_p () ? "enabled" : "disabled");
780 internal_error (__FILE__
, __LINE__
,
781 "show_mask_address: bad switch");
786 /* Should call_function allocate stack space for a struct return? */
789 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
791 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
794 /* Should call_function pass struct by reference?
795 For each architecture, structs are passed either by
796 value or by reference, depending on their size. */
799 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
801 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
802 int len
= TYPE_LENGTH (check_typedef (type
));
804 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
805 return (len
> MIPS_SAVED_REGSIZE
);
811 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
813 return 0; /* Assumption: N32/N64 never passes struct by ref. */
817 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
819 return 0; /* Assumption: O32/O64 never passes struct by ref. */
822 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
825 pc_is_mips16 (bfd_vma memaddr
)
827 struct minimal_symbol
*sym
;
829 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
830 if (is_mips16_addr (memaddr
))
833 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
834 the high bit of the info field. Use this to decide if the function is
835 MIPS16 or normal MIPS. */
836 sym
= lookup_minimal_symbol_by_pc (memaddr
);
838 return msymbol_is_special (sym
);
843 /* MIPS believes that the PC has a sign extended value. Perhaphs the
844 all registers should be sign extended for simplicity? */
847 mips_read_pc (ptid_t ptid
)
849 return read_signed_register_pid (PC_REGNUM
, ptid
);
852 /* This returns the PC of the first inst after the prologue. If we can't
853 find the prologue, then return 0. */
856 after_prologue (CORE_ADDR pc
,
857 mips_extra_func_info_t proc_desc
)
859 struct symtab_and_line sal
;
860 CORE_ADDR func_addr
, func_end
;
862 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
863 to read the stack pointer from the current machine state, because
864 the current machine state has nothing to do with the information
865 we need from the proc_desc; and the process may or may not exist
868 proc_desc
= find_proc_desc (pc
, NULL
, 0);
872 /* If function is frameless, then we need to do it the hard way. I
873 strongly suspect that frameless always means prologueless... */
874 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
875 && PROC_FRAME_OFFSET (proc_desc
) == 0)
879 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
880 return 0; /* Unknown */
882 sal
= find_pc_line (func_addr
, 0);
884 if (sal
.end
< func_end
)
887 /* The line after the prologue is after the end of the function. In this
888 case, tell the caller to find the prologue the hard way. */
893 /* Decode a MIPS32 instruction that saves a register in the stack, and
894 set the appropriate bit in the general register mask or float register mask
895 to indicate which register is saved. This is a helper function
896 for mips_find_saved_regs. */
899 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
900 unsigned long *float_mask
)
904 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
905 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
906 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
908 /* It might be possible to use the instruction to
909 find the offset, rather than the code below which
910 is based on things being in a certain order in the
911 frame, but figuring out what the instruction's offset
912 is relative to might be a little tricky. */
913 reg
= (inst
& 0x001f0000) >> 16;
914 *gen_mask
|= (1 << reg
);
916 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
917 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
918 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
921 reg
= ((inst
& 0x001f0000) >> 16);
922 *float_mask
|= (1 << reg
);
926 /* Decode a MIPS16 instruction that saves a register in the stack, and
927 set the appropriate bit in the general register or float register mask
928 to indicate which register is saved. This is a helper function
929 for mips_find_saved_regs. */
932 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
934 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
936 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
937 *gen_mask
|= (1 << reg
);
939 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
941 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
942 *gen_mask
|= (1 << reg
);
944 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
945 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
946 *gen_mask
|= (1 << RA_REGNUM
);
950 /* Fetch and return instruction from the specified location. If the PC
951 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
954 mips_fetch_instruction (CORE_ADDR addr
)
956 char buf
[MIPS_INSTLEN
];
960 if (pc_is_mips16 (addr
))
962 instlen
= MIPS16_INSTLEN
;
963 addr
= unmake_mips16_addr (addr
);
966 instlen
= MIPS_INSTLEN
;
967 status
= read_memory_nobpt (addr
, buf
, instlen
);
969 memory_error (status
, addr
);
970 return extract_unsigned_integer (buf
, instlen
);
974 /* These the fields of 32 bit mips instructions */
975 #define mips32_op(x) (x >> 26)
976 #define itype_op(x) (x >> 26)
977 #define itype_rs(x) ((x >> 21) & 0x1f)
978 #define itype_rt(x) ((x >> 16) & 0x1f)
979 #define itype_immediate(x) (x & 0xffff)
981 #define jtype_op(x) (x >> 26)
982 #define jtype_target(x) (x & 0x03ffffff)
984 #define rtype_op(x) (x >> 26)
985 #define rtype_rs(x) ((x >> 21) & 0x1f)
986 #define rtype_rt(x) ((x >> 16) & 0x1f)
987 #define rtype_rd(x) ((x >> 11) & 0x1f)
988 #define rtype_shamt(x) ((x >> 6) & 0x1f)
989 #define rtype_funct(x) (x & 0x3f)
992 mips32_relative_offset (unsigned long inst
)
995 x
= itype_immediate (inst
);
996 if (x
& 0x8000) /* sign bit set */
998 x
|= 0xffff0000; /* sign extension */
1004 /* Determine whate to set a single step breakpoint while considering
1005 branch prediction */
1007 mips32_next_pc (CORE_ADDR pc
)
1011 inst
= mips_fetch_instruction (pc
);
1012 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1014 if (itype_op (inst
) >> 2 == 5)
1015 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1017 op
= (itype_op (inst
) & 0x03);
1027 goto greater_branch
;
1032 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1033 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1035 int tf
= itype_rt (inst
) & 0x01;
1036 int cnum
= itype_rt (inst
) >> 2;
1037 int fcrcs
= read_signed_register (mips_regnum (current_gdbarch
)->fp_control_status
);
1038 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1040 if (((cond
>> cnum
) & 0x01) == tf
)
1041 pc
+= mips32_relative_offset (inst
) + 4;
1046 pc
+= 4; /* Not a branch, next instruction is easy */
1049 { /* This gets way messy */
1051 /* Further subdivide into SPECIAL, REGIMM and other */
1052 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1054 case 0: /* SPECIAL */
1055 op
= rtype_funct (inst
);
1060 /* Set PC to that address */
1061 pc
= read_signed_register (rtype_rs (inst
));
1067 break; /* end SPECIAL */
1068 case 1: /* REGIMM */
1070 op
= itype_rt (inst
); /* branch condition */
1075 case 16: /* BLTZAL */
1076 case 18: /* BLTZALL */
1078 if (read_signed_register (itype_rs (inst
)) < 0)
1079 pc
+= mips32_relative_offset (inst
) + 4;
1081 pc
+= 8; /* after the delay slot */
1085 case 17: /* BGEZAL */
1086 case 19: /* BGEZALL */
1087 if (read_signed_register (itype_rs (inst
)) >= 0)
1088 pc
+= mips32_relative_offset (inst
) + 4;
1090 pc
+= 8; /* after the delay slot */
1092 /* All of the other instructions in the REGIMM category */
1097 break; /* end REGIMM */
1102 reg
= jtype_target (inst
) << 2;
1103 /* Upper four bits get never changed... */
1104 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1107 /* FIXME case JALX : */
1110 reg
= jtype_target (inst
) << 2;
1111 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1112 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1114 break; /* The new PC will be alternate mode */
1115 case 4: /* BEQ, BEQL */
1117 if (read_signed_register (itype_rs (inst
)) ==
1118 read_signed_register (itype_rt (inst
)))
1119 pc
+= mips32_relative_offset (inst
) + 4;
1123 case 5: /* BNE, BNEL */
1125 if (read_signed_register (itype_rs (inst
)) !=
1126 read_signed_register (itype_rt (inst
)))
1127 pc
+= mips32_relative_offset (inst
) + 4;
1131 case 6: /* BLEZ, BLEZL */
1132 if (read_signed_register (itype_rs (inst
) <= 0))
1133 pc
+= mips32_relative_offset (inst
) + 4;
1139 greater_branch
: /* BGTZ, BGTZL */
1140 if (read_signed_register (itype_rs (inst
) > 0))
1141 pc
+= mips32_relative_offset (inst
) + 4;
1148 } /* mips32_next_pc */
1150 /* Decoding the next place to set a breakpoint is irregular for the
1151 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1152 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1153 We dont want to set a single step instruction on the extend instruction
1157 /* Lots of mips16 instruction formats */
1158 /* Predicting jumps requires itype,ritype,i8type
1159 and their extensions extItype,extritype,extI8type
1161 enum mips16_inst_fmts
1163 itype
, /* 0 immediate 5,10 */
1164 ritype
, /* 1 5,3,8 */
1165 rrtype
, /* 2 5,3,3,5 */
1166 rritype
, /* 3 5,3,3,5 */
1167 rrrtype
, /* 4 5,3,3,3,2 */
1168 rriatype
, /* 5 5,3,3,1,4 */
1169 shifttype
, /* 6 5,3,3,3,2 */
1170 i8type
, /* 7 5,3,8 */
1171 i8movtype
, /* 8 5,3,3,5 */
1172 i8mov32rtype
, /* 9 5,3,5,3 */
1173 i64type
, /* 10 5,3,8 */
1174 ri64type
, /* 11 5,3,3,5 */
1175 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1176 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1177 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1178 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1179 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1180 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1181 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1182 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1183 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1184 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1186 /* I am heaping all the fields of the formats into one structure and
1187 then, only the fields which are involved in instruction extension */
1191 unsigned int regx
; /* Function in i8 type */
1196 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1197 for the bits which make up the immediatate extension. */
1200 extended_offset (unsigned int extension
)
1203 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1205 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1207 value
|= extension
& 0x01f; /* extract 4:0 */
1211 /* Only call this function if you know that this is an extendable
1212 instruction, It wont malfunction, but why make excess remote memory references?
1213 If the immediate operands get sign extended or somthing, do it after
1214 the extension is performed.
1216 /* FIXME: Every one of these cases needs to worry about sign extension
1217 when the offset is to be used in relative addressing */
1221 fetch_mips_16 (CORE_ADDR pc
)
1224 pc
&= 0xfffffffe; /* clear the low order bit */
1225 target_read_memory (pc
, buf
, 2);
1226 return extract_unsigned_integer (buf
, 2);
1230 unpack_mips16 (CORE_ADDR pc
,
1231 unsigned int extension
,
1233 enum mips16_inst_fmts insn_format
,
1234 struct upk_mips16
*upk
)
1239 switch (insn_format
)
1246 value
= extended_offset (extension
);
1247 value
= value
<< 11; /* rom for the original value */
1248 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1252 value
= inst
& 0x7ff;
1253 /* FIXME : Consider sign extension */
1262 { /* A register identifier and an offset */
1263 /* Most of the fields are the same as I type but the
1264 immediate value is of a different length */
1268 value
= extended_offset (extension
);
1269 value
= value
<< 8; /* from the original instruction */
1270 value
|= inst
& 0xff; /* eleven bits from instruction */
1271 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1272 if (value
& 0x4000) /* test the sign bit , bit 26 */
1274 value
&= ~0x3fff; /* remove the sign bit */
1280 value
= inst
& 0xff; /* 8 bits */
1281 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1282 /* FIXME: Do sign extension , this format needs it */
1283 if (value
& 0x80) /* THIS CONFUSES ME */
1285 value
&= 0xef; /* remove the sign bit */
1295 unsigned long value
;
1296 unsigned int nexthalf
;
1297 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1298 value
= value
<< 16;
1299 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1307 internal_error (__FILE__
, __LINE__
,
1310 upk
->offset
= offset
;
1317 add_offset_16 (CORE_ADDR pc
, int offset
)
1319 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1323 extended_mips16_next_pc (CORE_ADDR pc
,
1324 unsigned int extension
,
1327 int op
= (insn
>> 11);
1330 case 2: /* Branch */
1333 struct upk_mips16 upk
;
1334 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1335 offset
= upk
.offset
;
1341 pc
+= (offset
<< 1) + 2;
1344 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1346 struct upk_mips16 upk
;
1347 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1348 pc
= add_offset_16 (pc
, upk
.offset
);
1349 if ((insn
>> 10) & 0x01) /* Exchange mode */
1350 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1357 struct upk_mips16 upk
;
1359 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1360 reg
= read_signed_register (upk
.regx
);
1362 pc
+= (upk
.offset
<< 1) + 2;
1369 struct upk_mips16 upk
;
1371 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1372 reg
= read_signed_register (upk
.regx
);
1374 pc
+= (upk
.offset
<< 1) + 2;
1379 case 12: /* I8 Formats btez btnez */
1381 struct upk_mips16 upk
;
1383 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1384 /* upk.regx contains the opcode */
1385 reg
= read_signed_register (24); /* Test register is 24 */
1386 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1387 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1388 /* pc = add_offset_16(pc,upk.offset) ; */
1389 pc
+= (upk
.offset
<< 1) + 2;
1394 case 29: /* RR Formats JR, JALR, JALR-RA */
1396 struct upk_mips16 upk
;
1397 /* upk.fmt = rrtype; */
1402 upk
.regx
= (insn
>> 8) & 0x07;
1403 upk
.regy
= (insn
>> 5) & 0x07;
1411 break; /* Function return instruction */
1417 break; /* BOGUS Guess */
1419 pc
= read_signed_register (reg
);
1426 /* This is an instruction extension. Fetch the real instruction
1427 (which follows the extension) and decode things based on
1431 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1444 mips16_next_pc (CORE_ADDR pc
)
1446 unsigned int insn
= fetch_mips_16 (pc
);
1447 return extended_mips16_next_pc (pc
, 0, insn
);
1450 /* The mips_next_pc function supports single_step when the remote
1451 target monitor or stub is not developed enough to do a single_step.
1452 It works by decoding the current instruction and predicting where a
1453 branch will go. This isnt hard because all the data is available.
1454 The MIPS32 and MIPS16 variants are quite different */
1456 mips_next_pc (CORE_ADDR pc
)
1459 return mips16_next_pc (pc
);
1461 return mips32_next_pc (pc
);
1464 /* Set up the 'saved_regs' array. This is a data structure containing
1465 the addresses on the stack where each register has been saved, for
1466 each stack frame. Registers that have not been saved will have
1467 zero here. The stack pointer register is special: rather than the
1468 address where the stack register has been saved,
1469 saved_regs[SP_REGNUM] will have the actual value of the previous
1470 frame's stack register. */
1473 mips_find_saved_regs (struct frame_info
*fci
)
1476 /* r0 bit means kernel trap */
1478 /* What registers have been saved? Bitmasks. */
1479 unsigned long gen_mask
, float_mask
;
1480 mips_extra_func_info_t proc_desc
;
1482 CORE_ADDR
*saved_regs
;
1484 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1486 saved_regs
= frame_saved_regs_zalloc (fci
);
1488 /* If it is the frame for sigtramp, the saved registers are located
1489 in a sigcontext structure somewhere on the stack. If the stack
1490 layout for sigtramp changes we might have to change these
1491 constants and the companion fixup_sigtramp in mdebugread.c */
1492 #ifndef SIGFRAME_BASE
1493 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1494 above the sigtramp frame. */
1495 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1496 /* FIXME! Are these correct?? */
1497 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1498 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1499 #define SIGFRAME_FPREGSAVE_OFF \
1500 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1502 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1504 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1506 CORE_ADDR reg_position
= (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
1507 + ireg
* mips_regsize (current_gdbarch
));
1508 set_reg_offset (saved_regs
, ireg
, reg_position
);
1510 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1512 CORE_ADDR reg_position
= (get_frame_base (fci
)
1513 + SIGFRAME_FPREGSAVE_OFF
1514 + ireg
* mips_regsize (current_gdbarch
));
1515 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1518 set_reg_offset (saved_regs
, PC_REGNUM
, get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1519 /* SP_REGNUM, contains the value and not the address. */
1520 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1524 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1525 if (proc_desc
== NULL
)
1526 /* I'm not sure how/whether this can happen. Normally when we
1527 can't find a proc_desc, we "synthesize" one using
1528 heuristic_proc_desc and set the saved_regs right away. */
1531 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1532 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1533 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1535 if (/* In any frame other than the innermost or a frame interrupted
1536 by a signal, we assume that all registers have been saved.
1537 This assumes that all register saves in a function happen
1538 before the first function call. */
1539 (get_next_frame (fci
) == NULL
1540 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1542 /* In a dummy frame we know exactly where things are saved. */
1543 && !PROC_DESC_IS_DUMMY (proc_desc
)
1545 /* Don't bother unless we are inside a function prologue.
1546 Outside the prologue, we know where everything is. */
1548 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1550 /* Not sure exactly what kernel_trap means, but if it means the
1551 kernel saves the registers without a prologue doing it, we
1552 better not examine the prologue to see whether registers
1553 have been saved yet. */
1556 /* We need to figure out whether the registers that the
1557 proc_desc claims are saved have been saved yet. */
1561 /* Bitmasks; set if we have found a save for the register. */
1562 unsigned long gen_save_found
= 0;
1563 unsigned long float_save_found
= 0;
1566 /* If the address is odd, assume this is MIPS16 code. */
1567 addr
= PROC_LOW_ADDR (proc_desc
);
1568 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1570 /* Scan through this function's instructions preceding the
1571 current PC, and look for those that save registers. */
1572 while (addr
< get_frame_pc (fci
))
1574 inst
= mips_fetch_instruction (addr
);
1575 if (pc_is_mips16 (addr
))
1576 mips16_decode_reg_save (inst
, &gen_save_found
);
1578 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1581 gen_mask
= gen_save_found
;
1582 float_mask
= float_save_found
;
1585 /* Fill in the offsets for the registers which gen_mask says were
1588 CORE_ADDR reg_position
= (get_frame_base (fci
)
1589 + PROC_REG_OFFSET (proc_desc
));
1590 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1591 if (gen_mask
& 0x80000000)
1593 set_reg_offset (saved_regs
, ireg
, reg_position
);
1594 reg_position
-= MIPS_SAVED_REGSIZE
;
1598 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1599 order of that normally used by gcc. Therefore, we have to fetch
1600 the first instruction of the function, and if it's an entry
1601 instruction that saves $s0 or $s1, correct their saved addresses. */
1602 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1604 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1605 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1609 int sreg_count
= (inst
>> 6) & 3;
1611 /* Check if the ra register was pushed on the stack. */
1612 CORE_ADDR reg_position
= (get_frame_base (fci
)
1613 + PROC_REG_OFFSET (proc_desc
));
1615 reg_position
-= MIPS_SAVED_REGSIZE
;
1617 /* Check if the s0 and s1 registers were pushed on the
1619 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1621 set_reg_offset (saved_regs
, reg
, reg_position
);
1622 reg_position
-= MIPS_SAVED_REGSIZE
;
1627 /* Fill in the offsets for the registers which float_mask says were
1630 CORE_ADDR reg_position
= (get_frame_base (fci
)
1631 + PROC_FREG_OFFSET (proc_desc
));
1633 /* Fill in the offsets for the float registers which float_mask
1635 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1636 if (float_mask
& 0x80000000)
1638 if (MIPS_SAVED_REGSIZE
== 4 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1640 /* On a big endian 32 bit ABI, floating point registers
1641 are paired to form doubles such that the most
1642 significant part is in $f[N+1] and the least
1643 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1644 registers are also spilled as a pair and stored as a
1647 When little-endian the least significant part is
1648 stored first leading to the memory order $f[N] and
1651 Unfortunately, when big-endian the most significant
1652 part of the double is stored first, and the least
1653 significant is stored second. This leads to the
1654 registers being ordered in memory as firt $f[N+1] and
1657 For the big-endian case make certain that the
1658 addresses point at the correct (swapped) locations
1659 $f[N] and $f[N+1] pair (keep in mind that
1660 reg_position is decremented each time through the
1663 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1664 reg_position
- MIPS_SAVED_REGSIZE
);
1666 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1667 reg_position
+ MIPS_SAVED_REGSIZE
);
1670 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1671 reg_position
-= MIPS_SAVED_REGSIZE
;
1674 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1677 /* SP_REGNUM, contains the value and not the address. */
1678 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1682 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1684 /* Always a pseudo. */
1685 gdb_assert (regno
>= NUM_REGS
);
1689 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1692 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1693 /* The SP_REGNUM is special, its value is stored in saved_regs.
1694 In fact, it is so special that it can even only be fetched
1695 using a raw register number! Once this code as been converted
1696 to frame-unwind the problem goes away. */
1697 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1699 return frame_unwind_register_signed (fi
, regno
);
1703 /* mips_addr_bits_remove - remove useless address bits */
1706 mips_addr_bits_remove (CORE_ADDR addr
)
1708 if (mips_mask_address_p ()
1709 && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1710 /* This hack is a work-around for existing boards using PMON, the
1711 simulator, and any other 64-bit targets that doesn't have true
1712 64-bit addressing. On these targets, the upper 32 bits of
1713 addresses are ignored by the hardware. Thus, the PC or SP are
1714 likely to have been sign extended to all 1s by instruction
1715 sequences that load 32-bit addresses. For example, a typical
1716 piece of code that loads an address is this:
1718 lui $r2, <upper 16 bits>
1719 ori $r2, <lower 16 bits>
1721 But the lui sign-extends the value such that the upper 32 bits
1722 may be all 1s. The workaround is simply to mask off these
1723 bits. In the future, gcc may be changed to support true 64-bit
1724 addressing, and this masking will have to be disabled. */
1725 return addr
&= 0xffffffffUL
;
1730 /* mips_software_single_step() is called just before we want to resume
1731 the inferior, if we want to single-step it but there is no hardware
1732 or kernel single-step support (MIPS on GNU/Linux for example). We find
1733 the target of the coming instruction and breakpoint it.
1735 single_step is also called just after the inferior stops. If we had
1736 set up a simulated single-step, we undo our damage. */
1739 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1741 static CORE_ADDR next_pc
;
1742 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1743 static binsn_quantum break_mem
;
1746 if (insert_breakpoints_p
)
1748 pc
= read_register (PC_REGNUM
);
1749 next_pc
= mips_next_pc (pc
);
1751 target_insert_breakpoint (next_pc
, break_mem
);
1754 target_remove_breakpoint (next_pc
, break_mem
);
1758 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1763 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1764 : get_next_frame (prev
)
1765 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
))
1767 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1768 return tmp
? tmp
: pc
;
1773 mips_frame_saved_pc (struct frame_info
*frame
)
1777 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1779 /* Always unwind the cooked PC register value. */
1780 saved_pc
= frame_unwind_register_signed (frame
, NUM_REGS
+ PC_REGNUM
);
1784 mips_extra_func_info_t proc_desc
1785 = get_frame_extra_info (frame
)->proc_desc
;
1786 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1787 saved_pc
= read_memory_integer (get_frame_base (frame
) - MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1790 /* We have to get the saved pc from the sigcontext if it is
1791 a signal handler frame. */
1792 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1793 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1794 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1797 return ADDR_BITS_REMOVE (saved_pc
);
1800 static struct mips_extra_func_info temp_proc_desc
;
1802 /* This hack will go away once the get_prev_frame() code has been
1803 modified to set the frame's type first. That is BEFORE init extra
1804 frame info et.al. is called. This is because it will become
1805 possible to skip the init extra info call for sigtramp and dummy
1807 static CORE_ADDR
*temp_saved_regs
;
1809 /* Set a register's saved stack address in temp_saved_regs. If an
1810 address has already been set for this register, do nothing; this
1811 way we will only recognize the first save of a given register in a
1814 For simplicity, save the address in both [0 .. NUM_REGS) and
1815 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1816 is used as it is only second range (the ABI instead of ISA
1817 registers) that comes into play when finding saved registers in a
1821 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1823 if (saved_regs
[regno
] == 0)
1825 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1826 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1831 /* Test whether the PC points to the return instruction at the
1832 end of a function. */
1835 mips_about_to_return (CORE_ADDR pc
)
1837 if (pc_is_mips16 (pc
))
1838 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1839 generates a "jr $ra"; other times it generates code to load
1840 the return address from the stack to an accessible register (such
1841 as $a3), then a "jr" using that register. This second case
1842 is almost impossible to distinguish from an indirect jump
1843 used for switch statements, so we don't even try. */
1844 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1846 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1850 /* This fencepost looks highly suspicious to me. Removing it also
1851 seems suspicious as it could affect remote debugging across serial
1855 heuristic_proc_start (CORE_ADDR pc
)
1862 pc
= ADDR_BITS_REMOVE (pc
);
1864 fence
= start_pc
- heuristic_fence_post
;
1868 if (heuristic_fence_post
== UINT_MAX
1869 || fence
< VM_MIN_ADDRESS
)
1870 fence
= VM_MIN_ADDRESS
;
1872 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1874 /* search back for previous return */
1875 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1876 if (start_pc
< fence
)
1878 /* It's not clear to me why we reach this point when
1879 stop_soon, but with this test, at least we
1880 don't print out warnings for every child forked (eg, on
1881 decstation). 22apr93 rich@cygnus.com. */
1882 if (stop_soon
== NO_STOP_QUIETLY
)
1884 static int blurb_printed
= 0;
1886 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1891 /* This actually happens frequently in embedded
1892 development, when you first connect to a board
1893 and your stack pointer and pc are nowhere in
1894 particular. This message needs to give people
1895 in that situation enough information to
1896 determine that it's no big deal. */
1897 printf_filtered ("\n\
1898 GDB is unable to find the start of the function at 0x%s\n\
1899 and thus can't determine the size of that function's stack frame.\n\
1900 This means that GDB may be unable to access that stack frame, or\n\
1901 the frames below it.\n\
1902 This problem is most likely caused by an invalid program counter or\n\
1904 However, if you think GDB should simply search farther back\n\
1905 from 0x%s for code which looks like the beginning of a\n\
1906 function, you can increase the range of the search using the `set\n\
1907 heuristic-fence-post' command.\n",
1908 paddr_nz (pc
), paddr_nz (pc
));
1915 else if (pc_is_mips16 (start_pc
))
1917 unsigned short inst
;
1919 /* On MIPS16, any one of the following is likely to be the
1920 start of a function:
1924 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1925 inst
= mips_fetch_instruction (start_pc
);
1926 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1927 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1928 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1929 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1931 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1932 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1937 else if (mips_about_to_return (start_pc
))
1939 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1946 /* Fetch the immediate value from a MIPS16 instruction.
1947 If the previous instruction was an EXTEND, use it to extend
1948 the upper bits of the immediate value. This is a helper function
1949 for mips16_heuristic_proc_desc. */
1952 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1953 unsigned short inst
, /* current instruction */
1954 int nbits
, /* number of bits in imm field */
1955 int scale
, /* scale factor to be applied to imm */
1956 int is_signed
) /* is the imm field signed? */
1960 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1962 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1963 if (offset
& 0x8000) /* check for negative extend */
1964 offset
= 0 - (0x10000 - (offset
& 0xffff));
1965 return offset
| (inst
& 0x1f);
1969 int max_imm
= 1 << nbits
;
1970 int mask
= max_imm
- 1;
1971 int sign_bit
= max_imm
>> 1;
1973 offset
= inst
& mask
;
1974 if (is_signed
&& (offset
& sign_bit
))
1975 offset
= 0 - (max_imm
- offset
);
1976 return offset
* scale
;
1981 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1982 stream from start_pc to limit_pc. */
1985 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1986 struct frame_info
*next_frame
, CORE_ADDR sp
)
1989 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1990 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1991 unsigned inst
= 0; /* current instruction */
1992 unsigned entry_inst
= 0; /* the entry instruction */
1995 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1996 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1998 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2000 /* Save the previous instruction. If it's an EXTEND, we'll extract
2001 the immediate offset extension from it in mips16_get_imm. */
2004 /* Fetch and decode the instruction. */
2005 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2006 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2007 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2009 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2010 if (offset
< 0) /* negative stack adjustment? */
2011 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2013 /* Exit loop if a positive stack adjustment is found, which
2014 usually means that the stack cleanup code in the function
2015 epilogue is reached. */
2018 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2020 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2021 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2022 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2023 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2025 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2027 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2028 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2029 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2030 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2032 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2034 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2035 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2036 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2038 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2040 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2041 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2042 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2044 else if (inst
== 0x673d) /* move $s1, $sp */
2047 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2049 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2051 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2052 frame_addr
= sp
+ offset
;
2053 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2054 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2056 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2058 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2059 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2060 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2061 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2063 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2065 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2066 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2067 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2068 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2070 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2071 entry_inst
= inst
; /* save for later processing */
2072 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2073 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2076 /* The entry instruction is typically the first instruction in a function,
2077 and it stores registers at offsets relative to the value of the old SP
2078 (before the prologue). But the value of the sp parameter to this
2079 function is the new SP (after the prologue has been executed). So we
2080 can't calculate those offsets until we've seen the entire prologue,
2081 and can calculate what the old SP must have been. */
2082 if (entry_inst
!= 0)
2084 int areg_count
= (entry_inst
>> 8) & 7;
2085 int sreg_count
= (entry_inst
>> 6) & 3;
2087 /* The entry instruction always subtracts 32 from the SP. */
2088 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2090 /* Now we can calculate what the SP must have been at the
2091 start of the function prologue. */
2092 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2094 /* Check if a0-a3 were saved in the caller's argument save area. */
2095 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2097 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2098 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2099 offset
+= MIPS_SAVED_REGSIZE
;
2102 /* Check if the ra register was pushed on the stack. */
2104 if (entry_inst
& 0x20)
2106 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2107 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2108 offset
-= MIPS_SAVED_REGSIZE
;
2111 /* Check if the s0 and s1 registers were pushed on the stack. */
2112 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2114 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2115 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2116 offset
-= MIPS_SAVED_REGSIZE
;
2122 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2123 struct frame_info
*next_frame
, CORE_ADDR sp
)
2126 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2128 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2129 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2130 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2131 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2132 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2134 unsigned long inst
, high_word
, low_word
;
2137 /* Fetch the instruction. */
2138 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2140 /* Save some code by pre-extracting some useful fields. */
2141 high_word
= (inst
>> 16) & 0xffff;
2142 low_word
= inst
& 0xffff;
2143 reg
= high_word
& 0x1f;
2145 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2146 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2147 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2149 if (low_word
& 0x8000) /* negative stack adjustment? */
2150 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2152 /* Exit loop if a positive stack adjustment is found, which
2153 usually means that the stack cleanup code in the function
2154 epilogue is reached. */
2157 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2159 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2160 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2162 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2164 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2165 but the register size used is only 32 bits. Make the address
2166 for the saved register point to the lower 32 bits. */
2167 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2168 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2170 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2172 /* Old gcc frame, r30 is virtual frame pointer. */
2173 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2174 frame_addr
= sp
+ low_word
;
2175 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2177 unsigned alloca_adjust
;
2178 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2179 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2180 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2181 if (alloca_adjust
> 0)
2183 /* FP > SP + frame_size. This may be because
2184 * of an alloca or somethings similar.
2185 * Fix sp to "pre-alloca" value, and try again.
2187 sp
+= alloca_adjust
;
2192 /* move $30,$sp. With different versions of gas this will be either
2193 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2194 Accept any one of these. */
2195 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2197 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2198 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2200 unsigned alloca_adjust
;
2201 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2202 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2203 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2204 if (alloca_adjust
> 0)
2206 /* FP > SP + frame_size. This may be because
2207 * of an alloca or somethings similar.
2208 * Fix sp to "pre-alloca" value, and try again.
2210 sp
+= alloca_adjust
;
2215 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2217 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2218 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2223 static mips_extra_func_info_t
2224 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2225 struct frame_info
*next_frame
, int cur_frame
)
2230 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2236 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2237 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2238 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2239 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2240 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2241 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2243 if (start_pc
+ 200 < limit_pc
)
2244 limit_pc
= start_pc
+ 200;
2245 if (pc_is_mips16 (start_pc
))
2246 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2248 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2249 return &temp_proc_desc
;
2252 struct mips_objfile_private
2258 /* Global used to communicate between non_heuristic_proc_desc and
2259 compare_pdr_entries within qsort (). */
2260 static bfd
*the_bfd
;
2263 compare_pdr_entries (const void *a
, const void *b
)
2265 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2266 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2270 else if (lhs
== rhs
)
2276 static mips_extra_func_info_t
2277 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2279 CORE_ADDR startaddr
;
2280 mips_extra_func_info_t proc_desc
;
2281 struct block
*b
= block_for_pc (pc
);
2283 struct obj_section
*sec
;
2284 struct mips_objfile_private
*priv
;
2286 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2289 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2291 *addrptr
= startaddr
;
2295 sec
= find_pc_section (pc
);
2298 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2300 /* Search the ".pdr" section generated by GAS. This includes most of
2301 the information normally found in ECOFF PDRs. */
2303 the_bfd
= sec
->objfile
->obfd
;
2305 && (the_bfd
->format
== bfd_object
2306 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2307 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2309 /* Right now GAS only outputs the address as a four-byte sequence.
2310 This means that we should not bother with this method on 64-bit
2311 targets (until that is fixed). */
2313 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2314 sizeof (struct mips_objfile_private
));
2316 sec
->objfile
->obj_private
= priv
;
2318 else if (priv
== NULL
)
2322 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2323 sizeof (struct mips_objfile_private
));
2325 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2328 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2329 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2331 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2332 priv
->contents
, 0, priv
->size
);
2334 /* In general, the .pdr section is sorted. However, in the
2335 presence of multiple code sections (and other corner cases)
2336 it can become unsorted. Sort it so that we can use a faster
2338 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2343 sec
->objfile
->obj_private
= priv
;
2347 if (priv
->size
!= 0)
2353 high
= priv
->size
/ 32;
2359 mid
= (low
+ high
) / 2;
2361 ptr
= priv
->contents
+ mid
* 32;
2362 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2363 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2364 SECT_OFF_TEXT (sec
->objfile
));
2365 if (pdr_pc
== startaddr
)
2367 if (pdr_pc
> startaddr
)
2372 while (low
!= high
);
2376 struct symbol
*sym
= find_pc_function (pc
);
2378 /* Fill in what we need of the proc_desc. */
2379 proc_desc
= (mips_extra_func_info_t
)
2380 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2381 sizeof (struct mips_extra_func_info
));
2382 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2384 /* Only used for dummy frames. */
2385 PROC_HIGH_ADDR (proc_desc
) = 0;
2387 PROC_FRAME_OFFSET (proc_desc
)
2388 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2389 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2391 PROC_FRAME_ADJUST (proc_desc
) = 0;
2392 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2394 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2396 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2398 PROC_FREG_OFFSET (proc_desc
)
2399 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2400 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2402 proc_desc
->pdr
.isym
= (long) sym
;
2412 if (startaddr
> BLOCK_START (b
))
2414 /* This is the "pathological" case referred to in a comment in
2415 print_frame_info. It might be better to move this check into
2420 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2422 /* If we never found a PDR for this function in symbol reading, then
2423 examine prologues to find the information. */
2426 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2427 if (PROC_FRAME_REG (proc_desc
) == -1)
2437 static mips_extra_func_info_t
2438 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2440 mips_extra_func_info_t proc_desc
;
2441 CORE_ADDR startaddr
= 0;
2443 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2447 /* IF this is the topmost frame AND
2448 * (this proc does not have debugging information OR
2449 * the PC is in the procedure prologue)
2450 * THEN create a "heuristic" proc_desc (by analyzing
2451 * the actual code) to replace the "official" proc_desc.
2453 if (next_frame
== NULL
)
2455 struct symtab_and_line val
;
2456 struct symbol
*proc_symbol
=
2457 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2461 val
= find_pc_line (BLOCK_START
2462 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2464 val
.pc
= val
.end
? val
.end
: pc
;
2466 if (!proc_symbol
|| pc
< val
.pc
)
2468 mips_extra_func_info_t found_heuristic
=
2469 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2470 pc
, next_frame
, cur_frame
);
2471 if (found_heuristic
)
2472 proc_desc
= found_heuristic
;
2478 /* Is linked_proc_desc_table really necessary? It only seems to be used
2479 by procedure call dummys. However, the procedures being called ought
2480 to have their own proc_descs, and even if they don't,
2481 heuristic_proc_desc knows how to create them! */
2483 struct linked_proc_info
*link
;
2485 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2486 if (PROC_LOW_ADDR (&link
->info
) <= pc
2487 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2491 startaddr
= heuristic_proc_start (pc
);
2494 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2500 get_frame_pointer (struct frame_info
*frame
,
2501 mips_extra_func_info_t proc_desc
)
2503 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2504 + PROC_FRAME_OFFSET (proc_desc
)
2505 - PROC_FRAME_ADJUST (proc_desc
));
2508 static mips_extra_func_info_t cached_proc_desc
;
2511 mips_frame_chain (struct frame_info
*frame
)
2513 mips_extra_func_info_t proc_desc
;
2515 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2517 /* Check if the PC is inside a call stub. If it is, fetch the
2518 PC of the caller of that stub. */
2519 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2522 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2524 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2525 is well, frame->frame the bottom of the current frame will
2526 contain that value. */
2527 return get_frame_base (frame
);
2530 /* Look up the procedure descriptor for this PC. */
2531 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2535 cached_proc_desc
= proc_desc
;
2537 /* If no frame pointer and frame size is zero, we must be at end
2538 of stack (or otherwise hosed). If we don't check frame size,
2539 we loop forever if we see a zero size frame. */
2540 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2541 && PROC_FRAME_OFFSET (proc_desc
) == 0
2542 /* The previous frame from a sigtramp frame might be frameless
2543 and have frame size zero. */
2544 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2545 /* For a generic dummy frame, let get_frame_pointer() unwind a
2546 register value saved as part of the dummy frame call. */
2547 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2550 return get_frame_pointer (frame
, proc_desc
);
2554 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2557 mips_extra_func_info_t proc_desc
;
2559 if (get_frame_type (fci
) == DUMMY_FRAME
)
2562 /* Use proc_desc calculated in frame_chain. When there is no
2563 next frame, i.e, get_next_frame (fci) == NULL, we call
2564 find_proc_desc () to calculate it, passing an explicit
2565 NULL as the frame parameter. */
2567 get_next_frame (fci
)
2569 : find_proc_desc (get_frame_pc (fci
),
2570 NULL
/* i.e, get_next_frame (fci) */,
2573 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2575 get_frame_extra_info (fci
)->proc_desc
=
2576 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2579 /* Fixup frame-pointer - only needed for top frame */
2580 /* This may not be quite right, if proc has a real frame register.
2581 Get the value of the frame relative sp, procedure might have been
2582 interrupted by a signal at it's very start. */
2583 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2584 && !PROC_DESC_IS_DUMMY (proc_desc
))
2585 deprecated_update_frame_base_hack (fci
, read_next_frame_reg (get_next_frame (fci
), NUM_REGS
+ SP_REGNUM
));
2586 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2587 /* Do not ``fix'' fci->frame. It will have the value of the
2588 generic dummy frame's top-of-stack (since the draft
2589 fci->frame is obtained by returning the unwound stack
2590 pointer) and that is what we want. That way the fci->frame
2591 value will match the top-of-stack value that was saved as
2592 part of the dummy frames data. */
2595 deprecated_update_frame_base_hack (fci
, get_frame_pointer (get_next_frame (fci
), proc_desc
));
2597 if (proc_desc
== &temp_proc_desc
)
2601 /* Do not set the saved registers for a sigtramp frame,
2602 mips_find_saved_registers will do that for us. We can't
2603 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2605 /* FIXME: cagney/2002-11-18: This problem will go away once
2606 frame.c:get_prev_frame() is modified to set the frame's
2607 type before calling functions like this. */
2608 find_pc_partial_function (get_frame_pc (fci
), &name
,
2609 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2610 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2612 frame_saved_regs_zalloc (fci
);
2613 /* Set value of previous frame's stack pointer.
2614 Remember that saved_regs[SP_REGNUM] is special in
2615 that it contains the value of the stack pointer
2616 register. The other saved_regs values are addresses
2617 (in the inferior) at which a given register's value
2619 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2620 get_frame_base (fci
));
2621 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2622 temp_saved_regs
[RA_REGNUM
]);
2623 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2624 SIZEOF_FRAME_SAVED_REGS
);
2628 /* hack: if argument regs are saved, guess these contain args */
2629 /* assume we can't tell how many args for now */
2630 get_frame_extra_info (fci
)->num_args
= -1;
2631 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2633 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2635 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2642 /* MIPS stack frames are almost impenetrable. When execution stops,
2643 we basically have to look at symbol information for the function
2644 that we stopped in, which tells us *which* register (if any) is
2645 the base of the frame pointer, and what offset from that register
2646 the frame itself is at.
2648 This presents a problem when trying to examine a stack in memory
2649 (that isn't executing at the moment), using the "frame" command. We
2650 don't have a PC, nor do we have any registers except SP.
2652 This routine takes two arguments, SP and PC, and tries to make the
2653 cached frames look as if these two arguments defined a frame on the
2654 cache. This allows the rest of info frame to extract the important
2655 arguments without difficulty. */
2658 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2661 error ("MIPS frame specifications require two arguments: sp and pc");
2663 return create_new_frame (argv
[0], argv
[1]);
2666 /* According to the current ABI, should the type be passed in a
2667 floating-point register (assuming that there is space)? When there
2668 is no FPU, FP are not even considered as possibile candidates for
2669 FP registers and, consequently this returns false - forces FP
2670 arguments into integer registers. */
2673 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2675 return ((typecode
== TYPE_CODE_FLT
2677 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2678 && TYPE_NFIELDS (arg_type
) == 1
2679 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2680 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2683 /* On o32, argument passing in GPRs depends on the alignment of the type being
2684 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2687 mips_type_needs_double_align (struct type
*type
)
2689 enum type_code typecode
= TYPE_CODE (type
);
2691 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2693 else if (typecode
== TYPE_CODE_STRUCT
)
2695 if (TYPE_NFIELDS (type
) < 1)
2697 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2699 else if (typecode
== TYPE_CODE_UNION
)
2703 n
= TYPE_NFIELDS (type
);
2704 for (i
= 0; i
< n
; i
++)
2705 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2712 /* Adjust the address downward (direction of stack growth) so that it
2713 is correctly aligned for a new stack frame. */
2715 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2717 return align_down (addr
, 16);
2721 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2722 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2723 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2724 CORE_ADDR struct_addr
)
2730 int stack_offset
= 0;
2732 /* For shared libraries, "t9" needs to point at the function
2734 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2736 /* Set the return address register to point to the entry point of
2737 the program, where a breakpoint lies in wait. */
2738 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2740 /* First ensure that the stack and structure return address (if any)
2741 are properly aligned. The stack has to be at least 64-bit
2742 aligned even on 32-bit machines, because doubles must be 64-bit
2743 aligned. For n32 and n64, stack frames need to be 128-bit
2744 aligned, so we round to this widest known alignment. */
2746 sp
= align_down (sp
, 16);
2747 struct_addr
= align_down (struct_addr
, 16);
2749 /* Now make space on the stack for the args. We allocate more
2750 than necessary for EABI, because the first few arguments are
2751 passed in registers, but that's OK. */
2752 for (argnum
= 0; argnum
< nargs
; argnum
++)
2753 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2754 MIPS_STACK_ARGSIZE
);
2755 sp
-= align_up (len
, 16);
2758 fprintf_unfiltered (gdb_stdlog
,
2759 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2760 paddr_nz (sp
), (long) align_up (len
, 16));
2762 /* Initialize the integer and float register pointers. */
2764 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2766 /* The struct_return pointer occupies the first parameter-passing reg. */
2770 fprintf_unfiltered (gdb_stdlog
,
2771 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2772 argreg
, paddr_nz (struct_addr
));
2773 write_register (argreg
++, struct_addr
);
2776 /* Now load as many as possible of the first arguments into
2777 registers, and push the rest onto the stack. Loop thru args
2778 from first to last. */
2779 for (argnum
= 0; argnum
< nargs
; argnum
++)
2782 char valbuf
[MAX_REGISTER_SIZE
];
2783 struct value
*arg
= args
[argnum
];
2784 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2785 int len
= TYPE_LENGTH (arg_type
);
2786 enum type_code typecode
= TYPE_CODE (arg_type
);
2789 fprintf_unfiltered (gdb_stdlog
,
2790 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2791 argnum
+ 1, len
, (int) typecode
);
2793 /* The EABI passes structures that do not fit in a register by
2795 if (len
> MIPS_SAVED_REGSIZE
2796 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2798 store_unsigned_integer (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2799 typecode
= TYPE_CODE_PTR
;
2800 len
= MIPS_SAVED_REGSIZE
;
2803 fprintf_unfiltered (gdb_stdlog
, " push");
2806 val
= (char *) VALUE_CONTENTS (arg
);
2808 /* 32-bit ABIs always start floating point arguments in an
2809 even-numbered floating point register. Round the FP register
2810 up before the check to see if there are any FP registers
2811 left. Non MIPS_EABI targets also pass the FP in the integer
2812 registers so also round up normal registers. */
2813 if (!FP_REGISTER_DOUBLE
2814 && fp_register_arg_p (typecode
, arg_type
))
2816 if ((float_argreg
& 1))
2820 /* Floating point arguments passed in registers have to be
2821 treated specially. On 32-bit architectures, doubles
2822 are passed in register pairs; the even register gets
2823 the low word, and the odd register gets the high word.
2824 On non-EABI processors, the first two floating point arguments are
2825 also copied to general registers, because MIPS16 functions
2826 don't use float registers for arguments. This duplication of
2827 arguments in general registers can't hurt non-MIPS16 functions
2828 because those registers are normally skipped. */
2829 /* MIPS_EABI squeezes a struct that contains a single floating
2830 point value into an FP register instead of pushing it onto the
2832 if (fp_register_arg_p (typecode
, arg_type
)
2833 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2835 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2837 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2838 unsigned long regval
;
2840 /* Write the low word of the double to the even register(s). */
2841 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2843 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2844 float_argreg
, phex (regval
, 4));
2845 write_register (float_argreg
++, regval
);
2847 /* Write the high word of the double to the odd register(s). */
2848 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2850 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2851 float_argreg
, phex (regval
, 4));
2852 write_register (float_argreg
++, regval
);
2856 /* This is a floating point value that fits entirely
2857 in a single register. */
2858 /* On 32 bit ABI's the float_argreg is further adjusted
2859 above to ensure that it is even register aligned. */
2860 LONGEST regval
= extract_unsigned_integer (val
, len
);
2862 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2863 float_argreg
, phex (regval
, len
));
2864 write_register (float_argreg
++, regval
);
2869 /* Copy the argument to general registers or the stack in
2870 register-sized pieces. Large arguments are split between
2871 registers and stack. */
2872 /* Note: structs whose size is not a multiple of
2873 mips_regsize() are treated specially: Irix cc passes them
2874 in registers where gcc sometimes puts them on the stack.
2875 For maximum compatibility, we will put them in both
2877 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2878 (len
% MIPS_SAVED_REGSIZE
!= 0));
2880 /* Note: Floating-point values that didn't fit into an FP
2881 register are only written to memory. */
2884 /* Remember if the argument was written to the stack. */
2885 int stack_used_p
= 0;
2887 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2890 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2893 /* Write this portion of the argument to the stack. */
2894 if (argreg
> MIPS_LAST_ARG_REGNUM
2896 || fp_register_arg_p (typecode
, arg_type
))
2898 /* Should shorter than int integer values be
2899 promoted to int before being stored? */
2900 int longword_offset
= 0;
2903 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2905 if (MIPS_STACK_ARGSIZE
== 8 &&
2906 (typecode
== TYPE_CODE_INT
||
2907 typecode
== TYPE_CODE_PTR
||
2908 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2909 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2910 else if ((typecode
== TYPE_CODE_STRUCT
||
2911 typecode
== TYPE_CODE_UNION
) &&
2912 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2913 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2918 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2919 paddr_nz (stack_offset
));
2920 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2921 paddr_nz (longword_offset
));
2924 addr
= sp
+ stack_offset
+ longword_offset
;
2929 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2931 for (i
= 0; i
< partial_len
; i
++)
2933 fprintf_unfiltered (gdb_stdlog
, "%02x",
2937 write_memory (addr
, val
, partial_len
);
2940 /* Note!!! This is NOT an else clause. Odd sized
2941 structs may go thru BOTH paths. Floating point
2942 arguments will not. */
2943 /* Write this portion of the argument to a general
2944 purpose register. */
2945 if (argreg
<= MIPS_LAST_ARG_REGNUM
2946 && !fp_register_arg_p (typecode
, arg_type
))
2948 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2951 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2953 phex (regval
, MIPS_SAVED_REGSIZE
));
2954 write_register (argreg
, regval
);
2961 /* Compute the the offset into the stack at which we
2962 will copy the next parameter.
2964 In the new EABI (and the NABI32), the stack_offset
2965 only needs to be adjusted when it has been used. */
2968 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
2972 fprintf_unfiltered (gdb_stdlog
, "\n");
2975 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
2977 /* Return adjusted stack pointer. */
2981 /* N32/N64 version of push_dummy_call. */
2984 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2985 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2986 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2987 CORE_ADDR struct_addr
)
2993 int stack_offset
= 0;
2995 /* For shared libraries, "t9" needs to point at the function
2997 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2999 /* Set the return address register to point to the entry point of
3000 the program, where a breakpoint lies in wait. */
3001 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3003 /* First ensure that the stack and structure return address (if any)
3004 are properly aligned. The stack has to be at least 64-bit
3005 aligned even on 32-bit machines, because doubles must be 64-bit
3006 aligned. For n32 and n64, stack frames need to be 128-bit
3007 aligned, so we round to this widest known alignment. */
3009 sp
= align_down (sp
, 16);
3010 struct_addr
= align_down (struct_addr
, 16);
3012 /* Now make space on the stack for the args. */
3013 for (argnum
= 0; argnum
< nargs
; argnum
++)
3014 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3015 MIPS_STACK_ARGSIZE
);
3016 sp
-= align_up (len
, 16);
3019 fprintf_unfiltered (gdb_stdlog
,
3020 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3021 paddr_nz (sp
), (long) align_up (len
, 16));
3023 /* Initialize the integer and float register pointers. */
3025 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3027 /* The struct_return pointer occupies the first parameter-passing reg. */
3031 fprintf_unfiltered (gdb_stdlog
,
3032 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3033 argreg
, paddr_nz (struct_addr
));
3034 write_register (argreg
++, struct_addr
);
3037 /* Now load as many as possible of the first arguments into
3038 registers, and push the rest onto the stack. Loop thru args
3039 from first to last. */
3040 for (argnum
= 0; argnum
< nargs
; argnum
++)
3043 char valbuf
[MAX_REGISTER_SIZE
];
3044 struct value
*arg
= args
[argnum
];
3045 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3046 int len
= TYPE_LENGTH (arg_type
);
3047 enum type_code typecode
= TYPE_CODE (arg_type
);
3050 fprintf_unfiltered (gdb_stdlog
,
3051 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3052 argnum
+ 1, len
, (int) typecode
);
3054 val
= (char *) VALUE_CONTENTS (arg
);
3056 if (fp_register_arg_p (typecode
, arg_type
)
3057 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3059 /* This is a floating point value that fits entirely
3060 in a single register. */
3061 /* On 32 bit ABI's the float_argreg is further adjusted
3062 above to ensure that it is even register aligned. */
3063 LONGEST regval
= extract_unsigned_integer (val
, len
);
3065 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3066 float_argreg
, phex (regval
, len
));
3067 write_register (float_argreg
++, regval
);
3070 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3071 argreg
, phex (regval
, len
));
3072 write_register (argreg
, regval
);
3077 /* Copy the argument to general registers or the stack in
3078 register-sized pieces. Large arguments are split between
3079 registers and stack. */
3080 /* Note: structs whose size is not a multiple of
3081 mips_regsize() are treated specially: Irix cc passes them
3082 in registers where gcc sometimes puts them on the stack.
3083 For maximum compatibility, we will put them in both
3085 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3086 (len
% MIPS_SAVED_REGSIZE
!= 0));
3087 /* Note: Floating-point values that didn't fit into an FP
3088 register are only written to memory. */
3091 /* Rememer if the argument was written to the stack. */
3092 int stack_used_p
= 0;
3093 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
3094 len
: MIPS_SAVED_REGSIZE
;
3097 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3100 /* Write this portion of the argument to the stack. */
3101 if (argreg
> MIPS_LAST_ARG_REGNUM
3103 || fp_register_arg_p (typecode
, arg_type
))
3105 /* Should shorter than int integer values be
3106 promoted to int before being stored? */
3107 int longword_offset
= 0;
3110 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3112 if (MIPS_STACK_ARGSIZE
== 8 &&
3113 (typecode
== TYPE_CODE_INT
||
3114 typecode
== TYPE_CODE_PTR
||
3115 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3116 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3121 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3122 paddr_nz (stack_offset
));
3123 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3124 paddr_nz (longword_offset
));
3127 addr
= sp
+ stack_offset
+ longword_offset
;
3132 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3134 for (i
= 0; i
< partial_len
; i
++)
3136 fprintf_unfiltered (gdb_stdlog
, "%02x",
3140 write_memory (addr
, val
, partial_len
);
3143 /* Note!!! This is NOT an else clause. Odd sized
3144 structs may go thru BOTH paths. Floating point
3145 arguments will not. */
3146 /* Write this portion of the argument to a general
3147 purpose register. */
3148 if (argreg
<= MIPS_LAST_ARG_REGNUM
3149 && !fp_register_arg_p (typecode
, arg_type
))
3151 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3153 /* A non-floating-point argument being passed in a
3154 general register. If a struct or union, and if
3155 the remaining length is smaller than the register
3156 size, we have to adjust the register value on
3159 It does not seem to be necessary to do the
3160 same for integral types.
3162 cagney/2001-07-23: gdb/179: Also, GCC, when
3163 outputting LE O32 with sizeof (struct) <
3164 MIPS_SAVED_REGSIZE, generates a left shift as
3165 part of storing the argument in a register a
3166 register (the left shift isn't generated when
3167 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3168 is quite possible that this is GCC contradicting
3169 the LE/O32 ABI, GDB has not been adjusted to
3170 accommodate this. Either someone needs to
3171 demonstrate that the LE/O32 ABI specifies such a
3172 left shift OR this new ABI gets identified as
3173 such and GDB gets tweaked accordingly. */
3175 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3176 && partial_len
< MIPS_SAVED_REGSIZE
3177 && (typecode
== TYPE_CODE_STRUCT
||
3178 typecode
== TYPE_CODE_UNION
))
3179 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3183 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3185 phex (regval
, MIPS_SAVED_REGSIZE
));
3186 write_register (argreg
, regval
);
3193 /* Compute the the offset into the stack at which we
3194 will copy the next parameter.
3196 In N32 (N64?), the stack_offset only needs to be
3197 adjusted when it has been used. */
3200 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3204 fprintf_unfiltered (gdb_stdlog
, "\n");
3207 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3209 /* Return adjusted stack pointer. */
3213 /* O32 version of push_dummy_call. */
3216 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3217 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3218 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3219 CORE_ADDR struct_addr
)
3225 int stack_offset
= 0;
3227 /* For shared libraries, "t9" needs to point at the function
3229 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3231 /* Set the return address register to point to the entry point of
3232 the program, where a breakpoint lies in wait. */
3233 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3235 /* First ensure that the stack and structure return address (if any)
3236 are properly aligned. The stack has to be at least 64-bit
3237 aligned even on 32-bit machines, because doubles must be 64-bit
3238 aligned. For n32 and n64, stack frames need to be 128-bit
3239 aligned, so we round to this widest known alignment. */
3241 sp
= align_down (sp
, 16);
3242 struct_addr
= align_down (struct_addr
, 16);
3244 /* Now make space on the stack for the args. */
3245 for (argnum
= 0; argnum
< nargs
; argnum
++)
3246 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3247 MIPS_STACK_ARGSIZE
);
3248 sp
-= align_up (len
, 16);
3251 fprintf_unfiltered (gdb_stdlog
,
3252 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3253 paddr_nz (sp
), (long) align_up (len
, 16));
3255 /* Initialize the integer and float register pointers. */
3257 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3259 /* The struct_return pointer occupies the first parameter-passing reg. */
3263 fprintf_unfiltered (gdb_stdlog
,
3264 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3265 argreg
, paddr_nz (struct_addr
));
3266 write_register (argreg
++, struct_addr
);
3267 stack_offset
+= MIPS_STACK_ARGSIZE
;
3270 /* Now load as many as possible of the first arguments into
3271 registers, and push the rest onto the stack. Loop thru args
3272 from first to last. */
3273 for (argnum
= 0; argnum
< nargs
; argnum
++)
3276 char valbuf
[MAX_REGISTER_SIZE
];
3277 struct value
*arg
= args
[argnum
];
3278 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3279 int len
= TYPE_LENGTH (arg_type
);
3280 enum type_code typecode
= TYPE_CODE (arg_type
);
3283 fprintf_unfiltered (gdb_stdlog
,
3284 "mips_o32_push_dummy_call: %d len=%d type=%d",
3285 argnum
+ 1, len
, (int) typecode
);
3287 val
= (char *) VALUE_CONTENTS (arg
);
3289 /* 32-bit ABIs always start floating point arguments in an
3290 even-numbered floating point register. Round the FP register
3291 up before the check to see if there are any FP registers
3292 left. O32/O64 targets also pass the FP in the integer
3293 registers so also round up normal registers. */
3294 if (!FP_REGISTER_DOUBLE
3295 && fp_register_arg_p (typecode
, arg_type
))
3297 if ((float_argreg
& 1))
3301 /* Floating point arguments passed in registers have to be
3302 treated specially. On 32-bit architectures, doubles
3303 are passed in register pairs; the even register gets
3304 the low word, and the odd register gets the high word.
3305 On O32/O64, the first two floating point arguments are
3306 also copied to general registers, because MIPS16 functions
3307 don't use float registers for arguments. This duplication of
3308 arguments in general registers can't hurt non-MIPS16 functions
3309 because those registers are normally skipped. */
3311 if (fp_register_arg_p (typecode
, arg_type
)
3312 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3314 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3316 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3317 unsigned long regval
;
3319 /* Write the low word of the double to the even register(s). */
3320 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3322 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3323 float_argreg
, phex (regval
, 4));
3324 write_register (float_argreg
++, regval
);
3326 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3327 argreg
, phex (regval
, 4));
3328 write_register (argreg
++, regval
);
3330 /* Write the high word of the double to the odd register(s). */
3331 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3333 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3334 float_argreg
, phex (regval
, 4));
3335 write_register (float_argreg
++, regval
);
3338 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3339 argreg
, phex (regval
, 4));
3340 write_register (argreg
++, regval
);
3344 /* This is a floating point value that fits entirely
3345 in a single register. */
3346 /* On 32 bit ABI's the float_argreg is further adjusted
3347 above to ensure that it is even register aligned. */
3348 LONGEST regval
= extract_unsigned_integer (val
, len
);
3350 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3351 float_argreg
, phex (regval
, len
));
3352 write_register (float_argreg
++, regval
);
3353 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3354 registers for each argument. The below is (my
3355 guess) to ensure that the corresponding integer
3356 register has reserved the same space. */
3358 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3359 argreg
, phex (regval
, len
));
3360 write_register (argreg
, regval
);
3361 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3363 /* Reserve space for the FP register. */
3364 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3368 /* Copy the argument to general registers or the stack in
3369 register-sized pieces. Large arguments are split between
3370 registers and stack. */
3371 /* Note: structs whose size is not a multiple of
3372 mips_regsize() are treated specially: Irix cc passes them
3373 in registers where gcc sometimes puts them on the stack.
3374 For maximum compatibility, we will put them in both
3376 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3377 (len
% MIPS_SAVED_REGSIZE
!= 0));
3378 /* Structures should be aligned to eight bytes (even arg registers)
3379 on MIPS_ABI_O32, if their first member has double precision. */
3380 if (MIPS_SAVED_REGSIZE
< 8
3381 && mips_type_needs_double_align (arg_type
))
3386 /* Note: Floating-point values that didn't fit into an FP
3387 register are only written to memory. */
3390 /* Remember if the argument was written to the stack. */
3391 int stack_used_p
= 0;
3393 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3396 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3399 /* Write this portion of the argument to the stack. */
3400 if (argreg
> MIPS_LAST_ARG_REGNUM
3402 || fp_register_arg_p (typecode
, arg_type
))
3404 /* Should shorter than int integer values be
3405 promoted to int before being stored? */
3406 int longword_offset
= 0;
3409 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3411 if (MIPS_STACK_ARGSIZE
== 8 &&
3412 (typecode
== TYPE_CODE_INT
||
3413 typecode
== TYPE_CODE_PTR
||
3414 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3415 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3420 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3421 paddr_nz (stack_offset
));
3422 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3423 paddr_nz (longword_offset
));
3426 addr
= sp
+ stack_offset
+ longword_offset
;
3431 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3433 for (i
= 0; i
< partial_len
; i
++)
3435 fprintf_unfiltered (gdb_stdlog
, "%02x",
3439 write_memory (addr
, val
, partial_len
);
3442 /* Note!!! This is NOT an else clause. Odd sized
3443 structs may go thru BOTH paths. Floating point
3444 arguments will not. */
3445 /* Write this portion of the argument to a general
3446 purpose register. */
3447 if (argreg
<= MIPS_LAST_ARG_REGNUM
3448 && !fp_register_arg_p (typecode
, arg_type
))
3450 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3451 /* Value may need to be sign extended, because
3452 mips_regsize() != MIPS_SAVED_REGSIZE. */
3454 /* A non-floating-point argument being passed in a
3455 general register. If a struct or union, and if
3456 the remaining length is smaller than the register
3457 size, we have to adjust the register value on
3460 It does not seem to be necessary to do the
3461 same for integral types.
3463 Also don't do this adjustment on O64 binaries.
3465 cagney/2001-07-23: gdb/179: Also, GCC, when
3466 outputting LE O32 with sizeof (struct) <
3467 MIPS_SAVED_REGSIZE, generates a left shift as
3468 part of storing the argument in a register a
3469 register (the left shift isn't generated when
3470 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3471 is quite possible that this is GCC contradicting
3472 the LE/O32 ABI, GDB has not been adjusted to
3473 accommodate this. Either someone needs to
3474 demonstrate that the LE/O32 ABI specifies such a
3475 left shift OR this new ABI gets identified as
3476 such and GDB gets tweaked accordingly. */
3478 if (MIPS_SAVED_REGSIZE
< 8
3479 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3480 && partial_len
< MIPS_SAVED_REGSIZE
3481 && (typecode
== TYPE_CODE_STRUCT
||
3482 typecode
== TYPE_CODE_UNION
))
3483 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3487 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3489 phex (regval
, MIPS_SAVED_REGSIZE
));
3490 write_register (argreg
, regval
);
3493 /* Prevent subsequent floating point arguments from
3494 being passed in floating point registers. */
3495 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3501 /* Compute the the offset into the stack at which we
3502 will copy the next parameter.
3504 In older ABIs, the caller reserved space for
3505 registers that contained arguments. This was loosely
3506 refered to as their "home". Consequently, space is
3507 always allocated. */
3509 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3513 fprintf_unfiltered (gdb_stdlog
, "\n");
3516 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3518 /* Return adjusted stack pointer. */
3522 /* O64 version of push_dummy_call. */
3525 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3526 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3527 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3528 CORE_ADDR struct_addr
)
3534 int stack_offset
= 0;
3536 /* For shared libraries, "t9" needs to point at the function
3538 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3540 /* Set the return address register to point to the entry point of
3541 the program, where a breakpoint lies in wait. */
3542 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3544 /* First ensure that the stack and structure return address (if any)
3545 are properly aligned. The stack has to be at least 64-bit
3546 aligned even on 32-bit machines, because doubles must be 64-bit
3547 aligned. For n32 and n64, stack frames need to be 128-bit
3548 aligned, so we round to this widest known alignment. */
3550 sp
= align_down (sp
, 16);
3551 struct_addr
= align_down (struct_addr
, 16);
3553 /* Now make space on the stack for the args. */
3554 for (argnum
= 0; argnum
< nargs
; argnum
++)
3555 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3556 MIPS_STACK_ARGSIZE
);
3557 sp
-= align_up (len
, 16);
3560 fprintf_unfiltered (gdb_stdlog
,
3561 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3562 paddr_nz (sp
), (long) align_up (len
, 16));
3564 /* Initialize the integer and float register pointers. */
3566 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3568 /* The struct_return pointer occupies the first parameter-passing reg. */
3572 fprintf_unfiltered (gdb_stdlog
,
3573 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3574 argreg
, paddr_nz (struct_addr
));
3575 write_register (argreg
++, struct_addr
);
3576 stack_offset
+= MIPS_STACK_ARGSIZE
;
3579 /* Now load as many as possible of the first arguments into
3580 registers, and push the rest onto the stack. Loop thru args
3581 from first to last. */
3582 for (argnum
= 0; argnum
< nargs
; argnum
++)
3585 char valbuf
[MAX_REGISTER_SIZE
];
3586 struct value
*arg
= args
[argnum
];
3587 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3588 int len
= TYPE_LENGTH (arg_type
);
3589 enum type_code typecode
= TYPE_CODE (arg_type
);
3592 fprintf_unfiltered (gdb_stdlog
,
3593 "mips_o64_push_dummy_call: %d len=%d type=%d",
3594 argnum
+ 1, len
, (int) typecode
);
3596 val
= (char *) VALUE_CONTENTS (arg
);
3598 /* 32-bit ABIs always start floating point arguments in an
3599 even-numbered floating point register. Round the FP register
3600 up before the check to see if there are any FP registers
3601 left. O32/O64 targets also pass the FP in the integer
3602 registers so also round up normal registers. */
3603 if (!FP_REGISTER_DOUBLE
3604 && fp_register_arg_p (typecode
, arg_type
))
3606 if ((float_argreg
& 1))
3610 /* Floating point arguments passed in registers have to be
3611 treated specially. On 32-bit architectures, doubles
3612 are passed in register pairs; the even register gets
3613 the low word, and the odd register gets the high word.
3614 On O32/O64, the first two floating point arguments are
3615 also copied to general registers, because MIPS16 functions
3616 don't use float registers for arguments. This duplication of
3617 arguments in general registers can't hurt non-MIPS16 functions
3618 because those registers are normally skipped. */
3620 if (fp_register_arg_p (typecode
, arg_type
)
3621 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3623 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3625 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3626 unsigned long regval
;
3628 /* Write the low word of the double to the even register(s). */
3629 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3631 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3632 float_argreg
, phex (regval
, 4));
3633 write_register (float_argreg
++, regval
);
3635 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3636 argreg
, phex (regval
, 4));
3637 write_register (argreg
++, regval
);
3639 /* Write the high word of the double to the odd register(s). */
3640 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3642 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3643 float_argreg
, phex (regval
, 4));
3644 write_register (float_argreg
++, regval
);
3647 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3648 argreg
, phex (regval
, 4));
3649 write_register (argreg
++, regval
);
3653 /* This is a floating point value that fits entirely
3654 in a single register. */
3655 /* On 32 bit ABI's the float_argreg is further adjusted
3656 above to ensure that it is even register aligned. */
3657 LONGEST regval
= extract_unsigned_integer (val
, len
);
3659 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3660 float_argreg
, phex (regval
, len
));
3661 write_register (float_argreg
++, regval
);
3662 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3663 registers for each argument. The below is (my
3664 guess) to ensure that the corresponding integer
3665 register has reserved the same space. */
3667 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3668 argreg
, phex (regval
, len
));
3669 write_register (argreg
, regval
);
3670 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3672 /* Reserve space for the FP register. */
3673 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3677 /* Copy the argument to general registers or the stack in
3678 register-sized pieces. Large arguments are split between
3679 registers and stack. */
3680 /* Note: structs whose size is not a multiple of
3681 mips_regsize() are treated specially: Irix cc passes them
3682 in registers where gcc sometimes puts them on the stack.
3683 For maximum compatibility, we will put them in both
3685 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3686 (len
% MIPS_SAVED_REGSIZE
!= 0));
3687 /* Structures should be aligned to eight bytes (even arg registers)
3688 on MIPS_ABI_O32, if their first member has double precision. */
3689 if (MIPS_SAVED_REGSIZE
< 8
3690 && mips_type_needs_double_align (arg_type
))
3695 /* Note: Floating-point values that didn't fit into an FP
3696 register are only written to memory. */
3699 /* Remember if the argument was written to the stack. */
3700 int stack_used_p
= 0;
3702 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3705 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3708 /* Write this portion of the argument to the stack. */
3709 if (argreg
> MIPS_LAST_ARG_REGNUM
3711 || fp_register_arg_p (typecode
, arg_type
))
3713 /* Should shorter than int integer values be
3714 promoted to int before being stored? */
3715 int longword_offset
= 0;
3718 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3720 if (MIPS_STACK_ARGSIZE
== 8 &&
3721 (typecode
== TYPE_CODE_INT
||
3722 typecode
== TYPE_CODE_PTR
||
3723 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3724 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3729 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3730 paddr_nz (stack_offset
));
3731 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3732 paddr_nz (longword_offset
));
3735 addr
= sp
+ stack_offset
+ longword_offset
;
3740 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3742 for (i
= 0; i
< partial_len
; i
++)
3744 fprintf_unfiltered (gdb_stdlog
, "%02x",
3748 write_memory (addr
, val
, partial_len
);
3751 /* Note!!! This is NOT an else clause. Odd sized
3752 structs may go thru BOTH paths. Floating point
3753 arguments will not. */
3754 /* Write this portion of the argument to a general
3755 purpose register. */
3756 if (argreg
<= MIPS_LAST_ARG_REGNUM
3757 && !fp_register_arg_p (typecode
, arg_type
))
3759 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3760 /* Value may need to be sign extended, because
3761 mips_regsize() != MIPS_SAVED_REGSIZE. */
3763 /* A non-floating-point argument being passed in a
3764 general register. If a struct or union, and if
3765 the remaining length is smaller than the register
3766 size, we have to adjust the register value on
3769 It does not seem to be necessary to do the
3770 same for integral types.
3772 Also don't do this adjustment on O64 binaries.
3774 cagney/2001-07-23: gdb/179: Also, GCC, when
3775 outputting LE O32 with sizeof (struct) <
3776 MIPS_SAVED_REGSIZE, generates a left shift as
3777 part of storing the argument in a register a
3778 register (the left shift isn't generated when
3779 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3780 is quite possible that this is GCC contradicting
3781 the LE/O32 ABI, GDB has not been adjusted to
3782 accommodate this. Either someone needs to
3783 demonstrate that the LE/O32 ABI specifies such a
3784 left shift OR this new ABI gets identified as
3785 such and GDB gets tweaked accordingly. */
3787 if (MIPS_SAVED_REGSIZE
< 8
3788 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3789 && partial_len
< MIPS_SAVED_REGSIZE
3790 && (typecode
== TYPE_CODE_STRUCT
||
3791 typecode
== TYPE_CODE_UNION
))
3792 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3796 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3798 phex (regval
, MIPS_SAVED_REGSIZE
));
3799 write_register (argreg
, regval
);
3802 /* Prevent subsequent floating point arguments from
3803 being passed in floating point registers. */
3804 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3810 /* Compute the the offset into the stack at which we
3811 will copy the next parameter.
3813 In older ABIs, the caller reserved space for
3814 registers that contained arguments. This was loosely
3815 refered to as their "home". Consequently, space is
3816 always allocated. */
3818 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3822 fprintf_unfiltered (gdb_stdlog
, "\n");
3825 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3827 /* Return adjusted stack pointer. */
3832 mips_pop_frame (void)
3835 struct frame_info
*frame
= get_current_frame ();
3836 CORE_ADDR new_sp
= get_frame_base (frame
);
3837 mips_extra_func_info_t proc_desc
;
3839 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
3841 generic_pop_dummy_frame ();
3842 flush_cached_frames ();
3846 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
3847 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
3848 mips_find_saved_regs (frame
);
3849 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3850 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3851 && deprecated_get_frame_saved_regs (frame
)[regnum
])
3853 /* Floating point registers must not be sign extended,
3854 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3856 if (mips_regnum (current_gdbarch
)->fp0
<= regnum
&& regnum
< mips_regnum (current_gdbarch
)->fp0
+ 32)
3857 write_register (regnum
,
3858 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3859 MIPS_SAVED_REGSIZE
));
3861 write_register (regnum
,
3862 read_memory_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3863 MIPS_SAVED_REGSIZE
));
3866 write_register (SP_REGNUM
, new_sp
);
3867 flush_cached_frames ();
3869 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3871 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3873 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3875 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3877 if (&pi_ptr
->info
== proc_desc
)
3882 error ("Can't locate dummy extra frame info\n");
3884 if (prev_ptr
!= NULL
)
3885 prev_ptr
->next
= pi_ptr
->next
;
3887 linked_proc_desc_table
= pi_ptr
->next
;
3891 write_register (mips_regnum (current_gdbarch
)->hi
,
3892 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3893 MIPS_SAVED_REGSIZE
));
3894 write_register (mips_regnum (current_gdbarch
)->lo
,
3895 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3896 MIPS_SAVED_REGSIZE
));
3897 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3898 write_register (mips_regnum (current_gdbarch
)->fp_control_status
,
3899 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3900 MIPS_SAVED_REGSIZE
));
3904 /* Floating point register management.
3906 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3907 64bit operations, these early MIPS cpus treat fp register pairs
3908 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3909 registers and offer a compatibility mode that emulates the MIPS2 fp
3910 model. When operating in MIPS2 fp compat mode, later cpu's split
3911 double precision floats into two 32-bit chunks and store them in
3912 consecutive fp regs. To display 64-bit floats stored in this
3913 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3914 Throw in user-configurable endianness and you have a real mess.
3916 The way this works is:
3917 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3918 double-precision value will be split across two logical registers.
3919 The lower-numbered logical register will hold the low-order bits,
3920 regardless of the processor's endianness.
3921 - If we are on a 64-bit processor, and we are looking for a
3922 single-precision value, it will be in the low ordered bits
3923 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3924 save slot in memory.
3925 - If we are in 64-bit mode, everything is straightforward.
3927 Note that this code only deals with "live" registers at the top of the
3928 stack. We will attempt to deal with saved registers later, when
3929 the raw/cooked register interface is in place. (We need a general
3930 interface that can deal with dynamic saved register sizes -- fp
3931 regs could be 32 bits wide in one frame and 64 on the frame above
3934 static struct type
*
3935 mips_float_register_type (void)
3937 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3938 return builtin_type_ieee_single_big
;
3940 return builtin_type_ieee_single_little
;
3943 static struct type
*
3944 mips_double_register_type (void)
3946 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3947 return builtin_type_ieee_double_big
;
3949 return builtin_type_ieee_double_little
;
3952 /* Copy a 32-bit single-precision value from the current frame
3953 into rare_buffer. */
3956 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3959 int raw_size
= register_size (current_gdbarch
, regno
);
3960 char *raw_buffer
= alloca (raw_size
);
3962 if (!frame_register_read (frame
, regno
, raw_buffer
))
3963 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3966 /* We have a 64-bit value for this register. Find the low-order
3970 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3975 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3979 memcpy (rare_buffer
, raw_buffer
, 4);
3983 /* Copy a 64-bit double-precision value from the current frame into
3984 rare_buffer. This may include getting half of it from the next
3988 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3991 int raw_size
= register_size (current_gdbarch
, regno
);
3993 if (raw_size
== 8 && !mips2_fp_compat ())
3995 /* We have a 64-bit value for this register, and we should use
3997 if (!frame_register_read (frame
, regno
, rare_buffer
))
3998 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4002 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4003 internal_error (__FILE__
, __LINE__
,
4004 "mips_read_fp_register_double: bad access to "
4005 "odd-numbered FP register");
4007 /* mips_read_fp_register_single will find the correct 32 bits from
4009 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4011 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4012 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4016 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4017 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4023 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4025 { /* do values for FP (float) regs */
4027 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4028 int inv1
, inv2
, namelen
;
4030 raw_buffer
= (char *) alloca (2 * register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
));
4032 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4033 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4036 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4038 /* 4-byte registers: Print hex and floating. Also print even
4039 numbered registers as doubles. */
4040 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4041 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4043 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w', file
);
4045 fprintf_filtered (file
, " flt: ");
4047 fprintf_filtered (file
, " <invalid float> ");
4049 fprintf_filtered (file
, "%-17.9g", flt1
);
4051 if (regnum
% 2 == 0)
4053 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4054 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4057 fprintf_filtered (file
, " dbl: ");
4059 fprintf_filtered (file
, "<invalid double>");
4061 fprintf_filtered (file
, "%-24.17g", doub
);
4066 /* Eight byte registers: print each one as hex, float and double. */
4067 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4068 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4070 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4071 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4074 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g', file
);
4076 fprintf_filtered (file
, " flt: ");
4078 fprintf_filtered (file
, "<invalid float>");
4080 fprintf_filtered (file
, "%-17.9g", flt1
);
4082 fprintf_filtered (file
, " dbl: ");
4084 fprintf_filtered (file
, "<invalid double>");
4086 fprintf_filtered (file
, "%-24.17g", doub
);
4091 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4092 int regnum
, int all
)
4094 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4095 char raw_buffer
[MAX_REGISTER_SIZE
];
4098 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4100 mips_print_fp_register (file
, frame
, regnum
);
4104 /* Get the data in raw format. */
4105 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4107 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4111 fputs_filtered (REGISTER_NAME (regnum
), file
);
4113 /* The problem with printing numeric register names (r26, etc.) is that
4114 the user can't use them on input. Probably the best solution is to
4115 fix it so that either the numeric or the funky (a2, etc.) names
4116 are accepted on input. */
4117 if (regnum
< MIPS_NUMREGS
)
4118 fprintf_filtered (file
, "(r%d): ", regnum
);
4120 fprintf_filtered (file
, ": ");
4122 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4123 offset
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4127 print_scalar_formatted (raw_buffer
+ offset
, gdbarch_register_type (gdbarch
, regnum
),
4131 /* Replacement for generic do_registers_info.
4132 Print regs in pretty columns. */
4135 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4138 fprintf_filtered (file
, " ");
4139 mips_print_fp_register (file
, frame
, regnum
);
4140 fprintf_filtered (file
, "\n");
4145 /* Print a row's worth of GP (int) registers, with name labels above */
4148 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4151 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4152 /* do values for GP (int) regs */
4153 char raw_buffer
[MAX_REGISTER_SIZE
];
4154 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4158 /* For GP registers, we print a separate row of names above the vals */
4159 fprintf_filtered (file
, " ");
4160 for (col
= 0, regnum
= start_regnum
;
4161 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4164 if (*REGISTER_NAME (regnum
) == '\0')
4165 continue; /* unused register */
4166 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4167 break; /* end the row: reached FP register */
4168 fprintf_filtered (file
, mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4169 REGISTER_NAME (regnum
));
4172 /* print the R0 to R31 names */
4173 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4174 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4176 fprintf_filtered (file
, "\n ");
4178 /* now print the values in hex, 4 or 8 to the row */
4179 for (col
= 0, regnum
= start_regnum
;
4180 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4183 if (*REGISTER_NAME (regnum
) == '\0')
4184 continue; /* unused register */
4185 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4186 break; /* end row: reached FP register */
4187 /* OK: get the data in raw format. */
4188 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4189 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4190 /* pad small registers */
4192 byte
< (mips_regsize (current_gdbarch
)
4193 - register_size (current_gdbarch
, regnum
));
4195 printf_filtered (" ");
4196 /* Now print the register value in hex, endian order. */
4197 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4198 for (byte
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4199 byte
< register_size (current_gdbarch
, regnum
);
4201 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4203 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4206 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4207 fprintf_filtered (file
, " ");
4210 if (col
> 0) /* ie. if we actually printed anything... */
4211 fprintf_filtered (file
, "\n");
4216 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4219 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4220 struct frame_info
*frame
, int regnum
, int all
)
4222 if (regnum
!= -1) /* do one specified register */
4224 gdb_assert (regnum
>= NUM_REGS
);
4225 if (*(REGISTER_NAME (regnum
)) == '\0')
4226 error ("Not a valid register for the current processor type");
4228 mips_print_register (file
, frame
, regnum
, 0);
4229 fprintf_filtered (file
, "\n");
4232 /* do all (or most) registers */
4235 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4237 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4239 if (all
) /* true for "INFO ALL-REGISTERS" command */
4240 regnum
= print_fp_register_row (file
, frame
, regnum
);
4242 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4245 regnum
= print_gp_register_row (file
, frame
, regnum
);
4250 /* Is this a branch with a delay slot? */
4252 static int is_delayed (unsigned long);
4255 is_delayed (unsigned long insn
)
4258 for (i
= 0; i
< NUMOPCODES
; ++i
)
4259 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4260 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4262 return (i
< NUMOPCODES
4263 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4264 | INSN_COND_BRANCH_DELAY
4265 | INSN_COND_BRANCH_LIKELY
)));
4269 mips_step_skips_delay (CORE_ADDR pc
)
4271 char buf
[MIPS_INSTLEN
];
4273 /* There is no branch delay slot on MIPS16. */
4274 if (pc_is_mips16 (pc
))
4277 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4278 /* If error reading memory, guess that it is not a delayed branch. */
4280 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4284 /* Given PC at the function's start address, attempt to find the
4285 prologue end using SAL information. Return zero if the skip fails.
4287 A non-optimized prologue traditionally has one SAL for the function
4288 and a second for the function body. A single line function has
4289 them both pointing at the same line.
4291 An optimized prologue is similar but the prologue may contain
4292 instructions (SALs) from the instruction body. Need to skip those
4293 while not getting into the function body.
4295 The functions end point and an increasing SAL line are used as
4296 indicators of the prologue's endpoint.
4298 This code is based on the function refine_prologue_limit (versions
4299 found in both ia64 and ppc). */
4302 skip_prologue_using_sal (CORE_ADDR func_addr
)
4304 struct symtab_and_line prologue_sal
;
4308 /* Get an initial range for the function. */
4309 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
4310 start_pc
+= FUNCTION_START_OFFSET
;
4312 prologue_sal
= find_pc_line (start_pc
, 0);
4313 if (prologue_sal
.line
!= 0)
4315 while (prologue_sal
.end
< end_pc
)
4317 struct symtab_and_line sal
;
4319 sal
= find_pc_line (prologue_sal
.end
, 0);
4322 /* Assume that a consecutive SAL for the same (or larger)
4323 line mark the prologue -> body transition. */
4324 if (sal
.line
>= prologue_sal
.line
)
4326 /* The case in which compiler's optimizer/scheduler has
4327 moved instructions into the prologue. We look ahead in
4328 the function looking for address ranges whose
4329 corresponding line number is less the first one that we
4330 found for the function. This is more conservative then
4331 refine_prologue_limit which scans a large number of SALs
4332 looking for any in the prologue */
4336 return prologue_sal
.end
;
4339 /* Skip the PC past function prologue instructions (32-bit version).
4340 This is a helper function for mips_skip_prologue. */
4343 mips32_skip_prologue (CORE_ADDR pc
)
4347 int seen_sp_adjust
= 0;
4348 int load_immediate_bytes
= 0;
4350 /* Find an upper bound on the prologue. */
4351 end_pc
= skip_prologue_using_sal (pc
);
4353 end_pc
= pc
+ 100; /* Magic. */
4355 /* Skip the typical prologue instructions. These are the stack adjustment
4356 instruction and the instructions that save registers on the stack
4357 or in the gcc frame. */
4358 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4360 unsigned long high_word
;
4362 inst
= mips_fetch_instruction (pc
);
4363 high_word
= (inst
>> 16) & 0xffff;
4365 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4366 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4368 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4369 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4371 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4372 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4373 && (inst
& 0x001F0000)) /* reg != $zero */
4376 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4378 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4380 continue; /* reg != $zero */
4382 /* move $s8,$sp. With different versions of gas this will be either
4383 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4384 Accept any one of these. */
4385 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4388 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4390 else if (high_word
== 0x3c1c) /* lui $gp,n */
4392 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4394 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4395 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4397 /* The following instructions load $at or $t0 with an immediate
4398 value in preparation for a stack adjustment via
4399 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4400 a local variable, so we accept them only before a stack adjustment
4401 instruction was seen. */
4402 else if (!seen_sp_adjust
)
4404 if (high_word
== 0x3c01 || /* lui $at,n */
4405 high_word
== 0x3c08) /* lui $t0,n */
4407 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4410 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4411 high_word
== 0x3508 || /* ori $t0,$t0,n */
4412 high_word
== 0x3401 || /* ori $at,$zero,n */
4413 high_word
== 0x3408) /* ori $t0,$zero,n */
4415 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4425 /* In a frameless function, we might have incorrectly
4426 skipped some load immediate instructions. Undo the skipping
4427 if the load immediate was not followed by a stack adjustment. */
4428 if (load_immediate_bytes
&& !seen_sp_adjust
)
4429 pc
-= load_immediate_bytes
;
4433 /* Skip the PC past function prologue instructions (16-bit version).
4434 This is a helper function for mips_skip_prologue. */
4437 mips16_skip_prologue (CORE_ADDR pc
)
4440 int extend_bytes
= 0;
4441 int prev_extend_bytes
;
4443 /* Table of instructions likely to be found in a function prologue. */
4446 unsigned short inst
;
4447 unsigned short mask
;
4454 , /* addiu $sp,offset */
4458 , /* daddiu $sp,offset */
4462 , /* sw reg,n($sp) */
4466 , /* sd reg,n($sp) */
4470 , /* sw $ra,n($sp) */
4474 , /* sd $ra,n($sp) */
4482 , /* sw $a0-$a3,n($s1) */
4486 , /* move reg,$a0-$a3 */
4490 , /* entry pseudo-op */
4494 , /* addiu $s1,$sp,n */
4497 } /* end of table marker */
4500 /* Find an upper bound on the prologue. */
4501 end_pc
= skip_prologue_using_sal (pc
);
4503 end_pc
= pc
+ 100; /* Magic. */
4505 /* Skip the typical prologue instructions. These are the stack adjustment
4506 instruction and the instructions that save registers on the stack
4507 or in the gcc frame. */
4508 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4510 unsigned short inst
;
4513 inst
= mips_fetch_instruction (pc
);
4515 /* Normally we ignore an extend instruction. However, if it is
4516 not followed by a valid prologue instruction, we must adjust
4517 the pc back over the extend so that it won't be considered
4518 part of the prologue. */
4519 if ((inst
& 0xf800) == 0xf000) /* extend */
4521 extend_bytes
= MIPS16_INSTLEN
;
4524 prev_extend_bytes
= extend_bytes
;
4527 /* Check for other valid prologue instructions besides extend. */
4528 for (i
= 0; table
[i
].mask
!= 0; i
++)
4529 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4531 if (table
[i
].mask
!= 0) /* it was in table? */
4532 continue; /* ignore it */
4536 /* Return the current pc, adjusted backwards by 2 if
4537 the previous instruction was an extend. */
4538 return pc
- prev_extend_bytes
;
4544 /* To skip prologues, I use this predicate. Returns either PC itself
4545 if the code at PC does not look like a function prologue; otherwise
4546 returns an address that (if we're lucky) follows the prologue. If
4547 LENIENT, then we must skip everything which is involved in setting
4548 up the frame (it's OK to skip more, just so long as we don't skip
4549 anything which might clobber the registers which are being saved.
4550 We must skip more in the case where part of the prologue is in the
4551 delay slot of a non-prologue instruction). */
4554 mips_skip_prologue (CORE_ADDR pc
)
4556 /* See if we can determine the end of the prologue via the symbol table.
4557 If so, then return either PC, or the PC after the prologue, whichever
4560 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4562 if (post_prologue_pc
!= 0)
4563 return max (pc
, post_prologue_pc
);
4565 /* Can't determine prologue from the symbol table, need to examine
4568 if (pc_is_mips16 (pc
))
4569 return mips16_skip_prologue (pc
);
4571 return mips32_skip_prologue (pc
);
4574 /* Determine how a return value is stored within the MIPS register
4575 file, given the return type `valtype'. */
4577 struct return_value_word
4586 return_value_location (struct type
*valtype
,
4587 struct return_value_word
*hi
,
4588 struct return_value_word
*lo
)
4590 int len
= TYPE_LENGTH (valtype
);
4592 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4593 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4594 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4596 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4598 /* We need to break a 64bit float in two 32 bit halves and
4599 spread them across a floating-point register pair. */
4600 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4601 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4602 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4603 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8)
4605 hi
->reg_offset
= lo
->reg_offset
;
4606 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
4607 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
4613 /* The floating point value fits in a single floating-point
4615 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4616 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8
4619 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
4630 /* Locate a result possibly spread across two registers. */
4632 lo
->reg
= regnum
+ 0;
4633 hi
->reg
= regnum
+ 1;
4634 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4635 && len
< MIPS_SAVED_REGSIZE
)
4637 /* "un-left-justify" the value in the low register */
4638 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4643 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4644 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4645 && len
< MIPS_SAVED_REGSIZE
* 2
4646 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4647 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4649 /* "un-left-justify" the value spread across two registers. */
4650 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4651 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4653 hi
->len
= len
- lo
->len
;
4657 /* Only perform a partial copy of the second register. */
4660 if (len
> MIPS_SAVED_REGSIZE
)
4662 lo
->len
= MIPS_SAVED_REGSIZE
;
4663 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4671 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4672 && register_size (current_gdbarch
, regnum
) == 8
4673 && MIPS_SAVED_REGSIZE
== 4)
4675 /* Account for the fact that only the least-signficant part
4676 of the register is being used */
4677 lo
->reg_offset
+= 4;
4678 hi
->reg_offset
+= 4;
4681 hi
->buf_offset
= lo
->len
;
4685 /* Given a return value in `regbuf' with a type `valtype', extract and
4686 copy its value into `valbuf'. */
4689 mips_eabi_extract_return_value (struct type
*valtype
,
4693 struct return_value_word lo
;
4694 struct return_value_word hi
;
4695 return_value_location (valtype
, &hi
, &lo
);
4697 memcpy (valbuf
+ lo
.buf_offset
,
4698 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) + lo
.reg_offset
,
4702 memcpy (valbuf
+ hi
.buf_offset
,
4703 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) + hi
.reg_offset
,
4708 mips_o64_extract_return_value (struct type
*valtype
,
4712 struct return_value_word lo
;
4713 struct return_value_word hi
;
4714 return_value_location (valtype
, &hi
, &lo
);
4716 memcpy (valbuf
+ lo
.buf_offset
,
4717 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) + lo
.reg_offset
,
4721 memcpy (valbuf
+ hi
.buf_offset
,
4722 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) + hi
.reg_offset
,
4726 /* Given a return value in `valbuf' with a type `valtype', write it's
4727 value into the appropriate register. */
4730 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4732 char raw_buffer
[MAX_REGISTER_SIZE
];
4733 struct return_value_word lo
;
4734 struct return_value_word hi
;
4735 return_value_location (valtype
, &hi
, &lo
);
4737 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4738 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4739 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4740 register_size (current_gdbarch
, lo
.reg
));
4744 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4745 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4746 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4747 register_size (current_gdbarch
, hi
.reg
));
4752 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4754 char raw_buffer
[MAX_REGISTER_SIZE
];
4755 struct return_value_word lo
;
4756 struct return_value_word hi
;
4757 return_value_location (valtype
, &hi
, &lo
);
4759 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4760 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4761 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4762 register_size (current_gdbarch
, lo
.reg
));
4766 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4767 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4768 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4769 register_size (current_gdbarch
, hi
.reg
));
4773 /* O32 ABI stuff. */
4775 static enum return_value_convention
4776 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4777 struct regcache
*regcache
,
4778 void *readbuf
, const void *writebuf
)
4780 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4782 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4783 || TYPE_CODE (type
)== TYPE_CODE_UNION
4784 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
)
4785 return RETURN_VALUE_STRUCT_CONVENTION
;
4786 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4787 && TYPE_LENGTH (type
) == 4
4788 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4790 /* A single-precision floating-point value. It fits in the
4791 least significant part of FP0. */
4793 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4794 mips_xfer_register (regcache
,
4795 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4797 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4798 return RETURN_VALUE_REGISTER_CONVENTION
;
4800 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4801 && TYPE_LENGTH (type
) == 8
4802 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4804 /* A double-precision floating-point value. The most
4805 significant part goes in FP1, and the least significant in
4808 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4809 switch (TARGET_BYTE_ORDER
)
4811 case BFD_ENDIAN_LITTLE
:
4812 mips_xfer_register (regcache
,
4813 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4814 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4815 mips_xfer_register (regcache
,
4816 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4817 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4819 case BFD_ENDIAN_BIG
:
4820 mips_xfer_register (regcache
,
4821 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4822 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4823 mips_xfer_register (regcache
,
4824 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4825 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4828 internal_error (__FILE__
, __LINE__
, "bad switch");
4830 return RETURN_VALUE_REGISTER_CONVENTION
;
4833 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4834 && TYPE_NFIELDS (type
) <= 2
4835 && TYPE_NFIELDS (type
) >= 1
4836 && ((TYPE_NFIELDS (type
) == 1
4837 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4839 || (TYPE_NFIELDS (type
) == 2
4840 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4842 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4844 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4846 /* A struct that contains one or two floats. Each value is part
4847 in the least significant part of their floating point
4849 bfd_byte reg
[MAX_REGISTER_SIZE
];
4852 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4853 field
< TYPE_NFIELDS (type
);
4854 field
++, regnum
+= 2)
4856 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4859 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4860 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4861 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4862 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4864 return RETURN_VALUE_REGISTER_CONVENTION
;
4868 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4869 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4871 /* A structure or union. Extract the left justified value,
4872 regardless of the byte order. I.e. DO NOT USE
4876 for (offset
= 0, regnum
= V0_REGNUM
;
4877 offset
< TYPE_LENGTH (type
);
4878 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4880 int xfer
= register_size (current_gdbarch
, regnum
);
4881 if (offset
+ xfer
> TYPE_LENGTH (type
))
4882 xfer
= TYPE_LENGTH (type
) - offset
;
4884 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4885 offset
, xfer
, regnum
);
4886 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4887 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4889 return RETURN_VALUE_REGISTER_CONVENTION
;
4894 /* A scalar extract each part but least-significant-byte
4895 justified. o32 thinks registers are 4 byte, regardless of
4896 the ISA. mips_stack_argsize controls this. */
4899 for (offset
= 0, regnum
= V0_REGNUM
;
4900 offset
< TYPE_LENGTH (type
);
4901 offset
+= mips_stack_argsize (), regnum
++)
4903 int xfer
= mips_stack_argsize ();
4905 if (offset
+ xfer
> TYPE_LENGTH (type
))
4906 xfer
= TYPE_LENGTH (type
) - offset
;
4908 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4909 offset
, xfer
, regnum
);
4910 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4911 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4913 return RETURN_VALUE_REGISTER_CONVENTION
;
4917 /* N32/N44 ABI stuff. */
4919 static enum return_value_convention
4920 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
4921 struct type
*type
, struct regcache
*regcache
,
4922 void *readbuf
, const void *writebuf
)
4924 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4925 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4926 || TYPE_CODE (type
)== TYPE_CODE_UNION
4927 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
4928 || TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
)
4929 return RETURN_VALUE_STRUCT_CONVENTION
;
4930 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4931 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4933 /* A floating-point value belongs in the least significant part
4936 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4937 mips_xfer_register (regcache
,
4938 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4940 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4941 return RETURN_VALUE_REGISTER_CONVENTION
;
4943 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4944 && TYPE_NFIELDS (type
) <= 2
4945 && TYPE_NFIELDS (type
) >= 1
4946 && ((TYPE_NFIELDS (type
) == 1
4947 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4949 || (TYPE_NFIELDS (type
) == 2
4950 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4952 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4954 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4956 /* A struct that contains one or two floats. Each value is part
4957 in the least significant part of their floating point
4959 bfd_byte reg
[MAX_REGISTER_SIZE
];
4962 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4963 field
< TYPE_NFIELDS (type
);
4964 field
++, regnum
+= 2)
4966 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4969 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4970 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4971 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4972 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4974 return RETURN_VALUE_REGISTER_CONVENTION
;
4976 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4977 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4979 /* A structure or union. Extract the left justified value,
4980 regardless of the byte order. I.e. DO NOT USE
4984 for (offset
= 0, regnum
= V0_REGNUM
;
4985 offset
< TYPE_LENGTH (type
);
4986 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4988 int xfer
= register_size (current_gdbarch
, regnum
);
4989 if (offset
+ xfer
> TYPE_LENGTH (type
))
4990 xfer
= TYPE_LENGTH (type
) - offset
;
4992 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4993 offset
, xfer
, regnum
);
4994 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4995 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4997 return RETURN_VALUE_REGISTER_CONVENTION
;
5001 /* A scalar extract each part but least-significant-byte
5005 for (offset
= 0, regnum
= V0_REGNUM
;
5006 offset
< TYPE_LENGTH (type
);
5007 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
5009 int xfer
= register_size (current_gdbarch
, regnum
);
5011 if (offset
+ xfer
> TYPE_LENGTH (type
))
5012 xfer
= TYPE_LENGTH (type
) - offset
;
5014 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5015 offset
, xfer
, regnum
);
5016 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5017 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
5019 return RETURN_VALUE_REGISTER_CONVENTION
;
5024 mips_extract_struct_value_address (struct regcache
*regcache
)
5026 /* FIXME: This will only work at random. The caller passes the
5027 struct_return address in V0, but it is not preserved. It may
5028 still be there, or this may be a random value. */
5031 regcache_cooked_read_signed (regcache
, V0_REGNUM
, &val
);
5035 /* Exported procedure: Is PC in the signal trampoline code */
5038 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5040 if (sigtramp_address
== 0)
5042 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5045 /* Root of all "set mips "/"show mips " commands. This will eventually be
5046 used for all MIPS-specific commands. */
5049 show_mips_command (char *args
, int from_tty
)
5051 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5055 set_mips_command (char *args
, int from_tty
)
5057 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5058 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5061 /* Commands to show/set the MIPS FPU type. */
5064 show_mipsfpu_command (char *args
, int from_tty
)
5067 switch (MIPS_FPU_TYPE
)
5069 case MIPS_FPU_SINGLE
:
5070 fpu
= "single-precision";
5072 case MIPS_FPU_DOUBLE
:
5073 fpu
= "double-precision";
5076 fpu
= "absent (none)";
5079 internal_error (__FILE__
, __LINE__
, "bad switch");
5081 if (mips_fpu_type_auto
)
5082 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5085 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5091 set_mipsfpu_command (char *args
, int from_tty
)
5093 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5094 show_mipsfpu_command (args
, from_tty
);
5098 set_mipsfpu_single_command (char *args
, int from_tty
)
5100 mips_fpu_type
= MIPS_FPU_SINGLE
;
5101 mips_fpu_type_auto
= 0;
5102 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
5106 set_mipsfpu_double_command (char *args
, int from_tty
)
5108 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5109 mips_fpu_type_auto
= 0;
5110 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5114 set_mipsfpu_none_command (char *args
, int from_tty
)
5116 mips_fpu_type
= MIPS_FPU_NONE
;
5117 mips_fpu_type_auto
= 0;
5118 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
5122 set_mipsfpu_auto_command (char *args
, int from_tty
)
5124 mips_fpu_type_auto
= 1;
5127 /* Attempt to identify the particular processor model by reading the
5128 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5129 the relevant processor still exists (it dates back to '94) and
5130 secondly this is not the way to do this. The processor type should
5131 be set by forcing an architecture change. */
5134 deprecated_mips_set_processor_regs_hack (void)
5136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5139 prid
= read_register (PRID_REGNUM
);
5141 if ((prid
& ~0xf) == 0x700)
5142 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5145 /* Just like reinit_frame_cache, but with the right arguments to be
5146 callable as an sfunc. */
5149 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5150 struct cmd_list_element
*c
)
5152 reinit_frame_cache ();
5156 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5159 mips_extra_func_info_t proc_desc
;
5161 /* Search for the function containing this address. Set the low bit
5162 of the address when searching, in case we were given an even address
5163 that is the start of a 16-bit function. If we didn't do this,
5164 the search would fail because the symbol table says the function
5165 starts at an odd address, i.e. 1 byte past the given address. */
5166 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5167 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5169 /* Make an attempt to determine if this is a 16-bit function. If
5170 the procedure descriptor exists and the address therein is odd,
5171 it's definitely a 16-bit function. Otherwise, we have to just
5172 guess that if the address passed in is odd, it's 16-bits. */
5173 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5174 disassembler needs to be able to locally determine the ISA, and
5175 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5179 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5180 info
->mach
= bfd_mach_mips16
;
5184 if (pc_is_mips16 (memaddr
))
5185 info
->mach
= bfd_mach_mips16
;
5188 /* Round down the instruction address to the appropriate boundary. */
5189 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5191 /* Set the disassembler options. */
5192 if (tdep
->mips_abi
== MIPS_ABI_N32
5193 || tdep
->mips_abi
== MIPS_ABI_N64
)
5195 /* Set up the disassembler info, so that we get the right
5196 register names from libopcodes. */
5197 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5198 info
->disassembler_options
= "gpr-names=n32";
5200 info
->disassembler_options
= "gpr-names=64";
5201 info
->flavour
= bfd_target_elf_flavour
;
5204 /* This string is not recognized explicitly by the disassembler,
5205 but it tells the disassembler to not try to guess the ABI from
5206 the bfd elf headers, such that, if the user overrides the ABI
5207 of a program linked as NewABI, the disassembly will follow the
5208 register naming conventions specified by the user. */
5209 info
->disassembler_options
= "gpr-names=32";
5211 /* Call the appropriate disassembler based on the target endian-ness. */
5212 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5213 return print_insn_big_mips (memaddr
, info
);
5215 return print_insn_little_mips (memaddr
, info
);
5218 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5219 counter value to determine whether a 16- or 32-bit breakpoint should be
5220 used. It returns a pointer to a string of bytes that encode a breakpoint
5221 instruction, stores the length of the string to *lenptr, and adjusts pc
5222 (if necessary) to point to the actual memory location where the
5223 breakpoint should be inserted. */
5225 static const unsigned char *
5226 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5228 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5230 if (pc_is_mips16 (*pcptr
))
5232 static unsigned char mips16_big_breakpoint
[] = {0xe8, 0xa5};
5233 *pcptr
= unmake_mips16_addr (*pcptr
);
5234 *lenptr
= sizeof (mips16_big_breakpoint
);
5235 return mips16_big_breakpoint
;
5239 /* The IDT board uses an unusual breakpoint value, and
5240 sometimes gets confused when it sees the usual MIPS
5241 breakpoint instruction. */
5242 static unsigned char big_breakpoint
[] = {0, 0x5, 0, 0xd};
5243 static unsigned char pmon_big_breakpoint
[] = {0, 0, 0, 0xd};
5244 static unsigned char idt_big_breakpoint
[] = {0, 0, 0x0a, 0xd};
5246 *lenptr
= sizeof (big_breakpoint
);
5248 if (strcmp (target_shortname
, "mips") == 0)
5249 return idt_big_breakpoint
;
5250 else if (strcmp (target_shortname
, "ddb") == 0
5251 || strcmp (target_shortname
, "pmon") == 0
5252 || strcmp (target_shortname
, "lsi") == 0)
5253 return pmon_big_breakpoint
;
5255 return big_breakpoint
;
5260 if (pc_is_mips16 (*pcptr
))
5262 static unsigned char mips16_little_breakpoint
[] = {0xa5, 0xe8};
5263 *pcptr
= unmake_mips16_addr (*pcptr
);
5264 *lenptr
= sizeof (mips16_little_breakpoint
);
5265 return mips16_little_breakpoint
;
5269 static unsigned char little_breakpoint
[] = {0xd, 0, 0x5, 0};
5270 static unsigned char pmon_little_breakpoint
[] = {0xd, 0, 0, 0};
5271 static unsigned char idt_little_breakpoint
[] = {0xd, 0x0a, 0, 0};
5273 *lenptr
= sizeof (little_breakpoint
);
5275 if (strcmp (target_shortname
, "mips") == 0)
5276 return idt_little_breakpoint
;
5277 else if (strcmp (target_shortname
, "ddb") == 0
5278 || strcmp (target_shortname
, "pmon") == 0
5279 || strcmp (target_shortname
, "lsi") == 0)
5280 return pmon_little_breakpoint
;
5282 return little_breakpoint
;
5287 /* If PC is in a mips16 call or return stub, return the address of the target
5288 PC, which is either the callee or the caller. There are several
5289 cases which must be handled:
5291 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5292 target PC is in $31 ($ra).
5293 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5294 and the target PC is in $2.
5295 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5296 before the jal instruction, this is effectively a call stub
5297 and the the target PC is in $2. Otherwise this is effectively
5298 a return stub and the target PC is in $18.
5300 See the source code for the stubs in gcc/config/mips/mips16.S for
5303 This function implements the SKIP_TRAMPOLINE_CODE macro.
5307 mips_skip_stub (CORE_ADDR pc
)
5310 CORE_ADDR start_addr
;
5312 /* Find the starting address and name of the function containing the PC. */
5313 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5316 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5317 target PC is in $31 ($ra). */
5318 if (strcmp (name
, "__mips16_ret_sf") == 0
5319 || strcmp (name
, "__mips16_ret_df") == 0)
5320 return read_signed_register (RA_REGNUM
);
5322 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5324 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5325 and the target PC is in $2. */
5326 if (name
[19] >= '0' && name
[19] <= '9')
5327 return read_signed_register (2);
5329 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5330 before the jal instruction, this is effectively a call stub
5331 and the the target PC is in $2. Otherwise this is effectively
5332 a return stub and the target PC is in $18. */
5333 else if (name
[19] == 's' || name
[19] == 'd')
5335 if (pc
== start_addr
)
5337 /* Check if the target of the stub is a compiler-generated
5338 stub. Such a stub for a function bar might have a name
5339 like __fn_stub_bar, and might look like this:
5344 la $1,bar (becomes a lui/addiu pair)
5346 So scan down to the lui/addi and extract the target
5347 address from those two instructions. */
5349 CORE_ADDR target_pc
= read_signed_register (2);
5353 /* See if the name of the target function is __fn_stub_*. */
5354 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5356 if (strncmp (name
, "__fn_stub_", 10) != 0
5357 && strcmp (name
, "etext") != 0
5358 && strcmp (name
, "_etext") != 0)
5361 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5362 The limit on the search is arbitrarily set to 20
5363 instructions. FIXME. */
5364 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5366 inst
= mips_fetch_instruction (target_pc
);
5367 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5368 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5369 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5370 return pc
| (inst
& 0xffff); /* low word */
5373 /* Couldn't find the lui/addui pair, so return stub address. */
5377 /* This is the 'return' part of a call stub. The return
5378 address is in $r18. */
5379 return read_signed_register (18);
5382 return 0; /* not a stub */
5386 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5387 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5390 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5392 CORE_ADDR start_addr
;
5394 /* Find the starting address of the function containing the PC. If the
5395 caller didn't give us a name, look it up at the same time. */
5396 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5399 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5401 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5402 if (name
[19] >= '0' && name
[19] <= '9')
5404 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5405 before the jal instruction, this is effectively a call stub. */
5406 else if (name
[19] == 's' || name
[19] == 'd')
5407 return pc
== start_addr
;
5410 return 0; /* not a stub */
5414 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5415 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5418 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5420 CORE_ADDR start_addr
;
5422 /* Find the starting address of the function containing the PC. */
5423 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5426 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5427 if (strcmp (name
, "__mips16_ret_sf") == 0
5428 || strcmp (name
, "__mips16_ret_df") == 0)
5431 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5432 i.e. after the jal instruction, this is effectively a return stub. */
5433 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5434 && (name
[19] == 's' || name
[19] == 'd')
5435 && pc
!= start_addr
)
5438 return 0; /* not a stub */
5442 /* Return non-zero if the PC is in a library helper function that should
5443 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5446 mips_ignore_helper (CORE_ADDR pc
)
5450 /* Find the starting address and name of the function containing the PC. */
5451 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5454 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5455 that we want to ignore. */
5456 return (strcmp (name
, "__mips16_ret_sf") == 0
5457 || strcmp (name
, "__mips16_ret_df") == 0);
5461 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5462 the register stored on the stack (32) is different to its real raw
5463 size (64). The below ensures that registers are fetched from the
5464 stack using their ABI size and then stored into the RAW_BUFFER
5465 using their raw size.
5467 The alternative to adding this function would be to add an ABI
5468 macro - REGISTER_STACK_SIZE(). */
5471 mips_get_saved_register (char *raw_buffer
,
5474 struct frame_info
*frame
,
5476 enum lval_type
*lvalp
)
5479 enum lval_type lvalx
;
5483 /* Always a pseudo. */
5484 gdb_assert (regnum
>= NUM_REGS
);
5486 /* Make certain that all needed parameters are present. */
5491 if (optimizedp
== NULL
)
5492 optimizedp
= &optimizedx
;
5494 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5495 /* The SP_REGNUM is special, its value is stored in saved_regs.
5496 In fact, it is so special that it can even only be fetched
5497 using a raw register number! Once this code as been converted
5498 to frame-unwind the problem goes away. */
5499 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5500 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5501 &realnumx
, raw_buffer
);
5503 /* Get it from the next frame. */
5504 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5505 regnum
, optimizedp
, lvalp
, addrp
,
5506 &realnumx
, raw_buffer
);
5509 /* Immediately after a function call, return the saved pc.
5510 Can't always go through the frames for this because on some machines
5511 the new frame is not set up until the new function executes
5512 some instructions. */
5515 mips_saved_pc_after_call (struct frame_info
*frame
)
5517 return read_signed_register (RA_REGNUM
);
5521 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5522 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5525 mips_stab_reg_to_regnum (int num
)
5528 if (num
>= 0 && num
< 32)
5530 else if (num
>= 38 && num
< 70)
5531 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5533 regnum
= mips_regnum (current_gdbarch
)->hi
;
5535 regnum
= mips_regnum (current_gdbarch
)->lo
;
5537 /* This will hopefully (eventually) provoke a warning. Should
5538 we be calling complaint() here? */
5539 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5540 return NUM_REGS
+ regnum
;
5544 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5545 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5548 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5551 if (num
>= 0 && num
< 32)
5553 else if (num
>= 32 && num
< 64)
5554 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5556 regnum
= mips_regnum (current_gdbarch
)->hi
;
5558 regnum
= mips_regnum (current_gdbarch
)->lo
;
5560 /* This will hopefully (eventually) provoke a warning. Should we
5561 be calling complaint() here? */
5562 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5563 return NUM_REGS
+ regnum
;
5567 mips_register_sim_regno (int regnum
)
5569 /* Only makes sense to supply raw registers. */
5570 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5571 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5572 decide if it is valid. Should instead define a standard sim/gdb
5573 register numbering scheme. */
5574 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5575 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5578 return LEGACY_SIM_REGNO_IGNORE
;
5582 /* Convert an integer into an address. By first converting the value
5583 into a pointer and then extracting it signed, the address is
5584 guarenteed to be correctly sign extended. */
5587 mips_integer_to_address (struct type
*type
, void *buf
)
5589 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5590 LONGEST val
= unpack_long (type
, buf
);
5591 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5592 return extract_signed_integer (tmp
,
5593 TYPE_LENGTH (builtin_type_void_data_ptr
));
5597 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5599 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5600 const char *name
= bfd_get_section_name (abfd
, sect
);
5602 if (*abip
!= MIPS_ABI_UNKNOWN
)
5605 if (strncmp (name
, ".mdebug.", 8) != 0)
5608 if (strcmp (name
, ".mdebug.abi32") == 0)
5609 *abip
= MIPS_ABI_O32
;
5610 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5611 *abip
= MIPS_ABI_N32
;
5612 else if (strcmp (name
, ".mdebug.abi64") == 0)
5613 *abip
= MIPS_ABI_N64
;
5614 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5615 *abip
= MIPS_ABI_O64
;
5616 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5617 *abip
= MIPS_ABI_EABI32
;
5618 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5619 *abip
= MIPS_ABI_EABI64
;
5621 warning ("unsupported ABI %s.", name
+ 8);
5624 static enum mips_abi
5625 global_mips_abi (void)
5629 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5630 if (mips_abi_strings
[i
] == mips_abi_string
)
5631 return (enum mips_abi
) i
;
5633 internal_error (__FILE__
, __LINE__
,
5634 "unknown ABI string");
5637 static struct gdbarch
*
5638 mips_gdbarch_init (struct gdbarch_info info
,
5639 struct gdbarch_list
*arches
)
5641 struct gdbarch
*gdbarch
;
5642 struct gdbarch_tdep
*tdep
;
5644 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5647 /* First of all, extract the elf_flags, if available. */
5648 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5649 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5653 fprintf_unfiltered (gdb_stdlog
,
5654 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5657 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5658 switch ((elf_flags
& EF_MIPS_ABI
))
5660 case E_MIPS_ABI_O32
:
5661 found_abi
= MIPS_ABI_O32
;
5663 case E_MIPS_ABI_O64
:
5664 found_abi
= MIPS_ABI_O64
;
5666 case E_MIPS_ABI_EABI32
:
5667 found_abi
= MIPS_ABI_EABI32
;
5669 case E_MIPS_ABI_EABI64
:
5670 found_abi
= MIPS_ABI_EABI64
;
5673 if ((elf_flags
& EF_MIPS_ABI2
))
5674 found_abi
= MIPS_ABI_N32
;
5676 found_abi
= MIPS_ABI_UNKNOWN
;
5680 /* GCC creates a pseudo-section whose name describes the ABI. */
5681 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5682 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5684 /* If we have no usefu BFD information, use the ABI from the last
5685 MIPS architecture (if there is one). */
5686 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5687 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5689 /* Try the architecture for any hint of the correct ABI. */
5690 if (found_abi
== MIPS_ABI_UNKNOWN
5691 && info
.bfd_arch_info
!= NULL
5692 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5694 switch (info
.bfd_arch_info
->mach
)
5696 case bfd_mach_mips3900
:
5697 found_abi
= MIPS_ABI_EABI32
;
5699 case bfd_mach_mips4100
:
5700 case bfd_mach_mips5000
:
5701 found_abi
= MIPS_ABI_EABI64
;
5703 case bfd_mach_mips8000
:
5704 case bfd_mach_mips10000
:
5705 /* On Irix, ELF64 executables use the N64 ABI. The
5706 pseudo-sections which describe the ABI aren't present
5707 on IRIX. (Even for executables created by gcc.) */
5708 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5709 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5710 found_abi
= MIPS_ABI_N64
;
5712 found_abi
= MIPS_ABI_N32
;
5718 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5721 /* What has the user specified from the command line? */
5722 wanted_abi
= global_mips_abi ();
5724 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5727 /* Now that we have found what the ABI for this binary would be,
5728 check whether the user is overriding it. */
5729 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5730 mips_abi
= wanted_abi
;
5731 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5732 mips_abi
= found_abi
;
5734 mips_abi
= MIPS_ABI_O32
;
5736 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5739 /* Also used when doing an architecture lookup. */
5741 fprintf_unfiltered (gdb_stdlog
,
5742 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5743 mips64_transfers_32bit_regs_p
);
5745 /* try to find a pre-existing architecture */
5746 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5748 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5750 /* MIPS needs to be pedantic about which ABI the object is
5752 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5754 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5756 /* Need to be pedantic about which register virtual size is
5758 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5759 != mips64_transfers_32bit_regs_p
)
5761 return arches
->gdbarch
;
5764 /* Need a new architecture. Fill in a target specific vector. */
5765 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5766 gdbarch
= gdbarch_alloc (&info
, tdep
);
5767 tdep
->elf_flags
= elf_flags
;
5768 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5769 tdep
->found_abi
= found_abi
;
5770 tdep
->mips_abi
= mips_abi
;
5772 /* Initially set everything according to the default ABI/ISA. */
5773 set_gdbarch_short_bit (gdbarch
, 16);
5774 set_gdbarch_int_bit (gdbarch
, 32);
5775 set_gdbarch_float_bit (gdbarch
, 32);
5776 set_gdbarch_double_bit (gdbarch
, 64);
5777 set_gdbarch_long_double_bit (gdbarch
, 64);
5778 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5779 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5780 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5782 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5783 mips_elf_make_msymbol_special
);
5785 /* Fill in the OS dependant register numbers and names. */
5787 const char **reg_names
;
5788 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5789 struct mips_regnum
);
5790 if (info
.osabi
== GDB_OSABI_IRIX
)
5795 regnum
->badvaddr
= 66;
5798 regnum
->fp_control_status
= 69;
5799 regnum
->fp_implementation_revision
= 70;
5801 reg_names
= mips_irix_reg_names
;
5805 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5806 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5807 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5808 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5809 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5810 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5811 regnum
->fp_control_status
= 70;
5812 regnum
->fp_implementation_revision
= 71;
5814 if (info
.bfd_arch_info
!= NULL
5815 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5816 reg_names
= mips_tx39_reg_names
;
5818 reg_names
= mips_generic_reg_names
;
5820 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5821 replaced by read_pc? */
5822 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5823 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5824 set_gdbarch_num_regs (gdbarch
, num_regs
);
5825 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5826 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5827 tdep
->mips_processor_reg_names
= reg_names
;
5828 tdep
->regnum
= regnum
;
5834 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5835 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5836 tdep
->mips_default_saved_regsize
= 4;
5837 tdep
->mips_default_stack_argsize
= 4;
5838 tdep
->mips_fp_register_double
= 0;
5839 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5840 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5841 tdep
->default_mask_address_p
= 0;
5842 set_gdbarch_long_bit (gdbarch
, 32);
5843 set_gdbarch_ptr_bit (gdbarch
, 32);
5844 set_gdbarch_long_long_bit (gdbarch
, 64);
5845 set_gdbarch_deprecated_reg_struct_has_addr
5846 (gdbarch
, mips_o32_reg_struct_has_addr
);
5849 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5850 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o64_store_return_value
);
5851 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5852 tdep
->mips_default_saved_regsize
= 8;
5853 tdep
->mips_default_stack_argsize
= 8;
5854 tdep
->mips_fp_register_double
= 1;
5855 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5856 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5857 tdep
->default_mask_address_p
= 0;
5858 set_gdbarch_long_bit (gdbarch
, 32);
5859 set_gdbarch_ptr_bit (gdbarch
, 32);
5860 set_gdbarch_long_long_bit (gdbarch
, 64);
5861 set_gdbarch_deprecated_reg_struct_has_addr
5862 (gdbarch
, mips_o32_reg_struct_has_addr
);
5863 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
5865 case MIPS_ABI_EABI32
:
5866 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5867 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5868 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5869 tdep
->mips_default_saved_regsize
= 4;
5870 tdep
->mips_default_stack_argsize
= 4;
5871 tdep
->mips_fp_register_double
= 0;
5872 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5873 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5874 tdep
->default_mask_address_p
= 0;
5875 set_gdbarch_long_bit (gdbarch
, 32);
5876 set_gdbarch_ptr_bit (gdbarch
, 32);
5877 set_gdbarch_long_long_bit (gdbarch
, 64);
5878 set_gdbarch_deprecated_reg_struct_has_addr
5879 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5880 set_gdbarch_use_struct_convention (gdbarch
,
5881 mips_eabi_use_struct_convention
);
5883 case MIPS_ABI_EABI64
:
5884 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5885 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5886 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5887 tdep
->mips_default_saved_regsize
= 8;
5888 tdep
->mips_default_stack_argsize
= 8;
5889 tdep
->mips_fp_register_double
= 1;
5890 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5891 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5892 tdep
->default_mask_address_p
= 0;
5893 set_gdbarch_long_bit (gdbarch
, 64);
5894 set_gdbarch_ptr_bit (gdbarch
, 64);
5895 set_gdbarch_long_long_bit (gdbarch
, 64);
5896 set_gdbarch_deprecated_reg_struct_has_addr
5897 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5898 set_gdbarch_use_struct_convention (gdbarch
,
5899 mips_eabi_use_struct_convention
);
5902 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5903 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5904 tdep
->mips_default_saved_regsize
= 8;
5905 tdep
->mips_default_stack_argsize
= 8;
5906 tdep
->mips_fp_register_double
= 1;
5907 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5908 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5909 tdep
->default_mask_address_p
= 0;
5910 set_gdbarch_long_bit (gdbarch
, 32);
5911 set_gdbarch_ptr_bit (gdbarch
, 32);
5912 set_gdbarch_long_long_bit (gdbarch
, 64);
5913 set_gdbarch_deprecated_reg_struct_has_addr
5914 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5917 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5918 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5919 tdep
->mips_default_saved_regsize
= 8;
5920 tdep
->mips_default_stack_argsize
= 8;
5921 tdep
->mips_fp_register_double
= 1;
5922 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5923 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5924 tdep
->default_mask_address_p
= 0;
5925 set_gdbarch_long_bit (gdbarch
, 64);
5926 set_gdbarch_ptr_bit (gdbarch
, 64);
5927 set_gdbarch_long_long_bit (gdbarch
, 64);
5928 set_gdbarch_deprecated_reg_struct_has_addr
5929 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5932 internal_error (__FILE__
, __LINE__
,
5933 "unknown ABI in switch");
5936 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5937 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5940 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5941 flag in object files because to do so would make it impossible to
5942 link with libraries compiled without "-gp32". This is
5943 unnecessarily restrictive.
5945 We could solve this problem by adding "-gp32" multilibs to gcc,
5946 but to set this flag before gcc is built with such multilibs will
5947 break too many systems.''
5949 But even more unhelpfully, the default linker output target for
5950 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5951 for 64-bit programs - you need to change the ABI to change this,
5952 and not all gcc targets support that currently. Therefore using
5953 this flag to detect 32-bit mode would do the wrong thing given
5954 the current gcc - it would make GDB treat these 64-bit programs
5955 as 32-bit programs by default. */
5957 /* enable/disable the MIPS FPU */
5958 if (!mips_fpu_type_auto
)
5959 tdep
->mips_fpu_type
= mips_fpu_type
;
5960 else if (info
.bfd_arch_info
!= NULL
5961 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5962 switch (info
.bfd_arch_info
->mach
)
5964 case bfd_mach_mips3900
:
5965 case bfd_mach_mips4100
:
5966 case bfd_mach_mips4111
:
5967 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
5969 case bfd_mach_mips4650
:
5970 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
5973 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5977 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5979 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5980 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
5981 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
5982 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5984 /* Add/remove bits from an address. The MIPS needs be careful to
5985 ensure that all 32 bit addresses are sign extended to 64 bits. */
5986 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5988 /* There's a mess in stack frame creation. See comments in
5989 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
5990 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
5992 /* Map debug register numbers onto internal register numbers. */
5993 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5994 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5995 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5996 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5997 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5999 /* Initialize a frame */
6000 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
, mips_find_saved_regs
);
6001 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
6003 /* MIPS version of CALL_DUMMY */
6005 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6006 replaced by a command, and all targets will default to on stack
6007 (regardless of the stack's execute status). */
6008 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6009 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6010 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6011 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
6013 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6014 set_gdbarch_frameless_function_invocation (gdbarch
,
6015 generic_frameless_function_invocation_not
);
6016 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6017 set_gdbarch_frame_args_skip (gdbarch
, 0);
6019 set_gdbarch_deprecated_get_saved_register (gdbarch
, mips_get_saved_register
);
6021 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6022 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6023 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
6025 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6026 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
6028 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6029 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6030 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6032 set_gdbarch_function_start_offset (gdbarch
, 0);
6034 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6036 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6037 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6039 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6041 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6042 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6043 need to all be folded into the target vector. Since they are
6044 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6045 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6047 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6049 /* Hook in OS ABI-specific overrides, if they have been registered. */
6050 gdbarch_init_osabi (info
, gdbarch
);
6052 set_gdbarch_extract_struct_value_address (gdbarch
,
6053 mips_extract_struct_value_address
);
6055 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6057 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6058 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6064 mips_abi_update (char *ignore_args
, int from_tty
,
6065 struct cmd_list_element
*c
)
6067 struct gdbarch_info info
;
6069 /* Force the architecture to update, and (if it's a MIPS architecture)
6070 mips_gdbarch_init will take care of the rest. */
6071 gdbarch_info_init (&info
);
6072 gdbarch_update_p (info
);
6075 /* Print out which MIPS ABI is in use. */
6078 show_mips_abi (char *ignore_args
, int from_tty
)
6080 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6082 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6085 enum mips_abi global_abi
= global_mips_abi ();
6086 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6087 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6089 if (global_abi
== MIPS_ABI_UNKNOWN
)
6090 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6092 else if (global_abi
== actual_abi
)
6094 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6098 /* Probably shouldn't happen... */
6100 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6102 mips_abi_strings
[global_abi
]);
6108 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6110 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6114 int ef_mips_32bitmode
;
6115 /* determine the ISA */
6116 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6134 /* determine the size of a pointer */
6135 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6136 fprintf_unfiltered (file
,
6137 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6139 fprintf_unfiltered (file
,
6140 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6142 fprintf_unfiltered (file
,
6143 "mips_dump_tdep: ef_mips_arch = %d\n",
6145 fprintf_unfiltered (file
,
6146 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6148 mips_abi_strings
[tdep
->mips_abi
]);
6149 fprintf_unfiltered (file
,
6150 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6151 mips_mask_address_p (),
6152 tdep
->default_mask_address_p
);
6154 fprintf_unfiltered (file
,
6155 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6156 FP_REGISTER_DOUBLE
);
6157 fprintf_unfiltered (file
,
6158 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6159 MIPS_DEFAULT_FPU_TYPE
,
6160 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6161 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6162 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6164 fprintf_unfiltered (file
,
6165 "mips_dump_tdep: MIPS_EABI = %d\n",
6167 fprintf_unfiltered (file
,
6168 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6170 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6171 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6172 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6174 fprintf_unfiltered (file
,
6175 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6176 MIPS_DEFAULT_SAVED_REGSIZE
);
6177 fprintf_unfiltered (file
,
6178 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6179 FP_REGISTER_DOUBLE
);
6180 fprintf_unfiltered (file
,
6181 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6182 MIPS_DEFAULT_STACK_ARGSIZE
);
6183 fprintf_unfiltered (file
,
6184 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6185 MIPS_STACK_ARGSIZE
);
6186 fprintf_unfiltered (file
,
6187 "mips_dump_tdep: A0_REGNUM = %d\n",
6189 fprintf_unfiltered (file
,
6190 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6191 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6192 fprintf_unfiltered (file
,
6193 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6194 XSTRING (ATTACH_DETACH
));
6195 fprintf_unfiltered (file
,
6196 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6197 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6198 fprintf_unfiltered (file
,
6199 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6200 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6201 fprintf_unfiltered (file
,
6202 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6203 FIRST_EMBED_REGNUM
);
6204 fprintf_unfiltered (file
,
6205 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6206 XSTRING (IGNORE_HELPER_CALL (PC
)));
6207 fprintf_unfiltered (file
,
6208 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6209 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6210 fprintf_unfiltered (file
,
6211 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6212 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6216 #ifdef MACHINE_CPROC_FP_OFFSET
6217 fprintf_unfiltered (file
,
6218 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6219 MACHINE_CPROC_FP_OFFSET
);
6221 #ifdef MACHINE_CPROC_PC_OFFSET
6222 fprintf_unfiltered (file
,
6223 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6224 MACHINE_CPROC_PC_OFFSET
);
6226 #ifdef MACHINE_CPROC_SP_OFFSET
6227 fprintf_unfiltered (file
,
6228 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6229 MACHINE_CPROC_SP_OFFSET
);
6231 fprintf_unfiltered (file
,
6232 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6234 fprintf_unfiltered (file
,
6235 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6236 fprintf_unfiltered (file
,
6237 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6238 fprintf_unfiltered (file
,
6239 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6241 fprintf_unfiltered (file
,
6242 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6243 MIPS_LAST_ARG_REGNUM
,
6244 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6245 fprintf_unfiltered (file
,
6246 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6248 fprintf_unfiltered (file
,
6249 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6250 MIPS_SAVED_REGSIZE
);
6251 fprintf_unfiltered (file
,
6252 "mips_dump_tdep: PRID_REGNUM = %d\n",
6254 fprintf_unfiltered (file
,
6255 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6256 fprintf_unfiltered (file
,
6257 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6258 fprintf_unfiltered (file
,
6259 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6260 fprintf_unfiltered (file
,
6261 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6262 fprintf_unfiltered (file
,
6263 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6264 fprintf_unfiltered (file
,
6265 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6266 fprintf_unfiltered (file
,
6267 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6268 fprintf_unfiltered (file
,
6269 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6270 fprintf_unfiltered (file
,
6271 "mips_dump_tdep: PROC_PC_REG = function?\n");
6272 fprintf_unfiltered (file
,
6273 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6274 fprintf_unfiltered (file
,
6275 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6276 fprintf_unfiltered (file
,
6277 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6278 fprintf_unfiltered (file
,
6279 "mips_dump_tdep: PS_REGNUM = %d\n",
6281 fprintf_unfiltered (file
,
6282 "mips_dump_tdep: RA_REGNUM = %d\n",
6285 fprintf_unfiltered (file
,
6286 "mips_dump_tdep: SAVED_BYTES = %d\n",
6290 fprintf_unfiltered (file
,
6291 "mips_dump_tdep: SAVED_FP = %d\n",
6295 fprintf_unfiltered (file
,
6296 "mips_dump_tdep: SAVED_PC = %d\n",
6299 fprintf_unfiltered (file
,
6300 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6301 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6302 fprintf_unfiltered (file
,
6303 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6304 fprintf_unfiltered (file
,
6305 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6307 fprintf_unfiltered (file
,
6308 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6309 SIGFRAME_FPREGSAVE_OFF
);
6310 fprintf_unfiltered (file
,
6311 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6313 fprintf_unfiltered (file
,
6314 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6315 SIGFRAME_REGSAVE_OFF
);
6316 fprintf_unfiltered (file
,
6317 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6318 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6319 fprintf_unfiltered (file
,
6320 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6321 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6322 fprintf_unfiltered (file
,
6323 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6324 SOFTWARE_SINGLE_STEP_P ());
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6327 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6328 #ifdef STACK_END_ADDR
6329 fprintf_unfiltered (file
,
6330 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6333 fprintf_unfiltered (file
,
6334 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6335 XSTRING (STEP_SKIPS_DELAY (PC
)));
6336 fprintf_unfiltered (file
,
6337 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6338 STEP_SKIPS_DELAY_P
);
6339 fprintf_unfiltered (file
,
6340 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6341 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6342 fprintf_unfiltered (file
,
6343 "mips_dump_tdep: T9_REGNUM = %d\n",
6345 fprintf_unfiltered (file
,
6346 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6347 fprintf_unfiltered (file
,
6348 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6349 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6350 fprintf_unfiltered (file
,
6351 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6352 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6354 fprintf_unfiltered (file
,
6355 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6356 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6359 fprintf_unfiltered (file
,
6360 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6363 #ifdef TRACE_FLAVOR_SIZE
6364 fprintf_unfiltered (file
,
6365 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6369 fprintf_unfiltered (file
,
6370 "mips_dump_tdep: TRACE_SET # %s\n",
6371 XSTRING (TRACE_SET (X
,STATE
)));
6373 #ifdef UNUSED_REGNUM
6374 fprintf_unfiltered (file
,
6375 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6378 fprintf_unfiltered (file
,
6379 "mips_dump_tdep: V0_REGNUM = %d\n",
6381 fprintf_unfiltered (file
,
6382 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6383 (long) VM_MIN_ADDRESS
);
6384 fprintf_unfiltered (file
,
6385 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6387 fprintf_unfiltered (file
,
6388 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6392 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6395 _initialize_mips_tdep (void)
6397 static struct cmd_list_element
*mipsfpulist
= NULL
;
6398 struct cmd_list_element
*c
;
6400 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6401 if (MIPS_ABI_LAST
+ 1
6402 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6403 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6405 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6407 /* Add root prefix command for all "set mips"/"show mips" commands */
6408 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6409 "Various MIPS specific commands.",
6410 &setmipscmdlist
, "set mips ", 0, &setlist
);
6412 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6413 "Various MIPS specific commands.",
6414 &showmipscmdlist
, "show mips ", 0, &showlist
);
6416 /* Allow the user to override the saved register size. */
6417 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6420 &mips_saved_regsize_string
, "\
6421 Set size of general purpose registers saved on the stack.\n\
6422 This option can be set to one of:\n\
6423 32 - Force GDB to treat saved GP registers as 32-bit\n\
6424 64 - Force GDB to treat saved GP registers as 64-bit\n\
6425 auto - Allow GDB to use the target's default setting or autodetect the\n\
6426 saved GP register size from information contained in the executable.\n\
6431 /* Allow the user to override the argument stack size. */
6432 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6435 &mips_stack_argsize_string
, "\
6436 Set the amount of stack space reserved for each argument.\n\
6437 This option can be set to one of:\n\
6438 32 - Force GDB to allocate 32-bit chunks per argument\n\
6439 64 - Force GDB to allocate 64-bit chunks per argument\n\
6440 auto - Allow GDB to determine the correct setting from the current\n\
6441 target and executable (default)",
6445 /* Allow the user to override the ABI. */
6446 c
= add_set_enum_cmd
6447 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6448 "Set the ABI used by this program.\n"
6449 "This option can be set to one of:\n"
6450 " auto - the default ABI associated with the current binary\n"
6458 set_cmd_sfunc (c
, mips_abi_update
);
6459 add_cmd ("abi", class_obscure
, show_mips_abi
,
6460 "Show ABI in use by MIPS target", &showmipscmdlist
);
6462 /* Let the user turn off floating point and set the fence post for
6463 heuristic_proc_start. */
6465 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6466 "Set use of MIPS floating-point coprocessor.",
6467 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6468 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6469 "Select single-precision MIPS floating-point coprocessor.",
6471 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6472 "Select double-precision MIPS floating-point coprocessor.",
6474 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6475 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6476 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6477 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6478 "Select no MIPS floating-point coprocessor.",
6480 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6481 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6482 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6483 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6484 "Select MIPS floating-point coprocessor automatically.",
6486 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6487 "Show current use of MIPS floating-point coprocessor target.",
6490 /* We really would like to have both "0" and "unlimited" work, but
6491 command.c doesn't deal with that. So make it a var_zinteger
6492 because the user can always use "999999" or some such for unlimited. */
6493 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6494 (char *) &heuristic_fence_post
,
6496 Set the distance searched for the start of a function.\n\
6497 If you are debugging a stripped executable, GDB needs to search through the\n\
6498 program for the start of a function. This command sets the distance of the\n\
6499 search. The only need to set it is when debugging a stripped executable.",
6501 /* We need to throw away the frame cache when we set this, since it
6502 might change our ability to get backtraces. */
6503 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6504 add_show_from_set (c
, &showlist
);
6506 /* Allow the user to control whether the upper bits of 64-bit
6507 addresses should be zeroed. */
6508 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6509 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6510 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6511 allow GDB to determine the correct value.\n", "\
6512 Show zeroing of upper 32 bits of 64-bit addresses.",
6513 NULL
, show_mask_address
,
6514 &setmipscmdlist
, &showmipscmdlist
);
6516 /* Allow the user to control the size of 32 bit registers within the
6517 raw remote packet. */
6518 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6519 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6520 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6521 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6522 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6523 64 bits for others. Use \"off\" to disable compatibility mode", "\
6524 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6525 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6526 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6527 64 bits for others. Use \"off\" to disable compatibility mode",
6528 set_mips64_transfers_32bit_regs
, NULL
,
6529 &setlist
, &showlist
);
6531 /* Debug this files internals. */
6532 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6533 &mips_debug
, "Set mips debugging.\n\
6534 When non-zero, mips specific debugging is enabled.", &setdebuglist
),