1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
51 #include "floatformat.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
77 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
78 #define ST0_FR (1 << 26)
80 /* The sizes of floating point registers. */
84 MIPS_FPU_SINGLE_REGSIZE
= 4,
85 MIPS_FPU_DOUBLE_REGSIZE
= 8
94 static const char *mips_abi_string
;
96 static const char *const mips_abi_strings
[] = {
107 /* For backwards compatibility we default to MIPS16. This flag is
108 overridden as soon as unambiguous ELF file flags tell us the
109 compressed ISA encoding used. */
110 static const char mips_compression_mips16
[] = "mips16";
111 static const char mips_compression_micromips
[] = "micromips";
112 static const char *const mips_compression_strings
[] =
114 mips_compression_mips16
,
115 mips_compression_micromips
,
119 static const char *mips_compression_string
= mips_compression_mips16
;
121 /* The standard register names, and all the valid aliases for them. */
122 struct register_alias
128 /* Aliases for o32 and most other ABIs. */
129 const struct register_alias mips_o32_aliases
[] = {
136 /* Aliases for n32 and n64. */
137 const struct register_alias mips_n32_n64_aliases
[] = {
144 /* Aliases for ABI-independent registers. */
145 const struct register_alias mips_register_aliases
[] = {
146 /* The architecture manuals specify these ABI-independent names for
148 #define R(n) { "r" #n, n }
149 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
150 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
151 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
152 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 /* k0 and k1 are sometimes called these instead (for "kernel
160 /* This is the traditional GDB name for the CP0 status register. */
161 { "sr", MIPS_PS_REGNUM
},
163 /* This is the traditional GDB name for the CP0 BadVAddr register. */
164 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
166 /* This is the traditional GDB name for the FCSR. */
167 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
170 const struct register_alias mips_numeric_register_aliases
[] = {
171 #define R(n) { #n, n }
172 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
173 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
174 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
175 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
179 #ifndef MIPS_DEFAULT_FPU_TYPE
180 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
182 static int mips_fpu_type_auto
= 1;
183 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
185 static unsigned int mips_debug
= 0;
187 /* Properties (for struct target_desc) describing the g/G packet
189 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
190 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
192 struct target_desc
*mips_tdesc_gp32
;
193 struct target_desc
*mips_tdesc_gp64
;
195 const struct mips_regnum
*
196 mips_regnum (struct gdbarch
*gdbarch
)
198 return gdbarch_tdep (gdbarch
)->regnum
;
202 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
204 return mips_regnum (gdbarch
)->fp0
+ 12;
207 /* Return 1 if REGNUM refers to a floating-point general register, raw
208 or cooked. Otherwise return 0. */
211 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
213 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
215 return (rawnum
>= mips_regnum (gdbarch
)->fp0
216 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
219 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
221 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
223 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
224 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
226 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
227 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
229 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
231 /* Return the MIPS ABI associated with GDBARCH. */
233 mips_abi (struct gdbarch
*gdbarch
)
235 return gdbarch_tdep (gdbarch
)->mips_abi
;
239 mips_isa_regsize (struct gdbarch
*gdbarch
)
241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
243 /* If we know how big the registers are, use that size. */
244 if (tdep
->register_size_valid_p
)
245 return tdep
->register_size
;
247 /* Fall back to the previous behavior. */
248 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
249 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
252 /* Return the currently configured (or set) saved register size. */
255 mips_abi_regsize (struct gdbarch
*gdbarch
)
257 switch (mips_abi (gdbarch
))
259 case MIPS_ABI_EABI32
:
265 case MIPS_ABI_EABI64
:
267 case MIPS_ABI_UNKNOWN
:
270 internal_error (__FILE__
, __LINE__
, _("bad switch"));
274 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
275 are some functions to handle addresses associated with compressed
276 code including but not limited to testing, setting, or clearing
277 bit 0 of such addresses. */
279 /* Return one iff compressed code is the MIPS16 instruction set. */
282 is_mips16_isa (struct gdbarch
*gdbarch
)
284 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
287 /* Return one iff compressed code is the microMIPS instruction set. */
290 is_micromips_isa (struct gdbarch
*gdbarch
)
292 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
295 /* Return one iff ADDR denotes compressed code. */
298 is_compact_addr (CORE_ADDR addr
)
303 /* Return one iff ADDR denotes standard ISA code. */
306 is_mips_addr (CORE_ADDR addr
)
308 return !is_compact_addr (addr
);
311 /* Return one iff ADDR denotes MIPS16 code. */
314 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
316 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
319 /* Return one iff ADDR denotes microMIPS code. */
322 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
324 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
327 /* Strip the ISA (compression) bit off from ADDR. */
330 unmake_compact_addr (CORE_ADDR addr
)
332 return ((addr
) & ~(CORE_ADDR
) 1);
335 /* Add the ISA (compression) bit to ADDR. */
338 make_compact_addr (CORE_ADDR addr
)
340 return ((addr
) | (CORE_ADDR
) 1);
343 /* Extern version of unmake_compact_addr; we use a separate function
344 so that unmake_compact_addr can be inlined throughout this file. */
347 mips_unmake_compact_addr (CORE_ADDR addr
)
349 return unmake_compact_addr (addr
);
352 /* Functions for setting and testing a bit in a minimal symbol that
353 marks it as MIPS16 or microMIPS function. The MSB of the minimal
354 symbol's "info" field is used for this purpose.
356 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
357 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
358 one of the "special" bits in a minimal symbol to mark it accordingly.
359 The test checks an ELF-private flag that is valid for true function
360 symbols only; for synthetic symbols such as for PLT stubs that have
361 no ELF-private part at all the MIPS BFD backend arranges for this
362 information to be carried in the asymbol's udata field instead.
364 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
365 in a minimal symbol. */
368 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
370 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
371 unsigned char st_other
;
373 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
374 st_other
= elfsym
->internal_elf_sym
.st_other
;
375 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
376 st_other
= sym
->udata
.i
;
380 if (ELF_ST_IS_MICROMIPS (st_other
))
382 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
383 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
385 else if (ELF_ST_IS_MIPS16 (st_other
))
387 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
388 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
392 /* Return one iff MSYM refers to standard ISA code. */
395 msymbol_is_mips (struct minimal_symbol
*msym
)
397 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
398 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
401 /* Return one iff MSYM refers to MIPS16 code. */
404 msymbol_is_mips16 (struct minimal_symbol
*msym
)
406 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
409 /* Return one iff MSYM refers to microMIPS code. */
412 msymbol_is_micromips (struct minimal_symbol
*msym
)
414 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
417 /* Set the ISA bit in the main symbol too, complementing the corresponding
418 minimal symbol setting and reflecting the run-time value of the symbol.
419 The need for comes from the ISA bit having been cleared as code in
420 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
421 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
422 of symbols referring to compressed code different in GDB to the values
423 used by actual code. That in turn makes them evaluate incorrectly in
424 expressions, producing results different to what the same expressions
425 yield when compiled into the program being debugged. */
428 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
430 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
432 /* We are in symbol reading so it is OK to cast away constness. */
433 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
434 CORE_ADDR compact_block_start
;
435 struct bound_minimal_symbol msym
;
437 compact_block_start
= BLOCK_START (block
) | 1;
438 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
439 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
441 BLOCK_START (block
) = compact_block_start
;
446 /* XFER a value from the big/little/left end of the register.
447 Depending on the size of the value it might occupy the entire
448 register or just part of it. Make an allowance for this, aligning
449 things accordingly. */
452 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
453 int reg_num
, int length
,
454 enum bfd_endian endian
, gdb_byte
*in
,
455 const gdb_byte
*out
, int buf_offset
)
459 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
460 /* Need to transfer the left or right part of the register, based on
461 the targets byte order. */
465 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
467 case BFD_ENDIAN_LITTLE
:
470 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
474 internal_error (__FILE__
, __LINE__
, _("bad switch"));
477 fprintf_unfiltered (gdb_stderr
,
478 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
479 reg_num
, reg_offset
, buf_offset
, length
);
480 if (mips_debug
&& out
!= NULL
)
483 fprintf_unfiltered (gdb_stdlog
, "out ");
484 for (i
= 0; i
< length
; i
++)
485 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
488 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
491 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
493 if (mips_debug
&& in
!= NULL
)
496 fprintf_unfiltered (gdb_stdlog
, "in ");
497 for (i
= 0; i
< length
; i
++)
498 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
501 fprintf_unfiltered (gdb_stdlog
, "\n");
504 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
505 compatiblity mode. A return value of 1 means that we have
506 physical 64-bit registers, but should treat them as 32-bit registers. */
509 mips2_fp_compat (struct frame_info
*frame
)
511 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
512 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
514 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
518 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
519 in all the places we deal with FP registers. PR gdb/413. */
520 /* Otherwise check the FR bit in the status register - it controls
521 the FP compatiblity mode. If it is clear we are in compatibility
523 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
530 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
532 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
534 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
536 /* The list of available "set mips " and "show mips " commands. */
538 static struct cmd_list_element
*setmipscmdlist
= NULL
;
539 static struct cmd_list_element
*showmipscmdlist
= NULL
;
541 /* Integer registers 0 thru 31 are handled explicitly by
542 mips_register_name(). Processor specific registers 32 and above
543 are listed in the following tables. */
546 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
550 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
551 "sr", "lo", "hi", "bad", "cause", "pc",
552 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
553 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
554 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
555 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
559 /* Names of IDT R3041 registers. */
561 static const char *mips_r3041_reg_names
[] = {
562 "sr", "lo", "hi", "bad", "cause", "pc",
563 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
564 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
565 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
566 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
567 "fsr", "fir", "", /*"fp" */ "",
568 "", "", "bus", "ccfg", "", "", "", "",
569 "", "", "port", "cmp", "", "", "epc", "prid",
572 /* Names of tx39 registers. */
574 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
575 "sr", "lo", "hi", "bad", "cause", "pc",
576 "", "", "", "", "", "", "", "",
577 "", "", "", "", "", "", "", "",
578 "", "", "", "", "", "", "", "",
579 "", "", "", "", "", "", "", "",
581 "", "", "", "", "", "", "", "",
582 "", "", "config", "cache", "debug", "depc", "epc",
585 /* Names of IRIX registers. */
586 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
587 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
588 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
589 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
590 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
591 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
594 /* Names of registers with Linux kernels. */
595 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
596 "sr", "lo", "hi", "bad", "cause", "pc",
597 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
598 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
599 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
600 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
605 /* Return the name of the register corresponding to REGNO. */
607 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
609 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
610 /* GPR names for all ABIs other than n32/n64. */
611 static char *mips_gpr_names
[] = {
612 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
613 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
614 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
615 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
618 /* GPR names for n32 and n64 ABIs. */
619 static char *mips_n32_n64_gpr_names
[] = {
620 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
621 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
622 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
623 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
626 enum mips_abi abi
= mips_abi (gdbarch
);
628 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
629 but then don't make the raw register names visible. This (upper)
630 range of user visible register numbers are the pseudo-registers.
632 This approach was adopted accommodate the following scenario:
633 It is possible to debug a 64-bit device using a 32-bit
634 programming model. In such instances, the raw registers are
635 configured to be 64-bits wide, while the pseudo registers are
636 configured to be 32-bits wide. The registers that the user
637 sees - the pseudo registers - match the users expectations
638 given the programming model being used. */
639 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
640 if (regno
< gdbarch_num_regs (gdbarch
))
643 /* The MIPS integer registers are always mapped from 0 to 31. The
644 names of the registers (which reflects the conventions regarding
645 register use) vary depending on the ABI. */
646 if (0 <= rawnum
&& rawnum
< 32)
648 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
649 return mips_n32_n64_gpr_names
[rawnum
];
651 return mips_gpr_names
[rawnum
];
653 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
654 return tdesc_register_name (gdbarch
, rawnum
);
655 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
657 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
658 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
659 return tdep
->mips_processor_reg_names
[rawnum
- 32];
663 internal_error (__FILE__
, __LINE__
,
664 _("mips_register_name: bad register number %d"), rawnum
);
667 /* Return the groups that a MIPS register can be categorised into. */
670 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
671 struct reggroup
*reggroup
)
676 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
677 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
678 if (reggroup
== all_reggroup
)
680 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
681 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
682 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
683 (gdbarch), as not all architectures are multi-arch. */
684 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
685 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
686 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
688 if (reggroup
== float_reggroup
)
689 return float_p
&& pseudo
;
690 if (reggroup
== vector_reggroup
)
691 return vector_p
&& pseudo
;
692 if (reggroup
== general_reggroup
)
693 return (!vector_p
&& !float_p
) && pseudo
;
694 /* Save the pseudo registers. Need to make certain that any code
695 extracting register values from a saved register cache also uses
697 if (reggroup
== save_reggroup
)
698 return raw_p
&& pseudo
;
699 /* Restore the same pseudo register. */
700 if (reggroup
== restore_reggroup
)
701 return raw_p
&& pseudo
;
705 /* Return the groups that a MIPS register can be categorised into.
706 This version is only used if we have a target description which
707 describes real registers (and their groups). */
710 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
711 struct reggroup
*reggroup
)
713 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
714 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
717 /* Only save, restore, and display the pseudo registers. Need to
718 make certain that any code extracting register values from a
719 saved register cache also uses pseudo registers.
721 Note: saving and restoring the pseudo registers is slightly
722 strange; if we have 64 bits, we should save and restore all
723 64 bits. But this is hard and has little benefit. */
727 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
731 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
734 /* Map the symbol table registers which live in the range [1 *
735 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
736 registers. Take care of alignment and size problems. */
738 static enum register_status
739 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
740 int cookednum
, gdb_byte
*buf
)
742 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
743 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
744 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
745 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
746 return regcache_raw_read (regcache
, rawnum
, buf
);
747 else if (register_size (gdbarch
, rawnum
) >
748 register_size (gdbarch
, cookednum
))
750 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
751 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
754 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
756 enum register_status status
;
758 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
759 if (status
== REG_VALID
)
760 store_signed_integer (buf
, 4, byte_order
, regval
);
765 internal_error (__FILE__
, __LINE__
, _("bad register size"));
769 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
770 struct regcache
*regcache
, int cookednum
,
773 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
774 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
775 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
776 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
777 regcache_raw_write (regcache
, rawnum
, buf
);
778 else if (register_size (gdbarch
, rawnum
) >
779 register_size (gdbarch
, cookednum
))
781 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
782 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
785 /* Sign extend the shortened version of the register prior
786 to placing it in the raw register. This is required for
787 some mips64 parts in order to avoid unpredictable behavior. */
788 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
789 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
790 regcache_raw_write_signed (regcache
, rawnum
, regval
);
794 internal_error (__FILE__
, __LINE__
, _("bad register size"));
798 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
799 struct agent_expr
*ax
, int reg
)
801 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
802 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
803 && reg
< 2 * gdbarch_num_regs (gdbarch
));
805 ax_reg_mask (ax
, rawnum
);
811 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
812 struct agent_expr
*ax
, int reg
)
814 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
815 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
816 && reg
< 2 * gdbarch_num_regs (gdbarch
));
817 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
821 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
823 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
824 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
827 ax_simple (ax
, aop_lsh
);
830 ax_simple (ax
, aop_rsh_signed
);
834 internal_error (__FILE__
, __LINE__
, _("bad register size"));
839 /* Table to translate 3-bit register field to actual register number. */
840 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
842 /* Heuristic_proc_start may hunt through the text section for a long
843 time across a 2400 baud serial line. Allows the user to limit this
846 static int heuristic_fence_post
= 0;
848 /* Number of bytes of storage in the actual machine representation for
849 register N. NOTE: This defines the pseudo register type so need to
850 rebuild the architecture vector. */
852 static int mips64_transfers_32bit_regs_p
= 0;
855 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
856 struct cmd_list_element
*c
)
858 struct gdbarch_info info
;
859 gdbarch_info_init (&info
);
860 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
861 instead of relying on globals. Doing that would let generic code
862 handle the search for this specific architecture. */
863 if (!gdbarch_update_p (info
))
865 mips64_transfers_32bit_regs_p
= 0;
866 error (_("32-bit compatibility mode not supported"));
870 /* Convert to/from a register and the corresponding memory value. */
872 /* This predicate tests for the case of an 8 byte floating point
873 value that is being transferred to or from a pair of floating point
874 registers each of which are (or are considered to be) only 4 bytes
877 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
880 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
881 && register_size (gdbarch
, regnum
) == 4
882 && mips_float_register_p (gdbarch
, regnum
)
883 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
886 /* This predicate tests for the case of a value of less than 8
887 bytes in width that is being transfered to or from an 8 byte
888 general purpose register. */
890 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
893 int num_regs
= gdbarch_num_regs (gdbarch
);
895 return (register_size (gdbarch
, regnum
) == 8
896 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
897 && TYPE_LENGTH (type
) < 8);
901 mips_convert_register_p (struct gdbarch
*gdbarch
,
902 int regnum
, struct type
*type
)
904 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
905 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
909 mips_register_to_value (struct frame_info
*frame
, int regnum
,
910 struct type
*type
, gdb_byte
*to
,
911 int *optimizedp
, int *unavailablep
)
913 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
915 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
917 get_frame_register (frame
, regnum
+ 0, to
+ 4);
918 get_frame_register (frame
, regnum
+ 1, to
+ 0);
920 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
921 optimizedp
, unavailablep
))
924 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
925 optimizedp
, unavailablep
))
927 *optimizedp
= *unavailablep
= 0;
930 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
932 int len
= TYPE_LENGTH (type
);
935 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
936 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
937 optimizedp
, unavailablep
))
940 *optimizedp
= *unavailablep
= 0;
945 internal_error (__FILE__
, __LINE__
,
946 _("mips_register_to_value: unrecognized case"));
951 mips_value_to_register (struct frame_info
*frame
, int regnum
,
952 struct type
*type
, const gdb_byte
*from
)
954 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
956 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
958 put_frame_register (frame
, regnum
+ 0, from
+ 4);
959 put_frame_register (frame
, regnum
+ 1, from
+ 0);
961 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
964 int len
= TYPE_LENGTH (type
);
966 /* Sign extend values, irrespective of type, that are stored to
967 a 64-bit general purpose register. (32-bit unsigned values
968 are stored as signed quantities within a 64-bit register.
969 When performing an operation, in compiled code, that combines
970 a 32-bit unsigned value with a signed 64-bit value, a type
971 conversion is first performed that zeroes out the high 32 bits.) */
972 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
975 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
977 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
978 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
979 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
983 if (from
[len
-1] & 0x80)
984 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
986 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
987 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
988 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
993 internal_error (__FILE__
, __LINE__
,
994 _("mips_value_to_register: unrecognized case"));
998 /* Return the GDB type object for the "standard" data type of data in
1001 static struct type
*
1002 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1004 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1005 if (mips_float_register_p (gdbarch
, regnum
))
1007 /* The floating-point registers raw, or cooked, always match
1008 mips_isa_regsize(), and also map 1:1, byte for byte. */
1009 if (mips_isa_regsize (gdbarch
) == 4)
1010 return builtin_type (gdbarch
)->builtin_float
;
1012 return builtin_type (gdbarch
)->builtin_double
;
1014 else if (regnum
< gdbarch_num_regs (gdbarch
))
1016 /* The raw or ISA registers. These are all sized according to
1018 if (mips_isa_regsize (gdbarch
) == 4)
1019 return builtin_type (gdbarch
)->builtin_int32
;
1021 return builtin_type (gdbarch
)->builtin_int64
;
1025 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1027 /* The cooked or ABI registers. These are sized according to
1028 the ABI (with a few complications). */
1029 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1030 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1031 return builtin_type (gdbarch
)->builtin_int32
;
1032 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1033 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1034 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1035 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1036 /* The pseudo/cooked view of the embedded registers is always
1037 32-bit. The raw view is handled below. */
1038 return builtin_type (gdbarch
)->builtin_int32
;
1039 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1040 /* The target, while possibly using a 64-bit register buffer,
1041 is only transfering 32-bits of each integer register.
1042 Reflect this in the cooked/pseudo (ABI) register value. */
1043 return builtin_type (gdbarch
)->builtin_int32
;
1044 else if (mips_abi_regsize (gdbarch
) == 4)
1045 /* The ABI is restricted to 32-bit registers (the ISA could be
1047 return builtin_type (gdbarch
)->builtin_int32
;
1050 return builtin_type (gdbarch
)->builtin_int64
;
1054 /* Return the GDB type for the pseudo register REGNUM, which is the
1055 ABI-level view. This function is only called if there is a target
1056 description which includes registers, so we know precisely the
1057 types of hardware registers. */
1059 static struct type
*
1060 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1062 const int num_regs
= gdbarch_num_regs (gdbarch
);
1063 int rawnum
= regnum
% num_regs
;
1064 struct type
*rawtype
;
1066 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1068 /* Absent registers are still absent. */
1069 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1070 if (TYPE_LENGTH (rawtype
) == 0)
1073 if (mips_float_register_p (gdbarch
, rawnum
))
1074 /* Present the floating point registers however the hardware did;
1075 do not try to convert between FPU layouts. */
1078 /* Use pointer types for registers if we can. For n32 we can not,
1079 since we do not have a 64-bit pointer type. */
1080 if (mips_abi_regsize (gdbarch
)
1081 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1083 if (rawnum
== MIPS_SP_REGNUM
1084 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1085 return builtin_type (gdbarch
)->builtin_data_ptr
;
1086 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1087 return builtin_type (gdbarch
)->builtin_func_ptr
;
1090 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1091 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1092 || rawnum
== mips_regnum (gdbarch
)->lo
1093 || rawnum
== mips_regnum (gdbarch
)->hi
1094 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1095 || rawnum
== mips_regnum (gdbarch
)->cause
1096 || rawnum
== mips_regnum (gdbarch
)->pc
1097 || (mips_regnum (gdbarch
)->dspacc
!= -1
1098 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1099 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1100 return builtin_type (gdbarch
)->builtin_int32
;
1102 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1103 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1104 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1105 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1107 /* The pseudo/cooked view of embedded registers is always
1108 32-bit, even if the target transfers 64-bit values for them.
1109 New targets relying on XML descriptions should only transfer
1110 the necessary 32 bits, but older versions of GDB expected 64,
1111 so allow the target to provide 64 bits without interfering
1112 with the displayed type. */
1113 return builtin_type (gdbarch
)->builtin_int32
;
1116 /* For all other registers, pass through the hardware type. */
1120 /* Should the upper word of 64-bit addresses be zeroed? */
1121 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1124 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1126 switch (mask_address_var
)
1128 case AUTO_BOOLEAN_TRUE
:
1130 case AUTO_BOOLEAN_FALSE
:
1133 case AUTO_BOOLEAN_AUTO
:
1134 return tdep
->default_mask_address_p
;
1136 internal_error (__FILE__
, __LINE__
,
1137 _("mips_mask_address_p: bad switch"));
1143 show_mask_address (struct ui_file
*file
, int from_tty
,
1144 struct cmd_list_element
*c
, const char *value
)
1146 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1148 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1149 switch (mask_address_var
)
1151 case AUTO_BOOLEAN_TRUE
:
1152 printf_filtered ("The 32 bit mips address mask is enabled\n");
1154 case AUTO_BOOLEAN_FALSE
:
1155 printf_filtered ("The 32 bit mips address mask is disabled\n");
1157 case AUTO_BOOLEAN_AUTO
:
1159 ("The 32 bit address mask is set automatically. Currently %s\n",
1160 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1163 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1168 /* Tell if the program counter value in MEMADDR is in a standard ISA
1172 mips_pc_is_mips (CORE_ADDR memaddr
)
1174 struct bound_minimal_symbol sym
;
1176 /* Flags indicating that this is a MIPS16 or microMIPS function is
1177 stored by elfread.c in the high bit of the info field. Use this
1178 to decide if the function is standard MIPS. Otherwise if bit 0
1179 of the address is clear, then this is a standard MIPS function. */
1180 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1182 return msymbol_is_mips (sym
.minsym
);
1184 return is_mips_addr (memaddr
);
1187 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1190 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1192 struct bound_minimal_symbol sym
;
1194 /* A flag indicating that this is a MIPS16 function is stored by
1195 elfread.c in the high bit of the info field. Use this to decide
1196 if the function is MIPS16. Otherwise if bit 0 of the address is
1197 set, then ELF file flags will tell if this is a MIPS16 function. */
1198 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1200 return msymbol_is_mips16 (sym
.minsym
);
1202 return is_mips16_addr (gdbarch
, memaddr
);
1205 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1208 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1210 struct bound_minimal_symbol sym
;
1212 /* A flag indicating that this is a microMIPS function is stored by
1213 elfread.c in the high bit of the info field. Use this to decide
1214 if the function is microMIPS. Otherwise if bit 0 of the address
1215 is set, then ELF file flags will tell if this is a microMIPS
1217 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1219 return msymbol_is_micromips (sym
.minsym
);
1221 return is_micromips_addr (gdbarch
, memaddr
);
1224 /* Tell the ISA type of the function the program counter value in MEMADDR
1227 static enum mips_isa
1228 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1230 struct bound_minimal_symbol sym
;
1232 /* A flag indicating that this is a MIPS16 or a microMIPS function
1233 is stored by elfread.c in the high bit of the info field. Use
1234 this to decide if the function is MIPS16 or microMIPS or normal
1235 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1236 flags will tell if this is a MIPS16 or a microMIPS function. */
1237 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1240 if (msymbol_is_micromips (sym
.minsym
))
1241 return ISA_MICROMIPS
;
1242 else if (msymbol_is_mips16 (sym
.minsym
))
1249 if (is_mips_addr (memaddr
))
1251 else if (is_micromips_addr (gdbarch
, memaddr
))
1252 return ISA_MICROMIPS
;
1258 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1259 The need for comes from the ISA bit having been cleared, making
1260 addresses in FDE, range records, etc. referring to compressed code
1261 different to those in line information, the symbol table and finally
1262 the PC register. That in turn confuses many operations. */
1265 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1267 pc
= unmake_compact_addr (pc
);
1268 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1271 /* Recalculate the line record requested so that the resulting PC has
1272 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1273 this adjustment comes from some records associated with compressed
1274 code having the ISA bit cleared, most notably at function prologue
1275 ends. The ISA bit is in this context retrieved from the minimal
1276 symbol covering the address requested, which in turn has been
1277 constructed from the binary's symbol table rather than DWARF-2
1278 information. The correct setting of the ISA bit is required for
1279 breakpoint addresses to correctly match against the stop PC.
1281 As line entries can specify relative address adjustments we need to
1282 keep track of the absolute value of the last line address recorded
1283 in line information, so that we can calculate the actual address to
1284 apply the ISA bit adjustment to. We use PC for this tracking and
1285 keep the original address there.
1287 As such relative address adjustments can be odd within compressed
1288 code we need to keep track of the last line address with the ISA
1289 bit adjustment applied too, as the original address may or may not
1290 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1291 the adjusted address there.
1293 For relative address adjustments we then use these variables to
1294 calculate the address intended by line information, which will be
1295 PC-relative, and return an updated adjustment carrying ISA bit
1296 information, which will be ADJ_PC-relative. For absolute address
1297 adjustments we just return the same address that we store in ADJ_PC
1300 As the first line entry can be relative to an implied address value
1301 of 0 we need to have the initial address set up that we store in PC
1302 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1303 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1306 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1308 static CORE_ADDR adj_pc
;
1309 static CORE_ADDR pc
;
1312 pc
= rel
? pc
+ addr
: addr
;
1313 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1314 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1319 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1321 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1322 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1323 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1324 static const char mips_str_call_stub
[] = "__call_stub_";
1325 static const char mips_str_fn_stub
[] = "__fn_stub_";
1327 /* This is used as a PIC thunk prefix. */
1329 static const char mips_str_pic
[] = ".pic.";
1331 /* Return non-zero if the PC is inside a call thunk (aka stub or
1332 trampoline) that should be treated as a temporary frame. */
1335 mips_in_frame_stub (CORE_ADDR pc
)
1337 CORE_ADDR start_addr
;
1340 /* Find the starting address of the function containing the PC. */
1341 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1344 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1345 if (strncmp (name
, mips_str_mips16_call_stub
,
1346 strlen (mips_str_mips16_call_stub
)) == 0)
1348 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1349 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1351 /* If the PC is in __fn_stub_*, this is a call stub. */
1352 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1355 return 0; /* Not a stub. */
1358 /* MIPS believes that the PC has a sign extended value. Perhaps the
1359 all registers should be sign extended for simplicity? */
1362 mips_read_pc (struct regcache
*regcache
)
1364 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1367 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1372 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1376 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1377 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1378 intermediate frames. In this case we can get the caller's address
1379 from $ra, or if $ra contains an address within a thunk as well, then
1380 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1381 and thus the caller's address is in $s2. */
1382 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1384 pc
= frame_unwind_register_signed
1385 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1386 if (mips_in_frame_stub (pc
))
1387 pc
= frame_unwind_register_signed
1388 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1394 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1396 return frame_unwind_register_signed
1397 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1400 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1401 dummy frame. The frame ID's base needs to match the TOS value
1402 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1405 static struct frame_id
1406 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1408 return frame_id_build
1409 (get_frame_register_signed (this_frame
,
1410 gdbarch_num_regs (gdbarch
)
1412 get_frame_pc (this_frame
));
1415 /* Implement the "write_pc" gdbarch method. */
1418 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1420 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1422 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1425 /* Fetch and return instruction from the specified location. Handle
1426 MIPS16/microMIPS as appropriate. */
1429 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1430 enum mips_isa isa
, CORE_ADDR addr
, int *statusp
)
1432 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1433 gdb_byte buf
[MIPS_INSN32_SIZE
];
1441 instlen
= MIPS_INSN16_SIZE
;
1442 addr
= unmake_compact_addr (addr
);
1445 instlen
= MIPS_INSN32_SIZE
;
1448 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1451 status
= target_read_memory (addr
, buf
, instlen
);
1452 if (statusp
!= NULL
)
1456 if (statusp
== NULL
)
1457 memory_error (status
, addr
);
1460 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1463 /* These are the fields of 32 bit mips instructions. */
1464 #define mips32_op(x) (x >> 26)
1465 #define itype_op(x) (x >> 26)
1466 #define itype_rs(x) ((x >> 21) & 0x1f)
1467 #define itype_rt(x) ((x >> 16) & 0x1f)
1468 #define itype_immediate(x) (x & 0xffff)
1470 #define jtype_op(x) (x >> 26)
1471 #define jtype_target(x) (x & 0x03ffffff)
1473 #define rtype_op(x) (x >> 26)
1474 #define rtype_rs(x) ((x >> 21) & 0x1f)
1475 #define rtype_rt(x) ((x >> 16) & 0x1f)
1476 #define rtype_rd(x) ((x >> 11) & 0x1f)
1477 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1478 #define rtype_funct(x) (x & 0x3f)
1480 /* MicroMIPS instruction fields. */
1481 #define micromips_op(x) ((x) >> 10)
1483 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1484 bit and the size respectively of the field extracted. */
1485 #define b0s4_imm(x) ((x) & 0xf)
1486 #define b0s5_imm(x) ((x) & 0x1f)
1487 #define b0s5_reg(x) ((x) & 0x1f)
1488 #define b0s7_imm(x) ((x) & 0x7f)
1489 #define b0s10_imm(x) ((x) & 0x3ff)
1490 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1491 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1492 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1493 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1494 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1495 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1496 #define b6s4_op(x) (((x) >> 6) & 0xf)
1497 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1499 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1500 respectively of the field extracted. */
1501 #define b0s6_op(x) ((x) & 0x3f)
1502 #define b0s11_op(x) ((x) & 0x7ff)
1503 #define b0s12_imm(x) ((x) & 0xfff)
1504 #define b0s16_imm(x) ((x) & 0xffff)
1505 #define b0s26_imm(x) ((x) & 0x3ffffff)
1506 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1507 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1508 #define b12s4_op(x) (((x) >> 12) & 0xf)
1510 /* Return the size in bytes of the instruction INSN encoded in the ISA
1514 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1519 if (micromips_op (insn
) == 0x1f)
1520 return 3 * MIPS_INSN16_SIZE
;
1521 else if (((micromips_op (insn
) & 0x4) == 0x4)
1522 || ((micromips_op (insn
) & 0x7) == 0x0))
1523 return 2 * MIPS_INSN16_SIZE
;
1525 return MIPS_INSN16_SIZE
;
1527 if ((insn
& 0xf800) == 0xf000)
1528 return 2 * MIPS_INSN16_SIZE
;
1530 return MIPS_INSN16_SIZE
;
1532 return MIPS_INSN32_SIZE
;
1534 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1538 mips32_relative_offset (ULONGEST inst
)
1540 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1543 /* Determine the address of the next instruction executed after the INST
1544 floating condition branch instruction at PC. COUNT specifies the
1545 number of the floating condition bits tested by the branch. */
1548 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1549 ULONGEST inst
, CORE_ADDR pc
, int count
)
1551 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1552 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1553 int tf
= itype_rt (inst
) & 1;
1554 int mask
= (1 << count
) - 1;
1559 /* No way to handle; it'll most likely trap anyway. */
1562 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1563 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1565 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1566 pc
+= mips32_relative_offset (inst
);
1573 /* Return nonzero if the gdbarch is an Octeon series. */
1576 is_octeon (struct gdbarch
*gdbarch
)
1578 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1580 return (info
->mach
== bfd_mach_mips_octeon
1581 || info
->mach
== bfd_mach_mips_octeonp
1582 || info
->mach
== bfd_mach_mips_octeon2
);
1585 /* Return true if the OP represents the Octeon's BBIT instruction. */
1588 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1590 if (!is_octeon (gdbarch
))
1592 /* BBIT0 is encoded as LWC2: 110 010. */
1593 /* BBIT032 is encoded as LDC2: 110 110. */
1594 /* BBIT1 is encoded as SWC2: 111 010. */
1595 /* BBIT132 is encoded as SDC2: 111 110. */
1596 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1602 /* Determine where to set a single step breakpoint while considering
1603 branch prediction. */
1606 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1608 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1611 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1612 op
= itype_op (inst
);
1613 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1617 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1628 goto greater_branch
;
1633 else if (op
== 17 && itype_rs (inst
) == 8)
1634 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1635 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1636 else if (op
== 17 && itype_rs (inst
) == 9
1637 && (itype_rt (inst
) & 2) == 0)
1638 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1639 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1640 else if (op
== 17 && itype_rs (inst
) == 10
1641 && (itype_rt (inst
) & 2) == 0)
1642 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1643 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1646 /* The new PC will be alternate mode. */
1650 reg
= jtype_target (inst
) << 2;
1651 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1652 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1654 else if (is_octeon_bbit_op (op
, gdbarch
))
1658 branch_if
= op
== 58 || op
== 62;
1659 bit
= itype_rt (inst
);
1661 /* Take into account the *32 instructions. */
1662 if (op
== 54 || op
== 62)
1665 if (((get_frame_register_signed (frame
,
1666 itype_rs (inst
)) >> bit
) & 1)
1668 pc
+= mips32_relative_offset (inst
) + 4;
1670 pc
+= 8; /* After the delay slot. */
1674 pc
+= 4; /* Not a branch, next instruction is easy. */
1677 { /* This gets way messy. */
1679 /* Further subdivide into SPECIAL, REGIMM and other. */
1680 switch (op
& 0x07) /* Extract bits 28,27,26. */
1682 case 0: /* SPECIAL */
1683 op
= rtype_funct (inst
);
1688 /* Set PC to that address. */
1689 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1691 case 12: /* SYSCALL */
1693 struct gdbarch_tdep
*tdep
;
1695 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1696 if (tdep
->syscall_next_pc
!= NULL
)
1697 pc
= tdep
->syscall_next_pc (frame
);
1706 break; /* end SPECIAL */
1707 case 1: /* REGIMM */
1709 op
= itype_rt (inst
); /* branch condition */
1714 case 16: /* BLTZAL */
1715 case 18: /* BLTZALL */
1717 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1718 pc
+= mips32_relative_offset (inst
) + 4;
1720 pc
+= 8; /* after the delay slot */
1724 case 17: /* BGEZAL */
1725 case 19: /* BGEZALL */
1726 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1727 pc
+= mips32_relative_offset (inst
) + 4;
1729 pc
+= 8; /* after the delay slot */
1731 case 0x1c: /* BPOSGE32 */
1732 case 0x1e: /* BPOSGE64 */
1734 if (itype_rs (inst
) == 0)
1736 unsigned int pos
= (op
& 2) ? 64 : 32;
1737 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1740 /* No way to handle; it'll most likely trap anyway. */
1743 if ((get_frame_register_unsigned (frame
,
1744 dspctl
) & 0x7f) >= pos
)
1745 pc
+= mips32_relative_offset (inst
);
1750 /* All of the other instructions in the REGIMM category */
1755 break; /* end REGIMM */
1760 reg
= jtype_target (inst
) << 2;
1761 /* Upper four bits get never changed... */
1762 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1765 case 4: /* BEQ, BEQL */
1767 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1768 get_frame_register_signed (frame
, itype_rt (inst
)))
1769 pc
+= mips32_relative_offset (inst
) + 4;
1773 case 5: /* BNE, BNEL */
1775 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1776 get_frame_register_signed (frame
, itype_rt (inst
)))
1777 pc
+= mips32_relative_offset (inst
) + 4;
1781 case 6: /* BLEZ, BLEZL */
1782 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1783 pc
+= mips32_relative_offset (inst
) + 4;
1789 greater_branch
: /* BGTZ, BGTZL */
1790 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1791 pc
+= mips32_relative_offset (inst
) + 4;
1798 } /* mips32_next_pc */
1800 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1804 micromips_relative_offset7 (ULONGEST insn
)
1806 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1809 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1813 micromips_relative_offset10 (ULONGEST insn
)
1815 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1818 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1822 micromips_relative_offset16 (ULONGEST insn
)
1824 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1827 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1830 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1834 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1835 return mips_insn_size (ISA_MICROMIPS
, insn
);
1838 /* Calculate the address of the next microMIPS instruction to execute
1839 after the INSN coprocessor 1 conditional branch instruction at the
1840 address PC. COUNT denotes the number of coprocessor condition bits
1841 examined by the branch. */
1844 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1845 ULONGEST insn
, CORE_ADDR pc
, int count
)
1847 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1848 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1849 int tf
= b5s5_op (insn
>> 16) & 1;
1850 int mask
= (1 << count
) - 1;
1855 /* No way to handle; it'll most likely trap anyway. */
1858 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1859 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1861 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1862 pc
+= micromips_relative_offset16 (insn
);
1864 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1869 /* Calculate the address of the next microMIPS instruction to execute
1870 after the instruction at the address PC. */
1873 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1875 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1878 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1879 pc
+= MIPS_INSN16_SIZE
;
1880 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1882 /* 48-bit instructions. */
1883 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
1884 /* No branch or jump instructions in this category. */
1885 pc
+= 2 * MIPS_INSN16_SIZE
;
1888 /* 32-bit instructions. */
1889 case 2 * MIPS_INSN16_SIZE
:
1891 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1892 pc
+= MIPS_INSN16_SIZE
;
1893 switch (micromips_op (insn
>> 16))
1895 case 0x00: /* POOL32A: bits 000000 */
1896 if (b0s6_op (insn
) == 0x3c
1897 /* POOL32Axf: bits 000000 ... 111100 */
1898 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1899 /* JALR, JALR.HB: 000000 000x111100 111100 */
1900 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1901 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1904 case 0x10: /* POOL32I: bits 010000 */
1905 switch (b5s5_op (insn
>> 16))
1907 case 0x00: /* BLTZ: bits 010000 00000 */
1908 case 0x01: /* BLTZAL: bits 010000 00001 */
1909 case 0x11: /* BLTZALS: bits 010000 10001 */
1910 if (get_frame_register_signed (frame
,
1911 b0s5_reg (insn
>> 16)) < 0)
1912 pc
+= micromips_relative_offset16 (insn
);
1914 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1917 case 0x02: /* BGEZ: bits 010000 00010 */
1918 case 0x03: /* BGEZAL: bits 010000 00011 */
1919 case 0x13: /* BGEZALS: bits 010000 10011 */
1920 if (get_frame_register_signed (frame
,
1921 b0s5_reg (insn
>> 16)) >= 0)
1922 pc
+= micromips_relative_offset16 (insn
);
1924 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1927 case 0x04: /* BLEZ: bits 010000 00100 */
1928 if (get_frame_register_signed (frame
,
1929 b0s5_reg (insn
>> 16)) <= 0)
1930 pc
+= micromips_relative_offset16 (insn
);
1932 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1935 case 0x05: /* BNEZC: bits 010000 00101 */
1936 if (get_frame_register_signed (frame
,
1937 b0s5_reg (insn
>> 16)) != 0)
1938 pc
+= micromips_relative_offset16 (insn
);
1941 case 0x06: /* BGTZ: bits 010000 00110 */
1942 if (get_frame_register_signed (frame
,
1943 b0s5_reg (insn
>> 16)) > 0)
1944 pc
+= micromips_relative_offset16 (insn
);
1946 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1949 case 0x07: /* BEQZC: bits 010000 00111 */
1950 if (get_frame_register_signed (frame
,
1951 b0s5_reg (insn
>> 16)) == 0)
1952 pc
+= micromips_relative_offset16 (insn
);
1955 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1956 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1957 if (((insn
>> 16) & 0x3) == 0x0)
1958 /* BC2F, BC2T: don't know how to handle these. */
1962 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1963 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1965 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1966 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1969 /* No way to handle; it'll most likely trap anyway. */
1972 if ((get_frame_register_unsigned (frame
,
1973 dspctl
) & 0x7f) >= pos
)
1974 pc
+= micromips_relative_offset16 (insn
);
1976 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1980 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1981 /* BC1ANY2F: bits 010000 11100 xxx01 */
1982 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1983 /* BC1ANY2T: bits 010000 11101 xxx01 */
1984 if (((insn
>> 16) & 0x2) == 0x0)
1985 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1986 ((insn
>> 16) & 0x1) + 1);
1989 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1990 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1991 if (((insn
>> 16) & 0x3) == 0x1)
1992 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1997 case 0x1d: /* JALS: bits 011101 */
1998 case 0x35: /* J: bits 110101 */
1999 case 0x3d: /* JAL: bits 111101 */
2000 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2003 case 0x25: /* BEQ: bits 100101 */
2004 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2005 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2006 pc
+= micromips_relative_offset16 (insn
);
2008 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2011 case 0x2d: /* BNE: bits 101101 */
2012 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2013 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2014 pc
+= micromips_relative_offset16 (insn
);
2016 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2019 case 0x3c: /* JALX: bits 111100 */
2020 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2025 /* 16-bit instructions. */
2026 case MIPS_INSN16_SIZE
:
2027 switch (micromips_op (insn
))
2029 case 0x11: /* POOL16C: bits 010001 */
2030 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2031 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2032 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
2033 else if (b5s5_op (insn
) == 0x18)
2034 /* JRADDIUSP: bits 010001 11000 */
2035 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
2038 case 0x23: /* BEQZ16: bits 100011 */
2040 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2042 if (get_frame_register_signed (frame
, rs
) == 0)
2043 pc
+= micromips_relative_offset7 (insn
);
2045 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2049 case 0x2b: /* BNEZ16: bits 101011 */
2051 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2053 if (get_frame_register_signed (frame
, rs
) != 0)
2054 pc
+= micromips_relative_offset7 (insn
);
2056 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2060 case 0x33: /* B16: bits 110011 */
2061 pc
+= micromips_relative_offset10 (insn
);
2070 /* Decoding the next place to set a breakpoint is irregular for the
2071 mips 16 variant, but fortunately, there fewer instructions. We have
2072 to cope ith extensions for 16 bit instructions and a pair of actual
2073 32 bit instructions. We dont want to set a single step instruction
2074 on the extend instruction either. */
2076 /* Lots of mips16 instruction formats */
2077 /* Predicting jumps requires itype,ritype,i8type
2078 and their extensions extItype,extritype,extI8type. */
2079 enum mips16_inst_fmts
2081 itype
, /* 0 immediate 5,10 */
2082 ritype
, /* 1 5,3,8 */
2083 rrtype
, /* 2 5,3,3,5 */
2084 rritype
, /* 3 5,3,3,5 */
2085 rrrtype
, /* 4 5,3,3,3,2 */
2086 rriatype
, /* 5 5,3,3,1,4 */
2087 shifttype
, /* 6 5,3,3,3,2 */
2088 i8type
, /* 7 5,3,8 */
2089 i8movtype
, /* 8 5,3,3,5 */
2090 i8mov32rtype
, /* 9 5,3,5,3 */
2091 i64type
, /* 10 5,3,8 */
2092 ri64type
, /* 11 5,3,3,5 */
2093 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2094 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2095 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2096 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2097 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2098 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2099 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2100 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2101 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2102 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2104 /* I am heaping all the fields of the formats into one structure and
2105 then, only the fields which are involved in instruction extension. */
2109 unsigned int regx
; /* Function in i8 type. */
2114 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2115 for the bits which make up the immediate extension. */
2118 extended_offset (unsigned int extension
)
2122 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2124 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2126 value
|= extension
& 0x1f; /* Extract 4:0. */
2131 /* Only call this function if you know that this is an extendable
2132 instruction. It won't malfunction, but why make excess remote memory
2133 references? If the immediate operands get sign extended or something,
2134 do it after the extension is performed. */
2135 /* FIXME: Every one of these cases needs to worry about sign extension
2136 when the offset is to be used in relative addressing. */
2139 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2141 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2144 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2145 target_read_memory (pc
, buf
, 2);
2146 return extract_unsigned_integer (buf
, 2, byte_order
);
2150 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2151 unsigned int extension
,
2153 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2158 switch (insn_format
)
2165 value
= extended_offset ((extension
<< 16) | inst
);
2166 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2170 value
= inst
& 0x7ff;
2171 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2180 { /* A register identifier and an offset. */
2181 /* Most of the fields are the same as I type but the
2182 immediate value is of a different length. */
2186 value
= extended_offset ((extension
<< 16) | inst
);
2187 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2191 value
= inst
& 0xff; /* 8 bits */
2192 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2195 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2201 unsigned long value
;
2202 unsigned int nexthalf
;
2203 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2204 value
= value
<< 16;
2205 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2206 /* Low bit still set. */
2214 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2216 upk
->offset
= offset
;
2222 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2223 and having a signed 16-bit OFFSET. */
2226 add_offset_16 (CORE_ADDR pc
, int offset
)
2228 return pc
+ (offset
<< 1) + 2;
2232 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2233 unsigned int extension
, unsigned int insn
)
2235 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2236 int op
= (insn
>> 11);
2239 case 2: /* Branch */
2241 struct upk_mips16 upk
;
2242 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2243 pc
= add_offset_16 (pc
, upk
.offset
);
2246 case 3: /* JAL , JALX - Watch out, these are 32 bit
2249 struct upk_mips16 upk
;
2250 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2251 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2252 if ((insn
>> 10) & 0x01) /* Exchange mode */
2253 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2260 struct upk_mips16 upk
;
2262 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2263 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2265 pc
= add_offset_16 (pc
, upk
.offset
);
2272 struct upk_mips16 upk
;
2274 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2275 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2277 pc
= add_offset_16 (pc
, upk
.offset
);
2282 case 12: /* I8 Formats btez btnez */
2284 struct upk_mips16 upk
;
2286 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2287 /* upk.regx contains the opcode */
2288 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2289 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2290 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2291 pc
= add_offset_16 (pc
, upk
.offset
);
2296 case 29: /* RR Formats JR, JALR, JALR-RA */
2298 struct upk_mips16 upk
;
2299 /* upk.fmt = rrtype; */
2304 upk
.regx
= (insn
>> 8) & 0x07;
2305 upk
.regy
= (insn
>> 5) & 0x07;
2306 if ((upk
.regy
& 1) == 0)
2307 reg
= mips_reg3_to_reg
[upk
.regx
];
2309 reg
= 31; /* Function return instruction. */
2310 pc
= get_frame_register_signed (frame
, reg
);
2317 /* This is an instruction extension. Fetch the real instruction
2318 (which follows the extension) and decode things based on
2322 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2323 fetch_mips_16 (gdbarch
, pc
));
2336 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2338 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2339 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2340 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2343 /* The mips_next_pc function supports single_step when the remote
2344 target monitor or stub is not developed enough to do a single_step.
2345 It works by decoding the current instruction and predicting where a
2346 branch will go. This isn't hard because all the data is available.
2347 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2349 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2351 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2353 if (mips_pc_is_mips16 (gdbarch
, pc
))
2354 return mips16_next_pc (frame
, pc
);
2355 else if (mips_pc_is_micromips (gdbarch
, pc
))
2356 return micromips_next_pc (frame
, pc
);
2358 return mips32_next_pc (frame
, pc
);
2361 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2365 mips16_instruction_is_compact_branch (unsigned short insn
)
2367 switch (insn
& 0xf800)
2370 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2372 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2373 case 0x2800: /* BNEZ */
2374 case 0x2000: /* BEQZ */
2375 case 0x1000: /* B */
2382 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2386 micromips_instruction_is_compact_branch (unsigned short insn
)
2388 switch (micromips_op (insn
))
2390 case 0x11: /* POOL16C: bits 010001 */
2391 return (b5s5_op (insn
) == 0x18
2392 /* JRADDIUSP: bits 010001 11000 */
2393 || b5s5_op (insn
) == 0xd);
2394 /* JRC: bits 010011 01101 */
2395 case 0x10: /* POOL32I: bits 010000 */
2396 return (b5s5_op (insn
) & 0x1d) == 0x5;
2397 /* BEQZC/BNEZC: bits 010000 001x1 */
2403 struct mips_frame_cache
2406 struct trad_frame_saved_reg
*saved_regs
;
2409 /* Set a register's saved stack address in temp_saved_regs. If an
2410 address has already been set for this register, do nothing; this
2411 way we will only recognize the first save of a given register in a
2414 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2415 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2416 Strictly speaking, only the second range is used as it is only second
2417 range (the ABI instead of ISA registers) that comes into play when finding
2418 saved registers in a frame. */
2421 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2422 int regnum
, CORE_ADDR offset
)
2424 if (this_cache
!= NULL
2425 && this_cache
->saved_regs
[regnum
].addr
== -1)
2427 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2429 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2435 /* Fetch the immediate value from a MIPS16 instruction.
2436 If the previous instruction was an EXTEND, use it to extend
2437 the upper bits of the immediate value. This is a helper function
2438 for mips16_scan_prologue. */
2441 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2442 unsigned short inst
, /* current instruction */
2443 int nbits
, /* number of bits in imm field */
2444 int scale
, /* scale factor to be applied to imm */
2445 int is_signed
) /* is the imm field signed? */
2449 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2451 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2452 if (offset
& 0x8000) /* check for negative extend */
2453 offset
= 0 - (0x10000 - (offset
& 0xffff));
2454 return offset
| (inst
& 0x1f);
2458 int max_imm
= 1 << nbits
;
2459 int mask
= max_imm
- 1;
2460 int sign_bit
= max_imm
>> 1;
2462 offset
= inst
& mask
;
2463 if (is_signed
&& (offset
& sign_bit
))
2464 offset
= 0 - (max_imm
- offset
);
2465 return offset
* scale
;
2470 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2471 the associated FRAME_CACHE if not null.
2472 Return the address of the first instruction past the prologue. */
2475 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2476 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2477 struct frame_info
*this_frame
,
2478 struct mips_frame_cache
*this_cache
)
2480 int prev_non_prologue_insn
= 0;
2481 int this_non_prologue_insn
;
2482 int non_prologue_insns
= 0;
2485 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2487 long frame_offset
= 0; /* Size of stack frame. */
2488 long frame_adjust
= 0; /* Offset of FP from SP. */
2489 int frame_reg
= MIPS_SP_REGNUM
;
2490 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2491 unsigned inst
= 0; /* current instruction */
2492 unsigned entry_inst
= 0; /* the entry instruction */
2493 unsigned save_inst
= 0; /* the save instruction */
2494 int prev_delay_slot
= 0;
2498 int extend_bytes
= 0;
2499 int prev_extend_bytes
= 0;
2500 CORE_ADDR end_prologue_addr
;
2502 /* Can be called when there's no process, and hence when there's no
2504 if (this_frame
!= NULL
)
2505 sp
= get_frame_register_signed (this_frame
,
2506 gdbarch_num_regs (gdbarch
)
2511 if (limit_pc
> start_pc
+ 200)
2512 limit_pc
= start_pc
+ 200;
2515 /* Permit at most one non-prologue non-control-transfer instruction
2516 in the middle which may have been reordered by the compiler for
2518 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2520 this_non_prologue_insn
= 0;
2523 /* Save the previous instruction. If it's an EXTEND, we'll extract
2524 the immediate offset extension from it in mips16_get_imm. */
2527 /* Fetch and decode the instruction. */
2528 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2531 /* Normally we ignore extend instructions. However, if it is
2532 not followed by a valid prologue instruction, then this
2533 instruction is not part of the prologue either. We must
2534 remember in this case to adjust the end_prologue_addr back
2536 if ((inst
& 0xf800) == 0xf000) /* extend */
2538 extend_bytes
= MIPS_INSN16_SIZE
;
2542 prev_extend_bytes
= extend_bytes
;
2545 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2546 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2548 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2549 if (offset
< 0) /* Negative stack adjustment? */
2550 frame_offset
-= offset
;
2552 /* Exit loop if a positive stack adjustment is found, which
2553 usually means that the stack cleanup code in the function
2554 epilogue is reached. */
2557 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2559 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2560 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2561 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2563 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2565 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2566 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2567 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2569 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2571 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2572 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2574 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2576 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2577 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2579 else if (inst
== 0x673d) /* move $s1, $sp */
2584 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2586 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2587 frame_addr
= sp
+ offset
;
2589 frame_adjust
= offset
;
2591 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2593 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2594 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2595 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2597 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2599 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2600 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2601 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2603 else if ((inst
& 0xf81f) == 0xe809
2604 && (inst
& 0x700) != 0x700) /* entry */
2605 entry_inst
= inst
; /* Save for later processing. */
2606 else if ((inst
& 0xff80) == 0x6480) /* save */
2608 save_inst
= inst
; /* Save for later processing. */
2609 if (prev_extend_bytes
) /* extend */
2610 save_inst
|= prev_inst
<< 16;
2612 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2614 /* This instruction is part of the prologue, but we don't
2615 need to do anything special to handle it. */
2617 else if (mips16_instruction_has_delay_slot (inst
, 0))
2618 /* JAL/JALR/JALX/JR */
2620 /* The instruction in the delay slot can be a part
2621 of the prologue, so move forward once more. */
2623 if (mips16_instruction_has_delay_slot (inst
, 1))
2626 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2627 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2632 this_non_prologue_insn
= 1;
2635 non_prologue_insns
+= this_non_prologue_insn
;
2637 /* A jump or branch, or enough non-prologue insns seen? If so,
2638 then we must have reached the end of the prologue by now. */
2639 if (prev_delay_slot
|| non_prologue_insns
> 1
2640 || mips16_instruction_is_compact_branch (inst
))
2643 prev_non_prologue_insn
= this_non_prologue_insn
;
2644 prev_delay_slot
= in_delay_slot
;
2645 prev_pc
= cur_pc
- prev_extend_bytes
;
2648 /* The entry instruction is typically the first instruction in a function,
2649 and it stores registers at offsets relative to the value of the old SP
2650 (before the prologue). But the value of the sp parameter to this
2651 function is the new SP (after the prologue has been executed). So we
2652 can't calculate those offsets until we've seen the entire prologue,
2653 and can calculate what the old SP must have been. */
2654 if (entry_inst
!= 0)
2656 int areg_count
= (entry_inst
>> 8) & 7;
2657 int sreg_count
= (entry_inst
>> 6) & 3;
2659 /* The entry instruction always subtracts 32 from the SP. */
2662 /* Now we can calculate what the SP must have been at the
2663 start of the function prologue. */
2666 /* Check if a0-a3 were saved in the caller's argument save area. */
2667 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2669 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2670 offset
+= mips_abi_regsize (gdbarch
);
2673 /* Check if the ra register was pushed on the stack. */
2675 if (entry_inst
& 0x20)
2677 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2678 offset
-= mips_abi_regsize (gdbarch
);
2681 /* Check if the s0 and s1 registers were pushed on the stack. */
2682 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2684 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2685 offset
-= mips_abi_regsize (gdbarch
);
2689 /* The SAVE instruction is similar to ENTRY, except that defined by the
2690 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2691 size of the frame is specified as an immediate field of instruction
2692 and an extended variation exists which lets additional registers and
2693 frame space to be specified. The instruction always treats registers
2694 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2695 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2697 static int args_table
[16] = {
2698 0, 0, 0, 0, 1, 1, 1, 1,
2699 2, 2, 2, 0, 3, 3, 4, -1,
2701 static int astatic_table
[16] = {
2702 0, 1, 2, 3, 0, 1, 2, 3,
2703 0, 1, 2, 4, 0, 1, 0, -1,
2705 int aregs
= (save_inst
>> 16) & 0xf;
2706 int xsregs
= (save_inst
>> 24) & 0x7;
2707 int args
= args_table
[aregs
];
2708 int astatic
= astatic_table
[aregs
];
2713 warning (_("Invalid number of argument registers encoded in SAVE."));
2718 warning (_("Invalid number of static registers encoded in SAVE."));
2722 /* For standard SAVE the frame size of 0 means 128. */
2723 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2724 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2727 frame_offset
+= frame_size
;
2729 /* Now we can calculate what the SP must have been at the
2730 start of the function prologue. */
2733 /* Check if A0-A3 were saved in the caller's argument save area. */
2734 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2736 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2737 offset
+= mips_abi_regsize (gdbarch
);
2742 /* Check if the RA register was pushed on the stack. */
2743 if (save_inst
& 0x40)
2745 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2746 offset
-= mips_abi_regsize (gdbarch
);
2749 /* Check if the S8 register was pushed on the stack. */
2752 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2753 offset
-= mips_abi_regsize (gdbarch
);
2756 /* Check if S2-S7 were pushed on the stack. */
2757 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2759 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2760 offset
-= mips_abi_regsize (gdbarch
);
2763 /* Check if the S1 register was pushed on the stack. */
2764 if (save_inst
& 0x10)
2766 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2767 offset
-= mips_abi_regsize (gdbarch
);
2769 /* Check if the S0 register was pushed on the stack. */
2770 if (save_inst
& 0x20)
2772 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2773 offset
-= mips_abi_regsize (gdbarch
);
2776 /* Check if A0-A3 were pushed on the stack. */
2777 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2779 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2780 offset
-= mips_abi_regsize (gdbarch
);
2784 if (this_cache
!= NULL
)
2787 (get_frame_register_signed (this_frame
,
2788 gdbarch_num_regs (gdbarch
) + frame_reg
)
2789 + frame_offset
- frame_adjust
);
2790 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2791 be able to get rid of the assignment below, evetually. But it's
2792 still needed for now. */
2793 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2794 + mips_regnum (gdbarch
)->pc
]
2795 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2798 /* Set end_prologue_addr to the address of the instruction immediately
2799 after the last one we scanned. Unless the last one looked like a
2800 non-prologue instruction (and we looked ahead), in which case use
2801 its address instead. */
2802 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2803 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2805 return end_prologue_addr
;
2808 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2809 Procedures that use the 32-bit instruction set are handled by the
2810 mips_insn32 unwinder. */
2812 static struct mips_frame_cache
*
2813 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2815 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2816 struct mips_frame_cache
*cache
;
2818 if ((*this_cache
) != NULL
)
2819 return (*this_cache
);
2820 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2821 (*this_cache
) = cache
;
2822 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2824 /* Analyze the function prologue. */
2826 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2827 CORE_ADDR start_addr
;
2829 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2830 if (start_addr
== 0)
2831 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2832 /* We can't analyze the prologue if we couldn't find the begining
2834 if (start_addr
== 0)
2837 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2840 /* gdbarch_sp_regnum contains the value and not the address. */
2841 trad_frame_set_value (cache
->saved_regs
,
2842 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2845 return (*this_cache
);
2849 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2850 struct frame_id
*this_id
)
2852 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2854 /* This marks the outermost frame. */
2855 if (info
->base
== 0)
2857 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2860 static struct value
*
2861 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2862 void **this_cache
, int regnum
)
2864 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2866 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2870 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2871 struct frame_info
*this_frame
, void **this_cache
)
2873 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2874 CORE_ADDR pc
= get_frame_pc (this_frame
);
2875 if (mips_pc_is_mips16 (gdbarch
, pc
))
2880 static const struct frame_unwind mips_insn16_frame_unwind
=
2883 default_frame_unwind_stop_reason
,
2884 mips_insn16_frame_this_id
,
2885 mips_insn16_frame_prev_register
,
2887 mips_insn16_frame_sniffer
2891 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2894 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2899 static const struct frame_base mips_insn16_frame_base
=
2901 &mips_insn16_frame_unwind
,
2902 mips_insn16_frame_base_address
,
2903 mips_insn16_frame_base_address
,
2904 mips_insn16_frame_base_address
2907 static const struct frame_base
*
2908 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2910 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2911 CORE_ADDR pc
= get_frame_pc (this_frame
);
2912 if (mips_pc_is_mips16 (gdbarch
, pc
))
2913 return &mips_insn16_frame_base
;
2918 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2919 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2920 interpreted directly, and then multiplied by 4. */
2923 micromips_decode_imm9 (int imm
)
2925 imm
= (imm
^ 0x100) - 0x100;
2926 if (imm
> -3 && imm
< 2)
2931 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2932 the address of the first instruction past the prologue. */
2935 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2936 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2937 struct frame_info
*this_frame
,
2938 struct mips_frame_cache
*this_cache
)
2940 CORE_ADDR end_prologue_addr
;
2941 int prev_non_prologue_insn
= 0;
2942 int frame_reg
= MIPS_SP_REGNUM
;
2943 int this_non_prologue_insn
;
2944 int non_prologue_insns
= 0;
2945 long frame_offset
= 0; /* Size of stack frame. */
2946 long frame_adjust
= 0; /* Offset of FP from SP. */
2947 CORE_ADDR frame_addr
= 0; /* Value of $30, used as frame pointer. */
2948 int prev_delay_slot
= 0;
2952 ULONGEST insn
; /* current instruction */
2956 long v1_off
= 0; /* The assumption is LUI will replace it. */
2967 /* Can be called when there's no process, and hence when there's no
2969 if (this_frame
!= NULL
)
2970 sp
= get_frame_register_signed (this_frame
,
2971 gdbarch_num_regs (gdbarch
)
2976 if (limit_pc
> start_pc
+ 200)
2977 limit_pc
= start_pc
+ 200;
2980 /* Permit at most one non-prologue non-control-transfer instruction
2981 in the middle which may have been reordered by the compiler for
2983 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2985 this_non_prologue_insn
= 0;
2989 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2990 loc
+= MIPS_INSN16_SIZE
;
2991 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2993 /* 48-bit instructions. */
2994 case 3 * MIPS_INSN16_SIZE
:
2995 /* No prologue instructions in this category. */
2996 this_non_prologue_insn
= 1;
2997 loc
+= 2 * MIPS_INSN16_SIZE
;
3000 /* 32-bit instructions. */
3001 case 2 * MIPS_INSN16_SIZE
:
3003 insn
|= mips_fetch_instruction (gdbarch
,
3004 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3005 loc
+= MIPS_INSN16_SIZE
;
3006 switch (micromips_op (insn
>> 16))
3008 /* Record $sp/$fp adjustment. */
3009 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3010 case 0x0: /* POOL32A: bits 000000 */
3011 case 0x16: /* POOL32S: bits 010110 */
3012 op
= b0s11_op (insn
);
3013 sreg
= b0s5_reg (insn
>> 16);
3014 treg
= b5s5_reg (insn
>> 16);
3015 dreg
= b11s5_reg (insn
);
3017 /* SUBU: bits 000000 00111010000 */
3018 /* DSUBU: bits 010110 00111010000 */
3019 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3021 /* (D)SUBU $sp, $v1 */
3023 else if (op
!= 0x150
3024 /* ADDU: bits 000000 00101010000 */
3025 /* DADDU: bits 010110 00101010000 */
3026 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3027 this_non_prologue_insn
= 1;
3030 case 0x8: /* POOL32B: bits 001000 */
3031 op
= b12s4_op (insn
);
3032 breg
= b0s5_reg (insn
>> 16);
3033 reglist
= sreg
= b5s5_reg (insn
>> 16);
3034 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3035 if ((op
== 0x9 || op
== 0xc)
3036 /* SWP: bits 001000 1001 */
3037 /* SDP: bits 001000 1100 */
3038 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3039 /* S[DW]P reg,offset($sp) */
3041 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3042 set_reg_offset (gdbarch
, this_cache
,
3044 set_reg_offset (gdbarch
, this_cache
,
3045 sreg
+ 1, sp
+ offset
+ s
);
3047 else if ((op
== 0xd || op
== 0xf)
3048 /* SWM: bits 001000 1101 */
3049 /* SDM: bits 001000 1111 */
3050 && breg
== MIPS_SP_REGNUM
3051 /* SWM reglist,offset($sp) */
3052 && ((reglist
>= 1 && reglist
<= 9)
3053 || (reglist
>= 16 && reglist
<= 25)))
3055 int sreglist
= min(reglist
& 0xf, 8);
3057 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3058 for (i
= 0; i
< sreglist
; i
++)
3059 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3060 if ((reglist
& 0xf) > 8)
3061 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3062 if ((reglist
& 0x10) == 0x10)
3063 set_reg_offset (gdbarch
, this_cache
,
3064 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3067 this_non_prologue_insn
= 1;
3070 /* Record $sp/$fp adjustment. */
3071 /* Discard (D)ADDIU $gp used for PIC code. */
3072 case 0xc: /* ADDIU: bits 001100 */
3073 case 0x17: /* DADDIU: bits 010111 */
3074 sreg
= b0s5_reg (insn
>> 16);
3075 dreg
= b5s5_reg (insn
>> 16);
3076 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3077 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3078 /* (D)ADDIU $sp, imm */
3080 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3081 /* (D)ADDIU $fp, $sp, imm */
3083 frame_addr
= sp
+ offset
;
3084 frame_adjust
= offset
;
3087 else if (sreg
!= 28 || dreg
!= 28)
3088 /* (D)ADDIU $gp, imm */
3089 this_non_prologue_insn
= 1;
3092 /* LUI $v1 is used for larger $sp adjustments. */
3093 /* Discard LUI $gp used for PIC code. */
3094 case 0x10: /* POOL32I: bits 010000 */
3095 if (b5s5_op (insn
>> 16) == 0xd
3096 /* LUI: bits 010000 001101 */
3097 && b0s5_reg (insn
>> 16) == 3)
3099 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3100 else if (b5s5_op (insn
>> 16) != 0xd
3101 /* LUI: bits 010000 001101 */
3102 || b0s5_reg (insn
>> 16) != 28)
3104 this_non_prologue_insn
= 1;
3107 /* ORI $v1 is used for larger $sp adjustments. */
3108 case 0x14: /* ORI: bits 010100 */
3109 sreg
= b0s5_reg (insn
>> 16);
3110 dreg
= b5s5_reg (insn
>> 16);
3111 if (sreg
== 3 && dreg
== 3)
3113 v1_off
|= b0s16_imm (insn
);
3115 this_non_prologue_insn
= 1;
3118 case 0x26: /* SWC1: bits 100110 */
3119 case 0x2e: /* SDC1: bits 101110 */
3120 breg
= b0s5_reg (insn
>> 16);
3121 if (breg
!= MIPS_SP_REGNUM
)
3122 /* S[DW]C1 reg,offset($sp) */
3123 this_non_prologue_insn
= 1;
3126 case 0x36: /* SD: bits 110110 */
3127 case 0x3e: /* SW: bits 111110 */
3128 breg
= b0s5_reg (insn
>> 16);
3129 sreg
= b5s5_reg (insn
>> 16);
3130 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3131 if (breg
== MIPS_SP_REGNUM
)
3132 /* S[DW] reg,offset($sp) */
3133 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3135 this_non_prologue_insn
= 1;
3139 /* The instruction in the delay slot can be a part
3140 of the prologue, so move forward once more. */
3141 if (micromips_instruction_has_delay_slot (insn
, 0))
3144 this_non_prologue_insn
= 1;
3150 /* 16-bit instructions. */
3151 case MIPS_INSN16_SIZE
:
3152 switch (micromips_op (insn
))
3154 case 0x3: /* MOVE: bits 000011 */
3155 sreg
= b0s5_reg (insn
);
3156 dreg
= b5s5_reg (insn
);
3157 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3163 else if ((sreg
& 0x1c) != 0x4)
3164 /* MOVE reg, $a0-$a3 */
3165 this_non_prologue_insn
= 1;
3168 case 0x11: /* POOL16C: bits 010001 */
3169 if (b6s4_op (insn
) == 0x5)
3170 /* SWM: bits 010001 0101 */
3172 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3173 reglist
= b4s2_regl (insn
);
3174 for (i
= 0; i
<= reglist
; i
++)
3175 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3176 set_reg_offset (gdbarch
, this_cache
,
3177 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3180 this_non_prologue_insn
= 1;
3183 case 0x13: /* POOL16D: bits 010011 */
3184 if ((insn
& 0x1) == 0x1)
3185 /* ADDIUSP: bits 010011 1 */
3186 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3187 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3188 /* ADDIUS5: bits 010011 0 */
3189 /* ADDIUS5 $sp, imm */
3190 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3192 this_non_prologue_insn
= 1;
3195 case 0x32: /* SWSP: bits 110010 */
3196 offset
= b0s5_imm (insn
) << 2;
3197 sreg
= b5s5_reg (insn
);
3198 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3202 /* The instruction in the delay slot can be a part
3203 of the prologue, so move forward once more. */
3204 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3207 this_non_prologue_insn
= 1;
3213 frame_offset
-= sp_adj
;
3215 non_prologue_insns
+= this_non_prologue_insn
;
3217 /* A jump or branch, enough non-prologue insns seen or positive
3218 stack adjustment? If so, then we must have reached the end
3219 of the prologue by now. */
3220 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3221 || micromips_instruction_is_compact_branch (insn
))
3224 prev_non_prologue_insn
= this_non_prologue_insn
;
3225 prev_delay_slot
= in_delay_slot
;
3229 if (this_cache
!= NULL
)
3232 (get_frame_register_signed (this_frame
,
3233 gdbarch_num_regs (gdbarch
) + frame_reg
)
3234 + frame_offset
- frame_adjust
);
3235 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3236 be able to get rid of the assignment below, evetually. But it's
3237 still needed for now. */
3238 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3239 + mips_regnum (gdbarch
)->pc
]
3240 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3243 /* Set end_prologue_addr to the address of the instruction immediately
3244 after the last one we scanned. Unless the last one looked like a
3245 non-prologue instruction (and we looked ahead), in which case use
3246 its address instead. */
3248 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3250 return end_prologue_addr
;
3253 /* Heuristic unwinder for procedures using microMIPS instructions.
3254 Procedures that use the 32-bit instruction set are handled by the
3255 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3257 static struct mips_frame_cache
*
3258 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3260 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3261 struct mips_frame_cache
*cache
;
3263 if ((*this_cache
) != NULL
)
3264 return (*this_cache
);
3266 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3267 (*this_cache
) = cache
;
3268 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3270 /* Analyze the function prologue. */
3272 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3273 CORE_ADDR start_addr
;
3275 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3276 if (start_addr
== 0)
3277 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3278 /* We can't analyze the prologue if we couldn't find the begining
3280 if (start_addr
== 0)
3283 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3286 /* gdbarch_sp_regnum contains the value and not the address. */
3287 trad_frame_set_value (cache
->saved_regs
,
3288 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3291 return (*this_cache
);
3295 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3296 struct frame_id
*this_id
)
3298 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3300 /* This marks the outermost frame. */
3301 if (info
->base
== 0)
3303 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3306 static struct value
*
3307 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3308 void **this_cache
, int regnum
)
3310 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3312 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3316 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3317 struct frame_info
*this_frame
, void **this_cache
)
3319 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3320 CORE_ADDR pc
= get_frame_pc (this_frame
);
3322 if (mips_pc_is_micromips (gdbarch
, pc
))
3327 static const struct frame_unwind mips_micro_frame_unwind
=
3330 default_frame_unwind_stop_reason
,
3331 mips_micro_frame_this_id
,
3332 mips_micro_frame_prev_register
,
3334 mips_micro_frame_sniffer
3338 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3341 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3346 static const struct frame_base mips_micro_frame_base
=
3348 &mips_micro_frame_unwind
,
3349 mips_micro_frame_base_address
,
3350 mips_micro_frame_base_address
,
3351 mips_micro_frame_base_address
3354 static const struct frame_base
*
3355 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3357 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3358 CORE_ADDR pc
= get_frame_pc (this_frame
);
3360 if (mips_pc_is_micromips (gdbarch
, pc
))
3361 return &mips_micro_frame_base
;
3366 /* Mark all the registers as unset in the saved_regs array
3367 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3370 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3372 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3376 const int num_regs
= gdbarch_num_regs (gdbarch
);
3379 for (i
= 0; i
< num_regs
; i
++)
3381 this_cache
->saved_regs
[i
].addr
= -1;
3386 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3387 the associated FRAME_CACHE if not null.
3388 Return the address of the first instruction past the prologue. */
3391 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3392 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3393 struct frame_info
*this_frame
,
3394 struct mips_frame_cache
*this_cache
)
3396 int prev_non_prologue_insn
;
3397 int this_non_prologue_insn
;
3398 int non_prologue_insns
;
3399 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3401 int prev_delay_slot
;
3406 int frame_reg
= MIPS_SP_REGNUM
;
3408 CORE_ADDR end_prologue_addr
;
3409 int seen_sp_adjust
= 0;
3410 int load_immediate_bytes
= 0;
3412 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3414 /* Can be called when there's no process, and hence when there's no
3416 if (this_frame
!= NULL
)
3417 sp
= get_frame_register_signed (this_frame
,
3418 gdbarch_num_regs (gdbarch
)
3423 if (limit_pc
> start_pc
+ 200)
3424 limit_pc
= start_pc
+ 200;
3427 prev_non_prologue_insn
= 0;
3428 non_prologue_insns
= 0;
3429 prev_delay_slot
= 0;
3432 /* Permit at most one non-prologue non-control-transfer instruction
3433 in the middle which may have been reordered by the compiler for
3436 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3438 unsigned long inst
, high_word
, low_word
;
3441 this_non_prologue_insn
= 0;
3444 /* Fetch the instruction. */
3445 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3448 /* Save some code by pre-extracting some useful fields. */
3449 high_word
= (inst
>> 16) & 0xffff;
3450 low_word
= inst
& 0xffff;
3451 reg
= high_word
& 0x1f;
3453 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3454 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3455 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3457 if (low_word
& 0x8000) /* Negative stack adjustment? */
3458 frame_offset
+= 0x10000 - low_word
;
3460 /* Exit loop if a positive stack adjustment is found, which
3461 usually means that the stack cleanup code in the function
3462 epilogue is reached. */
3466 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3467 && !regsize_is_64_bits
)
3469 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3471 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3472 && regsize_is_64_bits
)
3474 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3475 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3477 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3479 /* Old gcc frame, r30 is virtual frame pointer. */
3480 if ((long) low_word
!= frame_offset
)
3481 frame_addr
= sp
+ low_word
;
3482 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3484 unsigned alloca_adjust
;
3487 frame_addr
= get_frame_register_signed
3488 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3491 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
3492 if (alloca_adjust
> 0)
3494 /* FP > SP + frame_size. This may be because of
3495 an alloca or somethings similar. Fix sp to
3496 "pre-alloca" value, and try again. */
3497 sp
+= alloca_adjust
;
3498 /* Need to reset the status of all registers. Otherwise,
3499 we will hit a guard that prevents the new address
3500 for each register to be recomputed during the second
3502 reset_saved_regs (gdbarch
, this_cache
);
3507 /* move $30,$sp. With different versions of gas this will be either
3508 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3509 Accept any one of these. */
3510 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3512 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3513 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3515 unsigned alloca_adjust
;
3518 frame_addr
= get_frame_register_signed
3519 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3521 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3522 if (alloca_adjust
> 0)
3524 /* FP > SP + frame_size. This may be because of
3525 an alloca or somethings similar. Fix sp to
3526 "pre-alloca" value, and try again. */
3528 /* Need to reset the status of all registers. Otherwise,
3529 we will hit a guard that prevents the new address
3530 for each register to be recomputed during the second
3532 reset_saved_regs (gdbarch
, this_cache
);
3537 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3538 && !regsize_is_64_bits
)
3540 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
3542 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3543 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3544 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3545 || high_word
== 0x3c1c /* lui $gp,n */
3546 || high_word
== 0x279c /* addiu $gp,$gp,n */
3547 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3548 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3551 /* These instructions are part of the prologue, but we don't
3552 need to do anything special to handle them. */
3554 /* The instructions below load $at or $t0 with an immediate
3555 value in preparation for a stack adjustment via
3556 subu $sp,$sp,[$at,$t0]. These instructions could also
3557 initialize a local variable, so we accept them only before
3558 a stack adjustment instruction was seen. */
3559 else if (!seen_sp_adjust
3561 && (high_word
== 0x3c01 /* lui $at,n */
3562 || high_word
== 0x3c08 /* lui $t0,n */
3563 || high_word
== 0x3421 /* ori $at,$at,n */
3564 || high_word
== 0x3508 /* ori $t0,$t0,n */
3565 || high_word
== 0x3401 /* ori $at,$zero,n */
3566 || high_word
== 0x3408 /* ori $t0,$zero,n */
3569 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3571 /* Check for branches and jumps. The instruction in the delay
3572 slot can be a part of the prologue, so move forward once more. */
3573 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3577 /* This instruction is not an instruction typically found
3578 in a prologue, so we must have reached the end of the
3582 this_non_prologue_insn
= 1;
3585 non_prologue_insns
+= this_non_prologue_insn
;
3587 /* A jump or branch, or enough non-prologue insns seen? If so,
3588 then we must have reached the end of the prologue by now. */
3589 if (prev_delay_slot
|| non_prologue_insns
> 1)
3592 prev_non_prologue_insn
= this_non_prologue_insn
;
3593 prev_delay_slot
= in_delay_slot
;
3597 if (this_cache
!= NULL
)
3600 (get_frame_register_signed (this_frame
,
3601 gdbarch_num_regs (gdbarch
) + frame_reg
)
3603 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3604 this assignment below, eventually. But it's still needed
3606 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3607 + mips_regnum (gdbarch
)->pc
]
3608 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3612 /* Set end_prologue_addr to the address of the instruction immediately
3613 after the last one we scanned. Unless the last one looked like a
3614 non-prologue instruction (and we looked ahead), in which case use
3615 its address instead. */
3617 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3619 /* In a frameless function, we might have incorrectly
3620 skipped some load immediate instructions. Undo the skipping
3621 if the load immediate was not followed by a stack adjustment. */
3622 if (load_immediate_bytes
&& !seen_sp_adjust
)
3623 end_prologue_addr
-= load_immediate_bytes
;
3625 return end_prologue_addr
;
3628 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3629 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3630 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3631 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3633 static struct mips_frame_cache
*
3634 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3636 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3637 struct mips_frame_cache
*cache
;
3639 if ((*this_cache
) != NULL
)
3640 return (*this_cache
);
3642 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3643 (*this_cache
) = cache
;
3644 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3646 /* Analyze the function prologue. */
3648 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3649 CORE_ADDR start_addr
;
3651 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3652 if (start_addr
== 0)
3653 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3654 /* We can't analyze the prologue if we couldn't find the begining
3656 if (start_addr
== 0)
3659 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3662 /* gdbarch_sp_regnum contains the value and not the address. */
3663 trad_frame_set_value (cache
->saved_regs
,
3664 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3667 return (*this_cache
);
3671 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3672 struct frame_id
*this_id
)
3674 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3676 /* This marks the outermost frame. */
3677 if (info
->base
== 0)
3679 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3682 static struct value
*
3683 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3684 void **this_cache
, int regnum
)
3686 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3688 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3692 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3693 struct frame_info
*this_frame
, void **this_cache
)
3695 CORE_ADDR pc
= get_frame_pc (this_frame
);
3696 if (mips_pc_is_mips (pc
))
3701 static const struct frame_unwind mips_insn32_frame_unwind
=
3704 default_frame_unwind_stop_reason
,
3705 mips_insn32_frame_this_id
,
3706 mips_insn32_frame_prev_register
,
3708 mips_insn32_frame_sniffer
3712 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3715 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3720 static const struct frame_base mips_insn32_frame_base
=
3722 &mips_insn32_frame_unwind
,
3723 mips_insn32_frame_base_address
,
3724 mips_insn32_frame_base_address
,
3725 mips_insn32_frame_base_address
3728 static const struct frame_base
*
3729 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3731 CORE_ADDR pc
= get_frame_pc (this_frame
);
3732 if (mips_pc_is_mips (pc
))
3733 return &mips_insn32_frame_base
;
3738 static struct trad_frame_cache
*
3739 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3742 CORE_ADDR start_addr
;
3743 CORE_ADDR stack_addr
;
3744 struct trad_frame_cache
*this_trad_cache
;
3745 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3746 int num_regs
= gdbarch_num_regs (gdbarch
);
3748 if ((*this_cache
) != NULL
)
3749 return (*this_cache
);
3750 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3751 (*this_cache
) = this_trad_cache
;
3753 /* The return address is in the link register. */
3754 trad_frame_set_reg_realreg (this_trad_cache
,
3755 gdbarch_pc_regnum (gdbarch
),
3756 num_regs
+ MIPS_RA_REGNUM
);
3758 /* Frame ID, since it's a frameless / stackless function, no stack
3759 space is allocated and SP on entry is the current SP. */
3760 pc
= get_frame_pc (this_frame
);
3761 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3762 stack_addr
= get_frame_register_signed (this_frame
,
3763 num_regs
+ MIPS_SP_REGNUM
);
3764 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3766 /* Assume that the frame's base is the same as the
3768 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3770 return this_trad_cache
;
3774 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3775 struct frame_id
*this_id
)
3777 struct trad_frame_cache
*this_trad_cache
3778 = mips_stub_frame_cache (this_frame
, this_cache
);
3779 trad_frame_get_id (this_trad_cache
, this_id
);
3782 static struct value
*
3783 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3784 void **this_cache
, int regnum
)
3786 struct trad_frame_cache
*this_trad_cache
3787 = mips_stub_frame_cache (this_frame
, this_cache
);
3788 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3792 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3793 struct frame_info
*this_frame
, void **this_cache
)
3796 struct obj_section
*s
;
3797 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3798 struct bound_minimal_symbol msym
;
3800 /* Use the stub unwinder for unreadable code. */
3801 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3804 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3807 /* Calling a PIC function from a non-PIC function passes through a
3808 stub. The stub for foo is named ".pic.foo". */
3809 msym
= lookup_minimal_symbol_by_pc (pc
);
3810 if (msym
.minsym
!= NULL
3811 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3812 && strncmp (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) == 0)
3818 static const struct frame_unwind mips_stub_frame_unwind
=
3821 default_frame_unwind_stop_reason
,
3822 mips_stub_frame_this_id
,
3823 mips_stub_frame_prev_register
,
3825 mips_stub_frame_sniffer
3829 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3832 struct trad_frame_cache
*this_trad_cache
3833 = mips_stub_frame_cache (this_frame
, this_cache
);
3834 return trad_frame_get_this_base (this_trad_cache
);
3837 static const struct frame_base mips_stub_frame_base
=
3839 &mips_stub_frame_unwind
,
3840 mips_stub_frame_base_address
,
3841 mips_stub_frame_base_address
,
3842 mips_stub_frame_base_address
3845 static const struct frame_base
*
3846 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3848 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3849 return &mips_stub_frame_base
;
3854 /* mips_addr_bits_remove - remove useless address bits */
3857 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3859 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3861 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3862 /* This hack is a work-around for existing boards using PMON, the
3863 simulator, and any other 64-bit targets that doesn't have true
3864 64-bit addressing. On these targets, the upper 32 bits of
3865 addresses are ignored by the hardware. Thus, the PC or SP are
3866 likely to have been sign extended to all 1s by instruction
3867 sequences that load 32-bit addresses. For example, a typical
3868 piece of code that loads an address is this:
3870 lui $r2, <upper 16 bits>
3871 ori $r2, <lower 16 bits>
3873 But the lui sign-extends the value such that the upper 32 bits
3874 may be all 1s. The workaround is simply to mask off these
3875 bits. In the future, gcc may be changed to support true 64-bit
3876 addressing, and this masking will have to be disabled. */
3877 return addr
&= 0xffffffffUL
;
3883 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3884 instruction and ending with a SC/SCD instruction. If such a sequence
3885 is found, attempt to step through it. A breakpoint is placed at the end of
3888 /* Instructions used during single-stepping of atomic sequences, standard
3890 #define LL_OPCODE 0x30
3891 #define LLD_OPCODE 0x34
3892 #define SC_OPCODE 0x38
3893 #define SCD_OPCODE 0x3c
3896 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3897 struct address_space
*aspace
, CORE_ADDR pc
)
3899 CORE_ADDR breaks
[2] = {-1, -1};
3901 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3905 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3906 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3908 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3909 /* Assume all atomic sequences start with a ll/lld instruction. */
3910 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3913 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3915 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3918 loc
+= MIPS_INSN32_SIZE
;
3919 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3921 /* Assume that there is at most one branch in the atomic
3922 sequence. If a branch is found, put a breakpoint in its
3923 destination address. */
3924 switch (itype_op (insn
))
3926 case 0: /* SPECIAL */
3927 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3928 return 0; /* fallback to the standard single-step code. */
3930 case 1: /* REGIMM */
3931 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3932 || ((itype_rt (insn
) & 0x1e) == 0
3933 && itype_rs (insn
) == 0)); /* BPOSGE* */
3937 return 0; /* fallback to the standard single-step code. */
3944 case 22: /* BLEZL */
3945 case 23: /* BGTTL */
3949 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3950 && (itype_rt (insn
) & 0x2) == 0);
3951 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3956 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3961 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3962 if (last_breakpoint
>= 1)
3963 return 0; /* More than one branch found, fallback to the
3964 standard single-step code. */
3965 breaks
[1] = branch_bp
;
3969 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3973 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3974 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3977 loc
+= MIPS_INSN32_SIZE
;
3979 /* Insert a breakpoint right after the end of the atomic sequence. */
3982 /* Check for duplicated breakpoints. Check also for a breakpoint
3983 placed (branch instruction's destination) in the atomic sequence. */
3984 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3985 last_breakpoint
= 0;
3987 /* Effectively inserts the breakpoints. */
3988 for (index
= 0; index
<= last_breakpoint
; index
++)
3989 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3995 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3996 struct address_space
*aspace
,
3999 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4000 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4001 CORE_ADDR breaks
[2] = {-1, -1};
4002 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4010 /* Assume all atomic sequences start with a ll/lld instruction. */
4011 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4012 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4014 loc
+= MIPS_INSN16_SIZE
;
4016 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4017 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4019 loc
+= MIPS_INSN16_SIZE
;
4021 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4022 that no atomic sequence is longer than "atomic_sequence_length"
4024 for (insn_count
= 0;
4025 !sc_found
&& insn_count
< atomic_sequence_length
;
4030 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4031 loc
+= MIPS_INSN16_SIZE
;
4033 /* Assume that there is at most one conditional branch in the
4034 atomic sequence. If a branch is found, put a breakpoint in
4035 its destination address. */
4036 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4038 /* 48-bit instructions. */
4039 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
4040 loc
+= 2 * MIPS_INSN16_SIZE
;
4043 /* 32-bit instructions. */
4044 case 2 * MIPS_INSN16_SIZE
:
4045 switch (micromips_op (insn
))
4047 case 0x10: /* POOL32I: bits 010000 */
4048 if ((b5s5_op (insn
) & 0x18) != 0x0
4049 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4050 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4051 && (b5s5_op (insn
) & 0x1d) != 0x11
4052 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4053 && ((b5s5_op (insn
) & 0x1e) != 0x14
4054 || (insn
& 0x3) != 0x0)
4055 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4056 && (b5s5_op (insn
) & 0x1e) != 0x1a
4057 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4058 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4059 || (insn
& 0x3) != 0x0)
4060 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4061 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4062 || (insn
& 0x3) != 0x1))
4063 /* BC1ANY*: bits 010000 111xx xxx01 */
4067 case 0x25: /* BEQ: bits 100101 */
4068 case 0x2d: /* BNE: bits 101101 */
4070 insn
|= mips_fetch_instruction (gdbarch
,
4071 ISA_MICROMIPS
, loc
, NULL
);
4072 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4073 + micromips_relative_offset16 (insn
));
4077 case 0x00: /* POOL32A: bits 000000 */
4079 insn
|= mips_fetch_instruction (gdbarch
,
4080 ISA_MICROMIPS
, loc
, NULL
);
4081 if (b0s6_op (insn
) != 0x3c
4082 /* POOL32Axf: bits 000000 ... 111100 */
4083 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4084 /* JALR, JALR.HB: 000000 000x111100 111100 */
4085 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4089 case 0x1d: /* JALS: bits 011101 */
4090 case 0x35: /* J: bits 110101 */
4091 case 0x3d: /* JAL: bits 111101 */
4092 case 0x3c: /* JALX: bits 111100 */
4093 return 0; /* Fall back to the standard single-step code. */
4095 case 0x18: /* POOL32C: bits 011000 */
4096 if ((b12s4_op (insn
) & 0xb) == 0xb)
4097 /* SC, SCD: bits 011000 1x11 */
4101 loc
+= MIPS_INSN16_SIZE
;
4104 /* 16-bit instructions. */
4105 case MIPS_INSN16_SIZE
:
4106 switch (micromips_op (insn
))
4108 case 0x23: /* BEQZ16: bits 100011 */
4109 case 0x2b: /* BNEZ16: bits 101011 */
4110 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4114 case 0x11: /* POOL16C: bits 010001 */
4115 if ((b5s5_op (insn
) & 0x1c) != 0xc
4116 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4117 && b5s5_op (insn
) != 0x18)
4118 /* JRADDIUSP: bits 010001 11000 */
4120 return 0; /* Fall back to the standard single-step code. */
4122 case 0x33: /* B16: bits 110011 */
4123 return 0; /* Fall back to the standard single-step code. */
4129 if (last_breakpoint
>= 1)
4130 return 0; /* More than one branch found, fallback to the
4131 standard single-step code. */
4132 breaks
[1] = branch_bp
;
4139 /* Insert a breakpoint right after the end of the atomic sequence. */
4142 /* Check for duplicated breakpoints. Check also for a breakpoint
4143 placed (branch instruction's destination) in the atomic sequence */
4144 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4145 last_breakpoint
= 0;
4147 /* Effectively inserts the breakpoints. */
4148 for (index
= 0; index
<= last_breakpoint
; index
++)
4149 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
4155 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4156 struct address_space
*aspace
, CORE_ADDR pc
)
4158 if (mips_pc_is_mips (pc
))
4159 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4160 else if (mips_pc_is_micromips (gdbarch
, pc
))
4161 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4166 /* mips_software_single_step() is called just before we want to resume
4167 the inferior, if we want to single-step it but there is no hardware
4168 or kernel single-step support (MIPS on GNU/Linux for example). We find
4169 the target of the coming instruction and breakpoint it. */
4172 mips_software_single_step (struct frame_info
*frame
)
4174 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4175 struct address_space
*aspace
= get_frame_address_space (frame
);
4176 CORE_ADDR pc
, next_pc
;
4178 pc
= get_frame_pc (frame
);
4179 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
4182 next_pc
= mips_next_pc (frame
, pc
);
4184 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
4188 /* Test whether the PC points to the return instruction at the
4189 end of a function. */
4192 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4197 /* This used to check for MIPS16, but this piece of code is never
4198 called for MIPS16 functions. And likewise microMIPS ones. */
4199 gdb_assert (mips_pc_is_mips (pc
));
4201 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4203 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4207 /* This fencepost looks highly suspicious to me. Removing it also
4208 seems suspicious as it could affect remote debugging across serial
4212 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4218 struct inferior
*inf
;
4220 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4222 fence
= start_pc
- heuristic_fence_post
;
4226 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4227 fence
= VM_MIN_ADDRESS
;
4229 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4231 inf
= current_inferior ();
4233 /* Search back for previous return. */
4234 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4235 if (start_pc
< fence
)
4237 /* It's not clear to me why we reach this point when
4238 stop_soon, but with this test, at least we
4239 don't print out warnings for every child forked (eg, on
4240 decstation). 22apr93 rich@cygnus.com. */
4241 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4243 static int blurb_printed
= 0;
4245 warning (_("GDB can't find the start of the function at %s."),
4246 paddress (gdbarch
, pc
));
4250 /* This actually happens frequently in embedded
4251 development, when you first connect to a board
4252 and your stack pointer and pc are nowhere in
4253 particular. This message needs to give people
4254 in that situation enough information to
4255 determine that it's no big deal. */
4256 printf_filtered ("\n\
4257 GDB is unable to find the start of the function at %s\n\
4258 and thus can't determine the size of that function's stack frame.\n\
4259 This means that GDB may be unable to access that stack frame, or\n\
4260 the frames below it.\n\
4261 This problem is most likely caused by an invalid program counter or\n\
4263 However, if you think GDB should simply search farther back\n\
4264 from %s for code which looks like the beginning of a\n\
4265 function, you can increase the range of the search using the `set\n\
4266 heuristic-fence-post' command.\n",
4267 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4274 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4276 unsigned short inst
;
4278 /* On MIPS16, any one of the following is likely to be the
4279 start of a function:
4285 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4286 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4287 if ((inst
& 0xff80) == 0x6480) /* save */
4289 if (start_pc
- instlen
>= fence
)
4291 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4292 start_pc
- instlen
, NULL
);
4293 if ((inst
& 0xf800) == 0xf000) /* extend */
4294 start_pc
-= instlen
;
4298 else if (((inst
& 0xf81f) == 0xe809
4299 && (inst
& 0x700) != 0x700) /* entry */
4300 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4301 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4302 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4304 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4305 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4310 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4318 /* On microMIPS, any one of the following is likely to be the
4319 start of a function:
4323 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4324 switch (micromips_op (insn
))
4326 case 0xc: /* ADDIU: bits 001100 */
4327 case 0x17: /* DADDIU: bits 010111 */
4328 sreg
= b0s5_reg (insn
);
4329 dreg
= b5s5_reg (insn
);
4331 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4332 pc
+ MIPS_INSN16_SIZE
, NULL
);
4333 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4334 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4335 /* (D)ADDIU $sp, imm */
4340 case 0x10: /* POOL32I: bits 010000 */
4341 if (b5s5_op (insn
) == 0xd
4342 /* LUI: bits 010000 001101 */
4343 && b0s5_reg (insn
>> 16) == 28)
4348 case 0x13: /* POOL16D: bits 010011 */
4349 if ((insn
& 0x1) == 0x1)
4350 /* ADDIUSP: bits 010011 1 */
4352 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4358 /* ADDIUS5: bits 010011 0 */
4360 dreg
= b5s5_reg (insn
);
4361 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4362 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4363 /* ADDIUS5 $sp, -imm */
4371 else if (mips_about_to_return (gdbarch
, start_pc
))
4373 /* Skip return and its delay slot. */
4374 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4381 struct mips_objfile_private
4387 /* According to the current ABI, should the type be passed in a
4388 floating-point register (assuming that there is space)? When there
4389 is no FPU, FP are not even considered as possible candidates for
4390 FP registers and, consequently this returns false - forces FP
4391 arguments into integer registers. */
4394 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4395 struct type
*arg_type
)
4397 return ((typecode
== TYPE_CODE_FLT
4398 || (MIPS_EABI (gdbarch
)
4399 && (typecode
== TYPE_CODE_STRUCT
4400 || typecode
== TYPE_CODE_UNION
)
4401 && TYPE_NFIELDS (arg_type
) == 1
4402 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4404 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4407 /* On o32, argument passing in GPRs depends on the alignment of the type being
4408 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4411 mips_type_needs_double_align (struct type
*type
)
4413 enum type_code typecode
= TYPE_CODE (type
);
4415 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4417 else if (typecode
== TYPE_CODE_STRUCT
)
4419 if (TYPE_NFIELDS (type
) < 1)
4421 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4423 else if (typecode
== TYPE_CODE_UNION
)
4427 n
= TYPE_NFIELDS (type
);
4428 for (i
= 0; i
< n
; i
++)
4429 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4436 /* Adjust the address downward (direction of stack growth) so that it
4437 is correctly aligned for a new stack frame. */
4439 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4441 return align_down (addr
, 16);
4444 /* Implement the "push_dummy_code" gdbarch method. */
4447 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4448 CORE_ADDR funaddr
, struct value
**args
,
4449 int nargs
, struct type
*value_type
,
4450 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4451 struct regcache
*regcache
)
4453 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4457 /* Reserve enough room on the stack for our breakpoint instruction. */
4458 bp_slot
= sp
- sizeof (nop_insn
);
4460 /* Return to microMIPS mode if calling microMIPS code to avoid
4461 triggering an address error exception on processors that only
4462 support microMIPS execution. */
4463 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4464 ? make_compact_addr (bp_slot
) : bp_slot
);
4466 /* The breakpoint layer automatically adjusts the address of
4467 breakpoints inserted in a branch delay slot. With enough
4468 bad luck, the 4 bytes located just before our breakpoint
4469 instruction could look like a branch instruction, and thus
4470 trigger the adjustement, and break the function call entirely.
4471 So, we reserve those 4 bytes and write a nop instruction
4472 to prevent that from happening. */
4473 nop_addr
= bp_slot
- sizeof (nop_insn
);
4474 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4475 sp
= mips_frame_align (gdbarch
, nop_addr
);
4477 /* Inferior resumes at the function entry point. */
4484 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4485 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4486 int nargs
, struct value
**args
, CORE_ADDR sp
,
4487 int struct_return
, CORE_ADDR struct_addr
)
4493 int stack_offset
= 0;
4494 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4495 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4496 int regsize
= mips_abi_regsize (gdbarch
);
4498 /* For shared libraries, "t9" needs to point at the function
4500 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4502 /* Set the return address register to point to the entry point of
4503 the program, where a breakpoint lies in wait. */
4504 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4506 /* First ensure that the stack and structure return address (if any)
4507 are properly aligned. The stack has to be at least 64-bit
4508 aligned even on 32-bit machines, because doubles must be 64-bit
4509 aligned. For n32 and n64, stack frames need to be 128-bit
4510 aligned, so we round to this widest known alignment. */
4512 sp
= align_down (sp
, 16);
4513 struct_addr
= align_down (struct_addr
, 16);
4515 /* Now make space on the stack for the args. We allocate more
4516 than necessary for EABI, because the first few arguments are
4517 passed in registers, but that's OK. */
4518 for (argnum
= 0; argnum
< nargs
; argnum
++)
4519 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4520 sp
-= align_up (len
, 16);
4523 fprintf_unfiltered (gdb_stdlog
,
4524 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4525 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4527 /* Initialize the integer and float register pointers. */
4528 argreg
= MIPS_A0_REGNUM
;
4529 float_argreg
= mips_fpa0_regnum (gdbarch
);
4531 /* The struct_return pointer occupies the first parameter-passing reg. */
4535 fprintf_unfiltered (gdb_stdlog
,
4536 "mips_eabi_push_dummy_call: "
4537 "struct_return reg=%d %s\n",
4538 argreg
, paddress (gdbarch
, struct_addr
));
4539 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4542 /* Now load as many as possible of the first arguments into
4543 registers, and push the rest onto the stack. Loop thru args
4544 from first to last. */
4545 for (argnum
= 0; argnum
< nargs
; argnum
++)
4547 const gdb_byte
*val
;
4548 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4549 struct value
*arg
= args
[argnum
];
4550 struct type
*arg_type
= check_typedef (value_type (arg
));
4551 int len
= TYPE_LENGTH (arg_type
);
4552 enum type_code typecode
= TYPE_CODE (arg_type
);
4555 fprintf_unfiltered (gdb_stdlog
,
4556 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4557 argnum
+ 1, len
, (int) typecode
);
4559 /* The EABI passes structures that do not fit in a register by
4562 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4564 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4565 value_address (arg
));
4566 typecode
= TYPE_CODE_PTR
;
4570 fprintf_unfiltered (gdb_stdlog
, " push");
4573 val
= value_contents (arg
);
4575 /* 32-bit ABIs always start floating point arguments in an
4576 even-numbered floating point register. Round the FP register
4577 up before the check to see if there are any FP registers
4578 left. Non MIPS_EABI targets also pass the FP in the integer
4579 registers so also round up normal registers. */
4580 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4582 if ((float_argreg
& 1))
4586 /* Floating point arguments passed in registers have to be
4587 treated specially. On 32-bit architectures, doubles
4588 are passed in register pairs; the even register gets
4589 the low word, and the odd register gets the high word.
4590 On non-EABI processors, the first two floating point arguments are
4591 also copied to general registers, because MIPS16 functions
4592 don't use float registers for arguments. This duplication of
4593 arguments in general registers can't hurt non-MIPS16 functions
4594 because those registers are normally skipped. */
4595 /* MIPS_EABI squeezes a struct that contains a single floating
4596 point value into an FP register instead of pushing it onto the
4598 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4599 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4601 /* EABI32 will pass doubles in consecutive registers, even on
4602 64-bit cores. At one time, we used to check the size of
4603 `float_argreg' to determine whether or not to pass doubles
4604 in consecutive registers, but this is not sufficient for
4605 making the ABI determination. */
4606 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4608 int low_offset
= gdbarch_byte_order (gdbarch
)
4609 == BFD_ENDIAN_BIG
? 4 : 0;
4612 /* Write the low word of the double to the even register(s). */
4613 regval
= extract_signed_integer (val
+ low_offset
,
4616 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4617 float_argreg
, phex (regval
, 4));
4618 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4620 /* Write the high word of the double to the odd register(s). */
4621 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4624 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4625 float_argreg
, phex (regval
, 4));
4626 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4630 /* This is a floating point value that fits entirely
4631 in a single register. */
4632 /* On 32 bit ABI's the float_argreg is further adjusted
4633 above to ensure that it is even register aligned. */
4634 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4636 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4637 float_argreg
, phex (regval
, len
));
4638 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4643 /* Copy the argument to general registers or the stack in
4644 register-sized pieces. Large arguments are split between
4645 registers and stack. */
4646 /* Note: structs whose size is not a multiple of regsize
4647 are treated specially: Irix cc passes
4648 them in registers where gcc sometimes puts them on the
4649 stack. For maximum compatibility, we will put them in
4651 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4653 /* Note: Floating-point values that didn't fit into an FP
4654 register are only written to memory. */
4657 /* Remember if the argument was written to the stack. */
4658 int stack_used_p
= 0;
4659 int partial_len
= (len
< regsize
? len
: regsize
);
4662 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4665 /* Write this portion of the argument to the stack. */
4666 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4668 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4670 /* Should shorter than int integer values be
4671 promoted to int before being stored? */
4672 int longword_offset
= 0;
4675 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4678 && (typecode
== TYPE_CODE_INT
4679 || typecode
== TYPE_CODE_PTR
4680 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4681 longword_offset
= regsize
- len
;
4682 else if ((typecode
== TYPE_CODE_STRUCT
4683 || typecode
== TYPE_CODE_UNION
)
4684 && TYPE_LENGTH (arg_type
) < regsize
)
4685 longword_offset
= regsize
- len
;
4690 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4691 paddress (gdbarch
, stack_offset
));
4692 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4693 paddress (gdbarch
, longword_offset
));
4696 addr
= sp
+ stack_offset
+ longword_offset
;
4701 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4702 paddress (gdbarch
, addr
));
4703 for (i
= 0; i
< partial_len
; i
++)
4705 fprintf_unfiltered (gdb_stdlog
, "%02x",
4709 write_memory (addr
, val
, partial_len
);
4712 /* Note!!! This is NOT an else clause. Odd sized
4713 structs may go thru BOTH paths. Floating point
4714 arguments will not. */
4715 /* Write this portion of the argument to a general
4716 purpose register. */
4717 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4718 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4721 extract_signed_integer (val
, partial_len
, byte_order
);
4724 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4726 phex (regval
, regsize
));
4727 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4734 /* Compute the offset into the stack at which we will
4735 copy the next parameter.
4737 In the new EABI (and the NABI32), the stack_offset
4738 only needs to be adjusted when it has been used. */
4741 stack_offset
+= align_up (partial_len
, regsize
);
4745 fprintf_unfiltered (gdb_stdlog
, "\n");
4748 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4750 /* Return adjusted stack pointer. */
4754 /* Determine the return value convention being used. */
4756 static enum return_value_convention
4757 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4758 struct type
*type
, struct regcache
*regcache
,
4759 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4761 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4762 int fp_return_type
= 0;
4763 int offset
, regnum
, xfer
;
4765 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4766 return RETURN_VALUE_STRUCT_CONVENTION
;
4768 /* Floating point type? */
4769 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4771 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4773 /* Structs with a single field of float type
4774 are returned in a floating point register. */
4775 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4776 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4777 && TYPE_NFIELDS (type
) == 1)
4779 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4781 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4788 /* A floating-point value belongs in the least significant part
4791 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4792 regnum
= mips_regnum (gdbarch
)->fp0
;
4796 /* An integer value goes in V0/V1. */
4798 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4799 regnum
= MIPS_V0_REGNUM
;
4802 offset
< TYPE_LENGTH (type
);
4803 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4805 xfer
= mips_abi_regsize (gdbarch
);
4806 if (offset
+ xfer
> TYPE_LENGTH (type
))
4807 xfer
= TYPE_LENGTH (type
) - offset
;
4808 mips_xfer_register (gdbarch
, regcache
,
4809 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4810 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4814 return RETURN_VALUE_REGISTER_CONVENTION
;
4818 /* N32/N64 ABI stuff. */
4820 /* Search for a naturally aligned double at OFFSET inside a struct
4821 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4825 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4830 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4833 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4836 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4839 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4842 struct type
*field_type
;
4844 /* We're only looking at normal fields. */
4845 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4846 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4849 /* If we have gone past the offset, there is no double to pass. */
4850 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4854 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4856 /* If this field is entirely before the requested offset, go
4857 on to the next one. */
4858 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4861 /* If this is our special aligned double, we can stop. */
4862 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4863 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4866 /* This field starts at or before the requested offset, and
4867 overlaps it. If it is a structure, recurse inwards. */
4868 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4875 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4876 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4877 int nargs
, struct value
**args
, CORE_ADDR sp
,
4878 int struct_return
, CORE_ADDR struct_addr
)
4884 int stack_offset
= 0;
4885 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4886 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4888 /* For shared libraries, "t9" needs to point at the function
4890 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4892 /* Set the return address register to point to the entry point of
4893 the program, where a breakpoint lies in wait. */
4894 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4896 /* First ensure that the stack and structure return address (if any)
4897 are properly aligned. The stack has to be at least 64-bit
4898 aligned even on 32-bit machines, because doubles must be 64-bit
4899 aligned. For n32 and n64, stack frames need to be 128-bit
4900 aligned, so we round to this widest known alignment. */
4902 sp
= align_down (sp
, 16);
4903 struct_addr
= align_down (struct_addr
, 16);
4905 /* Now make space on the stack for the args. */
4906 for (argnum
= 0; argnum
< nargs
; argnum
++)
4907 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4908 sp
-= align_up (len
, 16);
4911 fprintf_unfiltered (gdb_stdlog
,
4912 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4913 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4915 /* Initialize the integer and float register pointers. */
4916 argreg
= MIPS_A0_REGNUM
;
4917 float_argreg
= mips_fpa0_regnum (gdbarch
);
4919 /* The struct_return pointer occupies the first parameter-passing reg. */
4923 fprintf_unfiltered (gdb_stdlog
,
4924 "mips_n32n64_push_dummy_call: "
4925 "struct_return reg=%d %s\n",
4926 argreg
, paddress (gdbarch
, struct_addr
));
4927 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4930 /* Now load as many as possible of the first arguments into
4931 registers, and push the rest onto the stack. Loop thru args
4932 from first to last. */
4933 for (argnum
= 0; argnum
< nargs
; argnum
++)
4935 const gdb_byte
*val
;
4936 struct value
*arg
= args
[argnum
];
4937 struct type
*arg_type
= check_typedef (value_type (arg
));
4938 int len
= TYPE_LENGTH (arg_type
);
4939 enum type_code typecode
= TYPE_CODE (arg_type
);
4942 fprintf_unfiltered (gdb_stdlog
,
4943 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4944 argnum
+ 1, len
, (int) typecode
);
4946 val
= value_contents (arg
);
4948 /* A 128-bit long double value requires an even-odd pair of
4949 floating-point registers. */
4951 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4952 && (float_argreg
& 1))
4958 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4959 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4961 /* This is a floating point value that fits entirely
4962 in a single register or a pair of registers. */
4963 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4964 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4966 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4967 float_argreg
, phex (regval
, reglen
));
4968 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4971 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4972 argreg
, phex (regval
, reglen
));
4973 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4978 regval
= extract_unsigned_integer (val
+ reglen
,
4979 reglen
, byte_order
);
4981 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4982 float_argreg
, phex (regval
, reglen
));
4983 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4986 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4987 argreg
, phex (regval
, reglen
));
4988 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4995 /* Copy the argument to general registers or the stack in
4996 register-sized pieces. Large arguments are split between
4997 registers and stack. */
4998 /* For N32/N64, structs, unions, or other composite types are
4999 treated as a sequence of doublewords, and are passed in integer
5000 or floating point registers as though they were simple scalar
5001 parameters to the extent that they fit, with any excess on the
5002 stack packed according to the normal memory layout of the
5004 The caller does not reserve space for the register arguments;
5005 the callee is responsible for reserving it if required. */
5006 /* Note: Floating-point values that didn't fit into an FP
5007 register are only written to memory. */
5010 /* Remember if the argument was written to the stack. */
5011 int stack_used_p
= 0;
5012 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5015 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5018 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5019 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5021 /* Write this portion of the argument to the stack. */
5022 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5024 /* Should shorter than int integer values be
5025 promoted to int before being stored? */
5026 int longword_offset
= 0;
5029 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5031 if ((typecode
== TYPE_CODE_INT
5032 || typecode
== TYPE_CODE_PTR
)
5034 longword_offset
= MIPS64_REGSIZE
- len
;
5039 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5040 paddress (gdbarch
, stack_offset
));
5041 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5042 paddress (gdbarch
, longword_offset
));
5045 addr
= sp
+ stack_offset
+ longword_offset
;
5050 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5051 paddress (gdbarch
, addr
));
5052 for (i
= 0; i
< partial_len
; i
++)
5054 fprintf_unfiltered (gdb_stdlog
, "%02x",
5058 write_memory (addr
, val
, partial_len
);
5061 /* Note!!! This is NOT an else clause. Odd sized
5062 structs may go thru BOTH paths. */
5063 /* Write this portion of the argument to a general
5064 purpose register. */
5065 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5069 /* Sign extend pointers, 32-bit integers and signed
5070 16-bit and 8-bit integers; everything else is taken
5073 if ((partial_len
== 4
5074 && (typecode
== TYPE_CODE_PTR
5075 || typecode
== TYPE_CODE_INT
))
5077 && typecode
== TYPE_CODE_INT
5078 && !TYPE_UNSIGNED (arg_type
)))
5079 regval
= extract_signed_integer (val
, partial_len
,
5082 regval
= extract_unsigned_integer (val
, partial_len
,
5085 /* A non-floating-point argument being passed in a
5086 general register. If a struct or union, and if
5087 the remaining length is smaller than the register
5088 size, we have to adjust the register value on
5091 It does not seem to be necessary to do the
5092 same for integral types. */
5094 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5095 && partial_len
< MIPS64_REGSIZE
5096 && (typecode
== TYPE_CODE_STRUCT
5097 || typecode
== TYPE_CODE_UNION
))
5098 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5102 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5104 phex (regval
, MIPS64_REGSIZE
));
5105 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5107 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5108 TYPE_LENGTH (arg_type
) - len
))
5111 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5113 phex (regval
, MIPS64_REGSIZE
));
5114 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5125 /* Compute the offset into the stack at which we will
5126 copy the next parameter.
5128 In N32 (N64?), the stack_offset only needs to be
5129 adjusted when it has been used. */
5132 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5136 fprintf_unfiltered (gdb_stdlog
, "\n");
5139 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5141 /* Return adjusted stack pointer. */
5145 static enum return_value_convention
5146 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5147 struct type
*type
, struct regcache
*regcache
,
5148 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5150 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5152 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5154 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5155 if needed), as appropriate for the type. Composite results (struct,
5156 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5159 * A struct with only one or two floating point fields is returned in $f0
5160 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5163 * Any other composite results of at most 128 bits are returned in
5164 $2 (first 64 bits) and $3 (remainder, if necessary).
5166 * Larger composite results are handled by converting the function to a
5167 procedure with an implicit first parameter, which is a pointer to an area
5168 reserved by the caller to receive the result. [The o32-bit ABI requires
5169 that all composite results be handled by conversion to implicit first
5170 parameters. The MIPS/SGI Fortran implementation has always made a
5171 specific exception to return COMPLEX results in the floating point
5174 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5175 return RETURN_VALUE_STRUCT_CONVENTION
;
5176 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5177 && TYPE_LENGTH (type
) == 16
5178 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5180 /* A 128-bit floating-point value fills both $f0 and $f2. The
5181 two registers are used in the same as memory order, so the
5182 eight bytes with the lower memory address are in $f0. */
5184 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5185 mips_xfer_register (gdbarch
, regcache
,
5186 (gdbarch_num_regs (gdbarch
)
5187 + mips_regnum (gdbarch
)->fp0
),
5188 8, gdbarch_byte_order (gdbarch
),
5189 readbuf
, writebuf
, 0);
5190 mips_xfer_register (gdbarch
, regcache
,
5191 (gdbarch_num_regs (gdbarch
)
5192 + mips_regnum (gdbarch
)->fp0
+ 2),
5193 8, gdbarch_byte_order (gdbarch
),
5194 readbuf
? readbuf
+ 8 : readbuf
,
5195 writebuf
? writebuf
+ 8 : writebuf
, 0);
5196 return RETURN_VALUE_REGISTER_CONVENTION
;
5198 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5199 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5201 /* A single or double floating-point value that fits in FP0. */
5203 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5204 mips_xfer_register (gdbarch
, regcache
,
5205 (gdbarch_num_regs (gdbarch
)
5206 + mips_regnum (gdbarch
)->fp0
),
5208 gdbarch_byte_order (gdbarch
),
5209 readbuf
, writebuf
, 0);
5210 return RETURN_VALUE_REGISTER_CONVENTION
;
5212 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5213 && TYPE_NFIELDS (type
) <= 2
5214 && TYPE_NFIELDS (type
) >= 1
5215 && ((TYPE_NFIELDS (type
) == 1
5216 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5218 || (TYPE_NFIELDS (type
) == 2
5219 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5221 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5222 == TYPE_CODE_FLT
))))
5224 /* A struct that contains one or two floats. Each value is part
5225 in the least significant part of their floating point
5226 register (or GPR, for soft float). */
5229 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5230 ? mips_regnum (gdbarch
)->fp0
5232 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5234 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5237 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5239 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5241 /* A 16-byte long double field goes in two consecutive
5243 mips_xfer_register (gdbarch
, regcache
,
5244 gdbarch_num_regs (gdbarch
) + regnum
,
5246 gdbarch_byte_order (gdbarch
),
5247 readbuf
, writebuf
, offset
);
5248 mips_xfer_register (gdbarch
, regcache
,
5249 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5251 gdbarch_byte_order (gdbarch
),
5252 readbuf
, writebuf
, offset
+ 8);
5255 mips_xfer_register (gdbarch
, regcache
,
5256 gdbarch_num_regs (gdbarch
) + regnum
,
5257 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5258 gdbarch_byte_order (gdbarch
),
5259 readbuf
, writebuf
, offset
);
5261 return RETURN_VALUE_REGISTER_CONVENTION
;
5263 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5264 || TYPE_CODE (type
) == TYPE_CODE_UNION
5265 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5267 /* A composite type. Extract the left justified value,
5268 regardless of the byte order. I.e. DO NOT USE
5272 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5273 offset
< TYPE_LENGTH (type
);
5274 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5276 int xfer
= register_size (gdbarch
, regnum
);
5277 if (offset
+ xfer
> TYPE_LENGTH (type
))
5278 xfer
= TYPE_LENGTH (type
) - offset
;
5280 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5281 offset
, xfer
, regnum
);
5282 mips_xfer_register (gdbarch
, regcache
,
5283 gdbarch_num_regs (gdbarch
) + regnum
,
5284 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5287 return RETURN_VALUE_REGISTER_CONVENTION
;
5291 /* A scalar extract each part but least-significant-byte
5295 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5296 offset
< TYPE_LENGTH (type
);
5297 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5299 int xfer
= register_size (gdbarch
, regnum
);
5300 if (offset
+ xfer
> TYPE_LENGTH (type
))
5301 xfer
= TYPE_LENGTH (type
) - offset
;
5303 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5304 offset
, xfer
, regnum
);
5305 mips_xfer_register (gdbarch
, regcache
,
5306 gdbarch_num_regs (gdbarch
) + regnum
,
5307 xfer
, gdbarch_byte_order (gdbarch
),
5308 readbuf
, writebuf
, offset
);
5310 return RETURN_VALUE_REGISTER_CONVENTION
;
5314 /* Which registers to use for passing floating-point values between
5315 function calls, one of floating-point, general and both kinds of
5316 registers. O32 and O64 use different register kinds for standard
5317 MIPS and MIPS16 code; to make the handling of cases where we may
5318 not know what kind of code is being used (e.g. no debug information)
5319 easier we sometimes use both kinds. */
5328 /* O32 ABI stuff. */
5331 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5332 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5333 int nargs
, struct value
**args
, CORE_ADDR sp
,
5334 int struct_return
, CORE_ADDR struct_addr
)
5340 int stack_offset
= 0;
5341 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5342 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5344 /* For shared libraries, "t9" needs to point at the function
5346 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5348 /* Set the return address register to point to the entry point of
5349 the program, where a breakpoint lies in wait. */
5350 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5352 /* First ensure that the stack and structure return address (if any)
5353 are properly aligned. The stack has to be at least 64-bit
5354 aligned even on 32-bit machines, because doubles must be 64-bit
5355 aligned. For n32 and n64, stack frames need to be 128-bit
5356 aligned, so we round to this widest known alignment. */
5358 sp
= align_down (sp
, 16);
5359 struct_addr
= align_down (struct_addr
, 16);
5361 /* Now make space on the stack for the args. */
5362 for (argnum
= 0; argnum
< nargs
; argnum
++)
5364 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5366 /* Align to double-word if necessary. */
5367 if (mips_type_needs_double_align (arg_type
))
5368 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5369 /* Allocate space on the stack. */
5370 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5372 sp
-= align_up (len
, 16);
5375 fprintf_unfiltered (gdb_stdlog
,
5376 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5377 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5379 /* Initialize the integer and float register pointers. */
5380 argreg
= MIPS_A0_REGNUM
;
5381 float_argreg
= mips_fpa0_regnum (gdbarch
);
5383 /* The struct_return pointer occupies the first parameter-passing reg. */
5387 fprintf_unfiltered (gdb_stdlog
,
5388 "mips_o32_push_dummy_call: "
5389 "struct_return reg=%d %s\n",
5390 argreg
, paddress (gdbarch
, struct_addr
));
5391 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5392 stack_offset
+= MIPS32_REGSIZE
;
5395 /* Now load as many as possible of the first arguments into
5396 registers, and push the rest onto the stack. Loop thru args
5397 from first to last. */
5398 for (argnum
= 0; argnum
< nargs
; argnum
++)
5400 const gdb_byte
*val
;
5401 struct value
*arg
= args
[argnum
];
5402 struct type
*arg_type
= check_typedef (value_type (arg
));
5403 int len
= TYPE_LENGTH (arg_type
);
5404 enum type_code typecode
= TYPE_CODE (arg_type
);
5407 fprintf_unfiltered (gdb_stdlog
,
5408 "mips_o32_push_dummy_call: %d len=%d type=%d",
5409 argnum
+ 1, len
, (int) typecode
);
5411 val
= value_contents (arg
);
5413 /* 32-bit ABIs always start floating point arguments in an
5414 even-numbered floating point register. Round the FP register
5415 up before the check to see if there are any FP registers
5416 left. O32 targets also pass the FP in the integer registers
5417 so also round up normal registers. */
5418 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5420 if ((float_argreg
& 1))
5424 /* Floating point arguments passed in registers have to be
5425 treated specially. On 32-bit architectures, doubles are
5426 passed in register pairs; the even FP register gets the
5427 low word, and the odd FP register gets the high word.
5428 On O32, the first two floating point arguments are also
5429 copied to general registers, following their memory order,
5430 because MIPS16 functions don't use float registers for
5431 arguments. This duplication of arguments in general
5432 registers can't hurt non-MIPS16 functions, because those
5433 registers are normally skipped. */
5435 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5436 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5438 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5440 int freg_offset
= gdbarch_byte_order (gdbarch
)
5441 == BFD_ENDIAN_BIG
? 1 : 0;
5442 unsigned long regval
;
5445 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5447 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5448 float_argreg
+ freg_offset
,
5450 regcache_cooked_write_unsigned (regcache
,
5451 float_argreg
++ + freg_offset
,
5454 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5455 argreg
, phex (regval
, 4));
5456 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5459 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5461 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5462 float_argreg
- freg_offset
,
5464 regcache_cooked_write_unsigned (regcache
,
5465 float_argreg
++ - freg_offset
,
5468 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5469 argreg
, phex (regval
, 4));
5470 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5474 /* This is a floating point value that fits entirely
5475 in a single register. */
5476 /* On 32 bit ABI's the float_argreg is further adjusted
5477 above to ensure that it is even register aligned. */
5478 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5480 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5481 float_argreg
, phex (regval
, len
));
5482 regcache_cooked_write_unsigned (regcache
,
5483 float_argreg
++, regval
);
5484 /* Although two FP registers are reserved for each
5485 argument, only one corresponding integer register is
5488 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5489 argreg
, phex (regval
, len
));
5490 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5492 /* Reserve space for the FP register. */
5493 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5497 /* Copy the argument to general registers or the stack in
5498 register-sized pieces. Large arguments are split between
5499 registers and stack. */
5500 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5501 are treated specially: Irix cc passes
5502 them in registers where gcc sometimes puts them on the
5503 stack. For maximum compatibility, we will put them in
5505 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5506 && len
% MIPS32_REGSIZE
!= 0);
5507 /* Structures should be aligned to eight bytes (even arg registers)
5508 on MIPS_ABI_O32, if their first member has double precision. */
5509 if (mips_type_needs_double_align (arg_type
))
5514 stack_offset
+= MIPS32_REGSIZE
;
5519 /* Remember if the argument was written to the stack. */
5520 int stack_used_p
= 0;
5521 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5524 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5527 /* Write this portion of the argument to the stack. */
5528 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5529 || odd_sized_struct
)
5531 /* Should shorter than int integer values be
5532 promoted to int before being stored? */
5533 int longword_offset
= 0;
5539 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5540 paddress (gdbarch
, stack_offset
));
5541 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5542 paddress (gdbarch
, longword_offset
));
5545 addr
= sp
+ stack_offset
+ longword_offset
;
5550 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5551 paddress (gdbarch
, addr
));
5552 for (i
= 0; i
< partial_len
; i
++)
5554 fprintf_unfiltered (gdb_stdlog
, "%02x",
5558 write_memory (addr
, val
, partial_len
);
5561 /* Note!!! This is NOT an else clause. Odd sized
5562 structs may go thru BOTH paths. */
5563 /* Write this portion of the argument to a general
5564 purpose register. */
5565 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5567 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5569 /* Value may need to be sign extended, because
5570 mips_isa_regsize() != mips_abi_regsize(). */
5572 /* A non-floating-point argument being passed in a
5573 general register. If a struct or union, and if
5574 the remaining length is smaller than the register
5575 size, we have to adjust the register value on
5578 It does not seem to be necessary to do the
5579 same for integral types.
5581 Also don't do this adjustment on O64 binaries.
5583 cagney/2001-07-23: gdb/179: Also, GCC, when
5584 outputting LE O32 with sizeof (struct) <
5585 mips_abi_regsize(), generates a left shift
5586 as part of storing the argument in a register
5587 (the left shift isn't generated when
5588 sizeof (struct) >= mips_abi_regsize()). Since
5589 it is quite possible that this is GCC
5590 contradicting the LE/O32 ABI, GDB has not been
5591 adjusted to accommodate this. Either someone
5592 needs to demonstrate that the LE/O32 ABI
5593 specifies such a left shift OR this new ABI gets
5594 identified as such and GDB gets tweaked
5597 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5598 && partial_len
< MIPS32_REGSIZE
5599 && (typecode
== TYPE_CODE_STRUCT
5600 || typecode
== TYPE_CODE_UNION
))
5601 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5605 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5607 phex (regval
, MIPS32_REGSIZE
));
5608 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5611 /* Prevent subsequent floating point arguments from
5612 being passed in floating point registers. */
5613 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5619 /* Compute the offset into the stack at which we will
5620 copy the next parameter.
5622 In older ABIs, the caller reserved space for
5623 registers that contained arguments. This was loosely
5624 refered to as their "home". Consequently, space is
5625 always allocated. */
5627 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5631 fprintf_unfiltered (gdb_stdlog
, "\n");
5634 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5636 /* Return adjusted stack pointer. */
5640 static enum return_value_convention
5641 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5642 struct type
*type
, struct regcache
*regcache
,
5643 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5645 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5646 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5647 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5648 enum mips_fval_reg fval_reg
;
5650 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5651 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5652 || TYPE_CODE (type
) == TYPE_CODE_UNION
5653 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5654 return RETURN_VALUE_STRUCT_CONVENTION
;
5655 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5656 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5658 /* A single-precision floating-point value. If reading in or copying,
5659 then we get it from/put it to FP0 for standard MIPS code or GPR2
5660 for MIPS16 code. If writing out only, then we put it to both FP0
5661 and GPR2. We do not support reading in with no function known, if
5662 this safety check ever triggers, then we'll have to try harder. */
5663 gdb_assert (function
|| !readbuf
);
5668 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5671 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5673 case mips_fval_both
:
5674 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5677 if (fval_reg
!= mips_fval_gpr
)
5678 mips_xfer_register (gdbarch
, regcache
,
5679 (gdbarch_num_regs (gdbarch
)
5680 + mips_regnum (gdbarch
)->fp0
),
5682 gdbarch_byte_order (gdbarch
),
5683 readbuf
, writebuf
, 0);
5684 if (fval_reg
!= mips_fval_fpr
)
5685 mips_xfer_register (gdbarch
, regcache
,
5686 gdbarch_num_regs (gdbarch
) + 2,
5688 gdbarch_byte_order (gdbarch
),
5689 readbuf
, writebuf
, 0);
5690 return RETURN_VALUE_REGISTER_CONVENTION
;
5692 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5693 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5695 /* A double-precision floating-point value. If reading in or copying,
5696 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5697 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5698 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5699 no function known, if this safety check ever triggers, then we'll
5700 have to try harder. */
5701 gdb_assert (function
|| !readbuf
);
5706 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5709 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5711 case mips_fval_both
:
5712 fprintf_unfiltered (gdb_stderr
,
5713 "Return float in $fp1/$fp0 and $2/$3\n");
5716 if (fval_reg
!= mips_fval_gpr
)
5718 /* The most significant part goes in FP1, and the least significant
5720 switch (gdbarch_byte_order (gdbarch
))
5722 case BFD_ENDIAN_LITTLE
:
5723 mips_xfer_register (gdbarch
, regcache
,
5724 (gdbarch_num_regs (gdbarch
)
5725 + mips_regnum (gdbarch
)->fp0
+ 0),
5726 4, gdbarch_byte_order (gdbarch
),
5727 readbuf
, writebuf
, 0);
5728 mips_xfer_register (gdbarch
, regcache
,
5729 (gdbarch_num_regs (gdbarch
)
5730 + mips_regnum (gdbarch
)->fp0
+ 1),
5731 4, gdbarch_byte_order (gdbarch
),
5732 readbuf
, writebuf
, 4);
5734 case BFD_ENDIAN_BIG
:
5735 mips_xfer_register (gdbarch
, regcache
,
5736 (gdbarch_num_regs (gdbarch
)
5737 + mips_regnum (gdbarch
)->fp0
+ 1),
5738 4, gdbarch_byte_order (gdbarch
),
5739 readbuf
, writebuf
, 0);
5740 mips_xfer_register (gdbarch
, regcache
,
5741 (gdbarch_num_regs (gdbarch
)
5742 + mips_regnum (gdbarch
)->fp0
+ 0),
5743 4, gdbarch_byte_order (gdbarch
),
5744 readbuf
, writebuf
, 4);
5747 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5750 if (fval_reg
!= mips_fval_fpr
)
5752 /* The two 32-bit parts are always placed in GPR2 and GPR3
5753 following these registers' memory order. */
5754 mips_xfer_register (gdbarch
, regcache
,
5755 gdbarch_num_regs (gdbarch
) + 2,
5756 4, gdbarch_byte_order (gdbarch
),
5757 readbuf
, writebuf
, 0);
5758 mips_xfer_register (gdbarch
, regcache
,
5759 gdbarch_num_regs (gdbarch
) + 3,
5760 4, gdbarch_byte_order (gdbarch
),
5761 readbuf
, writebuf
, 4);
5763 return RETURN_VALUE_REGISTER_CONVENTION
;
5766 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5767 && TYPE_NFIELDS (type
) <= 2
5768 && TYPE_NFIELDS (type
) >= 1
5769 && ((TYPE_NFIELDS (type
) == 1
5770 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5772 || (TYPE_NFIELDS (type
) == 2
5773 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5775 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5777 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5779 /* A struct that contains one or two floats. Each value is part
5780 in the least significant part of their floating point
5782 gdb_byte reg
[MAX_REGISTER_SIZE
];
5785 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5786 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5788 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5791 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5793 mips_xfer_register (gdbarch
, regcache
,
5794 gdbarch_num_regs (gdbarch
) + regnum
,
5795 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5796 gdbarch_byte_order (gdbarch
),
5797 readbuf
, writebuf
, offset
);
5799 return RETURN_VALUE_REGISTER_CONVENTION
;
5803 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5804 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5806 /* A structure or union. Extract the left justified value,
5807 regardless of the byte order. I.e. DO NOT USE
5811 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5812 offset
< TYPE_LENGTH (type
);
5813 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5815 int xfer
= register_size (gdbarch
, regnum
);
5816 if (offset
+ xfer
> TYPE_LENGTH (type
))
5817 xfer
= TYPE_LENGTH (type
) - offset
;
5819 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5820 offset
, xfer
, regnum
);
5821 mips_xfer_register (gdbarch
, regcache
,
5822 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5823 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5825 return RETURN_VALUE_REGISTER_CONVENTION
;
5830 /* A scalar extract each part but least-significant-byte
5831 justified. o32 thinks registers are 4 byte, regardless of
5835 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5836 offset
< TYPE_LENGTH (type
);
5837 offset
+= MIPS32_REGSIZE
, regnum
++)
5839 int xfer
= MIPS32_REGSIZE
;
5840 if (offset
+ xfer
> TYPE_LENGTH (type
))
5841 xfer
= TYPE_LENGTH (type
) - offset
;
5843 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5844 offset
, xfer
, regnum
);
5845 mips_xfer_register (gdbarch
, regcache
,
5846 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5847 gdbarch_byte_order (gdbarch
),
5848 readbuf
, writebuf
, offset
);
5850 return RETURN_VALUE_REGISTER_CONVENTION
;
5854 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5858 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5859 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5861 struct value
**args
, CORE_ADDR sp
,
5862 int struct_return
, CORE_ADDR struct_addr
)
5868 int stack_offset
= 0;
5869 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5870 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5872 /* For shared libraries, "t9" needs to point at the function
5874 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5876 /* Set the return address register to point to the entry point of
5877 the program, where a breakpoint lies in wait. */
5878 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5880 /* First ensure that the stack and structure return address (if any)
5881 are properly aligned. The stack has to be at least 64-bit
5882 aligned even on 32-bit machines, because doubles must be 64-bit
5883 aligned. For n32 and n64, stack frames need to be 128-bit
5884 aligned, so we round to this widest known alignment. */
5886 sp
= align_down (sp
, 16);
5887 struct_addr
= align_down (struct_addr
, 16);
5889 /* Now make space on the stack for the args. */
5890 for (argnum
= 0; argnum
< nargs
; argnum
++)
5892 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5894 /* Allocate space on the stack. */
5895 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5897 sp
-= align_up (len
, 16);
5900 fprintf_unfiltered (gdb_stdlog
,
5901 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5902 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5904 /* Initialize the integer and float register pointers. */
5905 argreg
= MIPS_A0_REGNUM
;
5906 float_argreg
= mips_fpa0_regnum (gdbarch
);
5908 /* The struct_return pointer occupies the first parameter-passing reg. */
5912 fprintf_unfiltered (gdb_stdlog
,
5913 "mips_o64_push_dummy_call: "
5914 "struct_return reg=%d %s\n",
5915 argreg
, paddress (gdbarch
, struct_addr
));
5916 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5917 stack_offset
+= MIPS64_REGSIZE
;
5920 /* Now load as many as possible of the first arguments into
5921 registers, and push the rest onto the stack. Loop thru args
5922 from first to last. */
5923 for (argnum
= 0; argnum
< nargs
; argnum
++)
5925 const gdb_byte
*val
;
5926 struct value
*arg
= args
[argnum
];
5927 struct type
*arg_type
= check_typedef (value_type (arg
));
5928 int len
= TYPE_LENGTH (arg_type
);
5929 enum type_code typecode
= TYPE_CODE (arg_type
);
5932 fprintf_unfiltered (gdb_stdlog
,
5933 "mips_o64_push_dummy_call: %d len=%d type=%d",
5934 argnum
+ 1, len
, (int) typecode
);
5936 val
= value_contents (arg
);
5938 /* Floating point arguments passed in registers have to be
5939 treated specially. On 32-bit architectures, doubles are
5940 passed in register pairs; the even FP register gets the
5941 low word, and the odd FP register gets the high word.
5942 On O64, the first two floating point arguments are also
5943 copied to general registers, because MIPS16 functions
5944 don't use float registers for arguments. This duplication
5945 of arguments in general registers can't hurt non-MIPS16
5946 functions because those registers are normally skipped. */
5948 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5949 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5951 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5953 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5954 float_argreg
, phex (regval
, len
));
5955 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5957 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5958 argreg
, phex (regval
, len
));
5959 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5961 /* Reserve space for the FP register. */
5962 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5966 /* Copy the argument to general registers or the stack in
5967 register-sized pieces. Large arguments are split between
5968 registers and stack. */
5969 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5970 are treated specially: Irix cc passes them in registers
5971 where gcc sometimes puts them on the stack. For maximum
5972 compatibility, we will put them in both places. */
5973 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5974 && len
% MIPS64_REGSIZE
!= 0);
5977 /* Remember if the argument was written to the stack. */
5978 int stack_used_p
= 0;
5979 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5982 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5985 /* Write this portion of the argument to the stack. */
5986 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5987 || odd_sized_struct
)
5989 /* Should shorter than int integer values be
5990 promoted to int before being stored? */
5991 int longword_offset
= 0;
5994 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5996 if ((typecode
== TYPE_CODE_INT
5997 || typecode
== TYPE_CODE_PTR
5998 || typecode
== TYPE_CODE_FLT
)
6000 longword_offset
= MIPS64_REGSIZE
- len
;
6005 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
6006 paddress (gdbarch
, stack_offset
));
6007 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
6008 paddress (gdbarch
, longword_offset
));
6011 addr
= sp
+ stack_offset
+ longword_offset
;
6016 fprintf_unfiltered (gdb_stdlog
, " @%s ",
6017 paddress (gdbarch
, addr
));
6018 for (i
= 0; i
< partial_len
; i
++)
6020 fprintf_unfiltered (gdb_stdlog
, "%02x",
6024 write_memory (addr
, val
, partial_len
);
6027 /* Note!!! This is NOT an else clause. Odd sized
6028 structs may go thru BOTH paths. */
6029 /* Write this portion of the argument to a general
6030 purpose register. */
6031 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6033 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6035 /* Value may need to be sign extended, because
6036 mips_isa_regsize() != mips_abi_regsize(). */
6038 /* A non-floating-point argument being passed in a
6039 general register. If a struct or union, and if
6040 the remaining length is smaller than the register
6041 size, we have to adjust the register value on
6044 It does not seem to be necessary to do the
6045 same for integral types. */
6047 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6048 && partial_len
< MIPS64_REGSIZE
6049 && (typecode
== TYPE_CODE_STRUCT
6050 || typecode
== TYPE_CODE_UNION
))
6051 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6055 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6057 phex (regval
, MIPS64_REGSIZE
));
6058 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6061 /* Prevent subsequent floating point arguments from
6062 being passed in floating point registers. */
6063 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6069 /* Compute the offset into the stack at which we will
6070 copy the next parameter.
6072 In older ABIs, the caller reserved space for
6073 registers that contained arguments. This was loosely
6074 refered to as their "home". Consequently, space is
6075 always allocated. */
6077 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6081 fprintf_unfiltered (gdb_stdlog
, "\n");
6084 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6086 /* Return adjusted stack pointer. */
6090 static enum return_value_convention
6091 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6092 struct type
*type
, struct regcache
*regcache
,
6093 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6095 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6096 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6097 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6098 enum mips_fval_reg fval_reg
;
6100 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6101 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6102 || TYPE_CODE (type
) == TYPE_CODE_UNION
6103 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6104 return RETURN_VALUE_STRUCT_CONVENTION
;
6105 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6107 /* A floating-point value. If reading in or copying, then we get it
6108 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6109 If writing out only, then we put it to both FP0 and GPR2. We do
6110 not support reading in with no function known, if this safety
6111 check ever triggers, then we'll have to try harder. */
6112 gdb_assert (function
|| !readbuf
);
6117 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6120 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6122 case mips_fval_both
:
6123 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6126 if (fval_reg
!= mips_fval_gpr
)
6127 mips_xfer_register (gdbarch
, regcache
,
6128 (gdbarch_num_regs (gdbarch
)
6129 + mips_regnum (gdbarch
)->fp0
),
6131 gdbarch_byte_order (gdbarch
),
6132 readbuf
, writebuf
, 0);
6133 if (fval_reg
!= mips_fval_fpr
)
6134 mips_xfer_register (gdbarch
, regcache
,
6135 gdbarch_num_regs (gdbarch
) + 2,
6137 gdbarch_byte_order (gdbarch
),
6138 readbuf
, writebuf
, 0);
6139 return RETURN_VALUE_REGISTER_CONVENTION
;
6143 /* A scalar extract each part but least-significant-byte
6147 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6148 offset
< TYPE_LENGTH (type
);
6149 offset
+= MIPS64_REGSIZE
, regnum
++)
6151 int xfer
= MIPS64_REGSIZE
;
6152 if (offset
+ xfer
> TYPE_LENGTH (type
))
6153 xfer
= TYPE_LENGTH (type
) - offset
;
6155 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6156 offset
, xfer
, regnum
);
6157 mips_xfer_register (gdbarch
, regcache
,
6158 gdbarch_num_regs (gdbarch
) + regnum
,
6159 xfer
, gdbarch_byte_order (gdbarch
),
6160 readbuf
, writebuf
, offset
);
6162 return RETURN_VALUE_REGISTER_CONVENTION
;
6166 /* Floating point register management.
6168 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6169 64bit operations, these early MIPS cpus treat fp register pairs
6170 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6171 registers and offer a compatibility mode that emulates the MIPS2 fp
6172 model. When operating in MIPS2 fp compat mode, later cpu's split
6173 double precision floats into two 32-bit chunks and store them in
6174 consecutive fp regs. To display 64-bit floats stored in this
6175 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6176 Throw in user-configurable endianness and you have a real mess.
6178 The way this works is:
6179 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6180 double-precision value will be split across two logical registers.
6181 The lower-numbered logical register will hold the low-order bits,
6182 regardless of the processor's endianness.
6183 - If we are on a 64-bit processor, and we are looking for a
6184 single-precision value, it will be in the low ordered bits
6185 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6186 save slot in memory.
6187 - If we are in 64-bit mode, everything is straightforward.
6189 Note that this code only deals with "live" registers at the top of the
6190 stack. We will attempt to deal with saved registers later, when
6191 the raw/cooked register interface is in place. (We need a general
6192 interface that can deal with dynamic saved register sizes -- fp
6193 regs could be 32 bits wide in one frame and 64 on the frame above
6196 /* Copy a 32-bit single-precision value from the current frame
6197 into rare_buffer. */
6200 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6201 gdb_byte
*rare_buffer
)
6203 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6204 int raw_size
= register_size (gdbarch
, regno
);
6205 gdb_byte
*raw_buffer
= alloca (raw_size
);
6207 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6208 error (_("can't read register %d (%s)"),
6209 regno
, gdbarch_register_name (gdbarch
, regno
));
6212 /* We have a 64-bit value for this register. Find the low-order
6216 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6221 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6225 memcpy (rare_buffer
, raw_buffer
, 4);
6229 /* Copy a 64-bit double-precision value from the current frame into
6230 rare_buffer. This may include getting half of it from the next
6234 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6235 gdb_byte
*rare_buffer
)
6237 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6238 int raw_size
= register_size (gdbarch
, regno
);
6240 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6242 /* We have a 64-bit value for this register, and we should use
6244 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6245 error (_("can't read register %d (%s)"),
6246 regno
, gdbarch_register_name (gdbarch
, regno
));
6250 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6252 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6253 internal_error (__FILE__
, __LINE__
,
6254 _("mips_read_fp_register_double: bad access to "
6255 "odd-numbered FP register"));
6257 /* mips_read_fp_register_single will find the correct 32 bits from
6259 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6261 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6262 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6266 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6267 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6273 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6275 { /* Do values for FP (float) regs. */
6276 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6277 gdb_byte
*raw_buffer
;
6278 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6281 raw_buffer
= alloca (2 * register_size (gdbarch
,
6282 mips_regnum (gdbarch
)->fp0
));
6284 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6285 fprintf_filtered (file
, "%*s",
6286 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6289 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6291 struct value_print_options opts
;
6293 /* 4-byte registers: Print hex and floating. Also print even
6294 numbered registers as doubles. */
6295 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6296 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6299 get_formatted_print_options (&opts
, 'x');
6300 print_scalar_formatted (raw_buffer
,
6301 builtin_type (gdbarch
)->builtin_uint32
,
6304 fprintf_filtered (file
, " flt: ");
6306 fprintf_filtered (file
, " <invalid float> ");
6308 fprintf_filtered (file
, "%-17.9g", flt1
);
6310 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6312 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6313 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6316 fprintf_filtered (file
, " dbl: ");
6318 fprintf_filtered (file
, "<invalid double>");
6320 fprintf_filtered (file
, "%-24.17g", doub
);
6325 struct value_print_options opts
;
6327 /* Eight byte registers: print each one as hex, float and double. */
6328 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6329 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6332 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6333 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6336 get_formatted_print_options (&opts
, 'x');
6337 print_scalar_formatted (raw_buffer
,
6338 builtin_type (gdbarch
)->builtin_uint64
,
6341 fprintf_filtered (file
, " flt: ");
6343 fprintf_filtered (file
, "<invalid float>");
6345 fprintf_filtered (file
, "%-17.9g", flt1
);
6347 fprintf_filtered (file
, " dbl: ");
6349 fprintf_filtered (file
, "<invalid double>");
6351 fprintf_filtered (file
, "%-24.17g", doub
);
6356 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6359 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6360 struct value_print_options opts
;
6363 if (mips_float_register_p (gdbarch
, regnum
))
6365 mips_print_fp_register (file
, frame
, regnum
);
6369 val
= get_frame_register_value (frame
, regnum
);
6371 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6373 /* The problem with printing numeric register names (r26, etc.) is that
6374 the user can't use them on input. Probably the best solution is to
6375 fix it so that either the numeric or the funky (a2, etc.) names
6376 are accepted on input. */
6377 if (regnum
< MIPS_NUMREGS
)
6378 fprintf_filtered (file
, "(r%d): ", regnum
);
6380 fprintf_filtered (file
, ": ");
6382 get_formatted_print_options (&opts
, 'x');
6383 val_print_scalar_formatted (value_type (val
),
6384 value_contents_for_printing (val
),
6385 value_embedded_offset (val
),
6390 /* Replacement for generic do_registers_info.
6391 Print regs in pretty columns. */
6394 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6397 fprintf_filtered (file
, " ");
6398 mips_print_fp_register (file
, frame
, regnum
);
6399 fprintf_filtered (file
, "\n");
6404 /* Print a row's worth of GP (int) registers, with name labels above. */
6407 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6410 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6411 /* Do values for GP (int) regs. */
6412 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6413 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6418 /* For GP registers, we print a separate row of names above the vals. */
6419 for (col
= 0, regnum
= start_regnum
;
6420 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6421 + gdbarch_num_pseudo_regs (gdbarch
);
6424 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6425 continue; /* unused register */
6426 if (mips_float_register_p (gdbarch
, regnum
))
6427 break; /* End the row: reached FP register. */
6428 /* Large registers are handled separately. */
6429 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6432 break; /* End the row before this register. */
6434 /* Print this register on a row by itself. */
6435 mips_print_register (file
, frame
, regnum
);
6436 fprintf_filtered (file
, "\n");
6440 fprintf_filtered (file
, " ");
6441 fprintf_filtered (file
,
6442 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6443 gdbarch_register_name (gdbarch
, regnum
));
6450 /* Print the R0 to R31 names. */
6451 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6452 fprintf_filtered (file
, "\n R%-4d",
6453 start_regnum
% gdbarch_num_regs (gdbarch
));
6455 fprintf_filtered (file
, "\n ");
6457 /* Now print the values in hex, 4 or 8 to the row. */
6458 for (col
= 0, regnum
= start_regnum
;
6459 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6460 + gdbarch_num_pseudo_regs (gdbarch
);
6463 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6464 continue; /* unused register */
6465 if (mips_float_register_p (gdbarch
, regnum
))
6466 break; /* End row: reached FP register. */
6467 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6468 break; /* End row: large register. */
6470 /* OK: get the data in raw format. */
6471 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6472 error (_("can't read register %d (%s)"),
6473 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6474 /* pad small registers */
6476 byte
< (mips_abi_regsize (gdbarch
)
6477 - register_size (gdbarch
, regnum
)); byte
++)
6478 printf_filtered (" ");
6479 /* Now print the register value in hex, endian order. */
6480 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6482 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6483 byte
< register_size (gdbarch
, regnum
); byte
++)
6484 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6486 for (byte
= register_size (gdbarch
, regnum
) - 1;
6488 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6489 fprintf_filtered (file
, " ");
6492 if (col
> 0) /* ie. if we actually printed anything... */
6493 fprintf_filtered (file
, "\n");
6498 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6501 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6502 struct frame_info
*frame
, int regnum
, int all
)
6504 if (regnum
!= -1) /* Do one specified register. */
6506 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6507 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6508 error (_("Not a valid register for the current processor type"));
6510 mips_print_register (file
, frame
, regnum
);
6511 fprintf_filtered (file
, "\n");
6514 /* Do all (or most) registers. */
6516 regnum
= gdbarch_num_regs (gdbarch
);
6517 while (regnum
< gdbarch_num_regs (gdbarch
)
6518 + gdbarch_num_pseudo_regs (gdbarch
))
6520 if (mips_float_register_p (gdbarch
, regnum
))
6522 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6523 regnum
= print_fp_register_row (file
, frame
, regnum
);
6525 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6528 regnum
= print_gp_register_row (file
, frame
, regnum
);
6534 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6535 struct frame_info
*frame
)
6537 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6538 CORE_ADDR pc
= get_frame_pc (frame
);
6539 struct address_space
*aspace
;
6545 if ((mips_pc_is_mips (pc
)
6546 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6547 || (mips_pc_is_micromips (gdbarch
, pc
)
6548 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6549 || (mips_pc_is_mips16 (gdbarch
, pc
)
6550 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6553 isa
= mips_pc_isa (gdbarch
, pc
);
6554 /* _has_delay_slot above will have validated the read. */
6555 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6556 size
= mips_insn_size (isa
, insn
);
6557 aspace
= get_frame_address_space (frame
);
6558 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6561 /* To skip prologues, I use this predicate. Returns either PC itself
6562 if the code at PC does not look like a function prologue; otherwise
6563 returns an address that (if we're lucky) follows the prologue. If
6564 LENIENT, then we must skip everything which is involved in setting
6565 up the frame (it's OK to skip more, just so long as we don't skip
6566 anything which might clobber the registers which are being saved.
6567 We must skip more in the case where part of the prologue is in the
6568 delay slot of a non-prologue instruction). */
6571 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6574 CORE_ADDR func_addr
;
6576 /* See if we can determine the end of the prologue via the symbol table.
6577 If so, then return either PC, or the PC after the prologue, whichever
6579 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6581 CORE_ADDR post_prologue_pc
6582 = skip_prologue_using_sal (gdbarch
, func_addr
);
6583 if (post_prologue_pc
!= 0)
6584 return max (pc
, post_prologue_pc
);
6587 /* Can't determine prologue from the symbol table, need to examine
6590 /* Find an upper limit on the function prologue using the debug
6591 information. If the debug information could not be used to provide
6592 that bound, then use an arbitrary large number as the upper bound. */
6593 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6595 limit_pc
= pc
+ 100; /* Magic. */
6597 if (mips_pc_is_mips16 (gdbarch
, pc
))
6598 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6599 else if (mips_pc_is_micromips (gdbarch
, pc
))
6600 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6602 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6605 /* Check whether the PC is in a function epilogue (32-bit version).
6606 This is a helper function for mips_in_function_epilogue_p. */
6608 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6610 CORE_ADDR func_addr
= 0, func_end
= 0;
6612 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6614 /* The MIPS epilogue is max. 12 bytes long. */
6615 CORE_ADDR addr
= func_end
- 12;
6617 if (addr
< func_addr
+ 4)
6618 addr
= func_addr
+ 4;
6622 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6624 unsigned long high_word
;
6627 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6628 high_word
= (inst
>> 16) & 0xffff;
6630 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6631 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6632 && inst
!= 0x03e00008 /* jr $ra */
6633 && inst
!= 0x00000000) /* nop */
6643 /* Check whether the PC is in a function epilogue (microMIPS version).
6644 This is a helper function for mips_in_function_epilogue_p. */
6647 micromips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6649 CORE_ADDR func_addr
= 0;
6650 CORE_ADDR func_end
= 0;
6658 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6661 /* The microMIPS epilogue is max. 12 bytes long. */
6662 addr
= func_end
- 12;
6664 if (addr
< func_addr
+ 2)
6665 addr
= func_addr
+ 2;
6669 for (; pc
< func_end
; pc
+= loc
)
6672 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6673 loc
+= MIPS_INSN16_SIZE
;
6674 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6676 /* 48-bit instructions. */
6677 case 3 * MIPS_INSN16_SIZE
:
6678 /* No epilogue instructions in this category. */
6681 /* 32-bit instructions. */
6682 case 2 * MIPS_INSN16_SIZE
:
6684 insn
|= mips_fetch_instruction (gdbarch
,
6685 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6686 loc
+= MIPS_INSN16_SIZE
;
6687 switch (micromips_op (insn
>> 16))
6689 case 0xc: /* ADDIU: bits 001100 */
6690 case 0x17: /* DADDIU: bits 010111 */
6691 sreg
= b0s5_reg (insn
>> 16);
6692 dreg
= b5s5_reg (insn
>> 16);
6693 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6694 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6695 /* (D)ADDIU $sp, imm */
6705 /* 16-bit instructions. */
6706 case MIPS_INSN16_SIZE
:
6707 switch (micromips_op (insn
))
6709 case 0x3: /* MOVE: bits 000011 */
6710 sreg
= b0s5_reg (insn
);
6711 dreg
= b5s5_reg (insn
);
6712 if (sreg
== 0 && dreg
== 0)
6713 /* MOVE $zero, $zero aka NOP */
6717 case 0x11: /* POOL16C: bits 010001 */
6718 if (b5s5_op (insn
) == 0x18
6719 /* JRADDIUSP: bits 010011 11000 */
6720 || (b5s5_op (insn
) == 0xd
6721 /* JRC: bits 010011 01101 */
6722 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6727 case 0x13: /* POOL16D: bits 010011 */
6728 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6729 if ((insn
& 0x1) == 0x1
6730 /* ADDIUSP: bits 010011 1 */
6744 /* Check whether the PC is in a function epilogue (16-bit version).
6745 This is a helper function for mips_in_function_epilogue_p. */
6747 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6749 CORE_ADDR func_addr
= 0, func_end
= 0;
6751 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6753 /* The MIPS epilogue is max. 12 bytes long. */
6754 CORE_ADDR addr
= func_end
- 12;
6756 if (addr
< func_addr
+ 4)
6757 addr
= func_addr
+ 4;
6761 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6763 unsigned short inst
;
6765 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6767 if ((inst
& 0xf800) == 0xf000) /* extend */
6770 if (inst
!= 0x6300 /* addiu $sp,offset */
6771 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6772 && inst
!= 0xe820 /* jr $ra */
6773 && inst
!= 0xe8a0 /* jrc $ra */
6774 && inst
!= 0x6500) /* nop */
6784 /* The epilogue is defined here as the area at the end of a function,
6785 after an instruction which destroys the function's stack frame. */
6787 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6789 if (mips_pc_is_mips16 (gdbarch
, pc
))
6790 return mips16_in_function_epilogue_p (gdbarch
, pc
);
6791 else if (mips_pc_is_micromips (gdbarch
, pc
))
6792 return micromips_in_function_epilogue_p (gdbarch
, pc
);
6794 return mips32_in_function_epilogue_p (gdbarch
, pc
);
6797 /* Root of all "set mips "/"show mips " commands. This will eventually be
6798 used for all MIPS-specific commands. */
6801 show_mips_command (char *args
, int from_tty
)
6803 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6807 set_mips_command (char *args
, int from_tty
)
6810 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6811 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6814 /* Commands to show/set the MIPS FPU type. */
6817 show_mipsfpu_command (char *args
, int from_tty
)
6821 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6824 ("The MIPS floating-point coprocessor is unknown "
6825 "because the current architecture is not MIPS.\n");
6829 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6831 case MIPS_FPU_SINGLE
:
6832 fpu
= "single-precision";
6834 case MIPS_FPU_DOUBLE
:
6835 fpu
= "double-precision";
6838 fpu
= "absent (none)";
6841 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6843 if (mips_fpu_type_auto
)
6844 printf_unfiltered ("The MIPS floating-point coprocessor "
6845 "is set automatically (currently %s)\n",
6849 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6854 set_mipsfpu_command (char *args
, int from_tty
)
6856 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6857 "\"single\",\"none\" or \"auto\".\n");
6858 show_mipsfpu_command (args
, from_tty
);
6862 set_mipsfpu_single_command (char *args
, int from_tty
)
6864 struct gdbarch_info info
;
6865 gdbarch_info_init (&info
);
6866 mips_fpu_type
= MIPS_FPU_SINGLE
;
6867 mips_fpu_type_auto
= 0;
6868 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6869 instead of relying on globals. Doing that would let generic code
6870 handle the search for this specific architecture. */
6871 if (!gdbarch_update_p (info
))
6872 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6876 set_mipsfpu_double_command (char *args
, int from_tty
)
6878 struct gdbarch_info info
;
6879 gdbarch_info_init (&info
);
6880 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6881 mips_fpu_type_auto
= 0;
6882 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6883 instead of relying on globals. Doing that would let generic code
6884 handle the search for this specific architecture. */
6885 if (!gdbarch_update_p (info
))
6886 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6890 set_mipsfpu_none_command (char *args
, int from_tty
)
6892 struct gdbarch_info info
;
6893 gdbarch_info_init (&info
);
6894 mips_fpu_type
= MIPS_FPU_NONE
;
6895 mips_fpu_type_auto
= 0;
6896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6897 instead of relying on globals. Doing that would let generic code
6898 handle the search for this specific architecture. */
6899 if (!gdbarch_update_p (info
))
6900 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6904 set_mipsfpu_auto_command (char *args
, int from_tty
)
6906 mips_fpu_type_auto
= 1;
6909 /* Attempt to identify the particular processor model by reading the
6910 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6911 the relevant processor still exists (it dates back to '94) and
6912 secondly this is not the way to do this. The processor type should
6913 be set by forcing an architecture change. */
6916 deprecated_mips_set_processor_regs_hack (void)
6918 struct regcache
*regcache
= get_current_regcache ();
6919 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6920 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6923 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
6924 if ((prid
& ~0xf) == 0x700)
6925 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
6928 /* Just like reinit_frame_cache, but with the right arguments to be
6929 callable as an sfunc. */
6932 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6933 struct cmd_list_element
*c
)
6935 reinit_frame_cache ();
6939 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6941 struct gdbarch
*gdbarch
= info
->application_data
;
6943 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6944 disassembler needs to be able to locally determine the ISA, and
6945 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6947 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6948 info
->mach
= bfd_mach_mips16
;
6949 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6950 info
->mach
= bfd_mach_mips_micromips
;
6952 /* Round down the instruction address to the appropriate boundary. */
6953 memaddr
&= (info
->mach
== bfd_mach_mips16
6954 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6956 /* Set the disassembler options. */
6957 if (!info
->disassembler_options
)
6958 /* This string is not recognized explicitly by the disassembler,
6959 but it tells the disassembler to not try to guess the ABI from
6960 the bfd elf headers, such that, if the user overrides the ABI
6961 of a program linked as NewABI, the disassembly will follow the
6962 register naming conventions specified by the user. */
6963 info
->disassembler_options
= "gpr-names=32";
6965 /* Call the appropriate disassembler based on the target endian-ness. */
6966 if (info
->endian
== BFD_ENDIAN_BIG
)
6967 return print_insn_big_mips (memaddr
, info
);
6969 return print_insn_little_mips (memaddr
, info
);
6973 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
6975 /* Set up the disassembler info, so that we get the right
6976 register names from libopcodes. */
6977 info
->disassembler_options
= "gpr-names=n32";
6978 info
->flavour
= bfd_target_elf_flavour
;
6980 return gdb_print_insn_mips (memaddr
, info
);
6984 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
6986 /* Set up the disassembler info, so that we get the right
6987 register names from libopcodes. */
6988 info
->disassembler_options
= "gpr-names=64";
6989 info
->flavour
= bfd_target_elf_flavour
;
6991 return gdb_print_insn_mips (memaddr
, info
);
6994 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6995 program counter value to determine whether a 16- or 32-bit breakpoint
6996 should be used. It returns a pointer to a string of bytes that encode a
6997 breakpoint instruction, stores the length of the string to *lenptr, and
6998 adjusts pc (if necessary) to point to the actual memory location where
6999 the breakpoint should be inserted. */
7001 static const gdb_byte
*
7002 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
7003 CORE_ADDR
*pcptr
, int *lenptr
)
7005 CORE_ADDR pc
= *pcptr
;
7007 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7009 if (mips_pc_is_mips16 (gdbarch
, pc
))
7011 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7012 *pcptr
= unmake_compact_addr (pc
);
7013 *lenptr
= sizeof (mips16_big_breakpoint
);
7014 return mips16_big_breakpoint
;
7016 else if (mips_pc_is_micromips (gdbarch
, pc
))
7018 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7019 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7024 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7026 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7027 *pcptr
= unmake_compact_addr (pc
);
7029 return (size
== 2) ? micromips16_big_breakpoint
7030 : micromips32_big_breakpoint
;
7034 /* The IDT board uses an unusual breakpoint value, and
7035 sometimes gets confused when it sees the usual MIPS
7036 breakpoint instruction. */
7037 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7038 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
7039 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
7040 /* Likewise, IRIX appears to expect a different breakpoint,
7041 although this is not apparent until you try to use pthreads. */
7042 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
7044 *lenptr
= sizeof (big_breakpoint
);
7046 if (strcmp (target_shortname
, "mips") == 0)
7047 return idt_big_breakpoint
;
7048 else if (strcmp (target_shortname
, "ddb") == 0
7049 || strcmp (target_shortname
, "pmon") == 0
7050 || strcmp (target_shortname
, "lsi") == 0)
7051 return pmon_big_breakpoint
;
7052 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
7053 return irix_big_breakpoint
;
7055 return big_breakpoint
;
7060 if (mips_pc_is_mips16 (gdbarch
, pc
))
7062 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7063 *pcptr
= unmake_compact_addr (pc
);
7064 *lenptr
= sizeof (mips16_little_breakpoint
);
7065 return mips16_little_breakpoint
;
7067 else if (mips_pc_is_micromips (gdbarch
, pc
))
7069 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7070 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7075 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7077 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7078 *pcptr
= unmake_compact_addr (pc
);
7080 return (size
== 2) ? micromips16_little_breakpoint
7081 : micromips32_little_breakpoint
;
7085 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7086 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
7087 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
7089 *lenptr
= sizeof (little_breakpoint
);
7091 if (strcmp (target_shortname
, "mips") == 0)
7092 return idt_little_breakpoint
;
7093 else if (strcmp (target_shortname
, "ddb") == 0
7094 || strcmp (target_shortname
, "pmon") == 0
7095 || strcmp (target_shortname
, "lsi") == 0)
7096 return pmon_little_breakpoint
;
7098 return little_breakpoint
;
7103 /* Determine the remote breakpoint kind suitable for the PC. The following
7106 * 2 -- 16-bit MIPS16 mode breakpoint,
7108 * 3 -- 16-bit microMIPS mode breakpoint,
7110 * 4 -- 32-bit standard MIPS mode breakpoint,
7112 * 5 -- 32-bit microMIPS mode breakpoint. */
7115 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7118 CORE_ADDR pc
= *pcptr
;
7120 if (mips_pc_is_mips16 (gdbarch
, pc
))
7122 *pcptr
= unmake_compact_addr (pc
);
7125 else if (mips_pc_is_micromips (gdbarch
, pc
))
7131 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7132 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7133 *pcptr
= unmake_compact_addr (pc
);
7134 *kindptr
= size
| 1;
7140 /* Return non-zero if the standard MIPS instruction INST has a branch
7141 delay slot (i.e. it is a jump or branch instruction). This function
7142 is based on mips32_next_pc. */
7145 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7151 op
= itype_op (inst
);
7152 if ((inst
& 0xe0000000) != 0)
7154 rs
= itype_rs (inst
);
7155 rt
= itype_rt (inst
);
7156 return (is_octeon_bbit_op (op
, gdbarch
)
7157 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7158 || op
== 29 /* JALX: bits 011101 */
7161 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7162 || (rs
== 9 && (rt
& 0x2) == 0)
7163 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7164 || (rs
== 10 && (rt
& 0x2) == 0))));
7165 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7168 switch (op
& 0x07) /* extract bits 28,27,26 */
7170 case 0: /* SPECIAL */
7171 op
= rtype_funct (inst
);
7172 return (op
== 8 /* JR */
7173 || op
== 9); /* JALR */
7174 break; /* end SPECIAL */
7175 case 1: /* REGIMM */
7176 rs
= itype_rs (inst
);
7177 rt
= itype_rt (inst
); /* branch condition */
7178 return ((rt
& 0xc) == 0
7179 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7180 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7181 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7182 /* BPOSGE32, BPOSGE64: bits 1110x */
7183 break; /* end REGIMM */
7184 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7190 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7191 delay slot (i.e. it is a jump or branch instruction). */
7194 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7199 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7203 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7206 /* Return non-zero if the microMIPS instruction INSN, comprising the
7207 16-bit major opcode word in the high 16 bits and any second word
7208 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7209 jump or branch instruction). The instruction must be 32-bit if
7210 MUSTBE32 is set or can be any instruction otherwise. */
7213 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7215 ULONGEST major
= insn
>> 16;
7217 switch (micromips_op (major
))
7219 /* 16-bit instructions. */
7220 case 0x33: /* B16: bits 110011 */
7221 case 0x2b: /* BNEZ16: bits 101011 */
7222 case 0x23: /* BEQZ16: bits 100011 */
7224 case 0x11: /* POOL16C: bits 010001 */
7226 && ((b5s5_op (major
) == 0xc
7227 /* JR16: bits 010001 01100 */
7228 || (b5s5_op (major
) & 0x1e) == 0xe)));
7229 /* JALR16, JALRS16: bits 010001 0111x */
7230 /* 32-bit instructions. */
7231 case 0x3d: /* JAL: bits 111101 */
7232 case 0x3c: /* JALX: bits 111100 */
7233 case 0x35: /* J: bits 110101 */
7234 case 0x2d: /* BNE: bits 101101 */
7235 case 0x25: /* BEQ: bits 100101 */
7236 case 0x1d: /* JALS: bits 011101 */
7238 case 0x10: /* POOL32I: bits 010000 */
7239 return ((b5s5_op (major
) & 0x1c) == 0x0
7240 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7241 || (b5s5_op (major
) & 0x1d) == 0x4
7242 /* BLEZ, BGTZ: bits 010000 001x0 */
7243 || (b5s5_op (major
) & 0x1d) == 0x11
7244 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7245 || ((b5s5_op (major
) & 0x1e) == 0x14
7246 && (major
& 0x3) == 0x0)
7247 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7248 || (b5s5_op (major
) & 0x1e) == 0x1a
7249 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7250 || ((b5s5_op (major
) & 0x1e) == 0x1c
7251 && (major
& 0x3) == 0x0)
7252 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7253 || ((b5s5_op (major
) & 0x1c) == 0x1c
7254 && (major
& 0x3) == 0x1));
7255 /* BC1ANY*: bits 010000 111xx xxx01 */
7256 case 0x0: /* POOL32A: bits 000000 */
7257 return (b0s6_op (insn
) == 0x3c
7258 /* POOL32Axf: bits 000000 ... 111100 */
7259 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7260 /* JALR, JALR.HB: 000000 000x111100 111100 */
7261 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7267 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7268 slot (i.e. it is a non-compact jump instruction). The instruction
7269 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7272 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7273 CORE_ADDR addr
, int mustbe32
)
7278 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7282 if (mips_insn_size (ISA_MICROMIPS
, insn
) == 2 * MIPS_INSN16_SIZE
)
7284 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7289 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7292 /* Return non-zero if the MIPS16 instruction INST, which must be
7293 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7294 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7295 instruction). This function is based on mips16_next_pc. */
7298 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7300 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7302 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7305 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7306 slot (i.e. it is a non-compact jump instruction). The instruction
7307 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7310 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7311 CORE_ADDR addr
, int mustbe32
)
7313 unsigned short insn
;
7316 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7320 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7323 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7324 This assumes KSSEG exists. */
7327 mips_segment_boundary (CORE_ADDR bpaddr
)
7329 CORE_ADDR mask
= CORE_ADDR_MAX
;
7332 if (sizeof (CORE_ADDR
) == 8)
7333 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7334 a compiler warning produced where CORE_ADDR is a 32-bit type even
7335 though in that case this is dead code). */
7336 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7339 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7340 segsize
= 29; /* 32-bit compatibility segment */
7342 segsize
= 62; /* xkseg */
7344 case 2: /* xkphys */
7347 default: /* xksseg (1), xkuseg/kuseg (0) */
7351 else if (bpaddr
& 0x80000000) /* kernel segment */
7354 segsize
= 31; /* user segment */
7356 return bpaddr
& mask
;
7359 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7360 it backwards if necessary. Return the address of the new location. */
7363 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7365 CORE_ADDR prev_addr
;
7367 CORE_ADDR func_addr
;
7369 /* If a breakpoint is set on the instruction in a branch delay slot,
7370 GDB gets confused. When the breakpoint is hit, the PC isn't on
7371 the instruction in the branch delay slot, the PC will point to
7372 the branch instruction. Since the PC doesn't match any known
7373 breakpoints, GDB reports a trap exception.
7375 There are two possible fixes for this problem.
7377 1) When the breakpoint gets hit, see if the BD bit is set in the
7378 Cause register (which indicates the last exception occurred in a
7379 branch delay slot). If the BD bit is set, fix the PC to point to
7380 the instruction in the branch delay slot.
7382 2) When the user sets the breakpoint, don't allow him to set the
7383 breakpoint on the instruction in the branch delay slot. Instead
7384 move the breakpoint to the branch instruction (which will have
7387 The problem with the first solution is that if the user then
7388 single-steps the processor, the branch instruction will get
7389 skipped (since GDB thinks the PC is on the instruction in the
7392 So, we'll use the second solution. To do this we need to know if
7393 the instruction we're trying to set the breakpoint on is in the
7394 branch delay slot. */
7396 boundary
= mips_segment_boundary (bpaddr
);
7398 /* Make sure we don't scan back before the beginning of the current
7399 function, since we may fetch constant data or insns that look like
7400 a jump. Of course we might do that anyway if the compiler has
7401 moved constants inline. :-( */
7402 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7403 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7404 boundary
= func_addr
;
7406 if (mips_pc_is_mips (bpaddr
))
7408 if (bpaddr
== boundary
)
7411 /* If the previous instruction has a branch delay slot, we have
7412 to move the breakpoint to the branch instruction. */
7413 prev_addr
= bpaddr
- 4;
7414 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7419 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7420 CORE_ADDR addr
, jmpaddr
;
7423 boundary
= unmake_compact_addr (boundary
);
7425 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7426 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7427 so try for that first, then try the 2 byte JALR/JR.
7428 The microMIPS ASE has a whole range of jumps and branches
7429 with delay slots, some of which take 4 bytes and some take
7430 2 bytes, so the idea is the same.
7431 FIXME: We have to assume that bpaddr is not the second half
7432 of an extended instruction. */
7433 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7434 ? micromips_insn_at_pc_has_delay_slot
7435 : mips16_insn_at_pc_has_delay_slot
);
7439 for (i
= 1; i
< 4; i
++)
7441 if (unmake_compact_addr (addr
) == boundary
)
7443 addr
-= MIPS_INSN16_SIZE
;
7444 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7445 /* Looks like a JR/JALR at [target-1], but it could be
7446 the second word of a previous JAL/JALX, so record it
7447 and check back one more. */
7449 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7452 /* Looks like a JAL/JALX at [target-2], but it could also
7453 be the second word of a previous JAL/JALX, record it,
7454 and check back one more. */
7457 /* Looks like a JAL/JALX at [target-3], so any previously
7458 recorded JAL/JALX or JR/JALR must be wrong, because:
7461 -2: JAL-ext (can't be JAL/JALX)
7462 -1: bdslot (can't be JR/JALR)
7465 Of course it could be another JAL-ext which looks
7466 like a JAL, but in that case we'd have broken out
7467 of this loop at [target-2]:
7471 -2: bdslot (can't be jmp)
7478 /* Not a jump instruction: if we're at [target-1] this
7479 could be the second word of a JAL/JALX, so continue;
7480 otherwise we're done. */
7493 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7494 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7497 mips_is_stub_suffix (const char *suffix
, int zero
)
7502 return zero
&& suffix
[1] == '\0';
7504 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7509 return suffix
[1] == '\0';
7515 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7516 call stubs, one of sf, df, sc, or dc. */
7519 mips_is_stub_mode (const char *mode
)
7521 return ((mode
[0] == 's' || mode
[0] == 'd')
7522 && (mode
[1] == 'f' || mode
[1] == 'c'));
7525 /* Code at PC is a compiler-generated stub. Such a stub for a function
7526 bar might have a name like __fn_stub_bar, and might look like this:
7533 followed by (or interspersed with):
7540 addiu $25, $25, %lo(bar)
7543 ($1 may be used in old code; for robustness we accept any register)
7546 lui $28, %hi(_gp_disp)
7547 addiu $28, $28, %lo(_gp_disp)
7550 addiu $25, $25, %lo(bar)
7553 In the case of a __call_stub_bar stub, the sequence to set up
7554 arguments might look like this:
7561 followed by (or interspersed with) one of the jump sequences above.
7563 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7564 of J or JR, respectively, followed by:
7570 We are at the beginning of the stub here, and scan down and extract
7571 the target address from the jump immediate instruction or, if a jump
7572 register instruction is used, from the register referred. Return
7573 the value of PC calculated or 0 if inconclusive.
7575 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7578 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7580 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7581 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7582 int addrreg
= MIPS_ZERO_REGNUM
;
7583 CORE_ADDR start_pc
= pc
;
7584 CORE_ADDR target_pc
= 0;
7591 status
== 0 && target_pc
== 0 && i
< 20;
7592 i
++, pc
+= MIPS_INSN32_SIZE
)
7594 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7600 switch (itype_op (inst
))
7602 case 0: /* SPECIAL */
7603 switch (rtype_funct (inst
))
7607 rs
= rtype_rs (inst
);
7608 if (rs
== MIPS_GP_REGNUM
)
7609 target_pc
= gp
; /* Hmm... */
7610 else if (rs
== addrreg
)
7614 case 0x21: /* ADDU */
7615 rt
= rtype_rt (inst
);
7616 rs
= rtype_rs (inst
);
7617 rd
= rtype_rd (inst
);
7618 if (rd
== MIPS_GP_REGNUM
7619 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7620 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7628 target_pc
= jtype_target (inst
) << 2;
7629 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7633 rt
= itype_rt (inst
);
7634 rs
= itype_rs (inst
);
7637 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7638 if (rt
== MIPS_GP_REGNUM
)
7640 else if (rt
== addrreg
)
7646 rt
= itype_rt (inst
);
7647 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7648 if (rt
== MIPS_GP_REGNUM
)
7650 else if (rt
!= MIPS_ZERO_REGNUM
)
7658 rt
= itype_rt (inst
);
7659 rs
= itype_rs (inst
);
7660 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7661 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7665 memset (buf
, 0, sizeof (buf
));
7666 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7668 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7677 /* If PC is in a MIPS16 call or return stub, return the address of the
7678 target PC, which is either the callee or the caller. There are several
7679 cases which must be handled:
7681 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7682 and the target PC is in $31 ($ra).
7683 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7684 and the target PC is in $2.
7685 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7686 i.e. before the JALR instruction, this is effectively a call stub
7687 and the target PC is in $2. Otherwise this is effectively
7688 a return stub and the target PC is in $18.
7689 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7690 JAL or JALR instruction, this is effectively a call stub and the
7691 target PC is buried in the instruction stream. Otherwise this
7692 is effectively a return stub and the target PC is in $18.
7693 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7694 stub and the target PC is buried in the instruction stream.
7696 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7697 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7701 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7703 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7704 CORE_ADDR start_addr
;
7708 /* Find the starting address and name of the function containing the PC. */
7709 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7712 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7713 and the target PC is in $31 ($ra). */
7714 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7715 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7716 && mips_is_stub_mode (name
+ prefixlen
)
7717 && name
[prefixlen
+ 2] == '\0')
7718 return get_frame_register_signed
7719 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7721 /* If the PC is in __mips16_call_stub_*, this is one of the call
7722 call/return stubs. */
7723 prefixlen
= strlen (mips_str_mips16_call_stub
);
7724 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7726 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7727 and the target PC is in $2. */
7728 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7729 return get_frame_register_signed
7730 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7732 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7733 i.e. before the JALR instruction, this is effectively a call stub
7734 and the target PC is in $2. Otherwise this is effectively
7735 a return stub and the target PC is in $18. */
7736 else if (mips_is_stub_mode (name
+ prefixlen
)
7737 && name
[prefixlen
+ 2] == '_'
7738 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7740 if (pc
== start_addr
)
7741 /* This is the 'call' part of a call stub. The return
7742 address is in $2. */
7743 return get_frame_register_signed
7744 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7746 /* This is the 'return' part of a call stub. The return
7747 address is in $18. */
7748 return get_frame_register_signed
7749 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7752 return 0; /* Not a stub. */
7755 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7756 compiler-generated call or call/return stubs. */
7757 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
7758 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
7760 if (pc
== start_addr
)
7761 /* This is the 'call' part of a call stub. Call this helper
7762 to scan through this code for interesting instructions
7763 and determine the final PC. */
7764 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7766 /* This is the 'return' part of a call stub. The return address
7768 return get_frame_register_signed
7769 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7772 return 0; /* Not a stub. */
7775 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7776 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7779 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7781 CORE_ADDR start_addr
;
7784 /* Find the starting address of the function containing the PC. */
7785 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7788 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7789 the start, i.e. after the JALR instruction, this is effectively
7791 prefixlen
= strlen (mips_str_mips16_call_stub
);
7792 if (pc
!= start_addr
7793 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7794 && mips_is_stub_mode (name
+ prefixlen
)
7795 && name
[prefixlen
+ 2] == '_'
7796 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7799 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7800 the JAL or JALR instruction, this is effectively a return stub. */
7801 prefixlen
= strlen (mips_str_call_fp_stub
);
7802 if (pc
!= start_addr
7803 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7806 /* Consume the .pic. prefix of any PIC stub, this function must return
7807 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7808 or the call stub path will trigger in handle_inferior_event causing
7810 prefixlen
= strlen (mips_str_pic
);
7811 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7814 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7815 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7816 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7817 && mips_is_stub_mode (name
+ prefixlen
)
7818 && name
[prefixlen
+ 2] == '\0')
7821 return 0; /* Not a stub. */
7824 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7825 PC of the stub target. The stub just loads $t9 and jumps to it,
7826 so that $t9 has the correct value at function entry. */
7829 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7831 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7832 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7833 struct bound_minimal_symbol msym
;
7835 gdb_byte stub_code
[16];
7836 int32_t stub_words
[4];
7838 /* The stub for foo is named ".pic.foo", and is either two
7839 instructions inserted before foo or a three instruction sequence
7840 which jumps to foo. */
7841 msym
= lookup_minimal_symbol_by_pc (pc
);
7842 if (msym
.minsym
== NULL
7843 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7844 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7845 || strncmp (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) != 0)
7848 /* A two-instruction header. */
7849 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7852 /* A three-instruction (plus delay slot) trampoline. */
7853 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7855 if (target_read_memory (pc
, stub_code
, 16) != 0)
7857 for (i
= 0; i
< 4; i
++)
7858 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7861 /* A stub contains these instructions:
7864 addiu t9, t9, %lo(target)
7867 This works even for N64, since stubs are only generated with
7869 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7870 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7871 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7872 && stub_words
[3] == 0x00000000)
7873 return ((((stub_words
[0] & 0x0000ffff) << 16)
7874 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7877 /* Not a recognized stub. */
7882 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7884 CORE_ADDR requested_pc
= pc
;
7885 CORE_ADDR target_pc
;
7892 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7896 new_pc
= find_solib_trampoline_target (frame
, pc
);
7900 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7904 while (pc
!= target_pc
);
7906 return pc
!= requested_pc
? pc
: 0;
7909 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7910 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7913 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7916 if (num
>= 0 && num
< 32)
7918 else if (num
>= 38 && num
< 70)
7919 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7921 regnum
= mips_regnum (gdbarch
)->hi
;
7923 regnum
= mips_regnum (gdbarch
)->lo
;
7924 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7925 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7927 /* This will hopefully (eventually) provoke a warning. Should
7928 we be calling complaint() here? */
7929 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7930 return gdbarch_num_regs (gdbarch
) + regnum
;
7934 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7935 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7938 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7941 if (num
>= 0 && num
< 32)
7943 else if (num
>= 32 && num
< 64)
7944 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7946 regnum
= mips_regnum (gdbarch
)->hi
;
7948 regnum
= mips_regnum (gdbarch
)->lo
;
7949 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7950 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7952 /* This will hopefully (eventually) provoke a warning. Should we
7953 be calling complaint() here? */
7954 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7955 return gdbarch_num_regs (gdbarch
) + regnum
;
7959 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7961 /* Only makes sense to supply raw registers. */
7962 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7963 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7964 decide if it is valid. Should instead define a standard sim/gdb
7965 register numbering scheme. */
7966 if (gdbarch_register_name (gdbarch
,
7967 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7968 && gdbarch_register_name (gdbarch
,
7969 gdbarch_num_regs (gdbarch
)
7970 + regnum
)[0] != '\0')
7973 return LEGACY_SIM_REGNO_IGNORE
;
7977 /* Convert an integer into an address. Extracting the value signed
7978 guarantees a correctly sign extended address. */
7981 mips_integer_to_address (struct gdbarch
*gdbarch
,
7982 struct type
*type
, const gdb_byte
*buf
)
7984 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7985 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7988 /* Dummy virtual frame pointer method. This is no more or less accurate
7989 than most other architectures; we just need to be explicit about it,
7990 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7991 an assertion failure. */
7994 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7995 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7997 *reg
= MIPS_SP_REGNUM
;
8002 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
8004 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
8005 const char *name
= bfd_get_section_name (abfd
, sect
);
8007 if (*abip
!= MIPS_ABI_UNKNOWN
)
8010 if (strncmp (name
, ".mdebug.", 8) != 0)
8013 if (strcmp (name
, ".mdebug.abi32") == 0)
8014 *abip
= MIPS_ABI_O32
;
8015 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8016 *abip
= MIPS_ABI_N32
;
8017 else if (strcmp (name
, ".mdebug.abi64") == 0)
8018 *abip
= MIPS_ABI_N64
;
8019 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8020 *abip
= MIPS_ABI_O64
;
8021 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8022 *abip
= MIPS_ABI_EABI32
;
8023 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8024 *abip
= MIPS_ABI_EABI64
;
8026 warning (_("unsupported ABI %s."), name
+ 8);
8030 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8032 int *lbp
= (int *) obj
;
8033 const char *name
= bfd_get_section_name (abfd
, sect
);
8035 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
8037 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
8039 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
8040 warning (_("unrecognized .gcc_compiled_longXX"));
8043 static enum mips_abi
8044 global_mips_abi (void)
8048 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8049 if (mips_abi_strings
[i
] == mips_abi_string
)
8050 return (enum mips_abi
) i
;
8052 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8055 /* Return the default compressed instruction set, either of MIPS16
8056 or microMIPS, selected when none could have been determined from
8057 the ELF header of the binary being executed (or no binary has been
8060 static enum mips_isa
8061 global_mips_compression (void)
8065 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8066 if (mips_compression_strings
[i
] == mips_compression_string
)
8067 return (enum mips_isa
) i
;
8069 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8073 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8075 /* If the size matches the set of 32-bit or 64-bit integer registers,
8076 assume that's what we've got. */
8077 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8078 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8080 /* If the size matches the full set of registers GDB traditionally
8081 knows about, including floating point, for either 32-bit or
8082 64-bit, assume that's what we've got. */
8083 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8084 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8086 /* Otherwise we don't have a useful guess. */
8089 static struct value
*
8090 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8092 const int *reg_p
= baton
;
8093 return value_of_register (*reg_p
, frame
);
8096 static struct gdbarch
*
8097 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8099 struct gdbarch
*gdbarch
;
8100 struct gdbarch_tdep
*tdep
;
8102 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8104 enum mips_fpu_type fpu_type
;
8105 struct tdesc_arch_data
*tdesc_data
= NULL
;
8106 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8107 const char **reg_names
;
8108 struct mips_regnum mips_regnum
, *regnum
;
8109 enum mips_isa mips_isa
;
8113 /* Fill in the OS dependent register numbers and names. */
8114 if (info
.osabi
== GDB_OSABI_IRIX
)
8116 mips_regnum
.fp0
= 32;
8117 mips_regnum
.pc
= 64;
8118 mips_regnum
.cause
= 65;
8119 mips_regnum
.badvaddr
= 66;
8120 mips_regnum
.hi
= 67;
8121 mips_regnum
.lo
= 68;
8122 mips_regnum
.fp_control_status
= 69;
8123 mips_regnum
.fp_implementation_revision
= 70;
8124 mips_regnum
.dspacc
= dspacc
= -1;
8125 mips_regnum
.dspctl
= dspctl
= -1;
8127 reg_names
= mips_irix_reg_names
;
8129 else if (info
.osabi
== GDB_OSABI_LINUX
)
8131 mips_regnum
.fp0
= 38;
8132 mips_regnum
.pc
= 37;
8133 mips_regnum
.cause
= 36;
8134 mips_regnum
.badvaddr
= 35;
8135 mips_regnum
.hi
= 34;
8136 mips_regnum
.lo
= 33;
8137 mips_regnum
.fp_control_status
= 70;
8138 mips_regnum
.fp_implementation_revision
= 71;
8139 mips_regnum
.dspacc
= -1;
8140 mips_regnum
.dspctl
= -1;
8144 reg_names
= mips_linux_reg_names
;
8148 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8149 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8150 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8151 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8152 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8153 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8154 mips_regnum
.fp_control_status
= 70;
8155 mips_regnum
.fp_implementation_revision
= 71;
8156 mips_regnum
.dspacc
= dspacc
= -1;
8157 mips_regnum
.dspctl
= dspctl
= -1;
8158 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8159 if (info
.bfd_arch_info
!= NULL
8160 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8161 reg_names
= mips_tx39_reg_names
;
8163 reg_names
= mips_generic_reg_names
;
8166 /* Check any target description for validity. */
8167 if (tdesc_has_registers (info
.target_desc
))
8169 static const char *const mips_gprs
[] = {
8170 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8172 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8173 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8175 static const char *const mips_fprs
[] = {
8176 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8177 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8178 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8179 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8182 const struct tdesc_feature
*feature
;
8185 feature
= tdesc_find_feature (info
.target_desc
,
8186 "org.gnu.gdb.mips.cpu");
8187 if (feature
== NULL
)
8190 tdesc_data
= tdesc_data_alloc ();
8193 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8194 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8198 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8199 mips_regnum
.lo
, "lo");
8200 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8201 mips_regnum
.hi
, "hi");
8202 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8203 mips_regnum
.pc
, "pc");
8207 tdesc_data_cleanup (tdesc_data
);
8211 feature
= tdesc_find_feature (info
.target_desc
,
8212 "org.gnu.gdb.mips.cp0");
8213 if (feature
== NULL
)
8215 tdesc_data_cleanup (tdesc_data
);
8220 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8221 mips_regnum
.badvaddr
, "badvaddr");
8222 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8223 MIPS_PS_REGNUM
, "status");
8224 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8225 mips_regnum
.cause
, "cause");
8229 tdesc_data_cleanup (tdesc_data
);
8233 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8234 backend is not prepared for that, though. */
8235 feature
= tdesc_find_feature (info
.target_desc
,
8236 "org.gnu.gdb.mips.fpu");
8237 if (feature
== NULL
)
8239 tdesc_data_cleanup (tdesc_data
);
8244 for (i
= 0; i
< 32; i
++)
8245 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8246 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8248 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8249 mips_regnum
.fp_control_status
,
8252 &= tdesc_numbered_register (feature
, tdesc_data
,
8253 mips_regnum
.fp_implementation_revision
,
8258 tdesc_data_cleanup (tdesc_data
);
8264 feature
= tdesc_find_feature (info
.target_desc
,
8265 "org.gnu.gdb.mips.dsp");
8266 /* The DSP registers are optional; it's OK if they are absent. */
8267 if (feature
!= NULL
)
8271 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8272 dspacc
+ i
++, "hi1");
8273 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8274 dspacc
+ i
++, "lo1");
8275 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8276 dspacc
+ i
++, "hi2");
8277 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8278 dspacc
+ i
++, "lo2");
8279 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8280 dspacc
+ i
++, "hi3");
8281 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8282 dspacc
+ i
++, "lo3");
8284 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8289 tdesc_data_cleanup (tdesc_data
);
8293 mips_regnum
.dspacc
= dspacc
;
8294 mips_regnum
.dspctl
= dspctl
;
8298 /* It would be nice to detect an attempt to use a 64-bit ABI
8299 when only 32-bit registers are provided. */
8303 /* First of all, extract the elf_flags, if available. */
8304 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8305 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8306 else if (arches
!= NULL
)
8307 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8311 fprintf_unfiltered (gdb_stdlog
,
8312 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8314 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8315 switch ((elf_flags
& EF_MIPS_ABI
))
8317 case E_MIPS_ABI_O32
:
8318 found_abi
= MIPS_ABI_O32
;
8320 case E_MIPS_ABI_O64
:
8321 found_abi
= MIPS_ABI_O64
;
8323 case E_MIPS_ABI_EABI32
:
8324 found_abi
= MIPS_ABI_EABI32
;
8326 case E_MIPS_ABI_EABI64
:
8327 found_abi
= MIPS_ABI_EABI64
;
8330 if ((elf_flags
& EF_MIPS_ABI2
))
8331 found_abi
= MIPS_ABI_N32
;
8333 found_abi
= MIPS_ABI_UNKNOWN
;
8337 /* GCC creates a pseudo-section whose name describes the ABI. */
8338 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8339 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8341 /* If we have no useful BFD information, use the ABI from the last
8342 MIPS architecture (if there is one). */
8343 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8344 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8346 /* Try the architecture for any hint of the correct ABI. */
8347 if (found_abi
== MIPS_ABI_UNKNOWN
8348 && info
.bfd_arch_info
!= NULL
8349 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8351 switch (info
.bfd_arch_info
->mach
)
8353 case bfd_mach_mips3900
:
8354 found_abi
= MIPS_ABI_EABI32
;
8356 case bfd_mach_mips4100
:
8357 case bfd_mach_mips5000
:
8358 found_abi
= MIPS_ABI_EABI64
;
8360 case bfd_mach_mips8000
:
8361 case bfd_mach_mips10000
:
8362 /* On Irix, ELF64 executables use the N64 ABI. The
8363 pseudo-sections which describe the ABI aren't present
8364 on IRIX. (Even for executables created by gcc.) */
8365 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8366 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8367 found_abi
= MIPS_ABI_N64
;
8369 found_abi
= MIPS_ABI_N32
;
8374 /* Default 64-bit objects to N64 instead of O32. */
8375 if (found_abi
== MIPS_ABI_UNKNOWN
8376 && info
.abfd
!= NULL
8377 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8378 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8379 found_abi
= MIPS_ABI_N64
;
8382 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8385 /* What has the user specified from the command line? */
8386 wanted_abi
= global_mips_abi ();
8388 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8391 /* Now that we have found what the ABI for this binary would be,
8392 check whether the user is overriding it. */
8393 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8394 mips_abi
= wanted_abi
;
8395 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8396 mips_abi
= found_abi
;
8398 mips_abi
= MIPS_ABI_O32
;
8400 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8403 /* Determine the default compressed ISA. */
8404 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8405 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8406 mips_isa
= ISA_MICROMIPS
;
8407 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8408 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8409 mips_isa
= ISA_MIPS16
;
8411 mips_isa
= global_mips_compression ();
8412 mips_compression_string
= mips_compression_strings
[mips_isa
];
8414 /* Also used when doing an architecture lookup. */
8416 fprintf_unfiltered (gdb_stdlog
,
8417 "mips_gdbarch_init: "
8418 "mips64_transfers_32bit_regs_p = %d\n",
8419 mips64_transfers_32bit_regs_p
);
8421 /* Determine the MIPS FPU type. */
8424 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8425 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8426 Tag_GNU_MIPS_ABI_FP
);
8427 #endif /* HAVE_ELF */
8429 if (!mips_fpu_type_auto
)
8430 fpu_type
= mips_fpu_type
;
8431 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8433 switch (elf_fpu_type
)
8435 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8436 fpu_type
= MIPS_FPU_DOUBLE
;
8438 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8439 fpu_type
= MIPS_FPU_SINGLE
;
8441 case Val_GNU_MIPS_ABI_FP_SOFT
:
8443 /* Soft float or unknown. */
8444 fpu_type
= MIPS_FPU_NONE
;
8448 else if (info
.bfd_arch_info
!= NULL
8449 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8450 switch (info
.bfd_arch_info
->mach
)
8452 case bfd_mach_mips3900
:
8453 case bfd_mach_mips4100
:
8454 case bfd_mach_mips4111
:
8455 case bfd_mach_mips4120
:
8456 fpu_type
= MIPS_FPU_NONE
;
8458 case bfd_mach_mips4650
:
8459 fpu_type
= MIPS_FPU_SINGLE
;
8462 fpu_type
= MIPS_FPU_DOUBLE
;
8465 else if (arches
!= NULL
)
8466 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8468 fpu_type
= MIPS_FPU_DOUBLE
;
8470 fprintf_unfiltered (gdb_stdlog
,
8471 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8473 /* Check for blatant incompatibilities. */
8475 /* If we have only 32-bit registers, then we can't debug a 64-bit
8477 if (info
.target_desc
8478 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8479 && mips_abi
!= MIPS_ABI_EABI32
8480 && mips_abi
!= MIPS_ABI_O32
)
8482 if (tdesc_data
!= NULL
)
8483 tdesc_data_cleanup (tdesc_data
);
8487 /* Try to find a pre-existing architecture. */
8488 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8490 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8492 /* MIPS needs to be pedantic about which ABI and the compressed
8493 ISA variation the object is using. */
8494 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8496 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8498 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8500 /* Need to be pedantic about which register virtual size is
8502 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8503 != mips64_transfers_32bit_regs_p
)
8505 /* Be pedantic about which FPU is selected. */
8506 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8509 if (tdesc_data
!= NULL
)
8510 tdesc_data_cleanup (tdesc_data
);
8511 return arches
->gdbarch
;
8514 /* Need a new architecture. Fill in a target specific vector. */
8515 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
8516 gdbarch
= gdbarch_alloc (&info
, tdep
);
8517 tdep
->elf_flags
= elf_flags
;
8518 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8519 tdep
->found_abi
= found_abi
;
8520 tdep
->mips_abi
= mips_abi
;
8521 tdep
->mips_isa
= mips_isa
;
8522 tdep
->mips_fpu_type
= fpu_type
;
8523 tdep
->register_size_valid_p
= 0;
8524 tdep
->register_size
= 0;
8526 if (info
.target_desc
)
8528 /* Some useful properties can be inferred from the target. */
8529 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8531 tdep
->register_size_valid_p
= 1;
8532 tdep
->register_size
= 4;
8534 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8536 tdep
->register_size_valid_p
= 1;
8537 tdep
->register_size
= 8;
8541 /* Initially set everything according to the default ABI/ISA. */
8542 set_gdbarch_short_bit (gdbarch
, 16);
8543 set_gdbarch_int_bit (gdbarch
, 32);
8544 set_gdbarch_float_bit (gdbarch
, 32);
8545 set_gdbarch_double_bit (gdbarch
, 64);
8546 set_gdbarch_long_double_bit (gdbarch
, 64);
8547 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8548 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8549 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8551 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8552 mips_ax_pseudo_register_collect
);
8553 set_gdbarch_ax_pseudo_register_push_stack
8554 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8556 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8557 mips_elf_make_msymbol_special
);
8558 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8559 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8560 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8562 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8563 *regnum
= mips_regnum
;
8564 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8565 set_gdbarch_num_regs (gdbarch
, num_regs
);
8566 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8567 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8568 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8569 tdep
->mips_processor_reg_names
= reg_names
;
8570 tdep
->regnum
= regnum
;
8575 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8576 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8577 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8578 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8579 tdep
->default_mask_address_p
= 0;
8580 set_gdbarch_long_bit (gdbarch
, 32);
8581 set_gdbarch_ptr_bit (gdbarch
, 32);
8582 set_gdbarch_long_long_bit (gdbarch
, 64);
8585 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8586 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8587 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8588 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8589 tdep
->default_mask_address_p
= 0;
8590 set_gdbarch_long_bit (gdbarch
, 32);
8591 set_gdbarch_ptr_bit (gdbarch
, 32);
8592 set_gdbarch_long_long_bit (gdbarch
, 64);
8594 case MIPS_ABI_EABI32
:
8595 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8596 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8597 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8598 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8599 tdep
->default_mask_address_p
= 0;
8600 set_gdbarch_long_bit (gdbarch
, 32);
8601 set_gdbarch_ptr_bit (gdbarch
, 32);
8602 set_gdbarch_long_long_bit (gdbarch
, 64);
8604 case MIPS_ABI_EABI64
:
8605 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8606 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8607 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8608 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8609 tdep
->default_mask_address_p
= 0;
8610 set_gdbarch_long_bit (gdbarch
, 64);
8611 set_gdbarch_ptr_bit (gdbarch
, 64);
8612 set_gdbarch_long_long_bit (gdbarch
, 64);
8615 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8616 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8617 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8618 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8619 tdep
->default_mask_address_p
= 0;
8620 set_gdbarch_long_bit (gdbarch
, 32);
8621 set_gdbarch_ptr_bit (gdbarch
, 32);
8622 set_gdbarch_long_long_bit (gdbarch
, 64);
8623 set_gdbarch_long_double_bit (gdbarch
, 128);
8624 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8627 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8628 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8629 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8630 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8631 tdep
->default_mask_address_p
= 0;
8632 set_gdbarch_long_bit (gdbarch
, 64);
8633 set_gdbarch_ptr_bit (gdbarch
, 64);
8634 set_gdbarch_long_long_bit (gdbarch
, 64);
8635 set_gdbarch_long_double_bit (gdbarch
, 128);
8636 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8639 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8642 /* GCC creates a pseudo-section whose name specifies the size of
8643 longs, since -mlong32 or -mlong64 may be used independent of
8644 other options. How those options affect pointer sizes is ABI and
8645 architecture dependent, so use them to override the default sizes
8646 set by the ABI. This table shows the relationship between ABI,
8647 -mlongXX, and size of pointers:
8649 ABI -mlongXX ptr bits
8650 --- -------- --------
8664 Note that for o32 and eabi32, pointers are always 32 bits
8665 regardless of any -mlongXX option. For all others, pointers and
8666 longs are the same, as set by -mlongXX or set by defaults. */
8668 if (info
.abfd
!= NULL
)
8672 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8675 set_gdbarch_long_bit (gdbarch
, long_bit
);
8679 case MIPS_ABI_EABI32
:
8684 case MIPS_ABI_EABI64
:
8685 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8688 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8693 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8694 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8697 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8698 flag in object files because to do so would make it impossible to
8699 link with libraries compiled without "-gp32". This is
8700 unnecessarily restrictive.
8702 We could solve this problem by adding "-gp32" multilibs to gcc,
8703 but to set this flag before gcc is built with such multilibs will
8704 break too many systems.''
8706 But even more unhelpfully, the default linker output target for
8707 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8708 for 64-bit programs - you need to change the ABI to change this,
8709 and not all gcc targets support that currently. Therefore using
8710 this flag to detect 32-bit mode would do the wrong thing given
8711 the current gcc - it would make GDB treat these 64-bit programs
8712 as 32-bit programs by default. */
8714 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8715 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8717 /* Add/remove bits from an address. The MIPS needs be careful to
8718 ensure that all 32 bit addresses are sign extended to 64 bits. */
8719 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8721 /* Unwind the frame. */
8722 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8723 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8724 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8726 /* Map debug register numbers onto internal register numbers. */
8727 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8728 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8729 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8730 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8731 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8732 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8734 /* MIPS version of CALL_DUMMY. */
8736 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8737 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8738 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8740 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8741 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8742 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8744 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8745 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8746 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8747 mips_remote_breakpoint_from_pc
);
8748 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8749 mips_adjust_breakpoint_address
);
8751 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8753 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
8755 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8756 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8757 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8759 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8761 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8763 if (mips_abi
== MIPS_ABI_N32
)
8764 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8765 else if (mips_abi
== MIPS_ABI_N64
)
8766 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8768 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8770 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8771 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8772 need to all be folded into the target vector. Since they are
8773 being used as guards for target_stopped_by_watchpoint, why not have
8774 target_stopped_by_watchpoint return the type of watchpoint that the code
8776 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8778 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8780 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8781 to support MIPS16. This is a bad thing. Make sure not to do it
8782 if we have an OS ABI that actually supports shared libraries, since
8783 shared library support is more important. If we have an OS someday
8784 that supports both shared libraries and MIPS16, we'll have to find
8785 a better place for these.
8786 macro/2012-04-25: But that applies to return trampolines only and
8787 currently no MIPS OS ABI uses shared libraries that have them. */
8788 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8790 set_gdbarch_single_step_through_delay (gdbarch
,
8791 mips_single_step_through_delay
);
8793 /* Virtual tables. */
8794 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8796 mips_register_g_packet_guesses (gdbarch
);
8798 /* Hook in OS ABI-specific overrides, if they have been registered. */
8799 info
.tdep_info
= (void *) tdesc_data
;
8800 gdbarch_init_osabi (info
, gdbarch
);
8802 /* The hook may have adjusted num_regs, fetch the final value and
8803 set pc_regnum and sp_regnum now that it has been fixed. */
8804 num_regs
= gdbarch_num_regs (gdbarch
);
8805 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8806 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8808 /* Unwind the frame. */
8809 dwarf2_append_unwinders (gdbarch
);
8810 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8811 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8812 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8813 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8814 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8815 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8816 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8817 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8818 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8822 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8823 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8825 /* Override the normal target description methods to handle our
8826 dual real and pseudo registers. */
8827 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8828 set_gdbarch_register_reggroup_p (gdbarch
,
8829 mips_tdesc_register_reggroup_p
);
8831 num_regs
= gdbarch_num_regs (gdbarch
);
8832 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8833 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8834 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8837 /* Add ABI-specific aliases for the registers. */
8838 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8839 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8840 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8841 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8843 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8844 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8845 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8847 /* Add some other standard aliases. */
8848 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8849 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8850 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8852 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8853 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8854 value_of_mips_user_reg
,
8855 &mips_numeric_register_aliases
[i
].regnum
);
8861 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8863 struct gdbarch_info info
;
8865 /* Force the architecture to update, and (if it's a MIPS architecture)
8866 mips_gdbarch_init will take care of the rest. */
8867 gdbarch_info_init (&info
);
8868 gdbarch_update_p (info
);
8871 /* Print out which MIPS ABI is in use. */
8874 show_mips_abi (struct ui_file
*file
,
8876 struct cmd_list_element
*ignored_cmd
,
8877 const char *ignored_value
)
8879 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8882 "The MIPS ABI is unknown because the current architecture "
8886 enum mips_abi global_abi
= global_mips_abi ();
8887 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8888 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8890 if (global_abi
== MIPS_ABI_UNKNOWN
)
8893 "The MIPS ABI is set automatically (currently \"%s\").\n",
8895 else if (global_abi
== actual_abi
)
8898 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8902 /* Probably shouldn't happen... */
8903 fprintf_filtered (file
,
8904 "The (auto detected) MIPS ABI \"%s\" is in use "
8905 "even though the user setting was \"%s\".\n",
8906 actual_abi_str
, mips_abi_strings
[global_abi
]);
8911 /* Print out which MIPS compressed ISA encoding is used. */
8914 show_mips_compression (struct ui_file
*file
, int from_tty
,
8915 struct cmd_list_element
*c
, const char *value
)
8917 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8922 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8924 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8928 int ef_mips_32bitmode
;
8929 /* Determine the ISA. */
8930 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8948 /* Determine the size of a pointer. */
8949 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8950 fprintf_unfiltered (file
,
8951 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8953 fprintf_unfiltered (file
,
8954 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8956 fprintf_unfiltered (file
,
8957 "mips_dump_tdep: ef_mips_arch = %d\n",
8959 fprintf_unfiltered (file
,
8960 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8961 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8962 fprintf_unfiltered (file
,
8964 "mips_mask_address_p() %d (default %d)\n",
8965 mips_mask_address_p (tdep
),
8966 tdep
->default_mask_address_p
);
8968 fprintf_unfiltered (file
,
8969 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8970 MIPS_DEFAULT_FPU_TYPE
,
8971 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8972 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8973 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8975 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8976 MIPS_EABI (gdbarch
));
8977 fprintf_unfiltered (file
,
8978 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8979 MIPS_FPU_TYPE (gdbarch
),
8980 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8981 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8982 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8986 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8989 _initialize_mips_tdep (void)
8991 static struct cmd_list_element
*mipsfpulist
= NULL
;
8992 struct cmd_list_element
*c
;
8994 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8995 if (MIPS_ABI_LAST
+ 1
8996 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8997 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8999 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
9001 mips_pdr_data
= register_objfile_data ();
9003 /* Create feature sets with the appropriate properties. The values
9004 are not important. */
9005 mips_tdesc_gp32
= allocate_target_description ();
9006 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
9008 mips_tdesc_gp64
= allocate_target_description ();
9009 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
9011 /* Add root prefix command for all "set mips"/"show mips" commands. */
9012 add_prefix_cmd ("mips", no_class
, set_mips_command
,
9013 _("Various MIPS specific commands."),
9014 &setmipscmdlist
, "set mips ", 0, &setlist
);
9016 add_prefix_cmd ("mips", no_class
, show_mips_command
,
9017 _("Various MIPS specific commands."),
9018 &showmipscmdlist
, "show mips ", 0, &showlist
);
9020 /* Allow the user to override the ABI. */
9021 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9022 &mips_abi_string
, _("\
9023 Set the MIPS ABI used by this program."), _("\
9024 Show the MIPS ABI used by this program."), _("\
9025 This option can be set to one of:\n\
9026 auto - the default ABI associated with the current binary\n\
9035 &setmipscmdlist
, &showmipscmdlist
);
9037 /* Allow the user to set the ISA to assume for compressed code if ELF
9038 file flags don't tell or there is no program file selected. This
9039 setting is updated whenever unambiguous ELF file flags are interpreted,
9040 and carried over to subsequent sessions. */
9041 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9042 &mips_compression_string
, _("\
9043 Set the compressed ISA encoding used by MIPS code."), _("\
9044 Show the compressed ISA encoding used by MIPS code."), _("\
9045 Select the compressed ISA encoding used in functions that have no symbol\n\
9046 information available. The encoding can be set to either of:\n\
9049 and is updated automatically from ELF file flags if available."),
9051 show_mips_compression
,
9052 &setmipscmdlist
, &showmipscmdlist
);
9054 /* Let the user turn off floating point and set the fence post for
9055 heuristic_proc_start. */
9057 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9058 _("Set use of MIPS floating-point coprocessor."),
9059 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9060 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9061 _("Select single-precision MIPS floating-point coprocessor."),
9063 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9064 _("Select double-precision MIPS floating-point coprocessor."),
9066 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9067 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9068 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9069 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9070 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9071 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9072 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9073 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9074 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9075 _("Select MIPS floating-point coprocessor automatically."),
9077 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9078 _("Show current use of MIPS floating-point coprocessor target."),
9081 /* We really would like to have both "0" and "unlimited" work, but
9082 command.c doesn't deal with that. So make it a var_zinteger
9083 because the user can always use "999999" or some such for unlimited. */
9084 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9085 &heuristic_fence_post
, _("\
9086 Set the distance searched for the start of a function."), _("\
9087 Show the distance searched for the start of a function."), _("\
9088 If you are debugging a stripped executable, GDB needs to search through the\n\
9089 program for the start of a function. This command sets the distance of the\n\
9090 search. The only need to set it is when debugging a stripped executable."),
9091 reinit_frame_cache_sfunc
,
9092 NULL
, /* FIXME: i18n: The distance searched for
9093 the start of a function is %s. */
9094 &setlist
, &showlist
);
9096 /* Allow the user to control whether the upper bits of 64-bit
9097 addresses should be zeroed. */
9098 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9099 &mask_address_var
, _("\
9100 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9101 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9102 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9103 allow GDB to determine the correct value."),
9104 NULL
, show_mask_address
,
9105 &setmipscmdlist
, &showmipscmdlist
);
9107 /* Allow the user to control the size of 32 bit registers within the
9108 raw remote packet. */
9109 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9110 &mips64_transfers_32bit_regs_p
, _("\
9111 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9113 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9115 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9116 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9117 64 bits for others. Use \"off\" to disable compatibility mode"),
9118 set_mips64_transfers_32bit_regs
,
9119 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9120 MIPS target that transfers 32-bit
9121 quantities is %s. */
9122 &setlist
, &showlist
);
9124 /* Debug this files internals. */
9125 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9127 Set mips debugging."), _("\
9128 Show mips debugging."), _("\
9129 When non-zero, mips specific debugging is enabled."),
9131 NULL
, /* FIXME: i18n: Mips debugging is
9133 &setdebuglist
, &showdebuglist
);