1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
67 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
68 static int mips16_instruction_has_delay_slot (unsigned short inst
,
71 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
73 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
75 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
76 CORE_ADDR addr
, int mustbe32
);
78 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
79 struct frame_info
*, const char *);
81 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
82 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
83 #define ST0_FR (1 << 26)
85 /* The sizes of floating point registers. */
89 MIPS_FPU_SINGLE_REGSIZE
= 4,
90 MIPS_FPU_DOUBLE_REGSIZE
= 8
99 static const char *mips_abi_string
;
101 static const char *const mips_abi_strings
[] = {
112 /* Enum describing the different kinds of breakpoints. */
114 enum mips_breakpoint_kind
116 /* 16-bit MIPS16 mode breakpoint. */
117 MIPS_BP_KIND_MIPS16
= 2,
119 /* 16-bit microMIPS mode breakpoint. */
120 MIPS_BP_KIND_MICROMIPS16
= 3,
122 /* 32-bit standard MIPS mode breakpoint. */
123 MIPS_BP_KIND_MIPS32
= 4,
125 /* 32-bit microMIPS mode breakpoint. */
126 MIPS_BP_KIND_MICROMIPS32
= 5,
129 /* For backwards compatibility we default to MIPS16. This flag is
130 overridden as soon as unambiguous ELF file flags tell us the
131 compressed ISA encoding used. */
132 static const char mips_compression_mips16
[] = "mips16";
133 static const char mips_compression_micromips
[] = "micromips";
134 static const char *const mips_compression_strings
[] =
136 mips_compression_mips16
,
137 mips_compression_micromips
,
141 static const char *mips_compression_string
= mips_compression_mips16
;
143 /* The standard register names, and all the valid aliases for them. */
144 struct register_alias
150 /* Aliases for o32 and most other ABIs. */
151 const struct register_alias mips_o32_aliases
[] = {
158 /* Aliases for n32 and n64. */
159 const struct register_alias mips_n32_n64_aliases
[] = {
166 /* Aliases for ABI-independent registers. */
167 const struct register_alias mips_register_aliases
[] = {
168 /* The architecture manuals specify these ABI-independent names for
170 #define R(n) { "r" #n, n }
171 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
172 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
173 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
174 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
177 /* k0 and k1 are sometimes called these instead (for "kernel
182 /* This is the traditional GDB name for the CP0 status register. */
183 { "sr", MIPS_PS_REGNUM
},
185 /* This is the traditional GDB name for the CP0 BadVAddr register. */
186 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
188 /* This is the traditional GDB name for the FCSR. */
189 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
192 const struct register_alias mips_numeric_register_aliases
[] = {
193 #define R(n) { #n, n }
194 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
195 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
196 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
197 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
201 #ifndef MIPS_DEFAULT_FPU_TYPE
202 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
204 static int mips_fpu_type_auto
= 1;
205 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
207 static unsigned int mips_debug
= 0;
209 /* Properties (for struct target_desc) describing the g/G packet
211 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
212 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
214 struct target_desc
*mips_tdesc_gp32
;
215 struct target_desc
*mips_tdesc_gp64
;
217 const struct mips_regnum
*
218 mips_regnum (struct gdbarch
*gdbarch
)
220 return gdbarch_tdep (gdbarch
)->regnum
;
224 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
226 return mips_regnum (gdbarch
)->fp0
+ 12;
229 /* Return 1 if REGNUM refers to a floating-point general register, raw
230 or cooked. Otherwise return 0. */
233 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
235 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
237 return (rawnum
>= mips_regnum (gdbarch
)->fp0
238 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
241 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
243 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
245 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
246 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
248 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
249 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
251 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
253 /* Return the MIPS ABI associated with GDBARCH. */
255 mips_abi (struct gdbarch
*gdbarch
)
257 return gdbarch_tdep (gdbarch
)->mips_abi
;
261 mips_isa_regsize (struct gdbarch
*gdbarch
)
263 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
265 /* If we know how big the registers are, use that size. */
266 if (tdep
->register_size_valid_p
)
267 return tdep
->register_size
;
269 /* Fall back to the previous behavior. */
270 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
271 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
274 /* Max saved register size. */
275 #define MAX_MIPS_ABI_REGSIZE 8
277 /* Return the currently configured (or set) saved register size. */
280 mips_abi_regsize (struct gdbarch
*gdbarch
)
282 switch (mips_abi (gdbarch
))
284 case MIPS_ABI_EABI32
:
290 case MIPS_ABI_EABI64
:
292 case MIPS_ABI_UNKNOWN
:
295 internal_error (__FILE__
, __LINE__
, _("bad switch"));
299 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
300 are some functions to handle addresses associated with compressed
301 code including but not limited to testing, setting, or clearing
302 bit 0 of such addresses. */
304 /* Return one iff compressed code is the MIPS16 instruction set. */
307 is_mips16_isa (struct gdbarch
*gdbarch
)
309 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
312 /* Return one iff compressed code is the microMIPS instruction set. */
315 is_micromips_isa (struct gdbarch
*gdbarch
)
317 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
320 /* Return one iff ADDR denotes compressed code. */
323 is_compact_addr (CORE_ADDR addr
)
328 /* Return one iff ADDR denotes standard ISA code. */
331 is_mips_addr (CORE_ADDR addr
)
333 return !is_compact_addr (addr
);
336 /* Return one iff ADDR denotes MIPS16 code. */
339 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
341 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
344 /* Return one iff ADDR denotes microMIPS code. */
347 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
349 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
352 /* Strip the ISA (compression) bit off from ADDR. */
355 unmake_compact_addr (CORE_ADDR addr
)
357 return ((addr
) & ~(CORE_ADDR
) 1);
360 /* Add the ISA (compression) bit to ADDR. */
363 make_compact_addr (CORE_ADDR addr
)
365 return ((addr
) | (CORE_ADDR
) 1);
368 /* Extern version of unmake_compact_addr; we use a separate function
369 so that unmake_compact_addr can be inlined throughout this file. */
372 mips_unmake_compact_addr (CORE_ADDR addr
)
374 return unmake_compact_addr (addr
);
377 /* Functions for setting and testing a bit in a minimal symbol that
378 marks it as MIPS16 or microMIPS function. The MSB of the minimal
379 symbol's "info" field is used for this purpose.
381 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
382 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
383 one of the "special" bits in a minimal symbol to mark it accordingly.
384 The test checks an ELF-private flag that is valid for true function
385 symbols only; for synthetic symbols such as for PLT stubs that have
386 no ELF-private part at all the MIPS BFD backend arranges for this
387 information to be carried in the asymbol's udata field instead.
389 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
390 in a minimal symbol. */
393 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
395 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
396 unsigned char st_other
;
398 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
399 st_other
= elfsym
->internal_elf_sym
.st_other
;
400 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
401 st_other
= sym
->udata
.i
;
405 if (ELF_ST_IS_MICROMIPS (st_other
))
407 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
408 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
410 else if (ELF_ST_IS_MIPS16 (st_other
))
412 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
413 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
417 /* Return one iff MSYM refers to standard ISA code. */
420 msymbol_is_mips (struct minimal_symbol
*msym
)
422 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
423 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
426 /* Return one iff MSYM refers to MIPS16 code. */
429 msymbol_is_mips16 (struct minimal_symbol
*msym
)
431 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
434 /* Return one iff MSYM refers to microMIPS code. */
437 msymbol_is_micromips (struct minimal_symbol
*msym
)
439 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
442 /* Set the ISA bit in the main symbol too, complementing the corresponding
443 minimal symbol setting and reflecting the run-time value of the symbol.
444 The need for comes from the ISA bit having been cleared as code in
445 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
446 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
447 of symbols referring to compressed code different in GDB to the values
448 used by actual code. That in turn makes them evaluate incorrectly in
449 expressions, producing results different to what the same expressions
450 yield when compiled into the program being debugged. */
453 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
455 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
457 /* We are in symbol reading so it is OK to cast away constness. */
458 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
459 CORE_ADDR compact_block_start
;
460 struct bound_minimal_symbol msym
;
462 compact_block_start
= BLOCK_START (block
) | 1;
463 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
464 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
466 BLOCK_START (block
) = compact_block_start
;
471 /* XFER a value from the big/little/left end of the register.
472 Depending on the size of the value it might occupy the entire
473 register or just part of it. Make an allowance for this, aligning
474 things accordingly. */
477 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
478 int reg_num
, int length
,
479 enum bfd_endian endian
, gdb_byte
*in
,
480 const gdb_byte
*out
, int buf_offset
)
484 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
485 /* Need to transfer the left or right part of the register, based on
486 the targets byte order. */
490 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
492 case BFD_ENDIAN_LITTLE
:
495 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
499 internal_error (__FILE__
, __LINE__
, _("bad switch"));
502 fprintf_unfiltered (gdb_stderr
,
503 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
504 reg_num
, reg_offset
, buf_offset
, length
);
505 if (mips_debug
&& out
!= NULL
)
508 fprintf_unfiltered (gdb_stdlog
, "out ");
509 for (i
= 0; i
< length
; i
++)
510 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
513 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
516 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
518 if (mips_debug
&& in
!= NULL
)
521 fprintf_unfiltered (gdb_stdlog
, "in ");
522 for (i
= 0; i
< length
; i
++)
523 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
526 fprintf_unfiltered (gdb_stdlog
, "\n");
529 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
530 compatiblity mode. A return value of 1 means that we have
531 physical 64-bit registers, but should treat them as 32-bit registers. */
534 mips2_fp_compat (struct frame_info
*frame
)
536 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
537 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
539 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
543 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
544 in all the places we deal with FP registers. PR gdb/413. */
545 /* Otherwise check the FR bit in the status register - it controls
546 the FP compatiblity mode. If it is clear we are in compatibility
548 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
555 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
557 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
559 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
561 /* The list of available "set mips " and "show mips " commands. */
563 static struct cmd_list_element
*setmipscmdlist
= NULL
;
564 static struct cmd_list_element
*showmipscmdlist
= NULL
;
566 /* Integer registers 0 thru 31 are handled explicitly by
567 mips_register_name(). Processor specific registers 32 and above
568 are listed in the following tables. */
571 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
575 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
576 "sr", "lo", "hi", "bad", "cause", "pc",
577 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
578 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
579 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
580 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
584 /* Names of tx39 registers. */
586 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
587 "sr", "lo", "hi", "bad", "cause", "pc",
588 "", "", "", "", "", "", "", "",
589 "", "", "", "", "", "", "", "",
590 "", "", "", "", "", "", "", "",
591 "", "", "", "", "", "", "", "",
593 "", "", "", "", "", "", "", "",
594 "", "", "config", "cache", "debug", "depc", "epc",
597 /* Names of registers with Linux kernels. */
598 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
599 "sr", "lo", "hi", "bad", "cause", "pc",
600 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
601 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
602 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
603 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
608 /* Return the name of the register corresponding to REGNO. */
610 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
613 /* GPR names for all ABIs other than n32/n64. */
614 static const char *mips_gpr_names
[] = {
615 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
616 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
617 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
618 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
621 /* GPR names for n32 and n64 ABIs. */
622 static const char *mips_n32_n64_gpr_names
[] = {
623 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
624 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
625 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
626 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
629 enum mips_abi abi
= mips_abi (gdbarch
);
631 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
632 but then don't make the raw register names visible. This (upper)
633 range of user visible register numbers are the pseudo-registers.
635 This approach was adopted accommodate the following scenario:
636 It is possible to debug a 64-bit device using a 32-bit
637 programming model. In such instances, the raw registers are
638 configured to be 64-bits wide, while the pseudo registers are
639 configured to be 32-bits wide. The registers that the user
640 sees - the pseudo registers - match the users expectations
641 given the programming model being used. */
642 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
643 if (regno
< gdbarch_num_regs (gdbarch
))
646 /* The MIPS integer registers are always mapped from 0 to 31. The
647 names of the registers (which reflects the conventions regarding
648 register use) vary depending on the ABI. */
649 if (0 <= rawnum
&& rawnum
< 32)
651 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
652 return mips_n32_n64_gpr_names
[rawnum
];
654 return mips_gpr_names
[rawnum
];
656 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
657 return tdesc_register_name (gdbarch
, rawnum
);
658 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
660 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
661 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
662 return tdep
->mips_processor_reg_names
[rawnum
- 32];
666 internal_error (__FILE__
, __LINE__
,
667 _("mips_register_name: bad register number %d"), rawnum
);
670 /* Return the groups that a MIPS register can be categorised into. */
673 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
674 struct reggroup
*reggroup
)
679 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
680 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
681 if (reggroup
== all_reggroup
)
683 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
684 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
685 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
686 (gdbarch), as not all architectures are multi-arch. */
687 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
688 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
689 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
691 if (reggroup
== float_reggroup
)
692 return float_p
&& pseudo
;
693 if (reggroup
== vector_reggroup
)
694 return vector_p
&& pseudo
;
695 if (reggroup
== general_reggroup
)
696 return (!vector_p
&& !float_p
) && pseudo
;
697 /* Save the pseudo registers. Need to make certain that any code
698 extracting register values from a saved register cache also uses
700 if (reggroup
== save_reggroup
)
701 return raw_p
&& pseudo
;
702 /* Restore the same pseudo register. */
703 if (reggroup
== restore_reggroup
)
704 return raw_p
&& pseudo
;
708 /* Return the groups that a MIPS register can be categorised into.
709 This version is only used if we have a target description which
710 describes real registers (and their groups). */
713 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
714 struct reggroup
*reggroup
)
716 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
717 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
720 /* Only save, restore, and display the pseudo registers. Need to
721 make certain that any code extracting register values from a
722 saved register cache also uses pseudo registers.
724 Note: saving and restoring the pseudo registers is slightly
725 strange; if we have 64 bits, we should save and restore all
726 64 bits. But this is hard and has little benefit. */
730 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
734 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
737 /* Map the symbol table registers which live in the range [1 *
738 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
739 registers. Take care of alignment and size problems. */
741 static enum register_status
742 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
743 int cookednum
, gdb_byte
*buf
)
745 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
746 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
747 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
748 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
749 return regcache_raw_read (regcache
, rawnum
, buf
);
750 else if (register_size (gdbarch
, rawnum
) >
751 register_size (gdbarch
, cookednum
))
753 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
754 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
757 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
759 enum register_status status
;
761 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
762 if (status
== REG_VALID
)
763 store_signed_integer (buf
, 4, byte_order
, regval
);
768 internal_error (__FILE__
, __LINE__
, _("bad register size"));
772 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
773 struct regcache
*regcache
, int cookednum
,
776 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
777 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
778 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
779 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
780 regcache_raw_write (regcache
, rawnum
, buf
);
781 else if (register_size (gdbarch
, rawnum
) >
782 register_size (gdbarch
, cookednum
))
784 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
785 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
788 /* Sign extend the shortened version of the register prior
789 to placing it in the raw register. This is required for
790 some mips64 parts in order to avoid unpredictable behavior. */
791 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
792 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
793 regcache_raw_write_signed (regcache
, rawnum
, regval
);
797 internal_error (__FILE__
, __LINE__
, _("bad register size"));
801 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
802 struct agent_expr
*ax
, int reg
)
804 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
805 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
806 && reg
< 2 * gdbarch_num_regs (gdbarch
));
808 ax_reg_mask (ax
, rawnum
);
814 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
815 struct agent_expr
*ax
, int reg
)
817 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
818 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
819 && reg
< 2 * gdbarch_num_regs (gdbarch
));
820 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
824 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
826 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
827 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
830 ax_simple (ax
, aop_lsh
);
833 ax_simple (ax
, aop_rsh_signed
);
837 internal_error (__FILE__
, __LINE__
, _("bad register size"));
842 /* Table to translate 3-bit register field to actual register number. */
843 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
845 /* Heuristic_proc_start may hunt through the text section for a long
846 time across a 2400 baud serial line. Allows the user to limit this
849 static int heuristic_fence_post
= 0;
851 /* Number of bytes of storage in the actual machine representation for
852 register N. NOTE: This defines the pseudo register type so need to
853 rebuild the architecture vector. */
855 static int mips64_transfers_32bit_regs_p
= 0;
858 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
859 struct cmd_list_element
*c
)
861 struct gdbarch_info info
;
862 gdbarch_info_init (&info
);
863 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
864 instead of relying on globals. Doing that would let generic code
865 handle the search for this specific architecture. */
866 if (!gdbarch_update_p (info
))
868 mips64_transfers_32bit_regs_p
= 0;
869 error (_("32-bit compatibility mode not supported"));
873 /* Convert to/from a register and the corresponding memory value. */
875 /* This predicate tests for the case of an 8 byte floating point
876 value that is being transferred to or from a pair of floating point
877 registers each of which are (or are considered to be) only 4 bytes
880 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
883 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
884 && register_size (gdbarch
, regnum
) == 4
885 && mips_float_register_p (gdbarch
, regnum
)
886 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
889 /* This predicate tests for the case of a value of less than 8
890 bytes in width that is being transfered to or from an 8 byte
891 general purpose register. */
893 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
896 int num_regs
= gdbarch_num_regs (gdbarch
);
898 return (register_size (gdbarch
, regnum
) == 8
899 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
900 && TYPE_LENGTH (type
) < 8);
904 mips_convert_register_p (struct gdbarch
*gdbarch
,
905 int regnum
, struct type
*type
)
907 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
908 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
912 mips_register_to_value (struct frame_info
*frame
, int regnum
,
913 struct type
*type
, gdb_byte
*to
,
914 int *optimizedp
, int *unavailablep
)
916 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
918 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
920 get_frame_register (frame
, regnum
+ 0, to
+ 4);
921 get_frame_register (frame
, regnum
+ 1, to
+ 0);
923 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
924 optimizedp
, unavailablep
))
927 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
928 optimizedp
, unavailablep
))
930 *optimizedp
= *unavailablep
= 0;
933 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
935 int len
= TYPE_LENGTH (type
);
938 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
939 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
940 optimizedp
, unavailablep
))
943 *optimizedp
= *unavailablep
= 0;
948 internal_error (__FILE__
, __LINE__
,
949 _("mips_register_to_value: unrecognized case"));
954 mips_value_to_register (struct frame_info
*frame
, int regnum
,
955 struct type
*type
, const gdb_byte
*from
)
957 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
959 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
961 put_frame_register (frame
, regnum
+ 0, from
+ 4);
962 put_frame_register (frame
, regnum
+ 1, from
+ 0);
964 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
967 int len
= TYPE_LENGTH (type
);
969 /* Sign extend values, irrespective of type, that are stored to
970 a 64-bit general purpose register. (32-bit unsigned values
971 are stored as signed quantities within a 64-bit register.
972 When performing an operation, in compiled code, that combines
973 a 32-bit unsigned value with a signed 64-bit value, a type
974 conversion is first performed that zeroes out the high 32 bits.) */
975 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
978 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
980 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
981 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
982 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
986 if (from
[len
-1] & 0x80)
987 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
989 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
990 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
991 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
996 internal_error (__FILE__
, __LINE__
,
997 _("mips_value_to_register: unrecognized case"));
1001 /* Return the GDB type object for the "standard" data type of data in
1004 static struct type
*
1005 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1007 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1008 if (mips_float_register_p (gdbarch
, regnum
))
1010 /* The floating-point registers raw, or cooked, always match
1011 mips_isa_regsize(), and also map 1:1, byte for byte. */
1012 if (mips_isa_regsize (gdbarch
) == 4)
1013 return builtin_type (gdbarch
)->builtin_float
;
1015 return builtin_type (gdbarch
)->builtin_double
;
1017 else if (regnum
< gdbarch_num_regs (gdbarch
))
1019 /* The raw or ISA registers. These are all sized according to
1021 if (mips_isa_regsize (gdbarch
) == 4)
1022 return builtin_type (gdbarch
)->builtin_int32
;
1024 return builtin_type (gdbarch
)->builtin_int64
;
1028 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1030 /* The cooked or ABI registers. These are sized according to
1031 the ABI (with a few complications). */
1032 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1033 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1034 return builtin_type (gdbarch
)->builtin_int32
;
1035 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1036 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1037 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1038 /* The pseudo/cooked view of the embedded registers is always
1039 32-bit. The raw view is handled below. */
1040 return builtin_type (gdbarch
)->builtin_int32
;
1041 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1042 /* The target, while possibly using a 64-bit register buffer,
1043 is only transfering 32-bits of each integer register.
1044 Reflect this in the cooked/pseudo (ABI) register value. */
1045 return builtin_type (gdbarch
)->builtin_int32
;
1046 else if (mips_abi_regsize (gdbarch
) == 4)
1047 /* The ABI is restricted to 32-bit registers (the ISA could be
1049 return builtin_type (gdbarch
)->builtin_int32
;
1052 return builtin_type (gdbarch
)->builtin_int64
;
1056 /* Return the GDB type for the pseudo register REGNUM, which is the
1057 ABI-level view. This function is only called if there is a target
1058 description which includes registers, so we know precisely the
1059 types of hardware registers. */
1061 static struct type
*
1062 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1064 const int num_regs
= gdbarch_num_regs (gdbarch
);
1065 int rawnum
= regnum
% num_regs
;
1066 struct type
*rawtype
;
1068 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1070 /* Absent registers are still absent. */
1071 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1072 if (TYPE_LENGTH (rawtype
) == 0)
1075 /* Present the floating point registers however the hardware did;
1076 do not try to convert between FPU layouts. */
1077 if (mips_float_register_p (gdbarch
, rawnum
))
1080 /* Floating-point control registers are always 32-bit even though for
1081 backwards compatibility reasons 64-bit targets will transfer them
1082 as 64-bit quantities even if using XML descriptions. */
1083 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1084 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1085 return builtin_type (gdbarch
)->builtin_int32
;
1087 /* Use pointer types for registers if we can. For n32 we can not,
1088 since we do not have a 64-bit pointer type. */
1089 if (mips_abi_regsize (gdbarch
)
1090 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1092 if (rawnum
== MIPS_SP_REGNUM
1093 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1094 return builtin_type (gdbarch
)->builtin_data_ptr
;
1095 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1096 return builtin_type (gdbarch
)->builtin_func_ptr
;
1099 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1100 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1101 || rawnum
== mips_regnum (gdbarch
)->lo
1102 || rawnum
== mips_regnum (gdbarch
)->hi
1103 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1104 || rawnum
== mips_regnum (gdbarch
)->cause
1105 || rawnum
== mips_regnum (gdbarch
)->pc
1106 || (mips_regnum (gdbarch
)->dspacc
!= -1
1107 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1108 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1109 return builtin_type (gdbarch
)->builtin_int32
;
1111 /* The pseudo/cooked view of embedded registers is always
1112 32-bit, even if the target transfers 64-bit values for them.
1113 New targets relying on XML descriptions should only transfer
1114 the necessary 32 bits, but older versions of GDB expected 64,
1115 so allow the target to provide 64 bits without interfering
1116 with the displayed type. */
1117 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1118 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1119 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1120 return builtin_type (gdbarch
)->builtin_int32
;
1122 /* For all other registers, pass through the hardware type. */
1126 /* Should the upper word of 64-bit addresses be zeroed? */
1127 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1130 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1132 switch (mask_address_var
)
1134 case AUTO_BOOLEAN_TRUE
:
1136 case AUTO_BOOLEAN_FALSE
:
1139 case AUTO_BOOLEAN_AUTO
:
1140 return tdep
->default_mask_address_p
;
1142 internal_error (__FILE__
, __LINE__
,
1143 _("mips_mask_address_p: bad switch"));
1149 show_mask_address (struct ui_file
*file
, int from_tty
,
1150 struct cmd_list_element
*c
, const char *value
)
1152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1154 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1155 switch (mask_address_var
)
1157 case AUTO_BOOLEAN_TRUE
:
1158 printf_filtered ("The 32 bit mips address mask is enabled\n");
1160 case AUTO_BOOLEAN_FALSE
:
1161 printf_filtered ("The 32 bit mips address mask is disabled\n");
1163 case AUTO_BOOLEAN_AUTO
:
1165 ("The 32 bit address mask is set automatically. Currently %s\n",
1166 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1169 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1174 /* Tell if the program counter value in MEMADDR is in a standard ISA
1178 mips_pc_is_mips (CORE_ADDR memaddr
)
1180 struct bound_minimal_symbol sym
;
1182 /* Flags indicating that this is a MIPS16 or microMIPS function is
1183 stored by elfread.c in the high bit of the info field. Use this
1184 to decide if the function is standard MIPS. Otherwise if bit 0
1185 of the address is clear, then this is a standard MIPS function. */
1186 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1188 return msymbol_is_mips (sym
.minsym
);
1190 return is_mips_addr (memaddr
);
1193 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1196 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1198 struct bound_minimal_symbol sym
;
1200 /* A flag indicating that this is a MIPS16 function is stored by
1201 elfread.c in the high bit of the info field. Use this to decide
1202 if the function is MIPS16. Otherwise if bit 0 of the address is
1203 set, then ELF file flags will tell if this is a MIPS16 function. */
1204 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1206 return msymbol_is_mips16 (sym
.minsym
);
1208 return is_mips16_addr (gdbarch
, memaddr
);
1211 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1214 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1216 struct bound_minimal_symbol sym
;
1218 /* A flag indicating that this is a microMIPS function is stored by
1219 elfread.c in the high bit of the info field. Use this to decide
1220 if the function is microMIPS. Otherwise if bit 0 of the address
1221 is set, then ELF file flags will tell if this is a microMIPS
1223 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1225 return msymbol_is_micromips (sym
.minsym
);
1227 return is_micromips_addr (gdbarch
, memaddr
);
1230 /* Tell the ISA type of the function the program counter value in MEMADDR
1233 static enum mips_isa
1234 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1236 struct bound_minimal_symbol sym
;
1238 /* A flag indicating that this is a MIPS16 or a microMIPS function
1239 is stored by elfread.c in the high bit of the info field. Use
1240 this to decide if the function is MIPS16 or microMIPS or normal
1241 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1242 flags will tell if this is a MIPS16 or a microMIPS function. */
1243 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1246 if (msymbol_is_micromips (sym
.minsym
))
1247 return ISA_MICROMIPS
;
1248 else if (msymbol_is_mips16 (sym
.minsym
))
1255 if (is_mips_addr (memaddr
))
1257 else if (is_micromips_addr (gdbarch
, memaddr
))
1258 return ISA_MICROMIPS
;
1264 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1265 The need for comes from the ISA bit having been cleared, making
1266 addresses in FDE, range records, etc. referring to compressed code
1267 different to those in line information, the symbol table and finally
1268 the PC register. That in turn confuses many operations. */
1271 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1273 pc
= unmake_compact_addr (pc
);
1274 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1277 /* Recalculate the line record requested so that the resulting PC has
1278 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1279 this adjustment comes from some records associated with compressed
1280 code having the ISA bit cleared, most notably at function prologue
1281 ends. The ISA bit is in this context retrieved from the minimal
1282 symbol covering the address requested, which in turn has been
1283 constructed from the binary's symbol table rather than DWARF-2
1284 information. The correct setting of the ISA bit is required for
1285 breakpoint addresses to correctly match against the stop PC.
1287 As line entries can specify relative address adjustments we need to
1288 keep track of the absolute value of the last line address recorded
1289 in line information, so that we can calculate the actual address to
1290 apply the ISA bit adjustment to. We use PC for this tracking and
1291 keep the original address there.
1293 As such relative address adjustments can be odd within compressed
1294 code we need to keep track of the last line address with the ISA
1295 bit adjustment applied too, as the original address may or may not
1296 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1297 the adjusted address there.
1299 For relative address adjustments we then use these variables to
1300 calculate the address intended by line information, which will be
1301 PC-relative, and return an updated adjustment carrying ISA bit
1302 information, which will be ADJ_PC-relative. For absolute address
1303 adjustments we just return the same address that we store in ADJ_PC
1306 As the first line entry can be relative to an implied address value
1307 of 0 we need to have the initial address set up that we store in PC
1308 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1309 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1312 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1314 static CORE_ADDR adj_pc
;
1315 static CORE_ADDR pc
;
1318 pc
= rel
? pc
+ addr
: addr
;
1319 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1320 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1325 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1327 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1328 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1329 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1330 static const char mips_str_call_stub
[] = "__call_stub_";
1331 static const char mips_str_fn_stub
[] = "__fn_stub_";
1333 /* This is used as a PIC thunk prefix. */
1335 static const char mips_str_pic
[] = ".pic.";
1337 /* Return non-zero if the PC is inside a call thunk (aka stub or
1338 trampoline) that should be treated as a temporary frame. */
1341 mips_in_frame_stub (CORE_ADDR pc
)
1343 CORE_ADDR start_addr
;
1346 /* Find the starting address of the function containing the PC. */
1347 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1350 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1351 if (startswith (name
, mips_str_mips16_call_stub
))
1353 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1354 if (startswith (name
, mips_str_call_stub
))
1356 /* If the PC is in __fn_stub_*, this is a call stub. */
1357 if (startswith (name
, mips_str_fn_stub
))
1360 return 0; /* Not a stub. */
1363 /* MIPS believes that the PC has a sign extended value. Perhaps the
1364 all registers should be sign extended for simplicity? */
1367 mips_read_pc (struct regcache
*regcache
)
1369 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1372 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1377 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1381 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1382 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1383 intermediate frames. In this case we can get the caller's address
1384 from $ra, or if $ra contains an address within a thunk as well, then
1385 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1386 and thus the caller's address is in $s2. */
1387 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1389 pc
= frame_unwind_register_signed
1390 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1391 if (mips_in_frame_stub (pc
))
1392 pc
= frame_unwind_register_signed
1393 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1399 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1401 return frame_unwind_register_signed
1402 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1405 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1406 dummy frame. The frame ID's base needs to match the TOS value
1407 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1410 static struct frame_id
1411 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1413 return frame_id_build
1414 (get_frame_register_signed (this_frame
,
1415 gdbarch_num_regs (gdbarch
)
1417 get_frame_pc (this_frame
));
1420 /* Implement the "write_pc" gdbarch method. */
1423 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1425 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1427 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1430 /* Fetch and return instruction from the specified location. Handle
1431 MIPS16/microMIPS as appropriate. */
1434 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1435 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1437 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1438 gdb_byte buf
[MIPS_INSN32_SIZE
];
1446 instlen
= MIPS_INSN16_SIZE
;
1447 addr
= unmake_compact_addr (addr
);
1450 instlen
= MIPS_INSN32_SIZE
;
1453 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1456 err
= target_read_memory (addr
, buf
, instlen
);
1462 memory_error (TARGET_XFER_E_IO
, addr
);
1465 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1468 /* These are the fields of 32 bit mips instructions. */
1469 #define mips32_op(x) (x >> 26)
1470 #define itype_op(x) (x >> 26)
1471 #define itype_rs(x) ((x >> 21) & 0x1f)
1472 #define itype_rt(x) ((x >> 16) & 0x1f)
1473 #define itype_immediate(x) (x & 0xffff)
1475 #define jtype_op(x) (x >> 26)
1476 #define jtype_target(x) (x & 0x03ffffff)
1478 #define rtype_op(x) (x >> 26)
1479 #define rtype_rs(x) ((x >> 21) & 0x1f)
1480 #define rtype_rt(x) ((x >> 16) & 0x1f)
1481 #define rtype_rd(x) ((x >> 11) & 0x1f)
1482 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1483 #define rtype_funct(x) (x & 0x3f)
1485 /* MicroMIPS instruction fields. */
1486 #define micromips_op(x) ((x) >> 10)
1488 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1489 bit and the size respectively of the field extracted. */
1490 #define b0s4_imm(x) ((x) & 0xf)
1491 #define b0s5_imm(x) ((x) & 0x1f)
1492 #define b0s5_reg(x) ((x) & 0x1f)
1493 #define b0s7_imm(x) ((x) & 0x7f)
1494 #define b0s10_imm(x) ((x) & 0x3ff)
1495 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1496 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1497 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1498 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1499 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1500 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1501 #define b6s4_op(x) (((x) >> 6) & 0xf)
1502 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1504 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1505 respectively of the field extracted. */
1506 #define b0s6_op(x) ((x) & 0x3f)
1507 #define b0s11_op(x) ((x) & 0x7ff)
1508 #define b0s12_imm(x) ((x) & 0xfff)
1509 #define b0s16_imm(x) ((x) & 0xffff)
1510 #define b0s26_imm(x) ((x) & 0x3ffffff)
1511 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1512 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1513 #define b12s4_op(x) (((x) >> 12) & 0xf)
1515 /* Return the size in bytes of the instruction INSN encoded in the ISA
1519 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1524 if ((micromips_op (insn
) & 0x4) == 0x4
1525 || (micromips_op (insn
) & 0x7) == 0x0)
1526 return 2 * MIPS_INSN16_SIZE
;
1528 return MIPS_INSN16_SIZE
;
1530 if ((insn
& 0xf800) == 0xf000)
1531 return 2 * MIPS_INSN16_SIZE
;
1533 return MIPS_INSN16_SIZE
;
1535 return MIPS_INSN32_SIZE
;
1537 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1541 mips32_relative_offset (ULONGEST inst
)
1543 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1546 /* Determine the address of the next instruction executed after the INST
1547 floating condition branch instruction at PC. COUNT specifies the
1548 number of the floating condition bits tested by the branch. */
1551 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1552 ULONGEST inst
, CORE_ADDR pc
, int count
)
1554 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1555 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1556 int tf
= itype_rt (inst
) & 1;
1557 int mask
= (1 << count
) - 1;
1562 /* No way to handle; it'll most likely trap anyway. */
1565 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1566 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1568 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1569 pc
+= mips32_relative_offset (inst
);
1576 /* Return nonzero if the gdbarch is an Octeon series. */
1579 is_octeon (struct gdbarch
*gdbarch
)
1581 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1583 return (info
->mach
== bfd_mach_mips_octeon
1584 || info
->mach
== bfd_mach_mips_octeonp
1585 || info
->mach
== bfd_mach_mips_octeon2
);
1588 /* Return true if the OP represents the Octeon's BBIT instruction. */
1591 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1593 if (!is_octeon (gdbarch
))
1595 /* BBIT0 is encoded as LWC2: 110 010. */
1596 /* BBIT032 is encoded as LDC2: 110 110. */
1597 /* BBIT1 is encoded as SWC2: 111 010. */
1598 /* BBIT132 is encoded as SDC2: 111 110. */
1599 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1605 /* Determine where to set a single step breakpoint while considering
1606 branch prediction. */
1609 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1611 struct gdbarch
*gdbarch
= regcache
->arch ();
1614 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1615 op
= itype_op (inst
);
1616 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1620 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1631 goto greater_branch
;
1636 else if (op
== 17 && itype_rs (inst
) == 8)
1637 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1638 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1639 else if (op
== 17 && itype_rs (inst
) == 9
1640 && (itype_rt (inst
) & 2) == 0)
1641 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1642 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1643 else if (op
== 17 && itype_rs (inst
) == 10
1644 && (itype_rt (inst
) & 2) == 0)
1645 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1646 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1649 /* The new PC will be alternate mode. */
1653 reg
= jtype_target (inst
) << 2;
1654 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1655 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1657 else if (is_octeon_bbit_op (op
, gdbarch
))
1661 branch_if
= op
== 58 || op
== 62;
1662 bit
= itype_rt (inst
);
1664 /* Take into account the *32 instructions. */
1665 if (op
== 54 || op
== 62)
1668 if (((regcache_raw_get_signed (regcache
,
1669 itype_rs (inst
)) >> bit
) & 1)
1671 pc
+= mips32_relative_offset (inst
) + 4;
1673 pc
+= 8; /* After the delay slot. */
1677 pc
+= 4; /* Not a branch, next instruction is easy. */
1680 { /* This gets way messy. */
1682 /* Further subdivide into SPECIAL, REGIMM and other. */
1683 switch (op
& 0x07) /* Extract bits 28,27,26. */
1685 case 0: /* SPECIAL */
1686 op
= rtype_funct (inst
);
1691 /* Set PC to that address. */
1692 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1694 case 12: /* SYSCALL */
1696 struct gdbarch_tdep
*tdep
;
1698 tdep
= gdbarch_tdep (gdbarch
);
1699 if (tdep
->syscall_next_pc
!= NULL
)
1700 pc
= tdep
->syscall_next_pc (get_current_frame ());
1709 break; /* end SPECIAL */
1710 case 1: /* REGIMM */
1712 op
= itype_rt (inst
); /* branch condition */
1717 case 16: /* BLTZAL */
1718 case 18: /* BLTZALL */
1720 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1721 pc
+= mips32_relative_offset (inst
) + 4;
1723 pc
+= 8; /* after the delay slot */
1727 case 17: /* BGEZAL */
1728 case 19: /* BGEZALL */
1729 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1730 pc
+= mips32_relative_offset (inst
) + 4;
1732 pc
+= 8; /* after the delay slot */
1734 case 0x1c: /* BPOSGE32 */
1735 case 0x1e: /* BPOSGE64 */
1737 if (itype_rs (inst
) == 0)
1739 unsigned int pos
= (op
& 2) ? 64 : 32;
1740 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1743 /* No way to handle; it'll most likely trap anyway. */
1746 if ((regcache_raw_get_unsigned (regcache
,
1747 dspctl
) & 0x7f) >= pos
)
1748 pc
+= mips32_relative_offset (inst
);
1753 /* All of the other instructions in the REGIMM category */
1758 break; /* end REGIMM */
1763 reg
= jtype_target (inst
) << 2;
1764 /* Upper four bits get never changed... */
1765 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1768 case 4: /* BEQ, BEQL */
1770 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1771 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1772 pc
+= mips32_relative_offset (inst
) + 4;
1776 case 5: /* BNE, BNEL */
1778 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1779 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1780 pc
+= mips32_relative_offset (inst
) + 4;
1784 case 6: /* BLEZ, BLEZL */
1785 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1786 pc
+= mips32_relative_offset (inst
) + 4;
1792 greater_branch
: /* BGTZ, BGTZL */
1793 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1794 pc
+= mips32_relative_offset (inst
) + 4;
1801 } /* mips32_next_pc */
1803 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1807 micromips_relative_offset7 (ULONGEST insn
)
1809 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1812 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1816 micromips_relative_offset10 (ULONGEST insn
)
1818 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1821 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1825 micromips_relative_offset16 (ULONGEST insn
)
1827 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1830 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1833 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1837 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1838 return mips_insn_size (ISA_MICROMIPS
, insn
);
1841 /* Calculate the address of the next microMIPS instruction to execute
1842 after the INSN coprocessor 1 conditional branch instruction at the
1843 address PC. COUNT denotes the number of coprocessor condition bits
1844 examined by the branch. */
1847 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1848 ULONGEST insn
, CORE_ADDR pc
, int count
)
1850 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1851 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1852 int tf
= b5s5_op (insn
>> 16) & 1;
1853 int mask
= (1 << count
) - 1;
1858 /* No way to handle; it'll most likely trap anyway. */
1861 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1862 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1864 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1865 pc
+= micromips_relative_offset16 (insn
);
1867 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1872 /* Calculate the address of the next microMIPS instruction to execute
1873 after the instruction at the address PC. */
1876 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1878 struct gdbarch
*gdbarch
= regcache
->arch ();
1881 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1882 pc
+= MIPS_INSN16_SIZE
;
1883 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1885 /* 32-bit instructions. */
1886 case 2 * MIPS_INSN16_SIZE
:
1888 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1889 pc
+= MIPS_INSN16_SIZE
;
1890 switch (micromips_op (insn
>> 16))
1892 case 0x00: /* POOL32A: bits 000000 */
1893 if (b0s6_op (insn
) == 0x3c
1894 /* POOL32Axf: bits 000000 ... 111100 */
1895 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1896 /* JALR, JALR.HB: 000000 000x111100 111100 */
1897 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1898 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16));
1901 case 0x10: /* POOL32I: bits 010000 */
1902 switch (b5s5_op (insn
>> 16))
1904 case 0x00: /* BLTZ: bits 010000 00000 */
1905 case 0x01: /* BLTZAL: bits 010000 00001 */
1906 case 0x11: /* BLTZALS: bits 010000 10001 */
1907 if (regcache_raw_get_signed (regcache
,
1908 b0s5_reg (insn
>> 16)) < 0)
1909 pc
+= micromips_relative_offset16 (insn
);
1911 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1914 case 0x02: /* BGEZ: bits 010000 00010 */
1915 case 0x03: /* BGEZAL: bits 010000 00011 */
1916 case 0x13: /* BGEZALS: bits 010000 10011 */
1917 if (regcache_raw_get_signed (regcache
,
1918 b0s5_reg (insn
>> 16)) >= 0)
1919 pc
+= micromips_relative_offset16 (insn
);
1921 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1924 case 0x04: /* BLEZ: bits 010000 00100 */
1925 if (regcache_raw_get_signed (regcache
,
1926 b0s5_reg (insn
>> 16)) <= 0)
1927 pc
+= micromips_relative_offset16 (insn
);
1929 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1932 case 0x05: /* BNEZC: bits 010000 00101 */
1933 if (regcache_raw_get_signed (regcache
,
1934 b0s5_reg (insn
>> 16)) != 0)
1935 pc
+= micromips_relative_offset16 (insn
);
1938 case 0x06: /* BGTZ: bits 010000 00110 */
1939 if (regcache_raw_get_signed (regcache
,
1940 b0s5_reg (insn
>> 16)) > 0)
1941 pc
+= micromips_relative_offset16 (insn
);
1943 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1946 case 0x07: /* BEQZC: bits 010000 00111 */
1947 if (regcache_raw_get_signed (regcache
,
1948 b0s5_reg (insn
>> 16)) == 0)
1949 pc
+= micromips_relative_offset16 (insn
);
1952 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1953 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1954 if (((insn
>> 16) & 0x3) == 0x0)
1955 /* BC2F, BC2T: don't know how to handle these. */
1959 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1960 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1962 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1963 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1966 /* No way to handle; it'll most likely trap anyway. */
1969 if ((regcache_raw_get_unsigned (regcache
,
1970 dspctl
) & 0x7f) >= pos
)
1971 pc
+= micromips_relative_offset16 (insn
);
1973 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1977 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1978 /* BC1ANY2F: bits 010000 11100 xxx01 */
1979 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1980 /* BC1ANY2T: bits 010000 11101 xxx01 */
1981 if (((insn
>> 16) & 0x2) == 0x0)
1982 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
1983 ((insn
>> 16) & 0x1) + 1);
1986 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1987 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1988 if (((insn
>> 16) & 0x3) == 0x1)
1989 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
1994 case 0x1d: /* JALS: bits 011101 */
1995 case 0x35: /* J: bits 110101 */
1996 case 0x3d: /* JAL: bits 111101 */
1997 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2000 case 0x25: /* BEQ: bits 100101 */
2001 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2002 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2003 pc
+= micromips_relative_offset16 (insn
);
2005 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2008 case 0x2d: /* BNE: bits 101101 */
2009 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2010 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2011 pc
+= micromips_relative_offset16 (insn
);
2013 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2016 case 0x3c: /* JALX: bits 111100 */
2017 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2022 /* 16-bit instructions. */
2023 case MIPS_INSN16_SIZE
:
2024 switch (micromips_op (insn
))
2026 case 0x11: /* POOL16C: bits 010001 */
2027 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2028 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2029 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2030 else if (b5s5_op (insn
) == 0x18)
2031 /* JRADDIUSP: bits 010001 11000 */
2032 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2035 case 0x23: /* BEQZ16: bits 100011 */
2037 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2039 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2040 pc
+= micromips_relative_offset7 (insn
);
2042 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2046 case 0x2b: /* BNEZ16: bits 101011 */
2048 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2050 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2051 pc
+= micromips_relative_offset7 (insn
);
2053 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2057 case 0x33: /* B16: bits 110011 */
2058 pc
+= micromips_relative_offset10 (insn
);
2067 /* Decoding the next place to set a breakpoint is irregular for the
2068 mips 16 variant, but fortunately, there fewer instructions. We have
2069 to cope ith extensions for 16 bit instructions and a pair of actual
2070 32 bit instructions. We dont want to set a single step instruction
2071 on the extend instruction either. */
2073 /* Lots of mips16 instruction formats */
2074 /* Predicting jumps requires itype,ritype,i8type
2075 and their extensions extItype,extritype,extI8type. */
2076 enum mips16_inst_fmts
2078 itype
, /* 0 immediate 5,10 */
2079 ritype
, /* 1 5,3,8 */
2080 rrtype
, /* 2 5,3,3,5 */
2081 rritype
, /* 3 5,3,3,5 */
2082 rrrtype
, /* 4 5,3,3,3,2 */
2083 rriatype
, /* 5 5,3,3,1,4 */
2084 shifttype
, /* 6 5,3,3,3,2 */
2085 i8type
, /* 7 5,3,8 */
2086 i8movtype
, /* 8 5,3,3,5 */
2087 i8mov32rtype
, /* 9 5,3,5,3 */
2088 i64type
, /* 10 5,3,8 */
2089 ri64type
, /* 11 5,3,3,5 */
2090 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2091 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2092 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2093 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2094 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2095 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2096 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2097 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2098 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2099 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2101 /* I am heaping all the fields of the formats into one structure and
2102 then, only the fields which are involved in instruction extension. */
2106 unsigned int regx
; /* Function in i8 type. */
2111 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2112 for the bits which make up the immediate extension. */
2115 extended_offset (unsigned int extension
)
2119 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2121 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2123 value
|= extension
& 0x1f; /* Extract 4:0. */
2128 /* Only call this function if you know that this is an extendable
2129 instruction. It won't malfunction, but why make excess remote memory
2130 references? If the immediate operands get sign extended or something,
2131 do it after the extension is performed. */
2132 /* FIXME: Every one of these cases needs to worry about sign extension
2133 when the offset is to be used in relative addressing. */
2136 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2138 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2141 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2142 target_read_memory (pc
, buf
, 2);
2143 return extract_unsigned_integer (buf
, 2, byte_order
);
2147 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2148 unsigned int extension
,
2150 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2155 switch (insn_format
)
2162 value
= extended_offset ((extension
<< 16) | inst
);
2163 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2167 value
= inst
& 0x7ff;
2168 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2177 { /* A register identifier and an offset. */
2178 /* Most of the fields are the same as I type but the
2179 immediate value is of a different length. */
2183 value
= extended_offset ((extension
<< 16) | inst
);
2184 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2188 value
= inst
& 0xff; /* 8 bits */
2189 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2192 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2198 unsigned long value
;
2199 unsigned int nexthalf
;
2200 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2201 value
= value
<< 16;
2202 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2203 /* Low bit still set. */
2211 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2213 upk
->offset
= offset
;
2219 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2220 and having a signed 16-bit OFFSET. */
2223 add_offset_16 (CORE_ADDR pc
, int offset
)
2225 return pc
+ (offset
<< 1) + 2;
2229 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2230 unsigned int extension
, unsigned int insn
)
2232 struct gdbarch
*gdbarch
= regcache
->arch ();
2233 int op
= (insn
>> 11);
2236 case 2: /* Branch */
2238 struct upk_mips16 upk
;
2239 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2240 pc
= add_offset_16 (pc
, upk
.offset
);
2243 case 3: /* JAL , JALX - Watch out, these are 32 bit
2246 struct upk_mips16 upk
;
2247 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2248 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2249 if ((insn
>> 10) & 0x01) /* Exchange mode */
2250 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2257 struct upk_mips16 upk
;
2259 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2260 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2262 pc
= add_offset_16 (pc
, upk
.offset
);
2269 struct upk_mips16 upk
;
2271 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2272 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2274 pc
= add_offset_16 (pc
, upk
.offset
);
2279 case 12: /* I8 Formats btez btnez */
2281 struct upk_mips16 upk
;
2283 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2284 /* upk.regx contains the opcode */
2285 /* Test register is 24 */
2286 reg
= regcache_raw_get_signed (regcache
, 24);
2287 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2288 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2289 pc
= add_offset_16 (pc
, upk
.offset
);
2294 case 29: /* RR Formats JR, JALR, JALR-RA */
2296 struct upk_mips16 upk
;
2297 /* upk.fmt = rrtype; */
2302 upk
.regx
= (insn
>> 8) & 0x07;
2303 upk
.regy
= (insn
>> 5) & 0x07;
2304 if ((upk
.regy
& 1) == 0)
2305 reg
= mips_reg3_to_reg
[upk
.regx
];
2307 reg
= 31; /* Function return instruction. */
2308 pc
= regcache_raw_get_signed (regcache
, reg
);
2315 /* This is an instruction extension. Fetch the real instruction
2316 (which follows the extension) and decode things based on
2320 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2321 fetch_mips_16 (gdbarch
, pc
));
2334 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2336 struct gdbarch
*gdbarch
= regcache
->arch ();
2337 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2338 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2341 /* The mips_next_pc function supports single_step when the remote
2342 target monitor or stub is not developed enough to do a single_step.
2343 It works by decoding the current instruction and predicting where a
2344 branch will go. This isn't hard because all the data is available.
2345 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2347 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2349 struct gdbarch
*gdbarch
= regcache
->arch ();
2351 if (mips_pc_is_mips16 (gdbarch
, pc
))
2352 return mips16_next_pc (regcache
, pc
);
2353 else if (mips_pc_is_micromips (gdbarch
, pc
))
2354 return micromips_next_pc (regcache
, pc
);
2356 return mips32_next_pc (regcache
, pc
);
2359 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2363 mips16_instruction_is_compact_branch (unsigned short insn
)
2365 switch (insn
& 0xf800)
2368 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2370 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2371 case 0x2800: /* BNEZ */
2372 case 0x2000: /* BEQZ */
2373 case 0x1000: /* B */
2380 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2384 micromips_instruction_is_compact_branch (unsigned short insn
)
2386 switch (micromips_op (insn
))
2388 case 0x11: /* POOL16C: bits 010001 */
2389 return (b5s5_op (insn
) == 0x18
2390 /* JRADDIUSP: bits 010001 11000 */
2391 || b5s5_op (insn
) == 0xd);
2392 /* JRC: bits 010011 01101 */
2393 case 0x10: /* POOL32I: bits 010000 */
2394 return (b5s5_op (insn
) & 0x1d) == 0x5;
2395 /* BEQZC/BNEZC: bits 010000 001x1 */
2401 struct mips_frame_cache
2404 struct trad_frame_saved_reg
*saved_regs
;
2407 /* Set a register's saved stack address in temp_saved_regs. If an
2408 address has already been set for this register, do nothing; this
2409 way we will only recognize the first save of a given register in a
2412 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2413 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2414 Strictly speaking, only the second range is used as it is only second
2415 range (the ABI instead of ISA registers) that comes into play when finding
2416 saved registers in a frame. */
2419 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2420 int regnum
, CORE_ADDR offset
)
2422 if (this_cache
!= NULL
2423 && this_cache
->saved_regs
[regnum
].addr
== -1)
2425 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2427 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2433 /* Fetch the immediate value from a MIPS16 instruction.
2434 If the previous instruction was an EXTEND, use it to extend
2435 the upper bits of the immediate value. This is a helper function
2436 for mips16_scan_prologue. */
2439 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2440 unsigned short inst
, /* current instruction */
2441 int nbits
, /* number of bits in imm field */
2442 int scale
, /* scale factor to be applied to imm */
2443 int is_signed
) /* is the imm field signed? */
2447 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2449 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2450 if (offset
& 0x8000) /* check for negative extend */
2451 offset
= 0 - (0x10000 - (offset
& 0xffff));
2452 return offset
| (inst
& 0x1f);
2456 int max_imm
= 1 << nbits
;
2457 int mask
= max_imm
- 1;
2458 int sign_bit
= max_imm
>> 1;
2460 offset
= inst
& mask
;
2461 if (is_signed
&& (offset
& sign_bit
))
2462 offset
= 0 - (max_imm
- offset
);
2463 return offset
* scale
;
2468 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2469 the associated FRAME_CACHE if not null.
2470 Return the address of the first instruction past the prologue. */
2473 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2474 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2475 struct frame_info
*this_frame
,
2476 struct mips_frame_cache
*this_cache
)
2478 int prev_non_prologue_insn
= 0;
2479 int this_non_prologue_insn
;
2480 int non_prologue_insns
= 0;
2483 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2485 long frame_offset
= 0; /* Size of stack frame. */
2486 long frame_adjust
= 0; /* Offset of FP from SP. */
2487 int frame_reg
= MIPS_SP_REGNUM
;
2488 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2489 unsigned inst
= 0; /* current instruction */
2490 unsigned entry_inst
= 0; /* the entry instruction */
2491 unsigned save_inst
= 0; /* the save instruction */
2492 int prev_delay_slot
= 0;
2496 int extend_bytes
= 0;
2497 int prev_extend_bytes
= 0;
2498 CORE_ADDR end_prologue_addr
;
2500 /* Can be called when there's no process, and hence when there's no
2502 if (this_frame
!= NULL
)
2503 sp
= get_frame_register_signed (this_frame
,
2504 gdbarch_num_regs (gdbarch
)
2509 if (limit_pc
> start_pc
+ 200)
2510 limit_pc
= start_pc
+ 200;
2513 /* Permit at most one non-prologue non-control-transfer instruction
2514 in the middle which may have been reordered by the compiler for
2516 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2518 this_non_prologue_insn
= 0;
2521 /* Save the previous instruction. If it's an EXTEND, we'll extract
2522 the immediate offset extension from it in mips16_get_imm. */
2525 /* Fetch and decode the instruction. */
2526 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2529 /* Normally we ignore extend instructions. However, if it is
2530 not followed by a valid prologue instruction, then this
2531 instruction is not part of the prologue either. We must
2532 remember in this case to adjust the end_prologue_addr back
2534 if ((inst
& 0xf800) == 0xf000) /* extend */
2536 extend_bytes
= MIPS_INSN16_SIZE
;
2540 prev_extend_bytes
= extend_bytes
;
2543 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2544 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2546 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2547 if (offset
< 0) /* Negative stack adjustment? */
2548 frame_offset
-= offset
;
2550 /* Exit loop if a positive stack adjustment is found, which
2551 usually means that the stack cleanup code in the function
2552 epilogue is reached. */
2555 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2557 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2558 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2559 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2561 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2563 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2564 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2565 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2567 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2569 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2570 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2572 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2574 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2575 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2577 else if (inst
== 0x673d) /* move $s1, $sp */
2582 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2584 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2585 frame_addr
= sp
+ offset
;
2587 frame_adjust
= offset
;
2589 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2591 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2592 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2593 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2595 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2597 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2598 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2599 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2601 else if ((inst
& 0xf81f) == 0xe809
2602 && (inst
& 0x700) != 0x700) /* entry */
2603 entry_inst
= inst
; /* Save for later processing. */
2604 else if ((inst
& 0xff80) == 0x6480) /* save */
2606 save_inst
= inst
; /* Save for later processing. */
2607 if (prev_extend_bytes
) /* extend */
2608 save_inst
|= prev_inst
<< 16;
2610 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2612 /* This instruction is part of the prologue, but we don't
2613 need to do anything special to handle it. */
2615 else if (mips16_instruction_has_delay_slot (inst
, 0))
2616 /* JAL/JALR/JALX/JR */
2618 /* The instruction in the delay slot can be a part
2619 of the prologue, so move forward once more. */
2621 if (mips16_instruction_has_delay_slot (inst
, 1))
2624 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2625 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2630 this_non_prologue_insn
= 1;
2633 non_prologue_insns
+= this_non_prologue_insn
;
2635 /* A jump or branch, or enough non-prologue insns seen? If so,
2636 then we must have reached the end of the prologue by now. */
2637 if (prev_delay_slot
|| non_prologue_insns
> 1
2638 || mips16_instruction_is_compact_branch (inst
))
2641 prev_non_prologue_insn
= this_non_prologue_insn
;
2642 prev_delay_slot
= in_delay_slot
;
2643 prev_pc
= cur_pc
- prev_extend_bytes
;
2646 /* The entry instruction is typically the first instruction in a function,
2647 and it stores registers at offsets relative to the value of the old SP
2648 (before the prologue). But the value of the sp parameter to this
2649 function is the new SP (after the prologue has been executed). So we
2650 can't calculate those offsets until we've seen the entire prologue,
2651 and can calculate what the old SP must have been. */
2652 if (entry_inst
!= 0)
2654 int areg_count
= (entry_inst
>> 8) & 7;
2655 int sreg_count
= (entry_inst
>> 6) & 3;
2657 /* The entry instruction always subtracts 32 from the SP. */
2660 /* Now we can calculate what the SP must have been at the
2661 start of the function prologue. */
2664 /* Check if a0-a3 were saved in the caller's argument save area. */
2665 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2667 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2668 offset
+= mips_abi_regsize (gdbarch
);
2671 /* Check if the ra register was pushed on the stack. */
2673 if (entry_inst
& 0x20)
2675 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2676 offset
-= mips_abi_regsize (gdbarch
);
2679 /* Check if the s0 and s1 registers were pushed on the stack. */
2680 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2682 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2683 offset
-= mips_abi_regsize (gdbarch
);
2687 /* The SAVE instruction is similar to ENTRY, except that defined by the
2688 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2689 size of the frame is specified as an immediate field of instruction
2690 and an extended variation exists which lets additional registers and
2691 frame space to be specified. The instruction always treats registers
2692 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2693 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2695 static int args_table
[16] = {
2696 0, 0, 0, 0, 1, 1, 1, 1,
2697 2, 2, 2, 0, 3, 3, 4, -1,
2699 static int astatic_table
[16] = {
2700 0, 1, 2, 3, 0, 1, 2, 3,
2701 0, 1, 2, 4, 0, 1, 0, -1,
2703 int aregs
= (save_inst
>> 16) & 0xf;
2704 int xsregs
= (save_inst
>> 24) & 0x7;
2705 int args
= args_table
[aregs
];
2706 int astatic
= astatic_table
[aregs
];
2711 warning (_("Invalid number of argument registers encoded in SAVE."));
2716 warning (_("Invalid number of static registers encoded in SAVE."));
2720 /* For standard SAVE the frame size of 0 means 128. */
2721 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2722 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2725 frame_offset
+= frame_size
;
2727 /* Now we can calculate what the SP must have been at the
2728 start of the function prologue. */
2731 /* Check if A0-A3 were saved in the caller's argument save area. */
2732 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2734 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2735 offset
+= mips_abi_regsize (gdbarch
);
2740 /* Check if the RA register was pushed on the stack. */
2741 if (save_inst
& 0x40)
2743 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2744 offset
-= mips_abi_regsize (gdbarch
);
2747 /* Check if the S8 register was pushed on the stack. */
2750 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2751 offset
-= mips_abi_regsize (gdbarch
);
2754 /* Check if S2-S7 were pushed on the stack. */
2755 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2757 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2758 offset
-= mips_abi_regsize (gdbarch
);
2761 /* Check if the S1 register was pushed on the stack. */
2762 if (save_inst
& 0x10)
2764 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2765 offset
-= mips_abi_regsize (gdbarch
);
2767 /* Check if the S0 register was pushed on the stack. */
2768 if (save_inst
& 0x20)
2770 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2771 offset
-= mips_abi_regsize (gdbarch
);
2774 /* Check if A0-A3 were pushed on the stack. */
2775 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2777 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2778 offset
-= mips_abi_regsize (gdbarch
);
2782 if (this_cache
!= NULL
)
2785 (get_frame_register_signed (this_frame
,
2786 gdbarch_num_regs (gdbarch
) + frame_reg
)
2787 + frame_offset
- frame_adjust
);
2788 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2789 be able to get rid of the assignment below, evetually. But it's
2790 still needed for now. */
2791 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2792 + mips_regnum (gdbarch
)->pc
]
2793 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2796 /* Set end_prologue_addr to the address of the instruction immediately
2797 after the last one we scanned. Unless the last one looked like a
2798 non-prologue instruction (and we looked ahead), in which case use
2799 its address instead. */
2800 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2801 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2803 return end_prologue_addr
;
2806 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2807 Procedures that use the 32-bit instruction set are handled by the
2808 mips_insn32 unwinder. */
2810 static struct mips_frame_cache
*
2811 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2813 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2814 struct mips_frame_cache
*cache
;
2816 if ((*this_cache
) != NULL
)
2817 return (struct mips_frame_cache
*) (*this_cache
);
2818 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2819 (*this_cache
) = cache
;
2820 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2822 /* Analyze the function prologue. */
2824 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2825 CORE_ADDR start_addr
;
2827 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2828 if (start_addr
== 0)
2829 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2830 /* We can't analyze the prologue if we couldn't find the begining
2832 if (start_addr
== 0)
2835 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2836 (struct mips_frame_cache
*) *this_cache
);
2839 /* gdbarch_sp_regnum contains the value and not the address. */
2840 trad_frame_set_value (cache
->saved_regs
,
2841 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2844 return (struct mips_frame_cache
*) (*this_cache
);
2848 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2849 struct frame_id
*this_id
)
2851 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2853 /* This marks the outermost frame. */
2854 if (info
->base
== 0)
2856 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2859 static struct value
*
2860 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2861 void **this_cache
, int regnum
)
2863 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2865 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2869 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2870 struct frame_info
*this_frame
, void **this_cache
)
2872 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2873 CORE_ADDR pc
= get_frame_pc (this_frame
);
2874 if (mips_pc_is_mips16 (gdbarch
, pc
))
2879 static const struct frame_unwind mips_insn16_frame_unwind
=
2882 default_frame_unwind_stop_reason
,
2883 mips_insn16_frame_this_id
,
2884 mips_insn16_frame_prev_register
,
2886 mips_insn16_frame_sniffer
2890 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2893 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2898 static const struct frame_base mips_insn16_frame_base
=
2900 &mips_insn16_frame_unwind
,
2901 mips_insn16_frame_base_address
,
2902 mips_insn16_frame_base_address
,
2903 mips_insn16_frame_base_address
2906 static const struct frame_base
*
2907 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2909 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2910 CORE_ADDR pc
= get_frame_pc (this_frame
);
2911 if (mips_pc_is_mips16 (gdbarch
, pc
))
2912 return &mips_insn16_frame_base
;
2917 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2918 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2919 interpreted directly, and then multiplied by 4. */
2922 micromips_decode_imm9 (int imm
)
2924 imm
= (imm
^ 0x100) - 0x100;
2925 if (imm
> -3 && imm
< 2)
2930 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2931 the address of the first instruction past the prologue. */
2934 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2935 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2936 struct frame_info
*this_frame
,
2937 struct mips_frame_cache
*this_cache
)
2939 CORE_ADDR end_prologue_addr
;
2940 int prev_non_prologue_insn
= 0;
2941 int frame_reg
= MIPS_SP_REGNUM
;
2942 int this_non_prologue_insn
;
2943 int non_prologue_insns
= 0;
2944 long frame_offset
= 0; /* Size of stack frame. */
2945 long frame_adjust
= 0; /* Offset of FP from SP. */
2946 int prev_delay_slot
= 0;
2950 ULONGEST insn
; /* current instruction */
2954 long v1_off
= 0; /* The assumption is LUI will replace it. */
2965 /* Can be called when there's no process, and hence when there's no
2967 if (this_frame
!= NULL
)
2968 sp
= get_frame_register_signed (this_frame
,
2969 gdbarch_num_regs (gdbarch
)
2974 if (limit_pc
> start_pc
+ 200)
2975 limit_pc
= start_pc
+ 200;
2978 /* Permit at most one non-prologue non-control-transfer instruction
2979 in the middle which may have been reordered by the compiler for
2981 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2983 this_non_prologue_insn
= 0;
2987 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2988 loc
+= MIPS_INSN16_SIZE
;
2989 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2991 /* 32-bit instructions. */
2992 case 2 * MIPS_INSN16_SIZE
:
2994 insn
|= mips_fetch_instruction (gdbarch
,
2995 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2996 loc
+= MIPS_INSN16_SIZE
;
2997 switch (micromips_op (insn
>> 16))
2999 /* Record $sp/$fp adjustment. */
3000 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3001 case 0x0: /* POOL32A: bits 000000 */
3002 case 0x16: /* POOL32S: bits 010110 */
3003 op
= b0s11_op (insn
);
3004 sreg
= b0s5_reg (insn
>> 16);
3005 treg
= b5s5_reg (insn
>> 16);
3006 dreg
= b11s5_reg (insn
);
3008 /* SUBU: bits 000000 00111010000 */
3009 /* DSUBU: bits 010110 00111010000 */
3010 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3012 /* (D)SUBU $sp, $v1 */
3014 else if (op
!= 0x150
3015 /* ADDU: bits 000000 00101010000 */
3016 /* DADDU: bits 010110 00101010000 */
3017 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3018 this_non_prologue_insn
= 1;
3021 case 0x8: /* POOL32B: bits 001000 */
3022 op
= b12s4_op (insn
);
3023 breg
= b0s5_reg (insn
>> 16);
3024 reglist
= sreg
= b5s5_reg (insn
>> 16);
3025 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3026 if ((op
== 0x9 || op
== 0xc)
3027 /* SWP: bits 001000 1001 */
3028 /* SDP: bits 001000 1100 */
3029 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3030 /* S[DW]P reg,offset($sp) */
3032 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3033 set_reg_offset (gdbarch
, this_cache
,
3035 set_reg_offset (gdbarch
, this_cache
,
3036 sreg
+ 1, sp
+ offset
+ s
);
3038 else if ((op
== 0xd || op
== 0xf)
3039 /* SWM: bits 001000 1101 */
3040 /* SDM: bits 001000 1111 */
3041 && breg
== MIPS_SP_REGNUM
3042 /* SWM reglist,offset($sp) */
3043 && ((reglist
>= 1 && reglist
<= 9)
3044 || (reglist
>= 16 && reglist
<= 25)))
3046 int sreglist
= std::min(reglist
& 0xf, 8);
3048 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3049 for (i
= 0; i
< sreglist
; i
++)
3050 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3051 if ((reglist
& 0xf) > 8)
3052 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3053 if ((reglist
& 0x10) == 0x10)
3054 set_reg_offset (gdbarch
, this_cache
,
3055 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3058 this_non_prologue_insn
= 1;
3061 /* Record $sp/$fp adjustment. */
3062 /* Discard (D)ADDIU $gp used for PIC code. */
3063 case 0xc: /* ADDIU: bits 001100 */
3064 case 0x17: /* DADDIU: bits 010111 */
3065 sreg
= b0s5_reg (insn
>> 16);
3066 dreg
= b5s5_reg (insn
>> 16);
3067 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3068 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3069 /* (D)ADDIU $sp, imm */
3071 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3072 /* (D)ADDIU $fp, $sp, imm */
3074 frame_adjust
= offset
;
3077 else if (sreg
!= 28 || dreg
!= 28)
3078 /* (D)ADDIU $gp, imm */
3079 this_non_prologue_insn
= 1;
3082 /* LUI $v1 is used for larger $sp adjustments. */
3083 /* Discard LUI $gp used for PIC code. */
3084 case 0x10: /* POOL32I: bits 010000 */
3085 if (b5s5_op (insn
>> 16) == 0xd
3086 /* LUI: bits 010000 001101 */
3087 && b0s5_reg (insn
>> 16) == 3)
3089 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3090 else if (b5s5_op (insn
>> 16) != 0xd
3091 /* LUI: bits 010000 001101 */
3092 || b0s5_reg (insn
>> 16) != 28)
3094 this_non_prologue_insn
= 1;
3097 /* ORI $v1 is used for larger $sp adjustments. */
3098 case 0x14: /* ORI: bits 010100 */
3099 sreg
= b0s5_reg (insn
>> 16);
3100 dreg
= b5s5_reg (insn
>> 16);
3101 if (sreg
== 3 && dreg
== 3)
3103 v1_off
|= b0s16_imm (insn
);
3105 this_non_prologue_insn
= 1;
3108 case 0x26: /* SWC1: bits 100110 */
3109 case 0x2e: /* SDC1: bits 101110 */
3110 breg
= b0s5_reg (insn
>> 16);
3111 if (breg
!= MIPS_SP_REGNUM
)
3112 /* S[DW]C1 reg,offset($sp) */
3113 this_non_prologue_insn
= 1;
3116 case 0x36: /* SD: bits 110110 */
3117 case 0x3e: /* SW: bits 111110 */
3118 breg
= b0s5_reg (insn
>> 16);
3119 sreg
= b5s5_reg (insn
>> 16);
3120 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3121 if (breg
== MIPS_SP_REGNUM
)
3122 /* S[DW] reg,offset($sp) */
3123 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3125 this_non_prologue_insn
= 1;
3129 /* The instruction in the delay slot can be a part
3130 of the prologue, so move forward once more. */
3131 if (micromips_instruction_has_delay_slot (insn
, 0))
3134 this_non_prologue_insn
= 1;
3140 /* 16-bit instructions. */
3141 case MIPS_INSN16_SIZE
:
3142 switch (micromips_op (insn
))
3144 case 0x3: /* MOVE: bits 000011 */
3145 sreg
= b0s5_reg (insn
);
3146 dreg
= b5s5_reg (insn
);
3147 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3150 else if ((sreg
& 0x1c) != 0x4)
3151 /* MOVE reg, $a0-$a3 */
3152 this_non_prologue_insn
= 1;
3155 case 0x11: /* POOL16C: bits 010001 */
3156 if (b6s4_op (insn
) == 0x5)
3157 /* SWM: bits 010001 0101 */
3159 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3160 reglist
= b4s2_regl (insn
);
3161 for (i
= 0; i
<= reglist
; i
++)
3162 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3163 set_reg_offset (gdbarch
, this_cache
,
3164 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3167 this_non_prologue_insn
= 1;
3170 case 0x13: /* POOL16D: bits 010011 */
3171 if ((insn
& 0x1) == 0x1)
3172 /* ADDIUSP: bits 010011 1 */
3173 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3174 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3175 /* ADDIUS5: bits 010011 0 */
3176 /* ADDIUS5 $sp, imm */
3177 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3179 this_non_prologue_insn
= 1;
3182 case 0x32: /* SWSP: bits 110010 */
3183 offset
= b0s5_imm (insn
) << 2;
3184 sreg
= b5s5_reg (insn
);
3185 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3189 /* The instruction in the delay slot can be a part
3190 of the prologue, so move forward once more. */
3191 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3194 this_non_prologue_insn
= 1;
3200 frame_offset
-= sp_adj
;
3202 non_prologue_insns
+= this_non_prologue_insn
;
3204 /* A jump or branch, enough non-prologue insns seen or positive
3205 stack adjustment? If so, then we must have reached the end
3206 of the prologue by now. */
3207 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3208 || micromips_instruction_is_compact_branch (insn
))
3211 prev_non_prologue_insn
= this_non_prologue_insn
;
3212 prev_delay_slot
= in_delay_slot
;
3216 if (this_cache
!= NULL
)
3219 (get_frame_register_signed (this_frame
,
3220 gdbarch_num_regs (gdbarch
) + frame_reg
)
3221 + frame_offset
- frame_adjust
);
3222 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3223 be able to get rid of the assignment below, evetually. But it's
3224 still needed for now. */
3225 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3226 + mips_regnum (gdbarch
)->pc
]
3227 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3230 /* Set end_prologue_addr to the address of the instruction immediately
3231 after the last one we scanned. Unless the last one looked like a
3232 non-prologue instruction (and we looked ahead), in which case use
3233 its address instead. */
3235 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3237 return end_prologue_addr
;
3240 /* Heuristic unwinder for procedures using microMIPS instructions.
3241 Procedures that use the 32-bit instruction set are handled by the
3242 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3244 static struct mips_frame_cache
*
3245 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3247 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3248 struct mips_frame_cache
*cache
;
3250 if ((*this_cache
) != NULL
)
3251 return (struct mips_frame_cache
*) (*this_cache
);
3253 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3254 (*this_cache
) = cache
;
3255 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3257 /* Analyze the function prologue. */
3259 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3260 CORE_ADDR start_addr
;
3262 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3263 if (start_addr
== 0)
3264 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3265 /* We can't analyze the prologue if we couldn't find the begining
3267 if (start_addr
== 0)
3270 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3271 (struct mips_frame_cache
*) *this_cache
);
3274 /* gdbarch_sp_regnum contains the value and not the address. */
3275 trad_frame_set_value (cache
->saved_regs
,
3276 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3279 return (struct mips_frame_cache
*) (*this_cache
);
3283 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3284 struct frame_id
*this_id
)
3286 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3288 /* This marks the outermost frame. */
3289 if (info
->base
== 0)
3291 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3294 static struct value
*
3295 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3296 void **this_cache
, int regnum
)
3298 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3300 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3304 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3305 struct frame_info
*this_frame
, void **this_cache
)
3307 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3308 CORE_ADDR pc
= get_frame_pc (this_frame
);
3310 if (mips_pc_is_micromips (gdbarch
, pc
))
3315 static const struct frame_unwind mips_micro_frame_unwind
=
3318 default_frame_unwind_stop_reason
,
3319 mips_micro_frame_this_id
,
3320 mips_micro_frame_prev_register
,
3322 mips_micro_frame_sniffer
3326 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3329 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3334 static const struct frame_base mips_micro_frame_base
=
3336 &mips_micro_frame_unwind
,
3337 mips_micro_frame_base_address
,
3338 mips_micro_frame_base_address
,
3339 mips_micro_frame_base_address
3342 static const struct frame_base
*
3343 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3345 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3346 CORE_ADDR pc
= get_frame_pc (this_frame
);
3348 if (mips_pc_is_micromips (gdbarch
, pc
))
3349 return &mips_micro_frame_base
;
3354 /* Mark all the registers as unset in the saved_regs array
3355 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3358 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3360 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3364 const int num_regs
= gdbarch_num_regs (gdbarch
);
3367 for (i
= 0; i
< num_regs
; i
++)
3369 this_cache
->saved_regs
[i
].addr
= -1;
3374 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3375 the associated FRAME_CACHE if not null.
3376 Return the address of the first instruction past the prologue. */
3379 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3380 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3381 struct frame_info
*this_frame
,
3382 struct mips_frame_cache
*this_cache
)
3384 int prev_non_prologue_insn
;
3385 int this_non_prologue_insn
;
3386 int non_prologue_insns
;
3387 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3389 int prev_delay_slot
;
3394 int frame_reg
= MIPS_SP_REGNUM
;
3396 CORE_ADDR end_prologue_addr
;
3397 int seen_sp_adjust
= 0;
3398 int load_immediate_bytes
= 0;
3400 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3402 /* Can be called when there's no process, and hence when there's no
3404 if (this_frame
!= NULL
)
3405 sp
= get_frame_register_signed (this_frame
,
3406 gdbarch_num_regs (gdbarch
)
3411 if (limit_pc
> start_pc
+ 200)
3412 limit_pc
= start_pc
+ 200;
3415 prev_non_prologue_insn
= 0;
3416 non_prologue_insns
= 0;
3417 prev_delay_slot
= 0;
3420 /* Permit at most one non-prologue non-control-transfer instruction
3421 in the middle which may have been reordered by the compiler for
3424 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3426 unsigned long inst
, high_word
;
3430 this_non_prologue_insn
= 0;
3433 /* Fetch the instruction. */
3434 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3437 /* Save some code by pre-extracting some useful fields. */
3438 high_word
= (inst
>> 16) & 0xffff;
3439 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3440 reg
= high_word
& 0x1f;
3442 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3443 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3444 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3446 if (offset
< 0) /* Negative stack adjustment? */
3447 frame_offset
-= offset
;
3449 /* Exit loop if a positive stack adjustment is found, which
3450 usually means that the stack cleanup code in the function
3451 epilogue is reached. */
3455 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3456 && !regsize_is_64_bits
)
3458 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3460 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3461 && regsize_is_64_bits
)
3463 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3464 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3466 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3468 /* Old gcc frame, r30 is virtual frame pointer. */
3469 if (offset
!= frame_offset
)
3470 frame_addr
= sp
+ offset
;
3471 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3473 unsigned alloca_adjust
;
3476 frame_addr
= get_frame_register_signed
3477 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3480 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3481 if (alloca_adjust
> 0)
3483 /* FP > SP + frame_size. This may be because of
3484 an alloca or somethings similar. Fix sp to
3485 "pre-alloca" value, and try again. */
3486 sp
+= alloca_adjust
;
3487 /* Need to reset the status of all registers. Otherwise,
3488 we will hit a guard that prevents the new address
3489 for each register to be recomputed during the second
3491 reset_saved_regs (gdbarch
, this_cache
);
3496 /* move $30,$sp. With different versions of gas this will be either
3497 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3498 Accept any one of these. */
3499 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3501 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3502 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3504 unsigned alloca_adjust
;
3507 frame_addr
= get_frame_register_signed
3508 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3510 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3511 if (alloca_adjust
> 0)
3513 /* FP > SP + frame_size. This may be because of
3514 an alloca or somethings similar. Fix sp to
3515 "pre-alloca" value, and try again. */
3517 /* Need to reset the status of all registers. Otherwise,
3518 we will hit a guard that prevents the new address
3519 for each register to be recomputed during the second
3521 reset_saved_regs (gdbarch
, this_cache
);
3526 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3527 && !regsize_is_64_bits
)
3529 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3531 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3532 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3533 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3534 || high_word
== 0x3c1c /* lui $gp,n */
3535 || high_word
== 0x279c /* addiu $gp,$gp,n */
3536 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3537 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3540 /* These instructions are part of the prologue, but we don't
3541 need to do anything special to handle them. */
3543 /* The instructions below load $at or $t0 with an immediate
3544 value in preparation for a stack adjustment via
3545 subu $sp,$sp,[$at,$t0]. These instructions could also
3546 initialize a local variable, so we accept them only before
3547 a stack adjustment instruction was seen. */
3548 else if (!seen_sp_adjust
3550 && (high_word
== 0x3c01 /* lui $at,n */
3551 || high_word
== 0x3c08 /* lui $t0,n */
3552 || high_word
== 0x3421 /* ori $at,$at,n */
3553 || high_word
== 0x3508 /* ori $t0,$t0,n */
3554 || high_word
== 0x3401 /* ori $at,$zero,n */
3555 || high_word
== 0x3408 /* ori $t0,$zero,n */
3558 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3560 /* Check for branches and jumps. The instruction in the delay
3561 slot can be a part of the prologue, so move forward once more. */
3562 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3566 /* This instruction is not an instruction typically found
3567 in a prologue, so we must have reached the end of the
3571 this_non_prologue_insn
= 1;
3574 non_prologue_insns
+= this_non_prologue_insn
;
3576 /* A jump or branch, or enough non-prologue insns seen? If so,
3577 then we must have reached the end of the prologue by now. */
3578 if (prev_delay_slot
|| non_prologue_insns
> 1)
3581 prev_non_prologue_insn
= this_non_prologue_insn
;
3582 prev_delay_slot
= in_delay_slot
;
3586 if (this_cache
!= NULL
)
3589 (get_frame_register_signed (this_frame
,
3590 gdbarch_num_regs (gdbarch
) + frame_reg
)
3592 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3593 this assignment below, eventually. But it's still needed
3595 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3596 + mips_regnum (gdbarch
)->pc
]
3597 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3601 /* Set end_prologue_addr to the address of the instruction immediately
3602 after the last one we scanned. Unless the last one looked like a
3603 non-prologue instruction (and we looked ahead), in which case use
3604 its address instead. */
3606 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3608 /* In a frameless function, we might have incorrectly
3609 skipped some load immediate instructions. Undo the skipping
3610 if the load immediate was not followed by a stack adjustment. */
3611 if (load_immediate_bytes
&& !seen_sp_adjust
)
3612 end_prologue_addr
-= load_immediate_bytes
;
3614 return end_prologue_addr
;
3617 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3618 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3619 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3620 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3622 static struct mips_frame_cache
*
3623 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3625 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3626 struct mips_frame_cache
*cache
;
3628 if ((*this_cache
) != NULL
)
3629 return (struct mips_frame_cache
*) (*this_cache
);
3631 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3632 (*this_cache
) = cache
;
3633 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3635 /* Analyze the function prologue. */
3637 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3638 CORE_ADDR start_addr
;
3640 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3641 if (start_addr
== 0)
3642 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3643 /* We can't analyze the prologue if we couldn't find the begining
3645 if (start_addr
== 0)
3648 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3649 (struct mips_frame_cache
*) *this_cache
);
3652 /* gdbarch_sp_regnum contains the value and not the address. */
3653 trad_frame_set_value (cache
->saved_regs
,
3654 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3657 return (struct mips_frame_cache
*) (*this_cache
);
3661 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3662 struct frame_id
*this_id
)
3664 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3666 /* This marks the outermost frame. */
3667 if (info
->base
== 0)
3669 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3672 static struct value
*
3673 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3674 void **this_cache
, int regnum
)
3676 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3678 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3682 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3683 struct frame_info
*this_frame
, void **this_cache
)
3685 CORE_ADDR pc
= get_frame_pc (this_frame
);
3686 if (mips_pc_is_mips (pc
))
3691 static const struct frame_unwind mips_insn32_frame_unwind
=
3694 default_frame_unwind_stop_reason
,
3695 mips_insn32_frame_this_id
,
3696 mips_insn32_frame_prev_register
,
3698 mips_insn32_frame_sniffer
3702 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3705 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3710 static const struct frame_base mips_insn32_frame_base
=
3712 &mips_insn32_frame_unwind
,
3713 mips_insn32_frame_base_address
,
3714 mips_insn32_frame_base_address
,
3715 mips_insn32_frame_base_address
3718 static const struct frame_base
*
3719 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3721 CORE_ADDR pc
= get_frame_pc (this_frame
);
3722 if (mips_pc_is_mips (pc
))
3723 return &mips_insn32_frame_base
;
3728 static struct trad_frame_cache
*
3729 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3732 CORE_ADDR start_addr
;
3733 CORE_ADDR stack_addr
;
3734 struct trad_frame_cache
*this_trad_cache
;
3735 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3736 int num_regs
= gdbarch_num_regs (gdbarch
);
3738 if ((*this_cache
) != NULL
)
3739 return (struct trad_frame_cache
*) (*this_cache
);
3740 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3741 (*this_cache
) = this_trad_cache
;
3743 /* The return address is in the link register. */
3744 trad_frame_set_reg_realreg (this_trad_cache
,
3745 gdbarch_pc_regnum (gdbarch
),
3746 num_regs
+ MIPS_RA_REGNUM
);
3748 /* Frame ID, since it's a frameless / stackless function, no stack
3749 space is allocated and SP on entry is the current SP. */
3750 pc
= get_frame_pc (this_frame
);
3751 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3752 stack_addr
= get_frame_register_signed (this_frame
,
3753 num_regs
+ MIPS_SP_REGNUM
);
3754 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3756 /* Assume that the frame's base is the same as the
3758 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3760 return this_trad_cache
;
3764 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3765 struct frame_id
*this_id
)
3767 struct trad_frame_cache
*this_trad_cache
3768 = mips_stub_frame_cache (this_frame
, this_cache
);
3769 trad_frame_get_id (this_trad_cache
, this_id
);
3772 static struct value
*
3773 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3774 void **this_cache
, int regnum
)
3776 struct trad_frame_cache
*this_trad_cache
3777 = mips_stub_frame_cache (this_frame
, this_cache
);
3778 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3782 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3783 struct frame_info
*this_frame
, void **this_cache
)
3786 struct obj_section
*s
;
3787 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3788 struct bound_minimal_symbol msym
;
3790 /* Use the stub unwinder for unreadable code. */
3791 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3794 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3797 /* Calling a PIC function from a non-PIC function passes through a
3798 stub. The stub for foo is named ".pic.foo". */
3799 msym
= lookup_minimal_symbol_by_pc (pc
);
3800 if (msym
.minsym
!= NULL
3801 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3802 && startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
3808 static const struct frame_unwind mips_stub_frame_unwind
=
3811 default_frame_unwind_stop_reason
,
3812 mips_stub_frame_this_id
,
3813 mips_stub_frame_prev_register
,
3815 mips_stub_frame_sniffer
3819 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3822 struct trad_frame_cache
*this_trad_cache
3823 = mips_stub_frame_cache (this_frame
, this_cache
);
3824 return trad_frame_get_this_base (this_trad_cache
);
3827 static const struct frame_base mips_stub_frame_base
=
3829 &mips_stub_frame_unwind
,
3830 mips_stub_frame_base_address
,
3831 mips_stub_frame_base_address
,
3832 mips_stub_frame_base_address
3835 static const struct frame_base
*
3836 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3838 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3839 return &mips_stub_frame_base
;
3844 /* mips_addr_bits_remove - remove useless address bits */
3847 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3849 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3851 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3852 /* This hack is a work-around for existing boards using PMON, the
3853 simulator, and any other 64-bit targets that doesn't have true
3854 64-bit addressing. On these targets, the upper 32 bits of
3855 addresses are ignored by the hardware. Thus, the PC or SP are
3856 likely to have been sign extended to all 1s by instruction
3857 sequences that load 32-bit addresses. For example, a typical
3858 piece of code that loads an address is this:
3860 lui $r2, <upper 16 bits>
3861 ori $r2, <lower 16 bits>
3863 But the lui sign-extends the value such that the upper 32 bits
3864 may be all 1s. The workaround is simply to mask off these
3865 bits. In the future, gcc may be changed to support true 64-bit
3866 addressing, and this masking will have to be disabled. */
3867 return addr
&= 0xffffffffUL
;
3873 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3874 instruction and ending with a SC/SCD instruction. If such a sequence
3875 is found, attempt to step through it. A breakpoint is placed at the end of
3878 /* Instructions used during single-stepping of atomic sequences, standard
3880 #define LL_OPCODE 0x30
3881 #define LLD_OPCODE 0x34
3882 #define SC_OPCODE 0x38
3883 #define SCD_OPCODE 0x3c
3885 static std::vector
<CORE_ADDR
>
3886 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3888 CORE_ADDR breaks
[2] = {-1, -1};
3890 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3894 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3895 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3897 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3898 /* Assume all atomic sequences start with a ll/lld instruction. */
3899 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3902 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3904 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3907 loc
+= MIPS_INSN32_SIZE
;
3908 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3910 /* Assume that there is at most one branch in the atomic
3911 sequence. If a branch is found, put a breakpoint in its
3912 destination address. */
3913 switch (itype_op (insn
))
3915 case 0: /* SPECIAL */
3916 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3917 return {}; /* fallback to the standard single-step code. */
3919 case 1: /* REGIMM */
3920 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3921 || ((itype_rt (insn
) & 0x1e) == 0
3922 && itype_rs (insn
) == 0)); /* BPOSGE* */
3926 return {}; /* fallback to the standard single-step code. */
3933 case 22: /* BLEZL */
3934 case 23: /* BGTTL */
3938 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3939 && (itype_rt (insn
) & 0x2) == 0);
3940 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3945 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3950 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3951 if (last_breakpoint
>= 1)
3952 return {}; /* More than one branch found, fallback to the
3953 standard single-step code. */
3954 breaks
[1] = branch_bp
;
3958 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3962 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3963 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3966 loc
+= MIPS_INSN32_SIZE
;
3968 /* Insert a breakpoint right after the end of the atomic sequence. */
3971 /* Check for duplicated breakpoints. Check also for a breakpoint
3972 placed (branch instruction's destination) in the atomic sequence. */
3973 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3974 last_breakpoint
= 0;
3976 std::vector
<CORE_ADDR
> next_pcs
;
3978 /* Effectively inserts the breakpoints. */
3979 for (index
= 0; index
<= last_breakpoint
; index
++)
3980 next_pcs
.push_back (breaks
[index
]);
3985 static std::vector
<CORE_ADDR
>
3986 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3989 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3990 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3991 CORE_ADDR breaks
[2] = {-1, -1};
3992 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4000 /* Assume all atomic sequences start with a ll/lld instruction. */
4001 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4002 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4004 loc
+= MIPS_INSN16_SIZE
;
4006 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4007 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4009 loc
+= MIPS_INSN16_SIZE
;
4011 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4012 that no atomic sequence is longer than "atomic_sequence_length"
4014 for (insn_count
= 0;
4015 !sc_found
&& insn_count
< atomic_sequence_length
;
4020 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4021 loc
+= MIPS_INSN16_SIZE
;
4023 /* Assume that there is at most one conditional branch in the
4024 atomic sequence. If a branch is found, put a breakpoint in
4025 its destination address. */
4026 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4028 /* 32-bit instructions. */
4029 case 2 * MIPS_INSN16_SIZE
:
4030 switch (micromips_op (insn
))
4032 case 0x10: /* POOL32I: bits 010000 */
4033 if ((b5s5_op (insn
) & 0x18) != 0x0
4034 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4035 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4036 && (b5s5_op (insn
) & 0x1d) != 0x11
4037 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4038 && ((b5s5_op (insn
) & 0x1e) != 0x14
4039 || (insn
& 0x3) != 0x0)
4040 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4041 && (b5s5_op (insn
) & 0x1e) != 0x1a
4042 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4043 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4044 || (insn
& 0x3) != 0x0)
4045 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4046 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4047 || (insn
& 0x3) != 0x1))
4048 /* BC1ANY*: bits 010000 111xx xxx01 */
4052 case 0x25: /* BEQ: bits 100101 */
4053 case 0x2d: /* BNE: bits 101101 */
4055 insn
|= mips_fetch_instruction (gdbarch
,
4056 ISA_MICROMIPS
, loc
, NULL
);
4057 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4058 + micromips_relative_offset16 (insn
));
4062 case 0x00: /* POOL32A: bits 000000 */
4064 insn
|= mips_fetch_instruction (gdbarch
,
4065 ISA_MICROMIPS
, loc
, NULL
);
4066 if (b0s6_op (insn
) != 0x3c
4067 /* POOL32Axf: bits 000000 ... 111100 */
4068 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4069 /* JALR, JALR.HB: 000000 000x111100 111100 */
4070 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4074 case 0x1d: /* JALS: bits 011101 */
4075 case 0x35: /* J: bits 110101 */
4076 case 0x3d: /* JAL: bits 111101 */
4077 case 0x3c: /* JALX: bits 111100 */
4078 return {}; /* Fall back to the standard single-step code. */
4080 case 0x18: /* POOL32C: bits 011000 */
4081 if ((b12s4_op (insn
) & 0xb) == 0xb)
4082 /* SC, SCD: bits 011000 1x11 */
4086 loc
+= MIPS_INSN16_SIZE
;
4089 /* 16-bit instructions. */
4090 case MIPS_INSN16_SIZE
:
4091 switch (micromips_op (insn
))
4093 case 0x23: /* BEQZ16: bits 100011 */
4094 case 0x2b: /* BNEZ16: bits 101011 */
4095 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4099 case 0x11: /* POOL16C: bits 010001 */
4100 if ((b5s5_op (insn
) & 0x1c) != 0xc
4101 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4102 && b5s5_op (insn
) != 0x18)
4103 /* JRADDIUSP: bits 010001 11000 */
4105 return {}; /* Fall back to the standard single-step code. */
4107 case 0x33: /* B16: bits 110011 */
4108 return {}; /* Fall back to the standard single-step code. */
4114 if (last_breakpoint
>= 1)
4115 return {}; /* More than one branch found, fallback to the
4116 standard single-step code. */
4117 breaks
[1] = branch_bp
;
4124 /* Insert a breakpoint right after the end of the atomic sequence. */
4127 /* Check for duplicated breakpoints. Check also for a breakpoint
4128 placed (branch instruction's destination) in the atomic sequence */
4129 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4130 last_breakpoint
= 0;
4132 std::vector
<CORE_ADDR
> next_pcs
;
4134 /* Effectively inserts the breakpoints. */
4135 for (index
= 0; index
<= last_breakpoint
; index
++)
4136 next_pcs
.push_back (breaks
[index
]);
4141 static std::vector
<CORE_ADDR
>
4142 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4144 if (mips_pc_is_mips (pc
))
4145 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4146 else if (mips_pc_is_micromips (gdbarch
, pc
))
4147 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4152 /* mips_software_single_step() is called just before we want to resume
4153 the inferior, if we want to single-step it but there is no hardware
4154 or kernel single-step support (MIPS on GNU/Linux for example). We find
4155 the target of the coming instruction and breakpoint it. */
4157 std::vector
<CORE_ADDR
>
4158 mips_software_single_step (struct regcache
*regcache
)
4160 struct gdbarch
*gdbarch
= regcache
->arch ();
4161 CORE_ADDR pc
, next_pc
;
4163 pc
= regcache_read_pc (regcache
);
4164 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4166 if (!next_pcs
.empty ())
4169 next_pc
= mips_next_pc (regcache
, pc
);
4174 /* Test whether the PC points to the return instruction at the
4175 end of a function. */
4178 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4183 /* This used to check for MIPS16, but this piece of code is never
4184 called for MIPS16 functions. And likewise microMIPS ones. */
4185 gdb_assert (mips_pc_is_mips (pc
));
4187 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4189 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4193 /* This fencepost looks highly suspicious to me. Removing it also
4194 seems suspicious as it could affect remote debugging across serial
4198 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4204 struct inferior
*inf
;
4206 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4208 fence
= start_pc
- heuristic_fence_post
;
4212 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4213 fence
= VM_MIN_ADDRESS
;
4215 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4217 inf
= current_inferior ();
4219 /* Search back for previous return. */
4220 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4221 if (start_pc
< fence
)
4223 /* It's not clear to me why we reach this point when
4224 stop_soon, but with this test, at least we
4225 don't print out warnings for every child forked (eg, on
4226 decstation). 22apr93 rich@cygnus.com. */
4227 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4229 static int blurb_printed
= 0;
4231 warning (_("GDB can't find the start of the function at %s."),
4232 paddress (gdbarch
, pc
));
4236 /* This actually happens frequently in embedded
4237 development, when you first connect to a board
4238 and your stack pointer and pc are nowhere in
4239 particular. This message needs to give people
4240 in that situation enough information to
4241 determine that it's no big deal. */
4242 printf_filtered ("\n\
4243 GDB is unable to find the start of the function at %s\n\
4244 and thus can't determine the size of that function's stack frame.\n\
4245 This means that GDB may be unable to access that stack frame, or\n\
4246 the frames below it.\n\
4247 This problem is most likely caused by an invalid program counter or\n\
4249 However, if you think GDB should simply search farther back\n\
4250 from %s for code which looks like the beginning of a\n\
4251 function, you can increase the range of the search using the `set\n\
4252 heuristic-fence-post' command.\n",
4253 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4260 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4262 unsigned short inst
;
4264 /* On MIPS16, any one of the following is likely to be the
4265 start of a function:
4271 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4272 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4273 if ((inst
& 0xff80) == 0x6480) /* save */
4275 if (start_pc
- instlen
>= fence
)
4277 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4278 start_pc
- instlen
, NULL
);
4279 if ((inst
& 0xf800) == 0xf000) /* extend */
4280 start_pc
-= instlen
;
4284 else if (((inst
& 0xf81f) == 0xe809
4285 && (inst
& 0x700) != 0x700) /* entry */
4286 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4287 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4288 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4290 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4291 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4296 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4304 /* On microMIPS, any one of the following is likely to be the
4305 start of a function:
4309 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4310 switch (micromips_op (insn
))
4312 case 0xc: /* ADDIU: bits 001100 */
4313 case 0x17: /* DADDIU: bits 010111 */
4314 sreg
= b0s5_reg (insn
);
4315 dreg
= b5s5_reg (insn
);
4317 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4318 pc
+ MIPS_INSN16_SIZE
, NULL
);
4319 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4320 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4321 /* (D)ADDIU $sp, imm */
4326 case 0x10: /* POOL32I: bits 010000 */
4327 if (b5s5_op (insn
) == 0xd
4328 /* LUI: bits 010000 001101 */
4329 && b0s5_reg (insn
>> 16) == 28)
4334 case 0x13: /* POOL16D: bits 010011 */
4335 if ((insn
& 0x1) == 0x1)
4336 /* ADDIUSP: bits 010011 1 */
4338 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4344 /* ADDIUS5: bits 010011 0 */
4346 dreg
= b5s5_reg (insn
);
4347 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4348 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4349 /* ADDIUS5 $sp, -imm */
4357 else if (mips_about_to_return (gdbarch
, start_pc
))
4359 /* Skip return and its delay slot. */
4360 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4367 struct mips_objfile_private
4373 /* According to the current ABI, should the type be passed in a
4374 floating-point register (assuming that there is space)? When there
4375 is no FPU, FP are not even considered as possible candidates for
4376 FP registers and, consequently this returns false - forces FP
4377 arguments into integer registers. */
4380 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4381 struct type
*arg_type
)
4383 return ((typecode
== TYPE_CODE_FLT
4384 || (MIPS_EABI (gdbarch
)
4385 && (typecode
== TYPE_CODE_STRUCT
4386 || typecode
== TYPE_CODE_UNION
)
4387 && TYPE_NFIELDS (arg_type
) == 1
4388 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4390 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4393 /* On o32, argument passing in GPRs depends on the alignment of the type being
4394 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4397 mips_type_needs_double_align (struct type
*type
)
4399 enum type_code typecode
= TYPE_CODE (type
);
4401 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4403 else if (typecode
== TYPE_CODE_STRUCT
)
4405 if (TYPE_NFIELDS (type
) < 1)
4407 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4409 else if (typecode
== TYPE_CODE_UNION
)
4413 n
= TYPE_NFIELDS (type
);
4414 for (i
= 0; i
< n
; i
++)
4415 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4422 /* Adjust the address downward (direction of stack growth) so that it
4423 is correctly aligned for a new stack frame. */
4425 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4427 return align_down (addr
, 16);
4430 /* Implement the "push_dummy_code" gdbarch method. */
4433 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4434 CORE_ADDR funaddr
, struct value
**args
,
4435 int nargs
, struct type
*value_type
,
4436 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4437 struct regcache
*regcache
)
4439 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4443 /* Reserve enough room on the stack for our breakpoint instruction. */
4444 bp_slot
= sp
- sizeof (nop_insn
);
4446 /* Return to microMIPS mode if calling microMIPS code to avoid
4447 triggering an address error exception on processors that only
4448 support microMIPS execution. */
4449 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4450 ? make_compact_addr (bp_slot
) : bp_slot
);
4452 /* The breakpoint layer automatically adjusts the address of
4453 breakpoints inserted in a branch delay slot. With enough
4454 bad luck, the 4 bytes located just before our breakpoint
4455 instruction could look like a branch instruction, and thus
4456 trigger the adjustement, and break the function call entirely.
4457 So, we reserve those 4 bytes and write a nop instruction
4458 to prevent that from happening. */
4459 nop_addr
= bp_slot
- sizeof (nop_insn
);
4460 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4461 sp
= mips_frame_align (gdbarch
, nop_addr
);
4463 /* Inferior resumes at the function entry point. */
4470 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4471 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4472 int nargs
, struct value
**args
, CORE_ADDR sp
,
4473 int struct_return
, CORE_ADDR struct_addr
)
4479 int stack_offset
= 0;
4480 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4481 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4482 int abi_regsize
= mips_abi_regsize (gdbarch
);
4484 /* For shared libraries, "t9" needs to point at the function
4486 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4488 /* Set the return address register to point to the entry point of
4489 the program, where a breakpoint lies in wait. */
4490 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4492 /* First ensure that the stack and structure return address (if any)
4493 are properly aligned. The stack has to be at least 64-bit
4494 aligned even on 32-bit machines, because doubles must be 64-bit
4495 aligned. For n32 and n64, stack frames need to be 128-bit
4496 aligned, so we round to this widest known alignment. */
4498 sp
= align_down (sp
, 16);
4499 struct_addr
= align_down (struct_addr
, 16);
4501 /* Now make space on the stack for the args. We allocate more
4502 than necessary for EABI, because the first few arguments are
4503 passed in registers, but that's OK. */
4504 for (argnum
= 0; argnum
< nargs
; argnum
++)
4505 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4506 sp
-= align_up (len
, 16);
4509 fprintf_unfiltered (gdb_stdlog
,
4510 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4511 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4513 /* Initialize the integer and float register pointers. */
4514 argreg
= MIPS_A0_REGNUM
;
4515 float_argreg
= mips_fpa0_regnum (gdbarch
);
4517 /* The struct_return pointer occupies the first parameter-passing reg. */
4521 fprintf_unfiltered (gdb_stdlog
,
4522 "mips_eabi_push_dummy_call: "
4523 "struct_return reg=%d %s\n",
4524 argreg
, paddress (gdbarch
, struct_addr
));
4525 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4528 /* Now load as many as possible of the first arguments into
4529 registers, and push the rest onto the stack. Loop thru args
4530 from first to last. */
4531 for (argnum
= 0; argnum
< nargs
; argnum
++)
4533 const gdb_byte
*val
;
4534 /* This holds the address of structures that are passed by
4536 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4537 struct value
*arg
= args
[argnum
];
4538 struct type
*arg_type
= check_typedef (value_type (arg
));
4539 int len
= TYPE_LENGTH (arg_type
);
4540 enum type_code typecode
= TYPE_CODE (arg_type
);
4543 fprintf_unfiltered (gdb_stdlog
,
4544 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4545 argnum
+ 1, len
, (int) typecode
);
4547 /* The EABI passes structures that do not fit in a register by
4549 if (len
> abi_regsize
4550 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4552 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4553 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4554 value_address (arg
));
4555 typecode
= TYPE_CODE_PTR
;
4559 fprintf_unfiltered (gdb_stdlog
, " push");
4562 val
= value_contents (arg
);
4564 /* 32-bit ABIs always start floating point arguments in an
4565 even-numbered floating point register. Round the FP register
4566 up before the check to see if there are any FP registers
4567 left. Non MIPS_EABI targets also pass the FP in the integer
4568 registers so also round up normal registers. */
4569 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4571 if ((float_argreg
& 1))
4575 /* Floating point arguments passed in registers have to be
4576 treated specially. On 32-bit architectures, doubles
4577 are passed in register pairs; the even register gets
4578 the low word, and the odd register gets the high word.
4579 On non-EABI processors, the first two floating point arguments are
4580 also copied to general registers, because MIPS16 functions
4581 don't use float registers for arguments. This duplication of
4582 arguments in general registers can't hurt non-MIPS16 functions
4583 because those registers are normally skipped. */
4584 /* MIPS_EABI squeezes a struct that contains a single floating
4585 point value into an FP register instead of pushing it onto the
4587 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4588 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4590 /* EABI32 will pass doubles in consecutive registers, even on
4591 64-bit cores. At one time, we used to check the size of
4592 `float_argreg' to determine whether or not to pass doubles
4593 in consecutive registers, but this is not sufficient for
4594 making the ABI determination. */
4595 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4597 int low_offset
= gdbarch_byte_order (gdbarch
)
4598 == BFD_ENDIAN_BIG
? 4 : 0;
4601 /* Write the low word of the double to the even register(s). */
4602 regval
= extract_signed_integer (val
+ low_offset
,
4605 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4606 float_argreg
, phex (regval
, 4));
4607 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4609 /* Write the high word of the double to the odd register(s). */
4610 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4613 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4614 float_argreg
, phex (regval
, 4));
4615 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4619 /* This is a floating point value that fits entirely
4620 in a single register. */
4621 /* On 32 bit ABI's the float_argreg is further adjusted
4622 above to ensure that it is even register aligned. */
4623 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4625 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4626 float_argreg
, phex (regval
, len
));
4627 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4632 /* Copy the argument to general registers or the stack in
4633 register-sized pieces. Large arguments are split between
4634 registers and stack. */
4635 /* Note: structs whose size is not a multiple of abi_regsize
4636 are treated specially: Irix cc passes
4637 them in registers where gcc sometimes puts them on the
4638 stack. For maximum compatibility, we will put them in
4640 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4642 /* Note: Floating-point values that didn't fit into an FP
4643 register are only written to memory. */
4646 /* Remember if the argument was written to the stack. */
4647 int stack_used_p
= 0;
4648 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4651 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4654 /* Write this portion of the argument to the stack. */
4655 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4657 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4659 /* Should shorter than int integer values be
4660 promoted to int before being stored? */
4661 int longword_offset
= 0;
4664 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4666 if (abi_regsize
== 8
4667 && (typecode
== TYPE_CODE_INT
4668 || typecode
== TYPE_CODE_PTR
4669 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4670 longword_offset
= abi_regsize
- len
;
4671 else if ((typecode
== TYPE_CODE_STRUCT
4672 || typecode
== TYPE_CODE_UNION
)
4673 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4674 longword_offset
= abi_regsize
- len
;
4679 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4680 paddress (gdbarch
, stack_offset
));
4681 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4682 paddress (gdbarch
, longword_offset
));
4685 addr
= sp
+ stack_offset
+ longword_offset
;
4690 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4691 paddress (gdbarch
, addr
));
4692 for (i
= 0; i
< partial_len
; i
++)
4694 fprintf_unfiltered (gdb_stdlog
, "%02x",
4698 write_memory (addr
, val
, partial_len
);
4701 /* Note!!! This is NOT an else clause. Odd sized
4702 structs may go thru BOTH paths. Floating point
4703 arguments will not. */
4704 /* Write this portion of the argument to a general
4705 purpose register. */
4706 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4707 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4710 extract_signed_integer (val
, partial_len
, byte_order
);
4713 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4715 phex (regval
, abi_regsize
));
4716 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4723 /* Compute the offset into the stack at which we will
4724 copy the next parameter.
4726 In the new EABI (and the NABI32), the stack_offset
4727 only needs to be adjusted when it has been used. */
4730 stack_offset
+= align_up (partial_len
, abi_regsize
);
4734 fprintf_unfiltered (gdb_stdlog
, "\n");
4737 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4739 /* Return adjusted stack pointer. */
4743 /* Determine the return value convention being used. */
4745 static enum return_value_convention
4746 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4747 struct type
*type
, struct regcache
*regcache
,
4748 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4750 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4751 int fp_return_type
= 0;
4752 int offset
, regnum
, xfer
;
4754 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4755 return RETURN_VALUE_STRUCT_CONVENTION
;
4757 /* Floating point type? */
4758 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4760 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4762 /* Structs with a single field of float type
4763 are returned in a floating point register. */
4764 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4765 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4766 && TYPE_NFIELDS (type
) == 1)
4768 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4770 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4777 /* A floating-point value belongs in the least significant part
4780 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4781 regnum
= mips_regnum (gdbarch
)->fp0
;
4785 /* An integer value goes in V0/V1. */
4787 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4788 regnum
= MIPS_V0_REGNUM
;
4791 offset
< TYPE_LENGTH (type
);
4792 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4794 xfer
= mips_abi_regsize (gdbarch
);
4795 if (offset
+ xfer
> TYPE_LENGTH (type
))
4796 xfer
= TYPE_LENGTH (type
) - offset
;
4797 mips_xfer_register (gdbarch
, regcache
,
4798 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4799 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4803 return RETURN_VALUE_REGISTER_CONVENTION
;
4807 /* N32/N64 ABI stuff. */
4809 /* Search for a naturally aligned double at OFFSET inside a struct
4810 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4814 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4819 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4822 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4825 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4828 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4831 struct type
*field_type
;
4833 /* We're only looking at normal fields. */
4834 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4835 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4838 /* If we have gone past the offset, there is no double to pass. */
4839 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4843 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4845 /* If this field is entirely before the requested offset, go
4846 on to the next one. */
4847 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4850 /* If this is our special aligned double, we can stop. */
4851 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4852 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4855 /* This field starts at or before the requested offset, and
4856 overlaps it. If it is a structure, recurse inwards. */
4857 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4864 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4865 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4866 int nargs
, struct value
**args
, CORE_ADDR sp
,
4867 int struct_return
, CORE_ADDR struct_addr
)
4873 int stack_offset
= 0;
4874 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4875 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4877 /* For shared libraries, "t9" needs to point at the function
4879 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4881 /* Set the return address register to point to the entry point of
4882 the program, where a breakpoint lies in wait. */
4883 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4885 /* First ensure that the stack and structure return address (if any)
4886 are properly aligned. The stack has to be at least 64-bit
4887 aligned even on 32-bit machines, because doubles must be 64-bit
4888 aligned. For n32 and n64, stack frames need to be 128-bit
4889 aligned, so we round to this widest known alignment. */
4891 sp
= align_down (sp
, 16);
4892 struct_addr
= align_down (struct_addr
, 16);
4894 /* Now make space on the stack for the args. */
4895 for (argnum
= 0; argnum
< nargs
; argnum
++)
4896 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4897 sp
-= align_up (len
, 16);
4900 fprintf_unfiltered (gdb_stdlog
,
4901 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4902 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4904 /* Initialize the integer and float register pointers. */
4905 argreg
= MIPS_A0_REGNUM
;
4906 float_argreg
= mips_fpa0_regnum (gdbarch
);
4908 /* The struct_return pointer occupies the first parameter-passing reg. */
4912 fprintf_unfiltered (gdb_stdlog
,
4913 "mips_n32n64_push_dummy_call: "
4914 "struct_return reg=%d %s\n",
4915 argreg
, paddress (gdbarch
, struct_addr
));
4916 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4919 /* Now load as many as possible of the first arguments into
4920 registers, and push the rest onto the stack. Loop thru args
4921 from first to last. */
4922 for (argnum
= 0; argnum
< nargs
; argnum
++)
4924 const gdb_byte
*val
;
4925 struct value
*arg
= args
[argnum
];
4926 struct type
*arg_type
= check_typedef (value_type (arg
));
4927 int len
= TYPE_LENGTH (arg_type
);
4928 enum type_code typecode
= TYPE_CODE (arg_type
);
4931 fprintf_unfiltered (gdb_stdlog
,
4932 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4933 argnum
+ 1, len
, (int) typecode
);
4935 val
= value_contents (arg
);
4937 /* A 128-bit long double value requires an even-odd pair of
4938 floating-point registers. */
4940 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4941 && (float_argreg
& 1))
4947 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4948 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4950 /* This is a floating point value that fits entirely
4951 in a single register or a pair of registers. */
4952 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4953 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4955 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4956 float_argreg
, phex (regval
, reglen
));
4957 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4960 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4961 argreg
, phex (regval
, reglen
));
4962 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4967 regval
= extract_unsigned_integer (val
+ reglen
,
4968 reglen
, byte_order
);
4970 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4971 float_argreg
, phex (regval
, reglen
));
4972 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4975 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4976 argreg
, phex (regval
, reglen
));
4977 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4984 /* Copy the argument to general registers or the stack in
4985 register-sized pieces. Large arguments are split between
4986 registers and stack. */
4987 /* For N32/N64, structs, unions, or other composite types are
4988 treated as a sequence of doublewords, and are passed in integer
4989 or floating point registers as though they were simple scalar
4990 parameters to the extent that they fit, with any excess on the
4991 stack packed according to the normal memory layout of the
4993 The caller does not reserve space for the register arguments;
4994 the callee is responsible for reserving it if required. */
4995 /* Note: Floating-point values that didn't fit into an FP
4996 register are only written to memory. */
4999 /* Remember if the argument was written to the stack. */
5000 int stack_used_p
= 0;
5001 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5004 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5007 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5008 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5010 /* Write this portion of the argument to the stack. */
5011 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5013 /* Should shorter than int integer values be
5014 promoted to int before being stored? */
5015 int longword_offset
= 0;
5018 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5020 if ((typecode
== TYPE_CODE_INT
5021 || typecode
== TYPE_CODE_PTR
)
5023 longword_offset
= MIPS64_REGSIZE
- len
;
5028 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5029 paddress (gdbarch
, stack_offset
));
5030 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5031 paddress (gdbarch
, longword_offset
));
5034 addr
= sp
+ stack_offset
+ longword_offset
;
5039 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5040 paddress (gdbarch
, addr
));
5041 for (i
= 0; i
< partial_len
; i
++)
5043 fprintf_unfiltered (gdb_stdlog
, "%02x",
5047 write_memory (addr
, val
, partial_len
);
5050 /* Note!!! This is NOT an else clause. Odd sized
5051 structs may go thru BOTH paths. */
5052 /* Write this portion of the argument to a general
5053 purpose register. */
5054 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5058 /* Sign extend pointers, 32-bit integers and signed
5059 16-bit and 8-bit integers; everything else is taken
5062 if ((partial_len
== 4
5063 && (typecode
== TYPE_CODE_PTR
5064 || typecode
== TYPE_CODE_INT
))
5066 && typecode
== TYPE_CODE_INT
5067 && !TYPE_UNSIGNED (arg_type
)))
5068 regval
= extract_signed_integer (val
, partial_len
,
5071 regval
= extract_unsigned_integer (val
, partial_len
,
5074 /* A non-floating-point argument being passed in a
5075 general register. If a struct or union, and if
5076 the remaining length is smaller than the register
5077 size, we have to adjust the register value on
5080 It does not seem to be necessary to do the
5081 same for integral types. */
5083 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5084 && partial_len
< MIPS64_REGSIZE
5085 && (typecode
== TYPE_CODE_STRUCT
5086 || typecode
== TYPE_CODE_UNION
))
5087 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5091 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5093 phex (regval
, MIPS64_REGSIZE
));
5094 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5096 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5097 TYPE_LENGTH (arg_type
) - len
))
5100 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5102 phex (regval
, MIPS64_REGSIZE
));
5103 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5114 /* Compute the offset into the stack at which we will
5115 copy the next parameter.
5117 In N32 (N64?), the stack_offset only needs to be
5118 adjusted when it has been used. */
5121 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5125 fprintf_unfiltered (gdb_stdlog
, "\n");
5128 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5130 /* Return adjusted stack pointer. */
5134 static enum return_value_convention
5135 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5136 struct type
*type
, struct regcache
*regcache
,
5137 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5141 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5143 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5144 if needed), as appropriate for the type. Composite results (struct,
5145 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5148 * A struct with only one or two floating point fields is returned in $f0
5149 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5152 * Any other composite results of at most 128 bits are returned in
5153 $2 (first 64 bits) and $3 (remainder, if necessary).
5155 * Larger composite results are handled by converting the function to a
5156 procedure with an implicit first parameter, which is a pointer to an area
5157 reserved by the caller to receive the result. [The o32-bit ABI requires
5158 that all composite results be handled by conversion to implicit first
5159 parameters. The MIPS/SGI Fortran implementation has always made a
5160 specific exception to return COMPLEX results in the floating point
5163 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5164 return RETURN_VALUE_STRUCT_CONVENTION
;
5165 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5166 && TYPE_LENGTH (type
) == 16
5167 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5169 /* A 128-bit floating-point value fills both $f0 and $f2. The
5170 two registers are used in the same as memory order, so the
5171 eight bytes with the lower memory address are in $f0. */
5173 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5174 mips_xfer_register (gdbarch
, regcache
,
5175 (gdbarch_num_regs (gdbarch
)
5176 + mips_regnum (gdbarch
)->fp0
),
5177 8, gdbarch_byte_order (gdbarch
),
5178 readbuf
, writebuf
, 0);
5179 mips_xfer_register (gdbarch
, regcache
,
5180 (gdbarch_num_regs (gdbarch
)
5181 + mips_regnum (gdbarch
)->fp0
+ 2),
5182 8, gdbarch_byte_order (gdbarch
),
5183 readbuf
? readbuf
+ 8 : readbuf
,
5184 writebuf
? writebuf
+ 8 : writebuf
, 0);
5185 return RETURN_VALUE_REGISTER_CONVENTION
;
5187 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5188 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5190 /* A single or double floating-point value that fits in FP0. */
5192 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5193 mips_xfer_register (gdbarch
, regcache
,
5194 (gdbarch_num_regs (gdbarch
)
5195 + mips_regnum (gdbarch
)->fp0
),
5197 gdbarch_byte_order (gdbarch
),
5198 readbuf
, writebuf
, 0);
5199 return RETURN_VALUE_REGISTER_CONVENTION
;
5201 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5202 && TYPE_NFIELDS (type
) <= 2
5203 && TYPE_NFIELDS (type
) >= 1
5204 && ((TYPE_NFIELDS (type
) == 1
5205 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5207 || (TYPE_NFIELDS (type
) == 2
5208 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5210 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5211 == TYPE_CODE_FLT
))))
5213 /* A struct that contains one or two floats. Each value is part
5214 in the least significant part of their floating point
5215 register (or GPR, for soft float). */
5218 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5219 ? mips_regnum (gdbarch
)->fp0
5221 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5223 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5226 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5228 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5230 /* A 16-byte long double field goes in two consecutive
5232 mips_xfer_register (gdbarch
, regcache
,
5233 gdbarch_num_regs (gdbarch
) + regnum
,
5235 gdbarch_byte_order (gdbarch
),
5236 readbuf
, writebuf
, offset
);
5237 mips_xfer_register (gdbarch
, regcache
,
5238 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5240 gdbarch_byte_order (gdbarch
),
5241 readbuf
, writebuf
, offset
+ 8);
5244 mips_xfer_register (gdbarch
, regcache
,
5245 gdbarch_num_regs (gdbarch
) + regnum
,
5246 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5247 gdbarch_byte_order (gdbarch
),
5248 readbuf
, writebuf
, offset
);
5250 return RETURN_VALUE_REGISTER_CONVENTION
;
5252 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5253 || TYPE_CODE (type
) == TYPE_CODE_UNION
5254 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5256 /* A composite type. Extract the left justified value,
5257 regardless of the byte order. I.e. DO NOT USE
5261 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5262 offset
< TYPE_LENGTH (type
);
5263 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5265 int xfer
= register_size (gdbarch
, regnum
);
5266 if (offset
+ xfer
> TYPE_LENGTH (type
))
5267 xfer
= TYPE_LENGTH (type
) - offset
;
5269 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5270 offset
, xfer
, regnum
);
5271 mips_xfer_register (gdbarch
, regcache
,
5272 gdbarch_num_regs (gdbarch
) + regnum
,
5273 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5276 return RETURN_VALUE_REGISTER_CONVENTION
;
5280 /* A scalar extract each part but least-significant-byte
5284 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5285 offset
< TYPE_LENGTH (type
);
5286 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5288 int xfer
= register_size (gdbarch
, regnum
);
5289 if (offset
+ xfer
> TYPE_LENGTH (type
))
5290 xfer
= TYPE_LENGTH (type
) - offset
;
5292 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5293 offset
, xfer
, regnum
);
5294 mips_xfer_register (gdbarch
, regcache
,
5295 gdbarch_num_regs (gdbarch
) + regnum
,
5296 xfer
, gdbarch_byte_order (gdbarch
),
5297 readbuf
, writebuf
, offset
);
5299 return RETURN_VALUE_REGISTER_CONVENTION
;
5303 /* Which registers to use for passing floating-point values between
5304 function calls, one of floating-point, general and both kinds of
5305 registers. O32 and O64 use different register kinds for standard
5306 MIPS and MIPS16 code; to make the handling of cases where we may
5307 not know what kind of code is being used (e.g. no debug information)
5308 easier we sometimes use both kinds. */
5317 /* O32 ABI stuff. */
5320 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5321 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5322 int nargs
, struct value
**args
, CORE_ADDR sp
,
5323 int struct_return
, CORE_ADDR struct_addr
)
5329 int stack_offset
= 0;
5330 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5331 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5333 /* For shared libraries, "t9" needs to point at the function
5335 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5337 /* Set the return address register to point to the entry point of
5338 the program, where a breakpoint lies in wait. */
5339 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5341 /* First ensure that the stack and structure return address (if any)
5342 are properly aligned. The stack has to be at least 64-bit
5343 aligned even on 32-bit machines, because doubles must be 64-bit
5344 aligned. For n32 and n64, stack frames need to be 128-bit
5345 aligned, so we round to this widest known alignment. */
5347 sp
= align_down (sp
, 16);
5348 struct_addr
= align_down (struct_addr
, 16);
5350 /* Now make space on the stack for the args. */
5351 for (argnum
= 0; argnum
< nargs
; argnum
++)
5353 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5355 /* Align to double-word if necessary. */
5356 if (mips_type_needs_double_align (arg_type
))
5357 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5358 /* Allocate space on the stack. */
5359 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5361 sp
-= align_up (len
, 16);
5364 fprintf_unfiltered (gdb_stdlog
,
5365 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5366 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5368 /* Initialize the integer and float register pointers. */
5369 argreg
= MIPS_A0_REGNUM
;
5370 float_argreg
= mips_fpa0_regnum (gdbarch
);
5372 /* The struct_return pointer occupies the first parameter-passing reg. */
5376 fprintf_unfiltered (gdb_stdlog
,
5377 "mips_o32_push_dummy_call: "
5378 "struct_return reg=%d %s\n",
5379 argreg
, paddress (gdbarch
, struct_addr
));
5380 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5381 stack_offset
+= MIPS32_REGSIZE
;
5384 /* Now load as many as possible of the first arguments into
5385 registers, and push the rest onto the stack. Loop thru args
5386 from first to last. */
5387 for (argnum
= 0; argnum
< nargs
; argnum
++)
5389 const gdb_byte
*val
;
5390 struct value
*arg
= args
[argnum
];
5391 struct type
*arg_type
= check_typedef (value_type (arg
));
5392 int len
= TYPE_LENGTH (arg_type
);
5393 enum type_code typecode
= TYPE_CODE (arg_type
);
5396 fprintf_unfiltered (gdb_stdlog
,
5397 "mips_o32_push_dummy_call: %d len=%d type=%d",
5398 argnum
+ 1, len
, (int) typecode
);
5400 val
= value_contents (arg
);
5402 /* 32-bit ABIs always start floating point arguments in an
5403 even-numbered floating point register. Round the FP register
5404 up before the check to see if there are any FP registers
5405 left. O32 targets also pass the FP in the integer registers
5406 so also round up normal registers. */
5407 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5409 if ((float_argreg
& 1))
5413 /* Floating point arguments passed in registers have to be
5414 treated specially. On 32-bit architectures, doubles are
5415 passed in register pairs; the even FP register gets the
5416 low word, and the odd FP register gets the high word.
5417 On O32, the first two floating point arguments are also
5418 copied to general registers, following their memory order,
5419 because MIPS16 functions don't use float registers for
5420 arguments. This duplication of arguments in general
5421 registers can't hurt non-MIPS16 functions, because those
5422 registers are normally skipped. */
5424 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5425 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5427 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5429 int freg_offset
= gdbarch_byte_order (gdbarch
)
5430 == BFD_ENDIAN_BIG
? 1 : 0;
5431 unsigned long regval
;
5434 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5436 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5437 float_argreg
+ freg_offset
,
5439 regcache_cooked_write_unsigned (regcache
,
5440 float_argreg
++ + freg_offset
,
5443 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5444 argreg
, phex (regval
, 4));
5445 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5448 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5450 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5451 float_argreg
- freg_offset
,
5453 regcache_cooked_write_unsigned (regcache
,
5454 float_argreg
++ - freg_offset
,
5457 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5458 argreg
, phex (regval
, 4));
5459 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5463 /* This is a floating point value that fits entirely
5464 in a single register. */
5465 /* On 32 bit ABI's the float_argreg is further adjusted
5466 above to ensure that it is even register aligned. */
5467 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5469 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5470 float_argreg
, phex (regval
, len
));
5471 regcache_cooked_write_unsigned (regcache
,
5472 float_argreg
++, regval
);
5473 /* Although two FP registers are reserved for each
5474 argument, only one corresponding integer register is
5477 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5478 argreg
, phex (regval
, len
));
5479 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5481 /* Reserve space for the FP register. */
5482 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5486 /* Copy the argument to general registers or the stack in
5487 register-sized pieces. Large arguments are split between
5488 registers and stack. */
5489 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5490 are treated specially: Irix cc passes
5491 them in registers where gcc sometimes puts them on the
5492 stack. For maximum compatibility, we will put them in
5494 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5495 && len
% MIPS32_REGSIZE
!= 0);
5496 /* Structures should be aligned to eight bytes (even arg registers)
5497 on MIPS_ABI_O32, if their first member has double precision. */
5498 if (mips_type_needs_double_align (arg_type
))
5503 stack_offset
+= MIPS32_REGSIZE
;
5508 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5511 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5514 /* Write this portion of the argument to the stack. */
5515 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5516 || odd_sized_struct
)
5518 /* Should shorter than int integer values be
5519 promoted to int before being stored? */
5520 int longword_offset
= 0;
5525 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5526 paddress (gdbarch
, stack_offset
));
5527 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5528 paddress (gdbarch
, longword_offset
));
5531 addr
= sp
+ stack_offset
+ longword_offset
;
5536 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5537 paddress (gdbarch
, addr
));
5538 for (i
= 0; i
< partial_len
; i
++)
5540 fprintf_unfiltered (gdb_stdlog
, "%02x",
5544 write_memory (addr
, val
, partial_len
);
5547 /* Note!!! This is NOT an else clause. Odd sized
5548 structs may go thru BOTH paths. */
5549 /* Write this portion of the argument to a general
5550 purpose register. */
5551 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5553 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5555 /* Value may need to be sign extended, because
5556 mips_isa_regsize() != mips_abi_regsize(). */
5558 /* A non-floating-point argument being passed in a
5559 general register. If a struct or union, and if
5560 the remaining length is smaller than the register
5561 size, we have to adjust the register value on
5564 It does not seem to be necessary to do the
5565 same for integral types.
5567 Also don't do this adjustment on O64 binaries.
5569 cagney/2001-07-23: gdb/179: Also, GCC, when
5570 outputting LE O32 with sizeof (struct) <
5571 mips_abi_regsize(), generates a left shift
5572 as part of storing the argument in a register
5573 (the left shift isn't generated when
5574 sizeof (struct) >= mips_abi_regsize()). Since
5575 it is quite possible that this is GCC
5576 contradicting the LE/O32 ABI, GDB has not been
5577 adjusted to accommodate this. Either someone
5578 needs to demonstrate that the LE/O32 ABI
5579 specifies such a left shift OR this new ABI gets
5580 identified as such and GDB gets tweaked
5583 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5584 && partial_len
< MIPS32_REGSIZE
5585 && (typecode
== TYPE_CODE_STRUCT
5586 || typecode
== TYPE_CODE_UNION
))
5587 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5591 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5593 phex (regval
, MIPS32_REGSIZE
));
5594 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5597 /* Prevent subsequent floating point arguments from
5598 being passed in floating point registers. */
5599 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5605 /* Compute the offset into the stack at which we will
5606 copy the next parameter.
5608 In older ABIs, the caller reserved space for
5609 registers that contained arguments. This was loosely
5610 refered to as their "home". Consequently, space is
5611 always allocated. */
5613 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5617 fprintf_unfiltered (gdb_stdlog
, "\n");
5620 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5622 /* Return adjusted stack pointer. */
5626 static enum return_value_convention
5627 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5628 struct type
*type
, struct regcache
*regcache
,
5629 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5631 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5632 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5633 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5634 enum mips_fval_reg fval_reg
;
5636 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5637 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5638 || TYPE_CODE (type
) == TYPE_CODE_UNION
5639 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5640 return RETURN_VALUE_STRUCT_CONVENTION
;
5641 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5642 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5644 /* A single-precision floating-point value. If reading in or copying,
5645 then we get it from/put it to FP0 for standard MIPS code or GPR2
5646 for MIPS16 code. If writing out only, then we put it to both FP0
5647 and GPR2. We do not support reading in with no function known, if
5648 this safety check ever triggers, then we'll have to try harder. */
5649 gdb_assert (function
|| !readbuf
);
5654 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5657 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5659 case mips_fval_both
:
5660 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5663 if (fval_reg
!= mips_fval_gpr
)
5664 mips_xfer_register (gdbarch
, regcache
,
5665 (gdbarch_num_regs (gdbarch
)
5666 + mips_regnum (gdbarch
)->fp0
),
5668 gdbarch_byte_order (gdbarch
),
5669 readbuf
, writebuf
, 0);
5670 if (fval_reg
!= mips_fval_fpr
)
5671 mips_xfer_register (gdbarch
, regcache
,
5672 gdbarch_num_regs (gdbarch
) + 2,
5674 gdbarch_byte_order (gdbarch
),
5675 readbuf
, writebuf
, 0);
5676 return RETURN_VALUE_REGISTER_CONVENTION
;
5678 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5679 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5681 /* A double-precision floating-point value. If reading in or copying,
5682 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5683 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5684 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5685 no function known, if this safety check ever triggers, then we'll
5686 have to try harder. */
5687 gdb_assert (function
|| !readbuf
);
5692 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5695 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5697 case mips_fval_both
:
5698 fprintf_unfiltered (gdb_stderr
,
5699 "Return float in $fp1/$fp0 and $2/$3\n");
5702 if (fval_reg
!= mips_fval_gpr
)
5704 /* The most significant part goes in FP1, and the least significant
5706 switch (gdbarch_byte_order (gdbarch
))
5708 case BFD_ENDIAN_LITTLE
:
5709 mips_xfer_register (gdbarch
, regcache
,
5710 (gdbarch_num_regs (gdbarch
)
5711 + mips_regnum (gdbarch
)->fp0
+ 0),
5712 4, gdbarch_byte_order (gdbarch
),
5713 readbuf
, writebuf
, 0);
5714 mips_xfer_register (gdbarch
, regcache
,
5715 (gdbarch_num_regs (gdbarch
)
5716 + mips_regnum (gdbarch
)->fp0
+ 1),
5717 4, gdbarch_byte_order (gdbarch
),
5718 readbuf
, writebuf
, 4);
5720 case BFD_ENDIAN_BIG
:
5721 mips_xfer_register (gdbarch
, regcache
,
5722 (gdbarch_num_regs (gdbarch
)
5723 + mips_regnum (gdbarch
)->fp0
+ 1),
5724 4, gdbarch_byte_order (gdbarch
),
5725 readbuf
, writebuf
, 0);
5726 mips_xfer_register (gdbarch
, regcache
,
5727 (gdbarch_num_regs (gdbarch
)
5728 + mips_regnum (gdbarch
)->fp0
+ 0),
5729 4, gdbarch_byte_order (gdbarch
),
5730 readbuf
, writebuf
, 4);
5733 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5736 if (fval_reg
!= mips_fval_fpr
)
5738 /* The two 32-bit parts are always placed in GPR2 and GPR3
5739 following these registers' memory order. */
5740 mips_xfer_register (gdbarch
, regcache
,
5741 gdbarch_num_regs (gdbarch
) + 2,
5742 4, gdbarch_byte_order (gdbarch
),
5743 readbuf
, writebuf
, 0);
5744 mips_xfer_register (gdbarch
, regcache
,
5745 gdbarch_num_regs (gdbarch
) + 3,
5746 4, gdbarch_byte_order (gdbarch
),
5747 readbuf
, writebuf
, 4);
5749 return RETURN_VALUE_REGISTER_CONVENTION
;
5752 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5753 && TYPE_NFIELDS (type
) <= 2
5754 && TYPE_NFIELDS (type
) >= 1
5755 && ((TYPE_NFIELDS (type
) == 1
5756 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5758 || (TYPE_NFIELDS (type
) == 2
5759 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5761 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5763 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5765 /* A struct that contains one or two floats. Each value is part
5766 in the least significant part of their floating point
5770 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5771 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5773 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5776 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5778 mips_xfer_register (gdbarch
, regcache
,
5779 gdbarch_num_regs (gdbarch
) + regnum
,
5780 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5781 gdbarch_byte_order (gdbarch
),
5782 readbuf
, writebuf
, offset
);
5784 return RETURN_VALUE_REGISTER_CONVENTION
;
5788 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5789 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5791 /* A structure or union. Extract the left justified value,
5792 regardless of the byte order. I.e. DO NOT USE
5796 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5797 offset
< TYPE_LENGTH (type
);
5798 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5800 int xfer
= register_size (gdbarch
, regnum
);
5801 if (offset
+ xfer
> TYPE_LENGTH (type
))
5802 xfer
= TYPE_LENGTH (type
) - offset
;
5804 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5805 offset
, xfer
, regnum
);
5806 mips_xfer_register (gdbarch
, regcache
,
5807 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5808 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5810 return RETURN_VALUE_REGISTER_CONVENTION
;
5815 /* A scalar extract each part but least-significant-byte
5816 justified. o32 thinks registers are 4 byte, regardless of
5820 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5821 offset
< TYPE_LENGTH (type
);
5822 offset
+= MIPS32_REGSIZE
, regnum
++)
5824 int xfer
= MIPS32_REGSIZE
;
5825 if (offset
+ xfer
> TYPE_LENGTH (type
))
5826 xfer
= TYPE_LENGTH (type
) - offset
;
5828 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5829 offset
, xfer
, regnum
);
5830 mips_xfer_register (gdbarch
, regcache
,
5831 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5832 gdbarch_byte_order (gdbarch
),
5833 readbuf
, writebuf
, offset
);
5835 return RETURN_VALUE_REGISTER_CONVENTION
;
5839 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5843 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5844 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5846 struct value
**args
, CORE_ADDR sp
,
5847 int struct_return
, CORE_ADDR struct_addr
)
5853 int stack_offset
= 0;
5854 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5855 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5857 /* For shared libraries, "t9" needs to point at the function
5859 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5861 /* Set the return address register to point to the entry point of
5862 the program, where a breakpoint lies in wait. */
5863 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5865 /* First ensure that the stack and structure return address (if any)
5866 are properly aligned. The stack has to be at least 64-bit
5867 aligned even on 32-bit machines, because doubles must be 64-bit
5868 aligned. For n32 and n64, stack frames need to be 128-bit
5869 aligned, so we round to this widest known alignment. */
5871 sp
= align_down (sp
, 16);
5872 struct_addr
= align_down (struct_addr
, 16);
5874 /* Now make space on the stack for the args. */
5875 for (argnum
= 0; argnum
< nargs
; argnum
++)
5877 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5879 /* Allocate space on the stack. */
5880 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5882 sp
-= align_up (len
, 16);
5885 fprintf_unfiltered (gdb_stdlog
,
5886 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5887 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5889 /* Initialize the integer and float register pointers. */
5890 argreg
= MIPS_A0_REGNUM
;
5891 float_argreg
= mips_fpa0_regnum (gdbarch
);
5893 /* The struct_return pointer occupies the first parameter-passing reg. */
5897 fprintf_unfiltered (gdb_stdlog
,
5898 "mips_o64_push_dummy_call: "
5899 "struct_return reg=%d %s\n",
5900 argreg
, paddress (gdbarch
, struct_addr
));
5901 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5902 stack_offset
+= MIPS64_REGSIZE
;
5905 /* Now load as many as possible of the first arguments into
5906 registers, and push the rest onto the stack. Loop thru args
5907 from first to last. */
5908 for (argnum
= 0; argnum
< nargs
; argnum
++)
5910 const gdb_byte
*val
;
5911 struct value
*arg
= args
[argnum
];
5912 struct type
*arg_type
= check_typedef (value_type (arg
));
5913 int len
= TYPE_LENGTH (arg_type
);
5914 enum type_code typecode
= TYPE_CODE (arg_type
);
5917 fprintf_unfiltered (gdb_stdlog
,
5918 "mips_o64_push_dummy_call: %d len=%d type=%d",
5919 argnum
+ 1, len
, (int) typecode
);
5921 val
= value_contents (arg
);
5923 /* Floating point arguments passed in registers have to be
5924 treated specially. On 32-bit architectures, doubles are
5925 passed in register pairs; the even FP register gets the
5926 low word, and the odd FP register gets the high word.
5927 On O64, the first two floating point arguments are also
5928 copied to general registers, because MIPS16 functions
5929 don't use float registers for arguments. This duplication
5930 of arguments in general registers can't hurt non-MIPS16
5931 functions because those registers are normally skipped. */
5933 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5934 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5936 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5938 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5939 float_argreg
, phex (regval
, len
));
5940 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5942 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5943 argreg
, phex (regval
, len
));
5944 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5946 /* Reserve space for the FP register. */
5947 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5951 /* Copy the argument to general registers or the stack in
5952 register-sized pieces. Large arguments are split between
5953 registers and stack. */
5954 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5955 are treated specially: Irix cc passes them in registers
5956 where gcc sometimes puts them on the stack. For maximum
5957 compatibility, we will put them in both places. */
5958 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5959 && len
% MIPS64_REGSIZE
!= 0);
5962 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5965 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5968 /* Write this portion of the argument to the stack. */
5969 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5970 || odd_sized_struct
)
5972 /* Should shorter than int integer values be
5973 promoted to int before being stored? */
5974 int longword_offset
= 0;
5976 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5978 if ((typecode
== TYPE_CODE_INT
5979 || typecode
== TYPE_CODE_PTR
5980 || typecode
== TYPE_CODE_FLT
)
5982 longword_offset
= MIPS64_REGSIZE
- len
;
5987 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5988 paddress (gdbarch
, stack_offset
));
5989 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5990 paddress (gdbarch
, longword_offset
));
5993 addr
= sp
+ stack_offset
+ longword_offset
;
5998 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5999 paddress (gdbarch
, addr
));
6000 for (i
= 0; i
< partial_len
; i
++)
6002 fprintf_unfiltered (gdb_stdlog
, "%02x",
6006 write_memory (addr
, val
, partial_len
);
6009 /* Note!!! This is NOT an else clause. Odd sized
6010 structs may go thru BOTH paths. */
6011 /* Write this portion of the argument to a general
6012 purpose register. */
6013 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6015 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6017 /* Value may need to be sign extended, because
6018 mips_isa_regsize() != mips_abi_regsize(). */
6020 /* A non-floating-point argument being passed in a
6021 general register. If a struct or union, and if
6022 the remaining length is smaller than the register
6023 size, we have to adjust the register value on
6026 It does not seem to be necessary to do the
6027 same for integral types. */
6029 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6030 && partial_len
< MIPS64_REGSIZE
6031 && (typecode
== TYPE_CODE_STRUCT
6032 || typecode
== TYPE_CODE_UNION
))
6033 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6037 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6039 phex (regval
, MIPS64_REGSIZE
));
6040 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6043 /* Prevent subsequent floating point arguments from
6044 being passed in floating point registers. */
6045 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6051 /* Compute the offset into the stack at which we will
6052 copy the next parameter.
6054 In older ABIs, the caller reserved space for
6055 registers that contained arguments. This was loosely
6056 refered to as their "home". Consequently, space is
6057 always allocated. */
6059 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6063 fprintf_unfiltered (gdb_stdlog
, "\n");
6066 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6068 /* Return adjusted stack pointer. */
6072 static enum return_value_convention
6073 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6074 struct type
*type
, struct regcache
*regcache
,
6075 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6077 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6078 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6079 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6080 enum mips_fval_reg fval_reg
;
6082 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6083 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6084 || TYPE_CODE (type
) == TYPE_CODE_UNION
6085 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6086 return RETURN_VALUE_STRUCT_CONVENTION
;
6087 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6089 /* A floating-point value. If reading in or copying, then we get it
6090 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6091 If writing out only, then we put it to both FP0 and GPR2. We do
6092 not support reading in with no function known, if this safety
6093 check ever triggers, then we'll have to try harder. */
6094 gdb_assert (function
|| !readbuf
);
6099 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6102 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6104 case mips_fval_both
:
6105 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6108 if (fval_reg
!= mips_fval_gpr
)
6109 mips_xfer_register (gdbarch
, regcache
,
6110 (gdbarch_num_regs (gdbarch
)
6111 + mips_regnum (gdbarch
)->fp0
),
6113 gdbarch_byte_order (gdbarch
),
6114 readbuf
, writebuf
, 0);
6115 if (fval_reg
!= mips_fval_fpr
)
6116 mips_xfer_register (gdbarch
, regcache
,
6117 gdbarch_num_regs (gdbarch
) + 2,
6119 gdbarch_byte_order (gdbarch
),
6120 readbuf
, writebuf
, 0);
6121 return RETURN_VALUE_REGISTER_CONVENTION
;
6125 /* A scalar extract each part but least-significant-byte
6129 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6130 offset
< TYPE_LENGTH (type
);
6131 offset
+= MIPS64_REGSIZE
, regnum
++)
6133 int xfer
= MIPS64_REGSIZE
;
6134 if (offset
+ xfer
> TYPE_LENGTH (type
))
6135 xfer
= TYPE_LENGTH (type
) - offset
;
6137 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6138 offset
, xfer
, regnum
);
6139 mips_xfer_register (gdbarch
, regcache
,
6140 gdbarch_num_regs (gdbarch
) + regnum
,
6141 xfer
, gdbarch_byte_order (gdbarch
),
6142 readbuf
, writebuf
, offset
);
6144 return RETURN_VALUE_REGISTER_CONVENTION
;
6148 /* Floating point register management.
6150 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6151 64bit operations, these early MIPS cpus treat fp register pairs
6152 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6153 registers and offer a compatibility mode that emulates the MIPS2 fp
6154 model. When operating in MIPS2 fp compat mode, later cpu's split
6155 double precision floats into two 32-bit chunks and store them in
6156 consecutive fp regs. To display 64-bit floats stored in this
6157 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6158 Throw in user-configurable endianness and you have a real mess.
6160 The way this works is:
6161 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6162 double-precision value will be split across two logical registers.
6163 The lower-numbered logical register will hold the low-order bits,
6164 regardless of the processor's endianness.
6165 - If we are on a 64-bit processor, and we are looking for a
6166 single-precision value, it will be in the low ordered bits
6167 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6168 save slot in memory.
6169 - If we are in 64-bit mode, everything is straightforward.
6171 Note that this code only deals with "live" registers at the top of the
6172 stack. We will attempt to deal with saved registers later, when
6173 the raw/cooked register interface is in place. (We need a general
6174 interface that can deal with dynamic saved register sizes -- fp
6175 regs could be 32 bits wide in one frame and 64 on the frame above
6178 /* Copy a 32-bit single-precision value from the current frame
6179 into rare_buffer. */
6182 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6183 gdb_byte
*rare_buffer
)
6185 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6186 int raw_size
= register_size (gdbarch
, regno
);
6187 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6189 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6190 error (_("can't read register %d (%s)"),
6191 regno
, gdbarch_register_name (gdbarch
, regno
));
6194 /* We have a 64-bit value for this register. Find the low-order
6198 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6203 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6207 memcpy (rare_buffer
, raw_buffer
, 4);
6211 /* Copy a 64-bit double-precision value from the current frame into
6212 rare_buffer. This may include getting half of it from the next
6216 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6217 gdb_byte
*rare_buffer
)
6219 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6220 int raw_size
= register_size (gdbarch
, regno
);
6222 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6224 /* We have a 64-bit value for this register, and we should use
6226 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6227 error (_("can't read register %d (%s)"),
6228 regno
, gdbarch_register_name (gdbarch
, regno
));
6232 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6234 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6235 internal_error (__FILE__
, __LINE__
,
6236 _("mips_read_fp_register_double: bad access to "
6237 "odd-numbered FP register"));
6239 /* mips_read_fp_register_single will find the correct 32 bits from
6241 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6243 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6244 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6248 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6249 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6255 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6257 { /* Do values for FP (float) regs. */
6258 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6259 gdb_byte
*raw_buffer
;
6260 std::string flt_str
, dbl_str
;
6262 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6263 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6267 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6269 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6270 fprintf_filtered (file
, "%*s",
6271 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6274 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6276 struct value_print_options opts
;
6278 /* 4-byte registers: Print hex and floating. Also print even
6279 numbered registers as doubles. */
6280 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6281 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6283 get_formatted_print_options (&opts
, 'x');
6284 print_scalar_formatted (raw_buffer
,
6285 builtin_type (gdbarch
)->builtin_uint32
,
6288 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6290 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6292 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6293 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6295 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6300 struct value_print_options opts
;
6302 /* Eight byte registers: print each one as hex, float and double. */
6303 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6304 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6306 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6307 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6309 get_formatted_print_options (&opts
, 'x');
6310 print_scalar_formatted (raw_buffer
,
6311 builtin_type (gdbarch
)->builtin_uint64
,
6314 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6315 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6320 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6323 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6324 struct value_print_options opts
;
6327 if (mips_float_register_p (gdbarch
, regnum
))
6329 mips_print_fp_register (file
, frame
, regnum
);
6333 val
= get_frame_register_value (frame
, regnum
);
6335 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6337 /* The problem with printing numeric register names (r26, etc.) is that
6338 the user can't use them on input. Probably the best solution is to
6339 fix it so that either the numeric or the funky (a2, etc.) names
6340 are accepted on input. */
6341 if (regnum
< MIPS_NUMREGS
)
6342 fprintf_filtered (file
, "(r%d): ", regnum
);
6344 fprintf_filtered (file
, ": ");
6346 get_formatted_print_options (&opts
, 'x');
6347 val_print_scalar_formatted (value_type (val
),
6348 value_embedded_offset (val
),
6353 /* Print IEEE exception condition bits in FLAGS. */
6356 print_fpu_flags (struct ui_file
*file
, int flags
)
6358 if (flags
& (1 << 0))
6359 fputs_filtered (" inexact", file
);
6360 if (flags
& (1 << 1))
6361 fputs_filtered (" uflow", file
);
6362 if (flags
& (1 << 2))
6363 fputs_filtered (" oflow", file
);
6364 if (flags
& (1 << 3))
6365 fputs_filtered (" div0", file
);
6366 if (flags
& (1 << 4))
6367 fputs_filtered (" inval", file
);
6368 if (flags
& (1 << 5))
6369 fputs_filtered (" unimp", file
);
6370 fputc_filtered ('\n', file
);
6373 /* Print interesting information about the floating point processor
6374 (if present) or emulator. */
6377 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6378 struct frame_info
*frame
, const char *args
)
6380 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6381 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6385 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6386 type
= MIPS_FPU_NONE
;
6388 fprintf_filtered (file
, "fpu type: %s\n",
6389 type
== MIPS_FPU_DOUBLE
? "double-precision"
6390 : type
== MIPS_FPU_SINGLE
? "single-precision"
6393 if (type
== MIPS_FPU_NONE
)
6396 fprintf_filtered (file
, "reg size: %d bits\n",
6397 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6399 fputs_filtered ("cond :", file
);
6400 if (fcs
& (1 << 23))
6401 fputs_filtered (" 0", file
);
6402 for (i
= 1; i
<= 7; i
++)
6403 if (fcs
& (1 << (24 + i
)))
6404 fprintf_filtered (file
, " %d", i
);
6405 fputc_filtered ('\n', file
);
6407 fputs_filtered ("cause :", file
);
6408 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6409 fputs ("mask :", stdout
);
6410 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6411 fputs ("flags :", stdout
);
6412 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6414 fputs_filtered ("rounding: ", file
);
6417 case 0: fputs_filtered ("nearest\n", file
); break;
6418 case 1: fputs_filtered ("zero\n", file
); break;
6419 case 2: fputs_filtered ("+inf\n", file
); break;
6420 case 3: fputs_filtered ("-inf\n", file
); break;
6423 fputs_filtered ("flush :", file
);
6424 if (fcs
& (1 << 21))
6425 fputs_filtered (" nearest", file
);
6426 if (fcs
& (1 << 22))
6427 fputs_filtered (" override", file
);
6428 if (fcs
& (1 << 24))
6429 fputs_filtered (" zero", file
);
6430 if ((fcs
& (0xb << 21)) == 0)
6431 fputs_filtered (" no", file
);
6432 fputc_filtered ('\n', file
);
6434 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6435 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6436 fputc_filtered ('\n', file
);
6438 default_print_float_info (gdbarch
, file
, frame
, args
);
6441 /* Replacement for generic do_registers_info.
6442 Print regs in pretty columns. */
6445 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6448 fprintf_filtered (file
, " ");
6449 mips_print_fp_register (file
, frame
, regnum
);
6450 fprintf_filtered (file
, "\n");
6455 /* Print a row's worth of GP (int) registers, with name labels above. */
6458 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6461 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6462 /* Do values for GP (int) regs. */
6463 const gdb_byte
*raw_buffer
;
6464 struct value
*value
;
6465 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6470 /* For GP registers, we print a separate row of names above the vals. */
6471 for (col
= 0, regnum
= start_regnum
;
6472 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6473 + gdbarch_num_pseudo_regs (gdbarch
);
6476 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6477 continue; /* unused register */
6478 if (mips_float_register_p (gdbarch
, regnum
))
6479 break; /* End the row: reached FP register. */
6480 /* Large registers are handled separately. */
6481 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6484 break; /* End the row before this register. */
6486 /* Print this register on a row by itself. */
6487 mips_print_register (file
, frame
, regnum
);
6488 fprintf_filtered (file
, "\n");
6492 fprintf_filtered (file
, " ");
6493 fprintf_filtered (file
,
6494 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6495 gdbarch_register_name (gdbarch
, regnum
));
6502 /* Print the R0 to R31 names. */
6503 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6504 fprintf_filtered (file
, "\n R%-4d",
6505 start_regnum
% gdbarch_num_regs (gdbarch
));
6507 fprintf_filtered (file
, "\n ");
6509 /* Now print the values in hex, 4 or 8 to the row. */
6510 for (col
= 0, regnum
= start_regnum
;
6511 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6512 + gdbarch_num_pseudo_regs (gdbarch
);
6515 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6516 continue; /* unused register */
6517 if (mips_float_register_p (gdbarch
, regnum
))
6518 break; /* End row: reached FP register. */
6519 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6520 break; /* End row: large register. */
6522 /* OK: get the data in raw format. */
6523 value
= get_frame_register_value (frame
, regnum
);
6524 if (value_optimized_out (value
)
6525 || !value_entirely_available (value
))
6527 fprintf_filtered (file
, "%*s ",
6528 (int) mips_abi_regsize (gdbarch
) * 2,
6529 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6530 : "<unavailable>"));
6534 raw_buffer
= value_contents_all (value
);
6535 /* pad small registers */
6537 byte
< (mips_abi_regsize (gdbarch
)
6538 - register_size (gdbarch
, regnum
)); byte
++)
6539 fprintf_filtered (file
, " ");
6540 /* Now print the register value in hex, endian order. */
6541 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6543 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6544 byte
< register_size (gdbarch
, regnum
); byte
++)
6545 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6547 for (byte
= register_size (gdbarch
, regnum
) - 1;
6549 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6550 fprintf_filtered (file
, " ");
6553 if (col
> 0) /* ie. if we actually printed anything... */
6554 fprintf_filtered (file
, "\n");
6559 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6562 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6563 struct frame_info
*frame
, int regnum
, int all
)
6565 if (regnum
!= -1) /* Do one specified register. */
6567 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6568 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6569 error (_("Not a valid register for the current processor type"));
6571 mips_print_register (file
, frame
, regnum
);
6572 fprintf_filtered (file
, "\n");
6575 /* Do all (or most) registers. */
6577 regnum
= gdbarch_num_regs (gdbarch
);
6578 while (regnum
< gdbarch_num_regs (gdbarch
)
6579 + gdbarch_num_pseudo_regs (gdbarch
))
6581 if (mips_float_register_p (gdbarch
, regnum
))
6583 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6584 regnum
= print_fp_register_row (file
, frame
, regnum
);
6586 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6589 regnum
= print_gp_register_row (file
, frame
, regnum
);
6595 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6596 struct frame_info
*frame
)
6598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6599 CORE_ADDR pc
= get_frame_pc (frame
);
6605 if ((mips_pc_is_mips (pc
)
6606 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6607 || (mips_pc_is_micromips (gdbarch
, pc
)
6608 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6609 || (mips_pc_is_mips16 (gdbarch
, pc
)
6610 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6613 isa
= mips_pc_isa (gdbarch
, pc
);
6614 /* _has_delay_slot above will have validated the read. */
6615 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6616 size
= mips_insn_size (isa
, insn
);
6618 const address_space
*aspace
= get_frame_address_space (frame
);
6620 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6623 /* To skip prologues, I use this predicate. Returns either PC itself
6624 if the code at PC does not look like a function prologue; otherwise
6625 returns an address that (if we're lucky) follows the prologue. If
6626 LENIENT, then we must skip everything which is involved in setting
6627 up the frame (it's OK to skip more, just so long as we don't skip
6628 anything which might clobber the registers which are being saved.
6629 We must skip more in the case where part of the prologue is in the
6630 delay slot of a non-prologue instruction). */
6633 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6636 CORE_ADDR func_addr
;
6638 /* See if we can determine the end of the prologue via the symbol table.
6639 If so, then return either PC, or the PC after the prologue, whichever
6641 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6643 CORE_ADDR post_prologue_pc
6644 = skip_prologue_using_sal (gdbarch
, func_addr
);
6645 if (post_prologue_pc
!= 0)
6646 return std::max (pc
, post_prologue_pc
);
6649 /* Can't determine prologue from the symbol table, need to examine
6652 /* Find an upper limit on the function prologue using the debug
6653 information. If the debug information could not be used to provide
6654 that bound, then use an arbitrary large number as the upper bound. */
6655 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6657 limit_pc
= pc
+ 100; /* Magic. */
6659 if (mips_pc_is_mips16 (gdbarch
, pc
))
6660 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6661 else if (mips_pc_is_micromips (gdbarch
, pc
))
6662 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6664 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6667 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6668 This is a helper function for mips_stack_frame_destroyed_p. */
6671 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6673 CORE_ADDR func_addr
= 0, func_end
= 0;
6675 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6677 /* The MIPS epilogue is max. 12 bytes long. */
6678 CORE_ADDR addr
= func_end
- 12;
6680 if (addr
< func_addr
+ 4)
6681 addr
= func_addr
+ 4;
6685 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6687 unsigned long high_word
;
6690 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6691 high_word
= (inst
>> 16) & 0xffff;
6693 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6694 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6695 && inst
!= 0x03e00008 /* jr $ra */
6696 && inst
!= 0x00000000) /* nop */
6706 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6707 This is a helper function for mips_stack_frame_destroyed_p. */
6710 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6712 CORE_ADDR func_addr
= 0;
6713 CORE_ADDR func_end
= 0;
6721 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6724 /* The microMIPS epilogue is max. 12 bytes long. */
6725 addr
= func_end
- 12;
6727 if (addr
< func_addr
+ 2)
6728 addr
= func_addr
+ 2;
6732 for (; pc
< func_end
; pc
+= loc
)
6735 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6736 loc
+= MIPS_INSN16_SIZE
;
6737 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6739 /* 32-bit instructions. */
6740 case 2 * MIPS_INSN16_SIZE
:
6742 insn
|= mips_fetch_instruction (gdbarch
,
6743 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6744 loc
+= MIPS_INSN16_SIZE
;
6745 switch (micromips_op (insn
>> 16))
6747 case 0xc: /* ADDIU: bits 001100 */
6748 case 0x17: /* DADDIU: bits 010111 */
6749 sreg
= b0s5_reg (insn
>> 16);
6750 dreg
= b5s5_reg (insn
>> 16);
6751 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6752 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6753 /* (D)ADDIU $sp, imm */
6763 /* 16-bit instructions. */
6764 case MIPS_INSN16_SIZE
:
6765 switch (micromips_op (insn
))
6767 case 0x3: /* MOVE: bits 000011 */
6768 sreg
= b0s5_reg (insn
);
6769 dreg
= b5s5_reg (insn
);
6770 if (sreg
== 0 && dreg
== 0)
6771 /* MOVE $zero, $zero aka NOP */
6775 case 0x11: /* POOL16C: bits 010001 */
6776 if (b5s5_op (insn
) == 0x18
6777 /* JRADDIUSP: bits 010011 11000 */
6778 || (b5s5_op (insn
) == 0xd
6779 /* JRC: bits 010011 01101 */
6780 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6785 case 0x13: /* POOL16D: bits 010011 */
6786 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6787 if ((insn
& 0x1) == 0x1
6788 /* ADDIUSP: bits 010011 1 */
6802 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6803 This is a helper function for mips_stack_frame_destroyed_p. */
6806 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6808 CORE_ADDR func_addr
= 0, func_end
= 0;
6810 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6812 /* The MIPS epilogue is max. 12 bytes long. */
6813 CORE_ADDR addr
= func_end
- 12;
6815 if (addr
< func_addr
+ 4)
6816 addr
= func_addr
+ 4;
6820 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6822 unsigned short inst
;
6824 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6826 if ((inst
& 0xf800) == 0xf000) /* extend */
6829 if (inst
!= 0x6300 /* addiu $sp,offset */
6830 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6831 && inst
!= 0xe820 /* jr $ra */
6832 && inst
!= 0xe8a0 /* jrc $ra */
6833 && inst
!= 0x6500) /* nop */
6843 /* Implement the stack_frame_destroyed_p gdbarch method.
6845 The epilogue is defined here as the area at the end of a function,
6846 after an instruction which destroys the function's stack frame. */
6849 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6851 if (mips_pc_is_mips16 (gdbarch
, pc
))
6852 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6853 else if (mips_pc_is_micromips (gdbarch
, pc
))
6854 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6856 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6859 /* Root of all "set mips "/"show mips " commands. This will eventually be
6860 used for all MIPS-specific commands. */
6863 show_mips_command (const char *args
, int from_tty
)
6865 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6869 set_mips_command (const char *args
, int from_tty
)
6872 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6873 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6876 /* Commands to show/set the MIPS FPU type. */
6879 show_mipsfpu_command (const char *args
, int from_tty
)
6883 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6886 ("The MIPS floating-point coprocessor is unknown "
6887 "because the current architecture is not MIPS.\n");
6891 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6893 case MIPS_FPU_SINGLE
:
6894 fpu
= "single-precision";
6896 case MIPS_FPU_DOUBLE
:
6897 fpu
= "double-precision";
6900 fpu
= "absent (none)";
6903 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6905 if (mips_fpu_type_auto
)
6906 printf_unfiltered ("The MIPS floating-point coprocessor "
6907 "is set automatically (currently %s)\n",
6911 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6916 set_mipsfpu_command (const char *args
, int from_tty
)
6918 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6919 "\"single\",\"none\" or \"auto\".\n");
6920 show_mipsfpu_command (args
, from_tty
);
6924 set_mipsfpu_single_command (const char *args
, int from_tty
)
6926 struct gdbarch_info info
;
6927 gdbarch_info_init (&info
);
6928 mips_fpu_type
= MIPS_FPU_SINGLE
;
6929 mips_fpu_type_auto
= 0;
6930 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6931 instead of relying on globals. Doing that would let generic code
6932 handle the search for this specific architecture. */
6933 if (!gdbarch_update_p (info
))
6934 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6938 set_mipsfpu_double_command (const char *args
, int from_tty
)
6940 struct gdbarch_info info
;
6941 gdbarch_info_init (&info
);
6942 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6943 mips_fpu_type_auto
= 0;
6944 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6945 instead of relying on globals. Doing that would let generic code
6946 handle the search for this specific architecture. */
6947 if (!gdbarch_update_p (info
))
6948 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6952 set_mipsfpu_none_command (const char *args
, int from_tty
)
6954 struct gdbarch_info info
;
6955 gdbarch_info_init (&info
);
6956 mips_fpu_type
= MIPS_FPU_NONE
;
6957 mips_fpu_type_auto
= 0;
6958 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6959 instead of relying on globals. Doing that would let generic code
6960 handle the search for this specific architecture. */
6961 if (!gdbarch_update_p (info
))
6962 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6966 set_mipsfpu_auto_command (const char *args
, int from_tty
)
6968 mips_fpu_type_auto
= 1;
6971 /* Just like reinit_frame_cache, but with the right arguments to be
6972 callable as an sfunc. */
6975 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6976 struct cmd_list_element
*c
)
6978 reinit_frame_cache ();
6982 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6984 gdb_disassembler
*di
6985 = static_cast<gdb_disassembler
*>(info
->application_data
);
6986 struct gdbarch
*gdbarch
= di
->arch ();
6988 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6989 disassembler needs to be able to locally determine the ISA, and
6990 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6992 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6993 info
->mach
= bfd_mach_mips16
;
6994 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6995 info
->mach
= bfd_mach_mips_micromips
;
6997 /* Round down the instruction address to the appropriate boundary. */
6998 memaddr
&= (info
->mach
== bfd_mach_mips16
6999 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7001 /* Set the disassembler options. */
7002 if (!info
->disassembler_options
)
7003 /* This string is not recognized explicitly by the disassembler,
7004 but it tells the disassembler to not try to guess the ABI from
7005 the bfd elf headers, such that, if the user overrides the ABI
7006 of a program linked as NewABI, the disassembly will follow the
7007 register naming conventions specified by the user. */
7008 info
->disassembler_options
= "gpr-names=32";
7010 return default_print_insn (memaddr
, info
);
7014 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
7016 /* Set up the disassembler info, so that we get the right
7017 register names from libopcodes. */
7018 info
->disassembler_options
= "gpr-names=n32";
7019 info
->flavour
= bfd_target_elf_flavour
;
7021 return gdb_print_insn_mips (memaddr
, info
);
7025 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
7027 /* Set up the disassembler info, so that we get the right
7028 register names from libopcodes. */
7029 info
->disassembler_options
= "gpr-names=64";
7030 info
->flavour
= bfd_target_elf_flavour
;
7032 return gdb_print_insn_mips (memaddr
, info
);
7035 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7038 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7040 CORE_ADDR pc
= *pcptr
;
7042 if (mips_pc_is_mips16 (gdbarch
, pc
))
7044 *pcptr
= unmake_compact_addr (pc
);
7045 return MIPS_BP_KIND_MIPS16
;
7047 else if (mips_pc_is_micromips (gdbarch
, pc
))
7052 *pcptr
= unmake_compact_addr (pc
);
7053 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7054 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7055 return MIPS_BP_KIND_MICROMIPS16
;
7057 return MIPS_BP_KIND_MICROMIPS32
;
7060 return MIPS_BP_KIND_MIPS32
;
7063 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7065 static const gdb_byte
*
7066 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7068 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7072 case MIPS_BP_KIND_MIPS16
:
7074 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7075 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7078 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7079 return mips16_big_breakpoint
;
7081 return mips16_little_breakpoint
;
7083 case MIPS_BP_KIND_MICROMIPS16
:
7085 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7086 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7090 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7091 return micromips16_big_breakpoint
;
7093 return micromips16_little_breakpoint
;
7095 case MIPS_BP_KIND_MICROMIPS32
:
7097 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7098 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7101 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7102 return micromips32_big_breakpoint
;
7104 return micromips32_little_breakpoint
;
7106 case MIPS_BP_KIND_MIPS32
:
7108 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7109 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7112 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7113 return big_breakpoint
;
7115 return little_breakpoint
;
7118 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7122 /* Return non-zero if the standard MIPS instruction INST has a branch
7123 delay slot (i.e. it is a jump or branch instruction). This function
7124 is based on mips32_next_pc. */
7127 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7133 op
= itype_op (inst
);
7134 if ((inst
& 0xe0000000) != 0)
7136 rs
= itype_rs (inst
);
7137 rt
= itype_rt (inst
);
7138 return (is_octeon_bbit_op (op
, gdbarch
)
7139 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7140 || op
== 29 /* JALX: bits 011101 */
7143 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7144 || (rs
== 9 && (rt
& 0x2) == 0)
7145 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7146 || (rs
== 10 && (rt
& 0x2) == 0))));
7147 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7150 switch (op
& 0x07) /* extract bits 28,27,26 */
7152 case 0: /* SPECIAL */
7153 op
= rtype_funct (inst
);
7154 return (op
== 8 /* JR */
7155 || op
== 9); /* JALR */
7156 break; /* end SPECIAL */
7157 case 1: /* REGIMM */
7158 rs
= itype_rs (inst
);
7159 rt
= itype_rt (inst
); /* branch condition */
7160 return ((rt
& 0xc) == 0
7161 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7162 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7163 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7164 /* BPOSGE32, BPOSGE64: bits 1110x */
7165 break; /* end REGIMM */
7166 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7172 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7173 delay slot (i.e. it is a jump or branch instruction). */
7176 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7181 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7185 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7188 /* Return non-zero if the microMIPS instruction INSN, comprising the
7189 16-bit major opcode word in the high 16 bits and any second word
7190 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7191 jump or branch instruction). The instruction must be 32-bit if
7192 MUSTBE32 is set or can be any instruction otherwise. */
7195 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7197 ULONGEST major
= insn
>> 16;
7199 switch (micromips_op (major
))
7201 /* 16-bit instructions. */
7202 case 0x33: /* B16: bits 110011 */
7203 case 0x2b: /* BNEZ16: bits 101011 */
7204 case 0x23: /* BEQZ16: bits 100011 */
7206 case 0x11: /* POOL16C: bits 010001 */
7208 && ((b5s5_op (major
) == 0xc
7209 /* JR16: bits 010001 01100 */
7210 || (b5s5_op (major
) & 0x1e) == 0xe)));
7211 /* JALR16, JALRS16: bits 010001 0111x */
7212 /* 32-bit instructions. */
7213 case 0x3d: /* JAL: bits 111101 */
7214 case 0x3c: /* JALX: bits 111100 */
7215 case 0x35: /* J: bits 110101 */
7216 case 0x2d: /* BNE: bits 101101 */
7217 case 0x25: /* BEQ: bits 100101 */
7218 case 0x1d: /* JALS: bits 011101 */
7220 case 0x10: /* POOL32I: bits 010000 */
7221 return ((b5s5_op (major
) & 0x1c) == 0x0
7222 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7223 || (b5s5_op (major
) & 0x1d) == 0x4
7224 /* BLEZ, BGTZ: bits 010000 001x0 */
7225 || (b5s5_op (major
) & 0x1d) == 0x11
7226 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7227 || ((b5s5_op (major
) & 0x1e) == 0x14
7228 && (major
& 0x3) == 0x0)
7229 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7230 || (b5s5_op (major
) & 0x1e) == 0x1a
7231 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7232 || ((b5s5_op (major
) & 0x1e) == 0x1c
7233 && (major
& 0x3) == 0x0)
7234 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7235 || ((b5s5_op (major
) & 0x1c) == 0x1c
7236 && (major
& 0x3) == 0x1));
7237 /* BC1ANY*: bits 010000 111xx xxx01 */
7238 case 0x0: /* POOL32A: bits 000000 */
7239 return (b0s6_op (insn
) == 0x3c
7240 /* POOL32Axf: bits 000000 ... 111100 */
7241 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7242 /* JALR, JALR.HB: 000000 000x111100 111100 */
7243 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7249 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7250 slot (i.e. it is a non-compact jump instruction). The instruction
7251 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7254 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7255 CORE_ADDR addr
, int mustbe32
)
7261 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7264 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7266 if (size
== 2 * MIPS_INSN16_SIZE
)
7268 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7273 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7276 /* Return non-zero if the MIPS16 instruction INST, which must be
7277 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7278 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7279 instruction). This function is based on mips16_next_pc. */
7282 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7284 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7286 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7289 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7290 slot (i.e. it is a non-compact jump instruction). The instruction
7291 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7294 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7295 CORE_ADDR addr
, int mustbe32
)
7297 unsigned short insn
;
7300 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7304 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7307 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7308 This assumes KSSEG exists. */
7311 mips_segment_boundary (CORE_ADDR bpaddr
)
7313 CORE_ADDR mask
= CORE_ADDR_MAX
;
7316 if (sizeof (CORE_ADDR
) == 8)
7317 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7318 a compiler warning produced where CORE_ADDR is a 32-bit type even
7319 though in that case this is dead code). */
7320 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7323 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7324 segsize
= 29; /* 32-bit compatibility segment */
7326 segsize
= 62; /* xkseg */
7328 case 2: /* xkphys */
7331 default: /* xksseg (1), xkuseg/kuseg (0) */
7335 else if (bpaddr
& 0x80000000) /* kernel segment */
7338 segsize
= 31; /* user segment */
7340 return bpaddr
& mask
;
7343 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7344 it backwards if necessary. Return the address of the new location. */
7347 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7349 CORE_ADDR prev_addr
;
7351 CORE_ADDR func_addr
;
7353 /* If a breakpoint is set on the instruction in a branch delay slot,
7354 GDB gets confused. When the breakpoint is hit, the PC isn't on
7355 the instruction in the branch delay slot, the PC will point to
7356 the branch instruction. Since the PC doesn't match any known
7357 breakpoints, GDB reports a trap exception.
7359 There are two possible fixes for this problem.
7361 1) When the breakpoint gets hit, see if the BD bit is set in the
7362 Cause register (which indicates the last exception occurred in a
7363 branch delay slot). If the BD bit is set, fix the PC to point to
7364 the instruction in the branch delay slot.
7366 2) When the user sets the breakpoint, don't allow him to set the
7367 breakpoint on the instruction in the branch delay slot. Instead
7368 move the breakpoint to the branch instruction (which will have
7371 The problem with the first solution is that if the user then
7372 single-steps the processor, the branch instruction will get
7373 skipped (since GDB thinks the PC is on the instruction in the
7376 So, we'll use the second solution. To do this we need to know if
7377 the instruction we're trying to set the breakpoint on is in the
7378 branch delay slot. */
7380 boundary
= mips_segment_boundary (bpaddr
);
7382 /* Make sure we don't scan back before the beginning of the current
7383 function, since we may fetch constant data or insns that look like
7384 a jump. Of course we might do that anyway if the compiler has
7385 moved constants inline. :-( */
7386 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7387 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7388 boundary
= func_addr
;
7390 if (mips_pc_is_mips (bpaddr
))
7392 if (bpaddr
== boundary
)
7395 /* If the previous instruction has a branch delay slot, we have
7396 to move the breakpoint to the branch instruction. */
7397 prev_addr
= bpaddr
- 4;
7398 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7403 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7404 CORE_ADDR addr
, jmpaddr
;
7407 boundary
= unmake_compact_addr (boundary
);
7409 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7410 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7411 so try for that first, then try the 2 byte JALR/JR.
7412 The microMIPS ASE has a whole range of jumps and branches
7413 with delay slots, some of which take 4 bytes and some take
7414 2 bytes, so the idea is the same.
7415 FIXME: We have to assume that bpaddr is not the second half
7416 of an extended instruction. */
7417 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7418 ? micromips_insn_at_pc_has_delay_slot
7419 : mips16_insn_at_pc_has_delay_slot
);
7423 for (i
= 1; i
< 4; i
++)
7425 if (unmake_compact_addr (addr
) == boundary
)
7427 addr
-= MIPS_INSN16_SIZE
;
7428 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7429 /* Looks like a JR/JALR at [target-1], but it could be
7430 the second word of a previous JAL/JALX, so record it
7431 and check back one more. */
7433 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7436 /* Looks like a JAL/JALX at [target-2], but it could also
7437 be the second word of a previous JAL/JALX, record it,
7438 and check back one more. */
7441 /* Looks like a JAL/JALX at [target-3], so any previously
7442 recorded JAL/JALX or JR/JALR must be wrong, because:
7445 -2: JAL-ext (can't be JAL/JALX)
7446 -1: bdslot (can't be JR/JALR)
7449 Of course it could be another JAL-ext which looks
7450 like a JAL, but in that case we'd have broken out
7451 of this loop at [target-2]:
7455 -2: bdslot (can't be jmp)
7462 /* Not a jump instruction: if we're at [target-1] this
7463 could be the second word of a JAL/JALX, so continue;
7464 otherwise we're done. */
7477 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7478 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7481 mips_is_stub_suffix (const char *suffix
, int zero
)
7486 return zero
&& suffix
[1] == '\0';
7488 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7493 return suffix
[1] == '\0';
7499 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7500 call stubs, one of sf, df, sc, or dc. */
7503 mips_is_stub_mode (const char *mode
)
7505 return ((mode
[0] == 's' || mode
[0] == 'd')
7506 && (mode
[1] == 'f' || mode
[1] == 'c'));
7509 /* Code at PC is a compiler-generated stub. Such a stub for a function
7510 bar might have a name like __fn_stub_bar, and might look like this:
7517 followed by (or interspersed with):
7524 addiu $25, $25, %lo(bar)
7527 ($1 may be used in old code; for robustness we accept any register)
7530 lui $28, %hi(_gp_disp)
7531 addiu $28, $28, %lo(_gp_disp)
7534 addiu $25, $25, %lo(bar)
7537 In the case of a __call_stub_bar stub, the sequence to set up
7538 arguments might look like this:
7545 followed by (or interspersed with) one of the jump sequences above.
7547 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7548 of J or JR, respectively, followed by:
7554 We are at the beginning of the stub here, and scan down and extract
7555 the target address from the jump immediate instruction or, if a jump
7556 register instruction is used, from the register referred. Return
7557 the value of PC calculated or 0 if inconclusive.
7559 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7562 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7564 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7565 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7566 int addrreg
= MIPS_ZERO_REGNUM
;
7567 CORE_ADDR start_pc
= pc
;
7568 CORE_ADDR target_pc
= 0;
7575 status
== 0 && target_pc
== 0 && i
< 20;
7576 i
++, pc
+= MIPS_INSN32_SIZE
)
7578 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7584 switch (itype_op (inst
))
7586 case 0: /* SPECIAL */
7587 switch (rtype_funct (inst
))
7591 rs
= rtype_rs (inst
);
7592 if (rs
== MIPS_GP_REGNUM
)
7593 target_pc
= gp
; /* Hmm... */
7594 else if (rs
== addrreg
)
7598 case 0x21: /* ADDU */
7599 rt
= rtype_rt (inst
);
7600 rs
= rtype_rs (inst
);
7601 rd
= rtype_rd (inst
);
7602 if (rd
== MIPS_GP_REGNUM
7603 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7604 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7612 target_pc
= jtype_target (inst
) << 2;
7613 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7617 rt
= itype_rt (inst
);
7618 rs
= itype_rs (inst
);
7621 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7622 if (rt
== MIPS_GP_REGNUM
)
7624 else if (rt
== addrreg
)
7630 rt
= itype_rt (inst
);
7631 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7632 if (rt
== MIPS_GP_REGNUM
)
7634 else if (rt
!= MIPS_ZERO_REGNUM
)
7642 rt
= itype_rt (inst
);
7643 rs
= itype_rs (inst
);
7644 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7645 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7649 memset (buf
, 0, sizeof (buf
));
7650 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7652 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7661 /* If PC is in a MIPS16 call or return stub, return the address of the
7662 target PC, which is either the callee or the caller. There are several
7663 cases which must be handled:
7665 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7666 and the target PC is in $31 ($ra).
7667 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7668 and the target PC is in $2.
7669 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7670 i.e. before the JALR instruction, this is effectively a call stub
7671 and the target PC is in $2. Otherwise this is effectively
7672 a return stub and the target PC is in $18.
7673 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7674 JAL or JALR instruction, this is effectively a call stub and the
7675 target PC is buried in the instruction stream. Otherwise this
7676 is effectively a return stub and the target PC is in $18.
7677 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7678 stub and the target PC is buried in the instruction stream.
7680 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7681 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7685 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7687 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7688 CORE_ADDR start_addr
;
7692 /* Find the starting address and name of the function containing the PC. */
7693 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7696 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7697 and the target PC is in $31 ($ra). */
7698 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7699 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7700 && mips_is_stub_mode (name
+ prefixlen
)
7701 && name
[prefixlen
+ 2] == '\0')
7702 return get_frame_register_signed
7703 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7705 /* If the PC is in __mips16_call_stub_*, this is one of the call
7706 call/return stubs. */
7707 prefixlen
= strlen (mips_str_mips16_call_stub
);
7708 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7710 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7711 and the target PC is in $2. */
7712 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7713 return get_frame_register_signed
7714 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7716 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7717 i.e. before the JALR instruction, this is effectively a call stub
7718 and the target PC is in $2. Otherwise this is effectively
7719 a return stub and the target PC is in $18. */
7720 else if (mips_is_stub_mode (name
+ prefixlen
)
7721 && name
[prefixlen
+ 2] == '_'
7722 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7724 if (pc
== start_addr
)
7725 /* This is the 'call' part of a call stub. The return
7726 address is in $2. */
7727 return get_frame_register_signed
7728 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7730 /* This is the 'return' part of a call stub. The return
7731 address is in $18. */
7732 return get_frame_register_signed
7733 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7736 return 0; /* Not a stub. */
7739 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7740 compiler-generated call or call/return stubs. */
7741 if (startswith (name
, mips_str_fn_stub
)
7742 || startswith (name
, mips_str_call_stub
))
7744 if (pc
== start_addr
)
7745 /* This is the 'call' part of a call stub. Call this helper
7746 to scan through this code for interesting instructions
7747 and determine the final PC. */
7748 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7750 /* This is the 'return' part of a call stub. The return address
7752 return get_frame_register_signed
7753 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7756 return 0; /* Not a stub. */
7759 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7760 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7763 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7765 CORE_ADDR start_addr
;
7768 /* Find the starting address of the function containing the PC. */
7769 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7772 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7773 the start, i.e. after the JALR instruction, this is effectively
7775 prefixlen
= strlen (mips_str_mips16_call_stub
);
7776 if (pc
!= start_addr
7777 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7778 && mips_is_stub_mode (name
+ prefixlen
)
7779 && name
[prefixlen
+ 2] == '_'
7780 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7783 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7784 the JAL or JALR instruction, this is effectively a return stub. */
7785 prefixlen
= strlen (mips_str_call_fp_stub
);
7786 if (pc
!= start_addr
7787 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7790 /* Consume the .pic. prefix of any PIC stub, this function must return
7791 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7792 or the call stub path will trigger in handle_inferior_event causing
7794 prefixlen
= strlen (mips_str_pic
);
7795 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7798 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7799 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7800 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7801 && mips_is_stub_mode (name
+ prefixlen
)
7802 && name
[prefixlen
+ 2] == '\0')
7805 return 0; /* Not a stub. */
7808 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7809 PC of the stub target. The stub just loads $t9 and jumps to it,
7810 so that $t9 has the correct value at function entry. */
7813 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7815 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7816 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7817 struct bound_minimal_symbol msym
;
7819 gdb_byte stub_code
[16];
7820 int32_t stub_words
[4];
7822 /* The stub for foo is named ".pic.foo", and is either two
7823 instructions inserted before foo or a three instruction sequence
7824 which jumps to foo. */
7825 msym
= lookup_minimal_symbol_by_pc (pc
);
7826 if (msym
.minsym
== NULL
7827 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7828 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7829 || !startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
7832 /* A two-instruction header. */
7833 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7836 /* A three-instruction (plus delay slot) trampoline. */
7837 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7839 if (target_read_memory (pc
, stub_code
, 16) != 0)
7841 for (i
= 0; i
< 4; i
++)
7842 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7845 /* A stub contains these instructions:
7848 addiu t9, t9, %lo(target)
7851 This works even for N64, since stubs are only generated with
7853 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7854 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7855 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7856 && stub_words
[3] == 0x00000000)
7857 return ((((stub_words
[0] & 0x0000ffff) << 16)
7858 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7861 /* Not a recognized stub. */
7866 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7868 CORE_ADDR requested_pc
= pc
;
7869 CORE_ADDR target_pc
;
7876 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7880 new_pc
= find_solib_trampoline_target (frame
, pc
);
7884 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7888 while (pc
!= target_pc
);
7890 return pc
!= requested_pc
? pc
: 0;
7893 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7894 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7897 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7900 if (num
>= 0 && num
< 32)
7902 else if (num
>= 38 && num
< 70)
7903 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7905 regnum
= mips_regnum (gdbarch
)->hi
;
7907 regnum
= mips_regnum (gdbarch
)->lo
;
7908 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7909 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7912 return gdbarch_num_regs (gdbarch
) + regnum
;
7916 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7917 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7920 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7923 if (num
>= 0 && num
< 32)
7925 else if (num
>= 32 && num
< 64)
7926 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7928 regnum
= mips_regnum (gdbarch
)->hi
;
7930 regnum
= mips_regnum (gdbarch
)->lo
;
7931 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7932 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7935 return gdbarch_num_regs (gdbarch
) + regnum
;
7939 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7941 /* Only makes sense to supply raw registers. */
7942 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7943 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7944 decide if it is valid. Should instead define a standard sim/gdb
7945 register numbering scheme. */
7946 if (gdbarch_register_name (gdbarch
,
7947 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7948 && gdbarch_register_name (gdbarch
,
7949 gdbarch_num_regs (gdbarch
)
7950 + regnum
)[0] != '\0')
7953 return LEGACY_SIM_REGNO_IGNORE
;
7957 /* Convert an integer into an address. Extracting the value signed
7958 guarantees a correctly sign extended address. */
7961 mips_integer_to_address (struct gdbarch
*gdbarch
,
7962 struct type
*type
, const gdb_byte
*buf
)
7964 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7965 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7968 /* Dummy virtual frame pointer method. This is no more or less accurate
7969 than most other architectures; we just need to be explicit about it,
7970 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7971 an assertion failure. */
7974 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7975 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7977 *reg
= MIPS_SP_REGNUM
;
7982 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7984 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7985 const char *name
= bfd_get_section_name (abfd
, sect
);
7987 if (*abip
!= MIPS_ABI_UNKNOWN
)
7990 if (!startswith (name
, ".mdebug."))
7993 if (strcmp (name
, ".mdebug.abi32") == 0)
7994 *abip
= MIPS_ABI_O32
;
7995 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7996 *abip
= MIPS_ABI_N32
;
7997 else if (strcmp (name
, ".mdebug.abi64") == 0)
7998 *abip
= MIPS_ABI_N64
;
7999 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8000 *abip
= MIPS_ABI_O64
;
8001 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8002 *abip
= MIPS_ABI_EABI32
;
8003 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8004 *abip
= MIPS_ABI_EABI64
;
8006 warning (_("unsupported ABI %s."), name
+ 8);
8010 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8012 int *lbp
= (int *) obj
;
8013 const char *name
= bfd_get_section_name (abfd
, sect
);
8015 if (startswith (name
, ".gcc_compiled_long32"))
8017 else if (startswith (name
, ".gcc_compiled_long64"))
8019 else if (startswith (name
, ".gcc_compiled_long"))
8020 warning (_("unrecognized .gcc_compiled_longXX"));
8023 static enum mips_abi
8024 global_mips_abi (void)
8028 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8029 if (mips_abi_strings
[i
] == mips_abi_string
)
8030 return (enum mips_abi
) i
;
8032 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8035 /* Return the default compressed instruction set, either of MIPS16
8036 or microMIPS, selected when none could have been determined from
8037 the ELF header of the binary being executed (or no binary has been
8040 static enum mips_isa
8041 global_mips_compression (void)
8045 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8046 if (mips_compression_strings
[i
] == mips_compression_string
)
8047 return (enum mips_isa
) i
;
8049 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8053 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8055 /* If the size matches the set of 32-bit or 64-bit integer registers,
8056 assume that's what we've got. */
8057 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8058 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8060 /* If the size matches the full set of registers GDB traditionally
8061 knows about, including floating point, for either 32-bit or
8062 64-bit, assume that's what we've got. */
8063 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8064 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8066 /* Otherwise we don't have a useful guess. */
8069 static struct value
*
8070 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8072 const int *reg_p
= (const int *) baton
;
8073 return value_of_register (*reg_p
, frame
);
8076 static struct gdbarch
*
8077 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8079 struct gdbarch
*gdbarch
;
8080 struct gdbarch_tdep
*tdep
;
8082 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8084 enum mips_fpu_type fpu_type
;
8085 struct tdesc_arch_data
*tdesc_data
= NULL
;
8086 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8087 const char **reg_names
;
8088 struct mips_regnum mips_regnum
, *regnum
;
8089 enum mips_isa mips_isa
;
8093 /* Fill in the OS dependent register numbers and names. */
8094 if (info
.osabi
== GDB_OSABI_LINUX
)
8096 mips_regnum
.fp0
= 38;
8097 mips_regnum
.pc
= 37;
8098 mips_regnum
.cause
= 36;
8099 mips_regnum
.badvaddr
= 35;
8100 mips_regnum
.hi
= 34;
8101 mips_regnum
.lo
= 33;
8102 mips_regnum
.fp_control_status
= 70;
8103 mips_regnum
.fp_implementation_revision
= 71;
8104 mips_regnum
.dspacc
= -1;
8105 mips_regnum
.dspctl
= -1;
8109 reg_names
= mips_linux_reg_names
;
8113 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8114 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8115 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8116 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8117 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8118 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8119 mips_regnum
.fp_control_status
= 70;
8120 mips_regnum
.fp_implementation_revision
= 71;
8121 mips_regnum
.dspacc
= dspacc
= -1;
8122 mips_regnum
.dspctl
= dspctl
= -1;
8123 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8124 if (info
.bfd_arch_info
!= NULL
8125 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8126 reg_names
= mips_tx39_reg_names
;
8128 reg_names
= mips_generic_reg_names
;
8131 /* Check any target description for validity. */
8132 if (tdesc_has_registers (info
.target_desc
))
8134 static const char *const mips_gprs
[] = {
8135 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8136 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8137 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8138 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8140 static const char *const mips_fprs
[] = {
8141 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8142 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8143 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8144 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8147 const struct tdesc_feature
*feature
;
8150 feature
= tdesc_find_feature (info
.target_desc
,
8151 "org.gnu.gdb.mips.cpu");
8152 if (feature
== NULL
)
8155 tdesc_data
= tdesc_data_alloc ();
8158 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8159 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8163 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8164 mips_regnum
.lo
, "lo");
8165 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8166 mips_regnum
.hi
, "hi");
8167 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8168 mips_regnum
.pc
, "pc");
8172 tdesc_data_cleanup (tdesc_data
);
8176 feature
= tdesc_find_feature (info
.target_desc
,
8177 "org.gnu.gdb.mips.cp0");
8178 if (feature
== NULL
)
8180 tdesc_data_cleanup (tdesc_data
);
8185 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8186 mips_regnum
.badvaddr
, "badvaddr");
8187 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8188 MIPS_PS_REGNUM
, "status");
8189 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8190 mips_regnum
.cause
, "cause");
8194 tdesc_data_cleanup (tdesc_data
);
8198 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8199 backend is not prepared for that, though. */
8200 feature
= tdesc_find_feature (info
.target_desc
,
8201 "org.gnu.gdb.mips.fpu");
8202 if (feature
== NULL
)
8204 tdesc_data_cleanup (tdesc_data
);
8209 for (i
= 0; i
< 32; i
++)
8210 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8211 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8213 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8214 mips_regnum
.fp_control_status
,
8217 &= tdesc_numbered_register (feature
, tdesc_data
,
8218 mips_regnum
.fp_implementation_revision
,
8223 tdesc_data_cleanup (tdesc_data
);
8227 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8231 feature
= tdesc_find_feature (info
.target_desc
,
8232 "org.gnu.gdb.mips.dsp");
8233 /* The DSP registers are optional; it's OK if they are absent. */
8234 if (feature
!= NULL
)
8238 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8239 dspacc
+ i
++, "hi1");
8240 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8241 dspacc
+ i
++, "lo1");
8242 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8243 dspacc
+ i
++, "hi2");
8244 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8245 dspacc
+ i
++, "lo2");
8246 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8247 dspacc
+ i
++, "hi3");
8248 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8249 dspacc
+ i
++, "lo3");
8251 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8256 tdesc_data_cleanup (tdesc_data
);
8260 mips_regnum
.dspacc
= dspacc
;
8261 mips_regnum
.dspctl
= dspctl
;
8263 num_regs
= mips_regnum
.dspctl
+ 1;
8267 /* It would be nice to detect an attempt to use a 64-bit ABI
8268 when only 32-bit registers are provided. */
8272 /* First of all, extract the elf_flags, if available. */
8273 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8274 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8275 else if (arches
!= NULL
)
8276 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8280 fprintf_unfiltered (gdb_stdlog
,
8281 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8283 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8284 switch ((elf_flags
& EF_MIPS_ABI
))
8286 case E_MIPS_ABI_O32
:
8287 found_abi
= MIPS_ABI_O32
;
8289 case E_MIPS_ABI_O64
:
8290 found_abi
= MIPS_ABI_O64
;
8292 case E_MIPS_ABI_EABI32
:
8293 found_abi
= MIPS_ABI_EABI32
;
8295 case E_MIPS_ABI_EABI64
:
8296 found_abi
= MIPS_ABI_EABI64
;
8299 if ((elf_flags
& EF_MIPS_ABI2
))
8300 found_abi
= MIPS_ABI_N32
;
8302 found_abi
= MIPS_ABI_UNKNOWN
;
8306 /* GCC creates a pseudo-section whose name describes the ABI. */
8307 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8308 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8310 /* If we have no useful BFD information, use the ABI from the last
8311 MIPS architecture (if there is one). */
8312 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8313 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8315 /* Try the architecture for any hint of the correct ABI. */
8316 if (found_abi
== MIPS_ABI_UNKNOWN
8317 && info
.bfd_arch_info
!= NULL
8318 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8320 switch (info
.bfd_arch_info
->mach
)
8322 case bfd_mach_mips3900
:
8323 found_abi
= MIPS_ABI_EABI32
;
8325 case bfd_mach_mips4100
:
8326 case bfd_mach_mips5000
:
8327 found_abi
= MIPS_ABI_EABI64
;
8329 case bfd_mach_mips8000
:
8330 case bfd_mach_mips10000
:
8331 /* On Irix, ELF64 executables use the N64 ABI. The
8332 pseudo-sections which describe the ABI aren't present
8333 on IRIX. (Even for executables created by gcc.) */
8334 if (info
.abfd
!= NULL
8335 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8336 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8337 found_abi
= MIPS_ABI_N64
;
8339 found_abi
= MIPS_ABI_N32
;
8344 /* Default 64-bit objects to N64 instead of O32. */
8345 if (found_abi
== MIPS_ABI_UNKNOWN
8346 && info
.abfd
!= NULL
8347 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8348 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8349 found_abi
= MIPS_ABI_N64
;
8352 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8355 /* What has the user specified from the command line? */
8356 wanted_abi
= global_mips_abi ();
8358 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8361 /* Now that we have found what the ABI for this binary would be,
8362 check whether the user is overriding it. */
8363 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8364 mips_abi
= wanted_abi
;
8365 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8366 mips_abi
= found_abi
;
8368 mips_abi
= MIPS_ABI_O32
;
8370 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8373 /* Determine the default compressed ISA. */
8374 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8375 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8376 mips_isa
= ISA_MICROMIPS
;
8377 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8378 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8379 mips_isa
= ISA_MIPS16
;
8381 mips_isa
= global_mips_compression ();
8382 mips_compression_string
= mips_compression_strings
[mips_isa
];
8384 /* Also used when doing an architecture lookup. */
8386 fprintf_unfiltered (gdb_stdlog
,
8387 "mips_gdbarch_init: "
8388 "mips64_transfers_32bit_regs_p = %d\n",
8389 mips64_transfers_32bit_regs_p
);
8391 /* Determine the MIPS FPU type. */
8394 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8395 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8396 Tag_GNU_MIPS_ABI_FP
);
8397 #endif /* HAVE_ELF */
8399 if (!mips_fpu_type_auto
)
8400 fpu_type
= mips_fpu_type
;
8401 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8403 switch (elf_fpu_type
)
8405 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8406 fpu_type
= MIPS_FPU_DOUBLE
;
8408 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8409 fpu_type
= MIPS_FPU_SINGLE
;
8411 case Val_GNU_MIPS_ABI_FP_SOFT
:
8413 /* Soft float or unknown. */
8414 fpu_type
= MIPS_FPU_NONE
;
8418 else if (info
.bfd_arch_info
!= NULL
8419 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8420 switch (info
.bfd_arch_info
->mach
)
8422 case bfd_mach_mips3900
:
8423 case bfd_mach_mips4100
:
8424 case bfd_mach_mips4111
:
8425 case bfd_mach_mips4120
:
8426 fpu_type
= MIPS_FPU_NONE
;
8428 case bfd_mach_mips4650
:
8429 fpu_type
= MIPS_FPU_SINGLE
;
8432 fpu_type
= MIPS_FPU_DOUBLE
;
8435 else if (arches
!= NULL
)
8436 fpu_type
= MIPS_FPU_TYPE (arches
->gdbarch
);
8438 fpu_type
= MIPS_FPU_DOUBLE
;
8440 fprintf_unfiltered (gdb_stdlog
,
8441 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8443 /* Check for blatant incompatibilities. */
8445 /* If we have only 32-bit registers, then we can't debug a 64-bit
8447 if (info
.target_desc
8448 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8449 && mips_abi
!= MIPS_ABI_EABI32
8450 && mips_abi
!= MIPS_ABI_O32
)
8452 if (tdesc_data
!= NULL
)
8453 tdesc_data_cleanup (tdesc_data
);
8457 /* Try to find a pre-existing architecture. */
8458 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8460 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8462 /* MIPS needs to be pedantic about which ABI and the compressed
8463 ISA variation the object is using. */
8464 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8466 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8468 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8470 /* Need to be pedantic about which register virtual size is
8472 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8473 != mips64_transfers_32bit_regs_p
)
8475 /* Be pedantic about which FPU is selected. */
8476 if (MIPS_FPU_TYPE (arches
->gdbarch
) != fpu_type
)
8479 if (tdesc_data
!= NULL
)
8480 tdesc_data_cleanup (tdesc_data
);
8481 return arches
->gdbarch
;
8484 /* Need a new architecture. Fill in a target specific vector. */
8485 tdep
= XCNEW (struct gdbarch_tdep
);
8486 gdbarch
= gdbarch_alloc (&info
, tdep
);
8487 tdep
->elf_flags
= elf_flags
;
8488 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8489 tdep
->found_abi
= found_abi
;
8490 tdep
->mips_abi
= mips_abi
;
8491 tdep
->mips_isa
= mips_isa
;
8492 tdep
->mips_fpu_type
= fpu_type
;
8493 tdep
->register_size_valid_p
= 0;
8494 tdep
->register_size
= 0;
8496 if (info
.target_desc
)
8498 /* Some useful properties can be inferred from the target. */
8499 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8501 tdep
->register_size_valid_p
= 1;
8502 tdep
->register_size
= 4;
8504 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8506 tdep
->register_size_valid_p
= 1;
8507 tdep
->register_size
= 8;
8511 /* Initially set everything according to the default ABI/ISA. */
8512 set_gdbarch_short_bit (gdbarch
, 16);
8513 set_gdbarch_int_bit (gdbarch
, 32);
8514 set_gdbarch_float_bit (gdbarch
, 32);
8515 set_gdbarch_double_bit (gdbarch
, 64);
8516 set_gdbarch_long_double_bit (gdbarch
, 64);
8517 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8518 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8519 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8521 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8522 mips_ax_pseudo_register_collect
);
8523 set_gdbarch_ax_pseudo_register_push_stack
8524 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8526 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8527 mips_elf_make_msymbol_special
);
8528 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8529 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8530 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8532 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8533 *regnum
= mips_regnum
;
8534 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8535 set_gdbarch_num_regs (gdbarch
, num_regs
);
8536 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8537 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8538 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8539 tdep
->mips_processor_reg_names
= reg_names
;
8540 tdep
->regnum
= regnum
;
8545 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8546 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8547 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8548 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8549 tdep
->default_mask_address_p
= 0;
8550 set_gdbarch_long_bit (gdbarch
, 32);
8551 set_gdbarch_ptr_bit (gdbarch
, 32);
8552 set_gdbarch_long_long_bit (gdbarch
, 64);
8555 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8556 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8557 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8558 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8559 tdep
->default_mask_address_p
= 0;
8560 set_gdbarch_long_bit (gdbarch
, 32);
8561 set_gdbarch_ptr_bit (gdbarch
, 32);
8562 set_gdbarch_long_long_bit (gdbarch
, 64);
8564 case MIPS_ABI_EABI32
:
8565 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8566 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8567 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8568 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8569 tdep
->default_mask_address_p
= 0;
8570 set_gdbarch_long_bit (gdbarch
, 32);
8571 set_gdbarch_ptr_bit (gdbarch
, 32);
8572 set_gdbarch_long_long_bit (gdbarch
, 64);
8574 case MIPS_ABI_EABI64
:
8575 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8576 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8577 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8578 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8579 tdep
->default_mask_address_p
= 0;
8580 set_gdbarch_long_bit (gdbarch
, 64);
8581 set_gdbarch_ptr_bit (gdbarch
, 64);
8582 set_gdbarch_long_long_bit (gdbarch
, 64);
8585 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8586 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8587 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8588 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8589 tdep
->default_mask_address_p
= 0;
8590 set_gdbarch_long_bit (gdbarch
, 32);
8591 set_gdbarch_ptr_bit (gdbarch
, 32);
8592 set_gdbarch_long_long_bit (gdbarch
, 64);
8593 set_gdbarch_long_double_bit (gdbarch
, 128);
8594 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8597 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8598 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8599 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8600 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8601 tdep
->default_mask_address_p
= 0;
8602 set_gdbarch_long_bit (gdbarch
, 64);
8603 set_gdbarch_ptr_bit (gdbarch
, 64);
8604 set_gdbarch_long_long_bit (gdbarch
, 64);
8605 set_gdbarch_long_double_bit (gdbarch
, 128);
8606 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8609 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8612 /* GCC creates a pseudo-section whose name specifies the size of
8613 longs, since -mlong32 or -mlong64 may be used independent of
8614 other options. How those options affect pointer sizes is ABI and
8615 architecture dependent, so use them to override the default sizes
8616 set by the ABI. This table shows the relationship between ABI,
8617 -mlongXX, and size of pointers:
8619 ABI -mlongXX ptr bits
8620 --- -------- --------
8634 Note that for o32 and eabi32, pointers are always 32 bits
8635 regardless of any -mlongXX option. For all others, pointers and
8636 longs are the same, as set by -mlongXX or set by defaults. */
8638 if (info
.abfd
!= NULL
)
8642 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8645 set_gdbarch_long_bit (gdbarch
, long_bit
);
8649 case MIPS_ABI_EABI32
:
8654 case MIPS_ABI_EABI64
:
8655 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8658 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8663 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8664 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8667 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8668 flag in object files because to do so would make it impossible to
8669 link with libraries compiled without "-gp32". This is
8670 unnecessarily restrictive.
8672 We could solve this problem by adding "-gp32" multilibs to gcc,
8673 but to set this flag before gcc is built with such multilibs will
8674 break too many systems.''
8676 But even more unhelpfully, the default linker output target for
8677 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8678 for 64-bit programs - you need to change the ABI to change this,
8679 and not all gcc targets support that currently. Therefore using
8680 this flag to detect 32-bit mode would do the wrong thing given
8681 the current gcc - it would make GDB treat these 64-bit programs
8682 as 32-bit programs by default. */
8684 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8685 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8687 /* Add/remove bits from an address. The MIPS needs be careful to
8688 ensure that all 32 bit addresses are sign extended to 64 bits. */
8689 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8691 /* Unwind the frame. */
8692 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8693 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8694 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8696 /* Map debug register numbers onto internal register numbers. */
8697 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8698 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8699 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8700 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8701 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8702 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8704 /* MIPS version of CALL_DUMMY. */
8706 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8707 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8708 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8710 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8712 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8713 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8714 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8716 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8717 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8718 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8719 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8720 mips_adjust_breakpoint_address
);
8722 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8724 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8726 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8727 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8728 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8730 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8732 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8734 if (mips_abi
== MIPS_ABI_N32
)
8735 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8736 else if (mips_abi
== MIPS_ABI_N64
)
8737 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8739 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8741 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8742 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8743 need to all be folded into the target vector. Since they are
8744 being used as guards for target_stopped_by_watchpoint, why not have
8745 target_stopped_by_watchpoint return the type of watchpoint that the code
8747 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8749 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8751 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8752 to support MIPS16. This is a bad thing. Make sure not to do it
8753 if we have an OS ABI that actually supports shared libraries, since
8754 shared library support is more important. If we have an OS someday
8755 that supports both shared libraries and MIPS16, we'll have to find
8756 a better place for these.
8757 macro/2012-04-25: But that applies to return trampolines only and
8758 currently no MIPS OS ABI uses shared libraries that have them. */
8759 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8761 set_gdbarch_single_step_through_delay (gdbarch
,
8762 mips_single_step_through_delay
);
8764 /* Virtual tables. */
8765 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8767 mips_register_g_packet_guesses (gdbarch
);
8769 /* Hook in OS ABI-specific overrides, if they have been registered. */
8770 info
.tdesc_data
= tdesc_data
;
8771 gdbarch_init_osabi (info
, gdbarch
);
8773 /* The hook may have adjusted num_regs, fetch the final value and
8774 set pc_regnum and sp_regnum now that it has been fixed. */
8775 num_regs
= gdbarch_num_regs (gdbarch
);
8776 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8777 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8779 /* Unwind the frame. */
8780 dwarf2_append_unwinders (gdbarch
);
8781 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8782 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8783 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8784 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8785 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8786 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8787 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8788 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8789 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8793 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8794 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8796 /* Override the normal target description methods to handle our
8797 dual real and pseudo registers. */
8798 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8799 set_gdbarch_register_reggroup_p (gdbarch
,
8800 mips_tdesc_register_reggroup_p
);
8802 num_regs
= gdbarch_num_regs (gdbarch
);
8803 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8804 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8805 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8808 /* Add ABI-specific aliases for the registers. */
8809 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8810 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8811 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8812 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8814 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8815 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8816 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8818 /* Add some other standard aliases. */
8819 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8820 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8821 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8823 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8824 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8825 value_of_mips_user_reg
,
8826 &mips_numeric_register_aliases
[i
].regnum
);
8832 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8834 struct gdbarch_info info
;
8836 /* Force the architecture to update, and (if it's a MIPS architecture)
8837 mips_gdbarch_init will take care of the rest. */
8838 gdbarch_info_init (&info
);
8839 gdbarch_update_p (info
);
8842 /* Print out which MIPS ABI is in use. */
8845 show_mips_abi (struct ui_file
*file
,
8847 struct cmd_list_element
*ignored_cmd
,
8848 const char *ignored_value
)
8850 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8853 "The MIPS ABI is unknown because the current architecture "
8857 enum mips_abi global_abi
= global_mips_abi ();
8858 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8859 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8861 if (global_abi
== MIPS_ABI_UNKNOWN
)
8864 "The MIPS ABI is set automatically (currently \"%s\").\n",
8866 else if (global_abi
== actual_abi
)
8869 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8873 /* Probably shouldn't happen... */
8874 fprintf_filtered (file
,
8875 "The (auto detected) MIPS ABI \"%s\" is in use "
8876 "even though the user setting was \"%s\".\n",
8877 actual_abi_str
, mips_abi_strings
[global_abi
]);
8882 /* Print out which MIPS compressed ISA encoding is used. */
8885 show_mips_compression (struct ui_file
*file
, int from_tty
,
8886 struct cmd_list_element
*c
, const char *value
)
8888 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8892 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8895 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8901 case MIPS_FPU_SINGLE
:
8903 case MIPS_FPU_DOUBLE
:
8911 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8913 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8917 int ef_mips_32bitmode
;
8918 /* Determine the ISA. */
8919 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8937 /* Determine the size of a pointer. */
8938 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8939 fprintf_unfiltered (file
,
8940 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8942 fprintf_unfiltered (file
,
8943 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8945 fprintf_unfiltered (file
,
8946 "mips_dump_tdep: ef_mips_arch = %d\n",
8948 fprintf_unfiltered (file
,
8949 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8950 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8951 fprintf_unfiltered (file
,
8953 "mips_mask_address_p() %d (default %d)\n",
8954 mips_mask_address_p (tdep
),
8955 tdep
->default_mask_address_p
);
8957 fprintf_unfiltered (file
,
8958 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8959 MIPS_DEFAULT_FPU_TYPE
,
8960 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8961 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8962 MIPS_EABI (gdbarch
));
8963 fprintf_unfiltered (file
,
8964 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8965 MIPS_FPU_TYPE (gdbarch
),
8966 mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch
)));
8970 _initialize_mips_tdep (void)
8972 static struct cmd_list_element
*mipsfpulist
= NULL
;
8973 struct cmd_list_element
*c
;
8975 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8976 if (MIPS_ABI_LAST
+ 1
8977 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8978 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8980 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8982 mips_pdr_data
= register_objfile_data ();
8984 /* Create feature sets with the appropriate properties. The values
8985 are not important. */
8986 mips_tdesc_gp32
= allocate_target_description ();
8987 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8989 mips_tdesc_gp64
= allocate_target_description ();
8990 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8992 /* Add root prefix command for all "set mips"/"show mips" commands. */
8993 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8994 _("Various MIPS specific commands."),
8995 &setmipscmdlist
, "set mips ", 0, &setlist
);
8997 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8998 _("Various MIPS specific commands."),
8999 &showmipscmdlist
, "show mips ", 0, &showlist
);
9001 /* Allow the user to override the ABI. */
9002 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9003 &mips_abi_string
, _("\
9004 Set the MIPS ABI used by this program."), _("\
9005 Show the MIPS ABI used by this program."), _("\
9006 This option can be set to one of:\n\
9007 auto - the default ABI associated with the current binary\n\
9016 &setmipscmdlist
, &showmipscmdlist
);
9018 /* Allow the user to set the ISA to assume for compressed code if ELF
9019 file flags don't tell or there is no program file selected. This
9020 setting is updated whenever unambiguous ELF file flags are interpreted,
9021 and carried over to subsequent sessions. */
9022 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9023 &mips_compression_string
, _("\
9024 Set the compressed ISA encoding used by MIPS code."), _("\
9025 Show the compressed ISA encoding used by MIPS code."), _("\
9026 Select the compressed ISA encoding used in functions that have no symbol\n\
9027 information available. The encoding can be set to either of:\n\
9030 and is updated automatically from ELF file flags if available."),
9032 show_mips_compression
,
9033 &setmipscmdlist
, &showmipscmdlist
);
9035 /* Let the user turn off floating point and set the fence post for
9036 heuristic_proc_start. */
9038 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9039 _("Set use of MIPS floating-point coprocessor."),
9040 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9041 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9042 _("Select single-precision MIPS floating-point coprocessor."),
9044 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9045 _("Select double-precision MIPS floating-point coprocessor."),
9047 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9048 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9049 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9050 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9051 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9052 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9053 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9054 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9055 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9056 _("Select MIPS floating-point coprocessor automatically."),
9058 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9059 _("Show current use of MIPS floating-point coprocessor target."),
9062 /* We really would like to have both "0" and "unlimited" work, but
9063 command.c doesn't deal with that. So make it a var_zinteger
9064 because the user can always use "999999" or some such for unlimited. */
9065 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9066 &heuristic_fence_post
, _("\
9067 Set the distance searched for the start of a function."), _("\
9068 Show the distance searched for the start of a function."), _("\
9069 If you are debugging a stripped executable, GDB needs to search through the\n\
9070 program for the start of a function. This command sets the distance of the\n\
9071 search. The only need to set it is when debugging a stripped executable."),
9072 reinit_frame_cache_sfunc
,
9073 NULL
, /* FIXME: i18n: The distance searched for
9074 the start of a function is %s. */
9075 &setlist
, &showlist
);
9077 /* Allow the user to control whether the upper bits of 64-bit
9078 addresses should be zeroed. */
9079 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9080 &mask_address_var
, _("\
9081 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9082 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9083 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9084 allow GDB to determine the correct value."),
9085 NULL
, show_mask_address
,
9086 &setmipscmdlist
, &showmipscmdlist
);
9088 /* Allow the user to control the size of 32 bit registers within the
9089 raw remote packet. */
9090 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9091 &mips64_transfers_32bit_regs_p
, _("\
9092 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9094 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9096 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9097 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9098 64 bits for others. Use \"off\" to disable compatibility mode"),
9099 set_mips64_transfers_32bit_regs
,
9100 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9101 MIPS target that transfers 32-bit
9102 quantities is %s. */
9103 &setlist
, &showlist
);
9105 /* Debug this files internals. */
9106 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9108 Set mips debugging."), _("\
9109 Show mips debugging."), _("\
9110 When non-zero, mips specific debugging is enabled."),
9112 NULL
, /* FIXME: i18n: Mips debugging is
9114 &setdebuglist
, &showdebuglist
);