1 /* Copyright (C) 2009-2016 Free Software Foundation, Inc.
2 Contributed by ARM Ltd.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 #include "common-defs.h"
20 #include "break-common.h"
21 #include "common-regcache.h"
22 #include "nat/linux-nat.h"
23 #include "aarch64-linux-hw-point.h"
26 #include <asm/ptrace.h>
27 #include <sys/ptrace.h>
30 /* Number of hardware breakpoints/watchpoints the target supports.
31 They are initialized with values obtained via the ptrace calls
32 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
34 int aarch64_num_bp_regs
;
35 int aarch64_num_wp_regs
;
37 /* Utility function that returns the length in bytes of a watchpoint
38 according to the content of a hardware debug control register CTRL.
39 Note that the kernel currently only supports the following Byte
40 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
41 that for a hardware watchpoint, its valid length can only be 1
42 byte, 2 bytes, 4 bytes or 8 bytes. */
45 aarch64_watchpoint_length (unsigned int ctrl
)
47 switch (DR_CONTROL_LENGTH (ctrl
))
62 /* Given the hardware breakpoint or watchpoint type TYPE and its
63 length LEN, return the expected encoding for a hardware
64 breakpoint/watchpoint control register. */
67 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type
, int len
)
69 unsigned int ctrl
, ttype
;
87 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
93 ctrl
|= ((1 << len
) - 1) << 5;
100 /* Addresses to be written to the hardware breakpoint and watchpoint
101 value registers need to be aligned; the alignment is 4-byte and
102 8-type respectively. Linux kernel rejects any non-aligned address
103 it receives from the related ptrace call. Furthermore, the kernel
104 currently only supports the following Byte Address Select (BAS)
105 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
106 watchpoint to be accepted by the kernel (via ptrace call), its
107 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
108 Despite these limitations, the unaligned watchpoint is supported in
111 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
114 aarch64_point_is_aligned (int is_watchpoint
, CORE_ADDR addr
, int len
)
116 unsigned int alignment
= 0;
119 alignment
= AARCH64_HWP_ALIGNMENT
;
122 struct regcache
*regcache
123 = get_thread_regcache_for_ptid (current_lwp_ptid ());
125 /* Set alignment to 2 only if the current process is 32-bit,
126 since thumb instruction can be 2-byte aligned. Otherwise, set
127 alignment to AARCH64_HBP_ALIGNMENT. */
128 if (regcache_register_size (regcache
, 0) == 8)
129 alignment
= AARCH64_HBP_ALIGNMENT
;
134 if (addr
& (alignment
- 1))
137 if (len
!= 8 && len
!= 4 && len
!= 2 && len
!= 1)
143 /* Given the (potentially unaligned) watchpoint address in ADDR and
144 length in LEN, return the aligned address and aligned length in
145 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
146 aligned address and length will be valid values to write to the
147 hardware watchpoint value and control registers.
149 The given watchpoint may get truncated if more than one hardware
150 register is needed to cover the watched region. *NEXT_ADDR_P
151 and *NEXT_LEN_P, if non-NULL, will return the address and length
152 of the remaining part of the watchpoint (which can be processed
153 by calling this routine again to generate another aligned address
156 Essentially, unaligned watchpoint is achieved by minimally
157 enlarging the watched area to meet the alignment requirement, and
158 if necessary, splitting the watchpoint over several hardware
159 watchpoint registers. The trade-off is that there will be
160 false-positive hits for the read-type or the access-type hardware
161 watchpoints; for the write type, which is more commonly used, there
162 will be no such issues, as the higher-level breakpoint management
163 in gdb always examines the exact watched region for any content
164 change, and transparently resumes a thread from a watchpoint trap
165 if there is no change to the watched region.
167 Another limitation is that because the watched region is enlarged,
168 the watchpoint fault address returned by
169 aarch64_stopped_data_address may be outside of the original watched
170 region, especially when the triggering instruction is accessing a
171 larger region. When the fault address is not within any known
172 range, watchpoints_triggered in gdb will get confused, as the
173 higher-level watchpoint management is only aware of original
174 watched regions, and will think that some unknown watchpoint has
175 been triggered. In such a case, gdb may stop without displaying
176 any detailed information.
178 Once the kernel provides the full support for Byte Address Select
179 (BAS) in the hardware watchpoint control register, these
180 limitations can be largely relaxed with some further work. */
183 aarch64_align_watchpoint (CORE_ADDR addr
, int len
, CORE_ADDR
*aligned_addr_p
,
184 int *aligned_len_p
, CORE_ADDR
*next_addr_p
,
189 CORE_ADDR aligned_addr
;
190 const unsigned int alignment
= AARCH64_HWP_ALIGNMENT
;
191 const unsigned int max_wp_len
= AARCH64_HWP_MAX_LEN_PER_REG
;
193 /* As assumed by the algorithm. */
194 gdb_assert (alignment
== max_wp_len
);
199 /* Address to be put into the hardware watchpoint value register
201 offset
= addr
& (alignment
- 1);
202 aligned_addr
= addr
- offset
;
204 gdb_assert (offset
>= 0 && offset
< alignment
);
205 gdb_assert (aligned_addr
>= 0 && aligned_addr
<= addr
);
206 gdb_assert (offset
+ len
> 0);
208 if (offset
+ len
>= max_wp_len
)
210 /* Need more than one watchpoint registers; truncate it at the
211 alignment boundary. */
212 aligned_len
= max_wp_len
;
213 len
-= (max_wp_len
- offset
);
214 addr
+= (max_wp_len
- offset
);
215 gdb_assert ((addr
& (alignment
- 1)) == 0);
219 /* Find the smallest valid length that is large enough to
220 accommodate this watchpoint. */
221 static const unsigned char
222 aligned_len_array
[AARCH64_HWP_MAX_LEN_PER_REG
] =
223 { 1, 2, 4, 4, 8, 8, 8, 8 };
225 aligned_len
= aligned_len_array
[offset
+ len
- 1];
231 *aligned_addr_p
= aligned_addr
;
233 *aligned_len_p
= aligned_len
;
240 struct aarch64_dr_update_callback_param
246 /* Callback for iterate_over_lwps. Records the
247 information about the change of one hardware breakpoint/watchpoint
248 setting for the thread LWP.
249 The information is passed in via PTR.
250 N.B. The actual updating of hardware debug registers is not
251 carried out until the moment the thread is resumed. */
254 debug_reg_change_callback (struct lwp_info
*lwp
, void *ptr
)
256 struct aarch64_dr_update_callback_param
*param_p
257 = (struct aarch64_dr_update_callback_param
*) ptr
;
258 int tid
= ptid_get_lwp (ptid_of_lwp (lwp
));
259 int idx
= param_p
->idx
;
260 int is_watchpoint
= param_p
->is_watchpoint
;
261 struct arch_lwp_info
*info
= lwp_arch_private_info (lwp
);
262 dr_changed_t
*dr_changed_ptr
;
263 dr_changed_t dr_changed
;
267 info
= XCNEW (struct arch_lwp_info
);
268 lwp_set_arch_private_info (lwp
, info
);
273 debug_printf ("debug_reg_change_callback: \n\tOn entry:\n");
274 debug_printf ("\ttid%d, dr_changed_bp=0x%s, "
275 "dr_changed_wp=0x%s\n", tid
,
276 phex (info
->dr_changed_bp
, 8),
277 phex (info
->dr_changed_wp
, 8));
280 dr_changed_ptr
= is_watchpoint
? &info
->dr_changed_wp
281 : &info
->dr_changed_bp
;
282 dr_changed
= *dr_changed_ptr
;
285 && (idx
<= (is_watchpoint
? aarch64_num_wp_regs
286 : aarch64_num_bp_regs
)));
288 /* The actual update is done later just before resuming the lwp,
289 we just mark that one register pair needs updating. */
290 DR_MARK_N_CHANGED (dr_changed
, idx
);
291 *dr_changed_ptr
= dr_changed
;
293 /* If the lwp isn't stopped, force it to momentarily pause, so
294 we can update its debug registers. */
295 if (!lwp_is_stopped (lwp
))
296 linux_stop_lwp (lwp
);
300 debug_printf ("\tOn exit:\n\ttid%d, dr_changed_bp=0x%s, "
301 "dr_changed_wp=0x%s\n", tid
,
302 phex (info
->dr_changed_bp
, 8),
303 phex (info
->dr_changed_wp
, 8));
309 /* Notify each thread that their IDXth breakpoint/watchpoint register
310 pair needs to be updated. The message will be recorded in each
311 thread's arch-specific data area, the actual updating will be done
312 when the thread is resumed. */
315 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state
*state
,
316 int is_watchpoint
, unsigned int idx
)
318 struct aarch64_dr_update_callback_param param
;
319 ptid_t pid_ptid
= pid_to_ptid (ptid_get_pid (current_lwp_ptid ()));
321 param
.is_watchpoint
= is_watchpoint
;
324 iterate_over_lwps (pid_ptid
, debug_reg_change_callback
, (void *) ¶m
);
327 /* Record the insertion of one breakpoint/watchpoint, as represented
328 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
331 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state
*state
,
332 enum target_hw_bp_type type
,
333 CORE_ADDR addr
, int len
)
335 int i
, idx
, num_regs
, is_watchpoint
;
336 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
337 CORE_ADDR
*dr_addr_p
;
339 /* Set up state pointers. */
340 is_watchpoint
= (type
!= hw_execute
);
341 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
344 num_regs
= aarch64_num_wp_regs
;
345 dr_addr_p
= state
->dr_addr_wp
;
346 dr_ctrl_p
= state
->dr_ctrl_wp
;
347 dr_ref_count
= state
->dr_ref_count_wp
;
351 num_regs
= aarch64_num_bp_regs
;
352 dr_addr_p
= state
->dr_addr_bp
;
353 dr_ctrl_p
= state
->dr_ctrl_bp
;
354 dr_ref_count
= state
->dr_ref_count_bp
;
357 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
359 /* Find an existing or free register in our cache. */
361 for (i
= 0; i
< num_regs
; ++i
)
363 if ((dr_ctrl_p
[i
] & 1) == 0)
365 gdb_assert (dr_ref_count
[i
] == 0);
367 /* no break; continue hunting for an exising one. */
369 else if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
371 gdb_assert (dr_ref_count
[i
] != 0);
381 /* Update our cache. */
382 if ((dr_ctrl_p
[idx
] & 1) == 0)
385 dr_addr_p
[idx
] = addr
;
386 dr_ctrl_p
[idx
] = ctrl
;
387 dr_ref_count
[idx
] = 1;
388 /* Notify the change. */
389 aarch64_notify_debug_reg_change (state
, is_watchpoint
, idx
);
400 /* Record the removal of one breakpoint/watchpoint, as represented by
401 ADDR and CTRL, in the process' arch-specific data area *STATE. */
404 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state
*state
,
405 enum target_hw_bp_type type
,
406 CORE_ADDR addr
, int len
)
408 int i
, num_regs
, is_watchpoint
;
409 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
410 CORE_ADDR
*dr_addr_p
;
412 /* Set up state pointers. */
413 is_watchpoint
= (type
!= hw_execute
);
416 num_regs
= aarch64_num_wp_regs
;
417 dr_addr_p
= state
->dr_addr_wp
;
418 dr_ctrl_p
= state
->dr_ctrl_wp
;
419 dr_ref_count
= state
->dr_ref_count_wp
;
423 num_regs
= aarch64_num_bp_regs
;
424 dr_addr_p
= state
->dr_addr_bp
;
425 dr_ctrl_p
= state
->dr_ctrl_bp
;
426 dr_ref_count
= state
->dr_ref_count_bp
;
429 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
431 /* Find the entry that matches the ADDR and CTRL. */
432 for (i
= 0; i
< num_regs
; ++i
)
433 if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
435 gdb_assert (dr_ref_count
[i
] != 0);
443 /* Clear our cache. */
444 if (--dr_ref_count
[i
] == 0)
446 /* Clear the enable bit. */
450 /* Notify the change. */
451 aarch64_notify_debug_reg_change (state
, is_watchpoint
, i
);
458 aarch64_handle_breakpoint (enum target_hw_bp_type type
, CORE_ADDR addr
,
459 int len
, int is_insert
,
460 struct aarch64_debug_reg_state
*state
)
464 /* The hardware breakpoint on AArch64 should always be 4-byte
465 aligned, but on AArch32, it can be 2-byte aligned. Note that
466 we only check the alignment on inserting breakpoint because
467 aarch64_point_is_aligned needs the inferior_ptid inferior's
468 regcache to decide whether the inferior is 32-bit or 64-bit.
469 However when GDB follows the parent process and detach breakpoints
470 from child process, inferior_ptid is the child ptid, but the
471 child inferior doesn't exist in GDB's view yet. */
472 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr
, len
))
475 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
478 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
481 /* This is essentially the same as aarch64_handle_breakpoint, apart
482 from that it is an aligned watchpoint to be handled. */
485 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type
,
486 CORE_ADDR addr
, int len
, int is_insert
,
487 struct aarch64_debug_reg_state
*state
)
490 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
492 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
495 /* Insert/remove unaligned watchpoint by calling
496 aarch64_align_watchpoint repeatedly until the whole watched region,
497 as represented by ADDR and LEN, has been properly aligned and ready
498 to be written to one or more hardware watchpoint registers.
499 IS_INSERT indicates whether this is an insertion or a deletion.
500 Return 0 if succeed. */
503 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type
,
504 CORE_ADDR addr
, int len
, int is_insert
,
505 struct aarch64_debug_reg_state
*state
)
509 CORE_ADDR aligned_addr
;
510 int aligned_len
, ret
;
512 aarch64_align_watchpoint (addr
, len
, &aligned_addr
, &aligned_len
,
516 ret
= aarch64_dr_state_insert_one_point (state
, type
, aligned_addr
,
519 ret
= aarch64_dr_state_remove_one_point (state
, type
, aligned_addr
,
523 debug_printf ("handle_unaligned_watchpoint: is_insert: %d\n"
525 "aligned_addr: %s, aligned_len: %d\n"
527 "next_addr: %s, next_len: %d\n",
528 is_insert
, core_addr_to_string_nz (aligned_addr
),
529 aligned_len
, core_addr_to_string_nz (addr
), len
);
539 aarch64_handle_watchpoint (enum target_hw_bp_type type
, CORE_ADDR addr
,
540 int len
, int is_insert
,
541 struct aarch64_debug_reg_state
*state
)
543 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr
, len
))
544 return aarch64_handle_aligned_watchpoint (type
, addr
, len
, is_insert
,
547 return aarch64_handle_unaligned_watchpoint (type
, addr
, len
, is_insert
,
551 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
552 registers with data from *STATE. */
555 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state
*state
,
556 int tid
, int watchpoint
)
560 struct user_hwdebug_state regs
;
561 const CORE_ADDR
*addr
;
562 const unsigned int *ctrl
;
564 memset (®s
, 0, sizeof (regs
));
565 iov
.iov_base
= ®s
;
566 count
= watchpoint
? aarch64_num_wp_regs
: aarch64_num_bp_regs
;
567 addr
= watchpoint
? state
->dr_addr_wp
: state
->dr_addr_bp
;
568 ctrl
= watchpoint
? state
->dr_ctrl_wp
: state
->dr_ctrl_bp
;
571 iov
.iov_len
= (offsetof (struct user_hwdebug_state
, dbg_regs
)
572 + count
* sizeof (regs
.dbg_regs
[0]));
574 for (i
= 0; i
< count
; i
++)
576 regs
.dbg_regs
[i
].addr
= addr
[i
];
577 regs
.dbg_regs
[i
].ctrl
= ctrl
[i
];
580 if (ptrace (PTRACE_SETREGSET
, tid
,
581 watchpoint
? NT_ARM_HW_WATCH
: NT_ARM_HW_BREAK
,
583 error (_("Unexpected error setting hardware debug registers"));
586 /* Print the values of the cached breakpoint/watchpoint registers. */
589 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state
*state
,
590 const char *func
, CORE_ADDR addr
,
591 int len
, enum target_hw_bp_type type
)
595 debug_printf ("%s", func
);
597 debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
598 (unsigned long) addr
, len
,
599 type
== hw_write
? "hw-write-watchpoint"
600 : (type
== hw_read
? "hw-read-watchpoint"
601 : (type
== hw_access
? "hw-access-watchpoint"
602 : (type
== hw_execute
? "hw-breakpoint"
604 debug_printf (":\n");
606 debug_printf ("\tBREAKPOINTs:\n");
607 for (i
= 0; i
< aarch64_num_bp_regs
; i
++)
608 debug_printf ("\tBP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
609 i
, core_addr_to_string_nz (state
->dr_addr_bp
[i
]),
610 state
->dr_ctrl_bp
[i
], state
->dr_ref_count_bp
[i
]);
612 debug_printf ("\tWATCHPOINTs:\n");
613 for (i
= 0; i
< aarch64_num_wp_regs
; i
++)
614 debug_printf ("\tWP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
615 i
, core_addr_to_string_nz (state
->dr_addr_wp
[i
]),
616 state
->dr_ctrl_wp
[i
], state
->dr_ref_count_wp
[i
]);
619 /* Get the hardware debug register capacity information from the
620 process represented by TID. */
623 aarch64_linux_get_debug_reg_capacity (int tid
)
626 struct user_hwdebug_state dreg_state
;
628 iov
.iov_base
= &dreg_state
;
629 iov
.iov_len
= sizeof (dreg_state
);
631 /* Get hardware watchpoint register info. */
632 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_WATCH
, &iov
) == 0
633 && (AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
634 || AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8_1
635 || AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8_2
))
637 aarch64_num_wp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
638 if (aarch64_num_wp_regs
> AARCH64_HWP_MAX_NUM
)
640 warning (_("Unexpected number of hardware watchpoint registers"
641 " reported by ptrace, got %d, expected %d."),
642 aarch64_num_wp_regs
, AARCH64_HWP_MAX_NUM
);
643 aarch64_num_wp_regs
= AARCH64_HWP_MAX_NUM
;
648 warning (_("Unable to determine the number of hardware watchpoints"
650 aarch64_num_wp_regs
= 0;
653 /* Get hardware breakpoint register info. */
654 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_BREAK
, &iov
) == 0
655 && (AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
656 || AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8_1
657 || AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8_2
))
659 aarch64_num_bp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
660 if (aarch64_num_bp_regs
> AARCH64_HBP_MAX_NUM
)
662 warning (_("Unexpected number of hardware breakpoint registers"
663 " reported by ptrace, got %d, expected %d."),
664 aarch64_num_bp_regs
, AARCH64_HBP_MAX_NUM
);
665 aarch64_num_bp_regs
= AARCH64_HBP_MAX_NUM
;
670 warning (_("Unable to determine the number of hardware breakpoints"
672 aarch64_num_bp_regs
= 0;
676 /* Return true if we can watch a memory region that starts address
677 ADDR and whose length is LEN in bytes. */
680 aarch64_linux_region_ok_for_watchpoint (CORE_ADDR addr
, int len
)
682 CORE_ADDR aligned_addr
;
684 /* Can not set watchpoints for zero or negative lengths. */
688 /* Must have hardware watchpoint debug register(s). */
689 if (aarch64_num_wp_regs
== 0)
692 /* We support unaligned watchpoint address and arbitrary length,
693 as long as the size of the whole watched area after alignment
694 doesn't exceed size of the total area that all watchpoint debug
695 registers can watch cooperatively.
697 This is a very relaxed rule, but unfortunately there are
698 limitations, e.g. false-positive hits, due to limited support of
699 hardware debug registers in the kernel. See comment above
700 aarch64_align_watchpoint for more information. */
702 aligned_addr
= addr
& ~(AARCH64_HWP_MAX_LEN_PER_REG
- 1);
703 if (aligned_addr
+ aarch64_num_wp_regs
* AARCH64_HWP_MAX_LEN_PER_REG
707 /* All tests passed so we are likely to be able to set the watchpoint.
708 The reason that it is 'likely' rather than 'must' is because
709 we don't check the current usage of the watchpoint registers, and
710 there may not be enough registers available for this watchpoint.
711 Ideally we should check the cached debug register state, however
712 the checking is costly. */