1 /* Copyright (C) 2009-2015 Free Software Foundation, Inc.
2 Contributed by ARM Ltd.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 #include "common-defs.h"
20 #include "break-common.h"
21 #include "nat/linux-nat.h"
22 #include "aarch64-linux-hw-point.h"
25 #include <asm/ptrace.h>
26 #include <sys/ptrace.h>
29 /* Number of hardware breakpoints/watchpoints the target supports.
30 They are initialized with values obtained via the ptrace calls
31 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
33 int aarch64_num_bp_regs
;
34 int aarch64_num_wp_regs
;
36 /* Utility function that returns the length in bytes of a watchpoint
37 according to the content of a hardware debug control register CTRL.
38 Note that the kernel currently only supports the following Byte
39 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
40 that for a hardware watchpoint, its valid length can only be 1
41 byte, 2 bytes, 4 bytes or 8 bytes. */
44 aarch64_watchpoint_length (unsigned int ctrl
)
46 switch (DR_CONTROL_LENGTH (ctrl
))
61 /* Given the hardware breakpoint or watchpoint type TYPE and its
62 length LEN, return the expected encoding for a hardware
63 breakpoint/watchpoint control register. */
66 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type
, int len
)
68 unsigned int ctrl
, ttype
;
86 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
92 ctrl
|= ((1 << len
) - 1) << 5;
99 /* Addresses to be written to the hardware breakpoint and watchpoint
100 value registers need to be aligned; the alignment is 4-byte and
101 8-type respectively. Linux kernel rejects any non-aligned address
102 it receives from the related ptrace call. Furthermore, the kernel
103 currently only supports the following Byte Address Select (BAS)
104 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
105 watchpoint to be accepted by the kernel (via ptrace call), its
106 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
107 Despite these limitations, the unaligned watchpoint is supported in
110 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
113 aarch64_point_is_aligned (int is_watchpoint
, CORE_ADDR addr
, int len
)
115 unsigned int alignment
= is_watchpoint
? AARCH64_HWP_ALIGNMENT
116 : AARCH64_HBP_ALIGNMENT
;
118 if (addr
& (alignment
- 1))
121 if (len
!= 8 && len
!= 4 && len
!= 2 && len
!= 1)
127 /* Given the (potentially unaligned) watchpoint address in ADDR and
128 length in LEN, return the aligned address and aligned length in
129 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
130 aligned address and length will be valid values to write to the
131 hardware watchpoint value and control registers.
133 The given watchpoint may get truncated if more than one hardware
134 register is needed to cover the watched region. *NEXT_ADDR_P
135 and *NEXT_LEN_P, if non-NULL, will return the address and length
136 of the remaining part of the watchpoint (which can be processed
137 by calling this routine again to generate another aligned address
140 Essentially, unaligned watchpoint is achieved by minimally
141 enlarging the watched area to meet the alignment requirement, and
142 if necessary, splitting the watchpoint over several hardware
143 watchpoint registers. The trade-off is that there will be
144 false-positive hits for the read-type or the access-type hardware
145 watchpoints; for the write type, which is more commonly used, there
146 will be no such issues, as the higher-level breakpoint management
147 in gdb always examines the exact watched region for any content
148 change, and transparently resumes a thread from a watchpoint trap
149 if there is no change to the watched region.
151 Another limitation is that because the watched region is enlarged,
152 the watchpoint fault address returned by
153 aarch64_stopped_data_address may be outside of the original watched
154 region, especially when the triggering instruction is accessing a
155 larger region. When the fault address is not within any known
156 range, watchpoints_triggered in gdb will get confused, as the
157 higher-level watchpoint management is only aware of original
158 watched regions, and will think that some unknown watchpoint has
159 been triggered. In such a case, gdb may stop without displaying
160 any detailed information.
162 Once the kernel provides the full support for Byte Address Select
163 (BAS) in the hardware watchpoint control register, these
164 limitations can be largely relaxed with some further work. */
167 aarch64_align_watchpoint (CORE_ADDR addr
, int len
, CORE_ADDR
*aligned_addr_p
,
168 int *aligned_len_p
, CORE_ADDR
*next_addr_p
,
173 CORE_ADDR aligned_addr
;
174 const unsigned int alignment
= AARCH64_HWP_ALIGNMENT
;
175 const unsigned int max_wp_len
= AARCH64_HWP_MAX_LEN_PER_REG
;
177 /* As assumed by the algorithm. */
178 gdb_assert (alignment
== max_wp_len
);
183 /* Address to be put into the hardware watchpoint value register
185 offset
= addr
& (alignment
- 1);
186 aligned_addr
= addr
- offset
;
188 gdb_assert (offset
>= 0 && offset
< alignment
);
189 gdb_assert (aligned_addr
>= 0 && aligned_addr
<= addr
);
190 gdb_assert (offset
+ len
> 0);
192 if (offset
+ len
>= max_wp_len
)
194 /* Need more than one watchpoint registers; truncate it at the
195 alignment boundary. */
196 aligned_len
= max_wp_len
;
197 len
-= (max_wp_len
- offset
);
198 addr
+= (max_wp_len
- offset
);
199 gdb_assert ((addr
& (alignment
- 1)) == 0);
203 /* Find the smallest valid length that is large enough to
204 accommodate this watchpoint. */
205 static const unsigned char
206 aligned_len_array
[AARCH64_HWP_MAX_LEN_PER_REG
] =
207 { 1, 2, 4, 4, 8, 8, 8, 8 };
209 aligned_len
= aligned_len_array
[offset
+ len
- 1];
215 *aligned_addr_p
= aligned_addr
;
217 *aligned_len_p
= aligned_len
;
224 struct aarch64_dr_update_callback_param
230 /* Callback for iterate_over_lwps. Records the
231 information about the change of one hardware breakpoint/watchpoint
232 setting for the thread LWP.
233 The information is passed in via PTR.
234 N.B. The actual updating of hardware debug registers is not
235 carried out until the moment the thread is resumed. */
238 debug_reg_change_callback (struct lwp_info
*lwp
, void *ptr
)
240 struct aarch64_dr_update_callback_param
*param_p
241 = (struct aarch64_dr_update_callback_param
*) ptr
;
242 int tid
= ptid_get_lwp (ptid_of_lwp (lwp
));
243 int idx
= param_p
->idx
;
244 int is_watchpoint
= param_p
->is_watchpoint
;
245 struct arch_lwp_info
*info
= lwp_arch_private_info (lwp
);
246 dr_changed_t
*dr_changed_ptr
;
247 dr_changed_t dr_changed
;
251 info
= XCNEW (struct arch_lwp_info
);
252 lwp_set_arch_private_info (lwp
, info
);
257 debug_printf ("debug_reg_change_callback: \n\tOn entry:\n");
258 debug_printf ("\ttid%d, dr_changed_bp=0x%s, "
259 "dr_changed_wp=0x%s\n", tid
,
260 phex (info
->dr_changed_bp
, 8),
261 phex (info
->dr_changed_wp
, 8));
264 dr_changed_ptr
= is_watchpoint
? &info
->dr_changed_wp
265 : &info
->dr_changed_bp
;
266 dr_changed
= *dr_changed_ptr
;
269 && (idx
<= (is_watchpoint
? aarch64_num_wp_regs
270 : aarch64_num_bp_regs
)));
272 /* The actual update is done later just before resuming the lwp,
273 we just mark that one register pair needs updating. */
274 DR_MARK_N_CHANGED (dr_changed
, idx
);
275 *dr_changed_ptr
= dr_changed
;
277 /* If the lwp isn't stopped, force it to momentarily pause, so
278 we can update its debug registers. */
279 if (!lwp_is_stopped (lwp
))
280 linux_stop_lwp (lwp
);
284 debug_printf ("\tOn exit:\n\ttid%d, dr_changed_bp=0x%s, "
285 "dr_changed_wp=0x%s\n", tid
,
286 phex (info
->dr_changed_bp
, 8),
287 phex (info
->dr_changed_wp
, 8));
293 /* Notify each thread that their IDXth breakpoint/watchpoint register
294 pair needs to be updated. The message will be recorded in each
295 thread's arch-specific data area, the actual updating will be done
296 when the thread is resumed. */
299 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state
*state
,
300 int is_watchpoint
, unsigned int idx
)
302 struct aarch64_dr_update_callback_param param
;
303 ptid_t pid_ptid
= pid_to_ptid (ptid_get_pid (current_lwp_ptid ()));
305 param
.is_watchpoint
= is_watchpoint
;
308 iterate_over_lwps (pid_ptid
, debug_reg_change_callback
, (void *) ¶m
);
311 /* Record the insertion of one breakpoint/watchpoint, as represented
312 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
315 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state
*state
,
316 enum target_hw_bp_type type
,
317 CORE_ADDR addr
, int len
)
319 int i
, idx
, num_regs
, is_watchpoint
;
320 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
321 CORE_ADDR
*dr_addr_p
;
323 /* Set up state pointers. */
324 is_watchpoint
= (type
!= hw_execute
);
325 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
328 num_regs
= aarch64_num_wp_regs
;
329 dr_addr_p
= state
->dr_addr_wp
;
330 dr_ctrl_p
= state
->dr_ctrl_wp
;
331 dr_ref_count
= state
->dr_ref_count_wp
;
335 num_regs
= aarch64_num_bp_regs
;
336 dr_addr_p
= state
->dr_addr_bp
;
337 dr_ctrl_p
= state
->dr_ctrl_bp
;
338 dr_ref_count
= state
->dr_ref_count_bp
;
341 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
343 /* Find an existing or free register in our cache. */
345 for (i
= 0; i
< num_regs
; ++i
)
347 if ((dr_ctrl_p
[i
] & 1) == 0)
349 gdb_assert (dr_ref_count
[i
] == 0);
351 /* no break; continue hunting for an exising one. */
353 else if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
355 gdb_assert (dr_ref_count
[i
] != 0);
365 /* Update our cache. */
366 if ((dr_ctrl_p
[idx
] & 1) == 0)
369 dr_addr_p
[idx
] = addr
;
370 dr_ctrl_p
[idx
] = ctrl
;
371 dr_ref_count
[idx
] = 1;
372 /* Notify the change. */
373 aarch64_notify_debug_reg_change (state
, is_watchpoint
, idx
);
384 /* Record the removal of one breakpoint/watchpoint, as represented by
385 ADDR and CTRL, in the process' arch-specific data area *STATE. */
388 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state
*state
,
389 enum target_hw_bp_type type
,
390 CORE_ADDR addr
, int len
)
392 int i
, num_regs
, is_watchpoint
;
393 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
394 CORE_ADDR
*dr_addr_p
;
396 /* Set up state pointers. */
397 is_watchpoint
= (type
!= hw_execute
);
398 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
401 num_regs
= aarch64_num_wp_regs
;
402 dr_addr_p
= state
->dr_addr_wp
;
403 dr_ctrl_p
= state
->dr_ctrl_wp
;
404 dr_ref_count
= state
->dr_ref_count_wp
;
408 num_regs
= aarch64_num_bp_regs
;
409 dr_addr_p
= state
->dr_addr_bp
;
410 dr_ctrl_p
= state
->dr_ctrl_bp
;
411 dr_ref_count
= state
->dr_ref_count_bp
;
414 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
416 /* Find the entry that matches the ADDR and CTRL. */
417 for (i
= 0; i
< num_regs
; ++i
)
418 if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
420 gdb_assert (dr_ref_count
[i
] != 0);
428 /* Clear our cache. */
429 if (--dr_ref_count
[i
] == 0)
431 /* Clear the enable bit. */
435 /* Notify the change. */
436 aarch64_notify_debug_reg_change (state
, is_watchpoint
, i
);
443 aarch64_handle_breakpoint (enum target_hw_bp_type type
, CORE_ADDR addr
,
444 int len
, int is_insert
,
445 struct aarch64_debug_reg_state
*state
)
447 /* The hardware breakpoint on AArch64 should always be 4-byte
449 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr
, len
))
453 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
455 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
458 /* This is essentially the same as aarch64_handle_breakpoint, apart
459 from that it is an aligned watchpoint to be handled. */
462 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type
,
463 CORE_ADDR addr
, int len
, int is_insert
,
464 struct aarch64_debug_reg_state
*state
)
467 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
469 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
472 /* Insert/remove unaligned watchpoint by calling
473 aarch64_align_watchpoint repeatedly until the whole watched region,
474 as represented by ADDR and LEN, has been properly aligned and ready
475 to be written to one or more hardware watchpoint registers.
476 IS_INSERT indicates whether this is an insertion or a deletion.
477 Return 0 if succeed. */
480 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type
,
481 CORE_ADDR addr
, int len
, int is_insert
,
482 struct aarch64_debug_reg_state
*state
)
486 CORE_ADDR aligned_addr
;
487 int aligned_len
, ret
;
489 aarch64_align_watchpoint (addr
, len
, &aligned_addr
, &aligned_len
,
493 ret
= aarch64_dr_state_insert_one_point (state
, type
, aligned_addr
,
496 ret
= aarch64_dr_state_remove_one_point (state
, type
, aligned_addr
,
500 debug_printf ("handle_unaligned_watchpoint: is_insert: %d\n"
502 "aligned_addr: %s, aligned_len: %d\n"
504 "next_addr: %s, next_len: %d\n",
505 is_insert
, core_addr_to_string_nz (aligned_addr
),
506 aligned_len
, core_addr_to_string_nz (addr
), len
);
516 aarch64_handle_watchpoint (enum target_hw_bp_type type
, CORE_ADDR addr
,
517 int len
, int is_insert
,
518 struct aarch64_debug_reg_state
*state
)
520 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr
, len
))
521 return aarch64_handle_aligned_watchpoint (type
, addr
, len
, is_insert
,
524 return aarch64_handle_unaligned_watchpoint (type
, addr
, len
, is_insert
,
528 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
529 registers with data from *STATE. */
532 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state
*state
,
533 int tid
, int watchpoint
)
537 struct user_hwdebug_state regs
;
538 const CORE_ADDR
*addr
;
539 const unsigned int *ctrl
;
541 memset (®s
, 0, sizeof (regs
));
542 iov
.iov_base
= ®s
;
543 count
= watchpoint
? aarch64_num_wp_regs
: aarch64_num_bp_regs
;
544 addr
= watchpoint
? state
->dr_addr_wp
: state
->dr_addr_bp
;
545 ctrl
= watchpoint
? state
->dr_ctrl_wp
: state
->dr_ctrl_bp
;
548 iov
.iov_len
= (offsetof (struct user_hwdebug_state
, dbg_regs
[count
- 1])
549 + sizeof (regs
.dbg_regs
[count
- 1]));
551 for (i
= 0; i
< count
; i
++)
553 regs
.dbg_regs
[i
].addr
= addr
[i
];
554 regs
.dbg_regs
[i
].ctrl
= ctrl
[i
];
557 if (ptrace (PTRACE_SETREGSET
, tid
,
558 watchpoint
? NT_ARM_HW_WATCH
: NT_ARM_HW_BREAK
,
560 error (_("Unexpected error setting hardware debug registers"));
563 /* Print the values of the cached breakpoint/watchpoint registers. */
566 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state
*state
,
567 const char *func
, CORE_ADDR addr
,
568 int len
, enum target_hw_bp_type type
)
572 debug_printf ("%s", func
);
574 debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
575 (unsigned long) addr
, len
,
576 type
== hw_write
? "hw-write-watchpoint"
577 : (type
== hw_read
? "hw-read-watchpoint"
578 : (type
== hw_access
? "hw-access-watchpoint"
579 : (type
== hw_execute
? "hw-breakpoint"
581 debug_printf (":\n");
583 debug_printf ("\tBREAKPOINTs:\n");
584 for (i
= 0; i
< aarch64_num_bp_regs
; i
++)
585 debug_printf ("\tBP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
586 i
, core_addr_to_string_nz (state
->dr_addr_bp
[i
]),
587 state
->dr_ctrl_bp
[i
], state
->dr_ref_count_bp
[i
]);
589 debug_printf ("\tWATCHPOINTs:\n");
590 for (i
= 0; i
< aarch64_num_wp_regs
; i
++)
591 debug_printf ("\tWP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
592 i
, core_addr_to_string_nz (state
->dr_addr_wp
[i
]),
593 state
->dr_ctrl_wp
[i
], state
->dr_ref_count_wp
[i
]);
596 /* Get the hardware debug register capacity information from the
597 process represented by TID. */
600 aarch64_linux_get_debug_reg_capacity (int tid
)
603 struct user_hwdebug_state dreg_state
;
605 iov
.iov_base
= &dreg_state
;
606 iov
.iov_len
= sizeof (dreg_state
);
608 /* Get hardware watchpoint register info. */
609 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_WATCH
, &iov
) == 0
610 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
612 aarch64_num_wp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
613 if (aarch64_num_wp_regs
> AARCH64_HWP_MAX_NUM
)
615 warning (_("Unexpected number of hardware watchpoint registers"
616 " reported by ptrace, got %d, expected %d."),
617 aarch64_num_wp_regs
, AARCH64_HWP_MAX_NUM
);
618 aarch64_num_wp_regs
= AARCH64_HWP_MAX_NUM
;
623 warning (_("Unable to determine the number of hardware watchpoints"
625 aarch64_num_wp_regs
= 0;
628 /* Get hardware breakpoint register info. */
629 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_BREAK
, &iov
) == 0
630 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
632 aarch64_num_bp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
633 if (aarch64_num_bp_regs
> AARCH64_HBP_MAX_NUM
)
635 warning (_("Unexpected number of hardware breakpoint registers"
636 " reported by ptrace, got %d, expected %d."),
637 aarch64_num_bp_regs
, AARCH64_HBP_MAX_NUM
);
638 aarch64_num_bp_regs
= AARCH64_HBP_MAX_NUM
;
643 warning (_("Unable to determine the number of hardware breakpoints"
645 aarch64_num_bp_regs
= 0;