1 /* Target-dependent code for the NDS32 architecture, for GDB.
3 Copyright (C) 2013-2016 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
29 #include "reggroups.h"
32 #include "arch-utils.h"
35 #include "user-regs.h"
37 #include "dwarf2-frame.h"
39 #include "target-descriptions.h"
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
46 #include "features/nds32.c"
48 /* Simple macros for instruction analysis. */
49 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
58 extern void _initialize_nds32_tdep (void);
60 /* Use an invalid address value as 'not available' marker. */
61 enum { REG_UNAVAIL
= (CORE_ADDR
) -1 };
63 /* Use an impossible value as invalid offset. */
64 enum { INVALID_OFFSET
= (CORE_ADDR
) -1 };
66 /* Instruction groups for NDS32 epilogue analysis. */
69 /* Instructions used everywhere, not only in epilogue. */
71 /* Instructions used to reset sp for local vars, arguments, etc. */
73 /* Instructions used to recover saved regs and to recover padding. */
75 /* Instructions used to return to the caller. */
77 /* Instructions used to recover saved regs and to return to the caller. */
81 static const char *const nds32_register_names
[] =
84 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
85 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
86 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
87 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
92 static const char *const nds32_fdr_register_names
[] =
94 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
95 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
96 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
97 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
100 static const char *const nds32_fsr_register_names
[] =
102 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
103 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
104 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
105 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
108 /* The number of registers for four FPU configuration options. */
109 const int num_fdr_map
[] = { 4, 8, 16, 32 };
110 const int num_fsr_map
[] = { 8, 16, 32, 32 };
112 /* Aliases for registers. */
117 } nds32_register_aliases
[] =
133 {"cr6", "fucop_exist"},
150 {"ir14", "int_mask"},
151 {"ir15", "int_pend"},
155 {"ir19", "int_ctrl"},
157 {"ir21", "sp_priv1"},
159 {"ir23", "sp_priv2"},
161 {"ir25", "sp_priv3"},
162 {"ir26", "int_mask2"},
163 {"ir27", "int_pend2"},
164 {"ir28", "int_pri2"},
165 {"ir29", "int_trigger"},
175 {"mr8", "cache_ctl"},
176 {"mr9", "hsmp_saddr"},
177 {"mr10", "hsmp_eaddr"},
178 {"mr11", "bg_region"},
229 {"hspr0", "hsp_ctl"},
230 {"hspr1", "sp_bound"},
231 {"hspr2", "sp_bound_priv"},
239 {"dmar0", "dma_cfg"},
240 {"dmar1", "dma_gcsw"},
241 {"dmar2", "dma_chnsel"},
242 {"dmar3", "dma_act"},
243 {"dmar4", "dma_setup"},
244 {"dmar5", "dma_isaddr"},
245 {"dmar6", "dma_esaddr"},
246 {"dmar7", "dma_tcnt"},
247 {"dmar8", "dma_status"},
248 {"dmar9", "dma_2dset"},
249 {"dmar10", "dma_2dsctl"},
250 {"dmar11", "dma_rcnt"},
251 {"dmar12", "dma_hstatus"},
253 {"racr0", "prusr_acc_ctl"},
254 {"fucpr", "fucop_ctl"},
257 {"idr1", "misc_ctl"},
258 {"idr2", "ecc_misc"},
263 {"secur3", "p_isign"},
266 /* Value of a register alias. BATON is the regnum of the corresponding
269 static struct value
*
270 value_of_nds32_reg (struct frame_info
*frame
, const void *baton
)
272 return value_of_register ((int) (intptr_t) baton
, frame
);
275 /* Implement the "frame_align" gdbarch method. */
278 nds32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
280 /* 8-byte aligned. */
281 return align_down (sp
, 8);
284 /* Implement the "breakpoint_from_pc" gdbarch method.
286 Use the program counter to determine the contents and size of a
287 breakpoint instruction. Return a pointer to a string of bytes that
288 encode a breakpoint instruction, store the length of the string in
289 *LENPTR and optionally adjust *PCPTR to point to the correct memory
290 location for inserting the breakpoint. */
292 static const gdb_byte
*
293 nds32_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
296 /* The same insn machine code is used for little-endian and big-endian. */
297 static const gdb_byte break_insn
[] = { 0xEA, 0x00 };
299 *lenptr
= sizeof (break_insn
);
303 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
306 nds32_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
308 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
310 const int FDR
= FSR
+ 32;
312 if (num
>= 0 && num
< 32)
314 /* General-purpose registers (R0 - R31). */
317 else if (num
>= FSR
&& num
< FSR
+ 32)
319 /* Single precision floating-point registers (FS0 - FS31). */
320 return num
- FSR
+ tdep
->fs0_regnum
;
322 else if (num
>= FDR
&& num
< FDR
+ 32)
324 /* Double precision floating-point registers (FD0 - FD31). */
325 return num
- FDR
+ NDS32_FD0_REGNUM
;
328 /* No match, return a inaccessible register number. */
332 /* NDS32 register groups. */
333 static struct reggroup
*nds32_cr_reggroup
;
334 static struct reggroup
*nds32_ir_reggroup
;
335 static struct reggroup
*nds32_mr_reggroup
;
336 static struct reggroup
*nds32_dr_reggroup
;
337 static struct reggroup
*nds32_pfr_reggroup
;
338 static struct reggroup
*nds32_hspr_reggroup
;
339 static struct reggroup
*nds32_dmar_reggroup
;
340 static struct reggroup
*nds32_racr_reggroup
;
341 static struct reggroup
*nds32_idr_reggroup
;
342 static struct reggroup
*nds32_secur_reggroup
;
345 nds32_init_reggroups (void)
347 nds32_cr_reggroup
= reggroup_new ("cr", USER_REGGROUP
);
348 nds32_ir_reggroup
= reggroup_new ("ir", USER_REGGROUP
);
349 nds32_mr_reggroup
= reggroup_new ("mr", USER_REGGROUP
);
350 nds32_dr_reggroup
= reggroup_new ("dr", USER_REGGROUP
);
351 nds32_pfr_reggroup
= reggroup_new ("pfr", USER_REGGROUP
);
352 nds32_hspr_reggroup
= reggroup_new ("hspr", USER_REGGROUP
);
353 nds32_dmar_reggroup
= reggroup_new ("dmar", USER_REGGROUP
);
354 nds32_racr_reggroup
= reggroup_new ("racr", USER_REGGROUP
);
355 nds32_idr_reggroup
= reggroup_new ("idr", USER_REGGROUP
);
356 nds32_secur_reggroup
= reggroup_new ("secur", USER_REGGROUP
);
360 nds32_add_reggroups (struct gdbarch
*gdbarch
)
362 /* Add pre-defined register groups. */
363 reggroup_add (gdbarch
, general_reggroup
);
364 reggroup_add (gdbarch
, float_reggroup
);
365 reggroup_add (gdbarch
, system_reggroup
);
366 reggroup_add (gdbarch
, all_reggroup
);
367 reggroup_add (gdbarch
, save_reggroup
);
368 reggroup_add (gdbarch
, restore_reggroup
);
370 /* Add NDS32 register groups. */
371 reggroup_add (gdbarch
, nds32_cr_reggroup
);
372 reggroup_add (gdbarch
, nds32_ir_reggroup
);
373 reggroup_add (gdbarch
, nds32_mr_reggroup
);
374 reggroup_add (gdbarch
, nds32_dr_reggroup
);
375 reggroup_add (gdbarch
, nds32_pfr_reggroup
);
376 reggroup_add (gdbarch
, nds32_hspr_reggroup
);
377 reggroup_add (gdbarch
, nds32_dmar_reggroup
);
378 reggroup_add (gdbarch
, nds32_racr_reggroup
);
379 reggroup_add (gdbarch
, nds32_idr_reggroup
);
380 reggroup_add (gdbarch
, nds32_secur_reggroup
);
383 /* Implement the "register_reggroup_p" gdbarch method. */
386 nds32_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
387 struct reggroup
*reggroup
)
389 const char *reg_name
;
390 const char *group_name
;
393 if (reggroup
== all_reggroup
)
396 /* General reggroup contains only GPRs and PC. */
397 if (reggroup
== general_reggroup
)
398 return regnum
<= NDS32_PC_REGNUM
;
400 if (reggroup
== float_reggroup
|| reggroup
== save_reggroup
401 || reggroup
== restore_reggroup
)
403 ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
407 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
410 if (reggroup
== system_reggroup
)
411 return (regnum
> NDS32_PC_REGNUM
)
412 && !nds32_register_reggroup_p (gdbarch
, regnum
, float_reggroup
);
414 /* The NDS32 reggroup contains registers whose name is prefixed
416 reg_name
= gdbarch_register_name (gdbarch
, regnum
);
417 group_name
= reggroup_name (reggroup
);
418 return !strncmp (reg_name
, group_name
, strlen (group_name
));
421 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
424 nds32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
426 regnum
-= gdbarch_num_regs (gdbarch
);
428 /* Currently, only FSRs could be defined as pseudo registers. */
429 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
430 return arch_float_type (gdbarch
, -1, "builtin_type_ieee_single",
431 floatformats_ieee_single
);
433 warning (_("Unknown nds32 pseudo register %d."), regnum
);
437 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
440 nds32_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
442 regnum
-= gdbarch_num_regs (gdbarch
);
444 /* Currently, only FSRs could be defined as pseudo registers. */
445 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
446 return nds32_fsr_register_names
[regnum
];
448 warning (_("Unknown nds32 pseudo register %d."), regnum
);
452 /* Implement the "pseudo_register_read" gdbarch method. */
454 static enum register_status
455 nds32_pseudo_register_read (struct gdbarch
*gdbarch
,
456 struct regcache
*regcache
, int regnum
,
459 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
461 int offset
, fdr_regnum
;
462 enum register_status status
= REG_UNKNOWN
;
465 if (tdep
->fpu_freg
== -1 || tdep
->use_pseudo_fsrs
== 0)
468 regnum
-= gdbarch_num_regs (gdbarch
);
470 /* Currently, only FSRs could be defined as pseudo registers. */
471 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
473 /* fs0 is always the most significant half of fd0. */
474 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
475 offset
= (regnum
& 1) ? 4 : 0;
477 offset
= (regnum
& 1) ? 0 : 4;
479 fdr_regnum
= NDS32_FD0_REGNUM
+ (regnum
>> 1);
480 status
= regcache_raw_read (regcache
, fdr_regnum
, reg_buf
);
481 if (status
== REG_VALID
)
482 memcpy (buf
, reg_buf
+ offset
, 4);
488 /* Implement the "pseudo_register_write" gdbarch method. */
491 nds32_pseudo_register_write (struct gdbarch
*gdbarch
,
492 struct regcache
*regcache
, int regnum
,
495 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
497 int offset
, fdr_regnum
;
500 if (tdep
->fpu_freg
== -1 || tdep
->use_pseudo_fsrs
== 0)
503 regnum
-= gdbarch_num_regs (gdbarch
);
505 /* Currently, only FSRs could be defined as pseudo registers. */
506 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
508 /* fs0 is always the most significant half of fd0. */
509 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
510 offset
= (regnum
& 1) ? 4 : 0;
512 offset
= (regnum
& 1) ? 0 : 4;
514 fdr_regnum
= NDS32_FD0_REGNUM
+ (regnum
>> 1);
515 regcache_raw_read (regcache
, fdr_regnum
, reg_buf
);
516 memcpy (reg_buf
+ offset
, buf
, 4);
517 regcache_raw_write (regcache
, fdr_regnum
, reg_buf
);
521 /* Helper function for NDS32 ABI. Return true if FPRs can be used
522 to pass function arguments and return value. */
525 nds32_abi_use_fpr (int elf_abi
)
527 return elf_abi
== E_NDS_ABI_V2FP_PLUS
;
530 /* Helper function for NDS32 ABI. Return true if GPRs and stack
531 can be used together to pass an argument. */
534 nds32_abi_split (int elf_abi
)
536 return elf_abi
== E_NDS_ABI_AABI
;
539 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
541 struct nds32_frame_cache
543 /* The previous frame's inner most stack address. Used as this
544 frame ID's stack_addr. */
547 /* The frame's base, optionally used by the high-level debug info. */
550 /* During prologue analysis, keep how far the SP and FP have been offset
551 from the start of the stack frame (as defined by the previous frame's
553 During epilogue analysis, keep how far the SP has been offset from the
554 current stack pointer. */
558 /* The address of the first instruction in this function. */
561 /* Saved registers. */
562 CORE_ADDR saved_regs
[NDS32_NUM_SAVED_REGS
];
565 /* Allocate and initialize a frame cache. */
567 static struct nds32_frame_cache
*
568 nds32_alloc_frame_cache (void)
570 struct nds32_frame_cache
*cache
;
573 cache
= FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache
);
575 /* Initialize fp_offset to check if FP is set in prologue. */
576 cache
->fp_offset
= INVALID_OFFSET
;
578 /* Saved registers. We initialize these to -1 since zero is a valid
580 for (i
= 0; i
< NDS32_NUM_SAVED_REGS
; i
++)
581 cache
->saved_regs
[i
] = REG_UNAVAIL
;
586 /* Helper function for instructions used to push multiple words. */
589 nds32_push_multiple_words (struct nds32_frame_cache
*cache
, int rb
, int re
,
592 CORE_ADDR sp_offset
= cache
->sp_offset
;
595 /* Check LP, GP, FP in enable4. */
596 for (i
= 1; i
<= 3; i
++)
598 if ((enable4
>> i
) & 0x1)
601 cache
->saved_regs
[NDS32_SP_REGNUM
- i
] = sp_offset
;
605 /* Skip case where re == rb == sp. */
606 if ((rb
< REG_FP
) && (re
< REG_FP
))
608 for (i
= re
; i
>= rb
; i
--)
611 cache
->saved_regs
[i
] = sp_offset
;
615 /* For sp, update the offset. */
616 cache
->sp_offset
= sp_offset
;
619 /* Analyze the instructions within the given address range. If CACHE
620 is non-NULL, fill it in. Return the first address beyond the given
621 address range. If CACHE is NULL, return the first address not
622 recognized as a prologue instruction. */
625 nds32_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
626 CORE_ADDR limit_pc
, struct nds32_frame_cache
*cache
)
628 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
629 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
630 /* Current scanning status. */
631 int in_prologue_bb
= 0;
633 uint32_t insn
, insn_len
;
635 for (; pc
< limit_pc
; pc
+= insn_len
)
637 insn
= read_memory_unsigned_integer (pc
, 4, BFD_ENDIAN_BIG
);
639 if ((insn
& 0x80000000) == 0)
641 /* 32-bit instruction */
644 if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_SP
, REG_SP
, 0))
646 /* addi $sp, $sp, imm15s */
647 int imm15s
= N32_IMM15S (insn
);
652 cache
->sp_offset
+= -imm15s
;
658 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_FP
, REG_SP
, 0))
660 /* addi $fp, $sp, imm15s */
661 int imm15s
= N32_IMM15S (insn
);
666 cache
->fp_offset
= cache
->sp_offset
- imm15s
;
672 else if ((insn
& ~(__MASK (19) << 6)) == N32_SMW_ADM
673 && N32_RA5 (insn
) == REG_SP
)
675 /* smw.adm Rb, [$sp], Re, enable4 */
677 nds32_push_multiple_words (cache
, N32_RT5 (insn
),
679 N32_LSMW_ENABLE4 (insn
));
683 else if (insn
== N32_ALU1 (ADD
, REG_SP
, REG_SP
, REG_TA
)
684 || insn
== N32_ALU1 (ADD
, REG_SP
, REG_TA
, REG_SP
))
686 /* add $sp, $sp, $ta */
687 /* add $sp, $ta, $sp */
691 cache
->sp_offset
+= -val_ta
;
697 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (MOVI
, REG_TA
, 0))
699 /* movi $ta, imm20s */
701 val_ta
= N32_IMM20S (insn
);
705 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (SETHI
, REG_TA
, 0))
707 /* sethi $ta, imm20u */
709 val_ta
= N32_IMM20U (insn
) << 12;
713 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ORI
, REG_TA
, REG_TA
, 0))
715 /* ori $ta, $ta, imm15u */
717 val_ta
|= N32_IMM15U (insn
);
721 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_TA
, REG_TA
, 0))
723 /* addi $ta, $ta, imm15s */
725 val_ta
+= N32_IMM15S (insn
);
729 if (insn
== N32_ALU1 (ADD
, REG_GP
, REG_TA
, REG_GP
)
730 || insn
== N32_ALU1 (ADD
, REG_GP
, REG_GP
, REG_TA
))
732 /* add $gp, $ta, $gp */
733 /* add $gp, $gp, $ta */
737 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (MOVI
, REG_GP
, 0))
739 /* movi $gp, imm20s */
743 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (SETHI
, REG_GP
, 0))
745 /* sethi $gp, imm20u */
749 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ORI
, REG_GP
, REG_GP
, 0))
751 /* ori $gp, $gp, imm15u */
757 /* Jump/Branch insns never appear in prologue basic block.
758 The loop can be escaped early when these insns are met. */
759 if (in_prologue_bb
== 1)
761 int op
= N32_OP6 (insn
);
764 || op
== N32_OP6_JREG
767 || op
== N32_OP6_BR3
)
772 if (abi_use_fpr
&& N32_OP6 (insn
) == N32_OP6_SDC
773 && __GF (insn
, 12, 3) == 0)
775 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
776 normal form (bit [12] == 0) is used. */
778 /* fsdi FDt, [$sp + (imm12s << 2)] */
779 if (N32_RA5 (insn
) == REG_SP
)
783 /* The optimizer might shove anything into the prologue, if
784 we build up cache (cache != NULL) from analyzing prologue,
785 we just skip what we don't recognize and analyze further to
786 make cache as complete as possible. However, if we skip
787 prologue, we'll stop immediately on unrecognized
794 /* 16-bit instruction */
799 if (CHOP_BITS (insn
, 10) == N16_TYPE10 (ADDI10S
, 0))
802 int imm10s
= N16_IMM10S (insn
);
807 cache
->sp_offset
+= -imm10s
;
813 else if (__GF (insn
, 7, 8) == N16_T25_PUSH25
)
818 int imm8u
= (insn
& 0x1f) << 3;
819 int re
= (insn
>> 5) & 0x3;
820 const int reg_map
[] = { 6, 8, 10, 14 };
822 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
823 nds32_push_multiple_words (cache
, 6, reg_map
[re
], 0xe);
825 /* Operation 2 -- sp = sp - (imm5u << 3) */
826 cache
->sp_offset
+= imm8u
;
832 else if (insn
== N16_TYPE5 (ADD5PC
, REG_GP
))
838 else if (CHOP_BITS (insn
, 5) == N16_TYPE55 (MOVI55
, REG_GP
, 0))
840 /* movi55 $gp, imm5s */
846 /* Jump/Branch insns never appear in prologue basic block.
847 The loop can be escaped early when these insns are met. */
848 if (in_prologue_bb
== 1)
850 uint32_t insn5
= CHOP_BITS (insn
, 5);
851 uint32_t insn8
= CHOP_BITS (insn
, 8);
852 uint32_t insn38
= CHOP_BITS (insn
, 11);
854 if (insn5
== N16_TYPE5 (JR5
, 0)
855 || insn5
== N16_TYPE5 (JRAL5
, 0)
856 || insn5
== N16_TYPE5 (RET5
, 0)
857 || insn8
== N16_TYPE8 (J8
, 0)
858 || insn8
== N16_TYPE8 (BEQZS8
, 0)
859 || insn8
== N16_TYPE8 (BNEZS8
, 0)
860 || insn38
== N16_TYPE38 (BEQZ38
, 0, 0)
861 || insn38
== N16_TYPE38 (BNEZ38
, 0, 0)
862 || insn38
== N16_TYPE38 (BEQS38
, 0, 0)
863 || insn38
== N16_TYPE38 (BNES38
, 0, 0))
868 /* The optimizer might shove anything into the prologue, if
869 we build up cache (cache != NULL) from analyzing prologue,
870 we just skip what we don't recognize and analyze further to
871 make cache as complete as possible. However, if we skip
872 prologue, we'll stop immediately on unrecognized
882 /* Implement the "skip_prologue" gdbarch method.
884 Find the end of function prologue. */
887 nds32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
889 CORE_ADDR func_addr
, limit_pc
;
891 /* See if we can determine the end of the prologue via the symbol table.
892 If so, then return either PC, or the PC after the prologue, whichever
894 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
896 CORE_ADDR post_prologue_pc
897 = skip_prologue_using_sal (gdbarch
, func_addr
);
898 if (post_prologue_pc
!= 0)
899 return std::max (pc
, post_prologue_pc
);
902 /* Can't determine prologue from the symbol table, need to examine
905 /* Find an upper limit on the function prologue using the debug
906 information. If the debug information could not be used to provide
907 that bound, then use an arbitrary large number as the upper bound. */
908 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
910 limit_pc
= pc
+ 128; /* Magic. */
912 /* Find the end of prologue. */
913 return nds32_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
916 /* Allocate and fill in *THIS_CACHE with information about the prologue of
917 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
918 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
920 static struct nds32_frame_cache
*
921 nds32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
923 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
924 struct nds32_frame_cache
*cache
;
925 CORE_ADDR current_pc
;
931 return (struct nds32_frame_cache
*) *this_cache
;
933 cache
= nds32_alloc_frame_cache ();
936 cache
->pc
= get_frame_func (this_frame
);
937 current_pc
= get_frame_pc (this_frame
);
938 nds32_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
);
940 /* Compute the previous frame's stack pointer (which is also the
941 frame's ID's stack address), and this frame's base pointer. */
942 if (cache
->fp_offset
!= INVALID_OFFSET
)
944 /* FP is set in prologue, so it can be used to calculate other info. */
945 this_base
= get_frame_register_unsigned (this_frame
, NDS32_FP_REGNUM
);
946 prev_sp
= this_base
+ cache
->fp_offset
;
950 this_base
= get_frame_register_unsigned (this_frame
, NDS32_SP_REGNUM
);
951 prev_sp
= this_base
+ cache
->sp_offset
;
954 cache
->prev_sp
= prev_sp
;
955 cache
->base
= this_base
;
957 /* Adjust all the saved registers such that they contain addresses
958 instead of offsets. */
959 for (i
= 0; i
< NDS32_NUM_SAVED_REGS
; i
++)
960 if (cache
->saved_regs
[i
] != REG_UNAVAIL
)
961 cache
->saved_regs
[i
] = cache
->prev_sp
- cache
->saved_regs
[i
];
966 /* Implement the "this_id" frame_unwind method.
968 Our frame ID for a normal frame is the current function's starting
969 PC and the caller's SP when we were called. */
972 nds32_frame_this_id (struct frame_info
*this_frame
,
973 void **this_cache
, struct frame_id
*this_id
)
975 struct nds32_frame_cache
*cache
= nds32_frame_cache (this_frame
, this_cache
);
977 /* This marks the outermost frame. */
978 if (cache
->prev_sp
== 0)
981 *this_id
= frame_id_build (cache
->prev_sp
, cache
->pc
);
984 /* Implement the "prev_register" frame_unwind method. */
986 static struct value
*
987 nds32_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
990 struct nds32_frame_cache
*cache
= nds32_frame_cache (this_frame
, this_cache
);
992 if (regnum
== NDS32_SP_REGNUM
)
993 return frame_unwind_got_constant (this_frame
, regnum
, cache
->prev_sp
);
995 /* The PC of the previous frame is stored in the LP register of
996 the current frame. */
997 if (regnum
== NDS32_PC_REGNUM
)
998 regnum
= NDS32_LP_REGNUM
;
1000 if (regnum
< NDS32_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != REG_UNAVAIL
)
1001 return frame_unwind_got_memory (this_frame
, regnum
,
1002 cache
->saved_regs
[regnum
]);
1004 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1007 static const struct frame_unwind nds32_frame_unwind
=
1010 default_frame_unwind_stop_reason
,
1011 nds32_frame_this_id
,
1012 nds32_frame_prev_register
,
1014 default_frame_sniffer
,
1017 /* Return the frame base address of *THIS_FRAME. */
1020 nds32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1022 struct nds32_frame_cache
*cache
= nds32_frame_cache (this_frame
, this_cache
);
1027 static const struct frame_base nds32_frame_base
=
1029 &nds32_frame_unwind
,
1030 nds32_frame_base_address
,
1031 nds32_frame_base_address
,
1032 nds32_frame_base_address
1035 /* Helper function for instructions used to pop multiple words. */
1038 nds32_pop_multiple_words (struct nds32_frame_cache
*cache
, int rb
, int re
,
1041 CORE_ADDR sp_offset
= cache
->sp_offset
;
1044 /* Skip case where re == rb == sp. */
1045 if ((rb
< REG_FP
) && (re
< REG_FP
))
1047 for (i
= rb
; i
<= re
; i
++)
1049 cache
->saved_regs
[i
] = sp_offset
;
1054 /* Check FP, GP, LP in enable4. */
1055 for (i
= 3; i
>= 1; i
--)
1057 if ((enable4
>> i
) & 0x1)
1059 cache
->saved_regs
[NDS32_SP_REGNUM
- i
] = sp_offset
;
1064 /* For sp, update the offset. */
1065 cache
->sp_offset
= sp_offset
;
1068 /* The instruction sequences in NDS32 epilogue are
1070 INSN_RESET_SP (optional)
1071 (If exists, this must be the first instruction in epilogue
1072 and the stack has not been destroyed.).
1073 INSN_RECOVER (optional).
1074 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1076 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1077 the necessary information will be recorded. */
1080 nds32_analyze_epilogue_insn32 (int abi_use_fpr
, uint32_t insn
,
1081 struct nds32_frame_cache
*cache
)
1083 if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_SP
, REG_SP
, 0)
1084 && N32_IMM15S (insn
) > 0)
1085 /* addi $sp, $sp, imm15s */
1086 return INSN_RESET_SP
;
1087 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_SP
, REG_FP
, 0)
1088 && N32_IMM15S (insn
) < 0)
1089 /* addi $sp, $fp, imm15s */
1090 return INSN_RESET_SP
;
1091 else if ((insn
& ~(__MASK (19) << 6)) == N32_LMW_BIM
1092 && N32_RA5 (insn
) == REG_SP
)
1094 /* lmw.bim Rb, [$sp], Re, enable4 */
1096 nds32_pop_multiple_words (cache
, N32_RT5 (insn
),
1097 N32_RB5 (insn
), N32_LSMW_ENABLE4 (insn
));
1099 return INSN_RECOVER
;
1101 else if (insn
== N32_JREG (JR
, 0, REG_LP
, 0, 1))
1104 else if (insn
== N32_ALU1 (ADD
, REG_SP
, REG_SP
, REG_TA
)
1105 || insn
== N32_ALU1 (ADD
, REG_SP
, REG_TA
, REG_SP
))
1106 /* add $sp, $sp, $ta */
1107 /* add $sp, $ta, $sp */
1108 return INSN_RESET_SP
;
1109 else if (abi_use_fpr
1110 && (insn
& ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP
)
1112 if (__GF (insn
, 12, 1) == 0)
1113 /* fldi FDt, [$sp + (imm12s << 2)] */
1114 return INSN_RECOVER
;
1117 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1118 int offset
= N32_IMM12S (insn
) << 2;
1120 if (offset
== 8 || offset
== 12)
1123 cache
->sp_offset
+= offset
;
1125 return INSN_RECOVER
;
1133 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1134 the necessary information will be recorded. */
1137 nds32_analyze_epilogue_insn16 (uint32_t insn
, struct nds32_frame_cache
*cache
)
1139 if (insn
== N16_TYPE5 (RET5
, REG_LP
))
1142 else if (CHOP_BITS (insn
, 10) == N16_TYPE10 (ADDI10S
, 0))
1145 int imm10s
= N16_IMM10S (insn
);
1150 cache
->sp_offset
+= imm10s
;
1152 return INSN_RECOVER
;
1155 else if (__GF (insn
, 7, 8) == N16_T25_POP25
)
1160 int imm8u
= (insn
& 0x1f) << 3;
1161 int re
= (insn
>> 5) & 0x3;
1162 const int reg_map
[] = { 6, 8, 10, 14 };
1164 /* Operation 1 -- sp = sp + (imm5u << 3) */
1165 cache
->sp_offset
+= imm8u
;
1167 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1168 nds32_pop_multiple_words (cache
, 6, reg_map
[re
], 0xe);
1171 /* Operation 3 -- ret $lp */
1172 return INSN_RECOVER_RETURN
;
1178 /* Analyze a reasonable amount of instructions from the given PC to find
1179 the instruction used to return to the caller. Return 1 if the 'return'
1180 instruction could be found, 0 otherwise.
1182 If CACHE is non-NULL, fill it in. */
1185 nds32_analyze_epilogue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1186 struct nds32_frame_cache
*cache
)
1188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1189 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1191 uint32_t insn
, insn_len
;
1192 int insn_type
= INSN_NORMAL
;
1199 for (; pc
< limit_pc
; pc
+= insn_len
)
1201 insn
= read_memory_unsigned_integer (pc
, 4, BFD_ENDIAN_BIG
);
1203 if ((insn
& 0x80000000) == 0)
1205 /* 32-bit instruction */
1208 insn_type
= nds32_analyze_epilogue_insn32 (abi_use_fpr
, insn
, cache
);
1209 if (insn_type
== INSN_RETURN
)
1211 else if (insn_type
== INSN_RECOVER
)
1216 /* 16-bit instruction */
1220 insn_type
= nds32_analyze_epilogue_insn16 (insn
, cache
);
1221 if (insn_type
== INSN_RETURN
|| insn_type
== INSN_RECOVER_RETURN
)
1223 else if (insn_type
== INSN_RECOVER
)
1227 /* Stop the scan if this is an unexpected instruction. */
1234 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1237 nds32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1240 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1241 int insn_type
= INSN_NORMAL
;
1245 insn
= read_memory_unsigned_integer (addr
, 4, BFD_ENDIAN_BIG
);
1247 if ((insn
& 0x80000000) == 0)
1249 /* 32-bit instruction */
1251 insn_type
= nds32_analyze_epilogue_insn32 (abi_use_fpr
, insn
, NULL
);
1255 /* 16-bit instruction */
1258 insn_type
= nds32_analyze_epilogue_insn16 (insn
, NULL
);
1261 if (insn_type
== INSN_NORMAL
|| insn_type
== INSN_RESET_SP
)
1264 /* Search the required 'return' instruction within the following reasonable
1266 ret_found
= nds32_analyze_epilogue (gdbarch
, addr
, NULL
);
1270 /* Scan backwards to make sure that the last instruction has adjusted
1271 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1272 just a heuristic, so the false positives will be acceptable. */
1273 insn
= read_memory_unsigned_integer (addr
- 2, 4, BFD_ENDIAN_BIG
);
1275 /* Only 16-bit instructions are possible at addr - 2. */
1276 if ((insn
& 0x80000000) != 0)
1278 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1280 insn_type
= nds32_analyze_epilogue_insn16 (insn
>> 16, NULL
);
1281 if (insn_type
== INSN_RECOVER
)
1285 insn
= read_memory_unsigned_integer (addr
- 4, 4, BFD_ENDIAN_BIG
);
1287 /* If this is a 16-bit instruction at addr - 4, then there must be another
1288 16-bit instruction at addr - 2, so only 32-bit instructions need to
1289 be analyzed here. */
1290 if ((insn
& 0x80000000) == 0)
1292 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1294 insn_type
= nds32_analyze_epilogue_insn32 (abi_use_fpr
, insn
, NULL
);
1295 if (insn_type
== INSN_RECOVER
|| insn_type
== INSN_RESET_SP
)
1302 /* Implement the "sniffer" frame_unwind method. */
1305 nds32_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1306 struct frame_info
*this_frame
, void **this_cache
)
1308 if (frame_relative_level (this_frame
) == 0)
1309 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame
),
1310 get_frame_pc (this_frame
));
1315 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1316 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1317 allocated. Return a pointer to the current nds32_frame_cache in
1320 static struct nds32_frame_cache
*
1321 nds32_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1323 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1324 struct nds32_frame_cache
*cache
;
1325 CORE_ADDR current_pc
, current_sp
;
1329 return (struct nds32_frame_cache
*) *this_cache
;
1331 cache
= nds32_alloc_frame_cache ();
1332 *this_cache
= cache
;
1334 cache
->pc
= get_frame_func (this_frame
);
1335 current_pc
= get_frame_pc (this_frame
);
1336 nds32_analyze_epilogue (gdbarch
, current_pc
, cache
);
1338 current_sp
= get_frame_register_unsigned (this_frame
, NDS32_SP_REGNUM
);
1339 cache
->prev_sp
= current_sp
+ cache
->sp_offset
;
1341 /* Adjust all the saved registers such that they contain addresses
1342 instead of offsets. */
1343 for (i
= 0; i
< NDS32_NUM_SAVED_REGS
; i
++)
1344 if (cache
->saved_regs
[i
] != REG_UNAVAIL
)
1345 cache
->saved_regs
[i
] = current_sp
+ cache
->saved_regs
[i
];
1350 /* Implement the "this_id" frame_unwind method. */
1353 nds32_epilogue_frame_this_id (struct frame_info
*this_frame
,
1354 void **this_cache
, struct frame_id
*this_id
)
1356 struct nds32_frame_cache
*cache
1357 = nds32_epilogue_frame_cache (this_frame
, this_cache
);
1359 /* This marks the outermost frame. */
1360 if (cache
->prev_sp
== 0)
1363 *this_id
= frame_id_build (cache
->prev_sp
, cache
->pc
);
1366 /* Implement the "prev_register" frame_unwind method. */
1368 static struct value
*
1369 nds32_epilogue_frame_prev_register (struct frame_info
*this_frame
,
1370 void **this_cache
, int regnum
)
1372 struct nds32_frame_cache
*cache
1373 = nds32_epilogue_frame_cache (this_frame
, this_cache
);
1375 if (regnum
== NDS32_SP_REGNUM
)
1376 return frame_unwind_got_constant (this_frame
, regnum
, cache
->prev_sp
);
1378 /* The PC of the previous frame is stored in the LP register of
1379 the current frame. */
1380 if (regnum
== NDS32_PC_REGNUM
)
1381 regnum
= NDS32_LP_REGNUM
;
1383 if (regnum
< NDS32_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != REG_UNAVAIL
)
1384 return frame_unwind_got_memory (this_frame
, regnum
,
1385 cache
->saved_regs
[regnum
]);
1387 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1390 static const struct frame_unwind nds32_epilogue_frame_unwind
=
1393 default_frame_unwind_stop_reason
,
1394 nds32_epilogue_frame_this_id
,
1395 nds32_epilogue_frame_prev_register
,
1397 nds32_epilogue_frame_sniffer
1400 /* Implement the "dummy_id" gdbarch method. */
1402 static struct frame_id
1403 nds32_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1405 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
, NDS32_SP_REGNUM
);
1407 return frame_id_build (sp
, get_frame_pc (this_frame
));
1410 /* Implement the "unwind_pc" gdbarch method. */
1413 nds32_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1415 return frame_unwind_register_unsigned (next_frame
, NDS32_PC_REGNUM
);
1418 /* Implement the "unwind_sp" gdbarch method. */
1421 nds32_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1423 return frame_unwind_register_unsigned (next_frame
, NDS32_SP_REGNUM
);
1426 /* Floating type and struct type that has only one floating type member
1427 can pass value using FPU registers (when FPU ABI is used). */
1430 nds32_check_calling_use_fpr (struct type
*type
)
1433 enum type_code typecode
;
1438 t
= check_typedef (t
);
1439 typecode
= TYPE_CODE (t
);
1440 if (typecode
!= TYPE_CODE_STRUCT
)
1442 else if (TYPE_NFIELDS (t
) != 1)
1445 t
= TYPE_FIELD_TYPE (t
, 0);
1448 return typecode
== TYPE_CODE_FLT
;
1451 /* Return the alignment (in bytes) of the given type. */
1454 nds32_type_align (struct type
*type
)
1460 type
= check_typedef (type
);
1461 switch (TYPE_CODE (type
))
1464 /* Should never happen. */
1465 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1469 case TYPE_CODE_ENUM
:
1473 case TYPE_CODE_RANGE
:
1475 case TYPE_CODE_CHAR
:
1476 case TYPE_CODE_BOOL
:
1477 return TYPE_LENGTH (type
);
1479 case TYPE_CODE_ARRAY
:
1480 case TYPE_CODE_COMPLEX
:
1481 return nds32_type_align (TYPE_TARGET_TYPE (type
));
1483 case TYPE_CODE_STRUCT
:
1484 case TYPE_CODE_UNION
:
1486 for (n
= 0; n
< TYPE_NFIELDS (type
); n
++)
1488 falign
= nds32_type_align (TYPE_FIELD_TYPE (type
, n
));
1496 /* Implement the "push_dummy_call" gdbarch method. */
1499 nds32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1500 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1501 int nargs
, struct value
**args
, CORE_ADDR sp
,
1502 int struct_return
, CORE_ADDR struct_addr
)
1504 const int REND
= 6; /* End for register offset. */
1505 int goff
= 0; /* Current gpr offset for argument. */
1506 int foff
= 0; /* Current fpr offset for argument. */
1507 int soff
= 0; /* Current stack offset for argument. */
1510 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1511 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1512 struct type
*func_type
= value_type (function
);
1513 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1514 int abi_split
= nds32_abi_split (tdep
->elf_abi
);
1516 /* Set the return address. For the NDS32, the return breakpoint is
1517 always at BP_ADDR. */
1518 regcache_cooked_write_unsigned (regcache
, NDS32_LP_REGNUM
, bp_addr
);
1520 /* If STRUCT_RETURN is true, then the struct return address (in
1521 STRUCT_ADDR) will consume the first argument-passing register.
1522 Both adjust the register count and store that value. */
1525 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
, struct_addr
);
1529 /* Now make sure there's space on the stack */
1530 for (i
= 0; i
< nargs
; i
++)
1532 struct type
*type
= value_type (args
[i
]);
1533 int align
= nds32_type_align (type
);
1535 /* If align is zero, it may be an empty struct.
1536 Just ignore the argument of empty struct. */
1540 sp
-= TYPE_LENGTH (type
);
1541 sp
= align_down (sp
, align
);
1544 /* Stack must be 8-byte aligned. */
1545 sp
= align_down (sp
, 8);
1548 for (i
= 0; i
< nargs
; i
++)
1550 const gdb_byte
*val
;
1553 int calling_use_fpr
;
1556 type
= value_type (args
[i
]);
1557 calling_use_fpr
= nds32_check_calling_use_fpr (type
);
1558 len
= TYPE_LENGTH (type
);
1559 align
= nds32_type_align (type
);
1560 val
= value_contents (args
[i
]);
1562 /* The size of a composite type larger than 4 bytes will be rounded
1563 up to the nearest multiple of 4. */
1565 len
= align_up (len
, 4);
1567 /* Variadic functions are handled differently between AABI and ABI2FP+.
1569 For AABI, the caller pushes arguments in registers, callee stores
1570 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1571 Therefore, we don't have to handle variadic functions specially.
1573 For ABI2FP+, the caller pushes only named arguments in registers
1574 and pushes all unnamed arguments in stack. */
1576 if (abi_use_fpr
&& TYPE_VARARGS (func_type
)
1577 && i
>= TYPE_NFIELDS (func_type
))
1580 /* Try to use FPRs to pass arguments only when
1581 1. The program is built using toolchain with FPU support.
1582 2. The type of this argument can use FPR to pass value. */
1583 use_fpr
= abi_use_fpr
&& calling_use_fpr
;
1587 if (tdep
->fpu_freg
== -1)
1590 /* Adjust alignment. */
1591 if ((align
>> 2) > 0)
1592 foff
= align_up (foff
, align
>> 2);
1599 regcache_cooked_write (regcache
,
1600 tdep
->fs0_regnum
+ foff
, val
);
1604 regcache_cooked_write (regcache
,
1605 NDS32_FD0_REGNUM
+ (foff
>> 1), val
);
1610 internal_error (__FILE__
, __LINE__
,
1611 "Do not know how to handle %d-byte double.\n",
1621 When passing arguments using GPRs,
1623 * A composite type not larger than 4 bytes is passed in $rN.
1624 The format is as if the value is loaded with load instruction
1625 of corresponding size (e.g., LB, LH, LW).
1634 * Otherwise, a composite type is passed in consecutive registers.
1635 The size is rounded up to the nearest multiple of 4.
1636 The successive registers hold the parts of the argument as if
1637 were loaded using lmw instructions.
1643 LITTLE: [d c b a] [x x x e]
1644 BIG: [a b c d] [e x x x]
1647 /* Adjust alignment. */
1648 if ((align
>> 2) > 0)
1649 goff
= align_up (goff
, align
>> 2);
1651 if (len
<= (REND
- goff
) * 4)
1653 /* This argument can be passed wholly via GPRs. */
1656 regval
= extract_unsigned_integer (val
, (len
> 4) ? 4 : len
,
1658 regcache_cooked_write_unsigned (regcache
,
1659 NDS32_R0_REGNUM
+ goff
,
1669 /* Some parts of this argument can be passed via GPRs. */
1672 regval
= extract_unsigned_integer (val
, (len
> 4) ? 4 : len
,
1674 regcache_cooked_write_unsigned (regcache
,
1675 NDS32_R0_REGNUM
+ goff
,
1686 When pushing (split parts of) an argument into stack,
1688 * A composite type not larger than 4 bytes is copied to different
1690 In little-endian, the first byte of this argument is aligned
1691 at the low address of the next free word.
1692 In big-endian, the last byte of this argument is aligned
1693 at the high address of the next free word.
1704 /* Adjust alignment. */
1705 soff
= align_up (soff
, align
);
1709 int rlen
= (len
> 4) ? 4 : len
;
1711 if (byte_order
== BFD_ENDIAN_BIG
)
1712 write_memory (sp
+ soff
+ 4 - rlen
, val
, rlen
);
1714 write_memory (sp
+ soff
, val
, rlen
);
1722 /* Finally, update the SP register. */
1723 regcache_cooked_write_unsigned (regcache
, NDS32_SP_REGNUM
, sp
);
1728 /* If use_fpr, but no floating-point register exists,
1729 then it is an error. */
1730 error (_("Fail to call. FPU registers are required."));
1733 /* Read, for architecture GDBARCH, a function return value of TYPE
1734 from REGCACHE, and copy that into VALBUF. */
1737 nds32_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1738 struct regcache
*regcache
, gdb_byte
*valbuf
)
1740 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1741 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1742 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1743 int calling_use_fpr
;
1746 calling_use_fpr
= nds32_check_calling_use_fpr (type
);
1747 len
= TYPE_LENGTH (type
);
1749 if (abi_use_fpr
&& calling_use_fpr
)
1752 regcache_cooked_read (regcache
, tdep
->fs0_regnum
, valbuf
);
1754 regcache_cooked_read (regcache
, NDS32_FD0_REGNUM
, valbuf
);
1756 internal_error (__FILE__
, __LINE__
,
1757 _("Cannot extract return value of %d bytes "
1758 "long floating-point."), len
);
1763 When returning result,
1765 * A composite type not larger than 4 bytes is returned in $r0.
1766 The format is as if the result is loaded with load instruction
1767 of corresponding size (e.g., LB, LH, LW).
1776 * Otherwise, a composite type not larger than 8 bytes is returned
1778 In little-endian, the first word is loaded in $r0.
1779 In big-endian, the last word is loaded in $r1.
1785 LITTLE: [d c b a] [x x x e]
1786 BIG: [x x x a] [b c d e]
1793 /* By using store_unsigned_integer we avoid having to do
1794 anything special for small big-endian values. */
1795 regcache_cooked_read_unsigned (regcache
, NDS32_R0_REGNUM
, &tmp
);
1796 store_unsigned_integer (valbuf
, len
, byte_order
, tmp
);
1800 regcache_cooked_read (regcache
, NDS32_R0_REGNUM
, valbuf
);
1806 len1
= byte_order
== BFD_ENDIAN_BIG
? len
- 4 : 4;
1809 regcache_cooked_read_unsigned (regcache
, NDS32_R0_REGNUM
, &tmp
);
1810 store_unsigned_integer (valbuf
, len1
, byte_order
, tmp
);
1812 regcache_cooked_read_unsigned (regcache
, NDS32_R0_REGNUM
+ 1, &tmp
);
1813 store_unsigned_integer (valbuf
+ len1
, len2
, byte_order
, tmp
);
1817 regcache_cooked_read (regcache
, NDS32_R0_REGNUM
, valbuf
);
1818 regcache_cooked_read (regcache
, NDS32_R0_REGNUM
+ 1, valbuf
+ 4);
1823 /* Write, for architecture GDBARCH, a function return value of TYPE
1824 from VALBUF into REGCACHE. */
1827 nds32_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1828 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1830 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1831 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1832 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1833 int calling_use_fpr
;
1836 calling_use_fpr
= nds32_check_calling_use_fpr (type
);
1837 len
= TYPE_LENGTH (type
);
1839 if (abi_use_fpr
&& calling_use_fpr
)
1842 regcache_cooked_write (regcache
, tdep
->fs0_regnum
, valbuf
);
1844 regcache_cooked_write (regcache
, NDS32_FD0_REGNUM
, valbuf
);
1846 internal_error (__FILE__
, __LINE__
,
1847 _("Cannot store return value of %d bytes "
1848 "long floating-point."), len
);
1856 regval
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1857 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
, regval
);
1861 regcache_cooked_write (regcache
, NDS32_R0_REGNUM
, valbuf
);
1867 len1
= byte_order
== BFD_ENDIAN_BIG
? len
- 4 : 4;
1870 regval
= extract_unsigned_integer (valbuf
, len1
, byte_order
);
1871 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
, regval
);
1873 regval
= extract_unsigned_integer (valbuf
+ len1
, len2
, byte_order
);
1874 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
+ 1,
1879 regcache_cooked_write (regcache
, NDS32_R0_REGNUM
, valbuf
);
1880 regcache_cooked_write (regcache
, NDS32_R0_REGNUM
+ 1, valbuf
+ 4);
1885 /* Implement the "return_value" gdbarch method.
1887 Determine, for architecture GDBARCH, how a return value of TYPE
1888 should be returned. If it is supposed to be returned in registers,
1889 and READBUF is non-zero, read the appropriate value from REGCACHE,
1890 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1891 from WRITEBUF into REGCACHE. */
1893 static enum return_value_convention
1894 nds32_return_value (struct gdbarch
*gdbarch
, struct value
*func_type
,
1895 struct type
*type
, struct regcache
*regcache
,
1896 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1898 if (TYPE_LENGTH (type
) > 8)
1900 return RETURN_VALUE_STRUCT_CONVENTION
;
1904 if (readbuf
!= NULL
)
1905 nds32_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
1906 if (writebuf
!= NULL
)
1907 nds32_store_return_value (gdbarch
, type
, regcache
, writebuf
);
1909 return RETURN_VALUE_REGISTER_CONVENTION
;
1913 /* Implement the "get_longjmp_target" gdbarch method. */
1916 nds32_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1920 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1921 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1923 jb_addr
= get_frame_register_unsigned (frame
, NDS32_R0_REGNUM
);
1925 if (target_read_memory (jb_addr
+ 11 * 4, buf
, 4))
1928 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1932 /* Validate the given TDESC, and fixed-number some registers in it.
1933 Return 0 if the given TDESC does not contain the required feature
1934 or not contain required registers. */
1937 nds32_validate_tdesc_p (const struct target_desc
*tdesc
,
1938 struct tdesc_arch_data
*tdesc_data
,
1939 int *fpu_freg
, int *use_pseudo_fsrs
)
1941 const struct tdesc_feature
*feature
;
1944 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.nds32.core");
1945 if (feature
== NULL
)
1949 /* Validate and fixed-number R0-R10. */
1950 for (i
= NDS32_R0_REGNUM
; i
<= NDS32_R0_REGNUM
+ 10; i
++)
1951 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1952 nds32_register_names
[i
]);
1955 valid_p
&= tdesc_unnumbered_register (feature
,
1956 nds32_register_names
[NDS32_TA_REGNUM
]);
1958 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1959 for (i
= NDS32_FP_REGNUM
; i
<= NDS32_PC_REGNUM
; i
++)
1960 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1961 nds32_register_names
[i
]);
1966 /* Fixed-number R11-R27. */
1967 for (i
= NDS32_R0_REGNUM
+ 11; i
<= NDS32_R0_REGNUM
+ 27; i
++)
1968 tdesc_numbered_register (feature
, tdesc_data
, i
, nds32_register_names
[i
]);
1970 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.nds32.fpu");
1971 if (feature
!= NULL
)
1973 int num_fdr_regs
, num_fsr_regs
, fs0_regnum
, num_listed_fsr
;
1976 /* Guess FPU configuration via listed registers. */
1977 if (tdesc_unnumbered_register (feature
, "fd31"))
1979 else if (tdesc_unnumbered_register (feature
, "fd15"))
1981 else if (tdesc_unnumbered_register (feature
, "fd7"))
1983 else if (tdesc_unnumbered_register (feature
, "fd3"))
1987 /* Required FDR is not found. */
1992 /* Validate and fixed-number required FDRs. */
1993 num_fdr_regs
= num_fdr_map
[freg
];
1994 for (i
= 0; i
< num_fdr_regs
; i
++)
1995 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
1996 NDS32_FD0_REGNUM
+ i
,
1997 nds32_fdr_register_names
[i
]);
2001 /* Count the number of listed FSRs, and fixed-number them if present. */
2002 num_fsr_regs
= num_fsr_map
[freg
];
2003 fs0_regnum
= NDS32_FD0_REGNUM
+ num_fdr_regs
;
2005 for (i
= 0; i
< num_fsr_regs
; i
++)
2006 num_listed_fsr
+= tdesc_numbered_register (feature
, tdesc_data
,
2008 nds32_fsr_register_names
[i
]);
2010 if (num_listed_fsr
== 0)
2011 /* No required FSRs are listed explicitly, make them pseudo registers
2013 *use_pseudo_fsrs
= 1;
2014 else if (num_listed_fsr
== num_fsr_regs
)
2015 /* All required FSRs are listed explicitly. */
2016 *use_pseudo_fsrs
= 0;
2018 /* Some required FSRs are missing. */
2025 /* Initialize the current architecture based on INFO. If possible,
2026 re-use an architecture from ARCHES, which is a list of
2027 architectures already created during this debugging session.
2029 Called e.g. at program startup, when reading a core file, and when
2030 reading a binary file. */
2032 static struct gdbarch
*
2033 nds32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2035 struct gdbarch
*gdbarch
;
2036 struct gdbarch_tdep
*tdep
;
2037 struct gdbarch_list
*best_arch
;
2038 struct tdesc_arch_data
*tdesc_data
= NULL
;
2039 const struct target_desc
*tdesc
= info
.target_desc
;
2040 int elf_abi
= E_NDS_ABI_AABI
;
2042 int use_pseudo_fsrs
= 0;
2043 int i
, num_regs
, maxregs
;
2045 /* Extract the elf_flags if available. */
2046 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2047 elf_abi
= elf_elfheader (info
.abfd
)->e_flags
& EF_NDS_ABI
;
2049 /* If there is already a candidate, use it. */
2050 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2052 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2054 struct gdbarch_tdep
*idep
= gdbarch_tdep (best_arch
->gdbarch
);
2056 if (idep
->elf_abi
!= elf_abi
)
2059 /* Found a match. */
2063 if (best_arch
!= NULL
)
2064 return best_arch
->gdbarch
;
2066 if (!tdesc_has_registers (tdesc
))
2067 tdesc
= tdesc_nds32
;
2069 tdesc_data
= tdesc_data_alloc ();
2071 if (!nds32_validate_tdesc_p (tdesc
, tdesc_data
, &fpu_freg
, &use_pseudo_fsrs
))
2073 tdesc_data_cleanup (tdesc_data
);
2077 /* Allocate space for the new architecture. */
2078 tdep
= XCNEW (struct gdbarch_tdep
);
2079 tdep
->fpu_freg
= fpu_freg
;
2080 tdep
->use_pseudo_fsrs
= use_pseudo_fsrs
;
2081 tdep
->fs0_regnum
= -1;
2082 tdep
->elf_abi
= elf_abi
;
2084 gdbarch
= gdbarch_alloc (&info
, tdep
);
2087 num_regs
= NDS32_NUM_REGS
;
2088 else if (use_pseudo_fsrs
== 1)
2090 set_gdbarch_pseudo_register_read (gdbarch
, nds32_pseudo_register_read
);
2091 set_gdbarch_pseudo_register_write (gdbarch
, nds32_pseudo_register_write
);
2092 set_tdesc_pseudo_register_name (gdbarch
, nds32_pseudo_register_name
);
2093 set_tdesc_pseudo_register_type (gdbarch
, nds32_pseudo_register_type
);
2094 set_gdbarch_num_pseudo_regs (gdbarch
, num_fsr_map
[fpu_freg
]);
2096 num_regs
= NDS32_NUM_REGS
+ num_fdr_map
[fpu_freg
];
2099 num_regs
= NDS32_NUM_REGS
+ num_fdr_map
[fpu_freg
] + num_fsr_map
[fpu_freg
];
2101 set_gdbarch_num_regs (gdbarch
, num_regs
);
2102 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
2104 /* Cache the register number of fs0. */
2106 tdep
->fs0_regnum
= user_reg_map_name_to_regnum (gdbarch
, "fs0", -1);
2108 /* Add NDS32 register aliases. To avoid search in user register name space,
2109 user_reg_map_name_to_regnum is not used. */
2110 maxregs
= (gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
));
2111 for (i
= 0; i
< ARRAY_SIZE (nds32_register_aliases
); i
++)
2116 /* Search register name space. */
2117 for (j
= 0; j
< maxregs
; j
++)
2119 const char *regname
= gdbarch_register_name (gdbarch
, j
);
2122 && strcmp (regname
, nds32_register_aliases
[i
].name
) == 0)
2129 /* Try next alias entry if the given name can not be found in register
2134 user_reg_add (gdbarch
, nds32_register_aliases
[i
].alias
,
2135 value_of_nds32_reg
, (const void *) (intptr_t) regnum
);
2138 nds32_add_reggroups (gdbarch
);
2140 /* Hook in ABI-specific overrides, if they have been registered. */
2141 info
.tdep_info
= (void *) tdesc_data
;
2142 gdbarch_init_osabi (info
, gdbarch
);
2144 /* Override tdesc_register callbacks for system registers. */
2145 set_gdbarch_register_reggroup_p (gdbarch
, nds32_register_reggroup_p
);
2147 set_gdbarch_sp_regnum (gdbarch
, NDS32_SP_REGNUM
);
2148 set_gdbarch_pc_regnum (gdbarch
, NDS32_PC_REGNUM
);
2149 set_gdbarch_unwind_sp (gdbarch
, nds32_unwind_sp
);
2150 set_gdbarch_unwind_pc (gdbarch
, nds32_unwind_pc
);
2151 set_gdbarch_stack_frame_destroyed_p (gdbarch
, nds32_stack_frame_destroyed_p
);
2152 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, nds32_dwarf2_reg_to_regnum
);
2154 set_gdbarch_push_dummy_call (gdbarch
, nds32_push_dummy_call
);
2155 set_gdbarch_return_value (gdbarch
, nds32_return_value
);
2156 set_gdbarch_dummy_id (gdbarch
, nds32_dummy_id
);
2158 set_gdbarch_skip_prologue (gdbarch
, nds32_skip_prologue
);
2159 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2160 set_gdbarch_breakpoint_from_pc (gdbarch
, nds32_breakpoint_from_pc
);
2162 set_gdbarch_frame_align (gdbarch
, nds32_frame_align
);
2163 frame_base_set_default (gdbarch
, &nds32_frame_base
);
2165 set_gdbarch_print_insn (gdbarch
, print_insn_nds32
);
2167 /* Handle longjmp. */
2168 set_gdbarch_get_longjmp_target (gdbarch
, nds32_get_longjmp_target
);
2170 /* The order of appending is the order it check frame. */
2171 dwarf2_append_unwinders (gdbarch
);
2172 frame_unwind_append_unwinder (gdbarch
, &nds32_epilogue_frame_unwind
);
2173 frame_unwind_append_unwinder (gdbarch
, &nds32_frame_unwind
);
2179 _initialize_nds32_tdep (void)
2181 /* Initialize gdbarch. */
2182 register_gdbarch_init (bfd_arch_nds32
, nds32_gdbarch_init
);
2184 initialize_tdesc_nds32 ();
2185 nds32_init_reggroups ();