1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdbthread.h"
28 #include "linux-nat.h"
29 #include <sys/types.h>
32 #include <sys/ioctl.h>
35 #include <sys/procfs.h>
36 #include "nat/gdb_ptrace.h"
37 #include "inf-ptrace.h"
39 /* Prototypes for supply_gregset etc. */
42 #include "ppc-linux-tdep.h"
44 /* Required when using the AUXV. */
45 #include "elf/common.h"
48 #include "nat/ppc-linux.h"
50 /* Similarly for the hardware watchpoint support. These requests are used
51 when the PowerPC HWDEBUG ptrace interface is not available. */
52 #ifndef PTRACE_GET_DEBUGREG
53 #define PTRACE_GET_DEBUGREG 25
55 #ifndef PTRACE_SET_DEBUGREG
56 #define PTRACE_SET_DEBUGREG 26
58 #ifndef PTRACE_GETSIGINFO
59 #define PTRACE_GETSIGINFO 0x4202
62 /* These requests are used when the PowerPC HWDEBUG ptrace interface is
63 available. It exposes the debug facilities of PowerPC processors, as well
64 as additional features of BookE processors, such as ranged breakpoints and
65 watchpoints and hardware-accelerated condition evaluation. */
66 #ifndef PPC_PTRACE_GETHWDBGINFO
68 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
69 ptrace interface is not present in ptrace.h, so we'll have to pretty much
70 include it all here so that the code at least compiles on older systems. */
71 #define PPC_PTRACE_GETHWDBGINFO 0x89
72 #define PPC_PTRACE_SETHWDEBUG 0x88
73 #define PPC_PTRACE_DELHWDEBUG 0x87
77 uint32_t version
; /* Only version 1 exists to date. */
78 uint32_t num_instruction_bps
;
79 uint32_t num_data_bps
;
80 uint32_t num_condition_regs
;
81 uint32_t data_bp_alignment
;
82 uint32_t sizeof_condition
; /* size of the DVC register. */
86 /* Features will have bits indicating whether there is support for: */
87 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
88 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
89 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
90 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
92 struct ppc_hw_breakpoint
94 uint32_t version
; /* currently, version must be 1 */
95 uint32_t trigger_type
; /* only some combinations allowed */
96 uint32_t addr_mode
; /* address match mode */
97 uint32_t condition_mode
; /* break/watchpoint condition flags */
98 uint64_t addr
; /* break/watchpoint address */
99 uint64_t addr2
; /* range end or mask */
100 uint64_t condition_value
; /* contents of the DVC register */
104 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
105 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
106 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
107 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
110 #define PPC_BREAKPOINT_MODE_EXACT 0x0
111 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
112 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
113 #define PPC_BREAKPOINT_MODE_MASK 0x3
115 /* Condition mode. */
116 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
117 #define PPC_BREAKPOINT_CONDITION_AND 0x1
118 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
119 #define PPC_BREAKPOINT_CONDITION_OR 0x2
120 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
121 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
122 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
123 #define PPC_BREAKPOINT_CONDITION_BE(n) \
124 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
125 #endif /* PPC_PTRACE_GETHWDBGINFO */
127 /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
128 watchpoint (up to 512 bytes). */
129 #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
130 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
131 #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
133 /* Similarly for the general-purpose (gp0 -- gp31)
134 and floating-point registers (fp0 -- fp31). */
135 #ifndef PTRACE_GETREGS
136 #define PTRACE_GETREGS 12
138 #ifndef PTRACE_SETREGS
139 #define PTRACE_SETREGS 13
141 #ifndef PTRACE_GETFPREGS
142 #define PTRACE_GETFPREGS 14
144 #ifndef PTRACE_SETFPREGS
145 #define PTRACE_SETFPREGS 15
148 /* This oddity is because the Linux kernel defines elf_vrregset_t as
149 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
150 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
151 the vrsave as an extra 4 bytes at the end. I opted for creating a
152 flat array of chars, so that it is easier to manipulate for gdb.
154 There are 32 vector registers 16 bytes longs, plus a VSCR register
155 which is only 4 bytes long, but is fetched as a 16 bytes
156 quantity. Up to here we have the elf_vrregset_t structure.
157 Appended to this there is space for the VRSAVE register: 4 bytes.
158 Even though this vrsave register is not included in the regset
159 typedef, it is handled by the ptrace requests.
161 Note that GNU/Linux doesn't support little endian PPC hardware,
162 therefore the offset at which the real value of the VSCR register
163 is located will be always 12 bytes.
165 The layout is like this (where x is the actual value of the vscr reg): */
169 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
170 <-------> <-------><-------><->
175 #define SIZEOF_VRREGS 33*16+4
177 typedef char gdb_vrregset_t
[SIZEOF_VRREGS
];
179 /* This is the layout of the POWER7 VSX registers and the way they overlap
180 with the existing FPR and VMX registers.
182 VSR doubleword 0 VSR doubleword 1
183 ----------------------------------------------------------------
185 ----------------------------------------------------------------
187 ----------------------------------------------------------------
190 ----------------------------------------------------------------
191 VSR[30] | FPR[30] | |
192 ----------------------------------------------------------------
193 VSR[31] | FPR[31] | |
194 ----------------------------------------------------------------
196 ----------------------------------------------------------------
198 ----------------------------------------------------------------
201 ----------------------------------------------------------------
203 ----------------------------------------------------------------
205 ----------------------------------------------------------------
207 VSX has 64 128bit registers. The first 32 registers overlap with
208 the FP registers (doubleword 0) and hence extend them with additional
209 64 bits (doubleword 1). The other 32 regs overlap with the VMX
211 #define SIZEOF_VSXREGS 32*8
213 typedef char gdb_vsxregset_t
[SIZEOF_VSXREGS
];
215 /* On PPC processors that support the Signal Processing Extension
216 (SPE) APU, the general-purpose registers are 64 bits long.
217 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
218 ptrace calls only access the lower half of each register, to allow
219 them to behave the same way they do on non-SPE systems. There's a
220 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
221 read and write the top halves of all the general-purpose registers
222 at once, along with some SPE-specific registers.
224 GDB itself continues to claim the general-purpose registers are 32
225 bits long. It has unnamed raw registers that hold the upper halves
226 of the gprs, and the full 64-bit SIMD views of the registers,
227 'ev0' -- 'ev31', are pseudo-registers that splice the top and
228 bottom halves together.
230 This is the structure filled in by PTRACE_GETEVRREGS and written to
231 the inferior's registers by PTRACE_SETEVRREGS. */
232 struct gdb_evrregset_t
234 unsigned long evr
[32];
235 unsigned long long acc
;
236 unsigned long spefscr
;
239 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
240 PTRACE_SETVSXREGS requests, for reading and writing the VSX
241 POWER7 registers 0 through 31. Zero if we've tried one of them and
242 gotten an error. Note that VSX registers 32 through 63 overlap
243 with VR registers 0 through 31. */
244 int have_ptrace_getsetvsxregs
= 1;
246 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
247 PTRACE_SETVRREGS requests, for reading and writing the Altivec
248 registers. Zero if we've tried one of them and gotten an
250 int have_ptrace_getvrregs
= 1;
252 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
253 PTRACE_SETEVRREGS requests, for reading and writing the SPE
254 registers. Zero if we've tried one of them and gotten an
256 int have_ptrace_getsetevrregs
= 1;
258 /* Non-zero if our kernel may support the PTRACE_GETREGS and
259 PTRACE_SETREGS requests, for reading and writing the
260 general-purpose registers. Zero if we've tried one of
261 them and gotten an error. */
262 int have_ptrace_getsetregs
= 1;
264 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
265 PTRACE_SETFPREGS requests, for reading and writing the
266 floating-pointers registers. Zero if we've tried one of
267 them and gotten an error. */
268 int have_ptrace_getsetfpregs
= 1;
271 /* registers layout, as presented by the ptrace interface:
272 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
273 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
274 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
275 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
276 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
277 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
278 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
279 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
280 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
281 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
282 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
283 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
284 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
288 ppc_register_u_addr (struct gdbarch
*gdbarch
, int regno
)
291 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
292 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
293 interface, and not the wordsize of the program's ABI. */
294 int wordsize
= sizeof (long);
296 /* General purpose registers occupy 1 slot each in the buffer. */
297 if (regno
>= tdep
->ppc_gp0_regnum
298 && regno
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
299 u_addr
= ((regno
- tdep
->ppc_gp0_regnum
+ PT_R0
) * wordsize
);
301 /* Floating point regs: eight bytes each in both 32- and 64-bit
302 ptrace interfaces. Thus, two slots each in 32-bit interface, one
303 slot each in 64-bit interface. */
304 if (tdep
->ppc_fp0_regnum
>= 0
305 && regno
>= tdep
->ppc_fp0_regnum
306 && regno
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
307 u_addr
= (PT_FPR0
* wordsize
) + ((regno
- tdep
->ppc_fp0_regnum
) * 8);
309 /* UISA special purpose registers: 1 slot each. */
310 if (regno
== gdbarch_pc_regnum (gdbarch
))
311 u_addr
= PT_NIP
* wordsize
;
312 if (regno
== tdep
->ppc_lr_regnum
)
313 u_addr
= PT_LNK
* wordsize
;
314 if (regno
== tdep
->ppc_cr_regnum
)
315 u_addr
= PT_CCR
* wordsize
;
316 if (regno
== tdep
->ppc_xer_regnum
)
317 u_addr
= PT_XER
* wordsize
;
318 if (regno
== tdep
->ppc_ctr_regnum
)
319 u_addr
= PT_CTR
* wordsize
;
321 if (regno
== tdep
->ppc_mq_regnum
)
322 u_addr
= PT_MQ
* wordsize
;
324 if (regno
== tdep
->ppc_ps_regnum
)
325 u_addr
= PT_MSR
* wordsize
;
326 if (regno
== PPC_ORIG_R3_REGNUM
)
327 u_addr
= PT_ORIG_R3
* wordsize
;
328 if (regno
== PPC_TRAP_REGNUM
)
329 u_addr
= PT_TRAP
* wordsize
;
330 if (tdep
->ppc_fpscr_regnum
>= 0
331 && regno
== tdep
->ppc_fpscr_regnum
)
333 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
334 kernel headers incorrectly contained the 32-bit definition of
335 PT_FPSCR. For the 32-bit definition, floating-point
336 registers occupy two 32-bit "slots", and the FPSCR lives in
337 the second half of such a slot-pair (hence +1). For 64-bit,
338 the FPSCR instead occupies the full 64-bit 2-word-slot and
339 hence no adjustment is necessary. Hack around this. */
340 if (wordsize
== 8 && PT_FPSCR
== (48 + 32 + 1))
341 u_addr
= (48 + 32) * wordsize
;
342 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
343 slot and not just its second word. The PT_FPSCR supplied when
344 GDB is compiled as a 32-bit app doesn't reflect this. */
345 else if (wordsize
== 4 && register_size (gdbarch
, regno
) == 8
346 && PT_FPSCR
== (48 + 2*32 + 1))
347 u_addr
= (48 + 2*32) * wordsize
;
349 u_addr
= PT_FPSCR
* wordsize
;
354 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
355 registers set mechanism, as opposed to the interface for all the
356 other registers, that stores/fetches each register individually. */
358 fetch_vsx_register (struct regcache
*regcache
, int tid
, int regno
)
361 gdb_vsxregset_t regs
;
362 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
363 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
364 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
366 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
371 have_ptrace_getsetvsxregs
= 0;
374 perror_with_name (_("Unable to fetch VSX register"));
377 regcache_raw_supply (regcache
, regno
,
378 regs
+ (regno
- tdep
->ppc_vsr0_upper_regnum
)
382 /* The Linux kernel ptrace interface for AltiVec registers uses the
383 registers set mechanism, as opposed to the interface for all the
384 other registers, that stores/fetches each register individually. */
386 fetch_altivec_register (struct regcache
*regcache
, int tid
, int regno
)
391 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
392 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
393 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
395 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
400 have_ptrace_getvrregs
= 0;
403 perror_with_name (_("Unable to fetch AltiVec register"));
406 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
407 long on the hardware. We deal only with the lower 4 bytes of the
408 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
409 there is no need to define an offset for it. */
410 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
411 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
413 regcache_raw_supply (regcache
, regno
,
415 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
418 /* Fetch the top 32 bits of TID's general-purpose registers and the
419 SPE-specific registers, and place the results in EVRREGSET. If we
420 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
423 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
424 PTRACE_SETEVRREGS requests are supported is isolated here, and in
425 set_spe_registers. */
427 get_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
429 if (have_ptrace_getsetevrregs
)
431 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, evrregset
) >= 0)
435 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
436 we just return zeros. */
438 have_ptrace_getsetevrregs
= 0;
440 /* Anything else needs to be reported. */
441 perror_with_name (_("Unable to fetch SPE registers"));
445 memset (evrregset
, 0, sizeof (*evrregset
));
448 /* Supply values from TID for SPE-specific raw registers: the upper
449 halves of the GPRs, the accumulator, and the spefscr. REGNO must
450 be the number of an upper half register, acc, spefscr, or -1 to
451 supply the values of all registers. */
453 fetch_spe_register (struct regcache
*regcache
, int tid
, int regno
)
455 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
456 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
457 struct gdb_evrregset_t evrregs
;
459 gdb_assert (sizeof (evrregs
.evr
[0])
460 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
461 gdb_assert (sizeof (evrregs
.acc
)
462 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
463 gdb_assert (sizeof (evrregs
.spefscr
)
464 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
466 get_spe_registers (tid
, &evrregs
);
472 for (i
= 0; i
< ppc_num_gprs
; i
++)
473 regcache_raw_supply (regcache
, tdep
->ppc_ev0_upper_regnum
+ i
,
476 else if (tdep
->ppc_ev0_upper_regnum
<= regno
477 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
478 regcache_raw_supply (regcache
, regno
,
479 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
482 || regno
== tdep
->ppc_acc_regnum
)
483 regcache_raw_supply (regcache
, tdep
->ppc_acc_regnum
, &evrregs
.acc
);
486 || regno
== tdep
->ppc_spefscr_regnum
)
487 regcache_raw_supply (regcache
, tdep
->ppc_spefscr_regnum
,
492 fetch_register (struct regcache
*regcache
, int tid
, int regno
)
494 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
495 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
496 /* This isn't really an address. But ptrace thinks of it as one. */
497 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
498 int bytes_transferred
;
499 unsigned int offset
; /* Offset of registers within the u area. */
500 gdb_byte buf
[PPC_MAX_REGISTER_SIZE
];
502 if (altivec_register_p (gdbarch
, regno
))
504 /* If this is the first time through, or if it is not the first
505 time through, and we have comfirmed that there is kernel
506 support for such a ptrace request, then go and fetch the
508 if (have_ptrace_getvrregs
)
510 fetch_altivec_register (regcache
, tid
, regno
);
513 /* If we have discovered that there is no ptrace support for
514 AltiVec registers, fall through and return zeroes, because
515 regaddr will be -1 in this case. */
517 if (vsx_register_p (gdbarch
, regno
))
519 if (have_ptrace_getsetvsxregs
)
521 fetch_vsx_register (regcache
, tid
, regno
);
525 else if (spe_register_p (gdbarch
, regno
))
527 fetch_spe_register (regcache
, tid
, regno
);
533 memset (buf
, '\0', register_size (gdbarch
, regno
)); /* Supply zeroes */
534 regcache_raw_supply (regcache
, regno
, buf
);
538 /* Read the raw register using sizeof(long) sized chunks. On a
539 32-bit platform, 64-bit floating-point registers will require two
541 for (bytes_transferred
= 0;
542 bytes_transferred
< register_size (gdbarch
, regno
);
543 bytes_transferred
+= sizeof (long))
548 l
= ptrace (PTRACE_PEEKUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, 0);
549 regaddr
+= sizeof (long);
553 xsnprintf (message
, sizeof (message
), "reading register %s (#%d)",
554 gdbarch_register_name (gdbarch
, regno
), regno
);
555 perror_with_name (message
);
557 memcpy (&buf
[bytes_transferred
], &l
, sizeof (l
));
560 /* Now supply the register. Keep in mind that the regcache's idea
561 of the register's size may not be a multiple of sizeof
563 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
565 /* Little-endian values are always found at the left end of the
566 bytes transferred. */
567 regcache_raw_supply (regcache
, regno
, buf
);
569 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
571 /* Big-endian values are found at the right end of the bytes
573 size_t padding
= (bytes_transferred
- register_size (gdbarch
, regno
));
574 regcache_raw_supply (regcache
, regno
, buf
+ padding
);
577 internal_error (__FILE__
, __LINE__
,
578 _("fetch_register: unexpected byte order: %d"),
579 gdbarch_byte_order (gdbarch
));
583 supply_vsxregset (struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
586 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
587 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
588 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
590 for (i
= 0; i
< ppc_num_vshrs
; i
++)
592 regcache_raw_supply (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
593 *vsxregsetp
+ i
* vsxregsize
);
598 supply_vrregset (struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
601 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
602 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
603 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
604 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
605 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
607 for (i
= 0; i
< num_of_vrregs
; i
++)
609 /* The last 2 registers of this set are only 32 bit long, not
610 128. However an offset is necessary only for VSCR because it
611 occupies a whole vector, while VRSAVE occupies a full 4 bytes
613 if (i
== (num_of_vrregs
- 2))
614 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
615 *vrregsetp
+ i
* vrregsize
+ offset
);
617 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
618 *vrregsetp
+ i
* vrregsize
);
623 fetch_vsx_registers (struct regcache
*regcache
, int tid
)
626 gdb_vsxregset_t regs
;
628 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
633 have_ptrace_getsetvsxregs
= 0;
636 perror_with_name (_("Unable to fetch VSX registers"));
638 supply_vsxregset (regcache
, ®s
);
642 fetch_altivec_registers (struct regcache
*regcache
, int tid
)
647 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
652 have_ptrace_getvrregs
= 0;
655 perror_with_name (_("Unable to fetch AltiVec registers"));
657 supply_vrregset (regcache
, ®s
);
660 /* This function actually issues the request to ptrace, telling
661 it to get all general-purpose registers and put them into the
664 If the ptrace request does not exist, this function returns 0
665 and properly sets the have_ptrace_* flag. If the request fails,
666 this function calls perror_with_name. Otherwise, if the request
667 succeeds, then the regcache gets filled and 1 is returned. */
669 fetch_all_gp_regs (struct regcache
*regcache
, int tid
)
671 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
672 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
673 gdb_gregset_t gregset
;
675 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
679 have_ptrace_getsetregs
= 0;
682 perror_with_name (_("Couldn't get general-purpose registers."));
685 supply_gregset (regcache
, (const gdb_gregset_t
*) &gregset
);
690 /* This is a wrapper for the fetch_all_gp_regs function. It is
691 responsible for verifying if this target has the ptrace request
692 that can be used to fetch all general-purpose registers at one
693 shot. If it doesn't, then we should fetch them using the
694 old-fashioned way, which is to iterate over the registers and
695 request them one by one. */
697 fetch_gp_regs (struct regcache
*regcache
, int tid
)
699 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
700 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
703 if (have_ptrace_getsetregs
)
704 if (fetch_all_gp_regs (regcache
, tid
))
707 /* If we've hit this point, it doesn't really matter which
708 architecture we are using. We just need to read the
709 registers in the "old-fashioned way". */
710 for (i
= 0; i
< ppc_num_gprs
; i
++)
711 fetch_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
714 /* This function actually issues the request to ptrace, telling
715 it to get all floating-point registers and put them into the
718 If the ptrace request does not exist, this function returns 0
719 and properly sets the have_ptrace_* flag. If the request fails,
720 this function calls perror_with_name. Otherwise, if the request
721 succeeds, then the regcache gets filled and 1 is returned. */
723 fetch_all_fp_regs (struct regcache
*regcache
, int tid
)
725 gdb_fpregset_t fpregs
;
727 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
731 have_ptrace_getsetfpregs
= 0;
734 perror_with_name (_("Couldn't get floating-point registers."));
737 supply_fpregset (regcache
, (const gdb_fpregset_t
*) &fpregs
);
742 /* This is a wrapper for the fetch_all_fp_regs function. It is
743 responsible for verifying if this target has the ptrace request
744 that can be used to fetch all floating-point registers at one
745 shot. If it doesn't, then we should fetch them using the
746 old-fashioned way, which is to iterate over the registers and
747 request them one by one. */
749 fetch_fp_regs (struct regcache
*regcache
, int tid
)
751 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
752 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
755 if (have_ptrace_getsetfpregs
)
756 if (fetch_all_fp_regs (regcache
, tid
))
759 /* If we've hit this point, it doesn't really matter which
760 architecture we are using. We just need to read the
761 registers in the "old-fashioned way". */
762 for (i
= 0; i
< ppc_num_fprs
; i
++)
763 fetch_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
767 fetch_ppc_registers (struct regcache
*regcache
, int tid
)
770 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
771 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
773 fetch_gp_regs (regcache
, tid
);
774 if (tdep
->ppc_fp0_regnum
>= 0)
775 fetch_fp_regs (regcache
, tid
);
776 fetch_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
777 if (tdep
->ppc_ps_regnum
!= -1)
778 fetch_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
779 if (tdep
->ppc_cr_regnum
!= -1)
780 fetch_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
781 if (tdep
->ppc_lr_regnum
!= -1)
782 fetch_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
783 if (tdep
->ppc_ctr_regnum
!= -1)
784 fetch_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
785 if (tdep
->ppc_xer_regnum
!= -1)
786 fetch_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
787 if (tdep
->ppc_mq_regnum
!= -1)
788 fetch_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
789 if (ppc_linux_trap_reg_p (gdbarch
))
791 fetch_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
792 fetch_register (regcache
, tid
, PPC_TRAP_REGNUM
);
794 if (tdep
->ppc_fpscr_regnum
!= -1)
795 fetch_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
796 if (have_ptrace_getvrregs
)
797 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
798 fetch_altivec_registers (regcache
, tid
);
799 if (have_ptrace_getsetvsxregs
)
800 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
801 fetch_vsx_registers (regcache
, tid
);
802 if (tdep
->ppc_ev0_upper_regnum
>= 0)
803 fetch_spe_register (regcache
, tid
, -1);
806 /* Fetch registers from the child process. Fetch all registers if
807 regno == -1, otherwise fetch all general registers or all floating
808 point registers depending upon the value of regno. */
810 ppc_linux_fetch_inferior_registers (struct target_ops
*ops
,
811 struct regcache
*regcache
, int regno
)
813 pid_t tid
= get_ptrace_pid (regcache_get_ptid (regcache
));
816 fetch_ppc_registers (regcache
, tid
);
818 fetch_register (regcache
, tid
, regno
);
821 /* Store one VSX register. */
823 store_vsx_register (const struct regcache
*regcache
, int tid
, int regno
)
826 gdb_vsxregset_t regs
;
827 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
828 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
829 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
831 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
836 have_ptrace_getsetvsxregs
= 0;
839 perror_with_name (_("Unable to fetch VSX register"));
842 regcache_raw_collect (regcache
, regno
, regs
+
843 (regno
- tdep
->ppc_vsr0_upper_regnum
) * vsxregsize
);
845 ret
= ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
);
847 perror_with_name (_("Unable to store VSX register"));
850 /* Store one register. */
852 store_altivec_register (const struct regcache
*regcache
, int tid
, int regno
)
857 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
858 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
859 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
861 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
866 have_ptrace_getvrregs
= 0;
869 perror_with_name (_("Unable to fetch AltiVec register"));
872 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
873 long on the hardware. */
874 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
875 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
877 regcache_raw_collect (regcache
, regno
,
879 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
881 ret
= ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
);
883 perror_with_name (_("Unable to store AltiVec register"));
886 /* Assuming TID referrs to an SPE process, set the top halves of TID's
887 general-purpose registers and its SPE-specific registers to the
888 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
891 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
892 PTRACE_SETEVRREGS requests are supported is isolated here, and in
893 get_spe_registers. */
895 set_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
897 if (have_ptrace_getsetevrregs
)
899 if (ptrace (PTRACE_SETEVRREGS
, tid
, 0, evrregset
) >= 0)
903 /* EIO means that the PTRACE_SETEVRREGS request isn't
904 supported; we fail silently, and don't try the call
907 have_ptrace_getsetevrregs
= 0;
909 /* Anything else needs to be reported. */
910 perror_with_name (_("Unable to set SPE registers"));
915 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
916 If REGNO is -1, write the values of all the SPE-specific
919 store_spe_register (const struct regcache
*regcache
, int tid
, int regno
)
921 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
922 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
923 struct gdb_evrregset_t evrregs
;
925 gdb_assert (sizeof (evrregs
.evr
[0])
926 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
927 gdb_assert (sizeof (evrregs
.acc
)
928 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
929 gdb_assert (sizeof (evrregs
.spefscr
)
930 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
933 /* Since we're going to write out every register, the code below
934 should store to every field of evrregs; if that doesn't happen,
935 make it obvious by initializing it with suspicious values. */
936 memset (&evrregs
, 42, sizeof (evrregs
));
938 /* We can only read and write the entire EVR register set at a
939 time, so to write just a single register, we do a
940 read-modify-write maneuver. */
941 get_spe_registers (tid
, &evrregs
);
947 for (i
= 0; i
< ppc_num_gprs
; i
++)
948 regcache_raw_collect (regcache
,
949 tdep
->ppc_ev0_upper_regnum
+ i
,
952 else if (tdep
->ppc_ev0_upper_regnum
<= regno
953 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
954 regcache_raw_collect (regcache
, regno
,
955 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
958 || regno
== tdep
->ppc_acc_regnum
)
959 regcache_raw_collect (regcache
,
960 tdep
->ppc_acc_regnum
,
964 || regno
== tdep
->ppc_spefscr_regnum
)
965 regcache_raw_collect (regcache
,
966 tdep
->ppc_spefscr_regnum
,
969 /* Write back the modified register set. */
970 set_spe_registers (tid
, &evrregs
);
974 store_register (const struct regcache
*regcache
, int tid
, int regno
)
976 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
977 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
978 /* This isn't really an address. But ptrace thinks of it as one. */
979 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
981 size_t bytes_to_transfer
;
982 gdb_byte buf
[PPC_MAX_REGISTER_SIZE
];
984 if (altivec_register_p (gdbarch
, regno
))
986 store_altivec_register (regcache
, tid
, regno
);
989 if (vsx_register_p (gdbarch
, regno
))
991 store_vsx_register (regcache
, tid
, regno
);
994 else if (spe_register_p (gdbarch
, regno
))
996 store_spe_register (regcache
, tid
, regno
);
1003 /* First collect the register. Keep in mind that the regcache's
1004 idea of the register's size may not be a multiple of sizeof
1006 memset (buf
, 0, sizeof buf
);
1007 bytes_to_transfer
= align_up (register_size (gdbarch
, regno
), sizeof (long));
1008 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1010 /* Little-endian values always sit at the left end of the buffer. */
1011 regcache_raw_collect (regcache
, regno
, buf
);
1013 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1015 /* Big-endian values sit at the right end of the buffer. */
1016 size_t padding
= (bytes_to_transfer
- register_size (gdbarch
, regno
));
1017 regcache_raw_collect (regcache
, regno
, buf
+ padding
);
1020 for (i
= 0; i
< bytes_to_transfer
; i
+= sizeof (long))
1024 memcpy (&l
, &buf
[i
], sizeof (l
));
1026 ptrace (PTRACE_POKEUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, l
);
1027 regaddr
+= sizeof (long);
1030 && (regno
== tdep
->ppc_fpscr_regnum
1031 || regno
== PPC_ORIG_R3_REGNUM
1032 || regno
== PPC_TRAP_REGNUM
))
1034 /* Some older kernel versions don't allow fpscr, orig_r3
1035 or trap to be written. */
1042 xsnprintf (message
, sizeof (message
), "writing register %s (#%d)",
1043 gdbarch_register_name (gdbarch
, regno
), regno
);
1044 perror_with_name (message
);
1050 fill_vsxregset (const struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
1053 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1054 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1055 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
1057 for (i
= 0; i
< ppc_num_vshrs
; i
++)
1058 regcache_raw_collect (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
1059 *vsxregsetp
+ i
* vsxregsize
);
1063 fill_vrregset (const struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
1066 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1067 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1068 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
1069 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
1070 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
1072 for (i
= 0; i
< num_of_vrregs
; i
++)
1074 /* The last 2 registers of this set are only 32 bit long, not
1075 128, but only VSCR is fetched as a 16 bytes quantity. */
1076 if (i
== (num_of_vrregs
- 2))
1077 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1078 *vrregsetp
+ i
* vrregsize
+ offset
);
1080 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1081 *vrregsetp
+ i
* vrregsize
);
1086 store_vsx_registers (const struct regcache
*regcache
, int tid
)
1089 gdb_vsxregset_t regs
;
1091 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
1096 have_ptrace_getsetvsxregs
= 0;
1099 perror_with_name (_("Couldn't get VSX registers"));
1102 fill_vsxregset (regcache
, ®s
);
1104 if (ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
) < 0)
1105 perror_with_name (_("Couldn't write VSX registers"));
1109 store_altivec_registers (const struct regcache
*regcache
, int tid
)
1112 gdb_vrregset_t regs
;
1114 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
1119 have_ptrace_getvrregs
= 0;
1122 perror_with_name (_("Couldn't get AltiVec registers"));
1125 fill_vrregset (regcache
, ®s
);
1127 if (ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
) < 0)
1128 perror_with_name (_("Couldn't write AltiVec registers"));
1131 /* This function actually issues the request to ptrace, telling
1132 it to store all general-purpose registers present in the specified
1135 If the ptrace request does not exist, this function returns 0
1136 and properly sets the have_ptrace_* flag. If the request fails,
1137 this function calls perror_with_name. Otherwise, if the request
1138 succeeds, then the regcache is stored and 1 is returned. */
1140 store_all_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1142 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1143 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1144 gdb_gregset_t gregset
;
1146 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
1150 have_ptrace_getsetregs
= 0;
1153 perror_with_name (_("Couldn't get general-purpose registers."));
1156 fill_gregset (regcache
, &gregset
, regno
);
1158 if (ptrace (PTRACE_SETREGS
, tid
, 0, (void *) &gregset
) < 0)
1162 have_ptrace_getsetregs
= 0;
1165 perror_with_name (_("Couldn't set general-purpose registers."));
1171 /* This is a wrapper for the store_all_gp_regs function. It is
1172 responsible for verifying if this target has the ptrace request
1173 that can be used to store all general-purpose registers at one
1174 shot. If it doesn't, then we should store them using the
1175 old-fashioned way, which is to iterate over the registers and
1176 store them one by one. */
1178 store_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1180 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1181 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1184 if (have_ptrace_getsetregs
)
1185 if (store_all_gp_regs (regcache
, tid
, regno
))
1188 /* If we hit this point, it doesn't really matter which
1189 architecture we are using. We just need to store the
1190 registers in the "old-fashioned way". */
1191 for (i
= 0; i
< ppc_num_gprs
; i
++)
1192 store_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
1195 /* This function actually issues the request to ptrace, telling
1196 it to store all floating-point registers present in the specified
1199 If the ptrace request does not exist, this function returns 0
1200 and properly sets the have_ptrace_* flag. If the request fails,
1201 this function calls perror_with_name. Otherwise, if the request
1202 succeeds, then the regcache is stored and 1 is returned. */
1204 store_all_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1206 gdb_fpregset_t fpregs
;
1208 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1212 have_ptrace_getsetfpregs
= 0;
1215 perror_with_name (_("Couldn't get floating-point registers."));
1218 fill_fpregset (regcache
, &fpregs
, regno
);
1220 if (ptrace (PTRACE_SETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1224 have_ptrace_getsetfpregs
= 0;
1227 perror_with_name (_("Couldn't set floating-point registers."));
1233 /* This is a wrapper for the store_all_fp_regs function. It is
1234 responsible for verifying if this target has the ptrace request
1235 that can be used to store all floating-point registers at one
1236 shot. If it doesn't, then we should store them using the
1237 old-fashioned way, which is to iterate over the registers and
1238 store them one by one. */
1240 store_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1242 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1243 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1246 if (have_ptrace_getsetfpregs
)
1247 if (store_all_fp_regs (regcache
, tid
, regno
))
1250 /* If we hit this point, it doesn't really matter which
1251 architecture we are using. We just need to store the
1252 registers in the "old-fashioned way". */
1253 for (i
= 0; i
< ppc_num_fprs
; i
++)
1254 store_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
1258 store_ppc_registers (const struct regcache
*regcache
, int tid
)
1261 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1264 store_gp_regs (regcache
, tid
, -1);
1265 if (tdep
->ppc_fp0_regnum
>= 0)
1266 store_fp_regs (regcache
, tid
, -1);
1267 store_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
1268 if (tdep
->ppc_ps_regnum
!= -1)
1269 store_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
1270 if (tdep
->ppc_cr_regnum
!= -1)
1271 store_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
1272 if (tdep
->ppc_lr_regnum
!= -1)
1273 store_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
1274 if (tdep
->ppc_ctr_regnum
!= -1)
1275 store_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
1276 if (tdep
->ppc_xer_regnum
!= -1)
1277 store_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
1278 if (tdep
->ppc_mq_regnum
!= -1)
1279 store_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
1280 if (tdep
->ppc_fpscr_regnum
!= -1)
1281 store_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
1282 if (ppc_linux_trap_reg_p (gdbarch
))
1284 store_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
1285 store_register (regcache
, tid
, PPC_TRAP_REGNUM
);
1287 if (have_ptrace_getvrregs
)
1288 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
1289 store_altivec_registers (regcache
, tid
);
1290 if (have_ptrace_getsetvsxregs
)
1291 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
1292 store_vsx_registers (regcache
, tid
);
1293 if (tdep
->ppc_ev0_upper_regnum
>= 0)
1294 store_spe_register (regcache
, tid
, -1);
1297 /* Fetch the AT_HWCAP entry from the aux vector. */
1298 static unsigned long
1299 ppc_linux_get_hwcap (void)
1303 if (target_auxv_search (¤t_target
, AT_HWCAP
, &field
))
1304 return (unsigned long) field
;
1309 /* The cached DABR value, to install in new threads.
1310 This variable is used when the PowerPC HWDEBUG ptrace
1311 interface is not available. */
1312 static long saved_dabr_value
;
1314 /* Global structure that will store information about the available
1315 features provided by the PowerPC HWDEBUG ptrace interface. */
1316 static struct ppc_debug_info hwdebug_info
;
1318 /* Global variable that holds the maximum number of slots that the
1319 kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1321 static size_t max_slots_number
= 0;
1323 struct hw_break_tuple
1326 struct ppc_hw_breakpoint
*hw_break
;
1329 /* This is an internal VEC created to store information about *points inserted
1330 for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1332 typedef struct thread_points
1334 /* The TID to which this *point relates. */
1336 /* Information about the *point, such as its address, type, etc.
1338 Each element inside this vector corresponds to a hardware
1339 breakpoint or watchpoint in the thread represented by TID. The maximum
1340 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1341 the tuple is NULL, then the position in the vector is free. */
1342 struct hw_break_tuple
*hw_breaks
;
1344 DEF_VEC_P (thread_points_p
);
1346 VEC(thread_points_p
) *ppc_threads
= NULL
;
1348 /* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1350 #define PPC_DEBUG_CURRENT_VERSION 1
1352 /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
1354 have_ptrace_hwdebug_interface (void)
1356 static int have_ptrace_hwdebug_interface
= -1;
1358 if (have_ptrace_hwdebug_interface
== -1)
1362 tid
= ptid_get_lwp (inferior_ptid
);
1364 tid
= ptid_get_pid (inferior_ptid
);
1366 /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1367 if (ptrace (PPC_PTRACE_GETHWDBGINFO
, tid
, 0, &hwdebug_info
) >= 0)
1369 /* Check whether PowerPC HWDEBUG ptrace interface is functional and
1370 provides any supported feature. */
1371 if (hwdebug_info
.features
!= 0)
1373 have_ptrace_hwdebug_interface
= 1;
1374 max_slots_number
= hwdebug_info
.num_instruction_bps
1375 + hwdebug_info
.num_data_bps
1376 + hwdebug_info
.num_condition_regs
;
1377 return have_ptrace_hwdebug_interface
;
1380 /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1381 have_ptrace_hwdebug_interface
= 0;
1382 memset (&hwdebug_info
, 0, sizeof (struct ppc_debug_info
));
1385 return have_ptrace_hwdebug_interface
;
1389 ppc_linux_can_use_hw_breakpoint (struct target_ops
*self
,
1390 enum bptype type
, int cnt
, int ot
)
1392 int total_hw_wp
, total_hw_bp
;
1394 if (have_ptrace_hwdebug_interface ())
1396 /* When PowerPC HWDEBUG ptrace interface is available, the number of
1397 available hardware watchpoints and breakpoints is stored at the
1398 hwdebug_info struct. */
1399 total_hw_bp
= hwdebug_info
.num_instruction_bps
;
1400 total_hw_wp
= hwdebug_info
.num_data_bps
;
1404 /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1405 consider having 1 hardware watchpoint and no hardware breakpoints. */
1410 if (type
== bp_hardware_watchpoint
|| type
== bp_read_watchpoint
1411 || type
== bp_access_watchpoint
|| type
== bp_watchpoint
)
1413 if (cnt
+ ot
> total_hw_wp
)
1416 else if (type
== bp_hardware_breakpoint
)
1418 if (total_hw_bp
== 0)
1420 /* No hardware breakpoint support. */
1423 if (cnt
> total_hw_bp
)
1427 if (!have_ptrace_hwdebug_interface ())
1430 ptid_t ptid
= inferior_ptid
;
1432 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1433 and whether the target has DABR. If either answer is no, the
1434 ptrace call will return -1. Fail in that case. */
1435 tid
= ptid_get_lwp (ptid
);
1437 tid
= ptid_get_pid (ptid
);
1439 if (ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, 0) == -1)
1447 ppc_linux_region_ok_for_hw_watchpoint (struct target_ops
*self
,
1448 CORE_ADDR addr
, int len
)
1450 /* Handle sub-8-byte quantities. */
1454 /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1455 restrictions for watchpoints in the processors. In that case, we use that
1456 information to determine the hardcoded watchable region for
1458 if (have_ptrace_hwdebug_interface ())
1461 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1462 watchpoints and can watch any access within an arbitrary memory
1463 region. This is useful to watch arrays and structs, for instance. It
1464 takes two hardware watchpoints though. */
1466 && hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
1467 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1469 /* Check if the processor provides DAWR interface. */
1470 if (hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_DAWR
)
1471 /* DAWR interface allows to watch up to 512 byte wide ranges which
1472 can't cross a 512 byte boundary. */
1475 region_size
= hwdebug_info
.data_bp_alignment
;
1476 /* Server processors provide one hardware watchpoint and addr+len should
1477 fall in the watchable region provided by the ptrace interface. */
1479 && (addr
+ len
> (addr
& ~(region_size
- 1)) + region_size
))
1482 /* addr+len must fall in the 8 byte watchable region for DABR-based
1483 processors (i.e., server processors). Without the new PowerPC HWDEBUG
1484 ptrace interface, DAC-based processors (i.e., embedded processors) will
1485 use addresses aligned to 4-bytes due to the way the read/write flags are
1486 passed in the old ptrace interface. */
1487 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1488 && (addr
+ len
) > (addr
& ~3) + 4)
1489 || (addr
+ len
) > (addr
& ~7) + 8)
1495 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1497 hwdebug_point_cmp (struct ppc_hw_breakpoint
*a
, struct ppc_hw_breakpoint
*b
)
1499 return (a
->trigger_type
== b
->trigger_type
1500 && a
->addr_mode
== b
->addr_mode
1501 && a
->condition_mode
== b
->condition_mode
1502 && a
->addr
== b
->addr
1503 && a
->addr2
== b
->addr2
1504 && a
->condition_value
== b
->condition_value
);
1507 /* This function can be used to retrieve a thread_points by the TID of the
1508 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1509 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1510 provided TID will be created and returned. */
1511 static struct thread_points
*
1512 hwdebug_find_thread_points_by_tid (int tid
, int alloc_new
)
1515 struct thread_points
*t
;
1517 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, t
); i
++)
1523 /* Do we need to allocate a new point_item
1524 if the wanted one does not exist? */
1527 t
= XNEW (struct thread_points
);
1528 t
->hw_breaks
= XCNEWVEC (struct hw_break_tuple
, max_slots_number
);
1530 VEC_safe_push (thread_points_p
, ppc_threads
, t
);
1536 /* This function is a generic wrapper that is responsible for inserting a
1537 *point (i.e., calling `ptrace' in order to issue the request to the
1538 kernel) and registering it internally in GDB. */
1540 hwdebug_insert_point (struct ppc_hw_breakpoint
*b
, int tid
)
1544 struct ppc_hw_breakpoint
*p
= XNEW (struct ppc_hw_breakpoint
);
1545 struct hw_break_tuple
*hw_breaks
;
1546 struct cleanup
*c
= make_cleanup (xfree
, p
);
1547 struct thread_points
*t
;
1548 struct hw_break_tuple
*tuple
;
1550 memcpy (p
, b
, sizeof (struct ppc_hw_breakpoint
));
1553 slot
= ptrace (PPC_PTRACE_SETHWDEBUG
, tid
, 0, p
);
1555 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1557 /* Everything went fine, so we have to register this *point. */
1558 t
= hwdebug_find_thread_points_by_tid (tid
, 1);
1559 gdb_assert (t
!= NULL
);
1560 hw_breaks
= t
->hw_breaks
;
1562 /* Find a free element in the hw_breaks vector. */
1563 for (i
= 0; i
< max_slots_number
; i
++)
1564 if (hw_breaks
[i
].hw_break
== NULL
)
1566 hw_breaks
[i
].slot
= slot
;
1567 hw_breaks
[i
].hw_break
= p
;
1571 gdb_assert (i
!= max_slots_number
);
1573 discard_cleanups (c
);
1576 /* This function is a generic wrapper that is responsible for removing a
1577 *point (i.e., calling `ptrace' in order to issue the request to the
1578 kernel), and unregistering it internally at GDB. */
1580 hwdebug_remove_point (struct ppc_hw_breakpoint
*b
, int tid
)
1583 struct hw_break_tuple
*hw_breaks
;
1584 struct thread_points
*t
;
1586 t
= hwdebug_find_thread_points_by_tid (tid
, 0);
1587 gdb_assert (t
!= NULL
);
1588 hw_breaks
= t
->hw_breaks
;
1590 for (i
= 0; i
< max_slots_number
; i
++)
1591 if (hw_breaks
[i
].hw_break
&& hwdebug_point_cmp (hw_breaks
[i
].hw_break
, b
))
1594 gdb_assert (i
!= max_slots_number
);
1596 /* We have to ignore ENOENT errors because the kernel implements hardware
1597 breakpoints/watchpoints as "one-shot", that is, they are automatically
1598 deleted when hit. */
1600 if (ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
) < 0)
1601 if (errno
!= ENOENT
)
1602 perror_with_name (_("Unexpected error deleting "
1603 "breakpoint or watchpoint"));
1605 xfree (hw_breaks
[i
].hw_break
);
1606 hw_breaks
[i
].hw_break
= NULL
;
1609 /* Return the number of registers needed for a ranged breakpoint. */
1612 ppc_linux_ranged_break_num_registers (struct target_ops
*target
)
1614 return ((have_ptrace_hwdebug_interface ()
1615 && hwdebug_info
.features
& PPC_DEBUG_FEATURE_INSN_BP_RANGE
)?
1619 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1620 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1623 ppc_linux_insert_hw_breakpoint (struct target_ops
*self
,
1624 struct gdbarch
*gdbarch
,
1625 struct bp_target_info
*bp_tgt
)
1627 struct lwp_info
*lp
;
1628 struct ppc_hw_breakpoint p
;
1630 if (!have_ptrace_hwdebug_interface ())
1633 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1634 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1635 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1636 p
.addr
= (uint64_t) (bp_tgt
->placed_address
= bp_tgt
->reqstd_address
);
1637 p
.condition_value
= 0;
1641 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1643 /* The breakpoint will trigger if the address of the instruction is
1644 within the defined range, as follows: p.addr <= address < p.addr2. */
1645 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1649 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1654 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
1660 ppc_linux_remove_hw_breakpoint (struct target_ops
*self
,
1661 struct gdbarch
*gdbarch
,
1662 struct bp_target_info
*bp_tgt
)
1664 struct lwp_info
*lp
;
1665 struct ppc_hw_breakpoint p
;
1667 if (!have_ptrace_hwdebug_interface ())
1670 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1671 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1672 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1673 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1674 p
.condition_value
= 0;
1678 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1680 /* The breakpoint will trigger if the address of the instruction is within
1681 the defined range, as follows: p.addr <= address < p.addr2. */
1682 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1686 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1691 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
1697 get_trigger_type (enum target_hw_bp_type type
)
1701 if (type
== hw_read
)
1702 t
= PPC_BREAKPOINT_TRIGGER_READ
;
1703 else if (type
== hw_write
)
1704 t
= PPC_BREAKPOINT_TRIGGER_WRITE
;
1706 t
= PPC_BREAKPOINT_TRIGGER_READ
| PPC_BREAKPOINT_TRIGGER_WRITE
;
1711 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1712 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1713 or hw_access for an access watchpoint. Returns 0 on success and throws
1714 an error on failure. */
1717 ppc_linux_insert_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1718 CORE_ADDR mask
, enum target_hw_bp_type rw
)
1720 struct lwp_info
*lp
;
1721 struct ppc_hw_breakpoint p
;
1723 gdb_assert (have_ptrace_hwdebug_interface ());
1725 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1726 p
.trigger_type
= get_trigger_type (rw
);
1727 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1728 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1731 p
.condition_value
= 0;
1734 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
1739 /* Remove a masked watchpoint at ADDR with the mask MASK.
1740 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1741 or hw_access for an access watchpoint. Returns 0 on success and throws
1742 an error on failure. */
1745 ppc_linux_remove_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1746 CORE_ADDR mask
, enum target_hw_bp_type rw
)
1748 struct lwp_info
*lp
;
1749 struct ppc_hw_breakpoint p
;
1751 gdb_assert (have_ptrace_hwdebug_interface ());
1753 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1754 p
.trigger_type
= get_trigger_type (rw
);
1755 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1756 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1759 p
.condition_value
= 0;
1762 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
1767 /* Check whether we have at least one free DVC register. */
1769 can_use_watchpoint_cond_accel (void)
1771 struct thread_points
*p
;
1772 int tid
= ptid_get_lwp (inferior_ptid
);
1773 int cnt
= hwdebug_info
.num_condition_regs
, i
;
1774 CORE_ADDR tmp_value
;
1776 if (!have_ptrace_hwdebug_interface () || cnt
== 0)
1779 p
= hwdebug_find_thread_points_by_tid (tid
, 0);
1783 for (i
= 0; i
< max_slots_number
; i
++)
1784 if (p
->hw_breaks
[i
].hw_break
!= NULL
1785 && (p
->hw_breaks
[i
].hw_break
->condition_mode
1786 != PPC_BREAKPOINT_CONDITION_NONE
))
1789 /* There are no available slots now. */
1797 /* Calculate the enable bits and the contents of the Data Value Compare
1798 debug register present in BookE processors.
1800 ADDR is the address to be watched, LEN is the length of watched data
1801 and DATA_VALUE is the value which will trigger the watchpoint.
1802 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1803 CONDITION_VALUE will hold the value which should be put in the
1806 calculate_dvc (CORE_ADDR addr
, int len
, CORE_ADDR data_value
,
1807 uint32_t *condition_mode
, uint64_t *condition_value
)
1809 int i
, num_byte_enable
, align_offset
, num_bytes_off_dvc
,
1810 rightmost_enabled_byte
;
1811 CORE_ADDR addr_end_data
, addr_end_dvc
;
1813 /* The DVC register compares bytes within fixed-length windows which
1814 are word-aligned, with length equal to that of the DVC register.
1815 We need to calculate where our watch region is relative to that
1816 window and enable comparison of the bytes which fall within it. */
1818 align_offset
= addr
% hwdebug_info
.sizeof_condition
;
1819 addr_end_data
= addr
+ len
;
1820 addr_end_dvc
= (addr
- align_offset
1821 + hwdebug_info
.sizeof_condition
);
1822 num_bytes_off_dvc
= (addr_end_data
> addr_end_dvc
)?
1823 addr_end_data
- addr_end_dvc
: 0;
1824 num_byte_enable
= len
- num_bytes_off_dvc
;
1825 /* Here, bytes are numbered from right to left. */
1826 rightmost_enabled_byte
= (addr_end_data
< addr_end_dvc
)?
1827 addr_end_dvc
- addr_end_data
: 0;
1829 *condition_mode
= PPC_BREAKPOINT_CONDITION_AND
;
1830 for (i
= 0; i
< num_byte_enable
; i
++)
1832 |= PPC_BREAKPOINT_CONDITION_BE (i
+ rightmost_enabled_byte
);
1834 /* Now we need to match the position within the DVC of the comparison
1835 value with where the watch region is relative to the window
1836 (i.e., the ALIGN_OFFSET). */
1838 *condition_value
= ((uint64_t) data_value
>> num_bytes_off_dvc
* 8
1839 << rightmost_enabled_byte
* 8);
1842 /* Return the number of memory locations that need to be accessed to
1843 evaluate the expression which generated the given value chain.
1844 Returns -1 if there's any register access involved, or if there are
1845 other kinds of values which are not acceptable in a condition
1846 expression (e.g., lval_computed or lval_internalvar). */
1848 num_memory_accesses (struct value
*v
)
1850 int found_memory_cnt
= 0;
1851 struct value
*head
= v
;
1853 /* The idea here is that evaluating an expression generates a series
1854 of values, one holding the value of every subexpression. (The
1855 expression a*b+c has five subexpressions: a, b, a*b, c, and
1856 a*b+c.) GDB's values hold almost enough information to establish
1857 the criteria given above --- they identify memory lvalues,
1858 register lvalues, computed values, etcetera. So we can evaluate
1859 the expression, and then scan the chain of values that leaves
1860 behind to determine the memory locations involved in the evaluation
1863 However, I don't think that the values returned by inferior
1864 function calls are special in any way. So this function may not
1865 notice that an expression contains an inferior function call.
1868 for (; v
; v
= value_next (v
))
1870 /* Constants and values from the history are fine. */
1871 if (VALUE_LVAL (v
) == not_lval
|| deprecated_value_modifiable (v
) == 0)
1873 else if (VALUE_LVAL (v
) == lval_memory
)
1875 /* A lazy memory lvalue is one that GDB never needed to fetch;
1876 we either just used its address (e.g., `a' in `a.b') or
1877 we never needed it at all (e.g., `a' in `a,b'). */
1878 if (!value_lazy (v
))
1881 /* Other kinds of values are not fine. */
1886 return found_memory_cnt
;
1889 /* Verifies whether the expression COND can be implemented using the
1890 DVC (Data Value Compare) register in BookE processors. The expression
1891 must test the watch value for equality with a constant expression.
1892 If the function returns 1, DATA_VALUE will contain the constant against
1893 which the watch value should be compared and LEN will contain the size
1896 check_condition (CORE_ADDR watch_addr
, struct expression
*cond
,
1897 CORE_ADDR
*data_value
, int *len
)
1899 int pc
= 1, num_accesses_left
, num_accesses_right
;
1900 struct value
*left_val
, *right_val
, *left_chain
, *right_chain
;
1902 if (cond
->elts
[0].opcode
!= BINOP_EQUAL
)
1905 fetch_subexp_value (cond
, &pc
, &left_val
, NULL
, &left_chain
, 0);
1906 num_accesses_left
= num_memory_accesses (left_chain
);
1908 if (left_val
== NULL
|| num_accesses_left
< 0)
1910 free_value_chain (left_chain
);
1915 fetch_subexp_value (cond
, &pc
, &right_val
, NULL
, &right_chain
, 0);
1916 num_accesses_right
= num_memory_accesses (right_chain
);
1918 if (right_val
== NULL
|| num_accesses_right
< 0)
1920 free_value_chain (left_chain
);
1921 free_value_chain (right_chain
);
1926 if (num_accesses_left
== 1 && num_accesses_right
== 0
1927 && VALUE_LVAL (left_val
) == lval_memory
1928 && value_address (left_val
) == watch_addr
)
1930 *data_value
= value_as_long (right_val
);
1932 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1933 the same type as the memory region referenced by LEFT_VAL. */
1934 *len
= TYPE_LENGTH (check_typedef (value_type (left_val
)));
1936 else if (num_accesses_left
== 0 && num_accesses_right
== 1
1937 && VALUE_LVAL (right_val
) == lval_memory
1938 && value_address (right_val
) == watch_addr
)
1940 *data_value
= value_as_long (left_val
);
1942 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1943 the same type as the memory region referenced by RIGHT_VAL. */
1944 *len
= TYPE_LENGTH (check_typedef (value_type (right_val
)));
1948 free_value_chain (left_chain
);
1949 free_value_chain (right_chain
);
1954 free_value_chain (left_chain
);
1955 free_value_chain (right_chain
);
1960 /* Return non-zero if the target is capable of using hardware to evaluate
1961 the condition expression, thus only triggering the watchpoint when it is
1964 ppc_linux_can_accel_watchpoint_condition (struct target_ops
*self
,
1965 CORE_ADDR addr
, int len
, int rw
,
1966 struct expression
*cond
)
1968 CORE_ADDR data_value
;
1970 return (have_ptrace_hwdebug_interface ()
1971 && hwdebug_info
.num_condition_regs
> 0
1972 && check_condition (addr
, cond
, &data_value
, &len
));
1975 /* Set up P with the parameters necessary to request a watchpoint covering
1976 LEN bytes starting at ADDR and if possible with condition expression COND
1977 evaluated by hardware. INSERT tells if we are creating a request for
1978 inserting or removing the watchpoint. */
1981 create_watchpoint_request (struct ppc_hw_breakpoint
*p
, CORE_ADDR addr
,
1982 int len
, enum target_hw_bp_type type
,
1983 struct expression
*cond
, int insert
)
1986 || !(hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
))
1989 CORE_ADDR data_value
;
1991 use_condition
= (insert
? can_use_watchpoint_cond_accel ()
1992 : hwdebug_info
.num_condition_regs
> 0);
1993 if (cond
&& use_condition
&& check_condition (addr
, cond
,
1995 calculate_dvc (addr
, len
, data_value
, &p
->condition_mode
,
1996 &p
->condition_value
);
1999 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2000 p
->condition_value
= 0;
2003 p
->addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
2008 p
->addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
2009 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2010 p
->condition_value
= 0;
2012 /* The watchpoint will trigger if the address of the memory access is
2013 within the defined range, as follows: p->addr <= address < p->addr2.
2015 Note that the above sentence just documents how ptrace interprets
2016 its arguments; the watchpoint is set to watch the range defined by
2017 the user _inclusively_, as specified by the user interface. */
2018 p
->addr2
= (uint64_t) addr
+ len
;
2021 p
->version
= PPC_DEBUG_CURRENT_VERSION
;
2022 p
->trigger_type
= get_trigger_type (type
);
2023 p
->addr
= (uint64_t) addr
;
2027 ppc_linux_insert_watchpoint (struct target_ops
*self
, CORE_ADDR addr
, int len
,
2028 enum target_hw_bp_type type
,
2029 struct expression
*cond
)
2031 struct lwp_info
*lp
;
2034 if (have_ptrace_hwdebug_interface ())
2036 struct ppc_hw_breakpoint p
;
2038 create_watchpoint_request (&p
, addr
, len
, type
, cond
, 1);
2041 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
2048 long read_mode
, write_mode
;
2050 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2052 /* PowerPC 440 requires only the read/write flags to be passed
2059 /* PowerPC 970 and other DABR-based processors are required to pass
2060 the Breakpoint Translation bit together with the flags. */
2065 dabr_value
= addr
& ~(read_mode
| write_mode
);
2069 /* Set read and translate bits. */
2070 dabr_value
|= read_mode
;
2073 /* Set write and translate bits. */
2074 dabr_value
|= write_mode
;
2077 /* Set read, write and translate bits. */
2078 dabr_value
|= read_mode
| write_mode
;
2082 saved_dabr_value
= dabr_value
;
2085 if (ptrace (PTRACE_SET_DEBUGREG
, ptid_get_lwp (lp
->ptid
), 0,
2086 saved_dabr_value
) < 0)
2096 ppc_linux_remove_watchpoint (struct target_ops
*self
, CORE_ADDR addr
, int len
,
2097 enum target_hw_bp_type type
,
2098 struct expression
*cond
)
2100 struct lwp_info
*lp
;
2103 if (have_ptrace_hwdebug_interface ())
2105 struct ppc_hw_breakpoint p
;
2107 create_watchpoint_request (&p
, addr
, len
, type
, cond
, 0);
2110 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
2116 saved_dabr_value
= 0;
2118 if (ptrace (PTRACE_SET_DEBUGREG
, ptid_get_lwp (lp
->ptid
), 0,
2119 saved_dabr_value
) < 0)
2129 ppc_linux_new_thread (struct lwp_info
*lp
)
2131 int tid
= ptid_get_lwp (lp
->ptid
);
2133 if (have_ptrace_hwdebug_interface ())
2136 struct thread_points
*p
;
2137 struct hw_break_tuple
*hw_breaks
;
2139 if (VEC_empty (thread_points_p
, ppc_threads
))
2142 /* Get a list of breakpoints from any thread. */
2143 p
= VEC_last (thread_points_p
, ppc_threads
);
2144 hw_breaks
= p
->hw_breaks
;
2146 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2147 for (i
= 0; i
< max_slots_number
; i
++)
2148 if (hw_breaks
[i
].hw_break
)
2150 /* Older kernels did not make new threads inherit their parent
2151 thread's debug state, so we always clear the slot and replicate
2152 the debug state ourselves, ensuring compatibility with all
2155 /* The ppc debug resource accounting is done through "slots".
2156 Ask the kernel the deallocate this specific *point's slot. */
2157 ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
);
2159 hwdebug_insert_point (hw_breaks
[i
].hw_break
, tid
);
2163 ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, saved_dabr_value
);
2167 ppc_linux_thread_exit (struct thread_info
*tp
, int silent
)
2170 int tid
= ptid_get_lwp (tp
->ptid
);
2171 struct hw_break_tuple
*hw_breaks
;
2172 struct thread_points
*t
= NULL
, *p
;
2174 if (!have_ptrace_hwdebug_interface ())
2177 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, p
); i
++)
2187 VEC_unordered_remove (thread_points_p
, ppc_threads
, i
);
2189 hw_breaks
= t
->hw_breaks
;
2191 for (i
= 0; i
< max_slots_number
; i
++)
2192 if (hw_breaks
[i
].hw_break
)
2193 xfree (hw_breaks
[i
].hw_break
);
2195 xfree (t
->hw_breaks
);
2200 ppc_linux_stopped_data_address (struct target_ops
*target
, CORE_ADDR
*addr_p
)
2204 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
2207 if (siginfo
.si_signo
!= SIGTRAP
2208 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2211 if (have_ptrace_hwdebug_interface ())
2214 struct thread_points
*t
;
2215 struct hw_break_tuple
*hw_breaks
;
2216 /* The index (or slot) of the *point is passed in the si_errno field. */
2217 int slot
= siginfo
.si_errno
;
2219 t
= hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid
), 0);
2221 /* Find out if this *point is a hardware breakpoint.
2222 If so, we should return 0. */
2225 hw_breaks
= t
->hw_breaks
;
2226 for (i
= 0; i
< max_slots_number
; i
++)
2227 if (hw_breaks
[i
].hw_break
&& hw_breaks
[i
].slot
== slot
2228 && hw_breaks
[i
].hw_break
->trigger_type
2229 == PPC_BREAKPOINT_TRIGGER_EXECUTE
)
2234 *addr_p
= (CORE_ADDR
) (uintptr_t) siginfo
.si_addr
;
2239 ppc_linux_stopped_by_watchpoint (struct target_ops
*ops
)
2242 return ppc_linux_stopped_data_address (ops
, &addr
);
2246 ppc_linux_watchpoint_addr_within_range (struct target_ops
*target
,
2248 CORE_ADDR start
, int length
)
2252 if (have_ptrace_hwdebug_interface ()
2253 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2254 return start
<= addr
&& start
+ length
>= addr
;
2255 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2262 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2263 return start
<= addr
+ mask
&& start
+ length
- 1 >= addr
;
2266 /* Return the number of registers needed for a masked hardware watchpoint. */
2269 ppc_linux_masked_watch_num_registers (struct target_ops
*target
,
2270 CORE_ADDR addr
, CORE_ADDR mask
)
2272 if (!have_ptrace_hwdebug_interface ()
2273 || (hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_MASK
) == 0)
2275 else if ((mask
& 0xC0000000) != 0xC0000000)
2277 warning (_("The given mask covers kernel address space "
2278 "and cannot be used.\n"));
2287 ppc_linux_store_inferior_registers (struct target_ops
*ops
,
2288 struct regcache
*regcache
, int regno
)
2290 pid_t tid
= get_ptrace_pid (regcache_get_ptid (regcache
));
2293 store_register (regcache
, tid
, regno
);
2295 store_ppc_registers (regcache
, tid
);
2298 /* Functions for transferring registers between a gregset_t or fpregset_t
2299 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2300 by the ptrace interface, not the current program's ABI. Eg. if a
2301 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2302 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2305 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
2307 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2309 ppc_supply_gregset (regset
, regcache
, -1, gregsetp
, sizeof (*gregsetp
));
2313 fill_gregset (const struct regcache
*regcache
,
2314 gdb_gregset_t
*gregsetp
, int regno
)
2316 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2319 memset (gregsetp
, 0, sizeof (*gregsetp
));
2320 ppc_collect_gregset (regset
, regcache
, regno
, gregsetp
, sizeof (*gregsetp
));
2324 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
* fpregsetp
)
2326 const struct regset
*regset
= ppc_linux_fpregset ();
2328 ppc_supply_fpregset (regset
, regcache
, -1,
2329 fpregsetp
, sizeof (*fpregsetp
));
2333 fill_fpregset (const struct regcache
*regcache
,
2334 gdb_fpregset_t
*fpregsetp
, int regno
)
2336 const struct regset
*regset
= ppc_linux_fpregset ();
2338 ppc_collect_fpregset (regset
, regcache
, regno
,
2339 fpregsetp
, sizeof (*fpregsetp
));
2343 ppc_linux_target_wordsize (void)
2347 /* Check for 64-bit inferior process. This is the case when the host is
2348 64-bit, and in addition the top bit of the MSR register is set. */
2349 #ifdef __powerpc64__
2352 int tid
= ptid_get_lwp (inferior_ptid
);
2354 tid
= ptid_get_pid (inferior_ptid
);
2357 msr
= (long) ptrace (PTRACE_PEEKUSER
, tid
, PT_MSR
* 8, 0);
2358 if (errno
== 0 && ppc64_64bit_inferior_p (msr
))
2366 ppc_linux_auxv_parse (struct target_ops
*ops
, gdb_byte
**readptr
,
2367 gdb_byte
*endptr
, CORE_ADDR
*typep
, CORE_ADDR
*valp
)
2369 int sizeof_auxv_field
= ppc_linux_target_wordsize ();
2370 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
2371 gdb_byte
*ptr
= *readptr
;
2376 if (endptr
- ptr
< sizeof_auxv_field
* 2)
2379 *typep
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2380 ptr
+= sizeof_auxv_field
;
2381 *valp
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2382 ptr
+= sizeof_auxv_field
;
2388 static const struct target_desc
*
2389 ppc_linux_read_description (struct target_ops
*ops
)
2396 int tid
= ptid_get_lwp (inferior_ptid
);
2398 tid
= ptid_get_pid (inferior_ptid
);
2400 if (have_ptrace_getsetevrregs
)
2402 struct gdb_evrregset_t evrregset
;
2404 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, &evrregset
) >= 0)
2405 return tdesc_powerpc_e500l
;
2407 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2408 Anything else needs to be reported. */
2409 else if (errno
!= EIO
)
2410 perror_with_name (_("Unable to fetch SPE registers"));
2413 if (have_ptrace_getsetvsxregs
2414 && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_VSX
))
2416 gdb_vsxregset_t vsxregset
;
2418 if (ptrace (PTRACE_GETVSXREGS
, tid
, 0, &vsxregset
) >= 0)
2421 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2422 Anything else needs to be reported. */
2423 else if (errno
!= EIO
)
2424 perror_with_name (_("Unable to fetch VSX registers"));
2427 if (have_ptrace_getvrregs
2428 && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_ALTIVEC
))
2430 gdb_vrregset_t vrregset
;
2432 if (ptrace (PTRACE_GETVRREGS
, tid
, 0, &vrregset
) >= 0)
2435 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2436 Anything else needs to be reported. */
2437 else if (errno
!= EIO
)
2438 perror_with_name (_("Unable to fetch AltiVec registers"));
2441 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2442 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2443 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2444 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2445 half of the register are for Decimal Floating Point, we check if that
2446 feature is available to decide the size of the FPSCR. */
2447 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP
)
2450 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL
)
2453 if (ppc_linux_target_wordsize () == 8)
2456 return tdesc_powerpc_cell64l
;
2458 return isa205
? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l
;
2461 ? tdesc_powerpc_isa205_altivec64l
: tdesc_powerpc_altivec64l
;
2463 return isa205
? tdesc_powerpc_isa205_64l
: tdesc_powerpc_64l
;
2467 return tdesc_powerpc_cell32l
;
2469 return isa205
? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l
;
2471 return isa205
? tdesc_powerpc_isa205_altivec32l
: tdesc_powerpc_altivec32l
;
2473 return isa205
? tdesc_powerpc_isa205_32l
: tdesc_powerpc_32l
;
2476 void _initialize_ppc_linux_nat (void);
2479 _initialize_ppc_linux_nat (void)
2481 struct target_ops
*t
;
2483 /* Fill in the generic GNU/Linux methods. */
2484 t
= linux_target ();
2486 /* Add our register access methods. */
2487 t
->to_fetch_registers
= ppc_linux_fetch_inferior_registers
;
2488 t
->to_store_registers
= ppc_linux_store_inferior_registers
;
2490 /* Add our breakpoint/watchpoint methods. */
2491 t
->to_can_use_hw_breakpoint
= ppc_linux_can_use_hw_breakpoint
;
2492 t
->to_insert_hw_breakpoint
= ppc_linux_insert_hw_breakpoint
;
2493 t
->to_remove_hw_breakpoint
= ppc_linux_remove_hw_breakpoint
;
2494 t
->to_region_ok_for_hw_watchpoint
= ppc_linux_region_ok_for_hw_watchpoint
;
2495 t
->to_insert_watchpoint
= ppc_linux_insert_watchpoint
;
2496 t
->to_remove_watchpoint
= ppc_linux_remove_watchpoint
;
2497 t
->to_insert_mask_watchpoint
= ppc_linux_insert_mask_watchpoint
;
2498 t
->to_remove_mask_watchpoint
= ppc_linux_remove_mask_watchpoint
;
2499 t
->to_stopped_by_watchpoint
= ppc_linux_stopped_by_watchpoint
;
2500 t
->to_stopped_data_address
= ppc_linux_stopped_data_address
;
2501 t
->to_watchpoint_addr_within_range
= ppc_linux_watchpoint_addr_within_range
;
2502 t
->to_can_accel_watchpoint_condition
2503 = ppc_linux_can_accel_watchpoint_condition
;
2504 t
->to_masked_watch_num_registers
= ppc_linux_masked_watch_num_registers
;
2505 t
->to_ranged_break_num_registers
= ppc_linux_ranged_break_num_registers
;
2507 t
->to_read_description
= ppc_linux_read_description
;
2508 t
->to_auxv_parse
= ppc_linux_auxv_parse
;
2510 observer_attach_thread_exit (ppc_linux_thread_exit
);
2512 /* Register the target. */
2513 linux_nat_add_target (t
);
2514 linux_nat_set_new_thread (t
, ppc_linux_new_thread
);