1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
4 Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "gdb_string.h"
26 #include "gdbthread.h"
29 #include "gdb_assert.h"
31 #include "linux-nat.h"
34 #include <sys/types.h>
35 #include <sys/param.h>
38 #include <sys/ioctl.h>
41 #include <sys/procfs.h>
42 #include <sys/ptrace.h>
44 /* Prototypes for supply_gregset etc. */
47 #include "ppc-linux-tdep.h"
49 /* Required when using the AUXV. */
50 #include "elf/common.h"
53 /* This sometimes isn't defined. */
61 /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
62 If they aren't, we can provide them ourselves (their values are fixed
63 because they are part of the kernel ABI). They are used in the AT_HWCAP
65 #ifndef PPC_FEATURE_CELL
66 #define PPC_FEATURE_CELL 0x00010000
68 #ifndef PPC_FEATURE_BOOKE
69 #define PPC_FEATURE_BOOKE 0x00008000
71 #ifndef PPC_FEATURE_HAS_DFP
72 #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
75 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
76 configure time check. Some older glibc's (for instance 2.2.1)
77 don't have a specific powerpc version of ptrace.h, and fall back on
78 a generic one. In such cases, sys/ptrace.h defines
79 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
80 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
81 PTRACE_SETVRREGS to be. This also makes a configury check pretty
84 /* These definitions should really come from the glibc header files,
85 but Glibc doesn't know about the vrregs yet. */
86 #ifndef PTRACE_GETVRREGS
87 #define PTRACE_GETVRREGS 18
88 #define PTRACE_SETVRREGS 19
91 /* PTRACE requests for POWER7 VSX registers. */
92 #ifndef PTRACE_GETVSXREGS
93 #define PTRACE_GETVSXREGS 27
94 #define PTRACE_SETVSXREGS 28
97 /* Similarly for the ptrace requests for getting / setting the SPE
98 registers (ev0 -- ev31, acc, and spefscr). See the description of
99 gdb_evrregset_t for details. */
100 #ifndef PTRACE_GETEVRREGS
101 #define PTRACE_GETEVRREGS 20
102 #define PTRACE_SETEVRREGS 21
105 /* Similarly for the hardware watchpoint support. These requests are used
106 when the BookE kernel interface is not available. */
107 #ifndef PTRACE_GET_DEBUGREG
108 #define PTRACE_GET_DEBUGREG 25
110 #ifndef PTRACE_SET_DEBUGREG
111 #define PTRACE_SET_DEBUGREG 26
113 #ifndef PTRACE_GETSIGINFO
114 #define PTRACE_GETSIGINFO 0x4202
117 /* These requests are used when the BookE kernel interface is available.
118 It exposes the additional debug features of BookE processors, such as
119 ranged breakpoints and watchpoints and hardware-accelerated condition
121 #ifndef PPC_PTRACE_GETHWDBGINFO
123 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the new BookE
124 interface is not present in ptrace.h, so we'll have to pretty much include
125 it all here so that the code at least compiles on older systems. */
126 #define PPC_PTRACE_GETHWDBGINFO 0x89
127 #define PPC_PTRACE_SETHWDEBUG 0x88
128 #define PPC_PTRACE_DELHWDEBUG 0x87
130 struct ppc_debug_info
132 uint32_t version
; /* Only version 1 exists to date. */
133 uint32_t num_instruction_bps
;
134 uint32_t num_data_bps
;
135 uint32_t num_condition_regs
;
136 uint32_t data_bp_alignment
;
137 uint32_t sizeof_condition
; /* size of the DVC register. */
141 /* Features will have bits indicating whether there is support for: */
142 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
143 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
144 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
145 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
147 struct ppc_hw_breakpoint
149 uint32_t version
; /* currently, version must be 1 */
150 uint32_t trigger_type
; /* only some combinations allowed */
151 uint32_t addr_mode
; /* address match mode */
152 uint32_t condition_mode
; /* break/watchpoint condition flags */
153 uint64_t addr
; /* break/watchpoint address */
154 uint64_t addr2
; /* range end or mask */
155 uint64_t condition_value
; /* contents of the DVC register */
159 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
160 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
161 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
162 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
165 #define PPC_BREAKPOINT_MODE_EXACT 0x0
166 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
167 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
168 #define PPC_BREAKPOINT_MODE_MASK 0x3
170 /* Condition mode. */
171 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
172 #define PPC_BREAKPOINT_CONDITION_AND 0x1
173 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
174 #define PPC_BREAKPOINT_CONDITION_OR 0x2
175 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
176 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
177 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
178 #define PPC_BREAKPOINT_CONDITION_BE(n) \
179 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
180 #endif /* PPC_PTRACE_GETHWDBGINFO */
184 /* Similarly for the general-purpose (gp0 -- gp31)
185 and floating-point registers (fp0 -- fp31). */
186 #ifndef PTRACE_GETREGS
187 #define PTRACE_GETREGS 12
189 #ifndef PTRACE_SETREGS
190 #define PTRACE_SETREGS 13
192 #ifndef PTRACE_GETFPREGS
193 #define PTRACE_GETFPREGS 14
195 #ifndef PTRACE_SETFPREGS
196 #define PTRACE_SETFPREGS 15
199 /* This oddity is because the Linux kernel defines elf_vrregset_t as
200 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
201 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
202 the vrsave as an extra 4 bytes at the end. I opted for creating a
203 flat array of chars, so that it is easier to manipulate for gdb.
205 There are 32 vector registers 16 bytes longs, plus a VSCR register
206 which is only 4 bytes long, but is fetched as a 16 bytes
207 quantity. Up to here we have the elf_vrregset_t structure.
208 Appended to this there is space for the VRSAVE register: 4 bytes.
209 Even though this vrsave register is not included in the regset
210 typedef, it is handled by the ptrace requests.
212 Note that GNU/Linux doesn't support little endian PPC hardware,
213 therefore the offset at which the real value of the VSCR register
214 is located will be always 12 bytes.
216 The layout is like this (where x is the actual value of the vscr reg): */
220 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
221 <-------> <-------><-------><->
226 #define SIZEOF_VRREGS 33*16+4
228 typedef char gdb_vrregset_t
[SIZEOF_VRREGS
];
230 /* This is the layout of the POWER7 VSX registers and the way they overlap
231 with the existing FPR and VMX registers.
233 VSR doubleword 0 VSR doubleword 1
234 ----------------------------------------------------------------
236 ----------------------------------------------------------------
238 ----------------------------------------------------------------
241 ----------------------------------------------------------------
242 VSR[30] | FPR[30] | |
243 ----------------------------------------------------------------
244 VSR[31] | FPR[31] | |
245 ----------------------------------------------------------------
247 ----------------------------------------------------------------
249 ----------------------------------------------------------------
252 ----------------------------------------------------------------
254 ----------------------------------------------------------------
256 ----------------------------------------------------------------
258 VSX has 64 128bit registers. The first 32 registers overlap with
259 the FP registers (doubleword 0) and hence extend them with additional
260 64 bits (doubleword 1). The other 32 regs overlap with the VMX
262 #define SIZEOF_VSXREGS 32*8
264 typedef char gdb_vsxregset_t
[SIZEOF_VSXREGS
];
266 /* On PPC processors that support the Signal Processing Extension
267 (SPE) APU, the general-purpose registers are 64 bits long.
268 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
269 ptrace calls only access the lower half of each register, to allow
270 them to behave the same way they do on non-SPE systems. There's a
271 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
272 read and write the top halves of all the general-purpose registers
273 at once, along with some SPE-specific registers.
275 GDB itself continues to claim the general-purpose registers are 32
276 bits long. It has unnamed raw registers that hold the upper halves
277 of the gprs, and the full 64-bit SIMD views of the registers,
278 'ev0' -- 'ev31', are pseudo-registers that splice the top and
279 bottom halves together.
281 This is the structure filled in by PTRACE_GETEVRREGS and written to
282 the inferior's registers by PTRACE_SETEVRREGS. */
283 struct gdb_evrregset_t
285 unsigned long evr
[32];
286 unsigned long long acc
;
287 unsigned long spefscr
;
290 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
291 PTRACE_SETVSXREGS requests, for reading and writing the VSX
292 POWER7 registers 0 through 31. Zero if we've tried one of them and
293 gotten an error. Note that VSX registers 32 through 63 overlap
294 with VR registers 0 through 31. */
295 int have_ptrace_getsetvsxregs
= 1;
297 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
298 PTRACE_SETVRREGS requests, for reading and writing the Altivec
299 registers. Zero if we've tried one of them and gotten an
301 int have_ptrace_getvrregs
= 1;
303 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
304 PTRACE_SETEVRREGS requests, for reading and writing the SPE
305 registers. Zero if we've tried one of them and gotten an
307 int have_ptrace_getsetevrregs
= 1;
309 /* Non-zero if our kernel may support the PTRACE_GETREGS and
310 PTRACE_SETREGS requests, for reading and writing the
311 general-purpose registers. Zero if we've tried one of
312 them and gotten an error. */
313 int have_ptrace_getsetregs
= 1;
315 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
316 PTRACE_SETFPREGS requests, for reading and writing the
317 floating-pointers registers. Zero if we've tried one of
318 them and gotten an error. */
319 int have_ptrace_getsetfpregs
= 1;
322 /* registers layout, as presented by the ptrace interface:
323 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
324 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
325 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
326 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
327 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
328 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
329 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
330 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
331 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
332 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
333 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
334 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
335 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
339 ppc_register_u_addr (struct gdbarch
*gdbarch
, int regno
)
342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
343 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
344 interface, and not the wordsize of the program's ABI. */
345 int wordsize
= sizeof (long);
347 /* General purpose registers occupy 1 slot each in the buffer. */
348 if (regno
>= tdep
->ppc_gp0_regnum
349 && regno
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
350 u_addr
= ((regno
- tdep
->ppc_gp0_regnum
+ PT_R0
) * wordsize
);
352 /* Floating point regs: eight bytes each in both 32- and 64-bit
353 ptrace interfaces. Thus, two slots each in 32-bit interface, one
354 slot each in 64-bit interface. */
355 if (tdep
->ppc_fp0_regnum
>= 0
356 && regno
>= tdep
->ppc_fp0_regnum
357 && regno
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
358 u_addr
= (PT_FPR0
* wordsize
) + ((regno
- tdep
->ppc_fp0_regnum
) * 8);
360 /* UISA special purpose registers: 1 slot each. */
361 if (regno
== gdbarch_pc_regnum (gdbarch
))
362 u_addr
= PT_NIP
* wordsize
;
363 if (regno
== tdep
->ppc_lr_regnum
)
364 u_addr
= PT_LNK
* wordsize
;
365 if (regno
== tdep
->ppc_cr_regnum
)
366 u_addr
= PT_CCR
* wordsize
;
367 if (regno
== tdep
->ppc_xer_regnum
)
368 u_addr
= PT_XER
* wordsize
;
369 if (regno
== tdep
->ppc_ctr_regnum
)
370 u_addr
= PT_CTR
* wordsize
;
372 if (regno
== tdep
->ppc_mq_regnum
)
373 u_addr
= PT_MQ
* wordsize
;
375 if (regno
== tdep
->ppc_ps_regnum
)
376 u_addr
= PT_MSR
* wordsize
;
377 if (regno
== PPC_ORIG_R3_REGNUM
)
378 u_addr
= PT_ORIG_R3
* wordsize
;
379 if (regno
== PPC_TRAP_REGNUM
)
380 u_addr
= PT_TRAP
* wordsize
;
381 if (tdep
->ppc_fpscr_regnum
>= 0
382 && regno
== tdep
->ppc_fpscr_regnum
)
384 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
385 kernel headers incorrectly contained the 32-bit definition of
386 PT_FPSCR. For the 32-bit definition, floating-point
387 registers occupy two 32-bit "slots", and the FPSCR lives in
388 the second half of such a slot-pair (hence +1). For 64-bit,
389 the FPSCR instead occupies the full 64-bit 2-word-slot and
390 hence no adjustment is necessary. Hack around this. */
391 if (wordsize
== 8 && PT_FPSCR
== (48 + 32 + 1))
392 u_addr
= (48 + 32) * wordsize
;
393 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
394 slot and not just its second word. The PT_FPSCR supplied when
395 GDB is compiled as a 32-bit app doesn't reflect this. */
396 else if (wordsize
== 4 && register_size (gdbarch
, regno
) == 8
397 && PT_FPSCR
== (48 + 2*32 + 1))
398 u_addr
= (48 + 2*32) * wordsize
;
400 u_addr
= PT_FPSCR
* wordsize
;
405 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
406 registers set mechanism, as opposed to the interface for all the
407 other registers, that stores/fetches each register individually. */
409 fetch_vsx_register (struct regcache
*regcache
, int tid
, int regno
)
412 gdb_vsxregset_t regs
;
413 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
414 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
415 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
417 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
422 have_ptrace_getsetvsxregs
= 0;
425 perror_with_name (_("Unable to fetch VSX register"));
428 regcache_raw_supply (regcache
, regno
,
429 regs
+ (regno
- tdep
->ppc_vsr0_upper_regnum
)
433 /* The Linux kernel ptrace interface for AltiVec registers uses the
434 registers set mechanism, as opposed to the interface for all the
435 other registers, that stores/fetches each register individually. */
437 fetch_altivec_register (struct regcache
*regcache
, int tid
, int regno
)
442 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
443 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
444 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
446 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
451 have_ptrace_getvrregs
= 0;
454 perror_with_name (_("Unable to fetch AltiVec register"));
457 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
458 long on the hardware. We deal only with the lower 4 bytes of the
459 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
460 there is no need to define an offset for it. */
461 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
462 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
464 regcache_raw_supply (regcache
, regno
,
466 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
469 /* Fetch the top 32 bits of TID's general-purpose registers and the
470 SPE-specific registers, and place the results in EVRREGSET. If we
471 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
474 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
475 PTRACE_SETEVRREGS requests are supported is isolated here, and in
476 set_spe_registers. */
478 get_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
480 if (have_ptrace_getsetevrregs
)
482 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, evrregset
) >= 0)
486 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
487 we just return zeros. */
489 have_ptrace_getsetevrregs
= 0;
491 /* Anything else needs to be reported. */
492 perror_with_name (_("Unable to fetch SPE registers"));
496 memset (evrregset
, 0, sizeof (*evrregset
));
499 /* Supply values from TID for SPE-specific raw registers: the upper
500 halves of the GPRs, the accumulator, and the spefscr. REGNO must
501 be the number of an upper half register, acc, spefscr, or -1 to
502 supply the values of all registers. */
504 fetch_spe_register (struct regcache
*regcache
, int tid
, int regno
)
506 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
508 struct gdb_evrregset_t evrregs
;
510 gdb_assert (sizeof (evrregs
.evr
[0])
511 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
512 gdb_assert (sizeof (evrregs
.acc
)
513 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
514 gdb_assert (sizeof (evrregs
.spefscr
)
515 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
517 get_spe_registers (tid
, &evrregs
);
523 for (i
= 0; i
< ppc_num_gprs
; i
++)
524 regcache_raw_supply (regcache
, tdep
->ppc_ev0_upper_regnum
+ i
,
527 else if (tdep
->ppc_ev0_upper_regnum
<= regno
528 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
529 regcache_raw_supply (regcache
, regno
,
530 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
533 || regno
== tdep
->ppc_acc_regnum
)
534 regcache_raw_supply (regcache
, tdep
->ppc_acc_regnum
, &evrregs
.acc
);
537 || regno
== tdep
->ppc_spefscr_regnum
)
538 regcache_raw_supply (regcache
, tdep
->ppc_spefscr_regnum
,
543 fetch_register (struct regcache
*regcache
, int tid
, int regno
)
545 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
546 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
547 /* This isn't really an address. But ptrace thinks of it as one. */
548 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
549 int bytes_transferred
;
550 unsigned int offset
; /* Offset of registers within the u area. */
551 char buf
[MAX_REGISTER_SIZE
];
553 if (altivec_register_p (gdbarch
, regno
))
555 /* If this is the first time through, or if it is not the first
556 time through, and we have comfirmed that there is kernel
557 support for such a ptrace request, then go and fetch the
559 if (have_ptrace_getvrregs
)
561 fetch_altivec_register (regcache
, tid
, regno
);
564 /* If we have discovered that there is no ptrace support for
565 AltiVec registers, fall through and return zeroes, because
566 regaddr will be -1 in this case. */
568 if (vsx_register_p (gdbarch
, regno
))
570 if (have_ptrace_getsetvsxregs
)
572 fetch_vsx_register (regcache
, tid
, regno
);
576 else if (spe_register_p (gdbarch
, regno
))
578 fetch_spe_register (regcache
, tid
, regno
);
584 memset (buf
, '\0', register_size (gdbarch
, regno
)); /* Supply zeroes */
585 regcache_raw_supply (regcache
, regno
, buf
);
589 /* Read the raw register using sizeof(long) sized chunks. On a
590 32-bit platform, 64-bit floating-point registers will require two
592 for (bytes_transferred
= 0;
593 bytes_transferred
< register_size (gdbarch
, regno
);
594 bytes_transferred
+= sizeof (long))
597 *(long *) &buf
[bytes_transferred
]
598 = ptrace (PTRACE_PEEKUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, 0);
599 regaddr
+= sizeof (long);
603 sprintf (message
, "reading register %s (#%d)",
604 gdbarch_register_name (gdbarch
, regno
), regno
);
605 perror_with_name (message
);
609 /* Now supply the register. Keep in mind that the regcache's idea
610 of the register's size may not be a multiple of sizeof
612 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
614 /* Little-endian values are always found at the left end of the
615 bytes transferred. */
616 regcache_raw_supply (regcache
, regno
, buf
);
618 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
620 /* Big-endian values are found at the right end of the bytes
622 size_t padding
= (bytes_transferred
- register_size (gdbarch
, regno
));
623 regcache_raw_supply (regcache
, regno
, buf
+ padding
);
626 internal_error (__FILE__
, __LINE__
,
627 _("fetch_register: unexpected byte order: %d"),
628 gdbarch_byte_order (gdbarch
));
632 supply_vsxregset (struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
635 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
636 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
637 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
639 for (i
= 0; i
< ppc_num_vshrs
; i
++)
641 regcache_raw_supply (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
642 *vsxregsetp
+ i
* vsxregsize
);
647 supply_vrregset (struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
650 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
651 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
652 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
653 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
654 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
656 for (i
= 0; i
< num_of_vrregs
; i
++)
658 /* The last 2 registers of this set are only 32 bit long, not
659 128. However an offset is necessary only for VSCR because it
660 occupies a whole vector, while VRSAVE occupies a full 4 bytes
662 if (i
== (num_of_vrregs
- 2))
663 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
664 *vrregsetp
+ i
* vrregsize
+ offset
);
666 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
667 *vrregsetp
+ i
* vrregsize
);
672 fetch_vsx_registers (struct regcache
*regcache
, int tid
)
675 gdb_vsxregset_t regs
;
677 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
682 have_ptrace_getsetvsxregs
= 0;
685 perror_with_name (_("Unable to fetch VSX registers"));
687 supply_vsxregset (regcache
, ®s
);
691 fetch_altivec_registers (struct regcache
*regcache
, int tid
)
696 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
701 have_ptrace_getvrregs
= 0;
704 perror_with_name (_("Unable to fetch AltiVec registers"));
706 supply_vrregset (regcache
, ®s
);
709 /* This function actually issues the request to ptrace, telling
710 it to get all general-purpose registers and put them into the
713 If the ptrace request does not exist, this function returns 0
714 and properly sets the have_ptrace_* flag. If the request fails,
715 this function calls perror_with_name. Otherwise, if the request
716 succeeds, then the regcache gets filled and 1 is returned. */
718 fetch_all_gp_regs (struct regcache
*regcache
, int tid
)
720 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
721 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
722 gdb_gregset_t gregset
;
724 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
728 have_ptrace_getsetregs
= 0;
731 perror_with_name (_("Couldn't get general-purpose registers."));
734 supply_gregset (regcache
, (const gdb_gregset_t
*) &gregset
);
739 /* This is a wrapper for the fetch_all_gp_regs function. It is
740 responsible for verifying if this target has the ptrace request
741 that can be used to fetch all general-purpose registers at one
742 shot. If it doesn't, then we should fetch them using the
743 old-fashioned way, which is to iterate over the registers and
744 request them one by one. */
746 fetch_gp_regs (struct regcache
*regcache
, int tid
)
748 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
749 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
752 if (have_ptrace_getsetregs
)
753 if (fetch_all_gp_regs (regcache
, tid
))
756 /* If we've hit this point, it doesn't really matter which
757 architecture we are using. We just need to read the
758 registers in the "old-fashioned way". */
759 for (i
= 0; i
< ppc_num_gprs
; i
++)
760 fetch_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
763 /* This function actually issues the request to ptrace, telling
764 it to get all floating-point registers and put them into the
767 If the ptrace request does not exist, this function returns 0
768 and properly sets the have_ptrace_* flag. If the request fails,
769 this function calls perror_with_name. Otherwise, if the request
770 succeeds, then the regcache gets filled and 1 is returned. */
772 fetch_all_fp_regs (struct regcache
*regcache
, int tid
)
774 gdb_fpregset_t fpregs
;
776 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
780 have_ptrace_getsetfpregs
= 0;
783 perror_with_name (_("Couldn't get floating-point registers."));
786 supply_fpregset (regcache
, (const gdb_fpregset_t
*) &fpregs
);
791 /* This is a wrapper for the fetch_all_fp_regs function. It is
792 responsible for verifying if this target has the ptrace request
793 that can be used to fetch all floating-point registers at one
794 shot. If it doesn't, then we should fetch them using the
795 old-fashioned way, which is to iterate over the registers and
796 request them one by one. */
798 fetch_fp_regs (struct regcache
*regcache
, int tid
)
800 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
801 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
804 if (have_ptrace_getsetfpregs
)
805 if (fetch_all_fp_regs (regcache
, tid
))
808 /* If we've hit this point, it doesn't really matter which
809 architecture we are using. We just need to read the
810 registers in the "old-fashioned way". */
811 for (i
= 0; i
< ppc_num_fprs
; i
++)
812 fetch_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
816 fetch_ppc_registers (struct regcache
*regcache
, int tid
)
819 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
820 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
822 fetch_gp_regs (regcache
, tid
);
823 if (tdep
->ppc_fp0_regnum
>= 0)
824 fetch_fp_regs (regcache
, tid
);
825 fetch_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
826 if (tdep
->ppc_ps_regnum
!= -1)
827 fetch_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
828 if (tdep
->ppc_cr_regnum
!= -1)
829 fetch_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
830 if (tdep
->ppc_lr_regnum
!= -1)
831 fetch_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
832 if (tdep
->ppc_ctr_regnum
!= -1)
833 fetch_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
834 if (tdep
->ppc_xer_regnum
!= -1)
835 fetch_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
836 if (tdep
->ppc_mq_regnum
!= -1)
837 fetch_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
838 if (ppc_linux_trap_reg_p (gdbarch
))
840 fetch_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
841 fetch_register (regcache
, tid
, PPC_TRAP_REGNUM
);
843 if (tdep
->ppc_fpscr_regnum
!= -1)
844 fetch_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
845 if (have_ptrace_getvrregs
)
846 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
847 fetch_altivec_registers (regcache
, tid
);
848 if (have_ptrace_getsetvsxregs
)
849 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
850 fetch_vsx_registers (regcache
, tid
);
851 if (tdep
->ppc_ev0_upper_regnum
>= 0)
852 fetch_spe_register (regcache
, tid
, -1);
855 /* Fetch registers from the child process. Fetch all registers if
856 regno == -1, otherwise fetch all general registers or all floating
857 point registers depending upon the value of regno. */
859 ppc_linux_fetch_inferior_registers (struct target_ops
*ops
,
860 struct regcache
*regcache
, int regno
)
862 /* Overload thread id onto process id. */
863 int tid
= TIDGET (inferior_ptid
);
865 /* No thread id, just use process id. */
867 tid
= PIDGET (inferior_ptid
);
870 fetch_ppc_registers (regcache
, tid
);
872 fetch_register (regcache
, tid
, regno
);
875 /* Store one VSX register. */
877 store_vsx_register (const struct regcache
*regcache
, int tid
, int regno
)
880 gdb_vsxregset_t regs
;
881 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
882 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
883 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
885 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
890 have_ptrace_getsetvsxregs
= 0;
893 perror_with_name (_("Unable to fetch VSX register"));
896 regcache_raw_collect (regcache
, regno
, regs
+
897 (regno
- tdep
->ppc_vsr0_upper_regnum
) * vsxregsize
);
899 ret
= ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
);
901 perror_with_name (_("Unable to store VSX register"));
904 /* Store one register. */
906 store_altivec_register (const struct regcache
*regcache
, int tid
, int regno
)
911 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
912 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
913 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
915 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
920 have_ptrace_getvrregs
= 0;
923 perror_with_name (_("Unable to fetch AltiVec register"));
926 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
927 long on the hardware. */
928 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
929 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
931 regcache_raw_collect (regcache
, regno
,
933 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
935 ret
= ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
);
937 perror_with_name (_("Unable to store AltiVec register"));
940 /* Assuming TID referrs to an SPE process, set the top halves of TID's
941 general-purpose registers and its SPE-specific registers to the
942 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
945 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
946 PTRACE_SETEVRREGS requests are supported is isolated here, and in
947 get_spe_registers. */
949 set_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
951 if (have_ptrace_getsetevrregs
)
953 if (ptrace (PTRACE_SETEVRREGS
, tid
, 0, evrregset
) >= 0)
957 /* EIO means that the PTRACE_SETEVRREGS request isn't
958 supported; we fail silently, and don't try the call
961 have_ptrace_getsetevrregs
= 0;
963 /* Anything else needs to be reported. */
964 perror_with_name (_("Unable to set SPE registers"));
969 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
970 If REGNO is -1, write the values of all the SPE-specific
973 store_spe_register (const struct regcache
*regcache
, int tid
, int regno
)
975 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
976 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
977 struct gdb_evrregset_t evrregs
;
979 gdb_assert (sizeof (evrregs
.evr
[0])
980 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
981 gdb_assert (sizeof (evrregs
.acc
)
982 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
983 gdb_assert (sizeof (evrregs
.spefscr
)
984 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
987 /* Since we're going to write out every register, the code below
988 should store to every field of evrregs; if that doesn't happen,
989 make it obvious by initializing it with suspicious values. */
990 memset (&evrregs
, 42, sizeof (evrregs
));
992 /* We can only read and write the entire EVR register set at a
993 time, so to write just a single register, we do a
994 read-modify-write maneuver. */
995 get_spe_registers (tid
, &evrregs
);
1001 for (i
= 0; i
< ppc_num_gprs
; i
++)
1002 regcache_raw_collect (regcache
,
1003 tdep
->ppc_ev0_upper_regnum
+ i
,
1006 else if (tdep
->ppc_ev0_upper_regnum
<= regno
1007 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1008 regcache_raw_collect (regcache
, regno
,
1009 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
1012 || regno
== tdep
->ppc_acc_regnum
)
1013 regcache_raw_collect (regcache
,
1014 tdep
->ppc_acc_regnum
,
1018 || regno
== tdep
->ppc_spefscr_regnum
)
1019 regcache_raw_collect (regcache
,
1020 tdep
->ppc_spefscr_regnum
,
1023 /* Write back the modified register set. */
1024 set_spe_registers (tid
, &evrregs
);
1028 store_register (const struct regcache
*regcache
, int tid
, int regno
)
1030 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1031 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1032 /* This isn't really an address. But ptrace thinks of it as one. */
1033 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
1035 size_t bytes_to_transfer
;
1036 char buf
[MAX_REGISTER_SIZE
];
1038 if (altivec_register_p (gdbarch
, regno
))
1040 store_altivec_register (regcache
, tid
, regno
);
1043 if (vsx_register_p (gdbarch
, regno
))
1045 store_vsx_register (regcache
, tid
, regno
);
1048 else if (spe_register_p (gdbarch
, regno
))
1050 store_spe_register (regcache
, tid
, regno
);
1057 /* First collect the register. Keep in mind that the regcache's
1058 idea of the register's size may not be a multiple of sizeof
1060 memset (buf
, 0, sizeof buf
);
1061 bytes_to_transfer
= align_up (register_size (gdbarch
, regno
), sizeof (long));
1062 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1064 /* Little-endian values always sit at the left end of the buffer. */
1065 regcache_raw_collect (regcache
, regno
, buf
);
1067 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1069 /* Big-endian values sit at the right end of the buffer. */
1070 size_t padding
= (bytes_to_transfer
- register_size (gdbarch
, regno
));
1071 regcache_raw_collect (regcache
, regno
, buf
+ padding
);
1074 for (i
= 0; i
< bytes_to_transfer
; i
+= sizeof (long))
1077 ptrace (PTRACE_POKEUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
,
1079 regaddr
+= sizeof (long);
1082 && (regno
== tdep
->ppc_fpscr_regnum
1083 || regno
== PPC_ORIG_R3_REGNUM
1084 || regno
== PPC_TRAP_REGNUM
))
1086 /* Some older kernel versions don't allow fpscr, orig_r3
1087 or trap to be written. */
1094 sprintf (message
, "writing register %s (#%d)",
1095 gdbarch_register_name (gdbarch
, regno
), regno
);
1096 perror_with_name (message
);
1102 fill_vsxregset (const struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
1105 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1106 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1107 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
1109 for (i
= 0; i
< ppc_num_vshrs
; i
++)
1110 regcache_raw_collect (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
1111 *vsxregsetp
+ i
* vsxregsize
);
1115 fill_vrregset (const struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
1118 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1119 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1120 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
1121 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
1122 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
1124 for (i
= 0; i
< num_of_vrregs
; i
++)
1126 /* The last 2 registers of this set are only 32 bit long, not
1127 128, but only VSCR is fetched as a 16 bytes quantity. */
1128 if (i
== (num_of_vrregs
- 2))
1129 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1130 *vrregsetp
+ i
* vrregsize
+ offset
);
1132 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1133 *vrregsetp
+ i
* vrregsize
);
1138 store_vsx_registers (const struct regcache
*regcache
, int tid
)
1141 gdb_vsxregset_t regs
;
1143 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
1148 have_ptrace_getsetvsxregs
= 0;
1151 perror_with_name (_("Couldn't get VSX registers"));
1154 fill_vsxregset (regcache
, ®s
);
1156 if (ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
) < 0)
1157 perror_with_name (_("Couldn't write VSX registers"));
1161 store_altivec_registers (const struct regcache
*regcache
, int tid
)
1164 gdb_vrregset_t regs
;
1166 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
1171 have_ptrace_getvrregs
= 0;
1174 perror_with_name (_("Couldn't get AltiVec registers"));
1177 fill_vrregset (regcache
, ®s
);
1179 if (ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
) < 0)
1180 perror_with_name (_("Couldn't write AltiVec registers"));
1183 /* This function actually issues the request to ptrace, telling
1184 it to store all general-purpose registers present in the specified
1187 If the ptrace request does not exist, this function returns 0
1188 and properly sets the have_ptrace_* flag. If the request fails,
1189 this function calls perror_with_name. Otherwise, if the request
1190 succeeds, then the regcache is stored and 1 is returned. */
1192 store_all_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1194 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1196 gdb_gregset_t gregset
;
1198 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
1202 have_ptrace_getsetregs
= 0;
1205 perror_with_name (_("Couldn't get general-purpose registers."));
1208 fill_gregset (regcache
, &gregset
, regno
);
1210 if (ptrace (PTRACE_SETREGS
, tid
, 0, (void *) &gregset
) < 0)
1214 have_ptrace_getsetregs
= 0;
1217 perror_with_name (_("Couldn't set general-purpose registers."));
1223 /* This is a wrapper for the store_all_gp_regs function. It is
1224 responsible for verifying if this target has the ptrace request
1225 that can be used to store all general-purpose registers at one
1226 shot. If it doesn't, then we should store them using the
1227 old-fashioned way, which is to iterate over the registers and
1228 store them one by one. */
1230 store_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1232 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1233 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1236 if (have_ptrace_getsetregs
)
1237 if (store_all_gp_regs (regcache
, tid
, regno
))
1240 /* If we hit this point, it doesn't really matter which
1241 architecture we are using. We just need to store the
1242 registers in the "old-fashioned way". */
1243 for (i
= 0; i
< ppc_num_gprs
; i
++)
1244 store_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
1247 /* This function actually issues the request to ptrace, telling
1248 it to store all floating-point registers present in the specified
1251 If the ptrace request does not exist, this function returns 0
1252 and properly sets the have_ptrace_* flag. If the request fails,
1253 this function calls perror_with_name. Otherwise, if the request
1254 succeeds, then the regcache is stored and 1 is returned. */
1256 store_all_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1258 gdb_fpregset_t fpregs
;
1260 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1264 have_ptrace_getsetfpregs
= 0;
1267 perror_with_name (_("Couldn't get floating-point registers."));
1270 fill_fpregset (regcache
, &fpregs
, regno
);
1272 if (ptrace (PTRACE_SETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1276 have_ptrace_getsetfpregs
= 0;
1279 perror_with_name (_("Couldn't set floating-point registers."));
1285 /* This is a wrapper for the store_all_fp_regs function. It is
1286 responsible for verifying if this target has the ptrace request
1287 that can be used to store all floating-point registers at one
1288 shot. If it doesn't, then we should store them using the
1289 old-fashioned way, which is to iterate over the registers and
1290 store them one by one. */
1292 store_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1294 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1295 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1298 if (have_ptrace_getsetfpregs
)
1299 if (store_all_fp_regs (regcache
, tid
, regno
))
1302 /* If we hit this point, it doesn't really matter which
1303 architecture we are using. We just need to store the
1304 registers in the "old-fashioned way". */
1305 for (i
= 0; i
< ppc_num_fprs
; i
++)
1306 store_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
1310 store_ppc_registers (const struct regcache
*regcache
, int tid
)
1313 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1314 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1316 store_gp_regs (regcache
, tid
, -1);
1317 if (tdep
->ppc_fp0_regnum
>= 0)
1318 store_fp_regs (regcache
, tid
, -1);
1319 store_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
1320 if (tdep
->ppc_ps_regnum
!= -1)
1321 store_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
1322 if (tdep
->ppc_cr_regnum
!= -1)
1323 store_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
1324 if (tdep
->ppc_lr_regnum
!= -1)
1325 store_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
1326 if (tdep
->ppc_ctr_regnum
!= -1)
1327 store_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
1328 if (tdep
->ppc_xer_regnum
!= -1)
1329 store_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
1330 if (tdep
->ppc_mq_regnum
!= -1)
1331 store_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
1332 if (tdep
->ppc_fpscr_regnum
!= -1)
1333 store_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
1334 if (ppc_linux_trap_reg_p (gdbarch
))
1336 store_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
1337 store_register (regcache
, tid
, PPC_TRAP_REGNUM
);
1339 if (have_ptrace_getvrregs
)
1340 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
1341 store_altivec_registers (regcache
, tid
);
1342 if (have_ptrace_getsetvsxregs
)
1343 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
1344 store_vsx_registers (regcache
, tid
);
1345 if (tdep
->ppc_ev0_upper_regnum
>= 0)
1346 store_spe_register (regcache
, tid
, -1);
1349 /* Fetch the AT_HWCAP entry from the aux vector. */
1350 unsigned long ppc_linux_get_hwcap (void)
1354 if (target_auxv_search (¤t_target
, AT_HWCAP
, &field
))
1355 return (unsigned long) field
;
1360 /* The cached DABR value, to install in new threads.
1361 This variable is used when we are dealing with non-BookE
1363 static long saved_dabr_value
;
1365 /* Global structure that will store information about the available
1366 features on this BookE processor. */
1367 static struct ppc_debug_info booke_debug_info
;
1369 /* Global variable that holds the maximum number of slots that the
1370 kernel will use. This is only used when the processor is BookE. */
1371 static size_t max_slots_number
= 0;
1373 struct hw_break_tuple
1376 struct ppc_hw_breakpoint
*hw_break
;
1379 /* This is an internal VEC created to store information about *points inserted
1380 for each thread. This is used for BookE processors. */
1381 typedef struct thread_points
1383 /* The TID to which this *point relates. */
1385 /* Information about the *point, such as its address, type, etc.
1387 Each element inside this vector corresponds to a hardware
1388 breakpoint or watchpoint in the thread represented by TID. The maximum
1389 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1390 the tuple is NULL, then the position in the vector is free. */
1391 struct hw_break_tuple
*hw_breaks
;
1393 DEF_VEC_P (thread_points_p
);
1395 VEC(thread_points_p
) *ppc_threads
= NULL
;
1397 /* The version of the kernel interface that we will use if the processor is
1399 #define PPC_DEBUG_CURRENT_VERSION 1
1401 /* Returns non-zero if we support the ptrace interface which enables
1402 booke debugging resources. */
1404 have_ptrace_booke_interface (void)
1406 static int have_ptrace_booke_interface
= -1;
1408 if (have_ptrace_booke_interface
== -1)
1412 tid
= TIDGET (inferior_ptid
);
1414 tid
= PIDGET (inferior_ptid
);
1416 /* Check for kernel support for BOOKE debug registers. */
1417 if (ptrace (PPC_PTRACE_GETHWDBGINFO
, tid
, 0, &booke_debug_info
) >= 0)
1419 have_ptrace_booke_interface
= 1;
1420 max_slots_number
= booke_debug_info
.num_instruction_bps
1421 + booke_debug_info
.num_data_bps
1422 + booke_debug_info
.num_condition_regs
;
1426 /* Old school interface and no BOOKE debug registers support. */
1427 have_ptrace_booke_interface
= 0;
1428 memset (&booke_debug_info
, 0, sizeof (struct ppc_debug_info
));
1432 return have_ptrace_booke_interface
;
1436 ppc_linux_can_use_hw_breakpoint (int type
, int cnt
, int ot
)
1438 int total_hw_wp
, total_hw_bp
;
1440 if (have_ptrace_booke_interface ())
1442 /* For PPC BookE processors, the number of available hardware
1443 watchpoints and breakpoints is stored at the booke_debug_info
1445 total_hw_bp
= booke_debug_info
.num_instruction_bps
;
1446 total_hw_wp
= booke_debug_info
.num_data_bps
;
1450 /* For PPC server processors, we accept 1 hardware watchpoint and 0
1451 hardware breakpoints. */
1456 if (type
== bp_hardware_watchpoint
|| type
== bp_read_watchpoint
1457 || type
== bp_access_watchpoint
|| type
== bp_watchpoint
)
1459 if (cnt
> total_hw_wp
)
1462 else if (type
== bp_hardware_breakpoint
)
1464 if (cnt
> total_hw_bp
)
1468 if (!have_ptrace_booke_interface ())
1471 ptid_t ptid
= inferior_ptid
;
1473 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1474 and whether the target has DABR. If either answer is no, the
1475 ptrace call will return -1. Fail in that case. */
1476 tid
= TIDGET (ptid
);
1478 tid
= PIDGET (ptid
);
1480 if (ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, 0) == -1)
1488 ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
1490 /* Handle sub-8-byte quantities. */
1494 /* The new BookE ptrace interface tells if there are alignment restrictions
1495 for watchpoints in the processors. In that case, we use that information
1496 to determine the hardcoded watchable region for watchpoints. */
1497 if (have_ptrace_booke_interface ())
1499 /* DAC-based processors (i.e., embedded processors), like the PowerPC 440
1500 have ranged watchpoints and can watch any access within an arbitrary
1501 memory region. This is useful to watch arrays and structs, for
1502 instance. It takes two hardware watchpoints though. */
1504 && booke_debug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
)
1506 else if (booke_debug_info
.data_bp_alignment
1507 && (addr
+ len
> (addr
& ~(booke_debug_info
.data_bp_alignment
- 1))
1508 + booke_debug_info
.data_bp_alignment
))
1511 /* addr+len must fall in the 8 byte watchable region for DABR-based
1512 processors (i.e., server processors). Without the new BookE ptrace
1513 interface, DAC-based processors (i.e., embedded processors) will use
1514 addresses aligned to 4-bytes due to the way the read/write flags are
1515 passed in the old ptrace interface. */
1516 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1517 && (addr
+ len
) > (addr
& ~3) + 4)
1518 || (addr
+ len
) > (addr
& ~7) + 8)
1524 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1526 booke_cmp_hw_point (struct ppc_hw_breakpoint
*a
, struct ppc_hw_breakpoint
*b
)
1528 return (a
->trigger_type
== b
->trigger_type
1529 && a
->addr_mode
== b
->addr_mode
1530 && a
->condition_mode
== b
->condition_mode
1531 && a
->addr
== b
->addr
1532 && a
->addr2
== b
->addr2
1533 && a
->condition_value
== b
->condition_value
);
1536 /* This function can be used to retrieve a thread_points by the TID of the
1537 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1538 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1539 provided TID will be created and returned. */
1540 static struct thread_points
*
1541 booke_find_thread_points_by_tid (int tid
, int alloc_new
)
1544 struct thread_points
*t
;
1546 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, t
); i
++)
1552 /* Do we need to allocate a new point_item
1553 if the wanted one does not exist? */
1556 t
= xmalloc (sizeof (struct thread_points
));
1558 = xzalloc (max_slots_number
* sizeof (struct hw_break_tuple
));
1560 VEC_safe_push (thread_points_p
, ppc_threads
, t
);
1566 /* This function is a generic wrapper that is responsible for inserting a
1567 *point (i.e., calling `ptrace' in order to issue the request to the
1568 kernel) and registering it internally in GDB. */
1570 booke_insert_point (struct ppc_hw_breakpoint
*b
, int tid
)
1574 struct ppc_hw_breakpoint
*p
= xmalloc (sizeof (struct ppc_hw_breakpoint
));
1575 struct hw_break_tuple
*hw_breaks
;
1576 struct cleanup
*c
= make_cleanup (xfree
, p
);
1577 struct thread_points
*t
;
1578 struct hw_break_tuple
*tuple
;
1580 memcpy (p
, b
, sizeof (struct ppc_hw_breakpoint
));
1583 slot
= ptrace (PPC_PTRACE_SETHWDEBUG
, tid
, 0, p
);
1585 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1587 /* Everything went fine, so we have to register this *point. */
1588 t
= booke_find_thread_points_by_tid (tid
, 1);
1589 gdb_assert (t
!= NULL
);
1590 hw_breaks
= t
->hw_breaks
;
1592 /* Find a free element in the hw_breaks vector. */
1593 for (i
= 0; i
< max_slots_number
; i
++)
1594 if (hw_breaks
[i
].hw_break
== NULL
)
1596 hw_breaks
[i
].slot
= slot
;
1597 hw_breaks
[i
].hw_break
= p
;
1601 gdb_assert (i
!= max_slots_number
);
1603 discard_cleanups (c
);
1606 /* This function is a generic wrapper that is responsible for removing a
1607 *point (i.e., calling `ptrace' in order to issue the request to the
1608 kernel), and unregistering it internally at GDB. */
1610 booke_remove_point (struct ppc_hw_breakpoint
*b
, int tid
)
1613 struct hw_break_tuple
*hw_breaks
;
1614 struct thread_points
*t
;
1616 t
= booke_find_thread_points_by_tid (tid
, 0);
1617 gdb_assert (t
!= NULL
);
1618 hw_breaks
= t
->hw_breaks
;
1620 for (i
= 0; i
< max_slots_number
; i
++)
1621 if (hw_breaks
[i
].hw_break
&& booke_cmp_hw_point (hw_breaks
[i
].hw_break
, b
))
1624 gdb_assert (i
!= max_slots_number
);
1626 /* We have to ignore ENOENT errors because the kernel implements hardware
1627 breakpoints/watchpoints as "one-shot", that is, they are automatically
1628 deleted when hit. */
1630 if (ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
) < 0)
1631 if (errno
!= ENOENT
)
1632 perror_with_name (_("Unexpected error deleting "
1633 "breakpoint or watchpoint"));
1635 xfree (hw_breaks
[i
].hw_break
);
1636 hw_breaks
[i
].hw_break
= NULL
;
1639 /* Return the number of registers needed for a ranged breakpoint. */
1642 ppc_linux_ranged_break_num_registers (struct target_ops
*target
)
1644 return ((have_ptrace_booke_interface ()
1645 && booke_debug_info
.features
& PPC_DEBUG_FEATURE_INSN_BP_RANGE
)?
1649 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1650 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1653 ppc_linux_insert_hw_breakpoint (struct gdbarch
*gdbarch
,
1654 struct bp_target_info
*bp_tgt
)
1656 struct lwp_info
*lp
;
1657 struct ppc_hw_breakpoint p
;
1659 if (!have_ptrace_booke_interface ())
1662 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1663 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1664 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1665 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1666 p
.condition_value
= 0;
1670 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1672 /* The breakpoint will trigger if the address of the instruction is
1673 within the defined range, as follows: p.addr <= address < p.addr2. */
1674 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1678 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1683 booke_insert_point (&p
, TIDGET (lp
->ptid
));
1689 ppc_linux_remove_hw_breakpoint (struct gdbarch
*gdbarch
,
1690 struct bp_target_info
*bp_tgt
)
1692 struct lwp_info
*lp
;
1693 struct ppc_hw_breakpoint p
;
1695 if (!have_ptrace_booke_interface ())
1698 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1699 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1700 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1701 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1702 p
.condition_value
= 0;
1706 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1708 /* The breakpoint will trigger if the address of the instruction is within
1709 the defined range, as follows: p.addr <= address < p.addr2. */
1710 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1714 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1719 booke_remove_point (&p
, TIDGET (lp
->ptid
));
1725 get_trigger_type (int rw
)
1730 t
= PPC_BREAKPOINT_TRIGGER_READ
;
1731 else if (rw
== hw_write
)
1732 t
= PPC_BREAKPOINT_TRIGGER_WRITE
;
1734 t
= PPC_BREAKPOINT_TRIGGER_READ
| PPC_BREAKPOINT_TRIGGER_WRITE
;
1739 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1740 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1741 or hw_access for an access watchpoint. Returns 0 on success and throws
1742 an error on failure. */
1745 ppc_linux_insert_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1746 CORE_ADDR mask
, int rw
)
1748 struct lwp_info
*lp
;
1749 struct ppc_hw_breakpoint p
;
1751 gdb_assert (have_ptrace_booke_interface ());
1753 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1754 p
.trigger_type
= get_trigger_type (rw
);
1755 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1756 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1759 p
.condition_value
= 0;
1762 booke_insert_point (&p
, TIDGET (lp
->ptid
));
1767 /* Remove a masked watchpoint at ADDR with the mask MASK.
1768 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1769 or hw_access for an access watchpoint. Returns 0 on success and throws
1770 an error on failure. */
1773 ppc_linux_remove_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1774 CORE_ADDR mask
, int rw
)
1776 struct lwp_info
*lp
;
1777 struct ppc_hw_breakpoint p
;
1779 gdb_assert (have_ptrace_booke_interface ());
1781 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1782 p
.trigger_type
= get_trigger_type (rw
);
1783 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1784 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1787 p
.condition_value
= 0;
1790 booke_remove_point (&p
, TIDGET (lp
->ptid
));
1795 /* Check whether we have at least one free DVC register. */
1797 can_use_watchpoint_cond_accel (void)
1799 struct thread_points
*p
;
1800 int tid
= TIDGET (inferior_ptid
);
1801 int cnt
= booke_debug_info
.num_condition_regs
, i
;
1802 CORE_ADDR tmp_value
;
1804 if (!have_ptrace_booke_interface () || cnt
== 0)
1807 p
= booke_find_thread_points_by_tid (tid
, 0);
1811 for (i
= 0; i
< max_slots_number
; i
++)
1812 if (p
->hw_breaks
[i
].hw_break
!= NULL
1813 && (p
->hw_breaks
[i
].hw_break
->condition_mode
1814 != PPC_BREAKPOINT_CONDITION_NONE
))
1817 /* There are no available slots now. */
1825 /* Calculate the enable bits and the contents of the Data Value Compare
1826 debug register present in BookE processors.
1828 ADDR is the address to be watched, LEN is the length of watched data
1829 and DATA_VALUE is the value which will trigger the watchpoint.
1830 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1831 CONDITION_VALUE will hold the value which should be put in the
1834 calculate_dvc (CORE_ADDR addr
, int len
, CORE_ADDR data_value
,
1835 uint32_t *condition_mode
, uint64_t *condition_value
)
1837 int i
, num_byte_enable
, align_offset
, num_bytes_off_dvc
,
1838 rightmost_enabled_byte
;
1839 CORE_ADDR addr_end_data
, addr_end_dvc
;
1841 /* The DVC register compares bytes within fixed-length windows which
1842 are word-aligned, with length equal to that of the DVC register.
1843 We need to calculate where our watch region is relative to that
1844 window and enable comparison of the bytes which fall within it. */
1846 align_offset
= addr
% booke_debug_info
.sizeof_condition
;
1847 addr_end_data
= addr
+ len
;
1848 addr_end_dvc
= (addr
- align_offset
1849 + booke_debug_info
.sizeof_condition
);
1850 num_bytes_off_dvc
= (addr_end_data
> addr_end_dvc
)?
1851 addr_end_data
- addr_end_dvc
: 0;
1852 num_byte_enable
= len
- num_bytes_off_dvc
;
1853 /* Here, bytes are numbered from right to left. */
1854 rightmost_enabled_byte
= (addr_end_data
< addr_end_dvc
)?
1855 addr_end_dvc
- addr_end_data
: 0;
1857 *condition_mode
= PPC_BREAKPOINT_CONDITION_AND
;
1858 for (i
= 0; i
< num_byte_enable
; i
++)
1860 |= PPC_BREAKPOINT_CONDITION_BE (i
+ rightmost_enabled_byte
);
1862 /* Now we need to match the position within the DVC of the comparison
1863 value with where the watch region is relative to the window
1864 (i.e., the ALIGN_OFFSET). */
1866 *condition_value
= ((uint64_t) data_value
>> num_bytes_off_dvc
* 8
1867 << rightmost_enabled_byte
* 8);
1870 /* Return the number of memory locations that need to be accessed to
1871 evaluate the expression which generated the given value chain.
1872 Returns -1 if there's any register access involved, or if there are
1873 other kinds of values which are not acceptable in a condition
1874 expression (e.g., lval_computed or lval_internalvar). */
1876 num_memory_accesses (struct value
*v
)
1878 int found_memory_cnt
= 0;
1879 struct value
*head
= v
;
1881 /* The idea here is that evaluating an expression generates a series
1882 of values, one holding the value of every subexpression. (The
1883 expression a*b+c has five subexpressions: a, b, a*b, c, and
1884 a*b+c.) GDB's values hold almost enough information to establish
1885 the criteria given above --- they identify memory lvalues,
1886 register lvalues, computed values, etcetera. So we can evaluate
1887 the expression, and then scan the chain of values that leaves
1888 behind to determine the memory locations involved in the evaluation
1891 However, I don't think that the values returned by inferior
1892 function calls are special in any way. So this function may not
1893 notice that an expression contains an inferior function call.
1896 for (; v
; v
= value_next (v
))
1898 /* Constants and values from the history are fine. */
1899 if (VALUE_LVAL (v
) == not_lval
|| deprecated_value_modifiable (v
) == 0)
1901 else if (VALUE_LVAL (v
) == lval_memory
)
1903 /* A lazy memory lvalue is one that GDB never needed to fetch;
1904 we either just used its address (e.g., `a' in `a.b') or
1905 we never needed it at all (e.g., `a' in `a,b'). */
1906 if (!value_lazy (v
))
1909 /* Other kinds of values are not fine. */
1914 return found_memory_cnt
;
1917 /* Verifies whether the expression COND can be implemented using the
1918 DVC (Data Value Compare) register in BookE processors. The expression
1919 must test the watch value for equality with a constant expression.
1920 If the function returns 1, DATA_VALUE will contain the constant against
1921 which the watch value should be compared and LEN will contain the size
1924 check_condition (CORE_ADDR watch_addr
, struct expression
*cond
,
1925 CORE_ADDR
*data_value
, int *len
)
1927 int pc
= 1, num_accesses_left
, num_accesses_right
;
1928 struct value
*left_val
, *right_val
, *left_chain
, *right_chain
;
1930 if (cond
->elts
[0].opcode
!= BINOP_EQUAL
)
1933 fetch_subexp_value (cond
, &pc
, &left_val
, NULL
, &left_chain
);
1934 num_accesses_left
= num_memory_accesses (left_chain
);
1936 if (left_val
== NULL
|| num_accesses_left
< 0)
1938 free_value_chain (left_chain
);
1943 fetch_subexp_value (cond
, &pc
, &right_val
, NULL
, &right_chain
);
1944 num_accesses_right
= num_memory_accesses (right_chain
);
1946 if (right_val
== NULL
|| num_accesses_right
< 0)
1948 free_value_chain (left_chain
);
1949 free_value_chain (right_chain
);
1954 if (num_accesses_left
== 1 && num_accesses_right
== 0
1955 && VALUE_LVAL (left_val
) == lval_memory
1956 && value_address (left_val
) == watch_addr
)
1958 *data_value
= value_as_long (right_val
);
1960 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1961 the same type as the memory region referenced by LEFT_VAL. */
1962 *len
= TYPE_LENGTH (check_typedef (value_type (left_val
)));
1964 else if (num_accesses_left
== 0 && num_accesses_right
== 1
1965 && VALUE_LVAL (right_val
) == lval_memory
1966 && value_address (right_val
) == watch_addr
)
1968 *data_value
= value_as_long (left_val
);
1970 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1971 the same type as the memory region referenced by RIGHT_VAL. */
1972 *len
= TYPE_LENGTH (check_typedef (value_type (right_val
)));
1976 free_value_chain (left_chain
);
1977 free_value_chain (right_chain
);
1982 free_value_chain (left_chain
);
1983 free_value_chain (right_chain
);
1988 /* Return non-zero if the target is capable of using hardware to evaluate
1989 the condition expression, thus only triggering the watchpoint when it is
1992 ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr
, int len
, int rw
,
1993 struct expression
*cond
)
1995 CORE_ADDR data_value
;
1997 return (have_ptrace_booke_interface ()
1998 && booke_debug_info
.num_condition_regs
> 0
1999 && check_condition (addr
, cond
, &data_value
, &len
));
2002 /* Set up P with the parameters necessary to request a watchpoint covering
2003 LEN bytes starting at ADDR and if possible with condition expression COND
2004 evaluated by hardware. INSERT tells if we are creating a request for
2005 inserting or removing the watchpoint. */
2008 create_watchpoint_request (struct ppc_hw_breakpoint
*p
, CORE_ADDR addr
,
2009 int len
, int rw
, struct expression
*cond
,
2013 || !(booke_debug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
))
2016 CORE_ADDR data_value
;
2018 use_condition
= (insert
? can_use_watchpoint_cond_accel ()
2019 : booke_debug_info
.num_condition_regs
> 0);
2020 if (cond
&& use_condition
&& check_condition (addr
, cond
,
2022 calculate_dvc (addr
, len
, data_value
, &p
->condition_mode
,
2023 &p
->condition_value
);
2026 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2027 p
->condition_value
= 0;
2030 p
->addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
2035 p
->addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
2036 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2037 p
->condition_value
= 0;
2039 /* The watchpoint will trigger if the address of the memory access is
2040 within the defined range, as follows: p->addr <= address < p->addr2.
2042 Note that the above sentence just documents how ptrace interprets
2043 its arguments; the watchpoint is set to watch the range defined by
2044 the user _inclusively_, as specified by the user interface. */
2045 p
->addr2
= (uint64_t) addr
+ len
;
2048 p
->version
= PPC_DEBUG_CURRENT_VERSION
;
2049 p
->trigger_type
= get_trigger_type (rw
);
2050 p
->addr
= (uint64_t) addr
;
2054 ppc_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int rw
,
2055 struct expression
*cond
)
2057 struct lwp_info
*lp
;
2060 if (have_ptrace_booke_interface ())
2062 struct ppc_hw_breakpoint p
;
2064 create_watchpoint_request (&p
, addr
, len
, rw
, cond
, 1);
2067 booke_insert_point (&p
, TIDGET (lp
->ptid
));
2074 long read_mode
, write_mode
;
2076 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2078 /* PowerPC 440 requires only the read/write flags to be passed
2085 /* PowerPC 970 and other DABR-based processors are required to pass
2086 the Breakpoint Translation bit together with the flags. */
2091 dabr_value
= addr
& ~(read_mode
| write_mode
);
2095 /* Set read and translate bits. */
2096 dabr_value
|= read_mode
;
2099 /* Set write and translate bits. */
2100 dabr_value
|= write_mode
;
2103 /* Set read, write and translate bits. */
2104 dabr_value
|= read_mode
| write_mode
;
2108 saved_dabr_value
= dabr_value
;
2111 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (lp
->ptid
), 0,
2112 saved_dabr_value
) < 0)
2122 ppc_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int rw
,
2123 struct expression
*cond
)
2125 struct lwp_info
*lp
;
2128 if (have_ptrace_booke_interface ())
2130 struct ppc_hw_breakpoint p
;
2132 create_watchpoint_request (&p
, addr
, len
, rw
, cond
, 0);
2135 booke_remove_point (&p
, TIDGET (lp
->ptid
));
2141 saved_dabr_value
= 0;
2143 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (lp
->ptid
), 0,
2144 saved_dabr_value
) < 0)
2154 ppc_linux_new_thread (struct lwp_info
*lp
)
2156 int tid
= TIDGET (lp
->ptid
);
2158 if (have_ptrace_booke_interface ())
2161 struct thread_points
*p
;
2162 struct hw_break_tuple
*hw_breaks
;
2164 if (VEC_empty (thread_points_p
, ppc_threads
))
2167 /* Get a list of breakpoints from any thread. */
2168 p
= VEC_last (thread_points_p
, ppc_threads
);
2169 hw_breaks
= p
->hw_breaks
;
2171 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2172 for (i
= 0; i
< max_slots_number
; i
++)
2173 if (hw_breaks
[i
].hw_break
)
2174 booke_insert_point (hw_breaks
[i
].hw_break
, tid
);
2177 ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, saved_dabr_value
);
2181 ppc_linux_thread_exit (struct thread_info
*tp
, int silent
)
2184 int tid
= TIDGET (tp
->ptid
);
2185 struct hw_break_tuple
*hw_breaks
;
2186 struct thread_points
*t
= NULL
, *p
;
2188 if (!have_ptrace_booke_interface ())
2191 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, p
); i
++)
2201 VEC_unordered_remove (thread_points_p
, ppc_threads
, i
);
2203 hw_breaks
= t
->hw_breaks
;
2205 for (i
= 0; i
< max_slots_number
; i
++)
2206 if (hw_breaks
[i
].hw_break
)
2207 xfree (hw_breaks
[i
].hw_break
);
2209 xfree (t
->hw_breaks
);
2214 ppc_linux_stopped_data_address (struct target_ops
*target
, CORE_ADDR
*addr_p
)
2216 struct siginfo
*siginfo_p
;
2218 siginfo_p
= linux_nat_get_siginfo (inferior_ptid
);
2220 if (siginfo_p
->si_signo
!= SIGTRAP
2221 || (siginfo_p
->si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2224 if (have_ptrace_booke_interface ())
2227 struct thread_points
*t
;
2228 struct hw_break_tuple
*hw_breaks
;
2229 /* The index (or slot) of the *point is passed in the si_errno field. */
2230 int slot
= siginfo_p
->si_errno
;
2232 t
= booke_find_thread_points_by_tid (TIDGET (inferior_ptid
), 0);
2234 /* Find out if this *point is a hardware breakpoint.
2235 If so, we should return 0. */
2238 hw_breaks
= t
->hw_breaks
;
2239 for (i
= 0; i
< max_slots_number
; i
++)
2240 if (hw_breaks
[i
].hw_break
&& hw_breaks
[i
].slot
== slot
2241 && hw_breaks
[i
].hw_break
->trigger_type
2242 == PPC_BREAKPOINT_TRIGGER_EXECUTE
)
2247 *addr_p
= (CORE_ADDR
) (uintptr_t) siginfo_p
->si_addr
;
2252 ppc_linux_stopped_by_watchpoint (void)
2255 return ppc_linux_stopped_data_address (¤t_target
, &addr
);
2259 ppc_linux_watchpoint_addr_within_range (struct target_ops
*target
,
2261 CORE_ADDR start
, int length
)
2265 if (have_ptrace_booke_interface ()
2266 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2267 return start
<= addr
&& start
+ length
>= addr
;
2268 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2275 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2276 return start
<= addr
+ mask
&& start
+ length
- 1 >= addr
;
2279 /* Return the number of registers needed for a masked hardware watchpoint. */
2282 ppc_linux_masked_watch_num_registers (struct target_ops
*target
,
2283 CORE_ADDR addr
, CORE_ADDR mask
)
2285 if (!have_ptrace_booke_interface ()
2286 || (booke_debug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_MASK
) == 0)
2288 else if ((mask
& 0xC0000000) != 0xC0000000)
2290 warning (_("The given mask covers kernel address space "
2291 "and cannot be used.\n"));
2300 ppc_linux_store_inferior_registers (struct target_ops
*ops
,
2301 struct regcache
*regcache
, int regno
)
2303 /* Overload thread id onto process id. */
2304 int tid
= TIDGET (inferior_ptid
);
2306 /* No thread id, just use process id. */
2308 tid
= PIDGET (inferior_ptid
);
2311 store_register (regcache
, tid
, regno
);
2313 store_ppc_registers (regcache
, tid
);
2316 /* Functions for transferring registers between a gregset_t or fpregset_t
2317 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2318 by the ptrace interface, not the current program's ABI. Eg. if a
2319 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2320 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2323 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
2325 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2327 ppc_supply_gregset (regset
, regcache
, -1, gregsetp
, sizeof (*gregsetp
));
2331 fill_gregset (const struct regcache
*regcache
,
2332 gdb_gregset_t
*gregsetp
, int regno
)
2334 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2337 memset (gregsetp
, 0, sizeof (*gregsetp
));
2338 ppc_collect_gregset (regset
, regcache
, regno
, gregsetp
, sizeof (*gregsetp
));
2342 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
* fpregsetp
)
2344 const struct regset
*regset
= ppc_linux_fpregset ();
2346 ppc_supply_fpregset (regset
, regcache
, -1,
2347 fpregsetp
, sizeof (*fpregsetp
));
2351 fill_fpregset (const struct regcache
*regcache
,
2352 gdb_fpregset_t
*fpregsetp
, int regno
)
2354 const struct regset
*regset
= ppc_linux_fpregset ();
2356 ppc_collect_fpregset (regset
, regcache
, regno
,
2357 fpregsetp
, sizeof (*fpregsetp
));
2361 ppc_linux_target_wordsize (void)
2365 /* Check for 64-bit inferior process. This is the case when the host is
2366 64-bit, and in addition the top bit of the MSR register is set. */
2367 #ifdef __powerpc64__
2370 int tid
= TIDGET (inferior_ptid
);
2372 tid
= PIDGET (inferior_ptid
);
2375 msr
= (long) ptrace (PTRACE_PEEKUSER
, tid
, PT_MSR
* 8, 0);
2376 if (errno
== 0 && msr
< 0)
2384 ppc_linux_auxv_parse (struct target_ops
*ops
, gdb_byte
**readptr
,
2385 gdb_byte
*endptr
, CORE_ADDR
*typep
, CORE_ADDR
*valp
)
2387 int sizeof_auxv_field
= ppc_linux_target_wordsize ();
2388 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch
);
2389 gdb_byte
*ptr
= *readptr
;
2394 if (endptr
- ptr
< sizeof_auxv_field
* 2)
2397 *typep
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2398 ptr
+= sizeof_auxv_field
;
2399 *valp
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2400 ptr
+= sizeof_auxv_field
;
2406 static const struct target_desc
*
2407 ppc_linux_read_description (struct target_ops
*ops
)
2414 int tid
= TIDGET (inferior_ptid
);
2416 tid
= PIDGET (inferior_ptid
);
2418 if (have_ptrace_getsetevrregs
)
2420 struct gdb_evrregset_t evrregset
;
2422 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, &evrregset
) >= 0)
2423 return tdesc_powerpc_e500l
;
2425 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2426 Anything else needs to be reported. */
2427 else if (errno
!= EIO
)
2428 perror_with_name (_("Unable to fetch SPE registers"));
2431 if (have_ptrace_getsetvsxregs
)
2433 gdb_vsxregset_t vsxregset
;
2435 if (ptrace (PTRACE_GETVSXREGS
, tid
, 0, &vsxregset
) >= 0)
2438 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2439 Anything else needs to be reported. */
2440 else if (errno
!= EIO
)
2441 perror_with_name (_("Unable to fetch VSX registers"));
2444 if (have_ptrace_getvrregs
)
2446 gdb_vrregset_t vrregset
;
2448 if (ptrace (PTRACE_GETVRREGS
, tid
, 0, &vrregset
) >= 0)
2451 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2452 Anything else needs to be reported. */
2453 else if (errno
!= EIO
)
2454 perror_with_name (_("Unable to fetch AltiVec registers"));
2457 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2458 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2459 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2460 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2461 half of the register are for Decimal Floating Point, we check if that
2462 feature is available to decide the size of the FPSCR. */
2463 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP
)
2466 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL
)
2469 if (ppc_linux_target_wordsize () == 8)
2472 return tdesc_powerpc_cell64l
;
2474 return isa205
? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l
;
2477 ? tdesc_powerpc_isa205_altivec64l
: tdesc_powerpc_altivec64l
;
2479 return isa205
? tdesc_powerpc_isa205_64l
: tdesc_powerpc_64l
;
2483 return tdesc_powerpc_cell32l
;
2485 return isa205
? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l
;
2487 return isa205
? tdesc_powerpc_isa205_altivec32l
: tdesc_powerpc_altivec32l
;
2489 return isa205
? tdesc_powerpc_isa205_32l
: tdesc_powerpc_32l
;
2492 void _initialize_ppc_linux_nat (void);
2495 _initialize_ppc_linux_nat (void)
2497 struct target_ops
*t
;
2499 /* Fill in the generic GNU/Linux methods. */
2500 t
= linux_target ();
2502 /* Add our register access methods. */
2503 t
->to_fetch_registers
= ppc_linux_fetch_inferior_registers
;
2504 t
->to_store_registers
= ppc_linux_store_inferior_registers
;
2506 /* Add our breakpoint/watchpoint methods. */
2507 t
->to_can_use_hw_breakpoint
= ppc_linux_can_use_hw_breakpoint
;
2508 t
->to_insert_hw_breakpoint
= ppc_linux_insert_hw_breakpoint
;
2509 t
->to_remove_hw_breakpoint
= ppc_linux_remove_hw_breakpoint
;
2510 t
->to_region_ok_for_hw_watchpoint
= ppc_linux_region_ok_for_hw_watchpoint
;
2511 t
->to_insert_watchpoint
= ppc_linux_insert_watchpoint
;
2512 t
->to_remove_watchpoint
= ppc_linux_remove_watchpoint
;
2513 t
->to_insert_mask_watchpoint
= ppc_linux_insert_mask_watchpoint
;
2514 t
->to_remove_mask_watchpoint
= ppc_linux_remove_mask_watchpoint
;
2515 t
->to_stopped_by_watchpoint
= ppc_linux_stopped_by_watchpoint
;
2516 t
->to_stopped_data_address
= ppc_linux_stopped_data_address
;
2517 t
->to_watchpoint_addr_within_range
= ppc_linux_watchpoint_addr_within_range
;
2518 t
->to_can_accel_watchpoint_condition
2519 = ppc_linux_can_accel_watchpoint_condition
;
2520 t
->to_masked_watch_num_registers
= ppc_linux_masked_watch_num_registers
;
2521 t
->to_ranged_break_num_registers
= ppc_linux_ranged_break_num_registers
;
2523 t
->to_read_description
= ppc_linux_read_description
;
2524 t
->to_auxv_parse
= ppc_linux_auxv_parse
;
2526 observer_attach_thread_exit (ppc_linux_thread_exit
);
2528 /* Register the target. */
2529 linux_nat_add_target (t
);
2530 linux_nat_set_new_thread (t
, ppc_linux_new_thread
);