1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003,
4 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb_string.h"
27 #include "gdbthread.h"
30 #include "gdb_assert.h"
32 #include "linux-nat.h"
35 #include <sys/types.h>
36 #include <sys/param.h>
39 #include <sys/ioctl.h>
42 #include <sys/procfs.h>
43 #include <sys/ptrace.h>
45 /* Prototypes for supply_gregset etc. */
48 #include "ppc-linux-tdep.h"
50 /* Required when using the AUXV. */
51 #include "elf/common.h"
54 /* This sometimes isn't defined. */
62 /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
63 If they aren't, we can provide them ourselves (their values are fixed
64 because they are part of the kernel ABI). They are used in the AT_HWCAP
66 #ifndef PPC_FEATURE_CELL
67 #define PPC_FEATURE_CELL 0x00010000
69 #ifndef PPC_FEATURE_BOOKE
70 #define PPC_FEATURE_BOOKE 0x00008000
72 #ifndef PPC_FEATURE_HAS_DFP
73 #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
76 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
77 configure time check. Some older glibc's (for instance 2.2.1)
78 don't have a specific powerpc version of ptrace.h, and fall back on
79 a generic one. In such cases, sys/ptrace.h defines
80 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
81 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
82 PTRACE_SETVRREGS to be. This also makes a configury check pretty
85 /* These definitions should really come from the glibc header files,
86 but Glibc doesn't know about the vrregs yet. */
87 #ifndef PTRACE_GETVRREGS
88 #define PTRACE_GETVRREGS 18
89 #define PTRACE_SETVRREGS 19
92 /* PTRACE requests for POWER7 VSX registers. */
93 #ifndef PTRACE_GETVSXREGS
94 #define PTRACE_GETVSXREGS 27
95 #define PTRACE_SETVSXREGS 28
98 /* Similarly for the ptrace requests for getting / setting the SPE
99 registers (ev0 -- ev31, acc, and spefscr). See the description of
100 gdb_evrregset_t for details. */
101 #ifndef PTRACE_GETEVRREGS
102 #define PTRACE_GETEVRREGS 20
103 #define PTRACE_SETEVRREGS 21
106 /* Similarly for the hardware watchpoint support. These requests are used
107 when the BookE kernel interface is not available. */
108 #ifndef PTRACE_GET_DEBUGREG
109 #define PTRACE_GET_DEBUGREG 25
111 #ifndef PTRACE_SET_DEBUGREG
112 #define PTRACE_SET_DEBUGREG 26
114 #ifndef PTRACE_GETSIGINFO
115 #define PTRACE_GETSIGINFO 0x4202
118 /* These requests are used when the BookE kernel interface is available.
119 It exposes the additional debug features of BookE processors, such as
120 ranged breakpoints and watchpoints and hardware-accelerated condition
122 #ifndef PPC_PTRACE_GETHWDBGINFO
124 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the new BookE
125 interface is not present in ptrace.h, so we'll have to pretty much include
126 it all here so that the code at least compiles on older systems. */
127 #define PPC_PTRACE_GETHWDBGINFO 0x89
128 #define PPC_PTRACE_SETHWDEBUG 0x88
129 #define PPC_PTRACE_DELHWDEBUG 0x87
131 struct ppc_debug_info
133 uint32_t version
; /* Only version 1 exists to date */
134 uint32_t num_instruction_bps
;
135 uint32_t num_data_bps
;
136 uint32_t num_condition_regs
;
137 uint32_t data_bp_alignment
;
138 uint32_t sizeof_condition
; /* size of the DVC register */
142 /* Features will have bits indicating whether there is support for: */
143 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
144 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
145 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
146 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
148 struct ppc_hw_breakpoint
150 uint32_t version
; /* currently, version must be 1 */
151 uint32_t trigger_type
; /* only some combinations allowed */
152 uint32_t addr_mode
; /* address match mode */
153 uint32_t condition_mode
; /* break/watchpoint condition flags */
154 uint64_t addr
; /* break/watchpoint address */
155 uint64_t addr2
; /* range end or mask */
156 uint64_t condition_value
; /* contents of the DVC register */
160 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
161 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
162 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
163 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
166 #define PPC_BREAKPOINT_MODE_EXACT 0x0
167 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
168 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
169 #define PPC_BREAKPOINT_MODE_MASK 0x3
171 /* Condition mode. */
172 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
173 #define PPC_BREAKPOINT_CONDITION_AND 0x1
174 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
175 #define PPC_BREAKPOINT_CONDITION_OR 0x2
176 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
177 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
178 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
179 #define PPC_BREAKPOINT_CONDITION_BE(n) \
180 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
181 #endif /* PPC_PTRACE_GETHWDBGINFO */
185 /* Similarly for the general-purpose (gp0 -- gp31)
186 and floating-point registers (fp0 -- fp31). */
187 #ifndef PTRACE_GETREGS
188 #define PTRACE_GETREGS 12
190 #ifndef PTRACE_SETREGS
191 #define PTRACE_SETREGS 13
193 #ifndef PTRACE_GETFPREGS
194 #define PTRACE_GETFPREGS 14
196 #ifndef PTRACE_SETFPREGS
197 #define PTRACE_SETFPREGS 15
200 /* This oddity is because the Linux kernel defines elf_vrregset_t as
201 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
202 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
203 the vrsave as an extra 4 bytes at the end. I opted for creating a
204 flat array of chars, so that it is easier to manipulate for gdb.
206 There are 32 vector registers 16 bytes longs, plus a VSCR register
207 which is only 4 bytes long, but is fetched as a 16 bytes
208 quantity. Up to here we have the elf_vrregset_t structure.
209 Appended to this there is space for the VRSAVE register: 4 bytes.
210 Even though this vrsave register is not included in the regset
211 typedef, it is handled by the ptrace requests.
213 Note that GNU/Linux doesn't support little endian PPC hardware,
214 therefore the offset at which the real value of the VSCR register
215 is located will be always 12 bytes.
217 The layout is like this (where x is the actual value of the vscr reg): */
221 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
222 <-------> <-------><-------><->
227 #define SIZEOF_VRREGS 33*16+4
229 typedef char gdb_vrregset_t
[SIZEOF_VRREGS
];
231 /* This is the layout of the POWER7 VSX registers and the way they overlap
232 with the existing FPR and VMX registers.
234 VSR doubleword 0 VSR doubleword 1
235 ----------------------------------------------------------------
237 ----------------------------------------------------------------
239 ----------------------------------------------------------------
242 ----------------------------------------------------------------
243 VSR[30] | FPR[30] | |
244 ----------------------------------------------------------------
245 VSR[31] | FPR[31] | |
246 ----------------------------------------------------------------
248 ----------------------------------------------------------------
250 ----------------------------------------------------------------
253 ----------------------------------------------------------------
255 ----------------------------------------------------------------
257 ----------------------------------------------------------------
259 VSX has 64 128bit registers. The first 32 registers overlap with
260 the FP registers (doubleword 0) and hence extend them with additional
261 64 bits (doubleword 1). The other 32 regs overlap with the VMX
263 #define SIZEOF_VSXREGS 32*8
265 typedef char gdb_vsxregset_t
[SIZEOF_VSXREGS
];
267 /* On PPC processors that support the the Signal Processing Extension
268 (SPE) APU, the general-purpose registers are 64 bits long.
269 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
270 ptrace calls only access the lower half of each register, to allow
271 them to behave the same way they do on non-SPE systems. There's a
272 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
273 read and write the top halves of all the general-purpose registers
274 at once, along with some SPE-specific registers.
276 GDB itself continues to claim the general-purpose registers are 32
277 bits long. It has unnamed raw registers that hold the upper halves
278 of the gprs, and the the full 64-bit SIMD views of the registers,
279 'ev0' -- 'ev31', are pseudo-registers that splice the top and
280 bottom halves together.
282 This is the structure filled in by PTRACE_GETEVRREGS and written to
283 the inferior's registers by PTRACE_SETEVRREGS. */
284 struct gdb_evrregset_t
286 unsigned long evr
[32];
287 unsigned long long acc
;
288 unsigned long spefscr
;
291 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
292 PTRACE_SETVSXREGS requests, for reading and writing the VSX
293 POWER7 registers 0 through 31. Zero if we've tried one of them and
294 gotten an error. Note that VSX registers 32 through 63 overlap
295 with VR registers 0 through 31. */
296 int have_ptrace_getsetvsxregs
= 1;
298 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
299 PTRACE_SETVRREGS requests, for reading and writing the Altivec
300 registers. Zero if we've tried one of them and gotten an
302 int have_ptrace_getvrregs
= 1;
304 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
305 PTRACE_SETEVRREGS requests, for reading and writing the SPE
306 registers. Zero if we've tried one of them and gotten an
308 int have_ptrace_getsetevrregs
= 1;
310 /* Non-zero if our kernel may support the PTRACE_GETREGS and
311 PTRACE_SETREGS requests, for reading and writing the
312 general-purpose registers. Zero if we've tried one of
313 them and gotten an error. */
314 int have_ptrace_getsetregs
= 1;
316 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
317 PTRACE_SETFPREGS requests, for reading and writing the
318 floating-pointers registers. Zero if we've tried one of
319 them and gotten an error. */
320 int have_ptrace_getsetfpregs
= 1;
323 /* registers layout, as presented by the ptrace interface:
324 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
325 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
326 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
327 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
328 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
329 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
330 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
331 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
332 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
336 ppc_register_u_addr (struct gdbarch
*gdbarch
, int regno
)
339 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
340 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
341 interface, and not the wordsize of the program's ABI. */
342 int wordsize
= sizeof (long);
344 /* General purpose registers occupy 1 slot each in the buffer */
345 if (regno
>= tdep
->ppc_gp0_regnum
346 && regno
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
347 u_addr
= ((regno
- tdep
->ppc_gp0_regnum
+ PT_R0
) * wordsize
);
349 /* Floating point regs: eight bytes each in both 32- and 64-bit
350 ptrace interfaces. Thus, two slots each in 32-bit interface, one
351 slot each in 64-bit interface. */
352 if (tdep
->ppc_fp0_regnum
>= 0
353 && regno
>= tdep
->ppc_fp0_regnum
354 && regno
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
355 u_addr
= (PT_FPR0
* wordsize
) + ((regno
- tdep
->ppc_fp0_regnum
) * 8);
357 /* UISA special purpose registers: 1 slot each */
358 if (regno
== gdbarch_pc_regnum (gdbarch
))
359 u_addr
= PT_NIP
* wordsize
;
360 if (regno
== tdep
->ppc_lr_regnum
)
361 u_addr
= PT_LNK
* wordsize
;
362 if (regno
== tdep
->ppc_cr_regnum
)
363 u_addr
= PT_CCR
* wordsize
;
364 if (regno
== tdep
->ppc_xer_regnum
)
365 u_addr
= PT_XER
* wordsize
;
366 if (regno
== tdep
->ppc_ctr_regnum
)
367 u_addr
= PT_CTR
* wordsize
;
369 if (regno
== tdep
->ppc_mq_regnum
)
370 u_addr
= PT_MQ
* wordsize
;
372 if (regno
== tdep
->ppc_ps_regnum
)
373 u_addr
= PT_MSR
* wordsize
;
374 if (regno
== PPC_ORIG_R3_REGNUM
)
375 u_addr
= PT_ORIG_R3
* wordsize
;
376 if (regno
== PPC_TRAP_REGNUM
)
377 u_addr
= PT_TRAP
* wordsize
;
378 if (tdep
->ppc_fpscr_regnum
>= 0
379 && regno
== tdep
->ppc_fpscr_regnum
)
381 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
382 kernel headers incorrectly contained the 32-bit definition of
383 PT_FPSCR. For the 32-bit definition, floating-point
384 registers occupy two 32-bit "slots", and the FPSCR lives in
385 the second half of such a slot-pair (hence +1). For 64-bit,
386 the FPSCR instead occupies the full 64-bit 2-word-slot and
387 hence no adjustment is necessary. Hack around this. */
388 if (wordsize
== 8 && PT_FPSCR
== (48 + 32 + 1))
389 u_addr
= (48 + 32) * wordsize
;
390 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
391 slot and not just its second word. The PT_FPSCR supplied when
392 GDB is compiled as a 32-bit app doesn't reflect this. */
393 else if (wordsize
== 4 && register_size (gdbarch
, regno
) == 8
394 && PT_FPSCR
== (48 + 2*32 + 1))
395 u_addr
= (48 + 2*32) * wordsize
;
397 u_addr
= PT_FPSCR
* wordsize
;
402 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
403 registers set mechanism, as opposed to the interface for all the
404 other registers, that stores/fetches each register individually. */
406 fetch_vsx_register (struct regcache
*regcache
, int tid
, int regno
)
409 gdb_vsxregset_t regs
;
410 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
411 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
412 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
414 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
419 have_ptrace_getsetvsxregs
= 0;
422 perror_with_name (_("Unable to fetch VSX register"));
425 regcache_raw_supply (regcache
, regno
,
426 regs
+ (regno
- tdep
->ppc_vsr0_upper_regnum
)
430 /* The Linux kernel ptrace interface for AltiVec registers uses the
431 registers set mechanism, as opposed to the interface for all the
432 other registers, that stores/fetches each register individually. */
434 fetch_altivec_register (struct regcache
*regcache
, int tid
, int regno
)
439 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
440 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
441 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
443 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
448 have_ptrace_getvrregs
= 0;
451 perror_with_name (_("Unable to fetch AltiVec register"));
454 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
455 long on the hardware. We deal only with the lower 4 bytes of the
456 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
457 there is no need to define an offset for it. */
458 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
459 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
461 regcache_raw_supply (regcache
, regno
,
462 regs
+ (regno
- tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
465 /* Fetch the top 32 bits of TID's general-purpose registers and the
466 SPE-specific registers, and place the results in EVRREGSET. If we
467 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
470 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
471 PTRACE_SETEVRREGS requests are supported is isolated here, and in
472 set_spe_registers. */
474 get_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
476 if (have_ptrace_getsetevrregs
)
478 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, evrregset
) >= 0)
482 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
483 we just return zeros. */
485 have_ptrace_getsetevrregs
= 0;
487 /* Anything else needs to be reported. */
488 perror_with_name (_("Unable to fetch SPE registers"));
492 memset (evrregset
, 0, sizeof (*evrregset
));
495 /* Supply values from TID for SPE-specific raw registers: the upper
496 halves of the GPRs, the accumulator, and the spefscr. REGNO must
497 be the number of an upper half register, acc, spefscr, or -1 to
498 supply the values of all registers. */
500 fetch_spe_register (struct regcache
*regcache
, int tid
, int regno
)
502 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
503 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
504 struct gdb_evrregset_t evrregs
;
506 gdb_assert (sizeof (evrregs
.evr
[0])
507 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
508 gdb_assert (sizeof (evrregs
.acc
)
509 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
510 gdb_assert (sizeof (evrregs
.spefscr
)
511 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
513 get_spe_registers (tid
, &evrregs
);
519 for (i
= 0; i
< ppc_num_gprs
; i
++)
520 regcache_raw_supply (regcache
, tdep
->ppc_ev0_upper_regnum
+ i
,
523 else if (tdep
->ppc_ev0_upper_regnum
<= regno
524 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
525 regcache_raw_supply (regcache
, regno
,
526 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
529 || regno
== tdep
->ppc_acc_regnum
)
530 regcache_raw_supply (regcache
, tdep
->ppc_acc_regnum
, &evrregs
.acc
);
533 || regno
== tdep
->ppc_spefscr_regnum
)
534 regcache_raw_supply (regcache
, tdep
->ppc_spefscr_regnum
,
539 fetch_register (struct regcache
*regcache
, int tid
, int regno
)
541 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
542 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
543 /* This isn't really an address. But ptrace thinks of it as one. */
544 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
545 int bytes_transferred
;
546 unsigned int offset
; /* Offset of registers within the u area. */
547 char buf
[MAX_REGISTER_SIZE
];
549 if (altivec_register_p (gdbarch
, regno
))
551 /* If this is the first time through, or if it is not the first
552 time through, and we have comfirmed that there is kernel
553 support for such a ptrace request, then go and fetch the
555 if (have_ptrace_getvrregs
)
557 fetch_altivec_register (regcache
, tid
, regno
);
560 /* If we have discovered that there is no ptrace support for
561 AltiVec registers, fall through and return zeroes, because
562 regaddr will be -1 in this case. */
564 if (vsx_register_p (gdbarch
, regno
))
566 if (have_ptrace_getsetvsxregs
)
568 fetch_vsx_register (regcache
, tid
, regno
);
572 else if (spe_register_p (gdbarch
, regno
))
574 fetch_spe_register (regcache
, tid
, regno
);
580 memset (buf
, '\0', register_size (gdbarch
, regno
)); /* Supply zeroes */
581 regcache_raw_supply (regcache
, regno
, buf
);
585 /* Read the raw register using sizeof(long) sized chunks. On a
586 32-bit platform, 64-bit floating-point registers will require two
588 for (bytes_transferred
= 0;
589 bytes_transferred
< register_size (gdbarch
, regno
);
590 bytes_transferred
+= sizeof (long))
593 *(long *) &buf
[bytes_transferred
]
594 = ptrace (PTRACE_PEEKUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, 0);
595 regaddr
+= sizeof (long);
599 sprintf (message
, "reading register %s (#%d)",
600 gdbarch_register_name (gdbarch
, regno
), regno
);
601 perror_with_name (message
);
605 /* Now supply the register. Keep in mind that the regcache's idea
606 of the register's size may not be a multiple of sizeof
608 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
610 /* Little-endian values are always found at the left end of the
611 bytes transferred. */
612 regcache_raw_supply (regcache
, regno
, buf
);
614 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
616 /* Big-endian values are found at the right end of the bytes
618 size_t padding
= (bytes_transferred
- register_size (gdbarch
, regno
));
619 regcache_raw_supply (regcache
, regno
, buf
+ padding
);
622 internal_error (__FILE__
, __LINE__
,
623 _("fetch_register: unexpected byte order: %d"),
624 gdbarch_byte_order (gdbarch
));
628 supply_vsxregset (struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
631 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
632 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
633 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
635 for (i
= 0; i
< ppc_num_vshrs
; i
++)
637 regcache_raw_supply (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
638 *vsxregsetp
+ i
* vsxregsize
);
643 supply_vrregset (struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
646 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
647 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
648 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
649 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
650 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
652 for (i
= 0; i
< num_of_vrregs
; i
++)
654 /* The last 2 registers of this set are only 32 bit long, not
655 128. However an offset is necessary only for VSCR because it
656 occupies a whole vector, while VRSAVE occupies a full 4 bytes
658 if (i
== (num_of_vrregs
- 2))
659 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
660 *vrregsetp
+ i
* vrregsize
+ offset
);
662 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
663 *vrregsetp
+ i
* vrregsize
);
668 fetch_vsx_registers (struct regcache
*regcache
, int tid
)
671 gdb_vsxregset_t regs
;
673 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
678 have_ptrace_getsetvsxregs
= 0;
681 perror_with_name (_("Unable to fetch VSX registers"));
683 supply_vsxregset (regcache
, ®s
);
687 fetch_altivec_registers (struct regcache
*regcache
, int tid
)
692 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
697 have_ptrace_getvrregs
= 0;
700 perror_with_name (_("Unable to fetch AltiVec registers"));
702 supply_vrregset (regcache
, ®s
);
705 /* This function actually issues the request to ptrace, telling
706 it to get all general-purpose registers and put them into the
709 If the ptrace request does not exist, this function returns 0
710 and properly sets the have_ptrace_* flag. If the request fails,
711 this function calls perror_with_name. Otherwise, if the request
712 succeeds, then the regcache gets filled and 1 is returned. */
714 fetch_all_gp_regs (struct regcache
*regcache
, int tid
)
716 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
717 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
718 gdb_gregset_t gregset
;
720 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
724 have_ptrace_getsetregs
= 0;
727 perror_with_name (_("Couldn't get general-purpose registers."));
730 supply_gregset (regcache
, (const gdb_gregset_t
*) &gregset
);
735 /* This is a wrapper for the fetch_all_gp_regs function. It is
736 responsible for verifying if this target has the ptrace request
737 that can be used to fetch all general-purpose registers at one
738 shot. If it doesn't, then we should fetch them using the
739 old-fashioned way, which is to iterate over the registers and
740 request them one by one. */
742 fetch_gp_regs (struct regcache
*regcache
, int tid
)
744 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
745 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
748 if (have_ptrace_getsetregs
)
749 if (fetch_all_gp_regs (regcache
, tid
))
752 /* If we've hit this point, it doesn't really matter which
753 architecture we are using. We just need to read the
754 registers in the "old-fashioned way". */
755 for (i
= 0; i
< ppc_num_gprs
; i
++)
756 fetch_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
759 /* This function actually issues the request to ptrace, telling
760 it to get all floating-point registers and put them into the
763 If the ptrace request does not exist, this function returns 0
764 and properly sets the have_ptrace_* flag. If the request fails,
765 this function calls perror_with_name. Otherwise, if the request
766 succeeds, then the regcache gets filled and 1 is returned. */
768 fetch_all_fp_regs (struct regcache
*regcache
, int tid
)
770 gdb_fpregset_t fpregs
;
772 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
776 have_ptrace_getsetfpregs
= 0;
779 perror_with_name (_("Couldn't get floating-point registers."));
782 supply_fpregset (regcache
, (const gdb_fpregset_t
*) &fpregs
);
787 /* This is a wrapper for the fetch_all_fp_regs function. It is
788 responsible for verifying if this target has the ptrace request
789 that can be used to fetch all floating-point registers at one
790 shot. If it doesn't, then we should fetch them using the
791 old-fashioned way, which is to iterate over the registers and
792 request them one by one. */
794 fetch_fp_regs (struct regcache
*regcache
, int tid
)
796 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
797 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
800 if (have_ptrace_getsetfpregs
)
801 if (fetch_all_fp_regs (regcache
, tid
))
804 /* If we've hit this point, it doesn't really matter which
805 architecture we are using. We just need to read the
806 registers in the "old-fashioned way". */
807 for (i
= 0; i
< ppc_num_fprs
; i
++)
808 fetch_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
812 fetch_ppc_registers (struct regcache
*regcache
, int tid
)
815 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
816 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
818 fetch_gp_regs (regcache
, tid
);
819 if (tdep
->ppc_fp0_regnum
>= 0)
820 fetch_fp_regs (regcache
, tid
);
821 fetch_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
822 if (tdep
->ppc_ps_regnum
!= -1)
823 fetch_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
824 if (tdep
->ppc_cr_regnum
!= -1)
825 fetch_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
826 if (tdep
->ppc_lr_regnum
!= -1)
827 fetch_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
828 if (tdep
->ppc_ctr_regnum
!= -1)
829 fetch_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
830 if (tdep
->ppc_xer_regnum
!= -1)
831 fetch_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
832 if (tdep
->ppc_mq_regnum
!= -1)
833 fetch_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
834 if (ppc_linux_trap_reg_p (gdbarch
))
836 fetch_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
837 fetch_register (regcache
, tid
, PPC_TRAP_REGNUM
);
839 if (tdep
->ppc_fpscr_regnum
!= -1)
840 fetch_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
841 if (have_ptrace_getvrregs
)
842 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
843 fetch_altivec_registers (regcache
, tid
);
844 if (have_ptrace_getsetvsxregs
)
845 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
846 fetch_vsx_registers (regcache
, tid
);
847 if (tdep
->ppc_ev0_upper_regnum
>= 0)
848 fetch_spe_register (regcache
, tid
, -1);
851 /* Fetch registers from the child process. Fetch all registers if
852 regno == -1, otherwise fetch all general registers or all floating
853 point registers depending upon the value of regno. */
855 ppc_linux_fetch_inferior_registers (struct target_ops
*ops
,
856 struct regcache
*regcache
, int regno
)
858 /* Overload thread id onto process id */
859 int tid
= TIDGET (inferior_ptid
);
861 /* No thread id, just use process id */
863 tid
= PIDGET (inferior_ptid
);
866 fetch_ppc_registers (regcache
, tid
);
868 fetch_register (regcache
, tid
, regno
);
871 /* Store one VSX register. */
873 store_vsx_register (const struct regcache
*regcache
, int tid
, int regno
)
876 gdb_vsxregset_t regs
;
877 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
878 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
879 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
881 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
886 have_ptrace_getsetvsxregs
= 0;
889 perror_with_name (_("Unable to fetch VSX register"));
892 regcache_raw_collect (regcache
, regno
, regs
+
893 (regno
- tdep
->ppc_vsr0_upper_regnum
) * vsxregsize
);
895 ret
= ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
);
897 perror_with_name (_("Unable to store VSX register"));
900 /* Store one register. */
902 store_altivec_register (const struct regcache
*regcache
, int tid
, int regno
)
907 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
908 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
909 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
911 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
916 have_ptrace_getvrregs
= 0;
919 perror_with_name (_("Unable to fetch AltiVec register"));
922 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
923 long on the hardware. */
924 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
925 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
927 regcache_raw_collect (regcache
, regno
,
928 regs
+ (regno
- tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
930 ret
= ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
);
932 perror_with_name (_("Unable to store AltiVec register"));
935 /* Assuming TID referrs to an SPE process, set the top halves of TID's
936 general-purpose registers and its SPE-specific registers to the
937 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
940 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
941 PTRACE_SETEVRREGS requests are supported is isolated here, and in
942 get_spe_registers. */
944 set_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
946 if (have_ptrace_getsetevrregs
)
948 if (ptrace (PTRACE_SETEVRREGS
, tid
, 0, evrregset
) >= 0)
952 /* EIO means that the PTRACE_SETEVRREGS request isn't
953 supported; we fail silently, and don't try the call
956 have_ptrace_getsetevrregs
= 0;
958 /* Anything else needs to be reported. */
959 perror_with_name (_("Unable to set SPE registers"));
964 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
965 If REGNO is -1, write the values of all the SPE-specific
968 store_spe_register (const struct regcache
*regcache
, int tid
, int regno
)
970 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
971 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
972 struct gdb_evrregset_t evrregs
;
974 gdb_assert (sizeof (evrregs
.evr
[0])
975 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
976 gdb_assert (sizeof (evrregs
.acc
)
977 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
978 gdb_assert (sizeof (evrregs
.spefscr
)
979 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
982 /* Since we're going to write out every register, the code below
983 should store to every field of evrregs; if that doesn't happen,
984 make it obvious by initializing it with suspicious values. */
985 memset (&evrregs
, 42, sizeof (evrregs
));
987 /* We can only read and write the entire EVR register set at a
988 time, so to write just a single register, we do a
989 read-modify-write maneuver. */
990 get_spe_registers (tid
, &evrregs
);
996 for (i
= 0; i
< ppc_num_gprs
; i
++)
997 regcache_raw_collect (regcache
,
998 tdep
->ppc_ev0_upper_regnum
+ i
,
1001 else if (tdep
->ppc_ev0_upper_regnum
<= regno
1002 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1003 regcache_raw_collect (regcache
, regno
,
1004 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
1007 || regno
== tdep
->ppc_acc_regnum
)
1008 regcache_raw_collect (regcache
,
1009 tdep
->ppc_acc_regnum
,
1013 || regno
== tdep
->ppc_spefscr_regnum
)
1014 regcache_raw_collect (regcache
,
1015 tdep
->ppc_spefscr_regnum
,
1018 /* Write back the modified register set. */
1019 set_spe_registers (tid
, &evrregs
);
1023 store_register (const struct regcache
*regcache
, int tid
, int regno
)
1025 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1026 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1027 /* This isn't really an address. But ptrace thinks of it as one. */
1028 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
1030 size_t bytes_to_transfer
;
1031 char buf
[MAX_REGISTER_SIZE
];
1033 if (altivec_register_p (gdbarch
, regno
))
1035 store_altivec_register (regcache
, tid
, regno
);
1038 if (vsx_register_p (gdbarch
, regno
))
1040 store_vsx_register (regcache
, tid
, regno
);
1043 else if (spe_register_p (gdbarch
, regno
))
1045 store_spe_register (regcache
, tid
, regno
);
1052 /* First collect the register. Keep in mind that the regcache's
1053 idea of the register's size may not be a multiple of sizeof
1055 memset (buf
, 0, sizeof buf
);
1056 bytes_to_transfer
= align_up (register_size (gdbarch
, regno
), sizeof (long));
1057 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1059 /* Little-endian values always sit at the left end of the buffer. */
1060 regcache_raw_collect (regcache
, regno
, buf
);
1062 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1064 /* Big-endian values sit at the right end of the buffer. */
1065 size_t padding
= (bytes_to_transfer
- register_size (gdbarch
, regno
));
1066 regcache_raw_collect (regcache
, regno
, buf
+ padding
);
1069 for (i
= 0; i
< bytes_to_transfer
; i
+= sizeof (long))
1072 ptrace (PTRACE_POKEUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
,
1074 regaddr
+= sizeof (long);
1077 && (regno
== tdep
->ppc_fpscr_regnum
1078 || regno
== PPC_ORIG_R3_REGNUM
1079 || regno
== PPC_TRAP_REGNUM
))
1081 /* Some older kernel versions don't allow fpscr, orig_r3
1082 or trap to be written. */
1089 sprintf (message
, "writing register %s (#%d)",
1090 gdbarch_register_name (gdbarch
, regno
), regno
);
1091 perror_with_name (message
);
1097 fill_vsxregset (const struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
1100 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1102 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
1104 for (i
= 0; i
< ppc_num_vshrs
; i
++)
1105 regcache_raw_collect (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
1106 *vsxregsetp
+ i
* vsxregsize
);
1110 fill_vrregset (const struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
1113 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1114 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1115 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
1116 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
1117 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
1119 for (i
= 0; i
< num_of_vrregs
; i
++)
1121 /* The last 2 registers of this set are only 32 bit long, not
1122 128, but only VSCR is fetched as a 16 bytes quantity. */
1123 if (i
== (num_of_vrregs
- 2))
1124 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1125 *vrregsetp
+ i
* vrregsize
+ offset
);
1127 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1128 *vrregsetp
+ i
* vrregsize
);
1133 store_vsx_registers (const struct regcache
*regcache
, int tid
)
1136 gdb_vsxregset_t regs
;
1138 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
1143 have_ptrace_getsetvsxregs
= 0;
1146 perror_with_name (_("Couldn't get VSX registers"));
1149 fill_vsxregset (regcache
, ®s
);
1151 if (ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
) < 0)
1152 perror_with_name (_("Couldn't write VSX registers"));
1156 store_altivec_registers (const struct regcache
*regcache
, int tid
)
1159 gdb_vrregset_t regs
;
1161 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
1166 have_ptrace_getvrregs
= 0;
1169 perror_with_name (_("Couldn't get AltiVec registers"));
1172 fill_vrregset (regcache
, ®s
);
1174 if (ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
) < 0)
1175 perror_with_name (_("Couldn't write AltiVec registers"));
1178 /* This function actually issues the request to ptrace, telling
1179 it to store all general-purpose registers present in the specified
1182 If the ptrace request does not exist, this function returns 0
1183 and properly sets the have_ptrace_* flag. If the request fails,
1184 this function calls perror_with_name. Otherwise, if the request
1185 succeeds, then the regcache is stored and 1 is returned. */
1187 store_all_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1189 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1190 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1191 gdb_gregset_t gregset
;
1193 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
1197 have_ptrace_getsetregs
= 0;
1200 perror_with_name (_("Couldn't get general-purpose registers."));
1203 fill_gregset (regcache
, &gregset
, regno
);
1205 if (ptrace (PTRACE_SETREGS
, tid
, 0, (void *) &gregset
) < 0)
1209 have_ptrace_getsetregs
= 0;
1212 perror_with_name (_("Couldn't set general-purpose registers."));
1218 /* This is a wrapper for the store_all_gp_regs function. It is
1219 responsible for verifying if this target has the ptrace request
1220 that can be used to store all general-purpose registers at one
1221 shot. If it doesn't, then we should store them using the
1222 old-fashioned way, which is to iterate over the registers and
1223 store them one by one. */
1225 store_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1227 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1231 if (have_ptrace_getsetregs
)
1232 if (store_all_gp_regs (regcache
, tid
, regno
))
1235 /* If we hit this point, it doesn't really matter which
1236 architecture we are using. We just need to store the
1237 registers in the "old-fashioned way". */
1238 for (i
= 0; i
< ppc_num_gprs
; i
++)
1239 store_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
1242 /* This function actually issues the request to ptrace, telling
1243 it to store all floating-point registers present in the specified
1246 If the ptrace request does not exist, this function returns 0
1247 and properly sets the have_ptrace_* flag. If the request fails,
1248 this function calls perror_with_name. Otherwise, if the request
1249 succeeds, then the regcache is stored and 1 is returned. */
1251 store_all_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1253 gdb_fpregset_t fpregs
;
1255 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1259 have_ptrace_getsetfpregs
= 0;
1262 perror_with_name (_("Couldn't get floating-point registers."));
1265 fill_fpregset (regcache
, &fpregs
, regno
);
1267 if (ptrace (PTRACE_SETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1271 have_ptrace_getsetfpregs
= 0;
1274 perror_with_name (_("Couldn't set floating-point registers."));
1280 /* This is a wrapper for the store_all_fp_regs function. It is
1281 responsible for verifying if this target has the ptrace request
1282 that can be used to store all floating-point registers at one
1283 shot. If it doesn't, then we should store them using the
1284 old-fashioned way, which is to iterate over the registers and
1285 store them one by one. */
1287 store_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1289 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1290 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1293 if (have_ptrace_getsetfpregs
)
1294 if (store_all_fp_regs (regcache
, tid
, regno
))
1297 /* If we hit this point, it doesn't really matter which
1298 architecture we are using. We just need to store the
1299 registers in the "old-fashioned way". */
1300 for (i
= 0; i
< ppc_num_fprs
; i
++)
1301 store_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
1305 store_ppc_registers (const struct regcache
*regcache
, int tid
)
1308 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1309 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1311 store_gp_regs (regcache
, tid
, -1);
1312 if (tdep
->ppc_fp0_regnum
>= 0)
1313 store_fp_regs (regcache
, tid
, -1);
1314 store_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
1315 if (tdep
->ppc_ps_regnum
!= -1)
1316 store_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
1317 if (tdep
->ppc_cr_regnum
!= -1)
1318 store_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
1319 if (tdep
->ppc_lr_regnum
!= -1)
1320 store_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
1321 if (tdep
->ppc_ctr_regnum
!= -1)
1322 store_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
1323 if (tdep
->ppc_xer_regnum
!= -1)
1324 store_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
1325 if (tdep
->ppc_mq_regnum
!= -1)
1326 store_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
1327 if (tdep
->ppc_fpscr_regnum
!= -1)
1328 store_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
1329 if (ppc_linux_trap_reg_p (gdbarch
))
1331 store_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
1332 store_register (regcache
, tid
, PPC_TRAP_REGNUM
);
1334 if (have_ptrace_getvrregs
)
1335 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
1336 store_altivec_registers (regcache
, tid
);
1337 if (have_ptrace_getsetvsxregs
)
1338 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
1339 store_vsx_registers (regcache
, tid
);
1340 if (tdep
->ppc_ev0_upper_regnum
>= 0)
1341 store_spe_register (regcache
, tid
, -1);
1344 /* Fetch the AT_HWCAP entry from the aux vector. */
1345 unsigned long ppc_linux_get_hwcap (void)
1349 if (target_auxv_search (¤t_target
, AT_HWCAP
, &field
))
1350 return (unsigned long) field
;
1355 /* The cached DABR value, to install in new threads.
1356 This variable is used when we are dealing with non-BookE
1358 static long saved_dabr_value
;
1360 /* Global structure that will store information about the available
1361 features on this BookE processor. */
1362 static struct ppc_debug_info booke_debug_info
;
1364 /* Global variable that holds the maximum number of slots that the
1365 kernel will use. This is only used when the processor is BookE. */
1366 static size_t max_slots_number
= 0;
1368 struct hw_break_tuple
1371 struct ppc_hw_breakpoint
*hw_break
;
1374 /* This is an internal VEC created to store information about *points inserted
1375 for each thread. This is used for BookE processors. */
1376 typedef struct thread_points
1378 /* The TID to which this *point relates. */
1380 /* Information about the *point, such as its address, type, etc.
1382 Each element inside this vector corresponds to a hardware
1383 breakpoint or watchpoint in the thread represented by TID. The maximum
1384 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1385 the tuple is NULL, then the position in the vector is free. */
1386 struct hw_break_tuple
*hw_breaks
;
1388 DEF_VEC_P (thread_points_p
);
1390 VEC(thread_points_p
) *ppc_threads
= NULL
;
1392 /* The version of the kernel interface that we will use if the processor is
1394 #define PPC_DEBUG_CURRENT_VERSION 1
1396 /* Returns non-zero if we support the ptrace interface which enables
1397 booke debugging resources. */
1399 have_ptrace_booke_interface (void)
1401 static int have_ptrace_booke_interface
= -1;
1403 if (have_ptrace_booke_interface
== -1)
1407 tid
= TIDGET (inferior_ptid
);
1409 tid
= PIDGET (inferior_ptid
);
1411 /* Check for kernel support for BOOKE debug registers. */
1412 if (ptrace (PPC_PTRACE_GETHWDBGINFO
, tid
, 0, &booke_debug_info
) >= 0)
1414 have_ptrace_booke_interface
= 1;
1415 max_slots_number
= booke_debug_info
.num_instruction_bps
1416 + booke_debug_info
.num_data_bps
+ booke_debug_info
.num_condition_regs
;
1420 /* Old school interface and no BOOKE debug registers support. */
1421 have_ptrace_booke_interface
= 0;
1422 memset (&booke_debug_info
, 0, sizeof (struct ppc_debug_info
));
1426 return have_ptrace_booke_interface
;
1430 ppc_linux_can_use_hw_breakpoint (int type
, int cnt
, int ot
)
1432 int total_hw_wp
, total_hw_bp
;
1434 if (have_ptrace_booke_interface ())
1436 /* For PPC BookE processors, the number of available hardware
1437 watchpoints and breakpoints is stored at the booke_debug_info
1439 total_hw_bp
= booke_debug_info
.num_instruction_bps
;
1440 total_hw_wp
= booke_debug_info
.num_data_bps
;
1444 /* For PPC server processors, we accept 1 hardware watchpoint and 0
1445 hardware breakpoints. */
1450 if (type
== bp_hardware_watchpoint
|| type
== bp_read_watchpoint
1451 || type
== bp_access_watchpoint
|| type
== bp_watchpoint
)
1453 if (cnt
> total_hw_wp
)
1456 else if (type
== bp_hardware_breakpoint
)
1458 if (cnt
> total_hw_bp
)
1462 if (!have_ptrace_booke_interface ())
1465 ptid_t ptid
= inferior_ptid
;
1467 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether
1468 the target has DABR. If either answer is no, the ptrace call will
1469 return -1. Fail in that case. */
1470 tid
= TIDGET (ptid
);
1472 tid
= PIDGET (ptid
);
1474 if (ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, 0) == -1)
1482 ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
1484 /* Handle sub-8-byte quantities. */
1488 /* The new BookE ptrace interface tells if there are alignment restrictions
1489 for watchpoints in the processors. In that case, we use that information
1490 to determine the hardcoded watchable region for watchpoints. */
1491 if (have_ptrace_booke_interface ())
1493 if (booke_debug_info
.data_bp_alignment
1494 && (addr
+ len
> (addr
& ~(booke_debug_info
.data_bp_alignment
- 1))
1495 + booke_debug_info
.data_bp_alignment
))
1498 /* addr+len must fall in the 8 byte watchable region for DABR-based
1499 processors (i.e., server processors). Without the new BookE ptrace
1500 interface, DAC-based processors (i.e., embedded processors) will use
1501 addresses aligned to 4-bytes due to the way the read/write flags are
1502 passed in the old ptrace interface. */
1503 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1504 && (addr
+ len
) > (addr
& ~3) + 4)
1505 || (addr
+ len
) > (addr
& ~7) + 8)
1511 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1513 booke_cmp_hw_point (struct ppc_hw_breakpoint
*a
, struct ppc_hw_breakpoint
*b
)
1515 return (a
->trigger_type
== b
->trigger_type
1516 && a
->addr_mode
== b
->addr_mode
1517 && a
->condition_mode
== b
->condition_mode
1518 && a
->addr
== b
->addr
1519 && a
->addr2
== b
->addr2
1520 && a
->condition_value
== b
->condition_value
);
1523 /* This function can be used to retrieve a thread_points by the TID of the
1524 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1525 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1526 provided TID will be created and returned. */
1527 static struct thread_points
*
1528 booke_find_thread_points_by_tid (int tid
, int alloc_new
)
1531 struct thread_points
*t
;
1533 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, t
); i
++)
1539 /* Do we need to allocate a new point_item
1540 if the wanted one does not exist? */
1543 t
= xmalloc (sizeof (struct thread_points
));
1544 t
->hw_breaks
= xzalloc (max_slots_number
* sizeof (struct hw_break_tuple
));
1546 VEC_safe_push (thread_points_p
, ppc_threads
, t
);
1552 /* This function is a generic wrapper that is responsible for inserting a
1553 *point (i.e., calling `ptrace' in order to issue the request to the
1554 kernel) and registering it internally in GDB. */
1556 booke_insert_point (struct ppc_hw_breakpoint
*b
, int tid
)
1560 struct ppc_hw_breakpoint
*p
= xmalloc (sizeof (struct ppc_hw_breakpoint
));
1561 struct hw_break_tuple
*hw_breaks
;
1562 struct cleanup
*c
= make_cleanup (xfree
, p
);
1563 struct thread_points
*t
;
1564 struct hw_break_tuple
*tuple
;
1566 memcpy (p
, b
, sizeof (struct ppc_hw_breakpoint
));
1569 slot
= ptrace (PPC_PTRACE_SETHWDEBUG
, tid
, 0, p
);
1571 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1573 /* Everything went fine, so we have to register this *point. */
1574 t
= booke_find_thread_points_by_tid (tid
, 1);
1575 gdb_assert (t
!= NULL
);
1576 hw_breaks
= t
->hw_breaks
;
1578 /* Find a free element in the hw_breaks vector. */
1579 for (i
= 0; i
< max_slots_number
; i
++)
1580 if (hw_breaks
[i
].hw_break
== NULL
)
1582 hw_breaks
[i
].slot
= slot
;
1583 hw_breaks
[i
].hw_break
= p
;
1587 gdb_assert (i
!= max_slots_number
);
1589 discard_cleanups (c
);
1592 /* This function is a generic wrapper that is responsible for removing a
1593 *point (i.e., calling `ptrace' in order to issue the request to the
1594 kernel), and unregistering it internally at GDB. */
1596 booke_remove_point (struct ppc_hw_breakpoint
*b
, int tid
)
1599 struct hw_break_tuple
*hw_breaks
;
1600 struct thread_points
*t
;
1602 t
= booke_find_thread_points_by_tid (tid
, 0);
1603 gdb_assert (t
!= NULL
);
1604 hw_breaks
= t
->hw_breaks
;
1606 for (i
= 0; i
< max_slots_number
; i
++)
1607 if (hw_breaks
[i
].hw_break
&& booke_cmp_hw_point (hw_breaks
[i
].hw_break
, b
))
1610 gdb_assert (i
!= max_slots_number
);
1612 /* We have to ignore ENOENT errors because the kernel implements hardware
1613 breakpoints/watchpoints as "one-shot", that is, they are automatically
1614 deleted when hit. */
1616 if (ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
) < 0)
1617 if (errno
!= ENOENT
)
1618 perror_with_name (_("Unexpected error deleting breakpoint or watchpoint"));
1620 xfree (hw_breaks
[i
].hw_break
);
1621 hw_breaks
[i
].hw_break
= NULL
;
1625 ppc_linux_insert_hw_breakpoint (struct gdbarch
*gdbarch
,
1626 struct bp_target_info
*bp_tgt
)
1629 struct lwp_info
*lp
;
1630 struct ppc_hw_breakpoint p
;
1632 if (!have_ptrace_booke_interface ())
1635 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1636 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1637 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1638 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1639 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1641 p
.condition_value
= 0;
1644 booke_insert_point (&p
, TIDGET (ptid
));
1650 ppc_linux_remove_hw_breakpoint (struct gdbarch
*gdbarch
,
1651 struct bp_target_info
*bp_tgt
)
1654 struct lwp_info
*lp
;
1655 struct ppc_hw_breakpoint p
;
1657 if (!have_ptrace_booke_interface ())
1660 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1661 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1662 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1663 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1664 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1666 p
.condition_value
= 0;
1669 booke_remove_point (&p
, TIDGET (ptid
));
1675 get_trigger_type (int rw
)
1680 t
= PPC_BREAKPOINT_TRIGGER_READ
;
1681 else if (rw
== hw_write
)
1682 t
= PPC_BREAKPOINT_TRIGGER_WRITE
;
1684 t
= PPC_BREAKPOINT_TRIGGER_READ
| PPC_BREAKPOINT_TRIGGER_WRITE
;
1689 /* Check whether we have at least one free DVC register. */
1691 can_use_watchpoint_cond_accel (void)
1693 struct thread_points
*p
;
1694 int tid
= TIDGET (inferior_ptid
);
1695 int cnt
= booke_debug_info
.num_condition_regs
, i
;
1696 CORE_ADDR tmp_value
;
1698 if (!have_ptrace_booke_interface () || cnt
== 0)
1701 p
= booke_find_thread_points_by_tid (tid
, 0);
1705 for (i
= 0; i
< max_slots_number
; i
++)
1706 if (p
->hw_breaks
[i
].hw_break
!= NULL
1707 && (p
->hw_breaks
[i
].hw_break
->condition_mode
1708 != PPC_BREAKPOINT_CONDITION_NONE
))
1711 /* There are no available slots now. */
1719 /* Calculate the enable bits and the contents of the Data Value Compare
1720 debug register present in BookE processors.
1722 ADDR is the address to be watched, LEN is the length of watched data
1723 and DATA_VALUE is the value which will trigger the watchpoint.
1724 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1725 CONDITION_VALUE will hold the value which should be put in the
1728 calculate_dvc (CORE_ADDR addr
, int len
, CORE_ADDR data_value
,
1729 uint32_t *condition_mode
, uint64_t *condition_value
)
1731 int i
, num_byte_enable
, align_offset
, num_bytes_off_dvc
,
1732 rightmost_enabled_byte
;
1733 CORE_ADDR addr_end_data
, addr_end_dvc
;
1735 /* The DVC register compares bytes within fixed-length windows which
1736 are word-aligned, with length equal to that of the DVC register.
1737 We need to calculate where our watch region is relative to that
1738 window and enable comparison of the bytes which fall within it. */
1740 align_offset
= addr
% booke_debug_info
.sizeof_condition
;
1741 addr_end_data
= addr
+ len
;
1742 addr_end_dvc
= (addr
- align_offset
1743 + booke_debug_info
.sizeof_condition
);
1744 num_bytes_off_dvc
= (addr_end_data
> addr_end_dvc
)?
1745 addr_end_data
- addr_end_dvc
: 0;
1746 num_byte_enable
= len
- num_bytes_off_dvc
;
1747 /* Here, bytes are numbered from right to left. */
1748 rightmost_enabled_byte
= (addr_end_data
< addr_end_dvc
)?
1749 addr_end_dvc
- addr_end_data
: 0;
1751 *condition_mode
= PPC_BREAKPOINT_CONDITION_AND
;
1752 for (i
= 0; i
< num_byte_enable
; i
++)
1753 *condition_mode
|= PPC_BREAKPOINT_CONDITION_BE (i
+ rightmost_enabled_byte
);
1755 /* Now we need to match the position within the DVC of the comparison
1756 value with where the watch region is relative to the window
1757 (i.e., the ALIGN_OFFSET). */
1759 *condition_value
= ((uint64_t) data_value
>> num_bytes_off_dvc
* 8
1760 << rightmost_enabled_byte
* 8);
1763 /* Return the number of memory locations that need to be accessed to
1764 evaluate the expression which generated the given value chain.
1765 Returns -1 if there's any register access involved, or if there are
1766 other kinds of values which are not acceptable in a condition
1767 expression (e.g., lval_computed or lval_internalvar). */
1769 num_memory_accesses (struct value
*v
)
1771 int found_memory_cnt
= 0;
1772 struct value
*head
= v
;
1774 /* The idea here is that evaluating an expression generates a series
1775 of values, one holding the value of every subexpression. (The
1776 expression a*b+c has five subexpressions: a, b, a*b, c, and
1777 a*b+c.) GDB's values hold almost enough information to establish
1778 the criteria given above --- they identify memory lvalues,
1779 register lvalues, computed values, etcetera. So we can evaluate
1780 the expression, and then scan the chain of values that leaves
1781 behind to determine the memory locations involved in the evaluation
1784 However, I don't think that the values returned by inferior
1785 function calls are special in any way. So this function may not
1786 notice that an expression contains an inferior function call.
1789 for (; v
; v
= value_next (v
))
1791 /* Constants and values from the history are fine. */
1792 if (VALUE_LVAL (v
) == not_lval
|| deprecated_value_modifiable (v
) == 0)
1794 else if (VALUE_LVAL (v
) == lval_memory
)
1796 /* A lazy memory lvalue is one that GDB never needed to fetch;
1797 we either just used its address (e.g., `a' in `a.b') or
1798 we never needed it at all (e.g., `a' in `a,b'). */
1799 if (!value_lazy (v
))
1802 /* Other kinds of values are not fine. */
1807 return found_memory_cnt
;
1810 /* Verifies whether the expression COND can be implemented using the
1811 DVC (Data Value Compare) register in BookE processors. The expression
1812 must test the watch value for equality with a constant expression.
1813 If the function returns 1, DATA_VALUE will contain the constant against
1814 which the watch value should be compared. */
1816 check_condition (CORE_ADDR watch_addr
, struct expression
*cond
,
1817 CORE_ADDR
*data_value
)
1819 int pc
= 1, num_accesses_left
, num_accesses_right
;
1820 struct value
*left_val
, *right_val
, *left_chain
, *right_chain
;
1822 if (cond
->elts
[0].opcode
!= BINOP_EQUAL
)
1825 fetch_subexp_value (cond
, &pc
, &left_val
, NULL
, &left_chain
);
1826 num_accesses_left
= num_memory_accesses (left_chain
);
1828 if (left_val
== NULL
|| num_accesses_left
< 0)
1830 free_value_chain (left_chain
);
1835 fetch_subexp_value (cond
, &pc
, &right_val
, NULL
, &right_chain
);
1836 num_accesses_right
= num_memory_accesses (right_chain
);
1838 if (right_val
== NULL
|| num_accesses_right
< 0)
1840 free_value_chain (left_chain
);
1841 free_value_chain (right_chain
);
1846 if (num_accesses_left
== 1 && num_accesses_right
== 0
1847 && VALUE_LVAL (left_val
) == lval_memory
1848 && value_address (left_val
) == watch_addr
)
1849 *data_value
= value_as_long (right_val
);
1850 else if (num_accesses_left
== 0 && num_accesses_right
== 1
1851 && VALUE_LVAL (right_val
) == lval_memory
1852 && value_address (right_val
) == watch_addr
)
1853 *data_value
= value_as_long (left_val
);
1856 free_value_chain (left_chain
);
1857 free_value_chain (right_chain
);
1862 free_value_chain (left_chain
);
1863 free_value_chain (right_chain
);
1868 /* Return non-zero if the target is capable of using hardware to evaluate
1869 the condition expression, thus only triggering the watchpoint when it is
1872 ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr
, int len
, int rw
,
1873 struct expression
*cond
)
1875 CORE_ADDR data_value
;
1877 return (have_ptrace_booke_interface ()
1878 && booke_debug_info
.num_condition_regs
> 0
1879 && check_condition (addr
, cond
, &data_value
));
1883 ppc_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int rw
,
1884 struct expression
*cond
)
1886 struct lwp_info
*lp
;
1890 if (have_ptrace_booke_interface ())
1892 struct ppc_hw_breakpoint p
;
1893 CORE_ADDR data_value
;
1895 if (cond
&& can_use_watchpoint_cond_accel ()
1896 && check_condition (addr
, cond
, &data_value
))
1897 calculate_dvc (addr
, len
, data_value
, &p
.condition_mode
,
1898 &p
.condition_value
);
1901 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1902 p
.condition_value
= 0;
1905 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1906 p
.trigger_type
= get_trigger_type (rw
);
1907 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1908 p
.addr
= (uint64_t) addr
;
1912 booke_insert_point (&p
, TIDGET (ptid
));
1919 long read_mode
, write_mode
;
1921 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1923 /* PowerPC 440 requires only the read/write flags to be passed
1930 /* PowerPC 970 and other DABR-based processors are required to pass
1931 the Breakpoint Translation bit together with the flags. */
1936 dabr_value
= addr
& ~(read_mode
| write_mode
);
1940 /* Set read and translate bits. */
1941 dabr_value
|= read_mode
;
1944 /* Set write and translate bits. */
1945 dabr_value
|= write_mode
;
1948 /* Set read, write and translate bits. */
1949 dabr_value
|= read_mode
| write_mode
;
1953 saved_dabr_value
= dabr_value
;
1956 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (ptid
), 0,
1957 saved_dabr_value
) < 0)
1967 ppc_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int rw
,
1968 struct expression
*cond
)
1970 struct lwp_info
*lp
;
1974 if (have_ptrace_booke_interface ())
1976 struct ppc_hw_breakpoint p
;
1977 CORE_ADDR data_value
;
1979 if (cond
&& booke_debug_info
.num_condition_regs
> 0
1980 && check_condition (addr
, cond
, &data_value
))
1981 calculate_dvc (addr
, len
, data_value
, &p
.condition_mode
,
1982 &p
.condition_value
);
1985 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1986 p
.condition_value
= 0;
1989 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1990 p
.trigger_type
= get_trigger_type (rw
);
1991 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1992 p
.addr
= (uint64_t) addr
;
1996 booke_remove_point (&p
, TIDGET (ptid
));
2002 saved_dabr_value
= 0;
2004 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (ptid
), 0,
2005 saved_dabr_value
) < 0)
2015 ppc_linux_new_thread (ptid_t ptid
)
2017 int tid
= TIDGET (ptid
);
2019 if (have_ptrace_booke_interface ())
2022 struct thread_points
*p
;
2023 struct hw_break_tuple
*hw_breaks
;
2025 if (VEC_empty (thread_points_p
, ppc_threads
))
2028 /* Get a list of breakpoints from any thread. */
2029 p
= VEC_last (thread_points_p
, ppc_threads
);
2030 hw_breaks
= p
->hw_breaks
;
2032 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2033 for (i
= 0; i
< max_slots_number
; i
++)
2034 if (hw_breaks
[i
].hw_break
)
2035 booke_insert_point (hw_breaks
[i
].hw_break
, tid
);
2038 ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, saved_dabr_value
);
2042 ppc_linux_thread_exit (struct thread_info
*tp
, int silent
)
2045 int tid
= TIDGET (tp
->ptid
);
2046 struct hw_break_tuple
*hw_breaks
;
2047 struct thread_points
*t
= NULL
, *p
;
2049 if (!have_ptrace_booke_interface ())
2052 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, p
); i
++)
2062 VEC_unordered_remove (thread_points_p
, ppc_threads
, i
);
2064 hw_breaks
= t
->hw_breaks
;
2066 for (i
= 0; i
< max_slots_number
; i
++)
2067 if (hw_breaks
[i
].hw_break
)
2068 xfree (hw_breaks
[i
].hw_break
);
2070 xfree (t
->hw_breaks
);
2075 ppc_linux_stopped_data_address (struct target_ops
*target
, CORE_ADDR
*addr_p
)
2077 struct siginfo
*siginfo_p
;
2079 siginfo_p
= linux_nat_get_siginfo (inferior_ptid
);
2081 if (siginfo_p
->si_signo
!= SIGTRAP
2082 || (siginfo_p
->si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2085 if (have_ptrace_booke_interface ())
2088 struct thread_points
*t
;
2089 struct hw_break_tuple
*hw_breaks
;
2090 /* The index (or slot) of the *point is passed in the si_errno field. */
2091 int slot
= siginfo_p
->si_errno
;
2093 t
= booke_find_thread_points_by_tid (TIDGET (inferior_ptid
), 0);
2095 /* Find out if this *point is a hardware breakpoint.
2096 If so, we should return 0. */
2099 hw_breaks
= t
->hw_breaks
;
2100 for (i
= 0; i
< max_slots_number
; i
++)
2101 if (hw_breaks
[i
].hw_break
&& hw_breaks
[i
].slot
== slot
2102 && hw_breaks
[i
].hw_break
->trigger_type
2103 == PPC_BREAKPOINT_TRIGGER_EXECUTE
)
2108 *addr_p
= (CORE_ADDR
) (uintptr_t) siginfo_p
->si_addr
;
2113 ppc_linux_stopped_by_watchpoint (void)
2116 return ppc_linux_stopped_data_address (¤t_target
, &addr
);
2120 ppc_linux_watchpoint_addr_within_range (struct target_ops
*target
,
2122 CORE_ADDR start
, int length
)
2126 if (have_ptrace_booke_interface ()
2127 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2128 return start
<= addr
&& start
+ length
>= addr
;
2129 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2136 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2137 return start
<= addr
+ mask
&& start
+ length
- 1 >= addr
;
2141 ppc_linux_store_inferior_registers (struct target_ops
*ops
,
2142 struct regcache
*regcache
, int regno
)
2144 /* Overload thread id onto process id */
2145 int tid
= TIDGET (inferior_ptid
);
2147 /* No thread id, just use process id */
2149 tid
= PIDGET (inferior_ptid
);
2152 store_register (regcache
, tid
, regno
);
2154 store_ppc_registers (regcache
, tid
);
2157 /* Functions for transferring registers between a gregset_t or fpregset_t
2158 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2159 by the ptrace interface, not the current program's ABI. eg. If a
2160 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2161 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2164 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
2166 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2168 ppc_supply_gregset (regset
, regcache
, -1, gregsetp
, sizeof (*gregsetp
));
2172 fill_gregset (const struct regcache
*regcache
,
2173 gdb_gregset_t
*gregsetp
, int regno
)
2175 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2178 memset (gregsetp
, 0, sizeof (*gregsetp
));
2179 ppc_collect_gregset (regset
, regcache
, regno
, gregsetp
, sizeof (*gregsetp
));
2183 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
* fpregsetp
)
2185 const struct regset
*regset
= ppc_linux_fpregset ();
2187 ppc_supply_fpregset (regset
, regcache
, -1,
2188 fpregsetp
, sizeof (*fpregsetp
));
2192 fill_fpregset (const struct regcache
*regcache
,
2193 gdb_fpregset_t
*fpregsetp
, int regno
)
2195 const struct regset
*regset
= ppc_linux_fpregset ();
2197 ppc_collect_fpregset (regset
, regcache
, regno
,
2198 fpregsetp
, sizeof (*fpregsetp
));
2202 ppc_linux_target_wordsize (void)
2206 /* Check for 64-bit inferior process. This is the case when the host is
2207 64-bit, and in addition the top bit of the MSR register is set. */
2208 #ifdef __powerpc64__
2211 int tid
= TIDGET (inferior_ptid
);
2213 tid
= PIDGET (inferior_ptid
);
2216 msr
= (long) ptrace (PTRACE_PEEKUSER
, tid
, PT_MSR
* 8, 0);
2217 if (errno
== 0 && msr
< 0)
2225 ppc_linux_auxv_parse (struct target_ops
*ops
, gdb_byte
**readptr
,
2226 gdb_byte
*endptr
, CORE_ADDR
*typep
, CORE_ADDR
*valp
)
2228 int sizeof_auxv_field
= ppc_linux_target_wordsize ();
2229 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch
);
2230 gdb_byte
*ptr
= *readptr
;
2235 if (endptr
- ptr
< sizeof_auxv_field
* 2)
2238 *typep
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2239 ptr
+= sizeof_auxv_field
;
2240 *valp
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2241 ptr
+= sizeof_auxv_field
;
2247 static const struct target_desc
*
2248 ppc_linux_read_description (struct target_ops
*ops
)
2255 int tid
= TIDGET (inferior_ptid
);
2257 tid
= PIDGET (inferior_ptid
);
2259 if (have_ptrace_getsetevrregs
)
2261 struct gdb_evrregset_t evrregset
;
2263 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, &evrregset
) >= 0)
2264 return tdesc_powerpc_e500l
;
2266 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2267 Anything else needs to be reported. */
2268 else if (errno
!= EIO
)
2269 perror_with_name (_("Unable to fetch SPE registers"));
2272 if (have_ptrace_getsetvsxregs
)
2274 gdb_vsxregset_t vsxregset
;
2276 if (ptrace (PTRACE_GETVSXREGS
, tid
, 0, &vsxregset
) >= 0)
2279 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2280 Anything else needs to be reported. */
2281 else if (errno
!= EIO
)
2282 perror_with_name (_("Unable to fetch VSX registers"));
2285 if (have_ptrace_getvrregs
)
2287 gdb_vrregset_t vrregset
;
2289 if (ptrace (PTRACE_GETVRREGS
, tid
, 0, &vrregset
) >= 0)
2292 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2293 Anything else needs to be reported. */
2294 else if (errno
!= EIO
)
2295 perror_with_name (_("Unable to fetch AltiVec registers"));
2298 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2299 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2300 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2301 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2302 half of the register are for Decimal Floating Point, we check if that
2303 feature is available to decide the size of the FPSCR. */
2304 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP
)
2307 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL
)
2310 if (ppc_linux_target_wordsize () == 8)
2313 return tdesc_powerpc_cell64l
;
2315 return isa205
? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l
;
2317 return isa205
? tdesc_powerpc_isa205_altivec64l
: tdesc_powerpc_altivec64l
;
2319 return isa205
? tdesc_powerpc_isa205_64l
: tdesc_powerpc_64l
;
2323 return tdesc_powerpc_cell32l
;
2325 return isa205
? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l
;
2327 return isa205
? tdesc_powerpc_isa205_altivec32l
: tdesc_powerpc_altivec32l
;
2329 return isa205
? tdesc_powerpc_isa205_32l
: tdesc_powerpc_32l
;
2332 void _initialize_ppc_linux_nat (void);
2335 _initialize_ppc_linux_nat (void)
2337 struct target_ops
*t
;
2339 /* Fill in the generic GNU/Linux methods. */
2340 t
= linux_target ();
2342 /* Add our register access methods. */
2343 t
->to_fetch_registers
= ppc_linux_fetch_inferior_registers
;
2344 t
->to_store_registers
= ppc_linux_store_inferior_registers
;
2346 /* Add our breakpoint/watchpoint methods. */
2347 t
->to_can_use_hw_breakpoint
= ppc_linux_can_use_hw_breakpoint
;
2348 t
->to_insert_hw_breakpoint
= ppc_linux_insert_hw_breakpoint
;
2349 t
->to_remove_hw_breakpoint
= ppc_linux_remove_hw_breakpoint
;
2350 t
->to_region_ok_for_hw_watchpoint
= ppc_linux_region_ok_for_hw_watchpoint
;
2351 t
->to_insert_watchpoint
= ppc_linux_insert_watchpoint
;
2352 t
->to_remove_watchpoint
= ppc_linux_remove_watchpoint
;
2353 t
->to_stopped_by_watchpoint
= ppc_linux_stopped_by_watchpoint
;
2354 t
->to_stopped_data_address
= ppc_linux_stopped_data_address
;
2355 t
->to_watchpoint_addr_within_range
= ppc_linux_watchpoint_addr_within_range
;
2356 t
->to_can_accel_watchpoint_condition
= ppc_linux_can_accel_watchpoint_condition
;
2358 t
->to_read_description
= ppc_linux_read_description
;
2359 t
->to_auxv_parse
= ppc_linux_auxv_parse
;
2361 observer_attach_thread_exit (ppc_linux_thread_exit
);
2363 /* Register the target. */
2364 linux_nat_add_target (t
);
2365 linux_nat_set_new_thread (t
, ppc_linux_new_thread
);