1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003,
4 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "gdb_string.h"
27 #include "gdb_assert.h"
29 #include "linux-nat.h"
32 #include <sys/types.h>
33 #include <sys/param.h>
36 #include <sys/ioctl.h>
39 #include <sys/procfs.h>
40 #include <sys/ptrace.h>
42 /* Prototypes for supply_gregset etc. */
45 #include "ppc-linux-tdep.h"
47 /* This sometimes isn't defined. */
55 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
56 configure time check. Some older glibc's (for instance 2.2.1)
57 don't have a specific powerpc version of ptrace.h, and fall back on
58 a generic one. In such cases, sys/ptrace.h defines
59 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
60 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
61 PTRACE_SETVRREGS to be. This also makes a configury check pretty
64 /* These definitions should really come from the glibc header files,
65 but Glibc doesn't know about the vrregs yet. */
66 #ifndef PTRACE_GETVRREGS
67 #define PTRACE_GETVRREGS 18
68 #define PTRACE_SETVRREGS 19
72 /* Similarly for the ptrace requests for getting / setting the SPE
73 registers (ev0 -- ev31, acc, and spefscr). See the description of
74 gdb_evrregset_t for details. */
75 #ifndef PTRACE_GETEVRREGS
76 #define PTRACE_GETEVRREGS 20
77 #define PTRACE_SETEVRREGS 21
80 /* Similarly for the hardware watchpoint support. */
81 #ifndef PTRACE_GET_DEBUGREG
82 #define PTRACE_GET_DEBUGREG 25
84 #ifndef PTRACE_SET_DEBUGREG
85 #define PTRACE_SET_DEBUGREG 26
87 #ifndef PTRACE_GETSIGINFO
88 #define PTRACE_GETSIGINFO 0x4202
91 /* This oddity is because the Linux kernel defines elf_vrregset_t as
92 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
93 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
94 the vrsave as an extra 4 bytes at the end. I opted for creating a
95 flat array of chars, so that it is easier to manipulate for gdb.
97 There are 32 vector registers 16 bytes longs, plus a VSCR register
98 which is only 4 bytes long, but is fetched as a 16 bytes
99 quantity. Up to here we have the elf_vrregset_t structure.
100 Appended to this there is space for the VRSAVE register: 4 bytes.
101 Even though this vrsave register is not included in the regset
102 typedef, it is handled by the ptrace requests.
104 Note that GNU/Linux doesn't support little endian PPC hardware,
105 therefore the offset at which the real value of the VSCR register
106 is located will be always 12 bytes.
108 The layout is like this (where x is the actual value of the vscr reg): */
112 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
113 <-------> <-------><-------><->
118 #define SIZEOF_VRREGS 33*16+4
120 typedef char gdb_vrregset_t
[SIZEOF_VRREGS
];
123 /* On PPC processors that support the the Signal Processing Extension
124 (SPE) APU, the general-purpose registers are 64 bits long.
125 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
126 ptrace calls only access the lower half of each register, to allow
127 them to behave the same way they do on non-SPE systems. There's a
128 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
129 read and write the top halves of all the general-purpose registers
130 at once, along with some SPE-specific registers.
132 GDB itself continues to claim the general-purpose registers are 32
133 bits long. It has unnamed raw registers that hold the upper halves
134 of the gprs, and the the full 64-bit SIMD views of the registers,
135 'ev0' -- 'ev31', are pseudo-registers that splice the top and
136 bottom halves together.
138 This is the structure filled in by PTRACE_GETEVRREGS and written to
139 the inferior's registers by PTRACE_SETEVRREGS. */
140 struct gdb_evrregset_t
142 unsigned long evr
[32];
143 unsigned long long acc
;
144 unsigned long spefscr
;
148 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
149 PTRACE_SETVRREGS requests, for reading and writing the Altivec
150 registers. Zero if we've tried one of them and gotten an
152 int have_ptrace_getvrregs
= 1;
154 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
155 PTRACE_SETEVRREGS requests, for reading and writing the SPE
156 registers. Zero if we've tried one of them and gotten an
158 int have_ptrace_getsetevrregs
= 1;
161 /* registers layout, as presented by the ptrace interface:
162 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
163 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
164 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
165 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
166 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
167 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
168 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
169 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
170 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
174 ppc_register_u_addr (struct gdbarch
*gdbarch
, int regno
)
177 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
178 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
179 interface, and not the wordsize of the program's ABI. */
180 int wordsize
= sizeof (long);
182 /* General purpose registers occupy 1 slot each in the buffer */
183 if (regno
>= tdep
->ppc_gp0_regnum
184 && regno
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
185 u_addr
= ((regno
- tdep
->ppc_gp0_regnum
+ PT_R0
) * wordsize
);
187 /* Floating point regs: eight bytes each in both 32- and 64-bit
188 ptrace interfaces. Thus, two slots each in 32-bit interface, one
189 slot each in 64-bit interface. */
190 if (tdep
->ppc_fp0_regnum
>= 0
191 && regno
>= tdep
->ppc_fp0_regnum
192 && regno
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
193 u_addr
= (PT_FPR0
* wordsize
) + ((regno
- tdep
->ppc_fp0_regnum
) * 8);
195 /* UISA special purpose registers: 1 slot each */
196 if (regno
== gdbarch_pc_regnum (gdbarch
))
197 u_addr
= PT_NIP
* wordsize
;
198 if (regno
== tdep
->ppc_lr_regnum
)
199 u_addr
= PT_LNK
* wordsize
;
200 if (regno
== tdep
->ppc_cr_regnum
)
201 u_addr
= PT_CCR
* wordsize
;
202 if (regno
== tdep
->ppc_xer_regnum
)
203 u_addr
= PT_XER
* wordsize
;
204 if (regno
== tdep
->ppc_ctr_regnum
)
205 u_addr
= PT_CTR
* wordsize
;
207 if (regno
== tdep
->ppc_mq_regnum
)
208 u_addr
= PT_MQ
* wordsize
;
210 if (regno
== tdep
->ppc_ps_regnum
)
211 u_addr
= PT_MSR
* wordsize
;
212 if (regno
== PPC_ORIG_R3_REGNUM
)
213 u_addr
= PT_ORIG_R3
* wordsize
;
214 if (regno
== PPC_TRAP_REGNUM
)
215 u_addr
= PT_TRAP
* wordsize
;
216 if (tdep
->ppc_fpscr_regnum
>= 0
217 && regno
== tdep
->ppc_fpscr_regnum
)
219 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
220 kernel headers incorrectly contained the 32-bit definition of
221 PT_FPSCR. For the 32-bit definition, floating-point
222 registers occupy two 32-bit "slots", and the FPSCR lives in
223 the secondhalf of such a slot-pair (hence +1). For 64-bit,
224 the FPSCR instead occupies the full 64-bit 2-word-slot and
225 hence no adjustment is necessary. Hack around this. */
226 if (wordsize
== 8 && PT_FPSCR
== (48 + 32 + 1))
227 u_addr
= (48 + 32) * wordsize
;
229 u_addr
= PT_FPSCR
* wordsize
;
234 /* The Linux kernel ptrace interface for AltiVec registers uses the
235 registers set mechanism, as opposed to the interface for all the
236 other registers, that stores/fetches each register individually. */
238 fetch_altivec_register (struct regcache
*regcache
, int tid
, int regno
)
243 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
244 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
245 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
247 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
252 have_ptrace_getvrregs
= 0;
255 perror_with_name (_("Unable to fetch AltiVec register"));
258 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
259 long on the hardware. We deal only with the lower 4 bytes of the
260 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
261 there is no need to define an offset for it. */
262 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
263 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
265 regcache_raw_supply (regcache
, regno
,
266 regs
+ (regno
- tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
269 /* Fetch the top 32 bits of TID's general-purpose registers and the
270 SPE-specific registers, and place the results in EVRREGSET. If we
271 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
274 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
275 PTRACE_SETEVRREGS requests are supported is isolated here, and in
276 set_spe_registers. */
278 get_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
280 if (have_ptrace_getsetevrregs
)
282 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, evrregset
) >= 0)
286 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
287 we just return zeros. */
289 have_ptrace_getsetevrregs
= 0;
291 /* Anything else needs to be reported. */
292 perror_with_name (_("Unable to fetch SPE registers"));
296 memset (evrregset
, 0, sizeof (*evrregset
));
299 /* Supply values from TID for SPE-specific raw registers: the upper
300 halves of the GPRs, the accumulator, and the spefscr. REGNO must
301 be the number of an upper half register, acc, spefscr, or -1 to
302 supply the values of all registers. */
304 fetch_spe_register (struct regcache
*regcache
, int tid
, int regno
)
306 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
307 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
308 struct gdb_evrregset_t evrregs
;
310 gdb_assert (sizeof (evrregs
.evr
[0])
311 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
312 gdb_assert (sizeof (evrregs
.acc
)
313 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
314 gdb_assert (sizeof (evrregs
.spefscr
)
315 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
317 get_spe_registers (tid
, &evrregs
);
323 for (i
= 0; i
< ppc_num_gprs
; i
++)
324 regcache_raw_supply (regcache
, tdep
->ppc_ev0_upper_regnum
+ i
,
327 else if (tdep
->ppc_ev0_upper_regnum
<= regno
328 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
329 regcache_raw_supply (regcache
, regno
,
330 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
333 || regno
== tdep
->ppc_acc_regnum
)
334 regcache_raw_supply (regcache
, tdep
->ppc_acc_regnum
, &evrregs
.acc
);
337 || regno
== tdep
->ppc_spefscr_regnum
)
338 regcache_raw_supply (regcache
, tdep
->ppc_spefscr_regnum
,
343 fetch_register (struct regcache
*regcache
, int tid
, int regno
)
345 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
346 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
347 /* This isn't really an address. But ptrace thinks of it as one. */
348 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
349 int bytes_transferred
;
350 unsigned int offset
; /* Offset of registers within the u area. */
351 char buf
[MAX_REGISTER_SIZE
];
353 if (altivec_register_p (gdbarch
, regno
))
355 /* If this is the first time through, or if it is not the first
356 time through, and we have comfirmed that there is kernel
357 support for such a ptrace request, then go and fetch the
359 if (have_ptrace_getvrregs
)
361 fetch_altivec_register (regcache
, tid
, regno
);
364 /* If we have discovered that there is no ptrace support for
365 AltiVec registers, fall through and return zeroes, because
366 regaddr will be -1 in this case. */
368 else if (spe_register_p (gdbarch
, regno
))
370 fetch_spe_register (regcache
, tid
, regno
);
376 memset (buf
, '\0', register_size (gdbarch
, regno
)); /* Supply zeroes */
377 regcache_raw_supply (regcache
, regno
, buf
);
381 /* Read the raw register using sizeof(long) sized chunks. On a
382 32-bit platform, 64-bit floating-point registers will require two
384 for (bytes_transferred
= 0;
385 bytes_transferred
< register_size (gdbarch
, regno
);
386 bytes_transferred
+= sizeof (long))
389 *(long *) &buf
[bytes_transferred
]
390 = ptrace (PTRACE_PEEKUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, 0);
391 regaddr
+= sizeof (long);
395 sprintf (message
, "reading register %s (#%d)",
396 gdbarch_register_name (gdbarch
, regno
), regno
);
397 perror_with_name (message
);
401 /* Now supply the register. Keep in mind that the regcache's idea
402 of the register's size may not be a multiple of sizeof
404 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
406 /* Little-endian values are always found at the left end of the
407 bytes transferred. */
408 regcache_raw_supply (regcache
, regno
, buf
);
410 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
412 /* Big-endian values are found at the right end of the bytes
414 size_t padding
= (bytes_transferred
- register_size (gdbarch
, regno
));
415 regcache_raw_supply (regcache
, regno
, buf
+ padding
);
418 internal_error (__FILE__
, __LINE__
,
419 _("fetch_register: unexpected byte order: %d"),
420 gdbarch_byte_order (gdbarch
));
424 supply_vrregset (struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
427 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
428 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
429 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
430 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
431 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
433 for (i
= 0; i
< num_of_vrregs
; i
++)
435 /* The last 2 registers of this set are only 32 bit long, not
436 128. However an offset is necessary only for VSCR because it
437 occupies a whole vector, while VRSAVE occupies a full 4 bytes
439 if (i
== (num_of_vrregs
- 2))
440 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
441 *vrregsetp
+ i
* vrregsize
+ offset
);
443 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
444 *vrregsetp
+ i
* vrregsize
);
449 fetch_altivec_registers (struct regcache
*regcache
, int tid
)
454 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
459 have_ptrace_getvrregs
= 0;
462 perror_with_name (_("Unable to fetch AltiVec registers"));
464 supply_vrregset (regcache
, ®s
);
468 fetch_ppc_registers (struct regcache
*regcache
, int tid
)
471 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
472 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
474 for (i
= 0; i
< ppc_num_gprs
; i
++)
475 fetch_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
476 if (tdep
->ppc_fp0_regnum
>= 0)
477 for (i
= 0; i
< ppc_num_fprs
; i
++)
478 fetch_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
479 fetch_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
480 if (tdep
->ppc_ps_regnum
!= -1)
481 fetch_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
482 if (tdep
->ppc_cr_regnum
!= -1)
483 fetch_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
484 if (tdep
->ppc_lr_regnum
!= -1)
485 fetch_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
486 if (tdep
->ppc_ctr_regnum
!= -1)
487 fetch_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
488 if (tdep
->ppc_xer_regnum
!= -1)
489 fetch_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
490 if (tdep
->ppc_mq_regnum
!= -1)
491 fetch_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
492 if (ppc_linux_trap_reg_p (gdbarch
))
494 fetch_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
495 fetch_register (regcache
, tid
, PPC_TRAP_REGNUM
);
497 if (tdep
->ppc_fpscr_regnum
!= -1)
498 fetch_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
499 if (have_ptrace_getvrregs
)
500 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
501 fetch_altivec_registers (regcache
, tid
);
502 if (tdep
->ppc_ev0_upper_regnum
>= 0)
503 fetch_spe_register (regcache
, tid
, -1);
506 /* Fetch registers from the child process. Fetch all registers if
507 regno == -1, otherwise fetch all general registers or all floating
508 point registers depending upon the value of regno. */
510 ppc_linux_fetch_inferior_registers (struct regcache
*regcache
, int regno
)
512 /* Overload thread id onto process id */
513 int tid
= TIDGET (inferior_ptid
);
515 /* No thread id, just use process id */
517 tid
= PIDGET (inferior_ptid
);
520 fetch_ppc_registers (regcache
, tid
);
522 fetch_register (regcache
, tid
, regno
);
525 /* Store one register. */
527 store_altivec_register (const struct regcache
*regcache
, int tid
, int regno
)
532 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
533 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
534 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
536 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
541 have_ptrace_getvrregs
= 0;
544 perror_with_name (_("Unable to fetch AltiVec register"));
547 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
548 long on the hardware. */
549 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
550 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
552 regcache_raw_collect (regcache
, regno
,
553 regs
+ (regno
- tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
555 ret
= ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
);
557 perror_with_name (_("Unable to store AltiVec register"));
560 /* Assuming TID referrs to an SPE process, set the top halves of TID's
561 general-purpose registers and its SPE-specific registers to the
562 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
565 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
566 PTRACE_SETEVRREGS requests are supported is isolated here, and in
567 get_spe_registers. */
569 set_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
571 if (have_ptrace_getsetevrregs
)
573 if (ptrace (PTRACE_SETEVRREGS
, tid
, 0, evrregset
) >= 0)
577 /* EIO means that the PTRACE_SETEVRREGS request isn't
578 supported; we fail silently, and don't try the call
581 have_ptrace_getsetevrregs
= 0;
583 /* Anything else needs to be reported. */
584 perror_with_name (_("Unable to set SPE registers"));
589 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
590 If REGNO is -1, write the values of all the SPE-specific
593 store_spe_register (const struct regcache
*regcache
, int tid
, int regno
)
595 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
596 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
597 struct gdb_evrregset_t evrregs
;
599 gdb_assert (sizeof (evrregs
.evr
[0])
600 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
601 gdb_assert (sizeof (evrregs
.acc
)
602 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
603 gdb_assert (sizeof (evrregs
.spefscr
)
604 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
607 /* Since we're going to write out every register, the code below
608 should store to every field of evrregs; if that doesn't happen,
609 make it obvious by initializing it with suspicious values. */
610 memset (&evrregs
, 42, sizeof (evrregs
));
612 /* We can only read and write the entire EVR register set at a
613 time, so to write just a single register, we do a
614 read-modify-write maneuver. */
615 get_spe_registers (tid
, &evrregs
);
621 for (i
= 0; i
< ppc_num_gprs
; i
++)
622 regcache_raw_collect (regcache
,
623 tdep
->ppc_ev0_upper_regnum
+ i
,
626 else if (tdep
->ppc_ev0_upper_regnum
<= regno
627 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
628 regcache_raw_collect (regcache
, regno
,
629 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
632 || regno
== tdep
->ppc_acc_regnum
)
633 regcache_raw_collect (regcache
,
634 tdep
->ppc_acc_regnum
,
638 || regno
== tdep
->ppc_spefscr_regnum
)
639 regcache_raw_collect (regcache
,
640 tdep
->ppc_spefscr_regnum
,
643 /* Write back the modified register set. */
644 set_spe_registers (tid
, &evrregs
);
648 store_register (const struct regcache
*regcache
, int tid
, int regno
)
650 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
651 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
652 /* This isn't really an address. But ptrace thinks of it as one. */
653 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
655 size_t bytes_to_transfer
;
656 char buf
[MAX_REGISTER_SIZE
];
658 if (altivec_register_p (gdbarch
, regno
))
660 store_altivec_register (regcache
, tid
, regno
);
663 else if (spe_register_p (gdbarch
, regno
))
665 store_spe_register (regcache
, tid
, regno
);
672 /* First collect the register. Keep in mind that the regcache's
673 idea of the register's size may not be a multiple of sizeof
675 memset (buf
, 0, sizeof buf
);
676 bytes_to_transfer
= align_up (register_size (gdbarch
, regno
), sizeof (long));
677 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
679 /* Little-endian values always sit at the left end of the buffer. */
680 regcache_raw_collect (regcache
, regno
, buf
);
682 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
684 /* Big-endian values sit at the right end of the buffer. */
685 size_t padding
= (bytes_to_transfer
- register_size (gdbarch
, regno
));
686 regcache_raw_collect (regcache
, regno
, buf
+ padding
);
689 for (i
= 0; i
< bytes_to_transfer
; i
+= sizeof (long))
692 ptrace (PTRACE_POKEUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
,
694 regaddr
+= sizeof (long);
697 && (regno
== tdep
->ppc_fpscr_regnum
698 || regno
== PPC_ORIG_R3_REGNUM
699 || regno
== PPC_TRAP_REGNUM
))
701 /* Some older kernel versions don't allow fpscr, orig_r3
702 or trap to be written. */
709 sprintf (message
, "writing register %s (#%d)",
710 gdbarch_register_name (gdbarch
, regno
), regno
);
711 perror_with_name (message
);
717 fill_vrregset (const struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
720 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
721 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
722 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
723 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
724 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
726 for (i
= 0; i
< num_of_vrregs
; i
++)
728 /* The last 2 registers of this set are only 32 bit long, not
729 128, but only VSCR is fetched as a 16 bytes quantity. */
730 if (i
== (num_of_vrregs
- 2))
731 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
732 *vrregsetp
+ i
* vrregsize
+ offset
);
734 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
735 *vrregsetp
+ i
* vrregsize
);
740 store_altivec_registers (const struct regcache
*regcache
, int tid
)
745 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
750 have_ptrace_getvrregs
= 0;
753 perror_with_name (_("Couldn't get AltiVec registers"));
756 fill_vrregset (regcache
, ®s
);
758 if (ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
) < 0)
759 perror_with_name (_("Couldn't write AltiVec registers"));
763 store_ppc_registers (const struct regcache
*regcache
, int tid
)
766 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
767 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
769 for (i
= 0; i
< ppc_num_gprs
; i
++)
770 store_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
771 if (tdep
->ppc_fp0_regnum
>= 0)
772 for (i
= 0; i
< ppc_num_fprs
; i
++)
773 store_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
774 store_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
775 if (tdep
->ppc_ps_regnum
!= -1)
776 store_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
777 if (tdep
->ppc_cr_regnum
!= -1)
778 store_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
779 if (tdep
->ppc_lr_regnum
!= -1)
780 store_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
781 if (tdep
->ppc_ctr_regnum
!= -1)
782 store_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
783 if (tdep
->ppc_xer_regnum
!= -1)
784 store_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
785 if (tdep
->ppc_mq_regnum
!= -1)
786 store_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
787 if (tdep
->ppc_fpscr_regnum
!= -1)
788 store_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
789 if (ppc_linux_trap_reg_p (gdbarch
))
791 store_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
792 store_register (regcache
, tid
, PPC_TRAP_REGNUM
);
794 if (have_ptrace_getvrregs
)
795 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
796 store_altivec_registers (regcache
, tid
);
797 if (tdep
->ppc_ev0_upper_regnum
>= 0)
798 store_spe_register (regcache
, tid
, -1);
802 ppc_linux_check_watch_resources (int type
, int cnt
, int ot
)
805 ptid_t ptid
= inferior_ptid
;
807 /* DABR (data address breakpoint register) is optional for PPC variants.
808 Some variants have one DABR, others have none. So CNT can't be larger
813 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether
814 the target has DABR. If either answer is no, the ptrace call will
815 return -1. Fail in that case. */
820 if (ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, 0) == -1)
826 ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
828 /* Handle sub-8-byte quantities. */
832 /* addr+len must fall in the 8 byte watchable region. */
833 if ((addr
+ len
) > (addr
& ~7) + 8)
839 /* The cached DABR value, to install in new threads. */
840 static long saved_dabr_value
;
842 /* Set a watchpoint of type TYPE at address ADDR. */
844 ppc_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int rw
)
850 dabr_value
= addr
& ~7;
854 /* Set read and translate bits. */
858 /* Set write and translate bits. */
862 /* Set read, write and translate bits. */
867 saved_dabr_value
= dabr_value
;
870 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (ptid
), 0, saved_dabr_value
) < 0)
877 ppc_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int rw
)
883 saved_dabr_value
= 0;
885 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (ptid
), 0, saved_dabr_value
) < 0)
891 ppc_linux_new_thread (ptid_t ptid
)
893 ptrace (PTRACE_SET_DEBUGREG
, TIDGET (ptid
), 0, saved_dabr_value
);
897 ppc_linux_stopped_data_address (struct target_ops
*target
, CORE_ADDR
*addr_p
)
899 struct siginfo
*siginfo_p
;
901 siginfo_p
= linux_nat_get_siginfo (inferior_ptid
);
903 if (siginfo_p
->si_signo
!= SIGTRAP
904 || (siginfo_p
->si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
907 *addr_p
= (CORE_ADDR
) (uintptr_t) siginfo_p
->si_addr
;
912 ppc_linux_stopped_by_watchpoint (void)
915 return ppc_linux_stopped_data_address (¤t_target
, &addr
);
919 ppc_linux_watchpoint_addr_within_range (struct target_ops
*target
,
921 CORE_ADDR start
, int length
)
924 /* Check whether [start, start+length-1] intersects [addr, addr+7]. */
925 return start
<= addr
+ 7 && start
+ length
- 1 >= addr
;
929 ppc_linux_store_inferior_registers (struct regcache
*regcache
, int regno
)
931 /* Overload thread id onto process id */
932 int tid
= TIDGET (inferior_ptid
);
934 /* No thread id, just use process id */
936 tid
= PIDGET (inferior_ptid
);
939 store_register (regcache
, tid
, regno
);
941 store_ppc_registers (regcache
, tid
);
944 /* Functions for transferring registers between a gregset_t or fpregset_t
945 (see sys/ucontext.h) and gdb's regcache. The word size is that used
946 by the ptrace interface, not the current program's ABI. eg. If a
947 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
948 read or write 64-bit gregsets. This is to suit the host libthread_db. */
951 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
953 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
955 ppc_supply_gregset (regset
, regcache
, -1, gregsetp
, sizeof (*gregsetp
));
959 fill_gregset (const struct regcache
*regcache
,
960 gdb_gregset_t
*gregsetp
, int regno
)
962 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
965 memset (gregsetp
, 0, sizeof (*gregsetp
));
966 ppc_collect_gregset (regset
, regcache
, regno
, gregsetp
, sizeof (*gregsetp
));
970 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
* fpregsetp
)
972 const struct regset
*regset
= ppc_linux_fpregset ();
974 ppc_supply_fpregset (regset
, regcache
, -1,
975 fpregsetp
, sizeof (*fpregsetp
));
979 fill_fpregset (const struct regcache
*regcache
,
980 gdb_fpregset_t
*fpregsetp
, int regno
)
982 const struct regset
*regset
= ppc_linux_fpregset ();
984 ppc_collect_fpregset (regset
, regcache
, regno
,
985 fpregsetp
, sizeof (*fpregsetp
));
988 static const struct target_desc
*
989 ppc_linux_read_description (struct target_ops
*ops
)
993 int tid
= TIDGET (inferior_ptid
);
995 tid
= PIDGET (inferior_ptid
);
997 if (have_ptrace_getsetevrregs
)
999 struct gdb_evrregset_t evrregset
;
1001 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, &evrregset
) >= 0)
1002 return tdesc_powerpc_e500l
;
1004 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
1005 Anything else needs to be reported. */
1006 else if (errno
!= EIO
)
1007 perror_with_name (_("Unable to fetch SPE registers"));
1010 if (have_ptrace_getvrregs
)
1012 gdb_vrregset_t vrregset
;
1014 if (ptrace (PTRACE_GETVRREGS
, tid
, 0, &vrregset
) >= 0)
1017 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
1018 Anything else needs to be reported. */
1019 else if (errno
!= EIO
)
1020 perror_with_name (_("Unable to fetch AltiVec registers"));
1023 /* Check for 64-bit inferior process. This is the case when the host is
1024 64-bit, and in addition the top bit of the MSR register is set. */
1025 #ifdef __powerpc64__
1029 msr
= (long) ptrace (PTRACE_PEEKUSER
, tid
, PT_MSR
* 8, 0);
1030 if (errno
== 0 && msr
< 0)
1031 return altivec
? tdesc_powerpc_altivec64l
: tdesc_powerpc_64l
;
1035 return altivec
? tdesc_powerpc_altivec32l
: tdesc_powerpc_32l
;
1038 void _initialize_ppc_linux_nat (void);
1041 _initialize_ppc_linux_nat (void)
1043 struct target_ops
*t
;
1045 /* Fill in the generic GNU/Linux methods. */
1046 t
= linux_target ();
1048 /* Add our register access methods. */
1049 t
->to_fetch_registers
= ppc_linux_fetch_inferior_registers
;
1050 t
->to_store_registers
= ppc_linux_store_inferior_registers
;
1052 /* Add our watchpoint methods. */
1053 t
->to_can_use_hw_breakpoint
= ppc_linux_check_watch_resources
;
1054 t
->to_region_ok_for_hw_watchpoint
= ppc_linux_region_ok_for_hw_watchpoint
;
1055 t
->to_insert_watchpoint
= ppc_linux_insert_watchpoint
;
1056 t
->to_remove_watchpoint
= ppc_linux_remove_watchpoint
;
1057 t
->to_stopped_by_watchpoint
= ppc_linux_stopped_by_watchpoint
;
1058 t
->to_stopped_data_address
= ppc_linux_stopped_data_address
;
1059 t
->to_watchpoint_addr_within_range
= ppc_linux_watchpoint_addr_within_range
;
1061 t
->to_read_description
= ppc_linux_read_description
;
1063 /* Register the target. */
1064 linux_nat_add_target (t
);
1065 linux_nat_set_new_thread (t
, ppc_linux_new_thread
);