1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "gdb_string.h"
25 #include "gdbthread.h"
28 #include "gdb_assert.h"
30 #include "linux-nat.h"
33 #include <sys/types.h>
34 #include <sys/param.h>
37 #include <sys/ioctl.h>
40 #include <sys/procfs.h>
41 #include <sys/ptrace.h>
43 /* Prototypes for supply_gregset etc. */
46 #include "ppc-linux-tdep.h"
48 /* Required when using the AUXV. */
49 #include "elf/common.h"
52 /* This sometimes isn't defined. */
60 /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
61 If they aren't, we can provide them ourselves (their values are fixed
62 because they are part of the kernel ABI). They are used in the AT_HWCAP
64 #ifndef PPC_FEATURE_CELL
65 #define PPC_FEATURE_CELL 0x00010000
67 #ifndef PPC_FEATURE_BOOKE
68 #define PPC_FEATURE_BOOKE 0x00008000
70 #ifndef PPC_FEATURE_HAS_DFP
71 #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
74 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
75 configure time check. Some older glibc's (for instance 2.2.1)
76 don't have a specific powerpc version of ptrace.h, and fall back on
77 a generic one. In such cases, sys/ptrace.h defines
78 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
79 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
80 PTRACE_SETVRREGS to be. This also makes a configury check pretty
83 /* These definitions should really come from the glibc header files,
84 but Glibc doesn't know about the vrregs yet. */
85 #ifndef PTRACE_GETVRREGS
86 #define PTRACE_GETVRREGS 18
87 #define PTRACE_SETVRREGS 19
90 /* PTRACE requests for POWER7 VSX registers. */
91 #ifndef PTRACE_GETVSXREGS
92 #define PTRACE_GETVSXREGS 27
93 #define PTRACE_SETVSXREGS 28
96 /* Similarly for the ptrace requests for getting / setting the SPE
97 registers (ev0 -- ev31, acc, and spefscr). See the description of
98 gdb_evrregset_t for details. */
99 #ifndef PTRACE_GETEVRREGS
100 #define PTRACE_GETEVRREGS 20
101 #define PTRACE_SETEVRREGS 21
104 /* Similarly for the hardware watchpoint support. These requests are used
105 when the BookE kernel interface is not available. */
106 #ifndef PTRACE_GET_DEBUGREG
107 #define PTRACE_GET_DEBUGREG 25
109 #ifndef PTRACE_SET_DEBUGREG
110 #define PTRACE_SET_DEBUGREG 26
112 #ifndef PTRACE_GETSIGINFO
113 #define PTRACE_GETSIGINFO 0x4202
116 /* These requests are used when the BookE kernel interface is available.
117 It exposes the additional debug features of BookE processors, such as
118 ranged breakpoints and watchpoints and hardware-accelerated condition
120 #ifndef PPC_PTRACE_GETHWDBGINFO
122 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the new BookE
123 interface is not present in ptrace.h, so we'll have to pretty much include
124 it all here so that the code at least compiles on older systems. */
125 #define PPC_PTRACE_GETHWDBGINFO 0x89
126 #define PPC_PTRACE_SETHWDEBUG 0x88
127 #define PPC_PTRACE_DELHWDEBUG 0x87
129 struct ppc_debug_info
131 uint32_t version
; /* Only version 1 exists to date. */
132 uint32_t num_instruction_bps
;
133 uint32_t num_data_bps
;
134 uint32_t num_condition_regs
;
135 uint32_t data_bp_alignment
;
136 uint32_t sizeof_condition
; /* size of the DVC register. */
140 /* Features will have bits indicating whether there is support for: */
141 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
142 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
143 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
144 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
146 struct ppc_hw_breakpoint
148 uint32_t version
; /* currently, version must be 1 */
149 uint32_t trigger_type
; /* only some combinations allowed */
150 uint32_t addr_mode
; /* address match mode */
151 uint32_t condition_mode
; /* break/watchpoint condition flags */
152 uint64_t addr
; /* break/watchpoint address */
153 uint64_t addr2
; /* range end or mask */
154 uint64_t condition_value
; /* contents of the DVC register */
158 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
159 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
160 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
161 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
164 #define PPC_BREAKPOINT_MODE_EXACT 0x0
165 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
166 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
167 #define PPC_BREAKPOINT_MODE_MASK 0x3
169 /* Condition mode. */
170 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
171 #define PPC_BREAKPOINT_CONDITION_AND 0x1
172 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
173 #define PPC_BREAKPOINT_CONDITION_OR 0x2
174 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
175 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
176 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
177 #define PPC_BREAKPOINT_CONDITION_BE(n) \
178 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
179 #endif /* PPC_PTRACE_GETHWDBGINFO */
183 /* Similarly for the general-purpose (gp0 -- gp31)
184 and floating-point registers (fp0 -- fp31). */
185 #ifndef PTRACE_GETREGS
186 #define PTRACE_GETREGS 12
188 #ifndef PTRACE_SETREGS
189 #define PTRACE_SETREGS 13
191 #ifndef PTRACE_GETFPREGS
192 #define PTRACE_GETFPREGS 14
194 #ifndef PTRACE_SETFPREGS
195 #define PTRACE_SETFPREGS 15
198 /* This oddity is because the Linux kernel defines elf_vrregset_t as
199 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
200 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
201 the vrsave as an extra 4 bytes at the end. I opted for creating a
202 flat array of chars, so that it is easier to manipulate for gdb.
204 There are 32 vector registers 16 bytes longs, plus a VSCR register
205 which is only 4 bytes long, but is fetched as a 16 bytes
206 quantity. Up to here we have the elf_vrregset_t structure.
207 Appended to this there is space for the VRSAVE register: 4 bytes.
208 Even though this vrsave register is not included in the regset
209 typedef, it is handled by the ptrace requests.
211 Note that GNU/Linux doesn't support little endian PPC hardware,
212 therefore the offset at which the real value of the VSCR register
213 is located will be always 12 bytes.
215 The layout is like this (where x is the actual value of the vscr reg): */
219 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
220 <-------> <-------><-------><->
225 #define SIZEOF_VRREGS 33*16+4
227 typedef char gdb_vrregset_t
[SIZEOF_VRREGS
];
229 /* This is the layout of the POWER7 VSX registers and the way they overlap
230 with the existing FPR and VMX registers.
232 VSR doubleword 0 VSR doubleword 1
233 ----------------------------------------------------------------
235 ----------------------------------------------------------------
237 ----------------------------------------------------------------
240 ----------------------------------------------------------------
241 VSR[30] | FPR[30] | |
242 ----------------------------------------------------------------
243 VSR[31] | FPR[31] | |
244 ----------------------------------------------------------------
246 ----------------------------------------------------------------
248 ----------------------------------------------------------------
251 ----------------------------------------------------------------
253 ----------------------------------------------------------------
255 ----------------------------------------------------------------
257 VSX has 64 128bit registers. The first 32 registers overlap with
258 the FP registers (doubleword 0) and hence extend them with additional
259 64 bits (doubleword 1). The other 32 regs overlap with the VMX
261 #define SIZEOF_VSXREGS 32*8
263 typedef char gdb_vsxregset_t
[SIZEOF_VSXREGS
];
265 /* On PPC processors that support the Signal Processing Extension
266 (SPE) APU, the general-purpose registers are 64 bits long.
267 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
268 ptrace calls only access the lower half of each register, to allow
269 them to behave the same way they do on non-SPE systems. There's a
270 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
271 read and write the top halves of all the general-purpose registers
272 at once, along with some SPE-specific registers.
274 GDB itself continues to claim the general-purpose registers are 32
275 bits long. It has unnamed raw registers that hold the upper halves
276 of the gprs, and the full 64-bit SIMD views of the registers,
277 'ev0' -- 'ev31', are pseudo-registers that splice the top and
278 bottom halves together.
280 This is the structure filled in by PTRACE_GETEVRREGS and written to
281 the inferior's registers by PTRACE_SETEVRREGS. */
282 struct gdb_evrregset_t
284 unsigned long evr
[32];
285 unsigned long long acc
;
286 unsigned long spefscr
;
289 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
290 PTRACE_SETVSXREGS requests, for reading and writing the VSX
291 POWER7 registers 0 through 31. Zero if we've tried one of them and
292 gotten an error. Note that VSX registers 32 through 63 overlap
293 with VR registers 0 through 31. */
294 int have_ptrace_getsetvsxregs
= 1;
296 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
297 PTRACE_SETVRREGS requests, for reading and writing the Altivec
298 registers. Zero if we've tried one of them and gotten an
300 int have_ptrace_getvrregs
= 1;
302 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
303 PTRACE_SETEVRREGS requests, for reading and writing the SPE
304 registers. Zero if we've tried one of them and gotten an
306 int have_ptrace_getsetevrregs
= 1;
308 /* Non-zero if our kernel may support the PTRACE_GETREGS and
309 PTRACE_SETREGS requests, for reading and writing the
310 general-purpose registers. Zero if we've tried one of
311 them and gotten an error. */
312 int have_ptrace_getsetregs
= 1;
314 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
315 PTRACE_SETFPREGS requests, for reading and writing the
316 floating-pointers registers. Zero if we've tried one of
317 them and gotten an error. */
318 int have_ptrace_getsetfpregs
= 1;
321 /* registers layout, as presented by the ptrace interface:
322 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
323 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
324 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
325 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
326 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
327 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
328 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
329 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
330 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
331 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
332 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
333 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
334 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
338 ppc_register_u_addr (struct gdbarch
*gdbarch
, int regno
)
341 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
342 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
343 interface, and not the wordsize of the program's ABI. */
344 int wordsize
= sizeof (long);
346 /* General purpose registers occupy 1 slot each in the buffer. */
347 if (regno
>= tdep
->ppc_gp0_regnum
348 && regno
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
349 u_addr
= ((regno
- tdep
->ppc_gp0_regnum
+ PT_R0
) * wordsize
);
351 /* Floating point regs: eight bytes each in both 32- and 64-bit
352 ptrace interfaces. Thus, two slots each in 32-bit interface, one
353 slot each in 64-bit interface. */
354 if (tdep
->ppc_fp0_regnum
>= 0
355 && regno
>= tdep
->ppc_fp0_regnum
356 && regno
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
357 u_addr
= (PT_FPR0
* wordsize
) + ((regno
- tdep
->ppc_fp0_regnum
) * 8);
359 /* UISA special purpose registers: 1 slot each. */
360 if (regno
== gdbarch_pc_regnum (gdbarch
))
361 u_addr
= PT_NIP
* wordsize
;
362 if (regno
== tdep
->ppc_lr_regnum
)
363 u_addr
= PT_LNK
* wordsize
;
364 if (regno
== tdep
->ppc_cr_regnum
)
365 u_addr
= PT_CCR
* wordsize
;
366 if (regno
== tdep
->ppc_xer_regnum
)
367 u_addr
= PT_XER
* wordsize
;
368 if (regno
== tdep
->ppc_ctr_regnum
)
369 u_addr
= PT_CTR
* wordsize
;
371 if (regno
== tdep
->ppc_mq_regnum
)
372 u_addr
= PT_MQ
* wordsize
;
374 if (regno
== tdep
->ppc_ps_regnum
)
375 u_addr
= PT_MSR
* wordsize
;
376 if (regno
== PPC_ORIG_R3_REGNUM
)
377 u_addr
= PT_ORIG_R3
* wordsize
;
378 if (regno
== PPC_TRAP_REGNUM
)
379 u_addr
= PT_TRAP
* wordsize
;
380 if (tdep
->ppc_fpscr_regnum
>= 0
381 && regno
== tdep
->ppc_fpscr_regnum
)
383 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
384 kernel headers incorrectly contained the 32-bit definition of
385 PT_FPSCR. For the 32-bit definition, floating-point
386 registers occupy two 32-bit "slots", and the FPSCR lives in
387 the second half of such a slot-pair (hence +1). For 64-bit,
388 the FPSCR instead occupies the full 64-bit 2-word-slot and
389 hence no adjustment is necessary. Hack around this. */
390 if (wordsize
== 8 && PT_FPSCR
== (48 + 32 + 1))
391 u_addr
= (48 + 32) * wordsize
;
392 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
393 slot and not just its second word. The PT_FPSCR supplied when
394 GDB is compiled as a 32-bit app doesn't reflect this. */
395 else if (wordsize
== 4 && register_size (gdbarch
, regno
) == 8
396 && PT_FPSCR
== (48 + 2*32 + 1))
397 u_addr
= (48 + 2*32) * wordsize
;
399 u_addr
= PT_FPSCR
* wordsize
;
404 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
405 registers set mechanism, as opposed to the interface for all the
406 other registers, that stores/fetches each register individually. */
408 fetch_vsx_register (struct regcache
*regcache
, int tid
, int regno
)
411 gdb_vsxregset_t regs
;
412 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
413 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
414 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
416 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
421 have_ptrace_getsetvsxregs
= 0;
424 perror_with_name (_("Unable to fetch VSX register"));
427 regcache_raw_supply (regcache
, regno
,
428 regs
+ (regno
- tdep
->ppc_vsr0_upper_regnum
)
432 /* The Linux kernel ptrace interface for AltiVec registers uses the
433 registers set mechanism, as opposed to the interface for all the
434 other registers, that stores/fetches each register individually. */
436 fetch_altivec_register (struct regcache
*regcache
, int tid
, int regno
)
441 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
442 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
443 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
445 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
450 have_ptrace_getvrregs
= 0;
453 perror_with_name (_("Unable to fetch AltiVec register"));
456 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
457 long on the hardware. We deal only with the lower 4 bytes of the
458 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
459 there is no need to define an offset for it. */
460 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
461 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
463 regcache_raw_supply (regcache
, regno
,
465 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
468 /* Fetch the top 32 bits of TID's general-purpose registers and the
469 SPE-specific registers, and place the results in EVRREGSET. If we
470 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
473 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
474 PTRACE_SETEVRREGS requests are supported is isolated here, and in
475 set_spe_registers. */
477 get_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
479 if (have_ptrace_getsetevrregs
)
481 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, evrregset
) >= 0)
485 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
486 we just return zeros. */
488 have_ptrace_getsetevrregs
= 0;
490 /* Anything else needs to be reported. */
491 perror_with_name (_("Unable to fetch SPE registers"));
495 memset (evrregset
, 0, sizeof (*evrregset
));
498 /* Supply values from TID for SPE-specific raw registers: the upper
499 halves of the GPRs, the accumulator, and the spefscr. REGNO must
500 be the number of an upper half register, acc, spefscr, or -1 to
501 supply the values of all registers. */
503 fetch_spe_register (struct regcache
*regcache
, int tid
, int regno
)
505 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
506 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
507 struct gdb_evrregset_t evrregs
;
509 gdb_assert (sizeof (evrregs
.evr
[0])
510 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
511 gdb_assert (sizeof (evrregs
.acc
)
512 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
513 gdb_assert (sizeof (evrregs
.spefscr
)
514 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
516 get_spe_registers (tid
, &evrregs
);
522 for (i
= 0; i
< ppc_num_gprs
; i
++)
523 regcache_raw_supply (regcache
, tdep
->ppc_ev0_upper_regnum
+ i
,
526 else if (tdep
->ppc_ev0_upper_regnum
<= regno
527 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
528 regcache_raw_supply (regcache
, regno
,
529 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
532 || regno
== tdep
->ppc_acc_regnum
)
533 regcache_raw_supply (regcache
, tdep
->ppc_acc_regnum
, &evrregs
.acc
);
536 || regno
== tdep
->ppc_spefscr_regnum
)
537 regcache_raw_supply (regcache
, tdep
->ppc_spefscr_regnum
,
542 fetch_register (struct regcache
*regcache
, int tid
, int regno
)
544 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
545 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
546 /* This isn't really an address. But ptrace thinks of it as one. */
547 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
548 int bytes_transferred
;
549 unsigned int offset
; /* Offset of registers within the u area. */
550 gdb_byte buf
[MAX_REGISTER_SIZE
];
552 if (altivec_register_p (gdbarch
, regno
))
554 /* If this is the first time through, or if it is not the first
555 time through, and we have comfirmed that there is kernel
556 support for such a ptrace request, then go and fetch the
558 if (have_ptrace_getvrregs
)
560 fetch_altivec_register (regcache
, tid
, regno
);
563 /* If we have discovered that there is no ptrace support for
564 AltiVec registers, fall through and return zeroes, because
565 regaddr will be -1 in this case. */
567 if (vsx_register_p (gdbarch
, regno
))
569 if (have_ptrace_getsetvsxregs
)
571 fetch_vsx_register (regcache
, tid
, regno
);
575 else if (spe_register_p (gdbarch
, regno
))
577 fetch_spe_register (regcache
, tid
, regno
);
583 memset (buf
, '\0', register_size (gdbarch
, regno
)); /* Supply zeroes */
584 regcache_raw_supply (regcache
, regno
, buf
);
588 /* Read the raw register using sizeof(long) sized chunks. On a
589 32-bit platform, 64-bit floating-point registers will require two
591 for (bytes_transferred
= 0;
592 bytes_transferred
< register_size (gdbarch
, regno
);
593 bytes_transferred
+= sizeof (long))
598 l
= ptrace (PTRACE_PEEKUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, 0);
599 regaddr
+= sizeof (long);
603 xsnprintf (message
, sizeof (message
), "reading register %s (#%d)",
604 gdbarch_register_name (gdbarch
, regno
), regno
);
605 perror_with_name (message
);
607 memcpy (&buf
[bytes_transferred
], &l
, sizeof (l
));
610 /* Now supply the register. Keep in mind that the regcache's idea
611 of the register's size may not be a multiple of sizeof
613 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
615 /* Little-endian values are always found at the left end of the
616 bytes transferred. */
617 regcache_raw_supply (regcache
, regno
, buf
);
619 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
621 /* Big-endian values are found at the right end of the bytes
623 size_t padding
= (bytes_transferred
- register_size (gdbarch
, regno
));
624 regcache_raw_supply (regcache
, regno
, buf
+ padding
);
627 internal_error (__FILE__
, __LINE__
,
628 _("fetch_register: unexpected byte order: %d"),
629 gdbarch_byte_order (gdbarch
));
633 supply_vsxregset (struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
636 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
637 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
638 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
640 for (i
= 0; i
< ppc_num_vshrs
; i
++)
642 regcache_raw_supply (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
643 *vsxregsetp
+ i
* vsxregsize
);
648 supply_vrregset (struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
651 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
652 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
653 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
654 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
655 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
657 for (i
= 0; i
< num_of_vrregs
; i
++)
659 /* The last 2 registers of this set are only 32 bit long, not
660 128. However an offset is necessary only for VSCR because it
661 occupies a whole vector, while VRSAVE occupies a full 4 bytes
663 if (i
== (num_of_vrregs
- 2))
664 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
665 *vrregsetp
+ i
* vrregsize
+ offset
);
667 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
668 *vrregsetp
+ i
* vrregsize
);
673 fetch_vsx_registers (struct regcache
*regcache
, int tid
)
676 gdb_vsxregset_t regs
;
678 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
683 have_ptrace_getsetvsxregs
= 0;
686 perror_with_name (_("Unable to fetch VSX registers"));
688 supply_vsxregset (regcache
, ®s
);
692 fetch_altivec_registers (struct regcache
*regcache
, int tid
)
697 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
702 have_ptrace_getvrregs
= 0;
705 perror_with_name (_("Unable to fetch AltiVec registers"));
707 supply_vrregset (regcache
, ®s
);
710 /* This function actually issues the request to ptrace, telling
711 it to get all general-purpose registers and put them into the
714 If the ptrace request does not exist, this function returns 0
715 and properly sets the have_ptrace_* flag. If the request fails,
716 this function calls perror_with_name. Otherwise, if the request
717 succeeds, then the regcache gets filled and 1 is returned. */
719 fetch_all_gp_regs (struct regcache
*regcache
, int tid
)
721 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
722 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
723 gdb_gregset_t gregset
;
725 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
729 have_ptrace_getsetregs
= 0;
732 perror_with_name (_("Couldn't get general-purpose registers."));
735 supply_gregset (regcache
, (const gdb_gregset_t
*) &gregset
);
740 /* This is a wrapper for the fetch_all_gp_regs function. It is
741 responsible for verifying if this target has the ptrace request
742 that can be used to fetch all general-purpose registers at one
743 shot. If it doesn't, then we should fetch them using the
744 old-fashioned way, which is to iterate over the registers and
745 request them one by one. */
747 fetch_gp_regs (struct regcache
*regcache
, int tid
)
749 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
750 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
753 if (have_ptrace_getsetregs
)
754 if (fetch_all_gp_regs (regcache
, tid
))
757 /* If we've hit this point, it doesn't really matter which
758 architecture we are using. We just need to read the
759 registers in the "old-fashioned way". */
760 for (i
= 0; i
< ppc_num_gprs
; i
++)
761 fetch_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
764 /* This function actually issues the request to ptrace, telling
765 it to get all floating-point registers and put them into the
768 If the ptrace request does not exist, this function returns 0
769 and properly sets the have_ptrace_* flag. If the request fails,
770 this function calls perror_with_name. Otherwise, if the request
771 succeeds, then the regcache gets filled and 1 is returned. */
773 fetch_all_fp_regs (struct regcache
*regcache
, int tid
)
775 gdb_fpregset_t fpregs
;
777 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
781 have_ptrace_getsetfpregs
= 0;
784 perror_with_name (_("Couldn't get floating-point registers."));
787 supply_fpregset (regcache
, (const gdb_fpregset_t
*) &fpregs
);
792 /* This is a wrapper for the fetch_all_fp_regs function. It is
793 responsible for verifying if this target has the ptrace request
794 that can be used to fetch all floating-point registers at one
795 shot. If it doesn't, then we should fetch them using the
796 old-fashioned way, which is to iterate over the registers and
797 request them one by one. */
799 fetch_fp_regs (struct regcache
*regcache
, int tid
)
801 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
802 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
805 if (have_ptrace_getsetfpregs
)
806 if (fetch_all_fp_regs (regcache
, tid
))
809 /* If we've hit this point, it doesn't really matter which
810 architecture we are using. We just need to read the
811 registers in the "old-fashioned way". */
812 for (i
= 0; i
< ppc_num_fprs
; i
++)
813 fetch_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
817 fetch_ppc_registers (struct regcache
*regcache
, int tid
)
820 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
823 fetch_gp_regs (regcache
, tid
);
824 if (tdep
->ppc_fp0_regnum
>= 0)
825 fetch_fp_regs (regcache
, tid
);
826 fetch_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
827 if (tdep
->ppc_ps_regnum
!= -1)
828 fetch_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
829 if (tdep
->ppc_cr_regnum
!= -1)
830 fetch_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
831 if (tdep
->ppc_lr_regnum
!= -1)
832 fetch_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
833 if (tdep
->ppc_ctr_regnum
!= -1)
834 fetch_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
835 if (tdep
->ppc_xer_regnum
!= -1)
836 fetch_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
837 if (tdep
->ppc_mq_regnum
!= -1)
838 fetch_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
839 if (ppc_linux_trap_reg_p (gdbarch
))
841 fetch_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
842 fetch_register (regcache
, tid
, PPC_TRAP_REGNUM
);
844 if (tdep
->ppc_fpscr_regnum
!= -1)
845 fetch_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
846 if (have_ptrace_getvrregs
)
847 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
848 fetch_altivec_registers (regcache
, tid
);
849 if (have_ptrace_getsetvsxregs
)
850 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
851 fetch_vsx_registers (regcache
, tid
);
852 if (tdep
->ppc_ev0_upper_regnum
>= 0)
853 fetch_spe_register (regcache
, tid
, -1);
856 /* Fetch registers from the child process. Fetch all registers if
857 regno == -1, otherwise fetch all general registers or all floating
858 point registers depending upon the value of regno. */
860 ppc_linux_fetch_inferior_registers (struct target_ops
*ops
,
861 struct regcache
*regcache
, int regno
)
863 /* Overload thread id onto process id. */
864 int tid
= TIDGET (inferior_ptid
);
866 /* No thread id, just use process id. */
868 tid
= PIDGET (inferior_ptid
);
871 fetch_ppc_registers (regcache
, tid
);
873 fetch_register (regcache
, tid
, regno
);
876 /* Store one VSX register. */
878 store_vsx_register (const struct regcache
*regcache
, int tid
, int regno
)
881 gdb_vsxregset_t regs
;
882 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
883 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
884 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
886 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
891 have_ptrace_getsetvsxregs
= 0;
894 perror_with_name (_("Unable to fetch VSX register"));
897 regcache_raw_collect (regcache
, regno
, regs
+
898 (regno
- tdep
->ppc_vsr0_upper_regnum
) * vsxregsize
);
900 ret
= ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
);
902 perror_with_name (_("Unable to store VSX register"));
905 /* Store one register. */
907 store_altivec_register (const struct regcache
*regcache
, int tid
, int regno
)
912 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
913 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
914 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
916 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
921 have_ptrace_getvrregs
= 0;
924 perror_with_name (_("Unable to fetch AltiVec register"));
927 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
928 long on the hardware. */
929 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
930 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
932 regcache_raw_collect (regcache
, regno
,
934 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
936 ret
= ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
);
938 perror_with_name (_("Unable to store AltiVec register"));
941 /* Assuming TID referrs to an SPE process, set the top halves of TID's
942 general-purpose registers and its SPE-specific registers to the
943 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
946 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
947 PTRACE_SETEVRREGS requests are supported is isolated here, and in
948 get_spe_registers. */
950 set_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
952 if (have_ptrace_getsetevrregs
)
954 if (ptrace (PTRACE_SETEVRREGS
, tid
, 0, evrregset
) >= 0)
958 /* EIO means that the PTRACE_SETEVRREGS request isn't
959 supported; we fail silently, and don't try the call
962 have_ptrace_getsetevrregs
= 0;
964 /* Anything else needs to be reported. */
965 perror_with_name (_("Unable to set SPE registers"));
970 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
971 If REGNO is -1, write the values of all the SPE-specific
974 store_spe_register (const struct regcache
*regcache
, int tid
, int regno
)
976 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
977 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
978 struct gdb_evrregset_t evrregs
;
980 gdb_assert (sizeof (evrregs
.evr
[0])
981 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
982 gdb_assert (sizeof (evrregs
.acc
)
983 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
984 gdb_assert (sizeof (evrregs
.spefscr
)
985 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
988 /* Since we're going to write out every register, the code below
989 should store to every field of evrregs; if that doesn't happen,
990 make it obvious by initializing it with suspicious values. */
991 memset (&evrregs
, 42, sizeof (evrregs
));
993 /* We can only read and write the entire EVR register set at a
994 time, so to write just a single register, we do a
995 read-modify-write maneuver. */
996 get_spe_registers (tid
, &evrregs
);
1002 for (i
= 0; i
< ppc_num_gprs
; i
++)
1003 regcache_raw_collect (regcache
,
1004 tdep
->ppc_ev0_upper_regnum
+ i
,
1007 else if (tdep
->ppc_ev0_upper_regnum
<= regno
1008 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1009 regcache_raw_collect (regcache
, regno
,
1010 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
1013 || regno
== tdep
->ppc_acc_regnum
)
1014 regcache_raw_collect (regcache
,
1015 tdep
->ppc_acc_regnum
,
1019 || regno
== tdep
->ppc_spefscr_regnum
)
1020 regcache_raw_collect (regcache
,
1021 tdep
->ppc_spefscr_regnum
,
1024 /* Write back the modified register set. */
1025 set_spe_registers (tid
, &evrregs
);
1029 store_register (const struct regcache
*regcache
, int tid
, int regno
)
1031 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1033 /* This isn't really an address. But ptrace thinks of it as one. */
1034 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
1036 size_t bytes_to_transfer
;
1037 gdb_byte buf
[MAX_REGISTER_SIZE
];
1039 if (altivec_register_p (gdbarch
, regno
))
1041 store_altivec_register (regcache
, tid
, regno
);
1044 if (vsx_register_p (gdbarch
, regno
))
1046 store_vsx_register (regcache
, tid
, regno
);
1049 else if (spe_register_p (gdbarch
, regno
))
1051 store_spe_register (regcache
, tid
, regno
);
1058 /* First collect the register. Keep in mind that the regcache's
1059 idea of the register's size may not be a multiple of sizeof
1061 memset (buf
, 0, sizeof buf
);
1062 bytes_to_transfer
= align_up (register_size (gdbarch
, regno
), sizeof (long));
1063 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1065 /* Little-endian values always sit at the left end of the buffer. */
1066 regcache_raw_collect (regcache
, regno
, buf
);
1068 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1070 /* Big-endian values sit at the right end of the buffer. */
1071 size_t padding
= (bytes_to_transfer
- register_size (gdbarch
, regno
));
1072 regcache_raw_collect (regcache
, regno
, buf
+ padding
);
1075 for (i
= 0; i
< bytes_to_transfer
; i
+= sizeof (long))
1079 memcpy (&l
, &buf
[i
], sizeof (l
));
1081 ptrace (PTRACE_POKEUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, l
);
1082 regaddr
+= sizeof (long);
1085 && (regno
== tdep
->ppc_fpscr_regnum
1086 || regno
== PPC_ORIG_R3_REGNUM
1087 || regno
== PPC_TRAP_REGNUM
))
1089 /* Some older kernel versions don't allow fpscr, orig_r3
1090 or trap to be written. */
1097 xsnprintf (message
, sizeof (message
), "writing register %s (#%d)",
1098 gdbarch_register_name (gdbarch
, regno
), regno
);
1099 perror_with_name (message
);
1105 fill_vsxregset (const struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
1108 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1109 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1110 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
1112 for (i
= 0; i
< ppc_num_vshrs
; i
++)
1113 regcache_raw_collect (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
1114 *vsxregsetp
+ i
* vsxregsize
);
1118 fill_vrregset (const struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
1121 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1122 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1123 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
1124 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
1125 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
1127 for (i
= 0; i
< num_of_vrregs
; i
++)
1129 /* The last 2 registers of this set are only 32 bit long, not
1130 128, but only VSCR is fetched as a 16 bytes quantity. */
1131 if (i
== (num_of_vrregs
- 2))
1132 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1133 *vrregsetp
+ i
* vrregsize
+ offset
);
1135 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1136 *vrregsetp
+ i
* vrregsize
);
1141 store_vsx_registers (const struct regcache
*regcache
, int tid
)
1144 gdb_vsxregset_t regs
;
1146 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
1151 have_ptrace_getsetvsxregs
= 0;
1154 perror_with_name (_("Couldn't get VSX registers"));
1157 fill_vsxregset (regcache
, ®s
);
1159 if (ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
) < 0)
1160 perror_with_name (_("Couldn't write VSX registers"));
1164 store_altivec_registers (const struct regcache
*regcache
, int tid
)
1167 gdb_vrregset_t regs
;
1169 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
1174 have_ptrace_getvrregs
= 0;
1177 perror_with_name (_("Couldn't get AltiVec registers"));
1180 fill_vrregset (regcache
, ®s
);
1182 if (ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
) < 0)
1183 perror_with_name (_("Couldn't write AltiVec registers"));
1186 /* This function actually issues the request to ptrace, telling
1187 it to store all general-purpose registers present in the specified
1190 If the ptrace request does not exist, this function returns 0
1191 and properly sets the have_ptrace_* flag. If the request fails,
1192 this function calls perror_with_name. Otherwise, if the request
1193 succeeds, then the regcache is stored and 1 is returned. */
1195 store_all_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1197 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1198 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1199 gdb_gregset_t gregset
;
1201 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
1205 have_ptrace_getsetregs
= 0;
1208 perror_with_name (_("Couldn't get general-purpose registers."));
1211 fill_gregset (regcache
, &gregset
, regno
);
1213 if (ptrace (PTRACE_SETREGS
, tid
, 0, (void *) &gregset
) < 0)
1217 have_ptrace_getsetregs
= 0;
1220 perror_with_name (_("Couldn't set general-purpose registers."));
1226 /* This is a wrapper for the store_all_gp_regs function. It is
1227 responsible for verifying if this target has the ptrace request
1228 that can be used to store all general-purpose registers at one
1229 shot. If it doesn't, then we should store them using the
1230 old-fashioned way, which is to iterate over the registers and
1231 store them one by one. */
1233 store_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1235 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1239 if (have_ptrace_getsetregs
)
1240 if (store_all_gp_regs (regcache
, tid
, regno
))
1243 /* If we hit this point, it doesn't really matter which
1244 architecture we are using. We just need to store the
1245 registers in the "old-fashioned way". */
1246 for (i
= 0; i
< ppc_num_gprs
; i
++)
1247 store_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
1250 /* This function actually issues the request to ptrace, telling
1251 it to store all floating-point registers present in the specified
1254 If the ptrace request does not exist, this function returns 0
1255 and properly sets the have_ptrace_* flag. If the request fails,
1256 this function calls perror_with_name. Otherwise, if the request
1257 succeeds, then the regcache is stored and 1 is returned. */
1259 store_all_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1261 gdb_fpregset_t fpregs
;
1263 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1267 have_ptrace_getsetfpregs
= 0;
1270 perror_with_name (_("Couldn't get floating-point registers."));
1273 fill_fpregset (regcache
, &fpregs
, regno
);
1275 if (ptrace (PTRACE_SETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1279 have_ptrace_getsetfpregs
= 0;
1282 perror_with_name (_("Couldn't set floating-point registers."));
1288 /* This is a wrapper for the store_all_fp_regs function. It is
1289 responsible for verifying if this target has the ptrace request
1290 that can be used to store all floating-point registers at one
1291 shot. If it doesn't, then we should store them using the
1292 old-fashioned way, which is to iterate over the registers and
1293 store them one by one. */
1295 store_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1297 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1298 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1301 if (have_ptrace_getsetfpregs
)
1302 if (store_all_fp_regs (regcache
, tid
, regno
))
1305 /* If we hit this point, it doesn't really matter which
1306 architecture we are using. We just need to store the
1307 registers in the "old-fashioned way". */
1308 for (i
= 0; i
< ppc_num_fprs
; i
++)
1309 store_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
1313 store_ppc_registers (const struct regcache
*regcache
, int tid
)
1316 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1317 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1319 store_gp_regs (regcache
, tid
, -1);
1320 if (tdep
->ppc_fp0_regnum
>= 0)
1321 store_fp_regs (regcache
, tid
, -1);
1322 store_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
1323 if (tdep
->ppc_ps_regnum
!= -1)
1324 store_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
1325 if (tdep
->ppc_cr_regnum
!= -1)
1326 store_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
1327 if (tdep
->ppc_lr_regnum
!= -1)
1328 store_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
1329 if (tdep
->ppc_ctr_regnum
!= -1)
1330 store_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
1331 if (tdep
->ppc_xer_regnum
!= -1)
1332 store_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
1333 if (tdep
->ppc_mq_regnum
!= -1)
1334 store_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
1335 if (tdep
->ppc_fpscr_regnum
!= -1)
1336 store_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
1337 if (ppc_linux_trap_reg_p (gdbarch
))
1339 store_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
1340 store_register (regcache
, tid
, PPC_TRAP_REGNUM
);
1342 if (have_ptrace_getvrregs
)
1343 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
1344 store_altivec_registers (regcache
, tid
);
1345 if (have_ptrace_getsetvsxregs
)
1346 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
1347 store_vsx_registers (regcache
, tid
);
1348 if (tdep
->ppc_ev0_upper_regnum
>= 0)
1349 store_spe_register (regcache
, tid
, -1);
1352 /* Fetch the AT_HWCAP entry from the aux vector. */
1353 static unsigned long
1354 ppc_linux_get_hwcap (void)
1358 if (target_auxv_search (¤t_target
, AT_HWCAP
, &field
))
1359 return (unsigned long) field
;
1364 /* The cached DABR value, to install in new threads.
1365 This variable is used when we are dealing with non-BookE
1367 static long saved_dabr_value
;
1369 /* Global structure that will store information about the available
1370 features on this BookE processor. */
1371 static struct ppc_debug_info booke_debug_info
;
1373 /* Global variable that holds the maximum number of slots that the
1374 kernel will use. This is only used when the processor is BookE. */
1375 static size_t max_slots_number
= 0;
1377 struct hw_break_tuple
1380 struct ppc_hw_breakpoint
*hw_break
;
1383 /* This is an internal VEC created to store information about *points inserted
1384 for each thread. This is used for BookE processors. */
1385 typedef struct thread_points
1387 /* The TID to which this *point relates. */
1389 /* Information about the *point, such as its address, type, etc.
1391 Each element inside this vector corresponds to a hardware
1392 breakpoint or watchpoint in the thread represented by TID. The maximum
1393 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1394 the tuple is NULL, then the position in the vector is free. */
1395 struct hw_break_tuple
*hw_breaks
;
1397 DEF_VEC_P (thread_points_p
);
1399 VEC(thread_points_p
) *ppc_threads
= NULL
;
1401 /* The version of the kernel interface that we will use if the processor is
1403 #define PPC_DEBUG_CURRENT_VERSION 1
1405 /* Returns non-zero if we support the ptrace interface which enables
1406 booke debugging resources. */
1408 have_ptrace_booke_interface (void)
1410 static int have_ptrace_booke_interface
= -1;
1412 if (have_ptrace_booke_interface
== -1)
1416 tid
= TIDGET (inferior_ptid
);
1418 tid
= PIDGET (inferior_ptid
);
1420 /* Check for kernel support for BOOKE debug registers. */
1421 if (ptrace (PPC_PTRACE_GETHWDBGINFO
, tid
, 0, &booke_debug_info
) >= 0)
1423 /* Check whether ptrace BOOKE interface is functional and
1424 provides any supported feature. */
1425 if (booke_debug_info
.features
!= 0)
1427 have_ptrace_booke_interface
= 1;
1428 max_slots_number
= booke_debug_info
.num_instruction_bps
1429 + booke_debug_info
.num_data_bps
1430 + booke_debug_info
.num_condition_regs
;
1431 return have_ptrace_booke_interface
;
1434 /* Old school interface and no BOOKE debug registers support. */
1435 have_ptrace_booke_interface
= 0;
1436 memset (&booke_debug_info
, 0, sizeof (struct ppc_debug_info
));
1439 return have_ptrace_booke_interface
;
1443 ppc_linux_can_use_hw_breakpoint (int type
, int cnt
, int ot
)
1445 int total_hw_wp
, total_hw_bp
;
1447 if (have_ptrace_booke_interface ())
1449 /* For PPC BookE processors, the number of available hardware
1450 watchpoints and breakpoints is stored at the booke_debug_info
1452 total_hw_bp
= booke_debug_info
.num_instruction_bps
;
1453 total_hw_wp
= booke_debug_info
.num_data_bps
;
1457 /* For PPC server processors, we accept 1 hardware watchpoint and 0
1458 hardware breakpoints. */
1463 if (type
== bp_hardware_watchpoint
|| type
== bp_read_watchpoint
1464 || type
== bp_access_watchpoint
|| type
== bp_watchpoint
)
1466 if (cnt
+ ot
> total_hw_wp
)
1469 else if (type
== bp_hardware_breakpoint
)
1471 if (cnt
> total_hw_bp
)
1475 if (!have_ptrace_booke_interface ())
1478 ptid_t ptid
= inferior_ptid
;
1480 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1481 and whether the target has DABR. If either answer is no, the
1482 ptrace call will return -1. Fail in that case. */
1483 tid
= TIDGET (ptid
);
1485 tid
= PIDGET (ptid
);
1487 if (ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, 0) == -1)
1495 ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
1497 /* Handle sub-8-byte quantities. */
1501 /* The new BookE ptrace interface tells if there are alignment restrictions
1502 for watchpoints in the processors. In that case, we use that information
1503 to determine the hardcoded watchable region for watchpoints. */
1504 if (have_ptrace_booke_interface ())
1506 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1507 watchpoints and can watch any access within an arbitrary memory
1508 region. This is useful to watch arrays and structs, for instance. It
1509 takes two hardware watchpoints though. */
1511 && booke_debug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
1512 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1514 /* Server processors provide one hardware watchpoint and addr+len should
1515 fall in the watchable region provided by the ptrace interface. */
1516 if (booke_debug_info
.data_bp_alignment
1517 && (addr
+ len
> (addr
& ~(booke_debug_info
.data_bp_alignment
- 1))
1518 + booke_debug_info
.data_bp_alignment
))
1521 /* addr+len must fall in the 8 byte watchable region for DABR-based
1522 processors (i.e., server processors). Without the new BookE ptrace
1523 interface, DAC-based processors (i.e., embedded processors) will use
1524 addresses aligned to 4-bytes due to the way the read/write flags are
1525 passed in the old ptrace interface. */
1526 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1527 && (addr
+ len
) > (addr
& ~3) + 4)
1528 || (addr
+ len
) > (addr
& ~7) + 8)
1534 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1536 booke_cmp_hw_point (struct ppc_hw_breakpoint
*a
, struct ppc_hw_breakpoint
*b
)
1538 return (a
->trigger_type
== b
->trigger_type
1539 && a
->addr_mode
== b
->addr_mode
1540 && a
->condition_mode
== b
->condition_mode
1541 && a
->addr
== b
->addr
1542 && a
->addr2
== b
->addr2
1543 && a
->condition_value
== b
->condition_value
);
1546 /* This function can be used to retrieve a thread_points by the TID of the
1547 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1548 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1549 provided TID will be created and returned. */
1550 static struct thread_points
*
1551 booke_find_thread_points_by_tid (int tid
, int alloc_new
)
1554 struct thread_points
*t
;
1556 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, t
); i
++)
1562 /* Do we need to allocate a new point_item
1563 if the wanted one does not exist? */
1566 t
= xmalloc (sizeof (struct thread_points
));
1568 = xzalloc (max_slots_number
* sizeof (struct hw_break_tuple
));
1570 VEC_safe_push (thread_points_p
, ppc_threads
, t
);
1576 /* This function is a generic wrapper that is responsible for inserting a
1577 *point (i.e., calling `ptrace' in order to issue the request to the
1578 kernel) and registering it internally in GDB. */
1580 booke_insert_point (struct ppc_hw_breakpoint
*b
, int tid
)
1584 struct ppc_hw_breakpoint
*p
= xmalloc (sizeof (struct ppc_hw_breakpoint
));
1585 struct hw_break_tuple
*hw_breaks
;
1586 struct cleanup
*c
= make_cleanup (xfree
, p
);
1587 struct thread_points
*t
;
1588 struct hw_break_tuple
*tuple
;
1590 memcpy (p
, b
, sizeof (struct ppc_hw_breakpoint
));
1593 slot
= ptrace (PPC_PTRACE_SETHWDEBUG
, tid
, 0, p
);
1595 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1597 /* Everything went fine, so we have to register this *point. */
1598 t
= booke_find_thread_points_by_tid (tid
, 1);
1599 gdb_assert (t
!= NULL
);
1600 hw_breaks
= t
->hw_breaks
;
1602 /* Find a free element in the hw_breaks vector. */
1603 for (i
= 0; i
< max_slots_number
; i
++)
1604 if (hw_breaks
[i
].hw_break
== NULL
)
1606 hw_breaks
[i
].slot
= slot
;
1607 hw_breaks
[i
].hw_break
= p
;
1611 gdb_assert (i
!= max_slots_number
);
1613 discard_cleanups (c
);
1616 /* This function is a generic wrapper that is responsible for removing a
1617 *point (i.e., calling `ptrace' in order to issue the request to the
1618 kernel), and unregistering it internally at GDB. */
1620 booke_remove_point (struct ppc_hw_breakpoint
*b
, int tid
)
1623 struct hw_break_tuple
*hw_breaks
;
1624 struct thread_points
*t
;
1626 t
= booke_find_thread_points_by_tid (tid
, 0);
1627 gdb_assert (t
!= NULL
);
1628 hw_breaks
= t
->hw_breaks
;
1630 for (i
= 0; i
< max_slots_number
; i
++)
1631 if (hw_breaks
[i
].hw_break
&& booke_cmp_hw_point (hw_breaks
[i
].hw_break
, b
))
1634 gdb_assert (i
!= max_slots_number
);
1636 /* We have to ignore ENOENT errors because the kernel implements hardware
1637 breakpoints/watchpoints as "one-shot", that is, they are automatically
1638 deleted when hit. */
1640 if (ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
) < 0)
1641 if (errno
!= ENOENT
)
1642 perror_with_name (_("Unexpected error deleting "
1643 "breakpoint or watchpoint"));
1645 xfree (hw_breaks
[i
].hw_break
);
1646 hw_breaks
[i
].hw_break
= NULL
;
1649 /* Return the number of registers needed for a ranged breakpoint. */
1652 ppc_linux_ranged_break_num_registers (struct target_ops
*target
)
1654 return ((have_ptrace_booke_interface ()
1655 && booke_debug_info
.features
& PPC_DEBUG_FEATURE_INSN_BP_RANGE
)?
1659 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1660 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1663 ppc_linux_insert_hw_breakpoint (struct gdbarch
*gdbarch
,
1664 struct bp_target_info
*bp_tgt
)
1666 struct lwp_info
*lp
;
1667 struct ppc_hw_breakpoint p
;
1669 if (!have_ptrace_booke_interface ())
1672 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1673 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1674 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1675 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1676 p
.condition_value
= 0;
1680 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1682 /* The breakpoint will trigger if the address of the instruction is
1683 within the defined range, as follows: p.addr <= address < p.addr2. */
1684 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1688 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1693 booke_insert_point (&p
, TIDGET (lp
->ptid
));
1699 ppc_linux_remove_hw_breakpoint (struct gdbarch
*gdbarch
,
1700 struct bp_target_info
*bp_tgt
)
1702 struct lwp_info
*lp
;
1703 struct ppc_hw_breakpoint p
;
1705 if (!have_ptrace_booke_interface ())
1708 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1709 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1710 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1711 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1712 p
.condition_value
= 0;
1716 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1718 /* The breakpoint will trigger if the address of the instruction is within
1719 the defined range, as follows: p.addr <= address < p.addr2. */
1720 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1724 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1729 booke_remove_point (&p
, TIDGET (lp
->ptid
));
1735 get_trigger_type (int rw
)
1740 t
= PPC_BREAKPOINT_TRIGGER_READ
;
1741 else if (rw
== hw_write
)
1742 t
= PPC_BREAKPOINT_TRIGGER_WRITE
;
1744 t
= PPC_BREAKPOINT_TRIGGER_READ
| PPC_BREAKPOINT_TRIGGER_WRITE
;
1749 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1750 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1751 or hw_access for an access watchpoint. Returns 0 on success and throws
1752 an error on failure. */
1755 ppc_linux_insert_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1756 CORE_ADDR mask
, int rw
)
1758 struct lwp_info
*lp
;
1759 struct ppc_hw_breakpoint p
;
1761 gdb_assert (have_ptrace_booke_interface ());
1763 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1764 p
.trigger_type
= get_trigger_type (rw
);
1765 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1766 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1769 p
.condition_value
= 0;
1772 booke_insert_point (&p
, TIDGET (lp
->ptid
));
1777 /* Remove a masked watchpoint at ADDR with the mask MASK.
1778 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1779 or hw_access for an access watchpoint. Returns 0 on success and throws
1780 an error on failure. */
1783 ppc_linux_remove_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1784 CORE_ADDR mask
, int rw
)
1786 struct lwp_info
*lp
;
1787 struct ppc_hw_breakpoint p
;
1789 gdb_assert (have_ptrace_booke_interface ());
1791 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1792 p
.trigger_type
= get_trigger_type (rw
);
1793 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1794 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1797 p
.condition_value
= 0;
1800 booke_remove_point (&p
, TIDGET (lp
->ptid
));
1805 /* Check whether we have at least one free DVC register. */
1807 can_use_watchpoint_cond_accel (void)
1809 struct thread_points
*p
;
1810 int tid
= TIDGET (inferior_ptid
);
1811 int cnt
= booke_debug_info
.num_condition_regs
, i
;
1812 CORE_ADDR tmp_value
;
1814 if (!have_ptrace_booke_interface () || cnt
== 0)
1817 p
= booke_find_thread_points_by_tid (tid
, 0);
1821 for (i
= 0; i
< max_slots_number
; i
++)
1822 if (p
->hw_breaks
[i
].hw_break
!= NULL
1823 && (p
->hw_breaks
[i
].hw_break
->condition_mode
1824 != PPC_BREAKPOINT_CONDITION_NONE
))
1827 /* There are no available slots now. */
1835 /* Calculate the enable bits and the contents of the Data Value Compare
1836 debug register present in BookE processors.
1838 ADDR is the address to be watched, LEN is the length of watched data
1839 and DATA_VALUE is the value which will trigger the watchpoint.
1840 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1841 CONDITION_VALUE will hold the value which should be put in the
1844 calculate_dvc (CORE_ADDR addr
, int len
, CORE_ADDR data_value
,
1845 uint32_t *condition_mode
, uint64_t *condition_value
)
1847 int i
, num_byte_enable
, align_offset
, num_bytes_off_dvc
,
1848 rightmost_enabled_byte
;
1849 CORE_ADDR addr_end_data
, addr_end_dvc
;
1851 /* The DVC register compares bytes within fixed-length windows which
1852 are word-aligned, with length equal to that of the DVC register.
1853 We need to calculate where our watch region is relative to that
1854 window and enable comparison of the bytes which fall within it. */
1856 align_offset
= addr
% booke_debug_info
.sizeof_condition
;
1857 addr_end_data
= addr
+ len
;
1858 addr_end_dvc
= (addr
- align_offset
1859 + booke_debug_info
.sizeof_condition
);
1860 num_bytes_off_dvc
= (addr_end_data
> addr_end_dvc
)?
1861 addr_end_data
- addr_end_dvc
: 0;
1862 num_byte_enable
= len
- num_bytes_off_dvc
;
1863 /* Here, bytes are numbered from right to left. */
1864 rightmost_enabled_byte
= (addr_end_data
< addr_end_dvc
)?
1865 addr_end_dvc
- addr_end_data
: 0;
1867 *condition_mode
= PPC_BREAKPOINT_CONDITION_AND
;
1868 for (i
= 0; i
< num_byte_enable
; i
++)
1870 |= PPC_BREAKPOINT_CONDITION_BE (i
+ rightmost_enabled_byte
);
1872 /* Now we need to match the position within the DVC of the comparison
1873 value with where the watch region is relative to the window
1874 (i.e., the ALIGN_OFFSET). */
1876 *condition_value
= ((uint64_t) data_value
>> num_bytes_off_dvc
* 8
1877 << rightmost_enabled_byte
* 8);
1880 /* Return the number of memory locations that need to be accessed to
1881 evaluate the expression which generated the given value chain.
1882 Returns -1 if there's any register access involved, or if there are
1883 other kinds of values which are not acceptable in a condition
1884 expression (e.g., lval_computed or lval_internalvar). */
1886 num_memory_accesses (struct value
*v
)
1888 int found_memory_cnt
= 0;
1889 struct value
*head
= v
;
1891 /* The idea here is that evaluating an expression generates a series
1892 of values, one holding the value of every subexpression. (The
1893 expression a*b+c has five subexpressions: a, b, a*b, c, and
1894 a*b+c.) GDB's values hold almost enough information to establish
1895 the criteria given above --- they identify memory lvalues,
1896 register lvalues, computed values, etcetera. So we can evaluate
1897 the expression, and then scan the chain of values that leaves
1898 behind to determine the memory locations involved in the evaluation
1901 However, I don't think that the values returned by inferior
1902 function calls are special in any way. So this function may not
1903 notice that an expression contains an inferior function call.
1906 for (; v
; v
= value_next (v
))
1908 /* Constants and values from the history are fine. */
1909 if (VALUE_LVAL (v
) == not_lval
|| deprecated_value_modifiable (v
) == 0)
1911 else if (VALUE_LVAL (v
) == lval_memory
)
1913 /* A lazy memory lvalue is one that GDB never needed to fetch;
1914 we either just used its address (e.g., `a' in `a.b') or
1915 we never needed it at all (e.g., `a' in `a,b'). */
1916 if (!value_lazy (v
))
1919 /* Other kinds of values are not fine. */
1924 return found_memory_cnt
;
1927 /* Verifies whether the expression COND can be implemented using the
1928 DVC (Data Value Compare) register in BookE processors. The expression
1929 must test the watch value for equality with a constant expression.
1930 If the function returns 1, DATA_VALUE will contain the constant against
1931 which the watch value should be compared and LEN will contain the size
1934 check_condition (CORE_ADDR watch_addr
, struct expression
*cond
,
1935 CORE_ADDR
*data_value
, int *len
)
1937 int pc
= 1, num_accesses_left
, num_accesses_right
;
1938 struct value
*left_val
, *right_val
, *left_chain
, *right_chain
;
1940 if (cond
->elts
[0].opcode
!= BINOP_EQUAL
)
1943 fetch_subexp_value (cond
, &pc
, &left_val
, NULL
, &left_chain
);
1944 num_accesses_left
= num_memory_accesses (left_chain
);
1946 if (left_val
== NULL
|| num_accesses_left
< 0)
1948 free_value_chain (left_chain
);
1953 fetch_subexp_value (cond
, &pc
, &right_val
, NULL
, &right_chain
);
1954 num_accesses_right
= num_memory_accesses (right_chain
);
1956 if (right_val
== NULL
|| num_accesses_right
< 0)
1958 free_value_chain (left_chain
);
1959 free_value_chain (right_chain
);
1964 if (num_accesses_left
== 1 && num_accesses_right
== 0
1965 && VALUE_LVAL (left_val
) == lval_memory
1966 && value_address (left_val
) == watch_addr
)
1968 *data_value
= value_as_long (right_val
);
1970 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1971 the same type as the memory region referenced by LEFT_VAL. */
1972 *len
= TYPE_LENGTH (check_typedef (value_type (left_val
)));
1974 else if (num_accesses_left
== 0 && num_accesses_right
== 1
1975 && VALUE_LVAL (right_val
) == lval_memory
1976 && value_address (right_val
) == watch_addr
)
1978 *data_value
= value_as_long (left_val
);
1980 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1981 the same type as the memory region referenced by RIGHT_VAL. */
1982 *len
= TYPE_LENGTH (check_typedef (value_type (right_val
)));
1986 free_value_chain (left_chain
);
1987 free_value_chain (right_chain
);
1992 free_value_chain (left_chain
);
1993 free_value_chain (right_chain
);
1998 /* Return non-zero if the target is capable of using hardware to evaluate
1999 the condition expression, thus only triggering the watchpoint when it is
2002 ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr
, int len
, int rw
,
2003 struct expression
*cond
)
2005 CORE_ADDR data_value
;
2007 return (have_ptrace_booke_interface ()
2008 && booke_debug_info
.num_condition_regs
> 0
2009 && check_condition (addr
, cond
, &data_value
, &len
));
2012 /* Set up P with the parameters necessary to request a watchpoint covering
2013 LEN bytes starting at ADDR and if possible with condition expression COND
2014 evaluated by hardware. INSERT tells if we are creating a request for
2015 inserting or removing the watchpoint. */
2018 create_watchpoint_request (struct ppc_hw_breakpoint
*p
, CORE_ADDR addr
,
2019 int len
, int rw
, struct expression
*cond
,
2023 || !(booke_debug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
))
2026 CORE_ADDR data_value
;
2028 use_condition
= (insert
? can_use_watchpoint_cond_accel ()
2029 : booke_debug_info
.num_condition_regs
> 0);
2030 if (cond
&& use_condition
&& check_condition (addr
, cond
,
2032 calculate_dvc (addr
, len
, data_value
, &p
->condition_mode
,
2033 &p
->condition_value
);
2036 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2037 p
->condition_value
= 0;
2040 p
->addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
2045 p
->addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
2046 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2047 p
->condition_value
= 0;
2049 /* The watchpoint will trigger if the address of the memory access is
2050 within the defined range, as follows: p->addr <= address < p->addr2.
2052 Note that the above sentence just documents how ptrace interprets
2053 its arguments; the watchpoint is set to watch the range defined by
2054 the user _inclusively_, as specified by the user interface. */
2055 p
->addr2
= (uint64_t) addr
+ len
;
2058 p
->version
= PPC_DEBUG_CURRENT_VERSION
;
2059 p
->trigger_type
= get_trigger_type (rw
);
2060 p
->addr
= (uint64_t) addr
;
2064 ppc_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int rw
,
2065 struct expression
*cond
)
2067 struct lwp_info
*lp
;
2070 if (have_ptrace_booke_interface ())
2072 struct ppc_hw_breakpoint p
;
2074 create_watchpoint_request (&p
, addr
, len
, rw
, cond
, 1);
2077 booke_insert_point (&p
, TIDGET (lp
->ptid
));
2084 long read_mode
, write_mode
;
2086 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2088 /* PowerPC 440 requires only the read/write flags to be passed
2095 /* PowerPC 970 and other DABR-based processors are required to pass
2096 the Breakpoint Translation bit together with the flags. */
2101 dabr_value
= addr
& ~(read_mode
| write_mode
);
2105 /* Set read and translate bits. */
2106 dabr_value
|= read_mode
;
2109 /* Set write and translate bits. */
2110 dabr_value
|= write_mode
;
2113 /* Set read, write and translate bits. */
2114 dabr_value
|= read_mode
| write_mode
;
2118 saved_dabr_value
= dabr_value
;
2121 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (lp
->ptid
), 0,
2122 saved_dabr_value
) < 0)
2132 ppc_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int rw
,
2133 struct expression
*cond
)
2135 struct lwp_info
*lp
;
2138 if (have_ptrace_booke_interface ())
2140 struct ppc_hw_breakpoint p
;
2142 create_watchpoint_request (&p
, addr
, len
, rw
, cond
, 0);
2145 booke_remove_point (&p
, TIDGET (lp
->ptid
));
2151 saved_dabr_value
= 0;
2153 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (lp
->ptid
), 0,
2154 saved_dabr_value
) < 0)
2164 ppc_linux_new_thread (struct lwp_info
*lp
)
2166 int tid
= TIDGET (lp
->ptid
);
2168 if (have_ptrace_booke_interface ())
2171 struct thread_points
*p
;
2172 struct hw_break_tuple
*hw_breaks
;
2174 if (VEC_empty (thread_points_p
, ppc_threads
))
2177 /* Get a list of breakpoints from any thread. */
2178 p
= VEC_last (thread_points_p
, ppc_threads
);
2179 hw_breaks
= p
->hw_breaks
;
2181 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2182 for (i
= 0; i
< max_slots_number
; i
++)
2183 if (hw_breaks
[i
].hw_break
)
2185 /* Older kernels did not make new threads inherit their parent
2186 thread's debug state, so we always clear the slot and replicate
2187 the debug state ourselves, ensuring compatibility with all
2190 /* The ppc debug resource accounting is done through "slots".
2191 Ask the kernel the deallocate this specific *point's slot. */
2192 ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
);
2194 booke_insert_point (hw_breaks
[i
].hw_break
, tid
);
2198 ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, saved_dabr_value
);
2202 ppc_linux_thread_exit (struct thread_info
*tp
, int silent
)
2205 int tid
= TIDGET (tp
->ptid
);
2206 struct hw_break_tuple
*hw_breaks
;
2207 struct thread_points
*t
= NULL
, *p
;
2209 if (!have_ptrace_booke_interface ())
2212 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, p
); i
++)
2222 VEC_unordered_remove (thread_points_p
, ppc_threads
, i
);
2224 hw_breaks
= t
->hw_breaks
;
2226 for (i
= 0; i
< max_slots_number
; i
++)
2227 if (hw_breaks
[i
].hw_break
)
2228 xfree (hw_breaks
[i
].hw_break
);
2230 xfree (t
->hw_breaks
);
2235 ppc_linux_stopped_data_address (struct target_ops
*target
, CORE_ADDR
*addr_p
)
2239 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
2242 if (siginfo
.si_signo
!= SIGTRAP
2243 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2246 if (have_ptrace_booke_interface ())
2249 struct thread_points
*t
;
2250 struct hw_break_tuple
*hw_breaks
;
2251 /* The index (or slot) of the *point is passed in the si_errno field. */
2252 int slot
= siginfo
.si_errno
;
2254 t
= booke_find_thread_points_by_tid (TIDGET (inferior_ptid
), 0);
2256 /* Find out if this *point is a hardware breakpoint.
2257 If so, we should return 0. */
2260 hw_breaks
= t
->hw_breaks
;
2261 for (i
= 0; i
< max_slots_number
; i
++)
2262 if (hw_breaks
[i
].hw_break
&& hw_breaks
[i
].slot
== slot
2263 && hw_breaks
[i
].hw_break
->trigger_type
2264 == PPC_BREAKPOINT_TRIGGER_EXECUTE
)
2269 *addr_p
= (CORE_ADDR
) (uintptr_t) siginfo
.si_addr
;
2274 ppc_linux_stopped_by_watchpoint (void)
2277 return ppc_linux_stopped_data_address (¤t_target
, &addr
);
2281 ppc_linux_watchpoint_addr_within_range (struct target_ops
*target
,
2283 CORE_ADDR start
, int length
)
2287 if (have_ptrace_booke_interface ()
2288 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2289 return start
<= addr
&& start
+ length
>= addr
;
2290 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2297 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2298 return start
<= addr
+ mask
&& start
+ length
- 1 >= addr
;
2301 /* Return the number of registers needed for a masked hardware watchpoint. */
2304 ppc_linux_masked_watch_num_registers (struct target_ops
*target
,
2305 CORE_ADDR addr
, CORE_ADDR mask
)
2307 if (!have_ptrace_booke_interface ()
2308 || (booke_debug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_MASK
) == 0)
2310 else if ((mask
& 0xC0000000) != 0xC0000000)
2312 warning (_("The given mask covers kernel address space "
2313 "and cannot be used.\n"));
2322 ppc_linux_store_inferior_registers (struct target_ops
*ops
,
2323 struct regcache
*regcache
, int regno
)
2325 /* Overload thread id onto process id. */
2326 int tid
= TIDGET (inferior_ptid
);
2328 /* No thread id, just use process id. */
2330 tid
= PIDGET (inferior_ptid
);
2333 store_register (regcache
, tid
, regno
);
2335 store_ppc_registers (regcache
, tid
);
2338 /* Functions for transferring registers between a gregset_t or fpregset_t
2339 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2340 by the ptrace interface, not the current program's ABI. Eg. if a
2341 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2342 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2345 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
2347 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2349 ppc_supply_gregset (regset
, regcache
, -1, gregsetp
, sizeof (*gregsetp
));
2353 fill_gregset (const struct regcache
*regcache
,
2354 gdb_gregset_t
*gregsetp
, int regno
)
2356 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2359 memset (gregsetp
, 0, sizeof (*gregsetp
));
2360 ppc_collect_gregset (regset
, regcache
, regno
, gregsetp
, sizeof (*gregsetp
));
2364 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
* fpregsetp
)
2366 const struct regset
*regset
= ppc_linux_fpregset ();
2368 ppc_supply_fpregset (regset
, regcache
, -1,
2369 fpregsetp
, sizeof (*fpregsetp
));
2373 fill_fpregset (const struct regcache
*regcache
,
2374 gdb_fpregset_t
*fpregsetp
, int regno
)
2376 const struct regset
*regset
= ppc_linux_fpregset ();
2378 ppc_collect_fpregset (regset
, regcache
, regno
,
2379 fpregsetp
, sizeof (*fpregsetp
));
2383 ppc_linux_target_wordsize (void)
2387 /* Check for 64-bit inferior process. This is the case when the host is
2388 64-bit, and in addition the top bit of the MSR register is set. */
2389 #ifdef __powerpc64__
2392 int tid
= TIDGET (inferior_ptid
);
2394 tid
= PIDGET (inferior_ptid
);
2397 msr
= (long) ptrace (PTRACE_PEEKUSER
, tid
, PT_MSR
* 8, 0);
2398 if (errno
== 0 && msr
< 0)
2406 ppc_linux_auxv_parse (struct target_ops
*ops
, gdb_byte
**readptr
,
2407 gdb_byte
*endptr
, CORE_ADDR
*typep
, CORE_ADDR
*valp
)
2409 int sizeof_auxv_field
= ppc_linux_target_wordsize ();
2410 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
2411 gdb_byte
*ptr
= *readptr
;
2416 if (endptr
- ptr
< sizeof_auxv_field
* 2)
2419 *typep
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2420 ptr
+= sizeof_auxv_field
;
2421 *valp
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2422 ptr
+= sizeof_auxv_field
;
2428 static const struct target_desc
*
2429 ppc_linux_read_description (struct target_ops
*ops
)
2436 int tid
= TIDGET (inferior_ptid
);
2438 tid
= PIDGET (inferior_ptid
);
2440 if (have_ptrace_getsetevrregs
)
2442 struct gdb_evrregset_t evrregset
;
2444 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, &evrregset
) >= 0)
2445 return tdesc_powerpc_e500l
;
2447 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2448 Anything else needs to be reported. */
2449 else if (errno
!= EIO
)
2450 perror_with_name (_("Unable to fetch SPE registers"));
2453 if (have_ptrace_getsetvsxregs
)
2455 gdb_vsxregset_t vsxregset
;
2457 if (ptrace (PTRACE_GETVSXREGS
, tid
, 0, &vsxregset
) >= 0)
2460 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2461 Anything else needs to be reported. */
2462 else if (errno
!= EIO
)
2463 perror_with_name (_("Unable to fetch VSX registers"));
2466 if (have_ptrace_getvrregs
)
2468 gdb_vrregset_t vrregset
;
2470 if (ptrace (PTRACE_GETVRREGS
, tid
, 0, &vrregset
) >= 0)
2473 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2474 Anything else needs to be reported. */
2475 else if (errno
!= EIO
)
2476 perror_with_name (_("Unable to fetch AltiVec registers"));
2479 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2480 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2481 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2482 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2483 half of the register are for Decimal Floating Point, we check if that
2484 feature is available to decide the size of the FPSCR. */
2485 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP
)
2488 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL
)
2491 if (ppc_linux_target_wordsize () == 8)
2494 return tdesc_powerpc_cell64l
;
2496 return isa205
? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l
;
2499 ? tdesc_powerpc_isa205_altivec64l
: tdesc_powerpc_altivec64l
;
2501 return isa205
? tdesc_powerpc_isa205_64l
: tdesc_powerpc_64l
;
2505 return tdesc_powerpc_cell32l
;
2507 return isa205
? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l
;
2509 return isa205
? tdesc_powerpc_isa205_altivec32l
: tdesc_powerpc_altivec32l
;
2511 return isa205
? tdesc_powerpc_isa205_32l
: tdesc_powerpc_32l
;
2514 void _initialize_ppc_linux_nat (void);
2517 _initialize_ppc_linux_nat (void)
2519 struct target_ops
*t
;
2521 /* Fill in the generic GNU/Linux methods. */
2522 t
= linux_target ();
2524 /* Add our register access methods. */
2525 t
->to_fetch_registers
= ppc_linux_fetch_inferior_registers
;
2526 t
->to_store_registers
= ppc_linux_store_inferior_registers
;
2528 /* Add our breakpoint/watchpoint methods. */
2529 t
->to_can_use_hw_breakpoint
= ppc_linux_can_use_hw_breakpoint
;
2530 t
->to_insert_hw_breakpoint
= ppc_linux_insert_hw_breakpoint
;
2531 t
->to_remove_hw_breakpoint
= ppc_linux_remove_hw_breakpoint
;
2532 t
->to_region_ok_for_hw_watchpoint
= ppc_linux_region_ok_for_hw_watchpoint
;
2533 t
->to_insert_watchpoint
= ppc_linux_insert_watchpoint
;
2534 t
->to_remove_watchpoint
= ppc_linux_remove_watchpoint
;
2535 t
->to_insert_mask_watchpoint
= ppc_linux_insert_mask_watchpoint
;
2536 t
->to_remove_mask_watchpoint
= ppc_linux_remove_mask_watchpoint
;
2537 t
->to_stopped_by_watchpoint
= ppc_linux_stopped_by_watchpoint
;
2538 t
->to_stopped_data_address
= ppc_linux_stopped_data_address
;
2539 t
->to_watchpoint_addr_within_range
= ppc_linux_watchpoint_addr_within_range
;
2540 t
->to_can_accel_watchpoint_condition
2541 = ppc_linux_can_accel_watchpoint_condition
;
2542 t
->to_masked_watch_num_registers
= ppc_linux_masked_watch_num_registers
;
2543 t
->to_ranged_break_num_registers
= ppc_linux_ranged_break_num_registers
;
2545 t
->to_read_description
= ppc_linux_read_description
;
2546 t
->to_auxv_parse
= ppc_linux_auxv_parse
;
2548 observer_attach_thread_exit (ppc_linux_thread_exit
);
2550 /* Register the target. */
2551 linux_nat_add_target (t
);
2552 linux_nat_set_new_thread (t
, ppc_linux_new_thread
);