1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "gdbthread.h"
28 #include "gdb_assert.h"
30 #include "linux-nat.h"
33 #include <sys/types.h>
36 #include <sys/ioctl.h>
39 #include <sys/procfs.h>
40 #include <sys/ptrace.h>
42 /* Prototypes for supply_gregset etc. */
45 #include "ppc-linux-tdep.h"
47 /* Required when using the AUXV. */
48 #include "elf/common.h"
51 /* This sometimes isn't defined. */
59 /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
60 If they aren't, we can provide them ourselves (their values are fixed
61 because they are part of the kernel ABI). They are used in the AT_HWCAP
63 #ifndef PPC_FEATURE_CELL
64 #define PPC_FEATURE_CELL 0x00010000
66 #ifndef PPC_FEATURE_BOOKE
67 #define PPC_FEATURE_BOOKE 0x00008000
69 #ifndef PPC_FEATURE_HAS_DFP
70 #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
73 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
74 configure time check. Some older glibc's (for instance 2.2.1)
75 don't have a specific powerpc version of ptrace.h, and fall back on
76 a generic one. In such cases, sys/ptrace.h defines
77 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
78 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
79 PTRACE_SETVRREGS to be. This also makes a configury check pretty
82 /* These definitions should really come from the glibc header files,
83 but Glibc doesn't know about the vrregs yet. */
84 #ifndef PTRACE_GETVRREGS
85 #define PTRACE_GETVRREGS 18
86 #define PTRACE_SETVRREGS 19
89 /* PTRACE requests for POWER7 VSX registers. */
90 #ifndef PTRACE_GETVSXREGS
91 #define PTRACE_GETVSXREGS 27
92 #define PTRACE_SETVSXREGS 28
95 /* Similarly for the ptrace requests for getting / setting the SPE
96 registers (ev0 -- ev31, acc, and spefscr). See the description of
97 gdb_evrregset_t for details. */
98 #ifndef PTRACE_GETEVRREGS
99 #define PTRACE_GETEVRREGS 20
100 #define PTRACE_SETEVRREGS 21
103 /* Similarly for the hardware watchpoint support. These requests are used
104 when the PowerPC HWDEBUG ptrace interface is not available. */
105 #ifndef PTRACE_GET_DEBUGREG
106 #define PTRACE_GET_DEBUGREG 25
108 #ifndef PTRACE_SET_DEBUGREG
109 #define PTRACE_SET_DEBUGREG 26
111 #ifndef PTRACE_GETSIGINFO
112 #define PTRACE_GETSIGINFO 0x4202
115 /* These requests are used when the PowerPC HWDEBUG ptrace interface is
116 available. It exposes the debug facilities of PowerPC processors, as well
117 as additional features of BookE processors, such as ranged breakpoints and
118 watchpoints and hardware-accelerated condition evaluation. */
119 #ifndef PPC_PTRACE_GETHWDBGINFO
121 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
122 ptrace interface is not present in ptrace.h, so we'll have to pretty much
123 include it all here so that the code at least compiles on older systems. */
124 #define PPC_PTRACE_GETHWDBGINFO 0x89
125 #define PPC_PTRACE_SETHWDEBUG 0x88
126 #define PPC_PTRACE_DELHWDEBUG 0x87
128 struct ppc_debug_info
130 uint32_t version
; /* Only version 1 exists to date. */
131 uint32_t num_instruction_bps
;
132 uint32_t num_data_bps
;
133 uint32_t num_condition_regs
;
134 uint32_t data_bp_alignment
;
135 uint32_t sizeof_condition
; /* size of the DVC register. */
139 /* Features will have bits indicating whether there is support for: */
140 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
141 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
142 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
143 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
145 struct ppc_hw_breakpoint
147 uint32_t version
; /* currently, version must be 1 */
148 uint32_t trigger_type
; /* only some combinations allowed */
149 uint32_t addr_mode
; /* address match mode */
150 uint32_t condition_mode
; /* break/watchpoint condition flags */
151 uint64_t addr
; /* break/watchpoint address */
152 uint64_t addr2
; /* range end or mask */
153 uint64_t condition_value
; /* contents of the DVC register */
157 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
158 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
159 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
160 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
163 #define PPC_BREAKPOINT_MODE_EXACT 0x0
164 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
165 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
166 #define PPC_BREAKPOINT_MODE_MASK 0x3
168 /* Condition mode. */
169 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
170 #define PPC_BREAKPOINT_CONDITION_AND 0x1
171 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
172 #define PPC_BREAKPOINT_CONDITION_OR 0x2
173 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
174 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
175 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
176 #define PPC_BREAKPOINT_CONDITION_BE(n) \
177 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
178 #endif /* PPC_PTRACE_GETHWDBGINFO */
180 /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
181 watchpoint (up to 512 bytes). */
182 #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
183 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
184 #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
186 /* Similarly for the general-purpose (gp0 -- gp31)
187 and floating-point registers (fp0 -- fp31). */
188 #ifndef PTRACE_GETREGS
189 #define PTRACE_GETREGS 12
191 #ifndef PTRACE_SETREGS
192 #define PTRACE_SETREGS 13
194 #ifndef PTRACE_GETFPREGS
195 #define PTRACE_GETFPREGS 14
197 #ifndef PTRACE_SETFPREGS
198 #define PTRACE_SETFPREGS 15
201 /* This oddity is because the Linux kernel defines elf_vrregset_t as
202 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
203 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
204 the vrsave as an extra 4 bytes at the end. I opted for creating a
205 flat array of chars, so that it is easier to manipulate for gdb.
207 There are 32 vector registers 16 bytes longs, plus a VSCR register
208 which is only 4 bytes long, but is fetched as a 16 bytes
209 quantity. Up to here we have the elf_vrregset_t structure.
210 Appended to this there is space for the VRSAVE register: 4 bytes.
211 Even though this vrsave register is not included in the regset
212 typedef, it is handled by the ptrace requests.
214 Note that GNU/Linux doesn't support little endian PPC hardware,
215 therefore the offset at which the real value of the VSCR register
216 is located will be always 12 bytes.
218 The layout is like this (where x is the actual value of the vscr reg): */
222 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
223 <-------> <-------><-------><->
228 #define SIZEOF_VRREGS 33*16+4
230 typedef char gdb_vrregset_t
[SIZEOF_VRREGS
];
232 /* This is the layout of the POWER7 VSX registers and the way they overlap
233 with the existing FPR and VMX registers.
235 VSR doubleword 0 VSR doubleword 1
236 ----------------------------------------------------------------
238 ----------------------------------------------------------------
240 ----------------------------------------------------------------
243 ----------------------------------------------------------------
244 VSR[30] | FPR[30] | |
245 ----------------------------------------------------------------
246 VSR[31] | FPR[31] | |
247 ----------------------------------------------------------------
249 ----------------------------------------------------------------
251 ----------------------------------------------------------------
254 ----------------------------------------------------------------
256 ----------------------------------------------------------------
258 ----------------------------------------------------------------
260 VSX has 64 128bit registers. The first 32 registers overlap with
261 the FP registers (doubleword 0) and hence extend them with additional
262 64 bits (doubleword 1). The other 32 regs overlap with the VMX
264 #define SIZEOF_VSXREGS 32*8
266 typedef char gdb_vsxregset_t
[SIZEOF_VSXREGS
];
268 /* On PPC processors that support the Signal Processing Extension
269 (SPE) APU, the general-purpose registers are 64 bits long.
270 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
271 ptrace calls only access the lower half of each register, to allow
272 them to behave the same way they do on non-SPE systems. There's a
273 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
274 read and write the top halves of all the general-purpose registers
275 at once, along with some SPE-specific registers.
277 GDB itself continues to claim the general-purpose registers are 32
278 bits long. It has unnamed raw registers that hold the upper halves
279 of the gprs, and the full 64-bit SIMD views of the registers,
280 'ev0' -- 'ev31', are pseudo-registers that splice the top and
281 bottom halves together.
283 This is the structure filled in by PTRACE_GETEVRREGS and written to
284 the inferior's registers by PTRACE_SETEVRREGS. */
285 struct gdb_evrregset_t
287 unsigned long evr
[32];
288 unsigned long long acc
;
289 unsigned long spefscr
;
292 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
293 PTRACE_SETVSXREGS requests, for reading and writing the VSX
294 POWER7 registers 0 through 31. Zero if we've tried one of them and
295 gotten an error. Note that VSX registers 32 through 63 overlap
296 with VR registers 0 through 31. */
297 int have_ptrace_getsetvsxregs
= 1;
299 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
300 PTRACE_SETVRREGS requests, for reading and writing the Altivec
301 registers. Zero if we've tried one of them and gotten an
303 int have_ptrace_getvrregs
= 1;
305 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
306 PTRACE_SETEVRREGS requests, for reading and writing the SPE
307 registers. Zero if we've tried one of them and gotten an
309 int have_ptrace_getsetevrregs
= 1;
311 /* Non-zero if our kernel may support the PTRACE_GETREGS and
312 PTRACE_SETREGS requests, for reading and writing the
313 general-purpose registers. Zero if we've tried one of
314 them and gotten an error. */
315 int have_ptrace_getsetregs
= 1;
317 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
318 PTRACE_SETFPREGS requests, for reading and writing the
319 floating-pointers registers. Zero if we've tried one of
320 them and gotten an error. */
321 int have_ptrace_getsetfpregs
= 1;
324 /* registers layout, as presented by the ptrace interface:
325 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
326 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
327 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
328 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
329 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
330 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
331 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
332 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
333 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
334 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
335 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
336 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
337 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
341 ppc_register_u_addr (struct gdbarch
*gdbarch
, int regno
)
344 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
345 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
346 interface, and not the wordsize of the program's ABI. */
347 int wordsize
= sizeof (long);
349 /* General purpose registers occupy 1 slot each in the buffer. */
350 if (regno
>= tdep
->ppc_gp0_regnum
351 && regno
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
352 u_addr
= ((regno
- tdep
->ppc_gp0_regnum
+ PT_R0
) * wordsize
);
354 /* Floating point regs: eight bytes each in both 32- and 64-bit
355 ptrace interfaces. Thus, two slots each in 32-bit interface, one
356 slot each in 64-bit interface. */
357 if (tdep
->ppc_fp0_regnum
>= 0
358 && regno
>= tdep
->ppc_fp0_regnum
359 && regno
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
360 u_addr
= (PT_FPR0
* wordsize
) + ((regno
- tdep
->ppc_fp0_regnum
) * 8);
362 /* UISA special purpose registers: 1 slot each. */
363 if (regno
== gdbarch_pc_regnum (gdbarch
))
364 u_addr
= PT_NIP
* wordsize
;
365 if (regno
== tdep
->ppc_lr_regnum
)
366 u_addr
= PT_LNK
* wordsize
;
367 if (regno
== tdep
->ppc_cr_regnum
)
368 u_addr
= PT_CCR
* wordsize
;
369 if (regno
== tdep
->ppc_xer_regnum
)
370 u_addr
= PT_XER
* wordsize
;
371 if (regno
== tdep
->ppc_ctr_regnum
)
372 u_addr
= PT_CTR
* wordsize
;
374 if (regno
== tdep
->ppc_mq_regnum
)
375 u_addr
= PT_MQ
* wordsize
;
377 if (regno
== tdep
->ppc_ps_regnum
)
378 u_addr
= PT_MSR
* wordsize
;
379 if (regno
== PPC_ORIG_R3_REGNUM
)
380 u_addr
= PT_ORIG_R3
* wordsize
;
381 if (regno
== PPC_TRAP_REGNUM
)
382 u_addr
= PT_TRAP
* wordsize
;
383 if (tdep
->ppc_fpscr_regnum
>= 0
384 && regno
== tdep
->ppc_fpscr_regnum
)
386 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
387 kernel headers incorrectly contained the 32-bit definition of
388 PT_FPSCR. For the 32-bit definition, floating-point
389 registers occupy two 32-bit "slots", and the FPSCR lives in
390 the second half of such a slot-pair (hence +1). For 64-bit,
391 the FPSCR instead occupies the full 64-bit 2-word-slot and
392 hence no adjustment is necessary. Hack around this. */
393 if (wordsize
== 8 && PT_FPSCR
== (48 + 32 + 1))
394 u_addr
= (48 + 32) * wordsize
;
395 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
396 slot and not just its second word. The PT_FPSCR supplied when
397 GDB is compiled as a 32-bit app doesn't reflect this. */
398 else if (wordsize
== 4 && register_size (gdbarch
, regno
) == 8
399 && PT_FPSCR
== (48 + 2*32 + 1))
400 u_addr
= (48 + 2*32) * wordsize
;
402 u_addr
= PT_FPSCR
* wordsize
;
407 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
408 registers set mechanism, as opposed to the interface for all the
409 other registers, that stores/fetches each register individually. */
411 fetch_vsx_register (struct regcache
*regcache
, int tid
, int regno
)
414 gdb_vsxregset_t regs
;
415 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
416 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
417 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
419 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
424 have_ptrace_getsetvsxregs
= 0;
427 perror_with_name (_("Unable to fetch VSX register"));
430 regcache_raw_supply (regcache
, regno
,
431 regs
+ (regno
- tdep
->ppc_vsr0_upper_regnum
)
435 /* The Linux kernel ptrace interface for AltiVec registers uses the
436 registers set mechanism, as opposed to the interface for all the
437 other registers, that stores/fetches each register individually. */
439 fetch_altivec_register (struct regcache
*regcache
, int tid
, int regno
)
444 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
445 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
446 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
448 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
453 have_ptrace_getvrregs
= 0;
456 perror_with_name (_("Unable to fetch AltiVec register"));
459 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
460 long on the hardware. We deal only with the lower 4 bytes of the
461 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
462 there is no need to define an offset for it. */
463 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
464 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
466 regcache_raw_supply (regcache
, regno
,
468 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
471 /* Fetch the top 32 bits of TID's general-purpose registers and the
472 SPE-specific registers, and place the results in EVRREGSET. If we
473 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
476 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
477 PTRACE_SETEVRREGS requests are supported is isolated here, and in
478 set_spe_registers. */
480 get_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
482 if (have_ptrace_getsetevrregs
)
484 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, evrregset
) >= 0)
488 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
489 we just return zeros. */
491 have_ptrace_getsetevrregs
= 0;
493 /* Anything else needs to be reported. */
494 perror_with_name (_("Unable to fetch SPE registers"));
498 memset (evrregset
, 0, sizeof (*evrregset
));
501 /* Supply values from TID for SPE-specific raw registers: the upper
502 halves of the GPRs, the accumulator, and the spefscr. REGNO must
503 be the number of an upper half register, acc, spefscr, or -1 to
504 supply the values of all registers. */
506 fetch_spe_register (struct regcache
*regcache
, int tid
, int regno
)
508 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
510 struct gdb_evrregset_t evrregs
;
512 gdb_assert (sizeof (evrregs
.evr
[0])
513 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
514 gdb_assert (sizeof (evrregs
.acc
)
515 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
516 gdb_assert (sizeof (evrregs
.spefscr
)
517 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
519 get_spe_registers (tid
, &evrregs
);
525 for (i
= 0; i
< ppc_num_gprs
; i
++)
526 regcache_raw_supply (regcache
, tdep
->ppc_ev0_upper_regnum
+ i
,
529 else if (tdep
->ppc_ev0_upper_regnum
<= regno
530 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
531 regcache_raw_supply (regcache
, regno
,
532 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
535 || regno
== tdep
->ppc_acc_regnum
)
536 regcache_raw_supply (regcache
, tdep
->ppc_acc_regnum
, &evrregs
.acc
);
539 || regno
== tdep
->ppc_spefscr_regnum
)
540 regcache_raw_supply (regcache
, tdep
->ppc_spefscr_regnum
,
545 fetch_register (struct regcache
*regcache
, int tid
, int regno
)
547 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
548 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
549 /* This isn't really an address. But ptrace thinks of it as one. */
550 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
551 int bytes_transferred
;
552 unsigned int offset
; /* Offset of registers within the u area. */
553 gdb_byte buf
[MAX_REGISTER_SIZE
];
555 if (altivec_register_p (gdbarch
, regno
))
557 /* If this is the first time through, or if it is not the first
558 time through, and we have comfirmed that there is kernel
559 support for such a ptrace request, then go and fetch the
561 if (have_ptrace_getvrregs
)
563 fetch_altivec_register (regcache
, tid
, regno
);
566 /* If we have discovered that there is no ptrace support for
567 AltiVec registers, fall through and return zeroes, because
568 regaddr will be -1 in this case. */
570 if (vsx_register_p (gdbarch
, regno
))
572 if (have_ptrace_getsetvsxregs
)
574 fetch_vsx_register (regcache
, tid
, regno
);
578 else if (spe_register_p (gdbarch
, regno
))
580 fetch_spe_register (regcache
, tid
, regno
);
586 memset (buf
, '\0', register_size (gdbarch
, regno
)); /* Supply zeroes */
587 regcache_raw_supply (regcache
, regno
, buf
);
591 /* Read the raw register using sizeof(long) sized chunks. On a
592 32-bit platform, 64-bit floating-point registers will require two
594 for (bytes_transferred
= 0;
595 bytes_transferred
< register_size (gdbarch
, regno
);
596 bytes_transferred
+= sizeof (long))
601 l
= ptrace (PTRACE_PEEKUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, 0);
602 regaddr
+= sizeof (long);
606 xsnprintf (message
, sizeof (message
), "reading register %s (#%d)",
607 gdbarch_register_name (gdbarch
, regno
), regno
);
608 perror_with_name (message
);
610 memcpy (&buf
[bytes_transferred
], &l
, sizeof (l
));
613 /* Now supply the register. Keep in mind that the regcache's idea
614 of the register's size may not be a multiple of sizeof
616 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
618 /* Little-endian values are always found at the left end of the
619 bytes transferred. */
620 regcache_raw_supply (regcache
, regno
, buf
);
622 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
624 /* Big-endian values are found at the right end of the bytes
626 size_t padding
= (bytes_transferred
- register_size (gdbarch
, regno
));
627 regcache_raw_supply (regcache
, regno
, buf
+ padding
);
630 internal_error (__FILE__
, __LINE__
,
631 _("fetch_register: unexpected byte order: %d"),
632 gdbarch_byte_order (gdbarch
));
636 supply_vsxregset (struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
639 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
640 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
641 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
643 for (i
= 0; i
< ppc_num_vshrs
; i
++)
645 regcache_raw_supply (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
646 *vsxregsetp
+ i
* vsxregsize
);
651 supply_vrregset (struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
654 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
655 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
656 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
657 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
658 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
660 for (i
= 0; i
< num_of_vrregs
; i
++)
662 /* The last 2 registers of this set are only 32 bit long, not
663 128. However an offset is necessary only for VSCR because it
664 occupies a whole vector, while VRSAVE occupies a full 4 bytes
666 if (i
== (num_of_vrregs
- 2))
667 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
668 *vrregsetp
+ i
* vrregsize
+ offset
);
670 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
671 *vrregsetp
+ i
* vrregsize
);
676 fetch_vsx_registers (struct regcache
*regcache
, int tid
)
679 gdb_vsxregset_t regs
;
681 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
686 have_ptrace_getsetvsxregs
= 0;
689 perror_with_name (_("Unable to fetch VSX registers"));
691 supply_vsxregset (regcache
, ®s
);
695 fetch_altivec_registers (struct regcache
*regcache
, int tid
)
700 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
705 have_ptrace_getvrregs
= 0;
708 perror_with_name (_("Unable to fetch AltiVec registers"));
710 supply_vrregset (regcache
, ®s
);
713 /* This function actually issues the request to ptrace, telling
714 it to get all general-purpose registers and put them into the
717 If the ptrace request does not exist, this function returns 0
718 and properly sets the have_ptrace_* flag. If the request fails,
719 this function calls perror_with_name. Otherwise, if the request
720 succeeds, then the regcache gets filled and 1 is returned. */
722 fetch_all_gp_regs (struct regcache
*regcache
, int tid
)
724 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
725 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
726 gdb_gregset_t gregset
;
728 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
732 have_ptrace_getsetregs
= 0;
735 perror_with_name (_("Couldn't get general-purpose registers."));
738 supply_gregset (regcache
, (const gdb_gregset_t
*) &gregset
);
743 /* This is a wrapper for the fetch_all_gp_regs function. It is
744 responsible for verifying if this target has the ptrace request
745 that can be used to fetch all general-purpose registers at one
746 shot. If it doesn't, then we should fetch them using the
747 old-fashioned way, which is to iterate over the registers and
748 request them one by one. */
750 fetch_gp_regs (struct regcache
*regcache
, int tid
)
752 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
753 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
756 if (have_ptrace_getsetregs
)
757 if (fetch_all_gp_regs (regcache
, tid
))
760 /* If we've hit this point, it doesn't really matter which
761 architecture we are using. We just need to read the
762 registers in the "old-fashioned way". */
763 for (i
= 0; i
< ppc_num_gprs
; i
++)
764 fetch_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
767 /* This function actually issues the request to ptrace, telling
768 it to get all floating-point registers and put them into the
771 If the ptrace request does not exist, this function returns 0
772 and properly sets the have_ptrace_* flag. If the request fails,
773 this function calls perror_with_name. Otherwise, if the request
774 succeeds, then the regcache gets filled and 1 is returned. */
776 fetch_all_fp_regs (struct regcache
*regcache
, int tid
)
778 gdb_fpregset_t fpregs
;
780 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
784 have_ptrace_getsetfpregs
= 0;
787 perror_with_name (_("Couldn't get floating-point registers."));
790 supply_fpregset (regcache
, (const gdb_fpregset_t
*) &fpregs
);
795 /* This is a wrapper for the fetch_all_fp_regs function. It is
796 responsible for verifying if this target has the ptrace request
797 that can be used to fetch all floating-point registers at one
798 shot. If it doesn't, then we should fetch them using the
799 old-fashioned way, which is to iterate over the registers and
800 request them one by one. */
802 fetch_fp_regs (struct regcache
*regcache
, int tid
)
804 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
805 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
808 if (have_ptrace_getsetfpregs
)
809 if (fetch_all_fp_regs (regcache
, tid
))
812 /* If we've hit this point, it doesn't really matter which
813 architecture we are using. We just need to read the
814 registers in the "old-fashioned way". */
815 for (i
= 0; i
< ppc_num_fprs
; i
++)
816 fetch_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
820 fetch_ppc_registers (struct regcache
*regcache
, int tid
)
823 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
824 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
826 fetch_gp_regs (regcache
, tid
);
827 if (tdep
->ppc_fp0_regnum
>= 0)
828 fetch_fp_regs (regcache
, tid
);
829 fetch_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
830 if (tdep
->ppc_ps_regnum
!= -1)
831 fetch_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
832 if (tdep
->ppc_cr_regnum
!= -1)
833 fetch_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
834 if (tdep
->ppc_lr_regnum
!= -1)
835 fetch_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
836 if (tdep
->ppc_ctr_regnum
!= -1)
837 fetch_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
838 if (tdep
->ppc_xer_regnum
!= -1)
839 fetch_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
840 if (tdep
->ppc_mq_regnum
!= -1)
841 fetch_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
842 if (ppc_linux_trap_reg_p (gdbarch
))
844 fetch_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
845 fetch_register (regcache
, tid
, PPC_TRAP_REGNUM
);
847 if (tdep
->ppc_fpscr_regnum
!= -1)
848 fetch_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
849 if (have_ptrace_getvrregs
)
850 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
851 fetch_altivec_registers (regcache
, tid
);
852 if (have_ptrace_getsetvsxregs
)
853 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
854 fetch_vsx_registers (regcache
, tid
);
855 if (tdep
->ppc_ev0_upper_regnum
>= 0)
856 fetch_spe_register (regcache
, tid
, -1);
859 /* Fetch registers from the child process. Fetch all registers if
860 regno == -1, otherwise fetch all general registers or all floating
861 point registers depending upon the value of regno. */
863 ppc_linux_fetch_inferior_registers (struct target_ops
*ops
,
864 struct regcache
*regcache
, int regno
)
866 /* Overload thread id onto process id. */
867 int tid
= ptid_get_lwp (inferior_ptid
);
869 /* No thread id, just use process id. */
871 tid
= ptid_get_pid (inferior_ptid
);
874 fetch_ppc_registers (regcache
, tid
);
876 fetch_register (regcache
, tid
, regno
);
879 /* Store one VSX register. */
881 store_vsx_register (const struct regcache
*regcache
, int tid
, int regno
)
884 gdb_vsxregset_t regs
;
885 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
886 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
887 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
889 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
894 have_ptrace_getsetvsxregs
= 0;
897 perror_with_name (_("Unable to fetch VSX register"));
900 regcache_raw_collect (regcache
, regno
, regs
+
901 (regno
- tdep
->ppc_vsr0_upper_regnum
) * vsxregsize
);
903 ret
= ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
);
905 perror_with_name (_("Unable to store VSX register"));
908 /* Store one register. */
910 store_altivec_register (const struct regcache
*regcache
, int tid
, int regno
)
915 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
916 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
917 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
919 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
924 have_ptrace_getvrregs
= 0;
927 perror_with_name (_("Unable to fetch AltiVec register"));
930 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
931 long on the hardware. */
932 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
933 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
935 regcache_raw_collect (regcache
, regno
,
937 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
939 ret
= ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
);
941 perror_with_name (_("Unable to store AltiVec register"));
944 /* Assuming TID referrs to an SPE process, set the top halves of TID's
945 general-purpose registers and its SPE-specific registers to the
946 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
949 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
950 PTRACE_SETEVRREGS requests are supported is isolated here, and in
951 get_spe_registers. */
953 set_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
955 if (have_ptrace_getsetevrregs
)
957 if (ptrace (PTRACE_SETEVRREGS
, tid
, 0, evrregset
) >= 0)
961 /* EIO means that the PTRACE_SETEVRREGS request isn't
962 supported; we fail silently, and don't try the call
965 have_ptrace_getsetevrregs
= 0;
967 /* Anything else needs to be reported. */
968 perror_with_name (_("Unable to set SPE registers"));
973 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
974 If REGNO is -1, write the values of all the SPE-specific
977 store_spe_register (const struct regcache
*regcache
, int tid
, int regno
)
979 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
980 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
981 struct gdb_evrregset_t evrregs
;
983 gdb_assert (sizeof (evrregs
.evr
[0])
984 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
985 gdb_assert (sizeof (evrregs
.acc
)
986 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
987 gdb_assert (sizeof (evrregs
.spefscr
)
988 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
991 /* Since we're going to write out every register, the code below
992 should store to every field of evrregs; if that doesn't happen,
993 make it obvious by initializing it with suspicious values. */
994 memset (&evrregs
, 42, sizeof (evrregs
));
996 /* We can only read and write the entire EVR register set at a
997 time, so to write just a single register, we do a
998 read-modify-write maneuver. */
999 get_spe_registers (tid
, &evrregs
);
1005 for (i
= 0; i
< ppc_num_gprs
; i
++)
1006 regcache_raw_collect (regcache
,
1007 tdep
->ppc_ev0_upper_regnum
+ i
,
1010 else if (tdep
->ppc_ev0_upper_regnum
<= regno
1011 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1012 regcache_raw_collect (regcache
, regno
,
1013 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
1016 || regno
== tdep
->ppc_acc_regnum
)
1017 regcache_raw_collect (regcache
,
1018 tdep
->ppc_acc_regnum
,
1022 || regno
== tdep
->ppc_spefscr_regnum
)
1023 regcache_raw_collect (regcache
,
1024 tdep
->ppc_spefscr_regnum
,
1027 /* Write back the modified register set. */
1028 set_spe_registers (tid
, &evrregs
);
1032 store_register (const struct regcache
*regcache
, int tid
, int regno
)
1034 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1035 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1036 /* This isn't really an address. But ptrace thinks of it as one. */
1037 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
1039 size_t bytes_to_transfer
;
1040 gdb_byte buf
[MAX_REGISTER_SIZE
];
1042 if (altivec_register_p (gdbarch
, regno
))
1044 store_altivec_register (regcache
, tid
, regno
);
1047 if (vsx_register_p (gdbarch
, regno
))
1049 store_vsx_register (regcache
, tid
, regno
);
1052 else if (spe_register_p (gdbarch
, regno
))
1054 store_spe_register (regcache
, tid
, regno
);
1061 /* First collect the register. Keep in mind that the regcache's
1062 idea of the register's size may not be a multiple of sizeof
1064 memset (buf
, 0, sizeof buf
);
1065 bytes_to_transfer
= align_up (register_size (gdbarch
, regno
), sizeof (long));
1066 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1068 /* Little-endian values always sit at the left end of the buffer. */
1069 regcache_raw_collect (regcache
, regno
, buf
);
1071 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1073 /* Big-endian values sit at the right end of the buffer. */
1074 size_t padding
= (bytes_to_transfer
- register_size (gdbarch
, regno
));
1075 regcache_raw_collect (regcache
, regno
, buf
+ padding
);
1078 for (i
= 0; i
< bytes_to_transfer
; i
+= sizeof (long))
1082 memcpy (&l
, &buf
[i
], sizeof (l
));
1084 ptrace (PTRACE_POKEUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, l
);
1085 regaddr
+= sizeof (long);
1088 && (regno
== tdep
->ppc_fpscr_regnum
1089 || regno
== PPC_ORIG_R3_REGNUM
1090 || regno
== PPC_TRAP_REGNUM
))
1092 /* Some older kernel versions don't allow fpscr, orig_r3
1093 or trap to be written. */
1100 xsnprintf (message
, sizeof (message
), "writing register %s (#%d)",
1101 gdbarch_register_name (gdbarch
, regno
), regno
);
1102 perror_with_name (message
);
1108 fill_vsxregset (const struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
1111 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1112 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1113 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
1115 for (i
= 0; i
< ppc_num_vshrs
; i
++)
1116 regcache_raw_collect (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
1117 *vsxregsetp
+ i
* vsxregsize
);
1121 fill_vrregset (const struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
1124 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1125 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1126 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
1127 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
1128 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
1130 for (i
= 0; i
< num_of_vrregs
; i
++)
1132 /* The last 2 registers of this set are only 32 bit long, not
1133 128, but only VSCR is fetched as a 16 bytes quantity. */
1134 if (i
== (num_of_vrregs
- 2))
1135 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1136 *vrregsetp
+ i
* vrregsize
+ offset
);
1138 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1139 *vrregsetp
+ i
* vrregsize
);
1144 store_vsx_registers (const struct regcache
*regcache
, int tid
)
1147 gdb_vsxregset_t regs
;
1149 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
1154 have_ptrace_getsetvsxregs
= 0;
1157 perror_with_name (_("Couldn't get VSX registers"));
1160 fill_vsxregset (regcache
, ®s
);
1162 if (ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
) < 0)
1163 perror_with_name (_("Couldn't write VSX registers"));
1167 store_altivec_registers (const struct regcache
*regcache
, int tid
)
1170 gdb_vrregset_t regs
;
1172 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
1177 have_ptrace_getvrregs
= 0;
1180 perror_with_name (_("Couldn't get AltiVec registers"));
1183 fill_vrregset (regcache
, ®s
);
1185 if (ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
) < 0)
1186 perror_with_name (_("Couldn't write AltiVec registers"));
1189 /* This function actually issues the request to ptrace, telling
1190 it to store all general-purpose registers present in the specified
1193 If the ptrace request does not exist, this function returns 0
1194 and properly sets the have_ptrace_* flag. If the request fails,
1195 this function calls perror_with_name. Otherwise, if the request
1196 succeeds, then the regcache is stored and 1 is returned. */
1198 store_all_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1200 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1202 gdb_gregset_t gregset
;
1204 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
1208 have_ptrace_getsetregs
= 0;
1211 perror_with_name (_("Couldn't get general-purpose registers."));
1214 fill_gregset (regcache
, &gregset
, regno
);
1216 if (ptrace (PTRACE_SETREGS
, tid
, 0, (void *) &gregset
) < 0)
1220 have_ptrace_getsetregs
= 0;
1223 perror_with_name (_("Couldn't set general-purpose registers."));
1229 /* This is a wrapper for the store_all_gp_regs function. It is
1230 responsible for verifying if this target has the ptrace request
1231 that can be used to store all general-purpose registers at one
1232 shot. If it doesn't, then we should store them using the
1233 old-fashioned way, which is to iterate over the registers and
1234 store them one by one. */
1236 store_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1238 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1242 if (have_ptrace_getsetregs
)
1243 if (store_all_gp_regs (regcache
, tid
, regno
))
1246 /* If we hit this point, it doesn't really matter which
1247 architecture we are using. We just need to store the
1248 registers in the "old-fashioned way". */
1249 for (i
= 0; i
< ppc_num_gprs
; i
++)
1250 store_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
1253 /* This function actually issues the request to ptrace, telling
1254 it to store all floating-point registers present in the specified
1257 If the ptrace request does not exist, this function returns 0
1258 and properly sets the have_ptrace_* flag. If the request fails,
1259 this function calls perror_with_name. Otherwise, if the request
1260 succeeds, then the regcache is stored and 1 is returned. */
1262 store_all_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1264 gdb_fpregset_t fpregs
;
1266 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1270 have_ptrace_getsetfpregs
= 0;
1273 perror_with_name (_("Couldn't get floating-point registers."));
1276 fill_fpregset (regcache
, &fpregs
, regno
);
1278 if (ptrace (PTRACE_SETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1282 have_ptrace_getsetfpregs
= 0;
1285 perror_with_name (_("Couldn't set floating-point registers."));
1291 /* This is a wrapper for the store_all_fp_regs function. It is
1292 responsible for verifying if this target has the ptrace request
1293 that can be used to store all floating-point registers at one
1294 shot. If it doesn't, then we should store them using the
1295 old-fashioned way, which is to iterate over the registers and
1296 store them one by one. */
1298 store_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1300 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1301 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1304 if (have_ptrace_getsetfpregs
)
1305 if (store_all_fp_regs (regcache
, tid
, regno
))
1308 /* If we hit this point, it doesn't really matter which
1309 architecture we are using. We just need to store the
1310 registers in the "old-fashioned way". */
1311 for (i
= 0; i
< ppc_num_fprs
; i
++)
1312 store_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
1316 store_ppc_registers (const struct regcache
*regcache
, int tid
)
1319 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1320 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1322 store_gp_regs (regcache
, tid
, -1);
1323 if (tdep
->ppc_fp0_regnum
>= 0)
1324 store_fp_regs (regcache
, tid
, -1);
1325 store_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
1326 if (tdep
->ppc_ps_regnum
!= -1)
1327 store_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
1328 if (tdep
->ppc_cr_regnum
!= -1)
1329 store_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
1330 if (tdep
->ppc_lr_regnum
!= -1)
1331 store_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
1332 if (tdep
->ppc_ctr_regnum
!= -1)
1333 store_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
1334 if (tdep
->ppc_xer_regnum
!= -1)
1335 store_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
1336 if (tdep
->ppc_mq_regnum
!= -1)
1337 store_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
1338 if (tdep
->ppc_fpscr_regnum
!= -1)
1339 store_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
1340 if (ppc_linux_trap_reg_p (gdbarch
))
1342 store_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
1343 store_register (regcache
, tid
, PPC_TRAP_REGNUM
);
1345 if (have_ptrace_getvrregs
)
1346 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
1347 store_altivec_registers (regcache
, tid
);
1348 if (have_ptrace_getsetvsxregs
)
1349 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
1350 store_vsx_registers (regcache
, tid
);
1351 if (tdep
->ppc_ev0_upper_regnum
>= 0)
1352 store_spe_register (regcache
, tid
, -1);
1355 /* Fetch the AT_HWCAP entry from the aux vector. */
1356 static unsigned long
1357 ppc_linux_get_hwcap (void)
1361 if (target_auxv_search (¤t_target
, AT_HWCAP
, &field
))
1362 return (unsigned long) field
;
1367 /* The cached DABR value, to install in new threads.
1368 This variable is used when the PowerPC HWDEBUG ptrace
1369 interface is not available. */
1370 static long saved_dabr_value
;
1372 /* Global structure that will store information about the available
1373 features provided by the PowerPC HWDEBUG ptrace interface. */
1374 static struct ppc_debug_info hwdebug_info
;
1376 /* Global variable that holds the maximum number of slots that the
1377 kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1379 static size_t max_slots_number
= 0;
1381 struct hw_break_tuple
1384 struct ppc_hw_breakpoint
*hw_break
;
1387 /* This is an internal VEC created to store information about *points inserted
1388 for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1390 typedef struct thread_points
1392 /* The TID to which this *point relates. */
1394 /* Information about the *point, such as its address, type, etc.
1396 Each element inside this vector corresponds to a hardware
1397 breakpoint or watchpoint in the thread represented by TID. The maximum
1398 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1399 the tuple is NULL, then the position in the vector is free. */
1400 struct hw_break_tuple
*hw_breaks
;
1402 DEF_VEC_P (thread_points_p
);
1404 VEC(thread_points_p
) *ppc_threads
= NULL
;
1406 /* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1408 #define PPC_DEBUG_CURRENT_VERSION 1
1410 /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
1412 have_ptrace_hwdebug_interface (void)
1414 static int have_ptrace_hwdebug_interface
= -1;
1416 if (have_ptrace_hwdebug_interface
== -1)
1420 tid
= ptid_get_lwp (inferior_ptid
);
1422 tid
= ptid_get_pid (inferior_ptid
);
1424 /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1425 if (ptrace (PPC_PTRACE_GETHWDBGINFO
, tid
, 0, &hwdebug_info
) >= 0)
1427 /* Check whether PowerPC HWDEBUG ptrace interface is functional and
1428 provides any supported feature. */
1429 if (hwdebug_info
.features
!= 0)
1431 have_ptrace_hwdebug_interface
= 1;
1432 max_slots_number
= hwdebug_info
.num_instruction_bps
1433 + hwdebug_info
.num_data_bps
1434 + hwdebug_info
.num_condition_regs
;
1435 return have_ptrace_hwdebug_interface
;
1438 /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1439 have_ptrace_hwdebug_interface
= 0;
1440 memset (&hwdebug_info
, 0, sizeof (struct ppc_debug_info
));
1443 return have_ptrace_hwdebug_interface
;
1447 ppc_linux_can_use_hw_breakpoint (struct target_ops
*self
,
1448 int type
, int cnt
, int ot
)
1450 int total_hw_wp
, total_hw_bp
;
1452 if (have_ptrace_hwdebug_interface ())
1454 /* When PowerPC HWDEBUG ptrace interface is available, the number of
1455 available hardware watchpoints and breakpoints is stored at the
1456 hwdebug_info struct. */
1457 total_hw_bp
= hwdebug_info
.num_instruction_bps
;
1458 total_hw_wp
= hwdebug_info
.num_data_bps
;
1462 /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1463 consider having 1 hardware watchpoint and no hardware breakpoints. */
1468 if (type
== bp_hardware_watchpoint
|| type
== bp_read_watchpoint
1469 || type
== bp_access_watchpoint
|| type
== bp_watchpoint
)
1471 if (cnt
+ ot
> total_hw_wp
)
1474 else if (type
== bp_hardware_breakpoint
)
1476 if (cnt
> total_hw_bp
)
1480 if (!have_ptrace_hwdebug_interface ())
1483 ptid_t ptid
= inferior_ptid
;
1485 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1486 and whether the target has DABR. If either answer is no, the
1487 ptrace call will return -1. Fail in that case. */
1488 tid
= ptid_get_lwp (ptid
);
1490 tid
= ptid_get_pid (ptid
);
1492 if (ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, 0) == -1)
1500 ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
1502 /* Handle sub-8-byte quantities. */
1506 /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1507 restrictions for watchpoints in the processors. In that case, we use that
1508 information to determine the hardcoded watchable region for
1510 if (have_ptrace_hwdebug_interface ())
1513 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1514 watchpoints and can watch any access within an arbitrary memory
1515 region. This is useful to watch arrays and structs, for instance. It
1516 takes two hardware watchpoints though. */
1518 && hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
1519 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1521 /* Check if the processor provides DAWR interface. */
1522 if (hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_DAWR
)
1523 /* DAWR interface allows to watch up to 512 byte wide ranges which
1524 can't cross a 512 byte boundary. */
1527 region_size
= hwdebug_info
.data_bp_alignment
;
1528 /* Server processors provide one hardware watchpoint and addr+len should
1529 fall in the watchable region provided by the ptrace interface. */
1531 && (addr
+ len
> (addr
& ~(region_size
- 1)) + region_size
))
1534 /* addr+len must fall in the 8 byte watchable region for DABR-based
1535 processors (i.e., server processors). Without the new PowerPC HWDEBUG
1536 ptrace interface, DAC-based processors (i.e., embedded processors) will
1537 use addresses aligned to 4-bytes due to the way the read/write flags are
1538 passed in the old ptrace interface. */
1539 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1540 && (addr
+ len
) > (addr
& ~3) + 4)
1541 || (addr
+ len
) > (addr
& ~7) + 8)
1547 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1549 hwdebug_point_cmp (struct ppc_hw_breakpoint
*a
, struct ppc_hw_breakpoint
*b
)
1551 return (a
->trigger_type
== b
->trigger_type
1552 && a
->addr_mode
== b
->addr_mode
1553 && a
->condition_mode
== b
->condition_mode
1554 && a
->addr
== b
->addr
1555 && a
->addr2
== b
->addr2
1556 && a
->condition_value
== b
->condition_value
);
1559 /* This function can be used to retrieve a thread_points by the TID of the
1560 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1561 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1562 provided TID will be created and returned. */
1563 static struct thread_points
*
1564 hwdebug_find_thread_points_by_tid (int tid
, int alloc_new
)
1567 struct thread_points
*t
;
1569 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, t
); i
++)
1575 /* Do we need to allocate a new point_item
1576 if the wanted one does not exist? */
1579 t
= xmalloc (sizeof (struct thread_points
));
1581 = xzalloc (max_slots_number
* sizeof (struct hw_break_tuple
));
1583 VEC_safe_push (thread_points_p
, ppc_threads
, t
);
1589 /* This function is a generic wrapper that is responsible for inserting a
1590 *point (i.e., calling `ptrace' in order to issue the request to the
1591 kernel) and registering it internally in GDB. */
1593 hwdebug_insert_point (struct ppc_hw_breakpoint
*b
, int tid
)
1597 struct ppc_hw_breakpoint
*p
= xmalloc (sizeof (struct ppc_hw_breakpoint
));
1598 struct hw_break_tuple
*hw_breaks
;
1599 struct cleanup
*c
= make_cleanup (xfree
, p
);
1600 struct thread_points
*t
;
1601 struct hw_break_tuple
*tuple
;
1603 memcpy (p
, b
, sizeof (struct ppc_hw_breakpoint
));
1606 slot
= ptrace (PPC_PTRACE_SETHWDEBUG
, tid
, 0, p
);
1608 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1610 /* Everything went fine, so we have to register this *point. */
1611 t
= hwdebug_find_thread_points_by_tid (tid
, 1);
1612 gdb_assert (t
!= NULL
);
1613 hw_breaks
= t
->hw_breaks
;
1615 /* Find a free element in the hw_breaks vector. */
1616 for (i
= 0; i
< max_slots_number
; i
++)
1617 if (hw_breaks
[i
].hw_break
== NULL
)
1619 hw_breaks
[i
].slot
= slot
;
1620 hw_breaks
[i
].hw_break
= p
;
1624 gdb_assert (i
!= max_slots_number
);
1626 discard_cleanups (c
);
1629 /* This function is a generic wrapper that is responsible for removing a
1630 *point (i.e., calling `ptrace' in order to issue the request to the
1631 kernel), and unregistering it internally at GDB. */
1633 hwdebug_remove_point (struct ppc_hw_breakpoint
*b
, int tid
)
1636 struct hw_break_tuple
*hw_breaks
;
1637 struct thread_points
*t
;
1639 t
= hwdebug_find_thread_points_by_tid (tid
, 0);
1640 gdb_assert (t
!= NULL
);
1641 hw_breaks
= t
->hw_breaks
;
1643 for (i
= 0; i
< max_slots_number
; i
++)
1644 if (hw_breaks
[i
].hw_break
&& hwdebug_point_cmp (hw_breaks
[i
].hw_break
, b
))
1647 gdb_assert (i
!= max_slots_number
);
1649 /* We have to ignore ENOENT errors because the kernel implements hardware
1650 breakpoints/watchpoints as "one-shot", that is, they are automatically
1651 deleted when hit. */
1653 if (ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
) < 0)
1654 if (errno
!= ENOENT
)
1655 perror_with_name (_("Unexpected error deleting "
1656 "breakpoint or watchpoint"));
1658 xfree (hw_breaks
[i
].hw_break
);
1659 hw_breaks
[i
].hw_break
= NULL
;
1662 /* Return the number of registers needed for a ranged breakpoint. */
1665 ppc_linux_ranged_break_num_registers (struct target_ops
*target
)
1667 return ((have_ptrace_hwdebug_interface ()
1668 && hwdebug_info
.features
& PPC_DEBUG_FEATURE_INSN_BP_RANGE
)?
1672 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1673 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1676 ppc_linux_insert_hw_breakpoint (struct gdbarch
*gdbarch
,
1677 struct bp_target_info
*bp_tgt
)
1679 struct lwp_info
*lp
;
1680 struct ppc_hw_breakpoint p
;
1682 if (!have_ptrace_hwdebug_interface ())
1685 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1686 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1687 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1688 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1689 p
.condition_value
= 0;
1693 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1695 /* The breakpoint will trigger if the address of the instruction is
1696 within the defined range, as follows: p.addr <= address < p.addr2. */
1697 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1701 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1706 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
1712 ppc_linux_remove_hw_breakpoint (struct gdbarch
*gdbarch
,
1713 struct bp_target_info
*bp_tgt
)
1715 struct lwp_info
*lp
;
1716 struct ppc_hw_breakpoint p
;
1718 if (!have_ptrace_hwdebug_interface ())
1721 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1722 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1723 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1724 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1725 p
.condition_value
= 0;
1729 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1731 /* The breakpoint will trigger if the address of the instruction is within
1732 the defined range, as follows: p.addr <= address < p.addr2. */
1733 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1737 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1742 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
1748 get_trigger_type (int rw
)
1753 t
= PPC_BREAKPOINT_TRIGGER_READ
;
1754 else if (rw
== hw_write
)
1755 t
= PPC_BREAKPOINT_TRIGGER_WRITE
;
1757 t
= PPC_BREAKPOINT_TRIGGER_READ
| PPC_BREAKPOINT_TRIGGER_WRITE
;
1762 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1763 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1764 or hw_access for an access watchpoint. Returns 0 on success and throws
1765 an error on failure. */
1768 ppc_linux_insert_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1769 CORE_ADDR mask
, int rw
)
1771 struct lwp_info
*lp
;
1772 struct ppc_hw_breakpoint p
;
1774 gdb_assert (have_ptrace_hwdebug_interface ());
1776 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1777 p
.trigger_type
= get_trigger_type (rw
);
1778 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1779 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1782 p
.condition_value
= 0;
1785 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
1790 /* Remove a masked watchpoint at ADDR with the mask MASK.
1791 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1792 or hw_access for an access watchpoint. Returns 0 on success and throws
1793 an error on failure. */
1796 ppc_linux_remove_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1797 CORE_ADDR mask
, int rw
)
1799 struct lwp_info
*lp
;
1800 struct ppc_hw_breakpoint p
;
1802 gdb_assert (have_ptrace_hwdebug_interface ());
1804 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1805 p
.trigger_type
= get_trigger_type (rw
);
1806 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1807 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1810 p
.condition_value
= 0;
1813 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
1818 /* Check whether we have at least one free DVC register. */
1820 can_use_watchpoint_cond_accel (void)
1822 struct thread_points
*p
;
1823 int tid
= ptid_get_lwp (inferior_ptid
);
1824 int cnt
= hwdebug_info
.num_condition_regs
, i
;
1825 CORE_ADDR tmp_value
;
1827 if (!have_ptrace_hwdebug_interface () || cnt
== 0)
1830 p
= hwdebug_find_thread_points_by_tid (tid
, 0);
1834 for (i
= 0; i
< max_slots_number
; i
++)
1835 if (p
->hw_breaks
[i
].hw_break
!= NULL
1836 && (p
->hw_breaks
[i
].hw_break
->condition_mode
1837 != PPC_BREAKPOINT_CONDITION_NONE
))
1840 /* There are no available slots now. */
1848 /* Calculate the enable bits and the contents of the Data Value Compare
1849 debug register present in BookE processors.
1851 ADDR is the address to be watched, LEN is the length of watched data
1852 and DATA_VALUE is the value which will trigger the watchpoint.
1853 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1854 CONDITION_VALUE will hold the value which should be put in the
1857 calculate_dvc (CORE_ADDR addr
, int len
, CORE_ADDR data_value
,
1858 uint32_t *condition_mode
, uint64_t *condition_value
)
1860 int i
, num_byte_enable
, align_offset
, num_bytes_off_dvc
,
1861 rightmost_enabled_byte
;
1862 CORE_ADDR addr_end_data
, addr_end_dvc
;
1864 /* The DVC register compares bytes within fixed-length windows which
1865 are word-aligned, with length equal to that of the DVC register.
1866 We need to calculate where our watch region is relative to that
1867 window and enable comparison of the bytes which fall within it. */
1869 align_offset
= addr
% hwdebug_info
.sizeof_condition
;
1870 addr_end_data
= addr
+ len
;
1871 addr_end_dvc
= (addr
- align_offset
1872 + hwdebug_info
.sizeof_condition
);
1873 num_bytes_off_dvc
= (addr_end_data
> addr_end_dvc
)?
1874 addr_end_data
- addr_end_dvc
: 0;
1875 num_byte_enable
= len
- num_bytes_off_dvc
;
1876 /* Here, bytes are numbered from right to left. */
1877 rightmost_enabled_byte
= (addr_end_data
< addr_end_dvc
)?
1878 addr_end_dvc
- addr_end_data
: 0;
1880 *condition_mode
= PPC_BREAKPOINT_CONDITION_AND
;
1881 for (i
= 0; i
< num_byte_enable
; i
++)
1883 |= PPC_BREAKPOINT_CONDITION_BE (i
+ rightmost_enabled_byte
);
1885 /* Now we need to match the position within the DVC of the comparison
1886 value with where the watch region is relative to the window
1887 (i.e., the ALIGN_OFFSET). */
1889 *condition_value
= ((uint64_t) data_value
>> num_bytes_off_dvc
* 8
1890 << rightmost_enabled_byte
* 8);
1893 /* Return the number of memory locations that need to be accessed to
1894 evaluate the expression which generated the given value chain.
1895 Returns -1 if there's any register access involved, or if there are
1896 other kinds of values which are not acceptable in a condition
1897 expression (e.g., lval_computed or lval_internalvar). */
1899 num_memory_accesses (struct value
*v
)
1901 int found_memory_cnt
= 0;
1902 struct value
*head
= v
;
1904 /* The idea here is that evaluating an expression generates a series
1905 of values, one holding the value of every subexpression. (The
1906 expression a*b+c has five subexpressions: a, b, a*b, c, and
1907 a*b+c.) GDB's values hold almost enough information to establish
1908 the criteria given above --- they identify memory lvalues,
1909 register lvalues, computed values, etcetera. So we can evaluate
1910 the expression, and then scan the chain of values that leaves
1911 behind to determine the memory locations involved in the evaluation
1914 However, I don't think that the values returned by inferior
1915 function calls are special in any way. So this function may not
1916 notice that an expression contains an inferior function call.
1919 for (; v
; v
= value_next (v
))
1921 /* Constants and values from the history are fine. */
1922 if (VALUE_LVAL (v
) == not_lval
|| deprecated_value_modifiable (v
) == 0)
1924 else if (VALUE_LVAL (v
) == lval_memory
)
1926 /* A lazy memory lvalue is one that GDB never needed to fetch;
1927 we either just used its address (e.g., `a' in `a.b') or
1928 we never needed it at all (e.g., `a' in `a,b'). */
1929 if (!value_lazy (v
))
1932 /* Other kinds of values are not fine. */
1937 return found_memory_cnt
;
1940 /* Verifies whether the expression COND can be implemented using the
1941 DVC (Data Value Compare) register in BookE processors. The expression
1942 must test the watch value for equality with a constant expression.
1943 If the function returns 1, DATA_VALUE will contain the constant against
1944 which the watch value should be compared and LEN will contain the size
1947 check_condition (CORE_ADDR watch_addr
, struct expression
*cond
,
1948 CORE_ADDR
*data_value
, int *len
)
1950 int pc
= 1, num_accesses_left
, num_accesses_right
;
1951 struct value
*left_val
, *right_val
, *left_chain
, *right_chain
;
1953 if (cond
->elts
[0].opcode
!= BINOP_EQUAL
)
1956 fetch_subexp_value (cond
, &pc
, &left_val
, NULL
, &left_chain
, 0);
1957 num_accesses_left
= num_memory_accesses (left_chain
);
1959 if (left_val
== NULL
|| num_accesses_left
< 0)
1961 free_value_chain (left_chain
);
1966 fetch_subexp_value (cond
, &pc
, &right_val
, NULL
, &right_chain
, 0);
1967 num_accesses_right
= num_memory_accesses (right_chain
);
1969 if (right_val
== NULL
|| num_accesses_right
< 0)
1971 free_value_chain (left_chain
);
1972 free_value_chain (right_chain
);
1977 if (num_accesses_left
== 1 && num_accesses_right
== 0
1978 && VALUE_LVAL (left_val
) == lval_memory
1979 && value_address (left_val
) == watch_addr
)
1981 *data_value
= value_as_long (right_val
);
1983 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1984 the same type as the memory region referenced by LEFT_VAL. */
1985 *len
= TYPE_LENGTH (check_typedef (value_type (left_val
)));
1987 else if (num_accesses_left
== 0 && num_accesses_right
== 1
1988 && VALUE_LVAL (right_val
) == lval_memory
1989 && value_address (right_val
) == watch_addr
)
1991 *data_value
= value_as_long (left_val
);
1993 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1994 the same type as the memory region referenced by RIGHT_VAL. */
1995 *len
= TYPE_LENGTH (check_typedef (value_type (right_val
)));
1999 free_value_chain (left_chain
);
2000 free_value_chain (right_chain
);
2005 free_value_chain (left_chain
);
2006 free_value_chain (right_chain
);
2011 /* Return non-zero if the target is capable of using hardware to evaluate
2012 the condition expression, thus only triggering the watchpoint when it is
2015 ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr
, int len
, int rw
,
2016 struct expression
*cond
)
2018 CORE_ADDR data_value
;
2020 return (have_ptrace_hwdebug_interface ()
2021 && hwdebug_info
.num_condition_regs
> 0
2022 && check_condition (addr
, cond
, &data_value
, &len
));
2025 /* Set up P with the parameters necessary to request a watchpoint covering
2026 LEN bytes starting at ADDR and if possible with condition expression COND
2027 evaluated by hardware. INSERT tells if we are creating a request for
2028 inserting or removing the watchpoint. */
2031 create_watchpoint_request (struct ppc_hw_breakpoint
*p
, CORE_ADDR addr
,
2032 int len
, int rw
, struct expression
*cond
,
2036 || !(hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
))
2039 CORE_ADDR data_value
;
2041 use_condition
= (insert
? can_use_watchpoint_cond_accel ()
2042 : hwdebug_info
.num_condition_regs
> 0);
2043 if (cond
&& use_condition
&& check_condition (addr
, cond
,
2045 calculate_dvc (addr
, len
, data_value
, &p
->condition_mode
,
2046 &p
->condition_value
);
2049 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2050 p
->condition_value
= 0;
2053 p
->addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
2058 p
->addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
2059 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2060 p
->condition_value
= 0;
2062 /* The watchpoint will trigger if the address of the memory access is
2063 within the defined range, as follows: p->addr <= address < p->addr2.
2065 Note that the above sentence just documents how ptrace interprets
2066 its arguments; the watchpoint is set to watch the range defined by
2067 the user _inclusively_, as specified by the user interface. */
2068 p
->addr2
= (uint64_t) addr
+ len
;
2071 p
->version
= PPC_DEBUG_CURRENT_VERSION
;
2072 p
->trigger_type
= get_trigger_type (rw
);
2073 p
->addr
= (uint64_t) addr
;
2077 ppc_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int rw
,
2078 struct expression
*cond
)
2080 struct lwp_info
*lp
;
2083 if (have_ptrace_hwdebug_interface ())
2085 struct ppc_hw_breakpoint p
;
2087 create_watchpoint_request (&p
, addr
, len
, rw
, cond
, 1);
2090 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
2097 long read_mode
, write_mode
;
2099 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2101 /* PowerPC 440 requires only the read/write flags to be passed
2108 /* PowerPC 970 and other DABR-based processors are required to pass
2109 the Breakpoint Translation bit together with the flags. */
2114 dabr_value
= addr
& ~(read_mode
| write_mode
);
2118 /* Set read and translate bits. */
2119 dabr_value
|= read_mode
;
2122 /* Set write and translate bits. */
2123 dabr_value
|= write_mode
;
2126 /* Set read, write and translate bits. */
2127 dabr_value
|= read_mode
| write_mode
;
2131 saved_dabr_value
= dabr_value
;
2134 if (ptrace (PTRACE_SET_DEBUGREG
, ptid_get_lwp (lp
->ptid
), 0,
2135 saved_dabr_value
) < 0)
2145 ppc_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int rw
,
2146 struct expression
*cond
)
2148 struct lwp_info
*lp
;
2151 if (have_ptrace_hwdebug_interface ())
2153 struct ppc_hw_breakpoint p
;
2155 create_watchpoint_request (&p
, addr
, len
, rw
, cond
, 0);
2158 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
2164 saved_dabr_value
= 0;
2166 if (ptrace (PTRACE_SET_DEBUGREG
, ptid_get_lwp (lp
->ptid
), 0,
2167 saved_dabr_value
) < 0)
2177 ppc_linux_new_thread (struct lwp_info
*lp
)
2179 int tid
= ptid_get_lwp (lp
->ptid
);
2181 if (have_ptrace_hwdebug_interface ())
2184 struct thread_points
*p
;
2185 struct hw_break_tuple
*hw_breaks
;
2187 if (VEC_empty (thread_points_p
, ppc_threads
))
2190 /* Get a list of breakpoints from any thread. */
2191 p
= VEC_last (thread_points_p
, ppc_threads
);
2192 hw_breaks
= p
->hw_breaks
;
2194 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2195 for (i
= 0; i
< max_slots_number
; i
++)
2196 if (hw_breaks
[i
].hw_break
)
2198 /* Older kernels did not make new threads inherit their parent
2199 thread's debug state, so we always clear the slot and replicate
2200 the debug state ourselves, ensuring compatibility with all
2203 /* The ppc debug resource accounting is done through "slots".
2204 Ask the kernel the deallocate this specific *point's slot. */
2205 ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
);
2207 hwdebug_insert_point (hw_breaks
[i
].hw_break
, tid
);
2211 ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, saved_dabr_value
);
2215 ppc_linux_thread_exit (struct thread_info
*tp
, int silent
)
2218 int tid
= ptid_get_lwp (tp
->ptid
);
2219 struct hw_break_tuple
*hw_breaks
;
2220 struct thread_points
*t
= NULL
, *p
;
2222 if (!have_ptrace_hwdebug_interface ())
2225 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, p
); i
++)
2235 VEC_unordered_remove (thread_points_p
, ppc_threads
, i
);
2237 hw_breaks
= t
->hw_breaks
;
2239 for (i
= 0; i
< max_slots_number
; i
++)
2240 if (hw_breaks
[i
].hw_break
)
2241 xfree (hw_breaks
[i
].hw_break
);
2243 xfree (t
->hw_breaks
);
2248 ppc_linux_stopped_data_address (struct target_ops
*target
, CORE_ADDR
*addr_p
)
2252 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
2255 if (siginfo
.si_signo
!= SIGTRAP
2256 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2259 if (have_ptrace_hwdebug_interface ())
2262 struct thread_points
*t
;
2263 struct hw_break_tuple
*hw_breaks
;
2264 /* The index (or slot) of the *point is passed in the si_errno field. */
2265 int slot
= siginfo
.si_errno
;
2267 t
= hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid
), 0);
2269 /* Find out if this *point is a hardware breakpoint.
2270 If so, we should return 0. */
2273 hw_breaks
= t
->hw_breaks
;
2274 for (i
= 0; i
< max_slots_number
; i
++)
2275 if (hw_breaks
[i
].hw_break
&& hw_breaks
[i
].slot
== slot
2276 && hw_breaks
[i
].hw_break
->trigger_type
2277 == PPC_BREAKPOINT_TRIGGER_EXECUTE
)
2282 *addr_p
= (CORE_ADDR
) (uintptr_t) siginfo
.si_addr
;
2287 ppc_linux_stopped_by_watchpoint (struct target_ops
*ops
)
2290 return ppc_linux_stopped_data_address (ops
, &addr
);
2294 ppc_linux_watchpoint_addr_within_range (struct target_ops
*target
,
2296 CORE_ADDR start
, int length
)
2300 if (have_ptrace_hwdebug_interface ()
2301 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2302 return start
<= addr
&& start
+ length
>= addr
;
2303 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2310 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2311 return start
<= addr
+ mask
&& start
+ length
- 1 >= addr
;
2314 /* Return the number of registers needed for a masked hardware watchpoint. */
2317 ppc_linux_masked_watch_num_registers (struct target_ops
*target
,
2318 CORE_ADDR addr
, CORE_ADDR mask
)
2320 if (!have_ptrace_hwdebug_interface ()
2321 || (hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_MASK
) == 0)
2323 else if ((mask
& 0xC0000000) != 0xC0000000)
2325 warning (_("The given mask covers kernel address space "
2326 "and cannot be used.\n"));
2335 ppc_linux_store_inferior_registers (struct target_ops
*ops
,
2336 struct regcache
*regcache
, int regno
)
2338 /* Overload thread id onto process id. */
2339 int tid
= ptid_get_lwp (inferior_ptid
);
2341 /* No thread id, just use process id. */
2343 tid
= ptid_get_pid (inferior_ptid
);
2346 store_register (regcache
, tid
, regno
);
2348 store_ppc_registers (regcache
, tid
);
2351 /* Functions for transferring registers between a gregset_t or fpregset_t
2352 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2353 by the ptrace interface, not the current program's ABI. Eg. if a
2354 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2355 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2358 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
2360 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2362 ppc_supply_gregset (regset
, regcache
, -1, gregsetp
, sizeof (*gregsetp
));
2366 fill_gregset (const struct regcache
*regcache
,
2367 gdb_gregset_t
*gregsetp
, int regno
)
2369 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2372 memset (gregsetp
, 0, sizeof (*gregsetp
));
2373 ppc_collect_gregset (regset
, regcache
, regno
, gregsetp
, sizeof (*gregsetp
));
2377 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
* fpregsetp
)
2379 const struct regset
*regset
= ppc_linux_fpregset ();
2381 ppc_supply_fpregset (regset
, regcache
, -1,
2382 fpregsetp
, sizeof (*fpregsetp
));
2386 fill_fpregset (const struct regcache
*regcache
,
2387 gdb_fpregset_t
*fpregsetp
, int regno
)
2389 const struct regset
*regset
= ppc_linux_fpregset ();
2391 ppc_collect_fpregset (regset
, regcache
, regno
,
2392 fpregsetp
, sizeof (*fpregsetp
));
2396 ppc_linux_target_wordsize (void)
2400 /* Check for 64-bit inferior process. This is the case when the host is
2401 64-bit, and in addition the top bit of the MSR register is set. */
2402 #ifdef __powerpc64__
2405 int tid
= ptid_get_lwp (inferior_ptid
);
2407 tid
= ptid_get_pid (inferior_ptid
);
2410 msr
= (long) ptrace (PTRACE_PEEKUSER
, tid
, PT_MSR
* 8, 0);
2411 if (errno
== 0 && msr
< 0)
2419 ppc_linux_auxv_parse (struct target_ops
*ops
, gdb_byte
**readptr
,
2420 gdb_byte
*endptr
, CORE_ADDR
*typep
, CORE_ADDR
*valp
)
2422 int sizeof_auxv_field
= ppc_linux_target_wordsize ();
2423 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
2424 gdb_byte
*ptr
= *readptr
;
2429 if (endptr
- ptr
< sizeof_auxv_field
* 2)
2432 *typep
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2433 ptr
+= sizeof_auxv_field
;
2434 *valp
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2435 ptr
+= sizeof_auxv_field
;
2441 static const struct target_desc
*
2442 ppc_linux_read_description (struct target_ops
*ops
)
2449 int tid
= ptid_get_lwp (inferior_ptid
);
2451 tid
= ptid_get_pid (inferior_ptid
);
2453 if (have_ptrace_getsetevrregs
)
2455 struct gdb_evrregset_t evrregset
;
2457 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, &evrregset
) >= 0)
2458 return tdesc_powerpc_e500l
;
2460 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2461 Anything else needs to be reported. */
2462 else if (errno
!= EIO
)
2463 perror_with_name (_("Unable to fetch SPE registers"));
2466 if (have_ptrace_getsetvsxregs
)
2468 gdb_vsxregset_t vsxregset
;
2470 if (ptrace (PTRACE_GETVSXREGS
, tid
, 0, &vsxregset
) >= 0)
2473 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2474 Anything else needs to be reported. */
2475 else if (errno
!= EIO
)
2476 perror_with_name (_("Unable to fetch VSX registers"));
2479 if (have_ptrace_getvrregs
)
2481 gdb_vrregset_t vrregset
;
2483 if (ptrace (PTRACE_GETVRREGS
, tid
, 0, &vrregset
) >= 0)
2486 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2487 Anything else needs to be reported. */
2488 else if (errno
!= EIO
)
2489 perror_with_name (_("Unable to fetch AltiVec registers"));
2492 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2493 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2494 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2495 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2496 half of the register are for Decimal Floating Point, we check if that
2497 feature is available to decide the size of the FPSCR. */
2498 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP
)
2501 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL
)
2504 if (ppc_linux_target_wordsize () == 8)
2507 return tdesc_powerpc_cell64l
;
2509 return isa205
? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l
;
2512 ? tdesc_powerpc_isa205_altivec64l
: tdesc_powerpc_altivec64l
;
2514 return isa205
? tdesc_powerpc_isa205_64l
: tdesc_powerpc_64l
;
2518 return tdesc_powerpc_cell32l
;
2520 return isa205
? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l
;
2522 return isa205
? tdesc_powerpc_isa205_altivec32l
: tdesc_powerpc_altivec32l
;
2524 return isa205
? tdesc_powerpc_isa205_32l
: tdesc_powerpc_32l
;
2527 void _initialize_ppc_linux_nat (void);
2530 _initialize_ppc_linux_nat (void)
2532 struct target_ops
*t
;
2534 /* Fill in the generic GNU/Linux methods. */
2535 t
= linux_target ();
2537 /* Add our register access methods. */
2538 t
->to_fetch_registers
= ppc_linux_fetch_inferior_registers
;
2539 t
->to_store_registers
= ppc_linux_store_inferior_registers
;
2541 /* Add our breakpoint/watchpoint methods. */
2542 t
->to_can_use_hw_breakpoint
= ppc_linux_can_use_hw_breakpoint
;
2543 t
->to_insert_hw_breakpoint
= ppc_linux_insert_hw_breakpoint
;
2544 t
->to_remove_hw_breakpoint
= ppc_linux_remove_hw_breakpoint
;
2545 t
->to_region_ok_for_hw_watchpoint
= ppc_linux_region_ok_for_hw_watchpoint
;
2546 t
->to_insert_watchpoint
= ppc_linux_insert_watchpoint
;
2547 t
->to_remove_watchpoint
= ppc_linux_remove_watchpoint
;
2548 t
->to_insert_mask_watchpoint
= ppc_linux_insert_mask_watchpoint
;
2549 t
->to_remove_mask_watchpoint
= ppc_linux_remove_mask_watchpoint
;
2550 t
->to_stopped_by_watchpoint
= ppc_linux_stopped_by_watchpoint
;
2551 t
->to_stopped_data_address
= ppc_linux_stopped_data_address
;
2552 t
->to_watchpoint_addr_within_range
= ppc_linux_watchpoint_addr_within_range
;
2553 t
->to_can_accel_watchpoint_condition
2554 = ppc_linux_can_accel_watchpoint_condition
;
2555 t
->to_masked_watch_num_registers
= ppc_linux_masked_watch_num_registers
;
2556 t
->to_ranged_break_num_registers
= ppc_linux_ranged_break_num_registers
;
2558 t
->to_read_description
= ppc_linux_read_description
;
2559 t
->to_auxv_parse
= ppc_linux_auxv_parse
;
2561 observer_attach_thread_exit (ppc_linux_thread_exit
);
2563 /* Register the target. */
2564 linux_nat_add_target (t
);
2565 linux_nat_set_new_thread (t
, ppc_linux_new_thread
);