1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "observable.h"
24 #include "gdbthread.h"
28 #include "linux-nat.h"
29 #include <sys/types.h>
32 #include <sys/ioctl.h>
35 #include <sys/procfs.h>
36 #include "nat/gdb_ptrace.h"
37 #include "inf-ptrace.h"
39 /* Prototypes for supply_gregset etc. */
42 #include "ppc-linux-tdep.h"
44 /* Required when using the AUXV. */
45 #include "elf/common.h"
48 #include "nat/ppc-linux.h"
50 /* Similarly for the hardware watchpoint support. These requests are used
51 when the PowerPC HWDEBUG ptrace interface is not available. */
52 #ifndef PTRACE_GET_DEBUGREG
53 #define PTRACE_GET_DEBUGREG 25
55 #ifndef PTRACE_SET_DEBUGREG
56 #define PTRACE_SET_DEBUGREG 26
58 #ifndef PTRACE_GETSIGINFO
59 #define PTRACE_GETSIGINFO 0x4202
62 /* These requests are used when the PowerPC HWDEBUG ptrace interface is
63 available. It exposes the debug facilities of PowerPC processors, as well
64 as additional features of BookE processors, such as ranged breakpoints and
65 watchpoints and hardware-accelerated condition evaluation. */
66 #ifndef PPC_PTRACE_GETHWDBGINFO
68 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
69 ptrace interface is not present in ptrace.h, so we'll have to pretty much
70 include it all here so that the code at least compiles on older systems. */
71 #define PPC_PTRACE_GETHWDBGINFO 0x89
72 #define PPC_PTRACE_SETHWDEBUG 0x88
73 #define PPC_PTRACE_DELHWDEBUG 0x87
77 uint32_t version
; /* Only version 1 exists to date. */
78 uint32_t num_instruction_bps
;
79 uint32_t num_data_bps
;
80 uint32_t num_condition_regs
;
81 uint32_t data_bp_alignment
;
82 uint32_t sizeof_condition
; /* size of the DVC register. */
86 /* Features will have bits indicating whether there is support for: */
87 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
88 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
89 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
90 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
92 struct ppc_hw_breakpoint
94 uint32_t version
; /* currently, version must be 1 */
95 uint32_t trigger_type
; /* only some combinations allowed */
96 uint32_t addr_mode
; /* address match mode */
97 uint32_t condition_mode
; /* break/watchpoint condition flags */
98 uint64_t addr
; /* break/watchpoint address */
99 uint64_t addr2
; /* range end or mask */
100 uint64_t condition_value
; /* contents of the DVC register */
104 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
105 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
106 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
107 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
110 #define PPC_BREAKPOINT_MODE_EXACT 0x0
111 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
112 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
113 #define PPC_BREAKPOINT_MODE_MASK 0x3
115 /* Condition mode. */
116 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
117 #define PPC_BREAKPOINT_CONDITION_AND 0x1
118 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
119 #define PPC_BREAKPOINT_CONDITION_OR 0x2
120 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
121 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
122 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
123 #define PPC_BREAKPOINT_CONDITION_BE(n) \
124 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
125 #endif /* PPC_PTRACE_GETHWDBGINFO */
127 /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
128 watchpoint (up to 512 bytes). */
129 #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
130 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
131 #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
133 /* Similarly for the general-purpose (gp0 -- gp31)
134 and floating-point registers (fp0 -- fp31). */
135 #ifndef PTRACE_GETREGS
136 #define PTRACE_GETREGS 12
138 #ifndef PTRACE_SETREGS
139 #define PTRACE_SETREGS 13
141 #ifndef PTRACE_GETFPREGS
142 #define PTRACE_GETFPREGS 14
144 #ifndef PTRACE_SETFPREGS
145 #define PTRACE_SETFPREGS 15
148 /* This oddity is because the Linux kernel defines elf_vrregset_t as
149 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
150 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
151 the vrsave as an extra 4 bytes at the end. I opted for creating a
152 flat array of chars, so that it is easier to manipulate for gdb.
154 There are 32 vector registers 16 bytes longs, plus a VSCR register
155 which is only 4 bytes long, but is fetched as a 16 bytes
156 quantity. Up to here we have the elf_vrregset_t structure.
157 Appended to this there is space for the VRSAVE register: 4 bytes.
158 Even though this vrsave register is not included in the regset
159 typedef, it is handled by the ptrace requests.
161 Note that GNU/Linux doesn't support little endian PPC hardware,
162 therefore the offset at which the real value of the VSCR register
163 is located will be always 12 bytes.
165 The layout is like this (where x is the actual value of the vscr reg): */
169 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
170 <-------> <-------><-------><->
175 #define SIZEOF_VRREGS 33*16+4
177 typedef char gdb_vrregset_t
[SIZEOF_VRREGS
];
179 /* This is the layout of the POWER7 VSX registers and the way they overlap
180 with the existing FPR and VMX registers.
182 VSR doubleword 0 VSR doubleword 1
183 ----------------------------------------------------------------
185 ----------------------------------------------------------------
187 ----------------------------------------------------------------
190 ----------------------------------------------------------------
191 VSR[30] | FPR[30] | |
192 ----------------------------------------------------------------
193 VSR[31] | FPR[31] | |
194 ----------------------------------------------------------------
196 ----------------------------------------------------------------
198 ----------------------------------------------------------------
201 ----------------------------------------------------------------
203 ----------------------------------------------------------------
205 ----------------------------------------------------------------
207 VSX has 64 128bit registers. The first 32 registers overlap with
208 the FP registers (doubleword 0) and hence extend them with additional
209 64 bits (doubleword 1). The other 32 regs overlap with the VMX
211 #define SIZEOF_VSXREGS 32*8
213 typedef char gdb_vsxregset_t
[SIZEOF_VSXREGS
];
215 /* On PPC processors that support the Signal Processing Extension
216 (SPE) APU, the general-purpose registers are 64 bits long.
217 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
218 ptrace calls only access the lower half of each register, to allow
219 them to behave the same way they do on non-SPE systems. There's a
220 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
221 read and write the top halves of all the general-purpose registers
222 at once, along with some SPE-specific registers.
224 GDB itself continues to claim the general-purpose registers are 32
225 bits long. It has unnamed raw registers that hold the upper halves
226 of the gprs, and the full 64-bit SIMD views of the registers,
227 'ev0' -- 'ev31', are pseudo-registers that splice the top and
228 bottom halves together.
230 This is the structure filled in by PTRACE_GETEVRREGS and written to
231 the inferior's registers by PTRACE_SETEVRREGS. */
232 struct gdb_evrregset_t
234 unsigned long evr
[32];
235 unsigned long long acc
;
236 unsigned long spefscr
;
239 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
240 PTRACE_SETVSXREGS requests, for reading and writing the VSX
241 POWER7 registers 0 through 31. Zero if we've tried one of them and
242 gotten an error. Note that VSX registers 32 through 63 overlap
243 with VR registers 0 through 31. */
244 int have_ptrace_getsetvsxregs
= 1;
246 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
247 PTRACE_SETVRREGS requests, for reading and writing the Altivec
248 registers. Zero if we've tried one of them and gotten an
250 int have_ptrace_getvrregs
= 1;
252 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
253 PTRACE_SETEVRREGS requests, for reading and writing the SPE
254 registers. Zero if we've tried one of them and gotten an
256 int have_ptrace_getsetevrregs
= 1;
258 /* Non-zero if our kernel may support the PTRACE_GETREGS and
259 PTRACE_SETREGS requests, for reading and writing the
260 general-purpose registers. Zero if we've tried one of
261 them and gotten an error. */
262 int have_ptrace_getsetregs
= 1;
264 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
265 PTRACE_SETFPREGS requests, for reading and writing the
266 floating-pointers registers. Zero if we've tried one of
267 them and gotten an error. */
268 int have_ptrace_getsetfpregs
= 1;
270 struct ppc_linux_nat_target final
: public linux_nat_target
272 /* Add our register access methods. */
273 void fetch_registers (struct regcache
*, int) override
;
274 void store_registers (struct regcache
*, int) override
;
276 /* Add our breakpoint/watchpoint methods. */
277 int can_use_hw_breakpoint (enum bptype
, int, int) override
;
279 int insert_hw_breakpoint (struct gdbarch
*, struct bp_target_info
*)
282 int remove_hw_breakpoint (struct gdbarch
*, struct bp_target_info
*)
285 int region_ok_for_hw_watchpoint (CORE_ADDR
, int) override
;
287 int insert_watchpoint (CORE_ADDR
, int, enum target_hw_bp_type
,
288 struct expression
*) override
;
290 int remove_watchpoint (CORE_ADDR
, int, enum target_hw_bp_type
,
291 struct expression
*) override
;
293 int insert_mask_watchpoint (CORE_ADDR
, CORE_ADDR
, enum target_hw_bp_type
)
296 int remove_mask_watchpoint (CORE_ADDR
, CORE_ADDR
, enum target_hw_bp_type
)
299 bool stopped_by_watchpoint () override
;
301 bool stopped_data_address (CORE_ADDR
*) override
;
303 bool watchpoint_addr_within_range (CORE_ADDR
, CORE_ADDR
, int) override
;
305 bool can_accel_watchpoint_condition (CORE_ADDR
, int, int, struct expression
*)
308 int masked_watch_num_registers (CORE_ADDR
, CORE_ADDR
) override
;
310 int ranged_break_num_registers () override
;
312 const struct target_desc
*read_description () override
;
314 int auxv_parse (gdb_byte
**readptr
,
315 gdb_byte
*endptr
, CORE_ADDR
*typep
, CORE_ADDR
*valp
)
319 static ppc_linux_nat_target the_ppc_linux_nat_target
;
322 /* registers layout, as presented by the ptrace interface:
323 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
324 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
325 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
326 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
327 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
328 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
329 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
330 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
331 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
332 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
333 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
334 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
335 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
339 ppc_register_u_addr (struct gdbarch
*gdbarch
, int regno
)
342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
343 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
344 interface, and not the wordsize of the program's ABI. */
345 int wordsize
= sizeof (long);
347 /* General purpose registers occupy 1 slot each in the buffer. */
348 if (regno
>= tdep
->ppc_gp0_regnum
349 && regno
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
350 u_addr
= ((regno
- tdep
->ppc_gp0_regnum
+ PT_R0
) * wordsize
);
352 /* Floating point regs: eight bytes each in both 32- and 64-bit
353 ptrace interfaces. Thus, two slots each in 32-bit interface, one
354 slot each in 64-bit interface. */
355 if (tdep
->ppc_fp0_regnum
>= 0
356 && regno
>= tdep
->ppc_fp0_regnum
357 && regno
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
358 u_addr
= (PT_FPR0
* wordsize
) + ((regno
- tdep
->ppc_fp0_regnum
) * 8);
360 /* UISA special purpose registers: 1 slot each. */
361 if (regno
== gdbarch_pc_regnum (gdbarch
))
362 u_addr
= PT_NIP
* wordsize
;
363 if (regno
== tdep
->ppc_lr_regnum
)
364 u_addr
= PT_LNK
* wordsize
;
365 if (regno
== tdep
->ppc_cr_regnum
)
366 u_addr
= PT_CCR
* wordsize
;
367 if (regno
== tdep
->ppc_xer_regnum
)
368 u_addr
= PT_XER
* wordsize
;
369 if (regno
== tdep
->ppc_ctr_regnum
)
370 u_addr
= PT_CTR
* wordsize
;
372 if (regno
== tdep
->ppc_mq_regnum
)
373 u_addr
= PT_MQ
* wordsize
;
375 if (regno
== tdep
->ppc_ps_regnum
)
376 u_addr
= PT_MSR
* wordsize
;
377 if (regno
== PPC_ORIG_R3_REGNUM
)
378 u_addr
= PT_ORIG_R3
* wordsize
;
379 if (regno
== PPC_TRAP_REGNUM
)
380 u_addr
= PT_TRAP
* wordsize
;
381 if (tdep
->ppc_fpscr_regnum
>= 0
382 && regno
== tdep
->ppc_fpscr_regnum
)
384 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
385 kernel headers incorrectly contained the 32-bit definition of
386 PT_FPSCR. For the 32-bit definition, floating-point
387 registers occupy two 32-bit "slots", and the FPSCR lives in
388 the second half of such a slot-pair (hence +1). For 64-bit,
389 the FPSCR instead occupies the full 64-bit 2-word-slot and
390 hence no adjustment is necessary. Hack around this. */
391 if (wordsize
== 8 && PT_FPSCR
== (48 + 32 + 1))
392 u_addr
= (48 + 32) * wordsize
;
393 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
394 slot and not just its second word. The PT_FPSCR supplied when
395 GDB is compiled as a 32-bit app doesn't reflect this. */
396 else if (wordsize
== 4 && register_size (gdbarch
, regno
) == 8
397 && PT_FPSCR
== (48 + 2*32 + 1))
398 u_addr
= (48 + 2*32) * wordsize
;
400 u_addr
= PT_FPSCR
* wordsize
;
405 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
406 registers set mechanism, as opposed to the interface for all the
407 other registers, that stores/fetches each register individually. */
409 fetch_vsx_register (struct regcache
*regcache
, int tid
, int regno
)
412 gdb_vsxregset_t regs
;
413 struct gdbarch
*gdbarch
= regcache
->arch ();
414 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
415 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
417 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
422 have_ptrace_getsetvsxregs
= 0;
425 perror_with_name (_("Unable to fetch VSX register"));
428 regcache_raw_supply (regcache
, regno
,
429 regs
+ (regno
- tdep
->ppc_vsr0_upper_regnum
)
433 /* The Linux kernel ptrace interface for AltiVec registers uses the
434 registers set mechanism, as opposed to the interface for all the
435 other registers, that stores/fetches each register individually. */
437 fetch_altivec_register (struct regcache
*regcache
, int tid
, int regno
)
442 struct gdbarch
*gdbarch
= regcache
->arch ();
443 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
444 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
446 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
451 have_ptrace_getvrregs
= 0;
454 perror_with_name (_("Unable to fetch AltiVec register"));
457 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
458 long on the hardware. We deal only with the lower 4 bytes of the
459 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
460 there is no need to define an offset for it. */
461 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
462 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
464 regcache_raw_supply (regcache
, regno
,
466 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
469 /* Fetch the top 32 bits of TID's general-purpose registers and the
470 SPE-specific registers, and place the results in EVRREGSET. If we
471 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
474 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
475 PTRACE_SETEVRREGS requests are supported is isolated here, and in
476 set_spe_registers. */
478 get_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
480 if (have_ptrace_getsetevrregs
)
482 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, evrregset
) >= 0)
486 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
487 we just return zeros. */
489 have_ptrace_getsetevrregs
= 0;
491 /* Anything else needs to be reported. */
492 perror_with_name (_("Unable to fetch SPE registers"));
496 memset (evrregset
, 0, sizeof (*evrregset
));
499 /* Supply values from TID for SPE-specific raw registers: the upper
500 halves of the GPRs, the accumulator, and the spefscr. REGNO must
501 be the number of an upper half register, acc, spefscr, or -1 to
502 supply the values of all registers. */
504 fetch_spe_register (struct regcache
*regcache
, int tid
, int regno
)
506 struct gdbarch
*gdbarch
= regcache
->arch ();
507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
508 struct gdb_evrregset_t evrregs
;
510 gdb_assert (sizeof (evrregs
.evr
[0])
511 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
512 gdb_assert (sizeof (evrregs
.acc
)
513 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
514 gdb_assert (sizeof (evrregs
.spefscr
)
515 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
517 get_spe_registers (tid
, &evrregs
);
523 for (i
= 0; i
< ppc_num_gprs
; i
++)
524 regcache_raw_supply (regcache
, tdep
->ppc_ev0_upper_regnum
+ i
,
527 else if (tdep
->ppc_ev0_upper_regnum
<= regno
528 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
529 regcache_raw_supply (regcache
, regno
,
530 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
533 || regno
== tdep
->ppc_acc_regnum
)
534 regcache_raw_supply (regcache
, tdep
->ppc_acc_regnum
, &evrregs
.acc
);
537 || regno
== tdep
->ppc_spefscr_regnum
)
538 regcache_raw_supply (regcache
, tdep
->ppc_spefscr_regnum
,
543 fetch_register (struct regcache
*regcache
, int tid
, int regno
)
545 struct gdbarch
*gdbarch
= regcache
->arch ();
546 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
547 /* This isn't really an address. But ptrace thinks of it as one. */
548 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
549 int bytes_transferred
;
550 unsigned int offset
; /* Offset of registers within the u area. */
551 gdb_byte buf
[PPC_MAX_REGISTER_SIZE
];
553 if (altivec_register_p (gdbarch
, regno
))
555 /* If this is the first time through, or if it is not the first
556 time through, and we have comfirmed that there is kernel
557 support for such a ptrace request, then go and fetch the
559 if (have_ptrace_getvrregs
)
561 fetch_altivec_register (regcache
, tid
, regno
);
564 /* If we have discovered that there is no ptrace support for
565 AltiVec registers, fall through and return zeroes, because
566 regaddr will be -1 in this case. */
568 if (vsx_register_p (gdbarch
, regno
))
570 if (have_ptrace_getsetvsxregs
)
572 fetch_vsx_register (regcache
, tid
, regno
);
576 else if (spe_register_p (gdbarch
, regno
))
578 fetch_spe_register (regcache
, tid
, regno
);
584 memset (buf
, '\0', register_size (gdbarch
, regno
)); /* Supply zeroes */
585 regcache_raw_supply (regcache
, regno
, buf
);
589 /* Read the raw register using sizeof(long) sized chunks. On a
590 32-bit platform, 64-bit floating-point registers will require two
592 for (bytes_transferred
= 0;
593 bytes_transferred
< register_size (gdbarch
, regno
);
594 bytes_transferred
+= sizeof (long))
599 l
= ptrace (PTRACE_PEEKUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, 0);
600 regaddr
+= sizeof (long);
604 xsnprintf (message
, sizeof (message
), "reading register %s (#%d)",
605 gdbarch_register_name (gdbarch
, regno
), regno
);
606 perror_with_name (message
);
608 memcpy (&buf
[bytes_transferred
], &l
, sizeof (l
));
611 /* Now supply the register. Keep in mind that the regcache's idea
612 of the register's size may not be a multiple of sizeof
614 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
616 /* Little-endian values are always found at the left end of the
617 bytes transferred. */
618 regcache_raw_supply (regcache
, regno
, buf
);
620 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
622 /* Big-endian values are found at the right end of the bytes
624 size_t padding
= (bytes_transferred
- register_size (gdbarch
, regno
));
625 regcache_raw_supply (regcache
, regno
, buf
+ padding
);
628 internal_error (__FILE__
, __LINE__
,
629 _("fetch_register: unexpected byte order: %d"),
630 gdbarch_byte_order (gdbarch
));
634 supply_vsxregset (struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
637 struct gdbarch
*gdbarch
= regcache
->arch ();
638 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
639 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
641 for (i
= 0; i
< ppc_num_vshrs
; i
++)
643 regcache_raw_supply (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
644 *vsxregsetp
+ i
* vsxregsize
);
649 supply_vrregset (struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
652 struct gdbarch
*gdbarch
= regcache
->arch ();
653 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
654 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
655 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
656 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
658 for (i
= 0; i
< num_of_vrregs
; i
++)
660 /* The last 2 registers of this set are only 32 bit long, not
661 128. However an offset is necessary only for VSCR because it
662 occupies a whole vector, while VRSAVE occupies a full 4 bytes
664 if (i
== (num_of_vrregs
- 2))
665 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
666 *vrregsetp
+ i
* vrregsize
+ offset
);
668 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
669 *vrregsetp
+ i
* vrregsize
);
674 fetch_vsx_registers (struct regcache
*regcache
, int tid
)
677 gdb_vsxregset_t regs
;
679 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
684 have_ptrace_getsetvsxregs
= 0;
687 perror_with_name (_("Unable to fetch VSX registers"));
689 supply_vsxregset (regcache
, ®s
);
693 fetch_altivec_registers (struct regcache
*regcache
, int tid
)
698 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
703 have_ptrace_getvrregs
= 0;
706 perror_with_name (_("Unable to fetch AltiVec registers"));
708 supply_vrregset (regcache
, ®s
);
711 /* This function actually issues the request to ptrace, telling
712 it to get all general-purpose registers and put them into the
715 If the ptrace request does not exist, this function returns 0
716 and properly sets the have_ptrace_* flag. If the request fails,
717 this function calls perror_with_name. Otherwise, if the request
718 succeeds, then the regcache gets filled and 1 is returned. */
720 fetch_all_gp_regs (struct regcache
*regcache
, int tid
)
722 struct gdbarch
*gdbarch
= regcache
->arch ();
723 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
724 gdb_gregset_t gregset
;
726 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
730 have_ptrace_getsetregs
= 0;
733 perror_with_name (_("Couldn't get general-purpose registers."));
736 supply_gregset (regcache
, (const gdb_gregset_t
*) &gregset
);
741 /* This is a wrapper for the fetch_all_gp_regs function. It is
742 responsible for verifying if this target has the ptrace request
743 that can be used to fetch all general-purpose registers at one
744 shot. If it doesn't, then we should fetch them using the
745 old-fashioned way, which is to iterate over the registers and
746 request them one by one. */
748 fetch_gp_regs (struct regcache
*regcache
, int tid
)
750 struct gdbarch
*gdbarch
= regcache
->arch ();
751 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
754 if (have_ptrace_getsetregs
)
755 if (fetch_all_gp_regs (regcache
, tid
))
758 /* If we've hit this point, it doesn't really matter which
759 architecture we are using. We just need to read the
760 registers in the "old-fashioned way". */
761 for (i
= 0; i
< ppc_num_gprs
; i
++)
762 fetch_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
765 /* This function actually issues the request to ptrace, telling
766 it to get all floating-point registers and put them into the
769 If the ptrace request does not exist, this function returns 0
770 and properly sets the have_ptrace_* flag. If the request fails,
771 this function calls perror_with_name. Otherwise, if the request
772 succeeds, then the regcache gets filled and 1 is returned. */
774 fetch_all_fp_regs (struct regcache
*regcache
, int tid
)
776 gdb_fpregset_t fpregs
;
778 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
782 have_ptrace_getsetfpregs
= 0;
785 perror_with_name (_("Couldn't get floating-point registers."));
788 supply_fpregset (regcache
, (const gdb_fpregset_t
*) &fpregs
);
793 /* This is a wrapper for the fetch_all_fp_regs function. It is
794 responsible for verifying if this target has the ptrace request
795 that can be used to fetch all floating-point registers at one
796 shot. If it doesn't, then we should fetch them using the
797 old-fashioned way, which is to iterate over the registers and
798 request them one by one. */
800 fetch_fp_regs (struct regcache
*regcache
, int tid
)
802 struct gdbarch
*gdbarch
= regcache
->arch ();
803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
806 if (have_ptrace_getsetfpregs
)
807 if (fetch_all_fp_regs (regcache
, tid
))
810 /* If we've hit this point, it doesn't really matter which
811 architecture we are using. We just need to read the
812 registers in the "old-fashioned way". */
813 for (i
= 0; i
< ppc_num_fprs
; i
++)
814 fetch_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
818 fetch_ppc_registers (struct regcache
*regcache
, int tid
)
821 struct gdbarch
*gdbarch
= regcache
->arch ();
822 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
824 fetch_gp_regs (regcache
, tid
);
825 if (tdep
->ppc_fp0_regnum
>= 0)
826 fetch_fp_regs (regcache
, tid
);
827 fetch_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
828 if (tdep
->ppc_ps_regnum
!= -1)
829 fetch_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
830 if (tdep
->ppc_cr_regnum
!= -1)
831 fetch_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
832 if (tdep
->ppc_lr_regnum
!= -1)
833 fetch_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
834 if (tdep
->ppc_ctr_regnum
!= -1)
835 fetch_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
836 if (tdep
->ppc_xer_regnum
!= -1)
837 fetch_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
838 if (tdep
->ppc_mq_regnum
!= -1)
839 fetch_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
840 if (ppc_linux_trap_reg_p (gdbarch
))
842 fetch_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
843 fetch_register (regcache
, tid
, PPC_TRAP_REGNUM
);
845 if (tdep
->ppc_fpscr_regnum
!= -1)
846 fetch_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
847 if (have_ptrace_getvrregs
)
848 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
849 fetch_altivec_registers (regcache
, tid
);
850 if (have_ptrace_getsetvsxregs
)
851 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
852 fetch_vsx_registers (regcache
, tid
);
853 if (tdep
->ppc_ev0_upper_regnum
>= 0)
854 fetch_spe_register (regcache
, tid
, -1);
857 /* Fetch registers from the child process. Fetch all registers if
858 regno == -1, otherwise fetch all general registers or all floating
859 point registers depending upon the value of regno. */
861 ppc_linux_nat_target::fetch_registers (struct regcache
*regcache
, int regno
)
863 pid_t tid
= get_ptrace_pid (regcache_get_ptid (regcache
));
866 fetch_ppc_registers (regcache
, tid
);
868 fetch_register (regcache
, tid
, regno
);
871 /* Store one VSX register. */
873 store_vsx_register (const struct regcache
*regcache
, int tid
, int regno
)
876 gdb_vsxregset_t regs
;
877 struct gdbarch
*gdbarch
= regcache
->arch ();
878 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
879 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
881 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
886 have_ptrace_getsetvsxregs
= 0;
889 perror_with_name (_("Unable to fetch VSX register"));
892 regcache_raw_collect (regcache
, regno
, regs
+
893 (regno
- tdep
->ppc_vsr0_upper_regnum
) * vsxregsize
);
895 ret
= ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
);
897 perror_with_name (_("Unable to store VSX register"));
900 /* Store one register. */
902 store_altivec_register (const struct regcache
*regcache
, int tid
, int regno
)
907 struct gdbarch
*gdbarch
= regcache
->arch ();
908 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
909 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
911 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
916 have_ptrace_getvrregs
= 0;
919 perror_with_name (_("Unable to fetch AltiVec register"));
922 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
923 long on the hardware. */
924 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
925 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
927 regcache_raw_collect (regcache
, regno
,
929 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
931 ret
= ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
);
933 perror_with_name (_("Unable to store AltiVec register"));
936 /* Assuming TID referrs to an SPE process, set the top halves of TID's
937 general-purpose registers and its SPE-specific registers to the
938 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
941 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
942 PTRACE_SETEVRREGS requests are supported is isolated here, and in
943 get_spe_registers. */
945 set_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
947 if (have_ptrace_getsetevrregs
)
949 if (ptrace (PTRACE_SETEVRREGS
, tid
, 0, evrregset
) >= 0)
953 /* EIO means that the PTRACE_SETEVRREGS request isn't
954 supported; we fail silently, and don't try the call
957 have_ptrace_getsetevrregs
= 0;
959 /* Anything else needs to be reported. */
960 perror_with_name (_("Unable to set SPE registers"));
965 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
966 If REGNO is -1, write the values of all the SPE-specific
969 store_spe_register (const struct regcache
*regcache
, int tid
, int regno
)
971 struct gdbarch
*gdbarch
= regcache
->arch ();
972 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
973 struct gdb_evrregset_t evrregs
;
975 gdb_assert (sizeof (evrregs
.evr
[0])
976 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
977 gdb_assert (sizeof (evrregs
.acc
)
978 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
979 gdb_assert (sizeof (evrregs
.spefscr
)
980 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
983 /* Since we're going to write out every register, the code below
984 should store to every field of evrregs; if that doesn't happen,
985 make it obvious by initializing it with suspicious values. */
986 memset (&evrregs
, 42, sizeof (evrregs
));
988 /* We can only read and write the entire EVR register set at a
989 time, so to write just a single register, we do a
990 read-modify-write maneuver. */
991 get_spe_registers (tid
, &evrregs
);
997 for (i
= 0; i
< ppc_num_gprs
; i
++)
998 regcache_raw_collect (regcache
,
999 tdep
->ppc_ev0_upper_regnum
+ i
,
1002 else if (tdep
->ppc_ev0_upper_regnum
<= regno
1003 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1004 regcache_raw_collect (regcache
, regno
,
1005 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
1008 || regno
== tdep
->ppc_acc_regnum
)
1009 regcache_raw_collect (regcache
,
1010 tdep
->ppc_acc_regnum
,
1014 || regno
== tdep
->ppc_spefscr_regnum
)
1015 regcache_raw_collect (regcache
,
1016 tdep
->ppc_spefscr_regnum
,
1019 /* Write back the modified register set. */
1020 set_spe_registers (tid
, &evrregs
);
1024 store_register (const struct regcache
*regcache
, int tid
, int regno
)
1026 struct gdbarch
*gdbarch
= regcache
->arch ();
1027 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1028 /* This isn't really an address. But ptrace thinks of it as one. */
1029 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
1031 size_t bytes_to_transfer
;
1032 gdb_byte buf
[PPC_MAX_REGISTER_SIZE
];
1034 if (altivec_register_p (gdbarch
, regno
))
1036 store_altivec_register (regcache
, tid
, regno
);
1039 if (vsx_register_p (gdbarch
, regno
))
1041 store_vsx_register (regcache
, tid
, regno
);
1044 else if (spe_register_p (gdbarch
, regno
))
1046 store_spe_register (regcache
, tid
, regno
);
1053 /* First collect the register. Keep in mind that the regcache's
1054 idea of the register's size may not be a multiple of sizeof
1056 memset (buf
, 0, sizeof buf
);
1057 bytes_to_transfer
= align_up (register_size (gdbarch
, regno
), sizeof (long));
1058 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1060 /* Little-endian values always sit at the left end of the buffer. */
1061 regcache_raw_collect (regcache
, regno
, buf
);
1063 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1065 /* Big-endian values sit at the right end of the buffer. */
1066 size_t padding
= (bytes_to_transfer
- register_size (gdbarch
, regno
));
1067 regcache_raw_collect (regcache
, regno
, buf
+ padding
);
1070 for (i
= 0; i
< bytes_to_transfer
; i
+= sizeof (long))
1074 memcpy (&l
, &buf
[i
], sizeof (l
));
1076 ptrace (PTRACE_POKEUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, l
);
1077 regaddr
+= sizeof (long);
1080 && (regno
== tdep
->ppc_fpscr_regnum
1081 || regno
== PPC_ORIG_R3_REGNUM
1082 || regno
== PPC_TRAP_REGNUM
))
1084 /* Some older kernel versions don't allow fpscr, orig_r3
1085 or trap to be written. */
1092 xsnprintf (message
, sizeof (message
), "writing register %s (#%d)",
1093 gdbarch_register_name (gdbarch
, regno
), regno
);
1094 perror_with_name (message
);
1100 fill_vsxregset (const struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
1103 struct gdbarch
*gdbarch
= regcache
->arch ();
1104 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1105 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
1107 for (i
= 0; i
< ppc_num_vshrs
; i
++)
1108 regcache_raw_collect (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
1109 *vsxregsetp
+ i
* vsxregsize
);
1113 fill_vrregset (const struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
1116 struct gdbarch
*gdbarch
= regcache
->arch ();
1117 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1118 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
1119 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
1120 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
1122 for (i
= 0; i
< num_of_vrregs
; i
++)
1124 /* The last 2 registers of this set are only 32 bit long, not
1125 128, but only VSCR is fetched as a 16 bytes quantity. */
1126 if (i
== (num_of_vrregs
- 2))
1127 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1128 *vrregsetp
+ i
* vrregsize
+ offset
);
1130 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1131 *vrregsetp
+ i
* vrregsize
);
1136 store_vsx_registers (const struct regcache
*regcache
, int tid
)
1139 gdb_vsxregset_t regs
;
1141 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
1146 have_ptrace_getsetvsxregs
= 0;
1149 perror_with_name (_("Couldn't get VSX registers"));
1152 fill_vsxregset (regcache
, ®s
);
1154 if (ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
) < 0)
1155 perror_with_name (_("Couldn't write VSX registers"));
1159 store_altivec_registers (const struct regcache
*regcache
, int tid
)
1162 gdb_vrregset_t regs
;
1164 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
1169 have_ptrace_getvrregs
= 0;
1172 perror_with_name (_("Couldn't get AltiVec registers"));
1175 fill_vrregset (regcache
, ®s
);
1177 if (ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
) < 0)
1178 perror_with_name (_("Couldn't write AltiVec registers"));
1181 /* This function actually issues the request to ptrace, telling
1182 it to store all general-purpose registers present in the specified
1185 If the ptrace request does not exist, this function returns 0
1186 and properly sets the have_ptrace_* flag. If the request fails,
1187 this function calls perror_with_name. Otherwise, if the request
1188 succeeds, then the regcache is stored and 1 is returned. */
1190 store_all_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1192 struct gdbarch
*gdbarch
= regcache
->arch ();
1193 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1194 gdb_gregset_t gregset
;
1196 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
1200 have_ptrace_getsetregs
= 0;
1203 perror_with_name (_("Couldn't get general-purpose registers."));
1206 fill_gregset (regcache
, &gregset
, regno
);
1208 if (ptrace (PTRACE_SETREGS
, tid
, 0, (void *) &gregset
) < 0)
1212 have_ptrace_getsetregs
= 0;
1215 perror_with_name (_("Couldn't set general-purpose registers."));
1221 /* This is a wrapper for the store_all_gp_regs function. It is
1222 responsible for verifying if this target has the ptrace request
1223 that can be used to store all general-purpose registers at one
1224 shot. If it doesn't, then we should store them using the
1225 old-fashioned way, which is to iterate over the registers and
1226 store them one by one. */
1228 store_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1230 struct gdbarch
*gdbarch
= regcache
->arch ();
1231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1234 if (have_ptrace_getsetregs
)
1235 if (store_all_gp_regs (regcache
, tid
, regno
))
1238 /* If we hit this point, it doesn't really matter which
1239 architecture we are using. We just need to store the
1240 registers in the "old-fashioned way". */
1241 for (i
= 0; i
< ppc_num_gprs
; i
++)
1242 store_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
1245 /* This function actually issues the request to ptrace, telling
1246 it to store all floating-point registers present in the specified
1249 If the ptrace request does not exist, this function returns 0
1250 and properly sets the have_ptrace_* flag. If the request fails,
1251 this function calls perror_with_name. Otherwise, if the request
1252 succeeds, then the regcache is stored and 1 is returned. */
1254 store_all_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1256 gdb_fpregset_t fpregs
;
1258 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1262 have_ptrace_getsetfpregs
= 0;
1265 perror_with_name (_("Couldn't get floating-point registers."));
1268 fill_fpregset (regcache
, &fpregs
, regno
);
1270 if (ptrace (PTRACE_SETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1274 have_ptrace_getsetfpregs
= 0;
1277 perror_with_name (_("Couldn't set floating-point registers."));
1283 /* This is a wrapper for the store_all_fp_regs function. It is
1284 responsible for verifying if this target has the ptrace request
1285 that can be used to store all floating-point registers at one
1286 shot. If it doesn't, then we should store them using the
1287 old-fashioned way, which is to iterate over the registers and
1288 store them one by one. */
1290 store_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1292 struct gdbarch
*gdbarch
= regcache
->arch ();
1293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1296 if (have_ptrace_getsetfpregs
)
1297 if (store_all_fp_regs (regcache
, tid
, regno
))
1300 /* If we hit this point, it doesn't really matter which
1301 architecture we are using. We just need to store the
1302 registers in the "old-fashioned way". */
1303 for (i
= 0; i
< ppc_num_fprs
; i
++)
1304 store_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
1308 store_ppc_registers (const struct regcache
*regcache
, int tid
)
1311 struct gdbarch
*gdbarch
= regcache
->arch ();
1312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1314 store_gp_regs (regcache
, tid
, -1);
1315 if (tdep
->ppc_fp0_regnum
>= 0)
1316 store_fp_regs (regcache
, tid
, -1);
1317 store_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
1318 if (tdep
->ppc_ps_regnum
!= -1)
1319 store_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
1320 if (tdep
->ppc_cr_regnum
!= -1)
1321 store_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
1322 if (tdep
->ppc_lr_regnum
!= -1)
1323 store_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
1324 if (tdep
->ppc_ctr_regnum
!= -1)
1325 store_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
1326 if (tdep
->ppc_xer_regnum
!= -1)
1327 store_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
1328 if (tdep
->ppc_mq_regnum
!= -1)
1329 store_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
1330 if (tdep
->ppc_fpscr_regnum
!= -1)
1331 store_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
1332 if (ppc_linux_trap_reg_p (gdbarch
))
1334 store_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
1335 store_register (regcache
, tid
, PPC_TRAP_REGNUM
);
1337 if (have_ptrace_getvrregs
)
1338 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
1339 store_altivec_registers (regcache
, tid
);
1340 if (have_ptrace_getsetvsxregs
)
1341 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
1342 store_vsx_registers (regcache
, tid
);
1343 if (tdep
->ppc_ev0_upper_regnum
>= 0)
1344 store_spe_register (regcache
, tid
, -1);
1347 /* Fetch the AT_HWCAP entry from the aux vector. */
1348 static unsigned long
1349 ppc_linux_get_hwcap (void)
1353 if (target_auxv_search (target_stack
, AT_HWCAP
, &field
))
1354 return (unsigned long) field
;
1359 /* The cached DABR value, to install in new threads.
1360 This variable is used when the PowerPC HWDEBUG ptrace
1361 interface is not available. */
1362 static long saved_dabr_value
;
1364 /* Global structure that will store information about the available
1365 features provided by the PowerPC HWDEBUG ptrace interface. */
1366 static struct ppc_debug_info hwdebug_info
;
1368 /* Global variable that holds the maximum number of slots that the
1369 kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1371 static size_t max_slots_number
= 0;
1373 struct hw_break_tuple
1376 struct ppc_hw_breakpoint
*hw_break
;
1379 /* This is an internal VEC created to store information about *points inserted
1380 for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1382 typedef struct thread_points
1384 /* The TID to which this *point relates. */
1386 /* Information about the *point, such as its address, type, etc.
1388 Each element inside this vector corresponds to a hardware
1389 breakpoint or watchpoint in the thread represented by TID. The maximum
1390 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1391 the tuple is NULL, then the position in the vector is free. */
1392 struct hw_break_tuple
*hw_breaks
;
1394 DEF_VEC_P (thread_points_p
);
1396 VEC(thread_points_p
) *ppc_threads
= NULL
;
1398 /* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1400 #define PPC_DEBUG_CURRENT_VERSION 1
1402 /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
1404 have_ptrace_hwdebug_interface (void)
1406 static int have_ptrace_hwdebug_interface
= -1;
1408 if (have_ptrace_hwdebug_interface
== -1)
1412 tid
= ptid_get_lwp (inferior_ptid
);
1414 tid
= ptid_get_pid (inferior_ptid
);
1416 /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1417 if (ptrace (PPC_PTRACE_GETHWDBGINFO
, tid
, 0, &hwdebug_info
) >= 0)
1419 /* Check whether PowerPC HWDEBUG ptrace interface is functional and
1420 provides any supported feature. */
1421 if (hwdebug_info
.features
!= 0)
1423 have_ptrace_hwdebug_interface
= 1;
1424 max_slots_number
= hwdebug_info
.num_instruction_bps
1425 + hwdebug_info
.num_data_bps
1426 + hwdebug_info
.num_condition_regs
;
1427 return have_ptrace_hwdebug_interface
;
1430 /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1431 have_ptrace_hwdebug_interface
= 0;
1432 memset (&hwdebug_info
, 0, sizeof (struct ppc_debug_info
));
1435 return have_ptrace_hwdebug_interface
;
1439 ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type
, int cnt
, int ot
)
1441 int total_hw_wp
, total_hw_bp
;
1443 if (have_ptrace_hwdebug_interface ())
1445 /* When PowerPC HWDEBUG ptrace interface is available, the number of
1446 available hardware watchpoints and breakpoints is stored at the
1447 hwdebug_info struct. */
1448 total_hw_bp
= hwdebug_info
.num_instruction_bps
;
1449 total_hw_wp
= hwdebug_info
.num_data_bps
;
1453 /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1454 consider having 1 hardware watchpoint and no hardware breakpoints. */
1459 if (type
== bp_hardware_watchpoint
|| type
== bp_read_watchpoint
1460 || type
== bp_access_watchpoint
|| type
== bp_watchpoint
)
1462 if (cnt
+ ot
> total_hw_wp
)
1465 else if (type
== bp_hardware_breakpoint
)
1467 if (total_hw_bp
== 0)
1469 /* No hardware breakpoint support. */
1472 if (cnt
> total_hw_bp
)
1476 if (!have_ptrace_hwdebug_interface ())
1479 ptid_t ptid
= inferior_ptid
;
1481 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1482 and whether the target has DABR. If either answer is no, the
1483 ptrace call will return -1. Fail in that case. */
1484 tid
= ptid_get_lwp (ptid
);
1486 tid
= ptid_get_pid (ptid
);
1488 if (ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, 0) == -1)
1496 ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
1498 /* Handle sub-8-byte quantities. */
1502 /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1503 restrictions for watchpoints in the processors. In that case, we use that
1504 information to determine the hardcoded watchable region for
1506 if (have_ptrace_hwdebug_interface ())
1509 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1510 watchpoints and can watch any access within an arbitrary memory
1511 region. This is useful to watch arrays and structs, for instance. It
1512 takes two hardware watchpoints though. */
1514 && hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
1515 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1517 /* Check if the processor provides DAWR interface. */
1518 if (hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_DAWR
)
1519 /* DAWR interface allows to watch up to 512 byte wide ranges which
1520 can't cross a 512 byte boundary. */
1523 region_size
= hwdebug_info
.data_bp_alignment
;
1524 /* Server processors provide one hardware watchpoint and addr+len should
1525 fall in the watchable region provided by the ptrace interface. */
1527 && (addr
+ len
> (addr
& ~(region_size
- 1)) + region_size
))
1530 /* addr+len must fall in the 8 byte watchable region for DABR-based
1531 processors (i.e., server processors). Without the new PowerPC HWDEBUG
1532 ptrace interface, DAC-based processors (i.e., embedded processors) will
1533 use addresses aligned to 4-bytes due to the way the read/write flags are
1534 passed in the old ptrace interface. */
1535 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1536 && (addr
+ len
) > (addr
& ~3) + 4)
1537 || (addr
+ len
) > (addr
& ~7) + 8)
1543 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1545 hwdebug_point_cmp (struct ppc_hw_breakpoint
*a
, struct ppc_hw_breakpoint
*b
)
1547 return (a
->trigger_type
== b
->trigger_type
1548 && a
->addr_mode
== b
->addr_mode
1549 && a
->condition_mode
== b
->condition_mode
1550 && a
->addr
== b
->addr
1551 && a
->addr2
== b
->addr2
1552 && a
->condition_value
== b
->condition_value
);
1555 /* This function can be used to retrieve a thread_points by the TID of the
1556 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1557 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1558 provided TID will be created and returned. */
1559 static struct thread_points
*
1560 hwdebug_find_thread_points_by_tid (int tid
, int alloc_new
)
1563 struct thread_points
*t
;
1565 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, t
); i
++)
1571 /* Do we need to allocate a new point_item
1572 if the wanted one does not exist? */
1575 t
= XNEW (struct thread_points
);
1576 t
->hw_breaks
= XCNEWVEC (struct hw_break_tuple
, max_slots_number
);
1578 VEC_safe_push (thread_points_p
, ppc_threads
, t
);
1584 /* This function is a generic wrapper that is responsible for inserting a
1585 *point (i.e., calling `ptrace' in order to issue the request to the
1586 kernel) and registering it internally in GDB. */
1588 hwdebug_insert_point (struct ppc_hw_breakpoint
*b
, int tid
)
1592 gdb::unique_xmalloc_ptr
<ppc_hw_breakpoint
> p (XDUP (ppc_hw_breakpoint
, b
));
1593 struct hw_break_tuple
*hw_breaks
;
1594 struct thread_points
*t
;
1595 struct hw_break_tuple
*tuple
;
1598 slot
= ptrace (PPC_PTRACE_SETHWDEBUG
, tid
, 0, p
.get ());
1600 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1602 /* Everything went fine, so we have to register this *point. */
1603 t
= hwdebug_find_thread_points_by_tid (tid
, 1);
1604 gdb_assert (t
!= NULL
);
1605 hw_breaks
= t
->hw_breaks
;
1607 /* Find a free element in the hw_breaks vector. */
1608 for (i
= 0; i
< max_slots_number
; i
++)
1609 if (hw_breaks
[i
].hw_break
== NULL
)
1611 hw_breaks
[i
].slot
= slot
;
1612 hw_breaks
[i
].hw_break
= p
.release ();
1616 gdb_assert (i
!= max_slots_number
);
1619 /* This function is a generic wrapper that is responsible for removing a
1620 *point (i.e., calling `ptrace' in order to issue the request to the
1621 kernel), and unregistering it internally at GDB. */
1623 hwdebug_remove_point (struct ppc_hw_breakpoint
*b
, int tid
)
1626 struct hw_break_tuple
*hw_breaks
;
1627 struct thread_points
*t
;
1629 t
= hwdebug_find_thread_points_by_tid (tid
, 0);
1630 gdb_assert (t
!= NULL
);
1631 hw_breaks
= t
->hw_breaks
;
1633 for (i
= 0; i
< max_slots_number
; i
++)
1634 if (hw_breaks
[i
].hw_break
&& hwdebug_point_cmp (hw_breaks
[i
].hw_break
, b
))
1637 gdb_assert (i
!= max_slots_number
);
1639 /* We have to ignore ENOENT errors because the kernel implements hardware
1640 breakpoints/watchpoints as "one-shot", that is, they are automatically
1641 deleted when hit. */
1643 if (ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
) < 0)
1644 if (errno
!= ENOENT
)
1645 perror_with_name (_("Unexpected error deleting "
1646 "breakpoint or watchpoint"));
1648 xfree (hw_breaks
[i
].hw_break
);
1649 hw_breaks
[i
].hw_break
= NULL
;
1652 /* Return the number of registers needed for a ranged breakpoint. */
1655 ppc_linux_nat_target::ranged_break_num_registers ()
1657 return ((have_ptrace_hwdebug_interface ()
1658 && hwdebug_info
.features
& PPC_DEBUG_FEATURE_INSN_BP_RANGE
)?
1662 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1663 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1666 ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch
*gdbarch
,
1667 struct bp_target_info
*bp_tgt
)
1669 struct lwp_info
*lp
;
1670 struct ppc_hw_breakpoint p
;
1672 if (!have_ptrace_hwdebug_interface ())
1675 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1676 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1677 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1678 p
.addr
= (uint64_t) (bp_tgt
->placed_address
= bp_tgt
->reqstd_address
);
1679 p
.condition_value
= 0;
1683 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1685 /* The breakpoint will trigger if the address of the instruction is
1686 within the defined range, as follows: p.addr <= address < p.addr2. */
1687 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1691 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1696 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
1702 ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch
*gdbarch
,
1703 struct bp_target_info
*bp_tgt
)
1705 struct lwp_info
*lp
;
1706 struct ppc_hw_breakpoint p
;
1708 if (!have_ptrace_hwdebug_interface ())
1711 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1712 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1713 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1714 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1715 p
.condition_value
= 0;
1719 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1721 /* The breakpoint will trigger if the address of the instruction is within
1722 the defined range, as follows: p.addr <= address < p.addr2. */
1723 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1727 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1732 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
1738 get_trigger_type (enum target_hw_bp_type type
)
1742 if (type
== hw_read
)
1743 t
= PPC_BREAKPOINT_TRIGGER_READ
;
1744 else if (type
== hw_write
)
1745 t
= PPC_BREAKPOINT_TRIGGER_WRITE
;
1747 t
= PPC_BREAKPOINT_TRIGGER_READ
| PPC_BREAKPOINT_TRIGGER_WRITE
;
1752 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1753 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1754 or hw_access for an access watchpoint. Returns 0 on success and throws
1755 an error on failure. */
1758 ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr
, CORE_ADDR mask
,
1759 target_hw_bp_type rw
)
1761 struct lwp_info
*lp
;
1762 struct ppc_hw_breakpoint p
;
1764 gdb_assert (have_ptrace_hwdebug_interface ());
1766 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1767 p
.trigger_type
= get_trigger_type (rw
);
1768 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1769 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1772 p
.condition_value
= 0;
1775 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
1780 /* Remove a masked watchpoint at ADDR with the mask MASK.
1781 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1782 or hw_access for an access watchpoint. Returns 0 on success and throws
1783 an error on failure. */
1786 ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr
, CORE_ADDR mask
,
1787 target_hw_bp_type rw
)
1789 struct lwp_info
*lp
;
1790 struct ppc_hw_breakpoint p
;
1792 gdb_assert (have_ptrace_hwdebug_interface ());
1794 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1795 p
.trigger_type
= get_trigger_type (rw
);
1796 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1797 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1800 p
.condition_value
= 0;
1803 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
1808 /* Check whether we have at least one free DVC register. */
1810 can_use_watchpoint_cond_accel (void)
1812 struct thread_points
*p
;
1813 int tid
= ptid_get_lwp (inferior_ptid
);
1814 int cnt
= hwdebug_info
.num_condition_regs
, i
;
1815 CORE_ADDR tmp_value
;
1817 if (!have_ptrace_hwdebug_interface () || cnt
== 0)
1820 p
= hwdebug_find_thread_points_by_tid (tid
, 0);
1824 for (i
= 0; i
< max_slots_number
; i
++)
1825 if (p
->hw_breaks
[i
].hw_break
!= NULL
1826 && (p
->hw_breaks
[i
].hw_break
->condition_mode
1827 != PPC_BREAKPOINT_CONDITION_NONE
))
1830 /* There are no available slots now. */
1838 /* Calculate the enable bits and the contents of the Data Value Compare
1839 debug register present in BookE processors.
1841 ADDR is the address to be watched, LEN is the length of watched data
1842 and DATA_VALUE is the value which will trigger the watchpoint.
1843 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1844 CONDITION_VALUE will hold the value which should be put in the
1847 calculate_dvc (CORE_ADDR addr
, int len
, CORE_ADDR data_value
,
1848 uint32_t *condition_mode
, uint64_t *condition_value
)
1850 int i
, num_byte_enable
, align_offset
, num_bytes_off_dvc
,
1851 rightmost_enabled_byte
;
1852 CORE_ADDR addr_end_data
, addr_end_dvc
;
1854 /* The DVC register compares bytes within fixed-length windows which
1855 are word-aligned, with length equal to that of the DVC register.
1856 We need to calculate where our watch region is relative to that
1857 window and enable comparison of the bytes which fall within it. */
1859 align_offset
= addr
% hwdebug_info
.sizeof_condition
;
1860 addr_end_data
= addr
+ len
;
1861 addr_end_dvc
= (addr
- align_offset
1862 + hwdebug_info
.sizeof_condition
);
1863 num_bytes_off_dvc
= (addr_end_data
> addr_end_dvc
)?
1864 addr_end_data
- addr_end_dvc
: 0;
1865 num_byte_enable
= len
- num_bytes_off_dvc
;
1866 /* Here, bytes are numbered from right to left. */
1867 rightmost_enabled_byte
= (addr_end_data
< addr_end_dvc
)?
1868 addr_end_dvc
- addr_end_data
: 0;
1870 *condition_mode
= PPC_BREAKPOINT_CONDITION_AND
;
1871 for (i
= 0; i
< num_byte_enable
; i
++)
1873 |= PPC_BREAKPOINT_CONDITION_BE (i
+ rightmost_enabled_byte
);
1875 /* Now we need to match the position within the DVC of the comparison
1876 value with where the watch region is relative to the window
1877 (i.e., the ALIGN_OFFSET). */
1879 *condition_value
= ((uint64_t) data_value
>> num_bytes_off_dvc
* 8
1880 << rightmost_enabled_byte
* 8);
1883 /* Return the number of memory locations that need to be accessed to
1884 evaluate the expression which generated the given value chain.
1885 Returns -1 if there's any register access involved, or if there are
1886 other kinds of values which are not acceptable in a condition
1887 expression (e.g., lval_computed or lval_internalvar). */
1889 num_memory_accesses (const std::vector
<value_ref_ptr
> &chain
)
1891 int found_memory_cnt
= 0;
1893 /* The idea here is that evaluating an expression generates a series
1894 of values, one holding the value of every subexpression. (The
1895 expression a*b+c has five subexpressions: a, b, a*b, c, and
1896 a*b+c.) GDB's values hold almost enough information to establish
1897 the criteria given above --- they identify memory lvalues,
1898 register lvalues, computed values, etcetera. So we can evaluate
1899 the expression, and then scan the chain of values that leaves
1900 behind to determine the memory locations involved in the evaluation
1903 However, I don't think that the values returned by inferior
1904 function calls are special in any way. So this function may not
1905 notice that an expression contains an inferior function call.
1908 for (const value_ref_ptr
&iter
: chain
)
1910 struct value
*v
= iter
.get ();
1912 /* Constants and values from the history are fine. */
1913 if (VALUE_LVAL (v
) == not_lval
|| deprecated_value_modifiable (v
) == 0)
1915 else if (VALUE_LVAL (v
) == lval_memory
)
1917 /* A lazy memory lvalue is one that GDB never needed to fetch;
1918 we either just used its address (e.g., `a' in `a.b') or
1919 we never needed it at all (e.g., `a' in `a,b'). */
1920 if (!value_lazy (v
))
1923 /* Other kinds of values are not fine. */
1928 return found_memory_cnt
;
1931 /* Verifies whether the expression COND can be implemented using the
1932 DVC (Data Value Compare) register in BookE processors. The expression
1933 must test the watch value for equality with a constant expression.
1934 If the function returns 1, DATA_VALUE will contain the constant against
1935 which the watch value should be compared and LEN will contain the size
1938 check_condition (CORE_ADDR watch_addr
, struct expression
*cond
,
1939 CORE_ADDR
*data_value
, int *len
)
1941 int pc
= 1, num_accesses_left
, num_accesses_right
;
1942 struct value
*left_val
, *right_val
;
1943 std::vector
<value_ref_ptr
> left_chain
, right_chain
;
1945 if (cond
->elts
[0].opcode
!= BINOP_EQUAL
)
1948 fetch_subexp_value (cond
, &pc
, &left_val
, NULL
, &left_chain
, 0);
1949 num_accesses_left
= num_memory_accesses (left_chain
);
1951 if (left_val
== NULL
|| num_accesses_left
< 0)
1954 fetch_subexp_value (cond
, &pc
, &right_val
, NULL
, &right_chain
, 0);
1955 num_accesses_right
= num_memory_accesses (right_chain
);
1957 if (right_val
== NULL
|| num_accesses_right
< 0)
1960 if (num_accesses_left
== 1 && num_accesses_right
== 0
1961 && VALUE_LVAL (left_val
) == lval_memory
1962 && value_address (left_val
) == watch_addr
)
1964 *data_value
= value_as_long (right_val
);
1966 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1967 the same type as the memory region referenced by LEFT_VAL. */
1968 *len
= TYPE_LENGTH (check_typedef (value_type (left_val
)));
1970 else if (num_accesses_left
== 0 && num_accesses_right
== 1
1971 && VALUE_LVAL (right_val
) == lval_memory
1972 && value_address (right_val
) == watch_addr
)
1974 *data_value
= value_as_long (left_val
);
1976 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1977 the same type as the memory region referenced by RIGHT_VAL. */
1978 *len
= TYPE_LENGTH (check_typedef (value_type (right_val
)));
1986 /* Return non-zero if the target is capable of using hardware to evaluate
1987 the condition expression, thus only triggering the watchpoint when it is
1990 ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr
, int len
,
1992 struct expression
*cond
)
1994 CORE_ADDR data_value
;
1996 return (have_ptrace_hwdebug_interface ()
1997 && hwdebug_info
.num_condition_regs
> 0
1998 && check_condition (addr
, cond
, &data_value
, &len
));
2001 /* Set up P with the parameters necessary to request a watchpoint covering
2002 LEN bytes starting at ADDR and if possible with condition expression COND
2003 evaluated by hardware. INSERT tells if we are creating a request for
2004 inserting or removing the watchpoint. */
2007 create_watchpoint_request (struct ppc_hw_breakpoint
*p
, CORE_ADDR addr
,
2008 int len
, enum target_hw_bp_type type
,
2009 struct expression
*cond
, int insert
)
2012 || !(hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
))
2015 CORE_ADDR data_value
;
2017 use_condition
= (insert
? can_use_watchpoint_cond_accel ()
2018 : hwdebug_info
.num_condition_regs
> 0);
2019 if (cond
&& use_condition
&& check_condition (addr
, cond
,
2021 calculate_dvc (addr
, len
, data_value
, &p
->condition_mode
,
2022 &p
->condition_value
);
2025 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2026 p
->condition_value
= 0;
2029 p
->addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
2034 p
->addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
2035 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2036 p
->condition_value
= 0;
2038 /* The watchpoint will trigger if the address of the memory access is
2039 within the defined range, as follows: p->addr <= address < p->addr2.
2041 Note that the above sentence just documents how ptrace interprets
2042 its arguments; the watchpoint is set to watch the range defined by
2043 the user _inclusively_, as specified by the user interface. */
2044 p
->addr2
= (uint64_t) addr
+ len
;
2047 p
->version
= PPC_DEBUG_CURRENT_VERSION
;
2048 p
->trigger_type
= get_trigger_type (type
);
2049 p
->addr
= (uint64_t) addr
;
2053 ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr
, int len
,
2054 enum target_hw_bp_type type
,
2055 struct expression
*cond
)
2057 struct lwp_info
*lp
;
2060 if (have_ptrace_hwdebug_interface ())
2062 struct ppc_hw_breakpoint p
;
2064 create_watchpoint_request (&p
, addr
, len
, type
, cond
, 1);
2067 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
2074 long read_mode
, write_mode
;
2076 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2078 /* PowerPC 440 requires only the read/write flags to be passed
2085 /* PowerPC 970 and other DABR-based processors are required to pass
2086 the Breakpoint Translation bit together with the flags. */
2091 dabr_value
= addr
& ~(read_mode
| write_mode
);
2095 /* Set read and translate bits. */
2096 dabr_value
|= read_mode
;
2099 /* Set write and translate bits. */
2100 dabr_value
|= write_mode
;
2103 /* Set read, write and translate bits. */
2104 dabr_value
|= read_mode
| write_mode
;
2108 saved_dabr_value
= dabr_value
;
2111 if (ptrace (PTRACE_SET_DEBUGREG
, ptid_get_lwp (lp
->ptid
), 0,
2112 saved_dabr_value
) < 0)
2122 ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr
, int len
,
2123 enum target_hw_bp_type type
,
2124 struct expression
*cond
)
2126 struct lwp_info
*lp
;
2129 if (have_ptrace_hwdebug_interface ())
2131 struct ppc_hw_breakpoint p
;
2133 create_watchpoint_request (&p
, addr
, len
, type
, cond
, 0);
2136 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
2142 saved_dabr_value
= 0;
2144 if (ptrace (PTRACE_SET_DEBUGREG
, ptid_get_lwp (lp
->ptid
), 0,
2145 saved_dabr_value
) < 0)
2155 ppc_linux_new_thread (struct lwp_info
*lp
)
2157 int tid
= ptid_get_lwp (lp
->ptid
);
2159 if (have_ptrace_hwdebug_interface ())
2162 struct thread_points
*p
;
2163 struct hw_break_tuple
*hw_breaks
;
2165 if (VEC_empty (thread_points_p
, ppc_threads
))
2168 /* Get a list of breakpoints from any thread. */
2169 p
= VEC_last (thread_points_p
, ppc_threads
);
2170 hw_breaks
= p
->hw_breaks
;
2172 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2173 for (i
= 0; i
< max_slots_number
; i
++)
2174 if (hw_breaks
[i
].hw_break
)
2176 /* Older kernels did not make new threads inherit their parent
2177 thread's debug state, so we always clear the slot and replicate
2178 the debug state ourselves, ensuring compatibility with all
2181 /* The ppc debug resource accounting is done through "slots".
2182 Ask the kernel the deallocate this specific *point's slot. */
2183 ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
);
2185 hwdebug_insert_point (hw_breaks
[i
].hw_break
, tid
);
2189 ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, saved_dabr_value
);
2193 ppc_linux_thread_exit (struct thread_info
*tp
, int silent
)
2196 int tid
= ptid_get_lwp (tp
->ptid
);
2197 struct hw_break_tuple
*hw_breaks
;
2198 struct thread_points
*t
= NULL
, *p
;
2200 if (!have_ptrace_hwdebug_interface ())
2203 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, p
); i
++)
2213 VEC_unordered_remove (thread_points_p
, ppc_threads
, i
);
2215 hw_breaks
= t
->hw_breaks
;
2217 for (i
= 0; i
< max_slots_number
; i
++)
2218 if (hw_breaks
[i
].hw_break
)
2219 xfree (hw_breaks
[i
].hw_break
);
2221 xfree (t
->hw_breaks
);
2226 ppc_linux_nat_target::stopped_data_address (CORE_ADDR
*addr_p
)
2230 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
2233 if (siginfo
.si_signo
!= SIGTRAP
2234 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2237 if (have_ptrace_hwdebug_interface ())
2240 struct thread_points
*t
;
2241 struct hw_break_tuple
*hw_breaks
;
2242 /* The index (or slot) of the *point is passed in the si_errno field. */
2243 int slot
= siginfo
.si_errno
;
2245 t
= hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid
), 0);
2247 /* Find out if this *point is a hardware breakpoint.
2248 If so, we should return 0. */
2251 hw_breaks
= t
->hw_breaks
;
2252 for (i
= 0; i
< max_slots_number
; i
++)
2253 if (hw_breaks
[i
].hw_break
&& hw_breaks
[i
].slot
== slot
2254 && hw_breaks
[i
].hw_break
->trigger_type
2255 == PPC_BREAKPOINT_TRIGGER_EXECUTE
)
2260 *addr_p
= (CORE_ADDR
) (uintptr_t) siginfo
.si_addr
;
2265 ppc_linux_nat_target::stopped_by_watchpoint ()
2268 return stopped_data_address (&addr
);
2272 ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr
,
2278 if (have_ptrace_hwdebug_interface ()
2279 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2280 return start
<= addr
&& start
+ length
>= addr
;
2281 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2288 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2289 return start
<= addr
+ mask
&& start
+ length
- 1 >= addr
;
2292 /* Return the number of registers needed for a masked hardware watchpoint. */
2295 ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr
, CORE_ADDR mask
)
2297 if (!have_ptrace_hwdebug_interface ()
2298 || (hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_MASK
) == 0)
2300 else if ((mask
& 0xC0000000) != 0xC0000000)
2302 warning (_("The given mask covers kernel address space "
2303 "and cannot be used.\n"));
2312 ppc_linux_nat_target::store_registers (struct regcache
*regcache
, int regno
)
2314 pid_t tid
= get_ptrace_pid (regcache_get_ptid (regcache
));
2317 store_register (regcache
, tid
, regno
);
2319 store_ppc_registers (regcache
, tid
);
2322 /* Functions for transferring registers between a gregset_t or fpregset_t
2323 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2324 by the ptrace interface, not the current program's ABI. Eg. if a
2325 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2326 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2329 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
2331 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2333 ppc_supply_gregset (regset
, regcache
, -1, gregsetp
, sizeof (*gregsetp
));
2337 fill_gregset (const struct regcache
*regcache
,
2338 gdb_gregset_t
*gregsetp
, int regno
)
2340 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2343 memset (gregsetp
, 0, sizeof (*gregsetp
));
2344 ppc_collect_gregset (regset
, regcache
, regno
, gregsetp
, sizeof (*gregsetp
));
2348 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
* fpregsetp
)
2350 const struct regset
*regset
= ppc_linux_fpregset ();
2352 ppc_supply_fpregset (regset
, regcache
, -1,
2353 fpregsetp
, sizeof (*fpregsetp
));
2357 fill_fpregset (const struct regcache
*regcache
,
2358 gdb_fpregset_t
*fpregsetp
, int regno
)
2360 const struct regset
*regset
= ppc_linux_fpregset ();
2362 ppc_collect_fpregset (regset
, regcache
, regno
,
2363 fpregsetp
, sizeof (*fpregsetp
));
2367 ppc_linux_target_wordsize (void)
2371 /* Check for 64-bit inferior process. This is the case when the host is
2372 64-bit, and in addition the top bit of the MSR register is set. */
2373 #ifdef __powerpc64__
2376 int tid
= ptid_get_lwp (inferior_ptid
);
2378 tid
= ptid_get_pid (inferior_ptid
);
2381 msr
= (long) ptrace (PTRACE_PEEKUSER
, tid
, PT_MSR
* 8, 0);
2382 if (errno
== 0 && ppc64_64bit_inferior_p (msr
))
2390 ppc_linux_nat_target::auxv_parse (gdb_byte
**readptr
,
2391 gdb_byte
*endptr
, CORE_ADDR
*typep
,
2394 int sizeof_auxv_field
= ppc_linux_target_wordsize ();
2395 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
2396 gdb_byte
*ptr
= *readptr
;
2401 if (endptr
- ptr
< sizeof_auxv_field
* 2)
2404 *typep
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2405 ptr
+= sizeof_auxv_field
;
2406 *valp
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2407 ptr
+= sizeof_auxv_field
;
2413 const struct target_desc
*
2414 ppc_linux_nat_target::read_description ()
2421 int tid
= ptid_get_lwp (inferior_ptid
);
2423 tid
= ptid_get_pid (inferior_ptid
);
2425 if (have_ptrace_getsetevrregs
)
2427 struct gdb_evrregset_t evrregset
;
2429 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, &evrregset
) >= 0)
2430 return tdesc_powerpc_e500l
;
2432 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2433 Anything else needs to be reported. */
2434 else if (errno
!= EIO
)
2435 perror_with_name (_("Unable to fetch SPE registers"));
2438 if (have_ptrace_getsetvsxregs
2439 && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_VSX
))
2441 gdb_vsxregset_t vsxregset
;
2443 if (ptrace (PTRACE_GETVSXREGS
, tid
, 0, &vsxregset
) >= 0)
2446 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2447 Anything else needs to be reported. */
2448 else if (errno
!= EIO
)
2449 perror_with_name (_("Unable to fetch VSX registers"));
2452 if (have_ptrace_getvrregs
2453 && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_ALTIVEC
))
2455 gdb_vrregset_t vrregset
;
2457 if (ptrace (PTRACE_GETVRREGS
, tid
, 0, &vrregset
) >= 0)
2460 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2461 Anything else needs to be reported. */
2462 else if (errno
!= EIO
)
2463 perror_with_name (_("Unable to fetch AltiVec registers"));
2466 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2467 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2468 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2469 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2470 half of the register are for Decimal Floating Point, we check if that
2471 feature is available to decide the size of the FPSCR. */
2472 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP
)
2475 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL
)
2478 if (ppc_linux_target_wordsize () == 8)
2481 return tdesc_powerpc_cell64l
;
2483 return isa205
? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l
;
2486 ? tdesc_powerpc_isa205_altivec64l
: tdesc_powerpc_altivec64l
;
2488 return isa205
? tdesc_powerpc_isa205_64l
: tdesc_powerpc_64l
;
2492 return tdesc_powerpc_cell32l
;
2494 return isa205
? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l
;
2496 return isa205
? tdesc_powerpc_isa205_altivec32l
: tdesc_powerpc_altivec32l
;
2498 return isa205
? tdesc_powerpc_isa205_32l
: tdesc_powerpc_32l
;
2502 _initialize_ppc_linux_nat (void)
2504 linux_target
= &the_ppc_linux_nat_target
;
2506 gdb::observers::thread_exit
.attach (ppc_linux_thread_exit
);
2508 /* Register the target. */
2509 add_target (linux_target
);
2511 linux_nat_set_new_thread (linux_target
, ppc_linux_new_thread
);