gdb/ppc-tdep.h

   1 /* Target-dependent code for GDB, the GNU debugger.
   2
   3    Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef PPC_TDEP_H
  22 #define PPC_TDEP_H
  23
  24 struct gdbarch;
  25 struct frame_info;
  26 struct value;
  27 struct regcache;
  28 struct type;
  29
  30 /* From ppc-linux-tdep.c... */
  31 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
  32                                                         struct type *valtype,
  33                                                         struct regcache *regcache,
  34                                                         gdb_byte *readbuf,
  35                                                         const gdb_byte *writebuf);
  36 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
  37                                                                struct type *valtype,
  38                                                                struct regcache *regcache,
  39                                                                gdb_byte *readbuf,
  40                                                                const gdb_byte *writebuf);
  41 CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
  42                                         struct value *function,
  43                                         struct regcache *regcache,
  44                                         CORE_ADDR bp_addr, int nargs,
  45                                         struct value **args, CORE_ADDR sp,
  46                                         int struct_return,
  47                                         CORE_ADDR struct_addr);
  48 CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
  49                                           struct value *function,
  50                                           struct regcache *regcache,
  51                                           CORE_ADDR bp_addr, int nargs,
  52                                           struct value **args, CORE_ADDR sp,
  53                                           int struct_return,
  54                                           CORE_ADDR struct_addr);
  55 CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
  56                                                     CORE_ADDR bpaddr);
  57 int ppc_linux_memory_remove_breakpoint (struct bp_target_info *bp_tgt);
  58 struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
  59 const struct regset *ppc_linux_gregset (int);
  60 const struct regset *ppc_linux_fpregset (void);
  61
  62 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
  63                                                           struct type *valtype,
  64                                                           struct regcache *regcache,
  65                                                           gdb_byte *readbuf,
  66                                                           const gdb_byte *writebuf);
  67
  68 /* From rs6000-tdep.c... */
  69 int altivec_register_p (int regno);
  70 int spe_register_p (int regno);
  71
  72 /* Return non-zero if the architecture described by GDBARCH has
  73    floating-point registers (f0 --- f31 and fpscr).  */
  74 int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
  75
  76 /* Register set description.  */
  77
  78 struct ppc_reg_offsets
  79 {
  80   /* General-purpose registers.  */
  81   int r0_offset;
  82   int gpr_size; /* size for r0-31, pc, ps, lr, ctr.  */
  83   int xr_size;  /* size for cr, xer, mq.  */
  84   int pc_offset;
  85   int ps_offset;
  86   int cr_offset;
  87   int lr_offset;
  88   int ctr_offset;
  89   int xer_offset;
  90   int mq_offset;
  91
  92   /* Floating-point registers.  */
  93   int f0_offset;
  94   int fpscr_offset;
  95   int fpscr_size;
  96
  97   /* AltiVec registers.  */
  98   int vr0_offset;
  99   int vscr_offset;
 100   int vrsave_offset;
 101 };
 102
 103 /* Supply register REGNUM in the general-purpose register set REGSET
 104    from the buffer specified by GREGS and LEN to register cache
 105    REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
 106
 107 extern void ppc_supply_gregset (const struct regset *regset,
 108                                 struct regcache *regcache,
 109                                 int regnum, const void *gregs, size_t len);
 110
 111 /* Supply register REGNUM in the floating-point register set REGSET
 112    from the buffer specified by FPREGS and LEN to register cache
 113    REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
 114
 115 extern void ppc_supply_fpregset (const struct regset *regset,
 116                                  struct regcache *regcache,
 117                                  int regnum, const void *fpregs, size_t len);
 118
 119 /* Collect register REGNUM in the general-purpose register set
 120    REGSET. from register cache REGCACHE into the buffer specified by
 121    GREGS and LEN.  If REGNUM is -1, do this for all registers in
 122    REGSET.  */
 123
 124 extern void ppc_collect_gregset (const struct regset *regset,
 125                                  const struct regcache *regcache,
 126                                  int regnum, void *gregs, size_t len);
 127
 128 /* Collect register REGNUM in the floating-point register set
 129    REGSET. from register cache REGCACHE into the buffer specified by
 130    FPREGS and LEN.  If REGNUM is -1, do this for all registers in
 131    REGSET.  */
 132
 133 extern void ppc_collect_fpregset (const struct regset *regset,
 134                                   const struct regcache *regcache,
 135                                   int regnum, void *fpregs, size_t len);
 136
 137 /* Private data that this module attaches to struct gdbarch. */
 138
 139 struct gdbarch_tdep
 140   {
 141     int wordsize;              /* size in bytes of fixed-point word */
 142     const struct reg *regs;    /* from current variant */
 143     int ppc_gp0_regnum;         /* GPR register 0 */
 144     int ppc_toc_regnum;         /* TOC register */
 145     int ppc_ps_regnum;          /* Processor (or machine) status (%msr) */
 146     int ppc_cr_regnum;          /* Condition register */
 147     int ppc_lr_regnum;          /* Link register */
 148     int ppc_ctr_regnum;         /* Count register */
 149     int ppc_xer_regnum;         /* Integer exception register */
 150
 151     /* Not all PPC and RS6000 variants will have the registers
 152        represented below.  A -1 is used to indicate that the register
 153        is not present in this variant.  */
 154
 155     /* Floating-point registers.  */
 156     int ppc_fp0_regnum;         /* floating-point register 0 */
 157     int ppc_fpscr_regnum;       /* fp status and condition register */
 158
 159     /* Segment registers.  */
 160     int ppc_sr0_regnum;         /* segment register 0 */
 161
 162     /* Multiplier-Quotient Register (older POWER architectures only).  */
 163     int ppc_mq_regnum;
 164
 165     /* Altivec registers.  */
 166     int ppc_vr0_regnum;         /* First AltiVec register */
 167     int ppc_vrsave_regnum;      /* Last AltiVec register */
 168
 169     /* SPE registers.  */
 170     int ppc_ev0_upper_regnum;   /* First GPR upper half register */
 171     int ppc_ev0_regnum;         /* First ev register */
 172     int ppc_ev31_regnum;        /* Last ev register */
 173     int ppc_acc_regnum;         /* SPE 'acc' register */
 174     int ppc_spefscr_regnum;     /* SPE 'spefscr' register */
 175
 176     /* Offset to ABI specific location where link register is saved.  */
 177     int lr_frame_offset;
 178
 179     /* An array of integers, such that sim_regno[I] is the simulator
 180        register number for GDB register number I, or -1 if the
 181        simulator does not implement that register.  */
 182     int *sim_regno;
 183
 184     /* Minimum possible text address.  */
 185     CORE_ADDR text_segment_base;
 186
 187     /* ISA-specific types.  */
 188     struct type *ppc_builtin_type_vec64;
 189     struct type *ppc_builtin_type_vec128;
 190 };
 191
 192
 193 /* Constants for register set sizes.  */
 194 enum
 195   {
 196     ppc_num_gprs = 32,          /* 32 general-purpose registers */
 197     ppc_num_fprs = 32,          /* 32 floating-point registers */
 198     ppc_num_srs = 16,           /* 16 segment registers */
 199     ppc_num_vrs = 32            /* 32 Altivec vector registers */
 200   };
 201
 202
 203 /* Constants for SPR register numbers.  These are *not* GDB register
 204    numbers: they are the numbers used in the PowerPC ISA itself to
 205    refer to these registers.
 206
 207    This table includes all the SPRs from all the variants I could find
 208    documentation for.
 209
 210    There may be registers from different PowerPC variants assigned the
 211    same number, but that's fine: GDB and the SIM always use the
 212    numbers in the context of a particular variant, so it's not
 213    ambiguous.
 214
 215    We need to deviate from the naming pattern when variants have
 216    special-purpose registers of the same name, but with different
 217    numbers.  Fortunately, this is rare: look below to see how we
 218    handle the 'tcr' registers on the 403/403GX and 602.  */
 219
 220 enum
 221   {
 222     ppc_spr_mq        =    0,
 223     ppc_spr_xer       =    1,
 224     ppc_spr_rtcu      =    4,
 225     ppc_spr_rtcl      =    5,
 226     ppc_spr_lr        =    8,
 227     ppc_spr_ctr       =    9,
 228     ppc_spr_cnt       =    9,
 229     ppc_spr_dsisr     =   18,
 230     ppc_spr_dar       =   19,
 231     ppc_spr_dec       =   22,
 232     ppc_spr_sdr1      =   25,
 233     ppc_spr_srr0      =   26,
 234     ppc_spr_srr1      =   27,
 235     ppc_spr_eie       =   80,
 236     ppc_spr_eid       =   81,
 237     ppc_spr_nri       =   82,
 238     ppc_spr_sp        =  102,
 239     ppc_spr_cmpa      =  144,
 240     ppc_spr_cmpb      =  145,
 241     ppc_spr_cmpc      =  146,
 242     ppc_spr_cmpd      =  147,
 243     ppc_spr_icr       =  148,
 244     ppc_spr_der       =  149,
 245     ppc_spr_counta    =  150,
 246     ppc_spr_countb    =  151,
 247     ppc_spr_cmpe      =  152,
 248     ppc_spr_cmpf      =  153,
 249     ppc_spr_cmpg      =  154,
 250     ppc_spr_cmph      =  155,
 251     ppc_spr_lctrl1    =  156,
 252     ppc_spr_lctrl2    =  157,
 253     ppc_spr_ictrl     =  158,
 254     ppc_spr_bar       =  159,
 255     ppc_spr_vrsave    =  256,
 256     ppc_spr_sprg0     =  272,
 257     ppc_spr_sprg1     =  273,
 258     ppc_spr_sprg2     =  274,
 259     ppc_spr_sprg3     =  275,
 260     ppc_spr_asr       =  280,
 261     ppc_spr_ear       =  282,
 262     ppc_spr_tbl       =  284,
 263     ppc_spr_tbu       =  285,
 264     ppc_spr_pvr       =  287,
 265     ppc_spr_spefscr   =  512,
 266     ppc_spr_ibat0u    =  528,
 267     ppc_spr_ibat0l    =  529,
 268     ppc_spr_ibat1u    =  530,
 269     ppc_spr_ibat1l    =  531,
 270     ppc_spr_ibat2u    =  532,
 271     ppc_spr_ibat2l    =  533,
 272     ppc_spr_ibat3u    =  534,
 273     ppc_spr_ibat3l    =  535,
 274     ppc_spr_dbat0u    =  536,
 275     ppc_spr_dbat0l    =  537,
 276     ppc_spr_dbat1u    =  538,
 277     ppc_spr_dbat1l    =  539,
 278     ppc_spr_dbat2u    =  540,
 279     ppc_spr_dbat2l    =  541,
 280     ppc_spr_dbat3u    =  542,
 281     ppc_spr_dbat3l    =  543,
 282     ppc_spr_ic_cst    =  560,
 283     ppc_spr_ic_adr    =  561,
 284     ppc_spr_ic_dat    =  562,
 285     ppc_spr_dc_cst    =  568,
 286     ppc_spr_dc_adr    =  569,
 287     ppc_spr_dc_dat    =  570,
 288     ppc_spr_dpdr      =  630,
 289     ppc_spr_dpir      =  631,
 290     ppc_spr_immr      =  638,
 291     ppc_spr_mi_ctr    =  784,
 292     ppc_spr_mi_ap     =  786,
 293     ppc_spr_mi_epn    =  787,
 294     ppc_spr_mi_twc    =  789,
 295     ppc_spr_mi_rpn    =  790,
 296     ppc_spr_mi_cam    =  816,
 297     ppc_spr_mi_ram0   =  817,
 298     ppc_spr_mi_ram1   =  818,
 299     ppc_spr_md_ctr    =  792,
 300     ppc_spr_m_casid   =  793,
 301     ppc_spr_md_ap     =  794,
 302     ppc_spr_md_epn    =  795,
 303     ppc_spr_m_twb     =  796,
 304     ppc_spr_md_twc    =  797,
 305     ppc_spr_md_rpn    =  798,
 306     ppc_spr_m_tw      =  799,
 307     ppc_spr_mi_dbcam  =  816,
 308     ppc_spr_mi_dbram0 =  817,
 309     ppc_spr_mi_dbram1 =  818,
 310     ppc_spr_md_dbcam  =  824,
 311     ppc_spr_md_cam    =  824,
 312     ppc_spr_md_dbram0 =  825,
 313     ppc_spr_md_ram0   =  825,
 314     ppc_spr_md_dbram1 =  826,
 315     ppc_spr_md_ram1   =  826,
 316     ppc_spr_ummcr0    =  936,
 317     ppc_spr_upmc1     =  937,
 318     ppc_spr_upmc2     =  938,
 319     ppc_spr_usia      =  939,
 320     ppc_spr_ummcr1    =  940,
 321     ppc_spr_upmc3     =  941,
 322     ppc_spr_upmc4     =  942,
 323     ppc_spr_zpr       =  944,
 324     ppc_spr_pid       =  945,
 325     ppc_spr_mmcr0     =  952,
 326     ppc_spr_pmc1      =  953,
 327     ppc_spr_sgr       =  953,
 328     ppc_spr_pmc2      =  954,
 329     ppc_spr_dcwr      =  954,
 330     ppc_spr_sia       =  955,
 331     ppc_spr_mmcr1     =  956,
 332     ppc_spr_pmc3      =  957,
 333     ppc_spr_pmc4      =  958,
 334     ppc_spr_sda       =  959,
 335     ppc_spr_tbhu      =  972,
 336     ppc_spr_tblu      =  973,
 337     ppc_spr_dmiss     =  976,
 338     ppc_spr_dcmp      =  977,
 339     ppc_spr_hash1     =  978,
 340     ppc_spr_hash2     =  979,
 341     ppc_spr_icdbdr    =  979,
 342     ppc_spr_imiss     =  980,
 343     ppc_spr_esr       =  980,
 344     ppc_spr_icmp      =  981,
 345     ppc_spr_dear      =  981,
 346     ppc_spr_rpa       =  982,
 347     ppc_spr_evpr      =  982,
 348     ppc_spr_cdbcr     =  983,
 349     ppc_spr_tsr       =  984,
 350     ppc_spr_602_tcr   =  984,
 351     ppc_spr_403_tcr   =  986,
 352     ppc_spr_ibr       =  986,
 353     ppc_spr_pit       =  987,
 354     ppc_spr_esasrr    =  988,
 355     ppc_spr_tbhi      =  988,
 356     ppc_spr_tblo      =  989,
 357     ppc_spr_srr2      =  990,
 358     ppc_spr_sebr      =  990,
 359     ppc_spr_srr3      =  991,
 360     ppc_spr_ser       =  991,
 361     ppc_spr_hid0      = 1008,
 362     ppc_spr_dbsr      = 1008,
 363     ppc_spr_hid1      = 1009,
 364     ppc_spr_iabr      = 1010,
 365     ppc_spr_dbcr      = 1010,
 366     ppc_spr_iac1      = 1012,
 367     ppc_spr_dabr      = 1013,
 368     ppc_spr_iac2      = 1013,
 369     ppc_spr_dac1      = 1014,
 370     ppc_spr_dac2      = 1015,
 371     ppc_spr_l2cr      = 1017,
 372     ppc_spr_dccr      = 1018,
 373     ppc_spr_ictc      = 1019,
 374     ppc_spr_iccr      = 1019,
 375     ppc_spr_thrm1     = 1020,
 376     ppc_spr_pbl1      = 1020,
 377     ppc_spr_thrm2     = 1021,
 378     ppc_spr_pbu1      = 1021,
 379     ppc_spr_thrm3     = 1022,
 380     ppc_spr_pbl2      = 1022,
 381     ppc_spr_fpecr     = 1022,
 382     ppc_spr_lt        = 1022,
 383     ppc_spr_pir       = 1023,
 384     ppc_spr_pbu2      = 1023
 385   };
 386
 387 /* Instruction size.  */
 388 #define PPC_INSN_SIZE 4
 389
 390 /* Estimate for the maximum number of instrctions in a function epilogue.  */
 391 #define PPC_MAX_EPILOGUE_INSTRUCTIONS  52
 392
 393 #endif /* ppc-tdep.h */