1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2/frame.h"
51 #include "user-regs.h"
53 #include "gdbsupport/common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
59 #include "riscv-ravenscar-thread.h"
61 /* The stack must be 16-byte aligned. */
62 #define SP_ALIGNMENT 16
64 /* The biggest alignment that the target supports. */
65 #define BIGGEST_ALIGNMENT 16
67 /* Define a series of is_XXX_insn functions to check if the value INSN
68 is an instance of instruction XXX. */
69 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
70 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
72 return (insn & INSN_MASK) == INSN_MATCH; \
74 #include "opcode/riscv-opc.h"
77 /* Cached information about a frame. */
79 struct riscv_unwind_cache
81 /* The register from which we can calculate the frame base. This is
82 usually $sp or $fp. */
85 /* The offset from the current value in register FRAME_BASE_REG to the
86 actual frame base address. */
87 int frame_base_offset
;
89 /* Information about previous register values. */
90 struct trad_frame_saved_reg
*regs
;
92 /* The id for this frame. */
93 struct frame_id this_id
;
95 /* The base (stack) address for this frame. This is the stack pointer
96 value on entry to this frame before any adjustments are made. */
100 /* RISC-V specific register group for CSRs. */
102 static reggroup
*csr_reggroup
= NULL
;
104 /* A set of registers that we expect to find in a tdesc_feature. These
105 are use in RISCV_GDBARCH_INIT when processing the target description. */
107 struct riscv_register_feature
109 /* Information for a single register. */
112 /* The GDB register number for this register. */
115 /* List of names for this register. The first name in this list is the
116 preferred name, the name GDB should use when describing this
118 std::vector
<const char *> names
;
120 /* When true this register is required in this feature set. */
124 /* The name for this feature. This is the name used to find this feature
125 within the target description. */
128 /* List of all the registers that we expect that we might find in this
130 std::vector
<struct register_info
> registers
;
133 /* The general x-registers feature set. */
135 static const struct riscv_register_feature riscv_xreg_feature
=
137 "org.gnu.gdb.riscv.cpu",
139 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" }, true },
140 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" }, true },
141 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" }, true },
142 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" }, true },
143 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" }, true },
144 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" }, true },
145 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" }, true },
146 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" }, true },
147 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" }, true },
148 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" }, true },
149 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" }, true },
150 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" }, true },
151 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" }, true },
152 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" }, true },
153 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" }, true },
154 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" }, true },
155 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" }, true },
156 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" }, true },
157 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" }, true },
158 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" }, true },
159 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" }, true },
160 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" }, true },
161 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" }, true },
162 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" }, true },
163 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" }, true },
164 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" }, true },
165 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" }, true },
166 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" }, true },
167 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" }, true },
168 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" }, true },
169 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" }, true },
170 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" }, true },
171 { RISCV_ZERO_REGNUM
+ 32, { "pc" }, true }
175 /* The f-registers feature set. */
177 static const struct riscv_register_feature riscv_freg_feature
=
179 "org.gnu.gdb.riscv.fpu",
181 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" }, true },
182 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" }, true },
183 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" }, true },
184 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" }, true },
185 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" }, true },
186 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" }, true },
187 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" }, true },
188 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" }, true },
189 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8" }, true },
190 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" }, true },
191 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" }, true },
192 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" }, true },
193 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" }, true },
194 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" }, true },
195 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" }, true },
196 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" }, true },
197 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" }, true },
198 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" }, true },
199 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" }, true },
200 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" }, true },
201 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" }, true },
202 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" }, true },
203 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" }, true },
204 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" }, true },
205 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" }, true },
206 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" }, true },
207 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" }, true },
208 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" }, true },
209 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" }, true },
210 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" }, true },
211 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" }, true },
212 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" }, true },
214 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags" }, true },
215 { RISCV_CSR_FRM_REGNUM
, { "frm" }, true },
216 { RISCV_CSR_FCSR_REGNUM
, { "fcsr" }, true },
221 /* Set of virtual registers. These are not physical registers on the
222 hardware, but might be available from the target. These are not pseudo
223 registers, reading these really does result in a register read from the
224 target, it is just that there might not be a physical register backing
227 static const struct riscv_register_feature riscv_virtual_feature
=
229 "org.gnu.gdb.riscv.virtual",
231 { RISCV_PRIV_REGNUM
, { "priv" }, false }
235 /* Feature set for CSRs. This set is NOT constant as the register names
236 list for each register is not complete. The aliases are computed
237 during RISCV_CREATE_CSR_ALIASES. */
239 static struct riscv_register_feature riscv_csr_feature
=
241 "org.gnu.gdb.riscv.csr",
243 #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
244 { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
245 #include "opcode/riscv-opc.h"
250 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
251 to the name list for each register. */
254 riscv_create_csr_aliases ()
256 for (auto ®
: riscv_csr_feature
.registers
)
258 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
259 const char *alias
= xstrprintf ("csr%d", csr_num
);
260 reg
.names
.push_back (alias
);
264 /* Controls whether we place compressed breakpoints or not. When in auto
265 mode GDB tries to determine if the target supports compressed
266 breakpoints, and uses them if it does. */
268 static enum auto_boolean use_compressed_breakpoints
;
270 /* The show callback for 'show riscv use-compressed-breakpoints'. */
273 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
274 struct cmd_list_element
*c
,
277 fprintf_filtered (file
,
278 _("Debugger's use of compressed breakpoints is set "
282 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
284 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
285 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
287 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
289 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
290 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
292 /* The show callback for all 'show debug riscv VARNAME' variables. */
295 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
296 struct cmd_list_element
*c
,
299 fprintf_filtered (file
,
300 _("RiscV debug variable `%s' is set to: %s\n"),
304 /* When this is set to non-zero debugging information about breakpoint
305 kinds will be printed. */
307 static unsigned int riscv_debug_breakpoints
= 0;
309 /* When this is set to non-zero debugging information about inferior calls
312 static unsigned int riscv_debug_infcall
= 0;
314 /* When this is set to non-zero debugging information about stack unwinding
317 static unsigned int riscv_debug_unwinder
= 0;
319 /* When this is set to non-zero debugging information about gdbarch
320 initialisation will be printed. */
322 static unsigned int riscv_debug_gdbarch
= 0;
324 /* See riscv-tdep.h. */
327 riscv_isa_xlen (struct gdbarch
*gdbarch
)
329 return gdbarch_tdep (gdbarch
)->isa_features
.xlen
;
332 /* See riscv-tdep.h. */
335 riscv_abi_xlen (struct gdbarch
*gdbarch
)
337 return gdbarch_tdep (gdbarch
)->abi_features
.xlen
;
340 /* See riscv-tdep.h. */
343 riscv_isa_flen (struct gdbarch
*gdbarch
)
345 return gdbarch_tdep (gdbarch
)->isa_features
.flen
;
348 /* See riscv-tdep.h. */
351 riscv_abi_flen (struct gdbarch
*gdbarch
)
353 return gdbarch_tdep (gdbarch
)->abi_features
.flen
;
356 /* Return true if the target for GDBARCH has floating point hardware. */
359 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
361 return (riscv_isa_flen (gdbarch
) > 0);
364 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
367 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
369 return gdbarch_tdep (gdbarch
)->abi_features
.flen
> 0;
372 /* Return true if REGNO is a floating pointer register. */
375 riscv_is_fp_regno_p (int regno
)
377 return (regno
>= RISCV_FIRST_FP_REGNUM
378 && regno
<= RISCV_LAST_FP_REGNUM
);
381 /* Implement the breakpoint_kind_from_pc gdbarch method. */
384 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
386 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
388 bool unaligned_p
= false;
391 /* Some targets don't support unaligned reads. The address can only
392 be unaligned if the C extension is supported. So it is safe to
393 use a compressed breakpoint in this case. */
398 /* Read the opcode byte to determine the instruction length. If
399 the read fails this may be because we tried to set the
400 breakpoint at an invalid address, in this case we provide a
401 fake result which will give a breakpoint length of 4.
402 Hopefully when we try to actually insert the breakpoint we
403 will see a failure then too which will be reported to the
405 if (target_read_code (*pcptr
, buf
, 1) == -1)
407 read_code (*pcptr
, buf
, 1);
410 if (riscv_debug_breakpoints
)
412 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
413 ? "C.EBREAK" : "EBREAK");
415 fprintf_unfiltered (gdb_stdlog
, "Using %s for breakpoint at %s ",
416 bp
, paddress (gdbarch
, *pcptr
));
418 fprintf_unfiltered (gdb_stdlog
, "(unaligned address)\n");
420 fprintf_unfiltered (gdb_stdlog
, "(instruction length %d)\n",
421 riscv_insn_length (buf
[0]));
423 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
428 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
434 /* Implement the sw_breakpoint_from_kind gdbarch method. */
436 static const gdb_byte
*
437 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
439 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
440 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
450 gdb_assert_not_reached (_("unhandled breakpoint kind"));
454 /* Callback function for user_reg_add. */
456 static struct value
*
457 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
459 const int *reg_p
= (const int *) baton
;
460 return value_of_register (*reg_p
, frame
);
463 /* Implement the register_name gdbarch method. This is used instead of
464 the function supplied by calling TDESC_USE_REGISTERS so that we can
465 ensure the preferred names are offered. */
468 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
470 /* Lookup the name through the target description. If we get back NULL
471 then this is an unknown register. If we do get a name back then we
472 look up the registers preferred name below. */
473 const char *name
= tdesc_register_name (gdbarch
, regnum
);
474 if (name
== NULL
|| name
[0] == '\0')
477 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
479 gdb_assert (regnum
< riscv_xreg_feature
.registers
.size ());
480 return riscv_xreg_feature
.registers
[regnum
].names
[0];
483 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
485 if (riscv_has_fp_regs (gdbarch
))
487 regnum
-= RISCV_FIRST_FP_REGNUM
;
488 gdb_assert (regnum
< riscv_freg_feature
.registers
.size ());
489 return riscv_freg_feature
.registers
[regnum
].names
[0];
495 /* Check that there's no gap between the set of registers handled above,
496 and the set of registers handled next. */
497 gdb_assert ((RISCV_LAST_FP_REGNUM
+ 1) == RISCV_FIRST_CSR_REGNUM
);
499 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
501 #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
502 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
506 #include "opcode/riscv-opc.h"
511 if (regnum
== RISCV_PRIV_REGNUM
)
514 /* It is possible that that the target provides some registers that GDB
515 is unaware of, in that case just return the NAME from the target
520 /* Construct a type for 64-bit FP registers. */
523 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
525 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
527 if (tdep
->riscv_fpreg_d_type
== nullptr)
529 const struct builtin_type
*bt
= builtin_type (gdbarch
);
531 /* The type we're building is this: */
533 union __gdb_builtin_type_fpreg_d
542 t
= arch_composite_type (gdbarch
,
543 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
544 append_composite_type_field (t
, "float", bt
->builtin_float
);
545 append_composite_type_field (t
, "double", bt
->builtin_double
);
547 t
->set_name ("builtin_type_fpreg_d");
548 tdep
->riscv_fpreg_d_type
= t
;
551 return tdep
->riscv_fpreg_d_type
;
554 /* Implement the register_type gdbarch method. This is installed as an
555 for the override setup by TDESC_USE_REGISTERS, for most registers we
556 delegate the type choice to the target description, but for a few
557 registers we try to improve the types if the target description has
558 taken a simplistic approach. */
561 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
563 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
564 int xlen
= riscv_isa_xlen (gdbarch
);
566 /* We want to perform some specific type "fixes" in cases where we feel
567 that we really can do better than the target description. For all
568 other cases we just return what the target description says. */
569 if (riscv_is_fp_regno_p (regnum
))
571 /* This spots the case for RV64 where the double is defined as
572 either 'ieee_double' or 'float' (which is the generic name that
573 converts to 'double' on 64-bit). In these cases its better to
574 present the registers using a union type. */
575 int flen
= riscv_isa_flen (gdbarch
);
577 && type
->code () == TYPE_CODE_FLT
578 && TYPE_LENGTH (type
) == flen
579 && (strcmp (type
->name (), "builtin_type_ieee_double") == 0
580 || strcmp (type
->name (), "double") == 0))
581 type
= riscv_fpreg_d_type (gdbarch
);
584 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
585 || regnum
== RISCV_RA_REGNUM
586 || regnum
== RISCV_FP_REGNUM
587 || regnum
== RISCV_SP_REGNUM
588 || regnum
== RISCV_GP_REGNUM
589 || regnum
== RISCV_TP_REGNUM
)
590 && type
->code () == TYPE_CODE_INT
591 && TYPE_LENGTH (type
) == xlen
)
593 /* This spots the case where some interesting registers are defined
594 as simple integers of the expected size, we force these registers
595 to be pointers as we believe that is more useful. */
596 if (regnum
== gdbarch_pc_regnum (gdbarch
)
597 || regnum
== RISCV_RA_REGNUM
)
598 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
599 else if (regnum
== RISCV_FP_REGNUM
600 || regnum
== RISCV_SP_REGNUM
601 || regnum
== RISCV_GP_REGNUM
602 || regnum
== RISCV_TP_REGNUM
)
603 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
609 /* Helper for riscv_print_registers_info, prints info for a single register
613 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
614 struct ui_file
*file
,
615 struct frame_info
*frame
,
618 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
620 struct type
*regtype
;
621 int print_raw_format
;
622 enum tab_stops
{ value_column_1
= 15 };
624 fputs_filtered (name
, file
);
625 print_spaces_filtered (value_column_1
- strlen (name
), file
);
629 val
= value_of_register (regnum
, frame
);
630 regtype
= value_type (val
);
632 catch (const gdb_exception_error
&ex
)
634 /* Handle failure to read a register without interrupting the entire
635 'info registers' flow. */
636 fprintf_filtered (file
, "%s\n", ex
.what ());
640 print_raw_format
= (value_entirely_available (val
)
641 && !value_optimized_out (val
));
643 if (regtype
->code () == TYPE_CODE_FLT
644 || (regtype
->code () == TYPE_CODE_UNION
645 && regtype
->num_fields () == 2
646 && TYPE_FIELD_TYPE (regtype
, 0)->code () == TYPE_CODE_FLT
647 && TYPE_FIELD_TYPE (regtype
, 1)->code () == TYPE_CODE_FLT
)
648 || (regtype
->code () == TYPE_CODE_UNION
649 && regtype
->num_fields () == 3
650 && TYPE_FIELD_TYPE (regtype
, 0)->code () == TYPE_CODE_FLT
651 && TYPE_FIELD_TYPE (regtype
, 1)->code () == TYPE_CODE_FLT
652 && TYPE_FIELD_TYPE (regtype
, 2)->code () == TYPE_CODE_FLT
))
654 struct value_print_options opts
;
655 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
656 enum bfd_endian byte_order
= type_byte_order (regtype
);
658 get_user_print_options (&opts
);
661 common_val_print (val
, file
, 0, &opts
, current_language
);
663 if (print_raw_format
)
665 fprintf_filtered (file
, "\t(raw ");
666 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
668 fprintf_filtered (file
, ")");
673 struct value_print_options opts
;
675 /* Print the register in hex. */
676 get_formatted_print_options (&opts
, 'x');
678 common_val_print (val
, file
, 0, &opts
, current_language
);
680 if (print_raw_format
)
682 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
685 int size
= register_size (gdbarch
, regnum
);
688 /* The SD field is always in the upper bit of MSTATUS, regardless
689 of the number of bits in MSTATUS. */
690 d
= value_as_long (val
);
692 fprintf_filtered (file
,
693 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
694 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
695 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
696 (int) ((d
>> (xlen
- 1)) & 0x1),
697 (int) ((d
>> 24) & 0x1f),
698 (int) ((d
>> 19) & 0x1),
699 (int) ((d
>> 18) & 0x1),
700 (int) ((d
>> 17) & 0x1),
701 (int) ((d
>> 15) & 0x3),
702 (int) ((d
>> 13) & 0x3),
703 (int) ((d
>> 11) & 0x3),
704 (int) ((d
>> 9) & 0x3),
705 (int) ((d
>> 8) & 0x1),
706 (int) ((d
>> 7) & 0x1),
707 (int) ((d
>> 6) & 0x1),
708 (int) ((d
>> 5) & 0x1),
709 (int) ((d
>> 4) & 0x1),
710 (int) ((d
>> 3) & 0x1),
711 (int) ((d
>> 2) & 0x1),
712 (int) ((d
>> 1) & 0x1),
713 (int) ((d
>> 0) & 0x1));
715 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
720 int size
= register_size (gdbarch
, regnum
);
722 /* The MXL field is always in the upper two bits of MISA,
723 regardless of the number of bits in MISA. Mask out other
724 bits to ensure we have a positive value. */
725 d
= value_as_long (val
);
726 base
= (d
>> ((size
* 8) - 2)) & 0x3;
729 for (; base
> 0; base
--)
731 fprintf_filtered (file
, "\tRV%d", xlen
);
733 for (i
= 0; i
< 26; i
++)
736 fprintf_filtered (file
, "%c", 'A' + i
);
739 else if (regnum
== RISCV_CSR_FCSR_REGNUM
740 || regnum
== RISCV_CSR_FFLAGS_REGNUM
741 || regnum
== RISCV_CSR_FRM_REGNUM
)
745 d
= value_as_long (val
);
747 fprintf_filtered (file
, "\t");
748 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
749 fprintf_filtered (file
,
750 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
751 (int) ((d
>> 5) & 0x7),
752 (int) ((d
>> 4) & 0x1),
753 (int) ((d
>> 3) & 0x1),
754 (int) ((d
>> 2) & 0x1),
755 (int) ((d
>> 1) & 0x1),
756 (int) ((d
>> 0) & 0x1));
758 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
760 static const char * const sfrm
[] =
762 "RNE (round to nearest; ties to even)",
763 "RTZ (Round towards zero)",
764 "RDN (Round down towards -INF)",
765 "RUP (Round up towards +INF)",
766 "RMM (Round to nearest; ties to max magnitude)",
769 "dynamic rounding mode",
771 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
772 ? (d
>> 5) : d
) & 0x3;
774 fprintf_filtered (file
, "%sFRM:%i [%s]",
775 (regnum
== RISCV_CSR_FCSR_REGNUM
780 else if (regnum
== RISCV_PRIV_REGNUM
)
785 d
= value_as_long (val
);
790 static const char * const sprv
[] =
797 fprintf_filtered (file
, "\tprv:%d [%s]",
801 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
805 /* If not a vector register, print it also according to its
807 if (TYPE_VECTOR (regtype
) == 0)
809 get_user_print_options (&opts
);
811 fprintf_filtered (file
, "\t");
812 common_val_print (val
, file
, 0, &opts
, current_language
);
817 fprintf_filtered (file
, "\n");
820 /* Return true if REGNUM is a valid CSR register. The CSR register space
821 is sparsely populated, so not every number is a named CSR. */
824 riscv_is_regnum_a_named_csr (int regnum
)
826 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
827 && regnum
<= RISCV_LAST_CSR_REGNUM
);
831 #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
832 #include "opcode/riscv-opc.h"
841 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
845 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
846 struct reggroup
*reggroup
)
848 /* Used by 'info registers' and 'info registers <groupname>'. */
850 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
851 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
854 if (regnum
> RISCV_LAST_REGNUM
)
856 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
860 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
863 if (reggroup
== all_reggroup
)
865 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
867 if (riscv_is_regnum_a_named_csr (regnum
))
871 else if (reggroup
== float_reggroup
)
872 return (riscv_is_fp_regno_p (regnum
)
873 || regnum
== RISCV_CSR_FCSR_REGNUM
874 || regnum
== RISCV_CSR_FFLAGS_REGNUM
875 || regnum
== RISCV_CSR_FRM_REGNUM
);
876 else if (reggroup
== general_reggroup
)
877 return regnum
< RISCV_FIRST_FP_REGNUM
;
878 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
880 if (riscv_has_fp_regs (gdbarch
))
881 return (regnum
<= RISCV_LAST_FP_REGNUM
882 || regnum
== RISCV_CSR_FCSR_REGNUM
883 || regnum
== RISCV_CSR_FFLAGS_REGNUM
884 || regnum
== RISCV_CSR_FRM_REGNUM
);
886 return regnum
< RISCV_FIRST_FP_REGNUM
;
888 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
890 if (regnum
== RISCV_PRIV_REGNUM
)
892 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
894 if (riscv_is_regnum_a_named_csr (regnum
))
898 else if (reggroup
== vector_reggroup
)
904 /* Implement the print_registers_info gdbarch method. This is used by
905 'info registers' and 'info all-registers'. */
908 riscv_print_registers_info (struct gdbarch
*gdbarch
,
909 struct ui_file
*file
,
910 struct frame_info
*frame
,
911 int regnum
, int print_all
)
915 /* Print one specified register. */
916 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
917 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
918 error (_("Not a valid register for the current processor type"));
919 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
923 struct reggroup
*reggroup
;
926 reggroup
= all_reggroup
;
928 reggroup
= general_reggroup
;
930 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
932 /* Zero never changes, so might as well hide by default. */
933 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
936 /* Registers with no name are not valid on this ISA. */
937 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
938 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
941 /* Is the register in the group we're interested in? */
942 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
945 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
950 /* Class that handles one decoded RiscV instruction. */
956 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
959 /* Unknown value is used at initialisation time. */
962 /* These instructions are all the ones we are interested in during the
972 /* These are needed for software breakpoint support. */
981 /* These are needed for stepping over atomic sequences. */
985 /* Other instructions are not interesting during the prologue scan, and
1000 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1002 /* Get the length of the instruction in bytes. */
1004 { return m_length
; }
1006 /* Get the opcode for this instruction. */
1007 enum opcode
opcode () const
1008 { return m_opcode
; }
1010 /* Get destination register field for this instruction. This is only
1011 valid if the OPCODE implies there is such a field for this
1016 /* Get the RS1 register field for this instruction. This is only valid
1017 if the OPCODE implies there is such a field for this instruction. */
1021 /* Get the RS2 register field for this instruction. This is only valid
1022 if the OPCODE implies there is such a field for this instruction. */
1026 /* Get the immediate for this instruction in signed form. This is only
1027 valid if the OPCODE implies there is such a field for this
1029 int imm_signed () const
1034 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1035 int decode_register_index (unsigned long opcode
, int offset
)
1037 return (opcode
>> offset
) & 0x1F;
1040 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1041 int decode_register_index_short (unsigned long opcode
, int offset
)
1043 return ((opcode
>> offset
) & 0x7) + 8;
1046 /* Helper for DECODE, decode 32-bit R-type instruction. */
1047 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1050 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1051 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1052 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1055 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1056 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1059 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1060 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1063 /* Helper for DECODE, decode 32-bit I-type instruction. */
1064 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1067 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1068 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1069 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1072 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1073 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1076 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1077 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
1080 /* Helper for DECODE, decode 32-bit S-type instruction. */
1081 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1084 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1085 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1086 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1089 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1090 encoding is different for each CS format instruction, so extracting
1091 the immediate is left up to the caller, who should pass the extracted
1092 immediate value through in IMM. */
1093 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1097 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1098 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1101 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1102 encoding is different for each CSS format instruction, so extracting
1103 the immediate is left up to the caller, who should pass the extracted
1104 immediate value through in IMM. */
1105 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1109 m_rs1
= RISCV_SP_REGNUM
;
1110 /* Not a compressed register number in this case. */
1111 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1114 /* Helper for DECODE, decode 32-bit U-type instruction. */
1115 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1118 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1119 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1122 /* Helper for DECODE, decode 32-bit J-type instruction. */
1123 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1126 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1127 m_imm
.s
= EXTRACT_UJTYPE_IMM (ival
);
1130 /* Helper for DECODE, decode 32-bit J-type instruction. */
1131 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1134 m_imm
.s
= EXTRACT_RVC_J_IMM (ival
);
1137 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1140 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1141 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1142 m_imm
.s
= EXTRACT_SBTYPE_IMM (ival
);
1145 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1148 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1149 m_imm
.s
= EXTRACT_RVC_B_IMM (ival
);
1152 /* Fetch instruction from target memory at ADDR, return the content of
1153 the instruction, and update LEN with the instruction length. */
1154 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1155 CORE_ADDR addr
, int *len
);
1157 /* The length of the instruction in bytes. Should be 2 or 4. */
1160 /* The instruction opcode. */
1161 enum opcode m_opcode
;
1163 /* The three possible registers an instruction might reference. Not
1164 every instruction fills in all of these registers. Which fields are
1165 valid depends on the opcode. The naming of these fields matches the
1166 naming in the riscv isa manual. */
1171 /* Possible instruction immediate. This is only valid if the instruction
1172 format contains an immediate, not all instruction, whether this is
1173 valid depends on the opcode. Despite only having one format for now
1174 the immediate is packed into a union, later instructions might require
1175 an unsigned formatted immediate, having the union in place now will
1176 reduce the need for code churn later. */
1177 union riscv_insn_immediate
1179 riscv_insn_immediate ()
1189 /* Fetch instruction from target memory at ADDR, return the content of the
1190 instruction, and update LEN with the instruction length. */
1193 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1194 CORE_ADDR addr
, int *len
)
1196 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1198 int instlen
, status
;
1200 /* All insns are at least 16 bits. */
1201 status
= target_read_memory (addr
, buf
, 2);
1203 memory_error (TARGET_XFER_E_IO
, addr
);
1205 /* If we need more, grab it now. */
1206 instlen
= riscv_insn_length (buf
[0]);
1207 gdb_assert (instlen
<= sizeof (buf
));
1212 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1214 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1217 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1220 /* Fetch from target memory an instruction at PC and decode it. This can
1221 throw an error if the memory access fails, callers are responsible for
1222 handling this error if that is appropriate. */
1225 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1229 /* Fetch the instruction, and the instructions length. */
1230 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1234 if (is_add_insn (ival
))
1235 decode_r_type_insn (ADD
, ival
);
1236 else if (is_addw_insn (ival
))
1237 decode_r_type_insn (ADDW
, ival
);
1238 else if (is_addi_insn (ival
))
1239 decode_i_type_insn (ADDI
, ival
);
1240 else if (is_addiw_insn (ival
))
1241 decode_i_type_insn (ADDIW
, ival
);
1242 else if (is_auipc_insn (ival
))
1243 decode_u_type_insn (AUIPC
, ival
);
1244 else if (is_lui_insn (ival
))
1245 decode_u_type_insn (LUI
, ival
);
1246 else if (is_sd_insn (ival
))
1247 decode_s_type_insn (SD
, ival
);
1248 else if (is_sw_insn (ival
))
1249 decode_s_type_insn (SW
, ival
);
1250 else if (is_jal_insn (ival
))
1251 decode_j_type_insn (JAL
, ival
);
1252 else if (is_jalr_insn (ival
))
1253 decode_i_type_insn (JALR
, ival
);
1254 else if (is_beq_insn (ival
))
1255 decode_b_type_insn (BEQ
, ival
);
1256 else if (is_bne_insn (ival
))
1257 decode_b_type_insn (BNE
, ival
);
1258 else if (is_blt_insn (ival
))
1259 decode_b_type_insn (BLT
, ival
);
1260 else if (is_bge_insn (ival
))
1261 decode_b_type_insn (BGE
, ival
);
1262 else if (is_bltu_insn (ival
))
1263 decode_b_type_insn (BLTU
, ival
);
1264 else if (is_bgeu_insn (ival
))
1265 decode_b_type_insn (BGEU
, ival
);
1266 else if (is_lr_w_insn (ival
))
1267 decode_r_type_insn (LR
, ival
);
1268 else if (is_lr_d_insn (ival
))
1269 decode_r_type_insn (LR
, ival
);
1270 else if (is_sc_w_insn (ival
))
1271 decode_r_type_insn (SC
, ival
);
1272 else if (is_sc_d_insn (ival
))
1273 decode_r_type_insn (SC
, ival
);
1275 /* None of the other fields are valid in this case. */
1278 else if (m_length
== 2)
1280 int xlen
= riscv_isa_xlen (gdbarch
);
1282 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1283 C_JALR. So must try to match C_JALR first as it has more bits in
1285 if (is_c_jalr_insn (ival
))
1286 decode_cr_type_insn (JALR
, ival
);
1287 else if (is_c_add_insn (ival
))
1288 decode_cr_type_insn (ADD
, ival
);
1289 /* C_ADDW is RV64 and RV128 only. */
1290 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1291 decode_cr_type_insn (ADDW
, ival
);
1292 else if (is_c_addi_insn (ival
))
1293 decode_ci_type_insn (ADDI
, ival
);
1294 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1295 only and C_JAL is RV32 only. */
1296 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1297 decode_ci_type_insn (ADDIW
, ival
);
1298 else if (xlen
== 4 && is_c_jal_insn (ival
))
1299 decode_cj_type_insn (JAL
, ival
);
1300 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1301 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1303 else if (is_c_addi16sp_insn (ival
))
1306 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1307 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1309 else if (is_c_addi4spn_insn (ival
))
1312 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1313 m_rs1
= RISCV_SP_REGNUM
;
1314 m_imm
.s
= EXTRACT_RVC_ADDI4SPN_IMM (ival
);
1316 else if (is_c_lui_insn (ival
))
1319 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1320 m_imm
.s
= EXTRACT_RVC_LUI_IMM (ival
);
1322 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1323 and C_FSW is RV32 only. */
1324 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1325 decode_cs_type_insn (SD
, ival
, EXTRACT_RVC_LD_IMM (ival
));
1326 else if (is_c_sw_insn (ival
))
1327 decode_cs_type_insn (SW
, ival
, EXTRACT_RVC_LW_IMM (ival
));
1328 else if (is_c_swsp_insn (ival
))
1329 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SWSP_IMM (ival
));
1330 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1331 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SDSP_IMM (ival
));
1332 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1333 So must try to match C_JR first as it ahs more bits in mask. */
1334 else if (is_c_jr_insn (ival
))
1335 decode_cr_type_insn (JALR
, ival
);
1336 else if (is_c_j_insn (ival
))
1337 decode_cj_type_insn (JAL
, ival
);
1338 else if (is_c_beqz_insn (ival
))
1339 decode_cb_type_insn (BEQ
, ival
);
1340 else if (is_c_bnez_insn (ival
))
1341 decode_cb_type_insn (BNE
, ival
);
1343 /* None of the other fields of INSN are valid in this case. */
1348 /* This must be a 6 or 8 byte instruction, we don't currently decode
1349 any of these, so just ignore it. */
1350 gdb_assert (m_length
== 6 || m_length
== 8);
1355 /* The prologue scanner. This is currently only used for skipping the
1356 prologue of a function when the DWARF information is not sufficient.
1357 However, it is written with filling of the frame cache in mind, which
1358 is why different groups of stack setup instructions are split apart
1359 during the core of the inner loop. In the future, the intention is to
1360 extend this function to fully support building up a frame cache that
1361 can unwind register values when there is no DWARF information. */
1364 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1365 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1366 struct riscv_unwind_cache
*cache
)
1368 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1369 CORE_ADDR end_prologue_addr
= 0;
1371 /* Find an upper limit on the function prologue using the debug
1372 information. If the debug information could not be used to provide
1373 that bound, then use an arbitrary large number as the upper bound. */
1374 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1375 if (after_prologue_pc
== 0)
1376 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1377 if (after_prologue_pc
< end_pc
)
1378 end_pc
= after_prologue_pc
;
1380 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1381 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1382 regs
[regno
] = pv_register (regno
, 0);
1383 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1385 if (riscv_debug_unwinder
)
1388 "Prologue scan for function starting at %s (limit %s)\n",
1389 core_addr_to_string (start_pc
),
1390 core_addr_to_string (end_pc
));
1392 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1394 struct riscv_insn insn
;
1396 /* Decode the current instruction, and decide where the next
1397 instruction lives based on the size of this instruction. */
1398 insn
.decode (gdbarch
, cur_pc
);
1399 gdb_assert (insn
.length () > 0);
1400 next_pc
= cur_pc
+ insn
.length ();
1402 /* Look for common stack adjustment insns. */
1403 if ((insn
.opcode () == riscv_insn::ADDI
1404 || insn
.opcode () == riscv_insn::ADDIW
)
1405 && insn
.rd () == RISCV_SP_REGNUM
1406 && insn
.rs1 () == RISCV_SP_REGNUM
)
1408 /* Handle: addi sp, sp, -i
1409 or: addiw sp, sp, -i */
1410 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1411 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1413 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1415 else if ((insn
.opcode () == riscv_insn::SW
1416 || insn
.opcode () == riscv_insn::SD
)
1417 && (insn
.rs1 () == RISCV_SP_REGNUM
1418 || insn
.rs1 () == RISCV_FP_REGNUM
))
1420 /* Handle: sw reg, offset(sp)
1421 or: sd reg, offset(sp)
1422 or: sw reg, offset(s0)
1423 or: sd reg, offset(s0) */
1424 /* Instruction storing a register onto the stack. */
1425 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1426 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1427 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
1428 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
1431 else if (insn
.opcode () == riscv_insn::ADDI
1432 && insn
.rd () == RISCV_FP_REGNUM
1433 && insn
.rs1 () == RISCV_SP_REGNUM
)
1435 /* Handle: addi s0, sp, size */
1436 /* Instructions setting up the frame pointer. */
1437 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1438 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1440 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1442 else if ((insn
.opcode () == riscv_insn::ADD
1443 || insn
.opcode () == riscv_insn::ADDW
)
1444 && insn
.rd () == RISCV_FP_REGNUM
1445 && insn
.rs1 () == RISCV_SP_REGNUM
1446 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1448 /* Handle: add s0, sp, 0
1449 or: addw s0, sp, 0 */
1450 /* Instructions setting up the frame pointer. */
1451 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1452 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1453 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
1455 else if ((insn
.opcode () == riscv_insn::ADDI
1456 && insn
.rd () == RISCV_ZERO_REGNUM
1457 && insn
.rs1 () == RISCV_ZERO_REGNUM
1458 && insn
.imm_signed () == 0))
1460 /* Handle: add x0, x0, 0 (NOP) */
1462 else if (insn
.opcode () == riscv_insn::AUIPC
)
1464 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1465 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
1467 else if (insn
.opcode () == riscv_insn::LUI
)
1469 /* Handle: lui REG, n
1470 Where REG is not gp register. */
1471 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1472 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
1474 else if (insn
.opcode () == riscv_insn::ADDI
)
1476 /* Handle: addi REG1, REG2, IMM */
1477 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1478 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1480 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1482 else if (insn
.opcode () == riscv_insn::ADD
)
1484 /* Handle: addi REG1, REG2, IMM */
1485 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1486 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1487 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1488 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
1492 end_prologue_addr
= cur_pc
;
1497 if (end_prologue_addr
== 0)
1498 end_prologue_addr
= cur_pc
;
1500 if (riscv_debug_unwinder
)
1501 fprintf_unfiltered (gdb_stdlog
, "End of prologue at %s\n",
1502 core_addr_to_string (end_prologue_addr
));
1506 /* Figure out if it is a frame pointer or just a stack pointer. Also
1507 the offset held in the pv_t is from the original register value to
1508 the current value, which for a grows down stack means a negative
1509 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1510 from the current value to the original value. */
1511 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
1513 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
1514 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
1518 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
1519 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
1522 /* Assign offset from old SP to all saved registers. As we don't
1523 have the previous value for the frame base register at this
1524 point, we store the offset as the address in the trad_frame, and
1525 then convert this to an actual address later. */
1526 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
1529 if (stack
.find_reg (gdbarch
, i
, &offset
))
1531 if (riscv_debug_unwinder
)
1533 /* Display OFFSET as a signed value, the offsets are from
1534 the frame base address to the registers location on
1535 the stack, with a descending stack this means the
1536 offsets are always negative. */
1537 fprintf_unfiltered (gdb_stdlog
,
1538 "Register $%s at stack offset %s\n",
1539 gdbarch_register_name (gdbarch
, i
),
1540 plongest ((LONGEST
) offset
));
1542 trad_frame_set_addr (cache
->regs
, i
, offset
);
1547 return end_prologue_addr
;
1550 /* Implement the riscv_skip_prologue gdbarch method. */
1553 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1555 CORE_ADDR func_addr
;
1557 /* See if we can determine the end of the prologue via the symbol
1558 table. If so, then return either PC, or the PC after the
1559 prologue, whichever is greater. */
1560 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1562 CORE_ADDR post_prologue_pc
1563 = skip_prologue_using_sal (gdbarch
, func_addr
);
1565 if (post_prologue_pc
!= 0)
1566 return std::max (pc
, post_prologue_pc
);
1569 /* Can't determine prologue from the symbol table, need to examine
1570 instructions. Pass -1 for the end address to indicate the prologue
1571 scanner can scan as far as it needs to find the end of the prologue. */
1572 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
1575 /* Implement the gdbarch push dummy code callback. */
1578 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1579 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1580 struct type
*value_type
, CORE_ADDR
*real_pc
,
1581 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1583 /* A nop instruction is 'add x0, x0, 0'. */
1584 static const gdb_byte nop_insn
[] = { 0x13, 0x00, 0x00, 0x00 };
1586 /* Allocate space for a breakpoint, and keep the stack correctly
1587 aligned. The space allocated here must be at least big enough to
1588 accommodate the NOP_INSN defined above. */
1593 /* When we insert a breakpoint we select whether to use a compressed
1594 breakpoint or not based on the existing contents of the memory.
1596 If the breakpoint is being placed onto the stack as part of setting up
1597 for an inferior call from GDB, then the existing stack contents may
1598 randomly appear to be a compressed instruction, causing GDB to insert
1599 a compressed breakpoint. If this happens on a target that does not
1600 support compressed instructions then this could cause problems.
1602 To prevent this issue we write an uncompressed nop onto the stack at
1603 the location where the breakpoint will be inserted. In this way we
1604 ensure that we always use an uncompressed breakpoint, which should
1605 work on all targets.
1607 We call TARGET_WRITE_MEMORY here so that if the write fails we don't
1608 throw an exception. Instead we ignore the error and move on. The
1609 assumption is that either GDB will error later when actually trying to
1610 insert a software breakpoint, or GDB will use hardware breakpoints and
1611 there will be no need to write to memory later. */
1612 int status
= target_write_memory (*bp_addr
, nop_insn
, sizeof (nop_insn
));
1614 if (riscv_debug_breakpoints
|| riscv_debug_infcall
)
1615 fprintf_unfiltered (gdb_stdlog
,
1616 "Writing %s-byte nop instruction to %s: %s\n",
1617 plongest (sizeof (nop_insn
)),
1618 paddress (gdbarch
, *bp_addr
),
1619 (status
== 0 ? "success" : "failed"));
1624 /* Implement the gdbarch type alignment method, overrides the generic
1625 alignment algorithm for anything that is RISC-V specific. */
1628 riscv_type_align (gdbarch
*gdbarch
, type
*type
)
1630 type
= check_typedef (type
);
1631 if (type
->code () == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
))
1632 return std::min (TYPE_LENGTH (type
), (ULONGEST
) BIGGEST_ALIGNMENT
);
1634 /* Anything else will be aligned by the generic code. */
1638 /* Holds information about a single argument either being passed to an
1639 inferior function, or returned from an inferior function. This includes
1640 information about the size, type, etc of the argument, and also
1641 information about how the argument will be passed (or returned). */
1643 struct riscv_arg_info
1645 /* Contents of the argument. */
1646 const gdb_byte
*contents
;
1648 /* Length of argument. */
1651 /* Alignment required for an argument of this type. */
1654 /* The type for this argument. */
1657 /* Each argument can have either 1 or 2 locations assigned to it. Each
1658 location describes where part of the argument will be placed. The
1659 second location is valid based on the LOC_TYPE and C_LENGTH fields
1660 of the first location (which is always valid). */
1663 /* What type of location this is. */
1666 /* Argument passed in a register. */
1669 /* Argument passed as an on stack argument. */
1672 /* Argument passed by reference. The second location is always
1673 valid for a BY_REF argument, and describes where the address
1674 of the BY_REF argument should be placed. */
1678 /* Information that depends on the location type. */
1681 /* Which register number to use. */
1684 /* The offset into the stack region. */
1688 /* The length of contents covered by this location. If this is less
1689 than the total length of the argument, then the second location
1690 will be valid, and will describe where the rest of the argument
1694 /* The offset within CONTENTS for this part of the argument. This can
1695 be non-zero even for the first part (the first field of a struct can
1696 have a non-zero offset due to padding). For the second part of the
1697 argument, this might be the C_LENGTH value of the first part,
1698 however, if we are passing a structure in two registers, and there's
1699 is padding between the first and second field, then this offset
1700 might be greater than the length of the first argument part. When
1701 the second argument location is not holding part of the argument
1702 value, but is instead holding the address of a reference argument,
1703 then this offset will be set to 0. */
1707 /* TRUE if this is an unnamed argument. */
1711 /* Information about a set of registers being used for passing arguments as
1712 part of a function call. The register set must be numerically
1713 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1714 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1716 struct riscv_arg_reg
1718 riscv_arg_reg (int first
, int last
)
1719 : next_regnum (first
),
1725 /* The GDB register number to use in this set. */
1728 /* The last GDB register number to use in this set. */
1732 /* Arguments can be passed as on stack arguments, or by reference. The
1733 on stack arguments must be in a continuous region starting from $sp,
1734 while the by reference arguments can be anywhere, but we'll put them
1735 on the stack after (at higher address) the on stack arguments.
1737 This might not be the right approach to take. The ABI is clear that
1738 an argument passed by reference can be modified by the callee, which
1739 us placing the argument (temporarily) onto the stack will not achieve
1740 (changes will be lost). There's also the possibility that very large
1741 arguments could overflow the stack.
1743 This struct is used to track offset into these two areas for where
1744 arguments are to be placed. */
1745 struct riscv_memory_offsets
1747 riscv_memory_offsets ()
1754 /* Offset into on stack argument area. */
1757 /* Offset into the pass by reference area. */
1761 /* Holds information about where arguments to a call will be placed. This
1762 is updated as arguments are added onto the call, and can be used to
1763 figure out where the next argument should be placed. */
1765 struct riscv_call_info
1767 riscv_call_info (struct gdbarch
*gdbarch
)
1768 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1769 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1771 xlen
= riscv_abi_xlen (gdbarch
);
1772 flen
= riscv_abi_flen (gdbarch
);
1774 /* Disable use of floating point registers if needed. */
1775 if (!riscv_has_fp_abi (gdbarch
))
1776 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1779 /* Track the memory areas used for holding in-memory arguments to a
1781 struct riscv_memory_offsets memory
;
1783 /* Holds information about the next integer register to use for passing
1785 struct riscv_arg_reg int_regs
;
1787 /* Holds information about the next floating point register to use for
1788 passing an argument. */
1789 struct riscv_arg_reg float_regs
;
1791 /* The XLEN and FLEN are copied in to this structure for convenience, and
1792 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
1797 /* Return the number of registers available for use as parameters in the
1798 register set REG. Returned value can be 0 or more. */
1801 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1803 if (reg
->next_regnum
> reg
->last_regnum
)
1806 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1809 /* If there is at least one register available in the register set REG then
1810 the next register from REG is assigned to LOC and the length field of
1811 LOC is updated to LENGTH. The register set REG is updated to indicate
1812 that the assigned register is no longer available and the function
1815 If there are no registers available in REG then the function returns
1816 false, and LOC and REG are unchanged. */
1819 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1820 struct riscv_arg_reg
*reg
,
1821 int length
, int offset
)
1823 if (reg
->next_regnum
<= reg
->last_regnum
)
1825 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1826 loc
->loc_data
.regno
= reg
->next_regnum
;
1828 loc
->c_length
= length
;
1829 loc
->c_offset
= offset
;
1836 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1837 record that an area of stack has been used to hold the parameter
1840 The length field of LOC is updated to LENGTH, the length of the
1841 parameter being stored, and ALIGN is the alignment required by the
1842 parameter, which will affect how memory is allocated out of MEMORY. */
1845 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1846 struct riscv_memory_offsets
*memory
,
1847 int length
, int align
)
1849 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1851 = align_up (memory
->arg_offset
, align
);
1852 loc
->loc_data
.offset
= memory
->arg_offset
;
1853 memory
->arg_offset
+= length
;
1854 loc
->c_length
= length
;
1856 /* Offset is always 0, either we're the first location part, in which
1857 case we're reading content from the start of the argument, or we're
1858 passing the address of a reference argument, so 0. */
1862 /* Update AINFO, which describes an argument that should be passed or
1863 returned using the integer ABI. The argloc fields within AINFO are
1864 updated to describe the location in which the argument will be passed to
1865 a function, or returned from a function.
1867 The CINFO structure contains the ongoing call information, the holds
1868 information such as which argument registers are remaining to be
1869 assigned to parameter, and how much memory has been used by parameters
1872 By examining the state of CINFO a suitable location can be selected,
1873 and assigned to AINFO. */
1876 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1877 struct riscv_call_info
*cinfo
)
1879 if (ainfo
->length
> (2 * cinfo
->xlen
))
1881 /* Argument is going to be passed by reference. */
1882 ainfo
->argloc
[0].loc_type
1883 = riscv_arg_info::location::by_ref
;
1884 cinfo
->memory
.ref_offset
1885 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1886 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1887 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1888 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1890 /* The second location for this argument is given over to holding the
1891 address of the by-reference data. Pass 0 for the offset as this
1892 is not part of the actual argument value. */
1893 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1896 riscv_assign_stack_location (&ainfo
->argloc
[1],
1897 &cinfo
->memory
, cinfo
->xlen
,
1902 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
1903 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
1905 /* Unnamed arguments in registers that require 2*XLEN alignment are
1906 passed in an aligned register pair. */
1907 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
1908 && cinfo
->int_regs
.next_regnum
& 1)
1909 cinfo
->int_regs
.next_regnum
++;
1911 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1912 &cinfo
->int_regs
, len
, 0))
1913 riscv_assign_stack_location (&ainfo
->argloc
[0],
1914 &cinfo
->memory
, len
, align
);
1916 if (len
< ainfo
->length
)
1918 len
= ainfo
->length
- len
;
1919 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1920 &cinfo
->int_regs
, len
,
1922 riscv_assign_stack_location (&ainfo
->argloc
[1],
1923 &cinfo
->memory
, len
, cinfo
->xlen
);
1928 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1929 is being passed with the floating point ABI. */
1932 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1933 struct riscv_call_info
*cinfo
)
1935 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
1936 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1939 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1942 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1946 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1947 is a complex floating point argument, and is therefore handled
1948 differently to other argument types. */
1951 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1952 struct riscv_call_info
*cinfo
)
1954 if (ainfo
->length
<= (2 * cinfo
->flen
)
1955 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
1956 && !ainfo
->is_unnamed
)
1959 int len
= ainfo
->length
/ 2;
1961 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1962 &cinfo
->float_regs
, len
, 0);
1963 gdb_assert (result
);
1965 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1966 &cinfo
->float_regs
, len
, len
);
1967 gdb_assert (result
);
1970 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1973 /* A structure used for holding information about a structure type within
1974 the inferior program. The RiscV ABI has special rules for handling some
1975 structures with a single field or with two fields. The counting of
1976 fields here is done after flattening out all nested structures. */
1978 class riscv_struct_info
1981 riscv_struct_info ()
1982 : m_number_of_fields (0),
1983 m_types
{ nullptr, nullptr },
1989 /* Analyse TYPE descending into nested structures, count the number of
1990 scalar fields and record the types of the first two fields found. */
1991 void analyse (struct type
*type
)
1993 analyse_inner (type
, 0);
1996 /* The number of scalar fields found in the analysed type. This is
1997 currently only accurate if the value returned is 0, 1, or 2 as the
1998 analysis stops counting when the number of fields is 3. This is
1999 because the RiscV ABI only has special cases for 1 or 2 fields,
2000 anything else we just don't care about. */
2001 int number_of_fields () const
2002 { return m_number_of_fields
; }
2004 /* Return the type for scalar field INDEX within the analysed type. Will
2005 return nullptr if there is no field at that index. Only INDEX values
2006 0 and 1 can be requested as the RiscV ABI only has special cases for
2007 structures with 1 or 2 fields. */
2008 struct type
*field_type (int index
) const
2010 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2011 return m_types
[index
];
2014 /* Return the offset of scalar field INDEX within the analysed type. Will
2015 return 0 if there is no field at that index. Only INDEX values 0 and
2016 1 can be requested as the RiscV ABI only has special cases for
2017 structures with 1 or 2 fields. */
2018 int field_offset (int index
) const
2020 gdb_assert (index
< (sizeof (m_offsets
) / sizeof (m_offsets
[0])));
2021 return m_offsets
[index
];
2025 /* The number of scalar fields found within the structure after recursing
2026 into nested structures. */
2027 int m_number_of_fields
;
2029 /* The types of the first two scalar fields found within the structure
2030 after recursing into nested structures. */
2031 struct type
*m_types
[2];
2033 /* The offsets of the first two scalar fields found within the structure
2034 after recursing into nested structures. */
2037 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2038 offset from the start of the top level structure being analysed. */
2039 void analyse_inner (struct type
*type
, int offset
);
2042 /* See description in class declaration. */
2045 riscv_struct_info::analyse_inner (struct type
*type
, int offset
)
2047 unsigned int count
= type
->num_fields ();
2050 for (i
= 0; i
< count
; ++i
)
2052 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
2055 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
2056 field_type
= check_typedef (field_type
);
2058 = offset
+ TYPE_FIELD_BITPOS (type
, i
) / TARGET_CHAR_BIT
;
2060 switch (field_type
->code ())
2062 case TYPE_CODE_STRUCT
:
2063 analyse_inner (field_type
, field_offset
);
2067 /* RiscV only flattens out structures. Anything else does not
2068 need to be flattened, we just record the type, and when we
2069 look at the analysis results we'll realise this is not a
2070 structure we can special case, and pass the structure in
2072 if (m_number_of_fields
< 2)
2074 m_types
[m_number_of_fields
] = field_type
;
2075 m_offsets
[m_number_of_fields
] = field_offset
;
2077 m_number_of_fields
++;
2081 /* RiscV only has special handling for structures with 1 or 2 scalar
2082 fields, any more than that and the structure is just passed in
2083 memory. We can safely drop out early when we find 3 or more
2086 if (m_number_of_fields
> 2)
2091 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2092 is a structure. Small structures on RiscV have some special case
2093 handling in order that the structure might be passed in register.
2094 Larger structures are passed in memory. After assigning location
2095 information to AINFO, CINFO will have been updated. */
2098 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2099 struct riscv_call_info
*cinfo
)
2101 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2103 struct riscv_struct_info sinfo
;
2105 sinfo
.analyse (ainfo
->type
);
2106 if (sinfo
.number_of_fields () == 1
2107 && sinfo
.field_type(0)->code () == TYPE_CODE_COMPLEX
)
2109 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2110 except we use the type of the complex field instead of the
2111 type from AINFO, and the first location might be at a non-zero
2113 if (TYPE_LENGTH (sinfo
.field_type (0)) <= (2 * cinfo
->flen
)
2114 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2115 && !ainfo
->is_unnamed
)
2118 int len
= TYPE_LENGTH (sinfo
.field_type (0)) / 2;
2119 int offset
= sinfo
.field_offset (0);
2121 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2122 &cinfo
->float_regs
, len
,
2124 gdb_assert (result
);
2126 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2127 &cinfo
->float_regs
, len
,
2129 gdb_assert (result
);
2132 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2136 if (sinfo
.number_of_fields () == 1
2137 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
)
2139 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2140 except we use the type of the first scalar field instead of
2141 the type from AINFO. Also the location might be at a non-zero
2143 if (TYPE_LENGTH (sinfo
.field_type (0)) > cinfo
->flen
2144 || ainfo
->is_unnamed
)
2145 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2148 int offset
= sinfo
.field_offset (0);
2149 int len
= TYPE_LENGTH (sinfo
.field_type (0));
2151 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2154 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2159 if (sinfo
.number_of_fields () == 2
2160 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2161 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2162 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2163 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
2164 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2166 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2167 int offset
= sinfo
.field_offset (0);
2168 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2169 &cinfo
->float_regs
, len0
, offset
))
2170 error (_("failed during argument setup"));
2172 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2173 offset
= sinfo
.field_offset (1);
2174 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
2175 - TYPE_LENGTH (sinfo
.field_type (0))));
2177 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2180 error (_("failed during argument setup"));
2184 if (sinfo
.number_of_fields () == 2
2185 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2186 && (sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2187 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2188 && is_integral_type (sinfo
.field_type (1))
2189 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
2191 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2192 int offset
= sinfo
.field_offset (0);
2193 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2194 &cinfo
->float_regs
, len0
, offset
))
2195 error (_("failed during argument setup"));
2197 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2198 offset
= sinfo
.field_offset (1);
2199 gdb_assert (len1
<= cinfo
->xlen
);
2200 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2201 &cinfo
->int_regs
, len1
, offset
))
2202 error (_("failed during argument setup"));
2206 if (sinfo
.number_of_fields () == 2
2207 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2208 && (is_integral_type (sinfo
.field_type (0))
2209 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
2210 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2211 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
2213 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2214 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2216 gdb_assert (len0
<= cinfo
->xlen
);
2217 gdb_assert (len1
<= cinfo
->flen
);
2219 int offset
= sinfo
.field_offset (0);
2220 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2221 &cinfo
->int_regs
, len0
, offset
))
2222 error (_("failed during argument setup"));
2224 offset
= sinfo
.field_offset (1);
2225 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2228 error (_("failed during argument setup"));
2234 /* Non of the structure flattening cases apply, so we just pass using
2236 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2239 /* Assign a location to call (or return) argument AINFO, the location is
2240 selected from CINFO which holds information about what call argument
2241 locations are available for use next. The TYPE is the type of the
2242 argument being passed, this information is recorded into AINFO (along
2243 with some additional information derived from the type). IS_UNNAMED
2244 is true if this is an unnamed (stdarg) argument, this info is also
2245 recorded into AINFO.
2247 After assigning a location to AINFO, CINFO will have been updated. */
2250 riscv_arg_location (struct gdbarch
*gdbarch
,
2251 struct riscv_arg_info
*ainfo
,
2252 struct riscv_call_info
*cinfo
,
2253 struct type
*type
, bool is_unnamed
)
2256 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
2257 ainfo
->align
= type_align (ainfo
->type
);
2258 ainfo
->is_unnamed
= is_unnamed
;
2259 ainfo
->contents
= nullptr;
2260 ainfo
->argloc
[0].c_length
= 0;
2261 ainfo
->argloc
[1].c_length
= 0;
2263 switch (ainfo
->type
->code ())
2266 case TYPE_CODE_BOOL
:
2267 case TYPE_CODE_CHAR
:
2268 case TYPE_CODE_RANGE
:
2269 case TYPE_CODE_ENUM
:
2271 if (ainfo
->length
<= cinfo
->xlen
)
2273 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2274 ainfo
->length
= cinfo
->xlen
;
2276 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2278 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2279 ainfo
->length
= 2 * cinfo
->xlen
;
2282 /* Recalculate the alignment requirement. */
2283 ainfo
->align
= type_align (ainfo
->type
);
2284 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2288 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2291 case TYPE_CODE_COMPLEX
:
2292 riscv_call_arg_complex_float (ainfo
, cinfo
);
2295 case TYPE_CODE_STRUCT
:
2296 riscv_call_arg_struct (ainfo
, cinfo
);
2300 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2305 /* Used for printing debug information about the call argument location in
2306 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2307 addresses for the location of pass-by-reference and
2308 arguments-on-the-stack memory areas. */
2311 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2312 struct riscv_arg_info
*info
,
2313 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2315 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2316 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2317 switch (info
->argloc
[0].loc_type
)
2319 case riscv_arg_info::location::in_reg
:
2321 (stream
, ", register %s",
2322 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2323 if (info
->argloc
[0].c_length
< info
->length
)
2325 switch (info
->argloc
[1].loc_type
)
2327 case riscv_arg_info::location::in_reg
:
2329 (stream
, ", register %s",
2330 gdbarch_register_name (gdbarch
,
2331 info
->argloc
[1].loc_data
.regno
));
2334 case riscv_arg_info::location::on_stack
:
2335 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2336 info
->argloc
[1].loc_data
.offset
);
2339 case riscv_arg_info::location::by_ref
:
2341 /* The second location should never be a reference, any
2342 argument being passed by reference just places its address
2343 in the first location and is done. */
2344 error (_("invalid argument location"));
2348 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2349 fprintf_unfiltered (stream
, " (offset 0x%x)",
2350 info
->argloc
[1].c_offset
);
2354 case riscv_arg_info::location::on_stack
:
2355 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2356 info
->argloc
[0].loc_data
.offset
);
2359 case riscv_arg_info::location::by_ref
:
2361 (stream
, ", by reference, data at offset 0x%x (%s)",
2362 info
->argloc
[0].loc_data
.offset
,
2363 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2364 if (info
->argloc
[1].loc_type
2365 == riscv_arg_info::location::in_reg
)
2367 (stream
, ", address in register %s",
2368 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2371 gdb_assert (info
->argloc
[1].loc_type
2372 == riscv_arg_info::location::on_stack
);
2374 (stream
, ", address on stack at offset 0x%x (%s)",
2375 info
->argloc
[1].loc_data
.offset
,
2376 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2381 gdb_assert_not_reached (_("unknown argument location type"));
2385 /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA
2386 into a buffer that is at least as big as the register REGNUM, padding
2387 out the DATA with either 0x00, or 0xff. For floating point registers
2388 0xff is used, for everyone else 0x00 is used. */
2391 riscv_regcache_cooked_write (int regnum
, const gdb_byte
*data
, int len
,
2392 struct regcache
*regcache
, int flen
)
2394 gdb_byte tmp
[sizeof (ULONGEST
)];
2396 /* FP values in FP registers must be NaN-boxed. */
2397 if (riscv_is_fp_regno_p (regnum
) && len
< flen
)
2398 memset (tmp
, -1, sizeof (tmp
));
2400 memset (tmp
, 0, sizeof (tmp
));
2401 memcpy (tmp
, data
, len
);
2402 regcache
->cooked_write (regnum
, tmp
);
2405 /* Implement the push dummy call gdbarch callback. */
2408 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2409 struct value
*function
,
2410 struct regcache
*regcache
,
2413 struct value
**args
,
2415 function_call_return_method return_method
,
2416 CORE_ADDR struct_addr
)
2419 CORE_ADDR sp_args
, sp_refs
;
2420 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2422 struct riscv_arg_info
*arg_info
=
2423 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2425 struct riscv_call_info
call_info (gdbarch
);
2429 struct type
*ftype
= check_typedef (value_type (function
));
2431 if (ftype
->code () == TYPE_CODE_PTR
)
2432 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
2434 /* We'll use register $a0 if we're returning a struct. */
2435 if (return_method
== return_method_struct
)
2436 ++call_info
.int_regs
.next_regnum
;
2438 for (i
= 0; i
< nargs
; ++i
)
2440 struct value
*arg_value
;
2441 struct type
*arg_type
;
2442 struct riscv_arg_info
*info
= &arg_info
[i
];
2444 arg_value
= args
[i
];
2445 arg_type
= check_typedef (value_type (arg_value
));
2447 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
2448 TYPE_VARARGS (ftype
) && i
>= ftype
->num_fields ());
2450 if (info
->type
!= arg_type
)
2451 arg_value
= value_cast (info
->type
, arg_value
);
2452 info
->contents
= value_contents (arg_value
);
2455 /* Adjust the stack pointer and align it. */
2456 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2457 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2459 if (riscv_debug_infcall
> 0)
2461 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2462 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2463 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2464 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2465 call_info
.xlen
, call_info
.flen
);
2466 if (return_method
== return_method_struct
)
2467 fprintf_unfiltered (gdb_stdlog
,
2468 "[*] struct return pointer in register $A0\n");
2469 for (i
= 0; i
< nargs
; ++i
)
2471 struct riscv_arg_info
*info
= &arg_info
[i
];
2473 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2474 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2475 fprintf_unfiltered (gdb_stdlog
, "\n");
2477 if (call_info
.memory
.arg_offset
> 0
2478 || call_info
.memory
.ref_offset
> 0)
2480 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2481 core_addr_to_string (osp
));
2482 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2483 call_info
.memory
.arg_offset
);
2484 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2485 call_info
.memory
.ref_offset
);
2486 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2487 core_addr_to_string_nz (osp
- sp
));
2491 /* Now load the argument into registers, or onto the stack. */
2493 if (return_method
== return_method_struct
)
2495 gdb_byte buf
[sizeof (LONGEST
)];
2497 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2498 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
2501 for (i
= 0; i
< nargs
; ++i
)
2504 int second_arg_length
= 0;
2505 const gdb_byte
*second_arg_data
;
2506 struct riscv_arg_info
*info
= &arg_info
[i
];
2508 gdb_assert (info
->length
> 0);
2510 switch (info
->argloc
[0].loc_type
)
2512 case riscv_arg_info::location::in_reg
:
2514 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2516 riscv_regcache_cooked_write (info
->argloc
[0].loc_data
.regno
,
2518 + info
->argloc
[0].c_offset
),
2519 info
->argloc
[0].c_length
,
2520 regcache
, call_info
.flen
);
2522 (((info
->argloc
[0].c_length
+ info
->argloc
[0].c_offset
) < info
->length
)
2523 ? info
->argloc
[1].c_length
: 0);
2524 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2528 case riscv_arg_info::location::on_stack
:
2529 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2530 write_memory (dst
, info
->contents
, info
->length
);
2531 second_arg_length
= 0;
2534 case riscv_arg_info::location::by_ref
:
2535 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2536 write_memory (dst
, info
->contents
, info
->length
);
2538 second_arg_length
= call_info
.xlen
;
2539 second_arg_data
= (gdb_byte
*) &dst
;
2543 gdb_assert_not_reached (_("unknown argument location type"));
2546 if (second_arg_length
> 0)
2548 switch (info
->argloc
[1].loc_type
)
2550 case riscv_arg_info::location::in_reg
:
2552 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2553 && second_arg_length
<= call_info
.flen
)
2554 || second_arg_length
<= call_info
.xlen
);
2555 riscv_regcache_cooked_write (info
->argloc
[1].loc_data
.regno
,
2558 regcache
, call_info
.flen
);
2562 case riscv_arg_info::location::on_stack
:
2566 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2567 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2571 case riscv_arg_info::location::by_ref
:
2573 /* The second location should never be a reference, any
2574 argument being passed by reference just places its address
2575 in the first location and is done. */
2576 error (_("invalid argument location"));
2582 /* Set the dummy return value to bp_addr.
2583 A dummy breakpoint will be setup to execute the call. */
2585 if (riscv_debug_infcall
> 0)
2586 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2587 core_addr_to_string (bp_addr
));
2588 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2590 /* Finally, update the stack pointer. */
2592 if (riscv_debug_infcall
> 0)
2593 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2594 core_addr_to_string (sp
));
2595 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2600 /* Implement the return_value gdbarch method. */
2602 static enum return_value_convention
2603 riscv_return_value (struct gdbarch
*gdbarch
,
2604 struct value
*function
,
2606 struct regcache
*regcache
,
2608 const gdb_byte
*writebuf
)
2610 struct riscv_call_info
call_info (gdbarch
);
2611 struct riscv_arg_info info
;
2612 struct type
*arg_type
;
2614 arg_type
= check_typedef (type
);
2615 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
2617 if (riscv_debug_infcall
> 0)
2619 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2620 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2621 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2622 fprintf_unfiltered (gdb_stdlog
, "\n");
2625 if (readbuf
!= nullptr || writebuf
!= nullptr)
2627 unsigned int arg_len
;
2628 struct value
*abi_val
;
2629 gdb_byte
*old_readbuf
= nullptr;
2632 /* We only do one thing at a time. */
2633 gdb_assert (readbuf
== nullptr || writebuf
== nullptr);
2635 /* In some cases the argument is not returned as the declared type,
2636 and we need to cast to or from the ABI type in order to
2637 correctly access the argument. When writing to the machine we
2638 do the cast here, when reading from the machine the cast occurs
2639 later, after extracting the value. As the ABI type can be
2640 larger than the declared type, then the read or write buffers
2641 passed in might be too small. Here we ensure that we are using
2642 buffers of sufficient size. */
2643 if (writebuf
!= nullptr)
2645 struct value
*arg_val
= value_from_contents (arg_type
, writebuf
);
2646 abi_val
= value_cast (info
.type
, arg_val
);
2647 writebuf
= value_contents_raw (abi_val
);
2651 abi_val
= allocate_value (info
.type
);
2652 old_readbuf
= readbuf
;
2653 readbuf
= value_contents_raw (abi_val
);
2655 arg_len
= TYPE_LENGTH (info
.type
);
2657 switch (info
.argloc
[0].loc_type
)
2659 /* Return value in register(s). */
2660 case riscv_arg_info::location::in_reg
:
2662 regnum
= info
.argloc
[0].loc_data
.regno
;
2663 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
2664 gdb_assert (info
.argloc
[0].c_length
2665 <= register_size (gdbarch
, regnum
));
2669 gdb_byte
*ptr
= readbuf
+ info
.argloc
[0].c_offset
;
2670 regcache
->cooked_read_part (regnum
, 0,
2671 info
.argloc
[0].c_length
,
2677 const gdb_byte
*ptr
= writebuf
+ info
.argloc
[0].c_offset
;
2678 riscv_regcache_cooked_write (regnum
, ptr
,
2679 info
.argloc
[0].c_length
,
2680 regcache
, call_info
.flen
);
2683 /* A return value in register can have a second part in a
2685 if (info
.argloc
[1].c_length
> 0)
2687 switch (info
.argloc
[1].loc_type
)
2689 case riscv_arg_info::location::in_reg
:
2690 regnum
= info
.argloc
[1].loc_data
.regno
;
2692 gdb_assert ((info
.argloc
[0].c_length
2693 + info
.argloc
[1].c_length
) <= arg_len
);
2694 gdb_assert (info
.argloc
[1].c_length
2695 <= register_size (gdbarch
, regnum
));
2699 readbuf
+= info
.argloc
[1].c_offset
;
2700 regcache
->cooked_read_part (regnum
, 0,
2701 info
.argloc
[1].c_length
,
2708 = writebuf
+ info
.argloc
[1].c_offset
;
2709 riscv_regcache_cooked_write
2710 (regnum
, ptr
, info
.argloc
[1].c_length
,
2711 regcache
, call_info
.flen
);
2715 case riscv_arg_info::location::by_ref
:
2716 case riscv_arg_info::location::on_stack
:
2718 error (_("invalid argument location"));
2725 /* Return value by reference will have its address in A0. */
2726 case riscv_arg_info::location::by_ref
:
2730 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2732 if (readbuf
!= nullptr)
2733 read_memory (addr
, readbuf
, info
.length
);
2734 if (writebuf
!= nullptr)
2735 write_memory (addr
, writebuf
, info
.length
);
2739 case riscv_arg_info::location::on_stack
:
2741 error (_("invalid argument location"));
2745 /* This completes the cast from abi type back to the declared type
2746 in the case that we are reading from the machine. See the
2747 comment at the head of this block for more details. */
2748 if (readbuf
!= nullptr)
2750 struct value
*arg_val
= value_cast (arg_type
, abi_val
);
2751 memcpy (old_readbuf
, value_contents_raw (arg_val
),
2752 TYPE_LENGTH (arg_type
));
2756 switch (info
.argloc
[0].loc_type
)
2758 case riscv_arg_info::location::in_reg
:
2759 return RETURN_VALUE_REGISTER_CONVENTION
;
2760 case riscv_arg_info::location::by_ref
:
2761 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2762 case riscv_arg_info::location::on_stack
:
2764 error (_("invalid argument location"));
2768 /* Implement the frame_align gdbarch method. */
2771 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2773 return align_down (addr
, 16);
2776 /* Generate, or return the cached frame cache for the RiscV frame
2779 static struct riscv_unwind_cache
*
2780 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2782 CORE_ADDR pc
, start_addr
;
2783 struct riscv_unwind_cache
*cache
;
2784 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2787 if ((*this_cache
) != NULL
)
2788 return (struct riscv_unwind_cache
*) *this_cache
;
2790 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
2791 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
2792 (*this_cache
) = cache
;
2794 /* Scan the prologue, filling in the cache. */
2795 start_addr
= get_frame_func (this_frame
);
2796 pc
= get_frame_pc (this_frame
);
2797 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
2799 /* We can now calculate the frame base address. */
2801 = (get_frame_register_signed (this_frame
, cache
->frame_base_reg
)
2802 + cache
->frame_base_offset
);
2803 if (riscv_debug_unwinder
)
2804 fprintf_unfiltered (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
2805 core_addr_to_string (cache
->frame_base
),
2806 gdbarch_register_name (gdbarch
,
2807 cache
->frame_base_reg
),
2808 cache
->frame_base_offset
);
2810 /* The prologue scanner sets the address of registers stored to the stack
2811 as the offset of that register from the frame base. The prologue
2812 scanner doesn't know the actual frame base value, and so is unable to
2813 compute the exact address. We do now know the frame base value, so
2814 update the address of registers stored to the stack. */
2815 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
2816 for (regno
= 0; regno
< numregs
; ++regno
)
2818 if (trad_frame_addr_p (cache
->regs
, regno
))
2819 cache
->regs
[regno
].addr
+= cache
->frame_base
;
2822 /* The previous $pc can be found wherever the $ra value can be found.
2823 The previous $ra value is gone, this would have been stored be the
2824 previous frame if required. */
2825 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
2826 trad_frame_set_unknown (cache
->regs
, RISCV_RA_REGNUM
);
2828 /* Build the frame id. */
2829 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
2831 /* The previous $sp value is the frame base value. */
2832 trad_frame_set_value (cache
->regs
, gdbarch_sp_regnum (gdbarch
),
2838 /* Implement the this_id callback for RiscV frame unwinder. */
2841 riscv_frame_this_id (struct frame_info
*this_frame
,
2842 void **prologue_cache
,
2843 struct frame_id
*this_id
)
2845 struct riscv_unwind_cache
*cache
;
2849 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2850 *this_id
= cache
->this_id
;
2852 catch (const gdb_exception_error
&ex
)
2854 /* Ignore errors, this leaves the frame id as the predefined outer
2855 frame id which terminates the backtrace at this point. */
2859 /* Implement the prev_register callback for RiscV frame unwinder. */
2861 static struct value
*
2862 riscv_frame_prev_register (struct frame_info
*this_frame
,
2863 void **prologue_cache
,
2866 struct riscv_unwind_cache
*cache
;
2868 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2869 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
2872 /* Structure defining the RiscV normal frame unwind functions. Since we
2873 are the fallback unwinder (DWARF unwinder is used first), we use the
2874 default frame sniffer, which always accepts the frame. */
2876 static const struct frame_unwind riscv_frame_unwind
=
2878 /*.type =*/ NORMAL_FRAME
,
2879 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2880 /*.this_id =*/ riscv_frame_this_id
,
2881 /*.prev_register =*/ riscv_frame_prev_register
,
2882 /*.unwind_data =*/ NULL
,
2883 /*.sniffer =*/ default_frame_sniffer
,
2884 /*.dealloc_cache =*/ NULL
,
2885 /*.prev_arch =*/ NULL
,
2888 /* Extract a set of required target features out of INFO, specifically the
2889 bfd being executed is examined to see what target features it requires.
2890 IF there is no current bfd, or the bfd doesn't indicate any useful
2891 features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
2893 static struct riscv_gdbarch_features
2894 riscv_features_from_gdbarch_info (const struct gdbarch_info info
)
2896 struct riscv_gdbarch_features features
;
2898 /* Now try to improve on the defaults by looking at the binary we are
2899 going to execute. We assume the user knows what they are doing and
2900 that the target will match the binary. Remember, this code path is
2901 only used at all if the target hasn't given us a description, so this
2902 is really a last ditched effort to do something sane before giving
2904 if (info
.abfd
!= NULL
2905 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2907 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2908 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2910 if (eclass
== ELFCLASS32
)
2912 else if (eclass
== ELFCLASS64
)
2915 internal_error (__FILE__
, __LINE__
,
2916 _("unknown ELF header class %d"), eclass
);
2918 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2920 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2927 /* Find a suitable default target description. Use the contents of INFO,
2928 specifically the bfd object being executed, to guide the selection of a
2929 suitable default target description. */
2931 static const struct target_desc
*
2932 riscv_find_default_target_description (const struct gdbarch_info info
)
2934 /* Extract desired feature set from INFO. */
2935 struct riscv_gdbarch_features features
2936 = riscv_features_from_gdbarch_info (info
);
2938 /* If the XLEN field is still 0 then we got nothing useful from INFO. In
2939 this case we fall back to a minimal useful target, 8-byte x-registers,
2940 with no floating point. */
2941 if (features
.xlen
== 0)
2944 /* Now build a target description based on the feature set. */
2945 return riscv_lookup_target_description (features
);
2948 /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
2949 is updated with the register numbers for each register as listed in
2950 REG_SET. If any register marked as required in REG_SET is not found in
2951 FEATURE then this function returns false, otherwise, it returns true. */
2954 riscv_check_tdesc_feature (struct tdesc_arch_data
*tdesc_data
,
2955 const struct tdesc_feature
*feature
,
2956 const struct riscv_register_feature
*reg_set
)
2958 for (const auto ®
: reg_set
->registers
)
2962 for (const char *name
: reg
.names
)
2965 tdesc_numbered_register (feature
, tdesc_data
, reg
.regnum
, name
);
2971 if (!found
&& reg
.required_p
)
2978 /* Add all the expected register sets into GDBARCH. */
2981 riscv_add_reggroups (struct gdbarch
*gdbarch
)
2983 /* Add predefined register groups. */
2984 reggroup_add (gdbarch
, all_reggroup
);
2985 reggroup_add (gdbarch
, save_reggroup
);
2986 reggroup_add (gdbarch
, restore_reggroup
);
2987 reggroup_add (gdbarch
, system_reggroup
);
2988 reggroup_add (gdbarch
, vector_reggroup
);
2989 reggroup_add (gdbarch
, general_reggroup
);
2990 reggroup_add (gdbarch
, float_reggroup
);
2992 /* Add RISC-V specific register groups. */
2993 reggroup_add (gdbarch
, csr_reggroup
);
2996 /* Create register aliases for all the alternative names that exist for
2997 registers in REG_SET. */
3000 riscv_setup_register_aliases (struct gdbarch
*gdbarch
,
3001 const struct riscv_register_feature
*reg_set
)
3003 for (auto ®
: reg_set
->registers
)
3005 /* The first item in the names list is the preferred name for the
3006 register, this is what RISCV_REGISTER_NAME returns, and so we
3007 don't need to create an alias with that name here. */
3008 for (int i
= 1; i
< reg
.names
.size (); ++i
)
3009 user_reg_add (gdbarch
, reg
.names
[i
], value_of_riscv_user_reg
,
3014 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3017 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3019 if (reg
< RISCV_DWARF_REGNUM_X31
)
3020 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3022 else if (reg
< RISCV_DWARF_REGNUM_F31
)
3023 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3028 /* Implement the gcc_target_options method. We have to select the arch and abi
3029 from the feature info. We have enough feature info to select the abi, but
3030 not enough info for the arch given all of the possible architecture
3031 extensions. So choose reasonable defaults for now. */
3034 riscv_gcc_target_options (struct gdbarch
*gdbarch
)
3036 int isa_xlen
= riscv_isa_xlen (gdbarch
);
3037 int isa_flen
= riscv_isa_flen (gdbarch
);
3038 int abi_xlen
= riscv_abi_xlen (gdbarch
);
3039 int abi_flen
= riscv_abi_flen (gdbarch
);
3040 std::string target_options
;
3042 target_options
= "-march=rv";
3044 target_options
+= "64";
3046 target_options
+= "32";
3048 target_options
+= "gc";
3049 else if (isa_flen
== 4)
3050 target_options
+= "imafc";
3052 target_options
+= "imac";
3054 target_options
+= " -mabi=";
3056 target_options
+= "lp64";
3058 target_options
+= "ilp32";
3060 target_options
+= "d";
3061 else if (abi_flen
== 4)
3062 target_options
+= "f";
3064 /* The gdb loader doesn't handle link-time relaxation relocations. */
3065 target_options
+= " -mno-relax";
3067 return target_options
;
3070 /* Implement the gnu_triplet_regexp method. A single compiler supports both
3071 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
3072 recommended) riscv. */
3075 riscv_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
3077 return "riscv(32|64)?";
3080 /* Initialize the current architecture based on INFO. If possible,
3081 re-use an architecture from ARCHES, which is a list of
3082 architectures already created during this debugging session.
3084 Called e.g. at program startup, when reading a core file, and when
3085 reading a binary file. */
3087 static struct gdbarch
*
3088 riscv_gdbarch_init (struct gdbarch_info info
,
3089 struct gdbarch_list
*arches
)
3091 struct gdbarch
*gdbarch
;
3092 struct gdbarch_tdep
*tdep
;
3093 struct riscv_gdbarch_features features
;
3094 const struct target_desc
*tdesc
= info
.target_desc
;
3096 /* Ensure we always have a target description. */
3097 if (!tdesc_has_registers (tdesc
))
3098 tdesc
= riscv_find_default_target_description (info
);
3101 if (riscv_debug_gdbarch
)
3102 fprintf_unfiltered (gdb_stdlog
, "Have got a target description\n");
3104 const struct tdesc_feature
*feature_cpu
3105 = tdesc_find_feature (tdesc
, riscv_xreg_feature
.name
);
3106 const struct tdesc_feature
*feature_fpu
3107 = tdesc_find_feature (tdesc
, riscv_freg_feature
.name
);
3108 const struct tdesc_feature
*feature_virtual
3109 = tdesc_find_feature (tdesc
, riscv_virtual_feature
.name
);
3110 const struct tdesc_feature
*feature_csr
3111 = tdesc_find_feature (tdesc
, riscv_csr_feature
.name
);
3113 if (feature_cpu
== NULL
)
3116 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3118 bool valid_p
= riscv_check_tdesc_feature (tdesc_data
,
3120 &riscv_xreg_feature
);
3123 /* Check that all of the core cpu registers have the same bitsize. */
3124 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
3126 for (auto &tdesc_reg
: feature_cpu
->registers
)
3127 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
3129 if (riscv_debug_gdbarch
)
3132 "From target-description, xlen = %d\n", xlen_bitsize
);
3134 features
.xlen
= (xlen_bitsize
/ 8);
3137 if (feature_fpu
!= NULL
)
3139 valid_p
&= riscv_check_tdesc_feature (tdesc_data
, feature_fpu
,
3140 &riscv_freg_feature
);
3142 /* Search for the first floating point register (by any alias), to
3143 determine the bitsize. */
3145 const auto &fp0
= riscv_freg_feature
.registers
[0];
3147 for (const char *name
: fp0
.names
)
3149 if (tdesc_unnumbered_register (feature_fpu
, name
))
3151 bitsize
= tdesc_register_bitsize (feature_fpu
, name
);
3156 gdb_assert (bitsize
!= -1);
3157 features
.flen
= (bitsize
/ 8);
3159 if (riscv_debug_gdbarch
)
3162 "From target-description, flen = %d\n", bitsize
);
3168 if (riscv_debug_gdbarch
)
3171 "No FPU in target-description, assume soft-float ABI\n");
3174 if (feature_virtual
)
3175 riscv_check_tdesc_feature (tdesc_data
, feature_virtual
,
3176 &riscv_virtual_feature
);
3179 riscv_check_tdesc_feature (tdesc_data
, feature_csr
,
3180 &riscv_csr_feature
);
3184 if (riscv_debug_gdbarch
)
3185 fprintf_unfiltered (gdb_stdlog
, "Target description is not valid\n");
3186 tdesc_data_cleanup (tdesc_data
);
3190 /* Have a look at what the supplied (if any) bfd object requires of the
3191 target, then check that this matches with what the target is
3193 struct riscv_gdbarch_features abi_features
3194 = riscv_features_from_gdbarch_info (info
);
3195 /* In theory a binary compiled for RV32 could run on an RV64 target,
3196 however, this has not been tested in GDB yet, so for now we require
3197 that the requested xlen match the targets xlen. */
3198 if (abi_features
.xlen
!= 0 && abi_features
.xlen
!= features
.xlen
)
3199 error (_("bfd requires xlen %d, but target has xlen %d"),
3200 abi_features
.xlen
, features
.xlen
);
3201 /* We do support running binaries compiled for 32-bit float on targets
3202 with 64-bit float, so we only complain if the binary requires more
3203 than the target has available. */
3204 if (abi_features
.flen
> features
.flen
)
3205 error (_("bfd requires flen %d, but target has flen %d"),
3206 abi_features
.flen
, features
.flen
);
3208 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3209 features from the INFO object. In this case we assume that the xlen
3210 abi matches the hardware. */
3211 if (abi_features
.xlen
== 0)
3212 abi_features
.xlen
= features
.xlen
;
3214 /* Find a candidate among the list of pre-declared architectures. */
3215 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3217 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3219 /* Check that the feature set of the ARCHES matches the feature set
3220 we are looking for. If it doesn't then we can't reuse this
3222 struct gdbarch_tdep
*other_tdep
= gdbarch_tdep (arches
->gdbarch
);
3224 if (other_tdep
->isa_features
!= features
3225 || other_tdep
->abi_features
!= abi_features
)
3233 tdesc_data_cleanup (tdesc_data
);
3234 return arches
->gdbarch
;
3237 /* None found, so create a new architecture from the information provided. */
3238 tdep
= new (struct gdbarch_tdep
);
3239 gdbarch
= gdbarch_alloc (&info
, tdep
);
3240 tdep
->isa_features
= features
;
3241 tdep
->abi_features
= abi_features
;
3243 /* Target data types. */
3244 set_gdbarch_short_bit (gdbarch
, 16);
3245 set_gdbarch_int_bit (gdbarch
, 32);
3246 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3247 set_gdbarch_long_long_bit (gdbarch
, 64);
3248 set_gdbarch_float_bit (gdbarch
, 32);
3249 set_gdbarch_double_bit (gdbarch
, 64);
3250 set_gdbarch_long_double_bit (gdbarch
, 128);
3251 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3252 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3253 set_gdbarch_char_signed (gdbarch
, 0);
3254 set_gdbarch_type_align (gdbarch
, riscv_type_align
);
3256 /* Information about the target architecture. */
3257 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
3258 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3259 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3260 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3262 /* Functions to analyze frames. */
3263 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3264 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3265 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3267 /* Functions handling dummy frames. */
3268 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3269 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3270 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3272 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3274 dwarf2_append_unwinders (gdbarch
);
3275 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3277 /* Register architecture. */
3278 riscv_add_reggroups (gdbarch
);
3280 /* Internal <-> external register number maps. */
3281 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3283 /* We reserve all possible register numbers for the known registers.
3284 This means the target description mechanism will add any target
3285 specific registers after this number. This helps make debugging GDB
3286 just a little easier. */
3287 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3289 /* We don't have to provide the count of 0 here (its the default) but
3290 include this line to make it explicit that, right now, we don't have
3291 any pseudo registers on RISC-V. */
3292 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
3294 /* Some specific register numbers GDB likes to know about. */
3295 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3296 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3298 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3300 /* Finalise the target description registers. */
3301 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3303 /* Override the register type callback setup by the target description
3304 mechanism. This allows us to provide special type for floating point
3306 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3308 /* Override the register name callback setup by the target description
3309 mechanism. This allows us to force our preferred names for the
3310 registers, no matter what the target description called them. */
3311 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
3313 /* Override the register group callback setup by the target description
3314 mechanism. This allows us to force registers into the groups we
3315 want, ignoring what the target tells us. */
3316 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
3318 /* Create register aliases for alternative register names. */
3319 riscv_setup_register_aliases (gdbarch
, &riscv_xreg_feature
);
3320 if (riscv_has_fp_regs (gdbarch
))
3321 riscv_setup_register_aliases (gdbarch
, &riscv_freg_feature
);
3322 riscv_setup_register_aliases (gdbarch
, &riscv_csr_feature
);
3324 /* Compile command hooks. */
3325 set_gdbarch_gcc_target_options (gdbarch
, riscv_gcc_target_options
);
3326 set_gdbarch_gnu_triplet_regexp (gdbarch
, riscv_gnu_triplet_regexp
);
3328 /* Hook in OS ABI-specific overrides, if they have been registered. */
3329 gdbarch_init_osabi (info
, gdbarch
);
3331 register_riscv_ravenscar_ops (gdbarch
);
3336 /* This decodes the current instruction and determines the address of the
3337 next instruction. */
3340 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
3342 struct gdbarch
*gdbarch
= regcache
->arch ();
3343 struct riscv_insn insn
;
3346 insn
.decode (gdbarch
, pc
);
3347 next_pc
= pc
+ insn
.length ();
3349 if (insn
.opcode () == riscv_insn::JAL
)
3350 next_pc
= pc
+ insn
.imm_signed ();
3351 else if (insn
.opcode () == riscv_insn::JALR
)
3354 regcache
->cooked_read (insn
.rs1 (), &source
);
3355 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
3357 else if (insn
.opcode () == riscv_insn::BEQ
)
3360 regcache
->cooked_read (insn
.rs1 (), &src1
);
3361 regcache
->cooked_read (insn
.rs2 (), &src2
);
3363 next_pc
= pc
+ insn
.imm_signed ();
3365 else if (insn
.opcode () == riscv_insn::BNE
)
3368 regcache
->cooked_read (insn
.rs1 (), &src1
);
3369 regcache
->cooked_read (insn
.rs2 (), &src2
);
3371 next_pc
= pc
+ insn
.imm_signed ();
3373 else if (insn
.opcode () == riscv_insn::BLT
)
3376 regcache
->cooked_read (insn
.rs1 (), &src1
);
3377 regcache
->cooked_read (insn
.rs2 (), &src2
);
3379 next_pc
= pc
+ insn
.imm_signed ();
3381 else if (insn
.opcode () == riscv_insn::BGE
)
3384 regcache
->cooked_read (insn
.rs1 (), &src1
);
3385 regcache
->cooked_read (insn
.rs2 (), &src2
);
3387 next_pc
= pc
+ insn
.imm_signed ();
3389 else if (insn
.opcode () == riscv_insn::BLTU
)
3391 ULONGEST src1
, src2
;
3392 regcache
->cooked_read (insn
.rs1 (), &src1
);
3393 regcache
->cooked_read (insn
.rs2 (), &src2
);
3395 next_pc
= pc
+ insn
.imm_signed ();
3397 else if (insn
.opcode () == riscv_insn::BGEU
)
3399 ULONGEST src1
, src2
;
3400 regcache
->cooked_read (insn
.rs1 (), &src1
);
3401 regcache
->cooked_read (insn
.rs2 (), &src2
);
3403 next_pc
= pc
+ insn
.imm_signed ();
3409 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3410 for the end of the sequence and put the breakpoint there. */
3413 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
3416 struct gdbarch
*gdbarch
= regcache
->arch ();
3417 struct riscv_insn insn
;
3418 CORE_ADDR cur_step_pc
= pc
;
3419 CORE_ADDR last_addr
= 0;
3421 /* First instruction has to be a load reserved. */
3422 insn
.decode (gdbarch
, cur_step_pc
);
3423 if (insn
.opcode () != riscv_insn::LR
)
3425 cur_step_pc
= cur_step_pc
+ insn
.length ();
3427 /* Next instruction should be branch to exit. */
3428 insn
.decode (gdbarch
, cur_step_pc
);
3429 if (insn
.opcode () != riscv_insn::BNE
)
3431 last_addr
= cur_step_pc
+ insn
.imm_signed ();
3432 cur_step_pc
= cur_step_pc
+ insn
.length ();
3434 /* Next instruction should be store conditional. */
3435 insn
.decode (gdbarch
, cur_step_pc
);
3436 if (insn
.opcode () != riscv_insn::SC
)
3438 cur_step_pc
= cur_step_pc
+ insn
.length ();
3440 /* Next instruction should be branch to start. */
3441 insn
.decode (gdbarch
, cur_step_pc
);
3442 if (insn
.opcode () != riscv_insn::BNE
)
3444 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
3446 cur_step_pc
= cur_step_pc
+ insn
.length ();
3448 /* We should now be at the end of the sequence. */
3449 if (cur_step_pc
!= last_addr
)
3452 *next_pc
= cur_step_pc
;
3456 /* This is called just before we want to resume the inferior, if we want to
3457 single-step it but there is no hardware or kernel single-step support. We
3458 find the target of the coming instruction and breakpoint it. */
3460 std::vector
<CORE_ADDR
>
3461 riscv_software_single_step (struct regcache
*regcache
)
3463 CORE_ADDR pc
, next_pc
;
3465 pc
= regcache_read_pc (regcache
);
3467 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
3470 next_pc
= riscv_next_pc (regcache
, pc
);
3475 /* Create RISC-V specific reggroups. */
3478 riscv_init_reggroups ()
3480 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
3483 void _initialize_riscv_tdep ();
3485 _initialize_riscv_tdep ()
3487 riscv_create_csr_aliases ();
3488 riscv_init_reggroups ();
3490 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
3492 /* Add root prefix command for all "set debug riscv" and "show debug
3494 add_basic_prefix_cmd ("riscv", no_class
,
3495 _("RISC-V specific debug commands."),
3496 &setdebugriscvcmdlist
, "set debug riscv ", 0,
3499 add_show_prefix_cmd ("riscv", no_class
,
3500 _("RISC-V specific debug commands."),
3501 &showdebugriscvcmdlist
, "show debug riscv ", 0,
3504 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
3505 &riscv_debug_breakpoints
, _("\
3506 Set riscv breakpoint debugging."), _("\
3507 Show riscv breakpoint debugging."), _("\
3508 When non-zero, print debugging information for the riscv specific parts\n\
3509 of the breakpoint mechanism."),
3511 show_riscv_debug_variable
,
3512 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3514 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
3515 &riscv_debug_infcall
, _("\
3516 Set riscv inferior call debugging."), _("\
3517 Show riscv inferior call debugging."), _("\
3518 When non-zero, print debugging information for the riscv specific parts\n\
3519 of the inferior call mechanism."),
3521 show_riscv_debug_variable
,
3522 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3524 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
3525 &riscv_debug_unwinder
, _("\
3526 Set riscv stack unwinding debugging."), _("\
3527 Show riscv stack unwinding debugging."), _("\
3528 When non-zero, print debugging information for the riscv specific parts\n\
3529 of the stack unwinding mechanism."),
3531 show_riscv_debug_variable
,
3532 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3534 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
3535 &riscv_debug_gdbarch
, _("\
3536 Set riscv gdbarch initialisation debugging."), _("\
3537 Show riscv gdbarch initialisation debugging."), _("\
3538 When non-zero, print debugging information for the riscv gdbarch\n\
3539 initialisation process."),
3541 show_riscv_debug_variable
,
3542 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3544 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3545 add_basic_prefix_cmd ("riscv", no_class
,
3546 _("RISC-V specific commands."),
3547 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
3549 add_show_prefix_cmd ("riscv", no_class
,
3550 _("RISC-V specific commands."),
3551 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
3554 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
3555 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
3556 &use_compressed_breakpoints
,
3558 Set debugger's use of compressed breakpoints."), _(" \
3559 Show debugger's use of compressed breakpoints."), _("\
3560 Debugging compressed code requires compressed breakpoints to be used. If\n\
3561 left to 'auto' then gdb will use them if the existing instruction is a\n\
3562 compressed instruction. If that doesn't give the correct behavior, then\n\
3563 this option can be used."),
3565 show_use_compressed_breakpoints
,