1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
58 /* The stack must be 16-byte aligned. */
59 #define SP_ALIGNMENT 16
61 /* Forward declarations. */
62 static bool riscv_has_feature (struct gdbarch
*gdbarch
, char feature
);
63 struct riscv_inferior_data
;
64 struct riscv_inferior_data
* riscv_inferior_data (struct inferior
*const inf
);
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Per inferior information for RiscV. */
78 struct riscv_inferior_data
80 /* True when MISA_VALUE is valid, otherwise false. */
83 /* If MISA_READ is true then MISA_VALUE holds the value of the MISA
84 register read from the target. */
88 /* Key created when the RiscV per-inferior data is registered. */
90 static const struct inferior_data
*riscv_inferior_data_reg
;
92 /* Architectural name for core registers. */
94 static const char * const riscv_gdb_reg_names
[RISCV_LAST_FP_REGNUM
+ 1] =
96 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
97 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
98 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
99 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
101 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
102 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
103 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
104 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
107 /* Maps "pretty" register names onto their GDB register number. */
109 struct register_alias
111 /* The register alias. Usually more descriptive than the
112 architectural name of the register. */
115 /* The GDB register number. */
119 /* Table of register aliases. */
121 static const struct register_alias riscv_register_aliases
[] =
189 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
190 #include "opcode/riscv-opc.h"
194 /* Controls whether we place compressed breakpoints or not. When in auto
195 mode GDB tries to determine if the target supports compressed
196 breakpoints, and uses them if it does. */
198 static enum auto_boolean use_compressed_breakpoints
;
200 /* The show callback for 'show riscv use-compressed-breakpoints'. */
203 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
204 struct cmd_list_element
*c
,
207 const char *additional_info
;
208 struct gdbarch
*gdbarch
= target_gdbarch ();
210 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
211 if (riscv_has_feature (gdbarch
, 'C'))
212 additional_info
= _(" (currently on)");
214 additional_info
= _(" (currently off)");
216 additional_info
= "";
218 fprintf_filtered (file
,
219 _("Debugger's use of compressed breakpoints is set "
220 "to %s%s.\n"), value
, additional_info
);
223 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
225 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
226 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
228 /* The show callback for the 'show riscv' prefix command. */
231 show_riscv_command (const char *args
, int from_tty
)
233 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
236 /* The set callback for the 'set riscv' prefix command. */
239 set_riscv_command (const char *args
, int from_tty
)
242 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
243 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
246 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
248 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
249 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
251 /* The show callback for the 'show debug riscv' prefix command. */
254 show_debug_riscv_command (const char *args
, int from_tty
)
256 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
259 /* The set callback for the 'set debug riscv' prefix command. */
262 set_debug_riscv_command (const char *args
, int from_tty
)
265 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
266 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
269 /* The show callback for all 'show debug riscv VARNAME' variables. */
272 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
273 struct cmd_list_element
*c
,
276 fprintf_filtered (file
,
277 _("RiscV debug variable `%s' is set to: %s\n"),
281 /* When this is set to non-zero debugging information about inferior calls
284 static unsigned int riscv_debug_infcall
= 0;
286 /* Read the MISA register from the target. The register will only be read
287 once, and the value read will be cached. If the register can't be read
288 from the target then a default value (0) will be returned. If the
289 pointer READ_P is not null, then the bool pointed to is updated to
290 indicate if the value returned was read from the target (true) or is the
294 riscv_read_misa_reg (bool *read_p
)
296 struct riscv_inferior_data
*inf_data
297 = riscv_inferior_data (current_inferior ());
299 if (!inf_data
->misa_read
&& target_has_registers
)
302 struct frame_info
*frame
= get_current_frame ();
306 value
= get_frame_register_unsigned (frame
, RISCV_CSR_MISA_REGNUM
);
308 CATCH (ex
, RETURN_MASK_ERROR
)
310 /* Old cores might have MISA located at a different offset. */
311 value
= get_frame_register_unsigned (frame
,
312 RISCV_CSR_LEGACY_MISA_REGNUM
);
316 inf_data
->misa_read
= true;
317 inf_data
->misa_value
= value
;
320 if (read_p
!= nullptr)
321 *read_p
= inf_data
->misa_read
;
323 return inf_data
->misa_value
;
326 /* Return true if FEATURE is available for the architecture GDBARCH. The
327 FEATURE should be one of the single character feature codes described in
328 the RiscV ISA manual, these are between 'A' and 'Z'. */
331 riscv_has_feature (struct gdbarch
*gdbarch
, char feature
)
333 bool have_read_misa
= false;
336 gdb_assert (feature
>= 'A' && feature
<= 'Z');
338 /* It would be nice to always check with the real target where possible,
339 however, for compressed instructions this is a bad idea.
341 The call to `set_gdbarch_decr_pc_after_break' is made just once per
342 GDBARCH and we decide at that point if we should decrement by 2 or 4
343 bytes based on whether the BFD has compressed instruction support or
346 If the BFD was not compiled with compressed instruction support, but we
347 are running on a target with compressed instructions then we might
348 place a 4-byte breakpoint, then decrement the $pc by 2 bytes leading to
351 It's safer if we just make decisions about compressed instruction
352 support based on the BFD. */
354 misa
= riscv_read_misa_reg (&have_read_misa
);
355 if (!have_read_misa
|| misa
== 0)
356 misa
= gdbarch_tdep (gdbarch
)->core_features
;
358 return (misa
& (1 << (feature
- 'A'))) != 0;
361 /* Return the width in bytes of the general purpose registers for GDBARCH.
362 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
366 riscv_isa_xlen (struct gdbarch
*gdbarch
)
368 switch (gdbarch_tdep (gdbarch
)->abi
.fields
.base_len
)
371 warning (_("unknown xlen size, assuming 4 bytes"));
381 /* Return the width in bytes of the floating point registers for GDBARCH.
382 If this architecture has no floating point registers, then return 0.
383 Possible values are 4, 8, or 16 for depending on which of single, double
384 or quad floating point support is available. */
387 riscv_isa_flen (struct gdbarch
*gdbarch
)
389 if (riscv_has_feature (gdbarch
, 'Q'))
391 else if (riscv_has_feature (gdbarch
, 'D'))
393 else if (riscv_has_feature (gdbarch
, 'F'))
399 /* Return true if the target for GDBARCH has floating point hardware. */
402 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
404 return (riscv_isa_flen (gdbarch
) > 0);
407 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
410 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
412 return (gdbarch_tdep (gdbarch
)->abi
.fields
.float_abi
!= 0);
415 /* Implement the breakpoint_kind_from_pc gdbarch method. */
418 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
420 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
422 if (riscv_has_feature (gdbarch
, 'C'))
427 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
433 /* Implement the sw_breakpoint_from_kind gdbarch method. */
435 static const gdb_byte
*
436 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
438 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
439 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
449 gdb_assert_not_reached ("unhandled breakpoint kind");
453 /* Callback function for user_reg_add. */
455 static struct value
*
456 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
458 const int *reg_p
= (const int *) baton
;
459 return value_of_register (*reg_p
, frame
);
462 /* Implement the register_name gdbarch method. */
465 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
467 /* Prefer to use the alias. */
468 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_REGNUM
)
472 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
473 if (regnum
== riscv_register_aliases
[i
].regnum
)
474 return riscv_register_aliases
[i
].name
;
477 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
478 return riscv_gdb_reg_names
[regnum
];
480 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
484 sprintf (buf
, "csr%d", regnum
- RISCV_FIRST_CSR_REGNUM
);
488 if (regnum
== RISCV_PRIV_REGNUM
)
494 /* Implement the register_type gdbarch method. */
497 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
501 if (regnum
< RISCV_FIRST_FP_REGNUM
)
503 if (regnum
== gdbarch_pc_regnum (gdbarch
)
504 || regnum
== RISCV_RA_REGNUM
)
505 return builtin_type (gdbarch
)->builtin_func_ptr
;
507 if (regnum
== RISCV_FP_REGNUM
508 || regnum
== RISCV_SP_REGNUM
509 || regnum
== RISCV_GP_REGNUM
510 || regnum
== RISCV_TP_REGNUM
)
511 return builtin_type (gdbarch
)->builtin_data_ptr
;
513 /* Remaining GPRs vary in size based on the current ISA. */
514 regsize
= riscv_isa_xlen (gdbarch
);
518 return builtin_type (gdbarch
)->builtin_uint32
;
520 return builtin_type (gdbarch
)->builtin_uint64
;
522 return builtin_type (gdbarch
)->builtin_uint128
;
524 internal_error (__FILE__
, __LINE__
,
525 _("unknown isa regsize %i"), regsize
);
528 else if (regnum
<= RISCV_LAST_FP_REGNUM
)
530 regsize
= riscv_isa_xlen (gdbarch
);
534 return builtin_type (gdbarch
)->builtin_float
;
536 return builtin_type (gdbarch
)->builtin_double
;
538 return builtin_type (gdbarch
)->builtin_long_double
;
540 internal_error (__FILE__
, __LINE__
,
541 _("unknown isa regsize %i"), regsize
);
544 else if (regnum
== RISCV_PRIV_REGNUM
)
545 return builtin_type (gdbarch
)->builtin_int8
;
548 if (regnum
== RISCV_CSR_FFLAGS_REGNUM
549 || regnum
== RISCV_CSR_FRM_REGNUM
550 || regnum
== RISCV_CSR_FCSR_REGNUM
)
551 return builtin_type (gdbarch
)->builtin_int32
;
553 regsize
= riscv_isa_xlen (gdbarch
);
557 return builtin_type (gdbarch
)->builtin_int32
;
559 return builtin_type (gdbarch
)->builtin_int64
;
561 return builtin_type (gdbarch
)->builtin_int128
;
563 internal_error (__FILE__
, __LINE__
,
564 _("unknown isa regsize %i"), regsize
);
569 /* Helper for riscv_print_registers_info, prints info for a single register
573 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
574 struct ui_file
*file
,
575 struct frame_info
*frame
,
578 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
579 struct value
*val
= value_of_register (regnum
, frame
);
580 struct type
*regtype
= value_type (val
);
581 int print_raw_format
;
582 enum tab_stops
{ value_column_1
= 15 };
584 fputs_filtered (name
, file
);
585 print_spaces_filtered (value_column_1
- strlen (name
), file
);
587 print_raw_format
= (value_entirely_available (val
)
588 && !value_optimized_out (val
));
590 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
)
592 struct value_print_options opts
;
593 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
594 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
596 get_user_print_options (&opts
);
600 value_embedded_offset (val
), 0,
601 file
, 0, val
, &opts
, current_language
);
603 if (print_raw_format
)
605 fprintf_filtered (file
, "\t(raw ");
606 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
608 fprintf_filtered (file
, ")");
613 struct value_print_options opts
;
615 /* Print the register in hex. */
616 get_formatted_print_options (&opts
, 'x');
619 value_embedded_offset (val
), 0,
620 file
, 0, val
, &opts
, current_language
);
622 if (print_raw_format
)
624 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
627 int size
= register_size (gdbarch
, regnum
);
630 d
= value_as_long (val
);
632 fprintf_filtered (file
,
633 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
634 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
635 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
636 (int) ((d
>> (xlen
- 1)) & 0x1),
637 (int) ((d
>> 24) & 0x1f),
638 (int) ((d
>> 19) & 0x1),
639 (int) ((d
>> 18) & 0x1),
640 (int) ((d
>> 17) & 0x1),
641 (int) ((d
>> 15) & 0x3),
642 (int) ((d
>> 13) & 0x3),
643 (int) ((d
>> 11) & 0x3),
644 (int) ((d
>> 9) & 0x3),
645 (int) ((d
>> 8) & 0x1),
646 (int) ((d
>> 7) & 0x1),
647 (int) ((d
>> 6) & 0x1),
648 (int) ((d
>> 5) & 0x1),
649 (int) ((d
>> 4) & 0x1),
650 (int) ((d
>> 3) & 0x1),
651 (int) ((d
>> 2) & 0x1),
652 (int) ((d
>> 1) & 0x1),
653 (int) ((d
>> 0) & 0x1));
655 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
661 d
= value_as_long (val
);
665 for (; base
> 0; base
--)
667 fprintf_filtered (file
, "\tRV%d", xlen
);
669 for (i
= 0; i
< 26; i
++)
672 fprintf_filtered (file
, "%c", 'A' + i
);
675 else if (regnum
== RISCV_CSR_FCSR_REGNUM
676 || regnum
== RISCV_CSR_FFLAGS_REGNUM
677 || regnum
== RISCV_CSR_FRM_REGNUM
)
681 d
= value_as_long (val
);
683 fprintf_filtered (file
, "\t");
684 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
685 fprintf_filtered (file
,
686 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
687 (int) ((d
>> 5) & 0x7),
688 (int) ((d
>> 4) & 0x1),
689 (int) ((d
>> 3) & 0x1),
690 (int) ((d
>> 2) & 0x1),
691 (int) ((d
>> 1) & 0x1),
692 (int) ((d
>> 0) & 0x1));
694 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
696 static const char * const sfrm
[] =
698 "RNE (round to nearest; ties to even)",
699 "RTZ (Round towards zero)",
700 "RDN (Round down towards -INF)",
701 "RUP (Round up towards +INF)",
702 "RMM (Round to nearest; ties to max magnitude)",
705 "dynamic rounding mode",
707 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
708 ? (d
>> 5) : d
) & 0x3;
710 fprintf_filtered (file
, "%sFRM:%i [%s]",
711 (regnum
== RISCV_CSR_FCSR_REGNUM
716 else if (regnum
== RISCV_PRIV_REGNUM
)
721 d
= value_as_long (val
);
726 static const char * const sprv
[] =
733 fprintf_filtered (file
, "\tprv:%d [%s]",
737 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
741 /* If not a vector register, print it also according to its
743 if (TYPE_VECTOR (regtype
) == 0)
745 get_user_print_options (&opts
);
747 fprintf_filtered (file
, "\t");
749 value_embedded_offset (val
), 0,
750 file
, 0, val
, &opts
, current_language
);
755 fprintf_filtered (file
, "\n");
758 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
762 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
763 struct reggroup
*reggroup
)
769 /* Used by 'info registers' and 'info registers <groupname>'. */
771 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
772 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
775 if (reggroup
== all_reggroup
)
777 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
779 /* Only include CSRs that have aliases. */
780 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
782 if (regnum
== riscv_register_aliases
[i
].regnum
)
787 else if (reggroup
== float_reggroup
)
788 return ((regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
789 || (regnum
== RISCV_CSR_FCSR_REGNUM
790 || regnum
== RISCV_CSR_FFLAGS_REGNUM
791 || regnum
== RISCV_CSR_FRM_REGNUM
));
792 else if (reggroup
== general_reggroup
)
793 return regnum
< RISCV_FIRST_FP_REGNUM
;
794 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
796 if (riscv_has_fp_regs (gdbarch
))
797 return regnum
<= RISCV_LAST_FP_REGNUM
;
799 return regnum
< RISCV_FIRST_FP_REGNUM
;
801 else if (reggroup
== system_reggroup
)
803 if (regnum
== RISCV_PRIV_REGNUM
)
805 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
807 /* Only include CSRs that have aliases. */
808 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
810 if (regnum
== riscv_register_aliases
[i
].regnum
)
815 else if (reggroup
== vector_reggroup
)
821 /* Implement the print_registers_info gdbarch method. This is used by
822 'info registers' and 'info all-registers'. */
825 riscv_print_registers_info (struct gdbarch
*gdbarch
,
826 struct ui_file
*file
,
827 struct frame_info
*frame
,
828 int regnum
, int print_all
)
832 /* Print one specified register. */
833 gdb_assert (regnum
<= RISCV_LAST_REGNUM
);
834 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
835 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
836 error (_("Not a valid register for the current processor type"));
837 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
841 struct reggroup
*reggroup
;
844 reggroup
= all_reggroup
;
846 reggroup
= general_reggroup
;
848 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
850 /* Zero never changes, so might as well hide by default. */
851 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
854 /* Registers with no name are not valid on this ISA. */
855 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
856 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
859 /* Is the register in the group we're interested in? */
860 if (!riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
))
863 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
868 /* Class that handles one decoded RiscV instruction. */
874 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
877 /* Unknown value is used at initialisation time. */
880 /* These instructions are all the ones we are interested in during the
891 /* Other instructions are not interesting during the prologue scan, and
906 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
908 /* Get the length of the instruction in bytes. */
912 /* Get the opcode for this instruction. */
913 enum opcode
opcode () const
916 /* Get destination register field for this instruction. This is only
917 valid if the OPCODE implies there is such a field for this
922 /* Get the RS1 register field for this instruction. This is only valid
923 if the OPCODE implies there is such a field for this instruction. */
927 /* Get the RS2 register field for this instruction. This is only valid
928 if the OPCODE implies there is such a field for this instruction. */
932 /* Get the immediate for this instruction in signed form. This is only
933 valid if the OPCODE implies there is such a field for this
935 int imm_signed () const
940 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
941 int decode_register_index (unsigned long opcode
, int offset
)
943 return (opcode
>> offset
) & 0x1F;
946 /* Helper for DECODE, decode 32-bit R-type instruction. */
947 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
950 m_rd
= decode_register_index (ival
, OP_SH_RD
);
951 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
952 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
955 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
956 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
959 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
960 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
963 /* Helper for DECODE, decode 32-bit I-type instruction. */
964 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
967 m_rd
= decode_register_index (ival
, OP_SH_RD
);
968 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
969 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
972 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
973 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
976 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
977 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
980 /* Helper for DECODE, decode 32-bit S-type instruction. */
981 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
984 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
985 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
986 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
989 /* Helper for DECODE, decode 32-bit U-type instruction. */
990 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
993 m_rd
= decode_register_index (ival
, OP_SH_RD
);
994 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
997 /* Fetch instruction from target memory at ADDR, return the content of
998 the instruction, and update LEN with the instruction length. */
999 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1000 CORE_ADDR addr
, int *len
);
1002 /* The length of the instruction in bytes. Should be 2 or 4. */
1005 /* The instruction opcode. */
1006 enum opcode m_opcode
;
1008 /* The three possible registers an instruction might reference. Not
1009 every instruction fills in all of these registers. Which fields are
1010 valid depends on the opcode. The naming of these fields matches the
1011 naming in the riscv isa manual. */
1016 /* Possible instruction immediate. This is only valid if the instruction
1017 format contains an immediate, not all instruction, whether this is
1018 valid depends on the opcode. Despite only having one format for now
1019 the immediate is packed into a union, later instructions might require
1020 an unsigned formatted immediate, having the union in place now will
1021 reduce the need for code churn later. */
1022 union riscv_insn_immediate
1024 riscv_insn_immediate ()
1034 /* Fetch instruction from target memory at ADDR, return the content of the
1035 instruction, and update LEN with the instruction length. */
1038 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1039 CORE_ADDR addr
, int *len
)
1041 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1043 int instlen
, status
;
1045 /* All insns are at least 16 bits. */
1046 status
= target_read_memory (addr
, buf
, 2);
1048 memory_error (TARGET_XFER_E_IO
, addr
);
1050 /* If we need more, grab it now. */
1051 instlen
= riscv_insn_length (buf
[0]);
1053 if (instlen
> sizeof (buf
))
1054 internal_error (__FILE__
, __LINE__
,
1055 _("%s: riscv_insn_length returned %i"),
1057 else if (instlen
> 2)
1059 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1061 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1064 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1067 /* Fetch from target memory an instruction at PC and decode it. */
1070 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1074 /* Fetch the instruction, and the instructions length. */
1075 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1079 if (is_add_insn (ival
))
1080 decode_r_type_insn (ADD
, ival
);
1081 else if (is_addw_insn (ival
))
1082 decode_r_type_insn (ADDW
, ival
);
1083 else if (is_addi_insn (ival
))
1084 decode_i_type_insn (ADDI
, ival
);
1085 else if (is_addiw_insn (ival
))
1086 decode_i_type_insn (ADDIW
, ival
);
1087 else if (is_auipc_insn (ival
))
1088 decode_u_type_insn (AUIPC
, ival
);
1089 else if (is_lui_insn (ival
))
1090 decode_u_type_insn (LUI
, ival
);
1091 else if (is_sd_insn (ival
))
1092 decode_s_type_insn (SD
, ival
);
1093 else if (is_sw_insn (ival
))
1094 decode_s_type_insn (SW
, ival
);
1096 /* None of the other fields are valid in this case. */
1099 else if (m_length
== 2)
1101 if (is_c_add_insn (ival
))
1102 decode_cr_type_insn (ADD
, ival
);
1103 else if (is_c_addw_insn (ival
))
1104 decode_cr_type_insn (ADDW
, ival
);
1105 else if (is_c_addi_insn (ival
))
1106 decode_ci_type_insn (ADDI
, ival
);
1107 else if (is_c_addiw_insn (ival
))
1108 decode_ci_type_insn (ADDIW
, ival
);
1109 else if (is_c_addi16sp_insn (ival
))
1112 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1113 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1115 else if (is_lui_insn (ival
))
1117 else if (is_c_sd_insn (ival
))
1119 else if (is_sw_insn (ival
))
1122 /* None of the other fields of INSN are valid in this case. */
1126 internal_error (__FILE__
, __LINE__
,
1127 _("unable to decode %d byte instructions in "
1128 "prologue at %s"), m_length
,
1129 core_addr_to_string (pc
));
1132 /* The prologue scanner. This is currently only used for skipping the
1133 prologue of a function when the DWARF information is not sufficient.
1134 However, it is written with filling of the frame cache in mind, which
1135 is why different groups of stack setup instructions are split apart
1136 during the core of the inner loop. In the future, the intention is to
1137 extend this function to fully support building up a frame cache that
1138 can unwind register values when there is no DWARF information. */
1141 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1142 CORE_ADDR start_pc
, CORE_ADDR limit_pc
)
1144 CORE_ADDR cur_pc
, next_pc
;
1145 long frame_offset
= 0;
1146 CORE_ADDR end_prologue_addr
= 0;
1148 if (limit_pc
> start_pc
+ 200)
1149 limit_pc
= start_pc
+ 200;
1151 for (next_pc
= cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
= next_pc
)
1153 struct riscv_insn insn
;
1155 /* Decode the current instruction, and decide where the next
1156 instruction lives based on the size of this instruction. */
1157 insn
.decode (gdbarch
, cur_pc
);
1158 gdb_assert (insn
.length () > 0);
1159 next_pc
= cur_pc
+ insn
.length ();
1161 /* Look for common stack adjustment insns. */
1162 if ((insn
.opcode () == riscv_insn::ADDI
1163 || insn
.opcode () == riscv_insn::ADDIW
)
1164 && insn
.rd () == RISCV_SP_REGNUM
1165 && insn
.rs1 () == RISCV_SP_REGNUM
)
1167 /* Handle: addi sp, sp, -i
1168 or: addiw sp, sp, -i */
1169 if (insn
.imm_signed () < 0)
1170 frame_offset
+= insn
.imm_signed ();
1174 else if ((insn
.opcode () == riscv_insn::SW
1175 || insn
.opcode () == riscv_insn::SD
)
1176 && (insn
.rs1 () == RISCV_SP_REGNUM
1177 || insn
.rs1 () == RISCV_FP_REGNUM
))
1179 /* Handle: sw reg, offset(sp)
1180 or: sd reg, offset(sp)
1181 or: sw reg, offset(s0)
1182 or: sd reg, offset(s0) */
1183 /* Instruction storing a register onto the stack. */
1185 else if (insn
.opcode () == riscv_insn::ADDI
1186 && insn
.rd () == RISCV_FP_REGNUM
1187 && insn
.rs1 () == RISCV_SP_REGNUM
)
1189 /* Handle: addi s0, sp, size */
1190 /* Instructions setting up the frame pointer. */
1192 else if ((insn
.opcode () == riscv_insn::ADD
1193 || insn
.opcode () == riscv_insn::ADDW
)
1194 && insn
.rd () == RISCV_FP_REGNUM
1195 && insn
.rs1 () == RISCV_SP_REGNUM
1196 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1198 /* Handle: add s0, sp, 0
1199 or: addw s0, sp, 0 */
1200 /* Instructions setting up the frame pointer. */
1202 else if ((insn
.rd () == RISCV_GP_REGNUM
1203 && (insn
.opcode () == riscv_insn::AUIPC
1204 || insn
.opcode () == riscv_insn::LUI
1205 || (insn
.opcode () == riscv_insn::ADDI
1206 && insn
.rs1 () == RISCV_GP_REGNUM
)
1207 || (insn
.opcode () == riscv_insn::ADD
1208 && (insn
.rs1 () == RISCV_GP_REGNUM
1209 || insn
.rs2 () == RISCV_GP_REGNUM
))))
1210 || (insn
.opcode () == riscv_insn::ADDI
1211 && insn
.rd () == RISCV_ZERO_REGNUM
1212 && insn
.rs1 () == RISCV_ZERO_REGNUM
1213 && insn
.imm_signed () == 0))
1215 /* Handle: auipc gp, n
1220 or: add x0, x0, 0 (NOP) */
1221 /* These instructions are part of the prologue, but we don't need
1222 to do anything special to handle them. */
1226 if (end_prologue_addr
== 0)
1227 end_prologue_addr
= cur_pc
;
1231 if (end_prologue_addr
== 0)
1232 end_prologue_addr
= cur_pc
;
1234 return end_prologue_addr
;
1237 /* Implement the riscv_skip_prologue gdbarch method. */
1240 riscv_skip_prologue (struct gdbarch
*gdbarch
,
1244 CORE_ADDR func_addr
;
1246 /* See if we can determine the end of the prologue via the symbol
1247 table. If so, then return either PC, or the PC after the
1248 prologue, whichever is greater. */
1249 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1251 CORE_ADDR post_prologue_pc
1252 = skip_prologue_using_sal (gdbarch
, func_addr
);
1254 if (post_prologue_pc
!= 0)
1255 return std::max (pc
, post_prologue_pc
);
1258 /* Can't determine prologue from the symbol table, need to examine
1261 /* Find an upper limit on the function prologue using the debug
1262 information. If the debug information could not be used to provide
1263 that bound, then use an arbitrary large number as the upper bound. */
1264 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1266 limit_pc
= pc
+ 100; /* MAGIC! */
1268 return riscv_scan_prologue (gdbarch
, pc
, limit_pc
);
1271 /* Implement the gdbarch push dummy code callback. */
1274 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1275 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1276 struct type
*value_type
, CORE_ADDR
*real_pc
,
1277 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1279 /* Allocate space for a breakpoint, and keep the stack correctly
1287 /* Compute the alignment of the type T. Used while setting up the
1288 arguments for a dummy call. */
1291 riscv_type_alignment (struct type
*t
)
1293 t
= check_typedef (t
);
1294 switch (TYPE_CODE (t
))
1297 error (_("Could not compute alignment of type"));
1299 case TYPE_CODE_RVALUE_REF
:
1301 case TYPE_CODE_ENUM
:
1305 case TYPE_CODE_CHAR
:
1306 case TYPE_CODE_BOOL
:
1307 return TYPE_LENGTH (t
);
1309 case TYPE_CODE_ARRAY
:
1310 case TYPE_CODE_COMPLEX
:
1311 return riscv_type_alignment (TYPE_TARGET_TYPE (t
));
1313 case TYPE_CODE_STRUCT
:
1314 case TYPE_CODE_UNION
:
1319 for (i
= 0; i
< TYPE_NFIELDS (t
); ++i
)
1321 if (TYPE_FIELD_LOC_KIND (t
, i
) == FIELD_LOC_KIND_BITPOS
)
1323 int a
= riscv_type_alignment (TYPE_FIELD_TYPE (t
, i
));
1333 /* Holds information about a single argument either being passed to an
1334 inferior function, or returned from an inferior function. This includes
1335 information about the size, type, etc of the argument, and also
1336 information about how the argument will be passed (or returned). */
1338 struct riscv_arg_info
1340 /* Contents of the argument. */
1341 const gdb_byte
*contents
;
1343 /* Length of argument. */
1346 /* Alignment required for an argument of this type. */
1349 /* The type for this argument. */
1352 /* Each argument can have either 1 or 2 locations assigned to it. Each
1353 location describes where part of the argument will be placed. The
1354 second location is valid based on the LOC_TYPE and C_LENGTH fields
1355 of the first location (which is always valid). */
1358 /* What type of location this is. */
1361 /* Argument passed in a register. */
1364 /* Argument passed as an on stack argument. */
1367 /* Argument passed by reference. The second location is always
1368 valid for a BY_REF argument, and describes where the address
1369 of the BY_REF argument should be placed. */
1373 /* Information that depends on the location type. */
1376 /* Which register number to use. */
1379 /* The offset into the stack region. */
1383 /* The length of contents covered by this location. If this is less
1384 than the total length of the argument, then the second location
1385 will be valid, and will describe where the rest of the argument
1389 /* The offset within CONTENTS for this part of the argument. Will
1390 always be 0 for the first part. For the second part of the
1391 argument, this might be the C_LENGTH value of the first part,
1392 however, if we are passing a structure in two registers, and there's
1393 is padding between the first and second field, then this offset
1394 might be greater than the length of the first argument part. When
1395 the second argument location is not holding part of the argument
1396 value, but is instead holding the address of a reference argument,
1397 then this offset will be set to 0. */
1402 /* Information about a set of registers being used for passing arguments as
1403 part of a function call. The register set must be numerically
1404 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1405 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1407 struct riscv_arg_reg
1409 riscv_arg_reg (int first
, int last
)
1410 : next_regnum (first
),
1416 /* The GDB register number to use in this set. */
1419 /* The last GDB register number to use in this set. */
1423 /* Arguments can be passed as on stack arguments, or by reference. The
1424 on stack arguments must be in a continuous region starting from $sp,
1425 while the by reference arguments can be anywhere, but we'll put them
1426 on the stack after (at higher address) the on stack arguments.
1428 This might not be the right approach to take. The ABI is clear that
1429 an argument passed by reference can be modified by the callee, which
1430 us placing the argument (temporarily) onto the stack will not achieve
1431 (changes will be lost). There's also the possibility that very large
1432 arguments could overflow the stack.
1434 This struct is used to track offset into these two areas for where
1435 arguments are to be placed. */
1436 struct riscv_memory_offsets
1438 riscv_memory_offsets ()
1445 /* Offset into on stack argument area. */
1448 /* Offset into the pass by reference area. */
1452 /* Holds information about where arguments to a call will be placed. This
1453 is updated as arguments are added onto the call, and can be used to
1454 figure out where the next argument should be placed. */
1456 struct riscv_call_info
1458 riscv_call_info (struct gdbarch
*gdbarch
)
1459 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1460 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1462 xlen
= riscv_isa_xlen (gdbarch
);
1463 flen
= riscv_isa_flen (gdbarch
);
1465 /* Disable use of floating point registers if needed. */
1466 if (!riscv_has_fp_abi (gdbarch
))
1467 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1470 /* Track the memory areas used for holding in-memory arguments to a
1472 struct riscv_memory_offsets memory
;
1474 /* Holds information about the next integer register to use for passing
1476 struct riscv_arg_reg int_regs
;
1478 /* Holds information about the next floating point register to use for
1479 passing an argument. */
1480 struct riscv_arg_reg float_regs
;
1482 /* The XLEN and FLEN are copied in to this structure for convenience, and
1483 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1488 /* Return the number of registers available for use as parameters in the
1489 register set REG. Returned value can be 0 or more. */
1492 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1494 if (reg
->next_regnum
> reg
->last_regnum
)
1497 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1500 /* If there is at least one register available in the register set REG then
1501 the next register from REG is assigned to LOC and the length field of
1502 LOC is updated to LENGTH. The register set REG is updated to indicate
1503 that the assigned register is no longer available and the function
1506 If there are no registers available in REG then the function returns
1507 false, and LOC and REG are unchanged. */
1510 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1511 struct riscv_arg_reg
*reg
,
1512 int length
, int offset
)
1514 if (reg
->next_regnum
<= reg
->last_regnum
)
1516 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1517 loc
->loc_data
.regno
= reg
->next_regnum
;
1519 loc
->c_length
= length
;
1520 loc
->c_offset
= offset
;
1527 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1528 record that an area of stack has been used to hold the parameter
1531 The length field of LOC is updated to LENGTH, the length of the
1532 parameter being stored, and ALIGN is the alignment required by the
1533 parameter, which will affect how memory is allocated out of MEMORY. */
1536 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1537 struct riscv_memory_offsets
*memory
,
1538 int length
, int align
)
1540 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1542 = align_up (memory
->arg_offset
, align
);
1543 loc
->loc_data
.offset
= memory
->arg_offset
;
1544 memory
->arg_offset
+= length
;
1545 loc
->c_length
= length
;
1547 /* Offset is always 0, either we're the first location part, in which
1548 case we're reading content from the start of the argument, or we're
1549 passing the address of a reference argument, so 0. */
1553 /* Update AINFO, which describes an argument that should be passed or
1554 returned using the integer ABI. The argloc fields within AINFO are
1555 updated to describe the location in which the argument will be passed to
1556 a function, or returned from a function.
1558 The CINFO structure contains the ongoing call information, the holds
1559 information such as which argument registers are remaining to be
1560 assigned to parameter, and how much memory has been used by parameters
1563 By examining the state of CINFO a suitable location can be selected,
1564 and assigned to AINFO. */
1567 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1568 struct riscv_call_info
*cinfo
)
1570 if (ainfo
->length
> (2 * cinfo
->xlen
))
1572 /* Argument is going to be passed by reference. */
1573 ainfo
->argloc
[0].loc_type
1574 = riscv_arg_info::location::by_ref
;
1575 cinfo
->memory
.ref_offset
1576 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1577 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1578 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1579 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1581 /* The second location for this argument is given over to holding the
1582 address of the by-reference data. Pass 0 for the offset as this
1583 is not part of the actual argument value. */
1584 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1587 riscv_assign_stack_location (&ainfo
->argloc
[1],
1588 &cinfo
->memory
, cinfo
->xlen
,
1593 int len
= (ainfo
->length
> cinfo
->xlen
) ? cinfo
->xlen
: ainfo
->length
;
1595 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1596 &cinfo
->int_regs
, len
, 0))
1597 riscv_assign_stack_location (&ainfo
->argloc
[0],
1598 &cinfo
->memory
, len
, ainfo
->align
);
1600 if (len
< ainfo
->length
)
1602 len
= ainfo
->length
- len
;
1603 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1604 &cinfo
->int_regs
, len
,
1606 riscv_assign_stack_location (&ainfo
->argloc
[1],
1607 &cinfo
->memory
, len
, cinfo
->xlen
);
1612 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1613 is being passed with the floating point ABI. */
1616 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1617 struct riscv_call_info
*cinfo
)
1619 if (ainfo
->length
> cinfo
->flen
)
1620 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1623 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1626 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1630 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1631 is a complex floating point argument, and is therefore handled
1632 differently to other argument types. */
1635 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1636 struct riscv_call_info
*cinfo
)
1638 if (ainfo
->length
<= (2 * cinfo
->flen
)
1639 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1642 int len
= ainfo
->length
/ 2;
1644 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1645 &cinfo
->float_regs
, len
, len
);
1646 gdb_assert (result
);
1648 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1649 &cinfo
->float_regs
, len
, len
);
1650 gdb_assert (result
);
1653 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1656 /* A structure used for holding information about a structure type within
1657 the inferior program. The RiscV ABI has special rules for handling some
1658 structures with a single field or with two fields. The counting of
1659 fields here is done after flattening out all nested structures. */
1661 class riscv_struct_info
1664 riscv_struct_info ()
1665 : m_number_of_fields (0),
1666 m_types
{ nullptr, nullptr }
1671 /* Analyse TYPE descending into nested structures, count the number of
1672 scalar fields and record the types of the first two fields found. */
1673 void analyse (struct type
*type
);
1675 /* The number of scalar fields found in the analysed type. This is
1676 currently only accurate if the value returned is 0, 1, or 2 as the
1677 analysis stops counting when the number of fields is 3. This is
1678 because the RiscV ABI only has special cases for 1 or 2 fields,
1679 anything else we just don't care about. */
1680 int number_of_fields () const
1681 { return m_number_of_fields
; }
1683 /* Return the type for scalar field INDEX within the analysed type. Will
1684 return nullptr if there is no field at that index. Only INDEX values
1685 0 and 1 can be requested as the RiscV ABI only has special cases for
1686 structures with 1 or 2 fields. */
1687 struct type
*field_type (int index
) const
1689 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
1690 return m_types
[index
];
1694 /* The number of scalar fields found within the structure after recursing
1695 into nested structures. */
1696 int m_number_of_fields
;
1698 /* The types of the first two scalar fields found within the structure
1699 after recursing into nested structures. */
1700 struct type
*m_types
[2];
1703 /* Analyse TYPE descending into nested structures, count the number of
1704 scalar fields and record the types of the first two fields found. */
1707 riscv_struct_info::analyse (struct type
*type
)
1709 unsigned int count
= TYPE_NFIELDS (type
);
1712 for (i
= 0; i
< count
; ++i
)
1714 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
1717 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
1718 field_type
= check_typedef (field_type
);
1720 switch (TYPE_CODE (field_type
))
1722 case TYPE_CODE_STRUCT
:
1723 analyse (field_type
);
1727 /* RiscV only flattens out structures. Anything else does not
1728 need to be flattened, we just record the type, and when we
1729 look at the analysis results we'll realise this is not a
1730 structure we can special case, and pass the structure in
1732 if (m_number_of_fields
< 2)
1733 m_types
[m_number_of_fields
] = field_type
;
1734 m_number_of_fields
++;
1738 /* RiscV only has special handling for structures with 1 or 2 scalar
1739 fields, any more than that and the structure is just passed in
1740 memory. We can safely drop out early when we find 3 or more
1743 if (m_number_of_fields
> 2)
1748 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1749 is a structure. Small structures on RiscV have some special case
1750 handling in order that the structure might be passed in register.
1751 Larger structures are passed in memory. After assigning location
1752 information to AINFO, CINFO will have been updated. */
1755 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
1756 struct riscv_call_info
*cinfo
)
1758 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
1760 struct riscv_struct_info sinfo
;
1762 sinfo
.analyse (ainfo
->type
);
1763 if (sinfo
.number_of_fields () == 1
1764 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
1766 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1767 == TYPE_LENGTH (sinfo
.field_type (0)));
1768 return riscv_call_arg_complex_float (ainfo
, cinfo
);
1771 if (sinfo
.number_of_fields () == 1
1772 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
1774 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1775 == TYPE_LENGTH (sinfo
.field_type (0)));
1776 return riscv_call_arg_scalar_float (ainfo
, cinfo
);
1779 if (sinfo
.number_of_fields () == 2
1780 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1781 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1782 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1783 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
1784 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1786 int len0
, len1
, offset
;
1788 gdb_assert (TYPE_LENGTH (ainfo
->type
) <= (2 * cinfo
->flen
));
1790 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1791 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1792 &cinfo
->float_regs
, len0
, 0))
1793 error (_("failed during argument setup"));
1795 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1796 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1797 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
1798 - TYPE_LENGTH (sinfo
.field_type (0))));
1800 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1803 error (_("failed during argument setup"));
1807 if (sinfo
.number_of_fields () == 2
1808 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1809 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1810 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1811 && is_integral_type (sinfo
.field_type (1))
1812 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
1814 int len0
, len1
, offset
;
1816 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1817 <= (cinfo
->flen
+ cinfo
->xlen
));
1819 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1820 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1821 &cinfo
->float_regs
, len0
, 0))
1822 error (_("failed during argument setup"));
1824 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1825 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1826 gdb_assert (len1
<= cinfo
->xlen
);
1827 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1828 &cinfo
->int_regs
, len1
, offset
))
1829 error (_("failed during argument setup"));
1833 if (sinfo
.number_of_fields () == 2
1834 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1835 && (is_integral_type (sinfo
.field_type (0))
1836 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
1837 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1838 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
1840 int len0
, len1
, offset
;
1842 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1843 <= (cinfo
->flen
+ cinfo
->xlen
));
1845 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1846 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1847 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1849 gdb_assert (len0
<= cinfo
->xlen
);
1850 gdb_assert (len1
<= cinfo
->flen
);
1852 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1853 &cinfo
->int_regs
, len0
, 0))
1854 error (_("failed during argument setup"));
1856 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1859 error (_("failed during argument setup"));
1865 /* Non of the structure flattening cases apply, so we just pass using
1867 ainfo
->length
= align_up (ainfo
->length
, cinfo
->xlen
);
1868 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1871 /* Assign a location to call (or return) argument AINFO, the location is
1872 selected from CINFO which holds information about what call argument
1873 locations are available for use next. The TYPE is the type of the
1874 argument being passed, this information is recorded into AINFO (along
1875 with some additional information derived from the type).
1877 After assigning a location to AINFO, CINFO will have been updated. */
1880 riscv_arg_location (struct gdbarch
*gdbarch
,
1881 struct riscv_arg_info
*ainfo
,
1882 struct riscv_call_info
*cinfo
,
1886 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
1887 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1888 ainfo
->contents
= nullptr;
1890 switch (TYPE_CODE (ainfo
->type
))
1893 case TYPE_CODE_BOOL
:
1894 case TYPE_CODE_CHAR
:
1895 case TYPE_CODE_RANGE
:
1896 case TYPE_CODE_ENUM
:
1898 if (ainfo
->length
<= cinfo
->xlen
)
1900 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
1901 ainfo
->length
= cinfo
->xlen
;
1903 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
1905 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
1906 ainfo
->length
= 2 * cinfo
->xlen
;
1909 /* Recalculate the alignment requirement. */
1910 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1911 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1915 riscv_call_arg_scalar_float (ainfo
, cinfo
);
1918 case TYPE_CODE_COMPLEX
:
1919 riscv_call_arg_complex_float (ainfo
, cinfo
);
1922 case TYPE_CODE_STRUCT
:
1923 riscv_call_arg_struct (ainfo
, cinfo
);
1927 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1932 /* Used for printing debug information about the call argument location in
1933 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
1934 addresses for the location of pass-by-reference and
1935 arguments-on-the-stack memory areas. */
1938 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
1939 struct riscv_arg_info
*info
,
1940 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
1942 const char* type_name
= TYPE_NAME (info
->type
);
1943 if (type_name
== nullptr)
1946 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
1947 type_name
, info
->length
, info
->align
);
1948 switch (info
->argloc
[0].loc_type
)
1950 case riscv_arg_info::location::in_reg
:
1952 (stream
, ", register %s",
1953 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
1954 if (info
->argloc
[0].c_length
< info
->length
)
1956 switch (info
->argloc
[1].loc_type
)
1958 case riscv_arg_info::location::in_reg
:
1960 (stream
, ", register %s",
1961 gdbarch_register_name (gdbarch
,
1962 info
->argloc
[1].loc_data
.regno
));
1965 case riscv_arg_info::location::on_stack
:
1966 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1967 info
->argloc
[1].loc_data
.offset
);
1970 case riscv_arg_info::location::by_ref
:
1972 /* The second location should never be a reference, any
1973 argument being passed by reference just places its address
1974 in the first location and is done. */
1975 error (_("invalid argument location"));
1979 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
1980 fprintf_unfiltered (stream
, " (offset 0x%x)",
1981 info
->argloc
[1].c_offset
);
1985 case riscv_arg_info::location::on_stack
:
1986 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1987 info
->argloc
[0].loc_data
.offset
);
1990 case riscv_arg_info::location::by_ref
:
1992 (stream
, ", by reference, data at offset 0x%x (%s)",
1993 info
->argloc
[0].loc_data
.offset
,
1994 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
1995 if (info
->argloc
[1].loc_type
1996 == riscv_arg_info::location::in_reg
)
1998 (stream
, ", address in register %s",
1999 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2002 gdb_assert (info
->argloc
[1].loc_type
2003 == riscv_arg_info::location::on_stack
);
2005 (stream
, ", address on stack at offset 0x%x (%s)",
2006 info
->argloc
[1].loc_data
.offset
,
2007 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2012 error ("unknown argument location type");
2016 /* Implement the push dummy call gdbarch callback. */
2019 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2020 struct value
*function
,
2021 struct regcache
*regcache
,
2024 struct value
**args
,
2027 CORE_ADDR struct_addr
)
2030 CORE_ADDR sp_args
, sp_refs
;
2031 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2034 struct riscv_arg_info
*arg_info
=
2035 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2036 struct riscv_arg_info
*info
;
2038 struct riscv_call_info
call_info (gdbarch
);
2042 /* We'll use register $a0 if we're returning a struct. */
2044 ++call_info
.int_regs
.next_regnum
;
2046 for (i
= 0, info
= &arg_info
[0];
2050 struct value
*arg_value
;
2051 struct type
*arg_type
;
2053 arg_value
= args
[i
];
2054 arg_type
= check_typedef (value_type (arg_value
));
2056 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
);
2058 if (info
->type
!= arg_type
)
2059 arg_value
= value_cast (info
->type
, arg_value
);
2060 info
->contents
= value_contents (arg_value
);
2063 /* Adjust the stack pointer and align it. */
2064 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2065 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2067 if (riscv_debug_infcall
> 0)
2069 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2070 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2071 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2072 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2073 call_info
.xlen
, call_info
.flen
);
2075 fprintf_unfiltered (gdb_stdlog
,
2076 "[*] struct return pointer in register $A0\n");
2077 for (i
= 0; i
< nargs
; ++i
)
2079 struct riscv_arg_info
*info
= &arg_info
[i
];
2081 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2082 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2083 fprintf_unfiltered (gdb_stdlog
, "\n");
2085 if (call_info
.memory
.arg_offset
> 0
2086 || call_info
.memory
.ref_offset
> 0)
2088 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2089 core_addr_to_string (osp
));
2090 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2091 call_info
.memory
.arg_offset
);
2092 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2093 call_info
.memory
.ref_offset
);
2094 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2095 core_addr_to_string_nz (osp
- sp
));
2099 /* Now load the argument into registers, or onto the stack. */
2103 gdb_byte buf
[sizeof (LONGEST
)];
2105 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2106 regcache_cooked_write (regcache
, RISCV_A0_REGNUM
, buf
);
2109 for (i
= 0; i
< nargs
; ++i
)
2112 int second_arg_length
= 0;
2113 const gdb_byte
*second_arg_data
;
2114 struct riscv_arg_info
*info
= &arg_info
[i
];
2116 gdb_assert (info
->length
> 0);
2118 switch (info
->argloc
[0].loc_type
)
2120 case riscv_arg_info::location::in_reg
:
2122 gdb_byte tmp
[sizeof (ULONGEST
)];
2124 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2125 memset (tmp
, 0, sizeof (tmp
));
2126 memcpy (tmp
, info
->contents
, info
->argloc
[0].c_length
);
2127 regcache_cooked_write (regcache
,
2128 info
->argloc
[0].loc_data
.regno
,
2131 ((info
->argloc
[0].c_length
< info
->length
)
2132 ? info
->argloc
[1].c_length
: 0);
2133 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2137 case riscv_arg_info::location::on_stack
:
2138 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2139 write_memory (dst
, info
->contents
, info
->length
);
2140 second_arg_length
= 0;
2143 case riscv_arg_info::location::by_ref
:
2144 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2145 write_memory (dst
, info
->contents
, info
->length
);
2147 second_arg_length
= call_info
.xlen
;
2148 second_arg_data
= (gdb_byte
*) &dst
;
2152 error ("unknown argument location type");
2155 if (second_arg_length
> 0)
2157 switch (info
->argloc
[1].loc_type
)
2159 case riscv_arg_info::location::in_reg
:
2161 gdb_byte tmp
[sizeof (ULONGEST
)];
2163 gdb_assert (second_arg_length
<= call_info
.xlen
);
2164 memset (tmp
, 0, sizeof (tmp
));
2165 memcpy (tmp
, second_arg_data
, second_arg_length
);
2166 regcache_cooked_write (regcache
,
2167 info
->argloc
[1].loc_data
.regno
,
2172 case riscv_arg_info::location::on_stack
:
2176 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2177 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2181 case riscv_arg_info::location::by_ref
:
2183 /* The second location should never be a reference, any
2184 argument being passed by reference just places its address
2185 in the first location and is done. */
2186 error (_("invalid argument location"));
2192 /* Set the dummy return value to bp_addr.
2193 A dummy breakpoint will be setup to execute the call. */
2195 if (riscv_debug_infcall
> 0)
2196 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2197 core_addr_to_string (bp_addr
));
2198 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2200 /* Finally, update the stack pointer. */
2202 if (riscv_debug_infcall
> 0)
2203 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2204 core_addr_to_string (sp
));
2205 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2210 /* Implement the return_value gdbarch method. */
2212 static enum return_value_convention
2213 riscv_return_value (struct gdbarch
*gdbarch
,
2214 struct value
*function
,
2216 struct regcache
*regcache
,
2218 const gdb_byte
*writebuf
)
2220 enum type_code rv_type
= TYPE_CODE (type
);
2221 unsigned int rv_size
= TYPE_LENGTH (type
);
2222 int fp
, regnum
, flen
;
2224 struct riscv_call_info
call_info (gdbarch
);
2225 struct riscv_arg_info info
;
2226 struct type
*arg_type
;
2228 arg_type
= check_typedef (type
);
2229 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
);
2231 if (riscv_debug_infcall
> 0)
2233 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2234 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2235 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2236 fprintf_unfiltered (gdb_stdlog
, "\n");
2239 if (readbuf
!= nullptr || writebuf
!= nullptr)
2243 switch (info
.argloc
[0].loc_type
)
2245 /* Return value in register(s). */
2246 case riscv_arg_info::location::in_reg
:
2248 regnum
= info
.argloc
[0].loc_data
.regno
;
2251 regcache_cooked_read (regcache
, regnum
, readbuf
);
2254 regcache_cooked_write (regcache
, regnum
, writebuf
);
2256 /* A return value in register can have a second part in a
2258 if (info
.argloc
[0].c_length
< info
.length
)
2260 switch (info
.argloc
[1].loc_type
)
2262 case riscv_arg_info::location::in_reg
:
2263 regnum
= info
.argloc
[1].loc_data
.regno
;
2267 readbuf
+= info
.argloc
[1].c_offset
;
2268 regcache_cooked_read (regcache
, regnum
, readbuf
);
2273 writebuf
+= info
.argloc
[1].c_offset
;
2274 regcache_cooked_write (regcache
, regnum
, writebuf
);
2278 case riscv_arg_info::location::by_ref
:
2279 case riscv_arg_info::location::on_stack
:
2281 error (_("invalid argument location"));
2288 /* Return value by reference will have its address in A0. */
2289 case riscv_arg_info::location::by_ref
:
2293 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2295 if (readbuf
!= nullptr)
2296 read_memory (addr
, readbuf
, info
.length
);
2297 if (writebuf
!= nullptr)
2298 write_memory (addr
, writebuf
, info
.length
);
2302 case riscv_arg_info::location::on_stack
:
2304 error (_("invalid argument location"));
2309 switch (info
.argloc
[0].loc_type
)
2311 case riscv_arg_info::location::in_reg
:
2312 return RETURN_VALUE_REGISTER_CONVENTION
;
2313 case riscv_arg_info::location::by_ref
:
2314 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2315 case riscv_arg_info::location::on_stack
:
2317 error (_("invalid argument location"));
2321 /* Implement the frame_align gdbarch method. */
2324 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2326 return align_down (addr
, 16);
2329 /* Implement the unwind_pc gdbarch method. */
2332 riscv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2334 return frame_unwind_register_unsigned (next_frame
, RISCV_PC_REGNUM
);
2337 /* Implement the unwind_sp gdbarch method. */
2340 riscv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2342 return frame_unwind_register_unsigned (next_frame
, RISCV_SP_REGNUM
);
2345 /* Implement the dummy_id gdbarch method. */
2347 static struct frame_id
2348 riscv_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2350 return frame_id_build (get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
),
2351 get_frame_pc (this_frame
));
2354 /* Generate, or return the cached frame cache for the RiscV frame
2357 static struct trad_frame_cache
*
2358 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2361 CORE_ADDR start_addr
;
2362 CORE_ADDR stack_addr
;
2363 struct trad_frame_cache
*this_trad_cache
;
2364 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2366 if ((*this_cache
) != NULL
)
2367 return (struct trad_frame_cache
*) *this_cache
;
2368 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2369 (*this_cache
) = this_trad_cache
;
2371 trad_frame_set_reg_realreg (this_trad_cache
, gdbarch_pc_regnum (gdbarch
),
2374 pc
= get_frame_pc (this_frame
);
2375 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2376 stack_addr
= get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
);
2377 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2379 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2381 return this_trad_cache
;
2384 /* Implement the this_id callback for RiscV frame unwinder. */
2387 riscv_frame_this_id (struct frame_info
*this_frame
,
2388 void **prologue_cache
,
2389 struct frame_id
*this_id
)
2391 struct trad_frame_cache
*info
;
2393 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2394 trad_frame_get_id (info
, this_id
);
2397 /* Implement the prev_register callback for RiscV frame unwinder. */
2399 static struct value
*
2400 riscv_frame_prev_register (struct frame_info
*this_frame
,
2401 void **prologue_cache
,
2404 struct trad_frame_cache
*info
;
2406 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2407 return trad_frame_get_register (info
, this_frame
, regnum
);
2410 /* Structure defining the RiscV normal frame unwind functions. Since we
2411 are the fallback unwinder (DWARF unwinder is used first), we use the
2412 default frame sniffer, which always accepts the frame. */
2414 static const struct frame_unwind riscv_frame_unwind
=
2416 /*.type =*/ NORMAL_FRAME
,
2417 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2418 /*.this_id =*/ riscv_frame_this_id
,
2419 /*.prev_register =*/ riscv_frame_prev_register
,
2420 /*.unwind_data =*/ NULL
,
2421 /*.sniffer =*/ default_frame_sniffer
,
2422 /*.dealloc_cache =*/ NULL
,
2423 /*.prev_arch =*/ NULL
,
2426 /* Initialize the current architecture based on INFO. If possible,
2427 re-use an architecture from ARCHES, which is a list of
2428 architectures already created during this debugging session.
2430 Called e.g. at program startup, when reading a core file, and when
2431 reading a binary file. */
2433 static struct gdbarch
*
2434 riscv_gdbarch_init (struct gdbarch_info info
,
2435 struct gdbarch_list
*arches
)
2437 struct gdbarch
*gdbarch
;
2438 struct gdbarch_tdep
*tdep
;
2439 struct gdbarch_tdep tmp_tdep
;
2440 bool has_compressed_isa
= false;
2443 /* Ideally, we'd like to get as much information from the target for
2444 things like register size, and whether the target has floating point
2445 hardware. However, there are some things that the target can't tell
2446 us, like, what ABI is being used.
2448 So, for now, we take as much information as possible from the ELF,
2449 including things like register size, and FP hardware support, along
2450 with information about the ABI.
2452 Information about this target is built up in TMP_TDEP, and then we
2453 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2454 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2455 memset (&tmp_tdep
, 0, sizeof (tmp_tdep
));
2457 if (info
.abfd
!= NULL
2458 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2460 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2461 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2463 if (eclass
== ELFCLASS32
)
2464 tmp_tdep
.abi
.fields
.base_len
= 1;
2465 else if (eclass
== ELFCLASS64
)
2466 tmp_tdep
.abi
.fields
.base_len
= 2;
2468 internal_error (__FILE__
, __LINE__
,
2469 _("unknown ELF header class %d"), eclass
);
2471 if (e_flags
& EF_RISCV_RVC
)
2473 has_compressed_isa
= true;
2474 tmp_tdep
.core_features
|= (1 << ('C' - 'A'));
2477 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2479 tmp_tdep
.abi
.fields
.float_abi
= 2;
2480 tmp_tdep
.core_features
|= (1 << ('D' - 'A'));
2481 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2483 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2485 tmp_tdep
.abi
.fields
.float_abi
= 1;
2486 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2491 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2493 if (binfo
->bits_per_word
== 32)
2494 tmp_tdep
.abi
.fields
.base_len
= 1;
2495 else if (binfo
->bits_per_word
== 64)
2496 tmp_tdep
.abi
.fields
.base_len
= 2;
2498 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2499 binfo
->bits_per_word
);
2502 /* Find a candidate among the list of pre-declared architectures. */
2503 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2505 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2506 if (gdbarch_tdep (arches
->gdbarch
)->abi
.value
== tmp_tdep
.abi
.value
)
2507 return arches
->gdbarch
;
2509 /* None found, so create a new architecture from the information provided. */
2510 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof *tdep
);
2511 gdbarch
= gdbarch_alloc (&info
, tdep
);
2512 memcpy (tdep
, &tmp_tdep
, sizeof (tmp_tdep
));
2514 /* Target data types. */
2515 set_gdbarch_short_bit (gdbarch
, 16);
2516 set_gdbarch_int_bit (gdbarch
, 32);
2517 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2518 set_gdbarch_long_long_bit (gdbarch
, 64);
2519 set_gdbarch_float_bit (gdbarch
, 32);
2520 set_gdbarch_double_bit (gdbarch
, 64);
2521 set_gdbarch_long_double_bit (gdbarch
, 128);
2522 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
2523 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2524 set_gdbarch_char_signed (gdbarch
, 0);
2526 /* Information about the target architecture. */
2527 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
2528 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
2529 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
2531 /* Register architecture. */
2532 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
2533 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
2534 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
2535 set_gdbarch_ps_regnum (gdbarch
, RISCV_FP_REGNUM
);
2536 set_gdbarch_deprecated_fp_regnum (gdbarch
, RISCV_FP_REGNUM
);
2538 /* Functions to supply register information. */
2539 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
2540 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
2541 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
2542 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
2544 /* Functions to analyze frames. */
2545 set_gdbarch_decr_pc_after_break (gdbarch
, (has_compressed_isa
? 2 : 4));
2546 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
2547 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2548 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
2550 /* Functions to access frame data. */
2551 set_gdbarch_unwind_pc (gdbarch
, riscv_unwind_pc
);
2552 set_gdbarch_unwind_sp (gdbarch
, riscv_unwind_sp
);
2554 /* Functions handling dummy frames. */
2555 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2556 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
2557 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
2558 set_gdbarch_dummy_id (gdbarch
, riscv_dummy_id
);
2560 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2562 dwarf2_append_unwinders (gdbarch
);
2563 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
2565 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
2566 user_reg_add (gdbarch
, riscv_register_aliases
[i
].name
,
2567 value_of_riscv_user_reg
, &riscv_register_aliases
[i
].regnum
);
2573 /* Allocate new riscv_inferior_data object. */
2575 static struct riscv_inferior_data
*
2576 riscv_new_inferior_data (void)
2578 struct riscv_inferior_data
*inf_data
2579 = new (struct riscv_inferior_data
);
2580 inf_data
->misa_read
= false;
2584 /* Free inferior data. */
2587 riscv_inferior_data_cleanup (struct inferior
*inf
, void *data
)
2589 struct riscv_inferior_data
*inf_data
=
2590 static_cast <struct riscv_inferior_data
*> (data
);
2594 /* Return riscv_inferior_data for the given INFERIOR. If not yet created,
2597 struct riscv_inferior_data
*
2598 riscv_inferior_data (struct inferior
*const inf
)
2600 struct riscv_inferior_data
*inf_data
;
2602 gdb_assert (inf
!= NULL
);
2605 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2606 if (inf_data
== NULL
)
2608 inf_data
= riscv_new_inferior_data ();
2609 set_inferior_data (inf
, riscv_inferior_data_reg
, inf_data
);
2615 /* Free the inferior data when an inferior exits. */
2618 riscv_invalidate_inferior_data (struct inferior
*inf
)
2620 struct riscv_inferior_data
*inf_data
;
2622 gdb_assert (inf
!= NULL
);
2624 /* Don't call RISCV_INFERIOR_DATA as we don't want to create the data if
2625 we've not already created it by this point. */
2627 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2628 if (inf_data
!= NULL
)
2631 set_inferior_data (inf
, riscv_inferior_data_reg
, NULL
);
2636 _initialize_riscv_tdep (void)
2638 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
2640 /* Register per-inferior data. */
2641 riscv_inferior_data_reg
2642 = register_inferior_data_with_cleanup (NULL
, riscv_inferior_data_cleanup
);
2644 /* Observers used to invalidate the inferior data when needed. */
2645 observer_attach_inferior_exit (riscv_invalidate_inferior_data
);
2646 observer_attach_inferior_appeared (riscv_invalidate_inferior_data
);
2648 /* Add root prefix command for all "set debug riscv" and "show debug
2650 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
2651 _("RISC-V specific debug commands."),
2652 &setdebugriscvcmdlist
, "set debug riscv ", 0,
2655 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
2656 _("RISC-V specific debug commands."),
2657 &showdebugriscvcmdlist
, "show debug riscv ", 0,
2660 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
2661 &riscv_debug_infcall
, _("\
2662 Set riscv inferior call debugging."), _("\
2663 Show riscv inferior call debugging."), _("\
2664 When non-zero, print debugging information for the riscv specific parts\n\
2665 of the inferior call mechanism."),
2667 show_riscv_debug_variable
,
2668 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
2670 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2671 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
2672 _("RISC-V specific commands."),
2673 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
2675 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
2676 _("RISC-V specific commands."),
2677 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
2680 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
2681 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
2682 &use_compressed_breakpoints
,
2684 Set debugger's use of compressed breakpoints."), _(" \
2685 Show debugger's use of compressed breakpoints."), _("\
2686 Debugging compressed code requires compressed breakpoints to be used. If\n \
2687 left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2688 is supported. If that doesn't give the correct behavior, then this option\n\
2691 show_use_compressed_breakpoints
,