1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
58 /* The stack must be 16-byte aligned. */
59 #define SP_ALIGNMENT 16
61 /* Forward declarations. */
62 static bool riscv_has_feature (struct gdbarch
*gdbarch
, char feature
);
63 struct riscv_inferior_data
;
64 struct riscv_inferior_data
* riscv_inferior_data (struct inferior
*const inf
);
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Per inferior information for RiscV. */
78 struct riscv_inferior_data
80 /* True when MISA_VALUE is valid, otherwise false. */
83 /* If MISA_READ is true then MISA_VALUE holds the value of the MISA
84 register read from the target. */
88 /* Key created when the RiscV per-inferior data is registered. */
90 static const struct inferior_data
*riscv_inferior_data_reg
;
92 /* Architectural name for core registers. */
94 static const char * const riscv_gdb_reg_names
[RISCV_LAST_FP_REGNUM
+ 1] =
96 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
97 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
98 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
99 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
101 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
102 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
103 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
104 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
107 /* Maps "pretty" register names onto their GDB register number. */
109 struct register_alias
111 /* The register alias. Usually more descriptive than the
112 architectural name of the register. */
115 /* The GDB register number. */
119 /* Table of register aliases. */
121 static const struct register_alias riscv_register_aliases
[] =
189 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
190 #include "opcode/riscv-opc.h"
194 /* Controls whether we place compressed breakpoints or not. When in auto
195 mode GDB tries to determine if the target supports compressed
196 breakpoints, and uses them if it does. */
198 static enum auto_boolean use_compressed_breakpoints
;
200 /* The show callback for 'show riscv use-compressed-breakpoints'. */
203 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
204 struct cmd_list_element
*c
,
207 const char *additional_info
;
208 struct gdbarch
*gdbarch
= target_gdbarch ();
210 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
211 if (riscv_has_feature (gdbarch
, 'C'))
212 additional_info
= _(" (currently on)");
214 additional_info
= _(" (currently off)");
216 additional_info
= "";
218 fprintf_filtered (file
,
219 _("Debugger's use of compressed breakpoints is set "
220 "to %s%s.\n"), value
, additional_info
);
223 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
225 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
226 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
228 /* The show callback for the 'show riscv' prefix command. */
231 show_riscv_command (const char *args
, int from_tty
)
233 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
236 /* The set callback for the 'set riscv' prefix command. */
239 set_riscv_command (const char *args
, int from_tty
)
242 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
243 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
246 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
248 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
249 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
251 /* The show callback for the 'show debug riscv' prefix command. */
254 show_debug_riscv_command (const char *args
, int from_tty
)
256 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
259 /* The set callback for the 'set debug riscv' prefix command. */
262 set_debug_riscv_command (const char *args
, int from_tty
)
265 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
266 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
269 /* The show callback for all 'show debug riscv VARNAME' variables. */
272 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
273 struct cmd_list_element
*c
,
276 fprintf_filtered (file
,
277 _("RiscV debug variable `%s' is set to: %s\n"),
281 /* When this is set to non-zero debugging information about inferior calls
284 static unsigned int riscv_debug_infcall
= 0;
286 /* Read the MISA register from the target. The register will only be read
287 once, and the value read will be cached. If the register can't be read
288 from the target then a default value (0) will be returned. If the
289 pointer READ_P is not null, then the bool pointed to is updated to
290 indicate if the value returned was read from the target (true) or is the
294 riscv_read_misa_reg (bool *read_p
)
296 struct riscv_inferior_data
*inf_data
297 = riscv_inferior_data (current_inferior ());
299 if (!inf_data
->misa_read
&& target_has_registers
)
302 struct frame_info
*frame
= get_current_frame ();
306 value
= get_frame_register_unsigned (frame
, RISCV_CSR_MISA_REGNUM
);
308 CATCH (ex
, RETURN_MASK_ERROR
)
310 /* Old cores might have MISA located at a different offset. */
311 value
= get_frame_register_unsigned (frame
,
312 RISCV_CSR_LEGACY_MISA_REGNUM
);
316 inf_data
->misa_read
= true;
317 inf_data
->misa_value
= value
;
320 if (read_p
!= nullptr)
321 *read_p
= inf_data
->misa_read
;
323 return inf_data
->misa_value
;
326 /* Return true if FEATURE is available for the architecture GDBARCH. The
327 FEATURE should be one of the single character feature codes described in
328 the RiscV ISA manual, these are between 'A' and 'Z'. */
331 riscv_has_feature (struct gdbarch
*gdbarch
, char feature
)
333 bool have_read_misa
= false;
336 gdb_assert (feature
>= 'A' && feature
<= 'Z');
338 /* It would be nice to always check with the real target where possible,
339 however, for compressed instructions this is a bad idea.
341 The call to `set_gdbarch_decr_pc_after_break' is made just once per
342 GDBARCH and we decide at that point if we should decrement by 2 or 4
343 bytes based on whether the BFD has compressed instruction support or
346 If the BFD was not compiled with compressed instruction support, but we
347 are running on a target with compressed instructions then we might
348 place a 4-byte breakpoint, then decrement the $pc by 2 bytes leading to
351 It's safer if we just make decisions about compressed instruction
352 support based on the BFD. */
354 misa
= riscv_read_misa_reg (&have_read_misa
);
355 if (!have_read_misa
|| misa
== 0)
356 misa
= gdbarch_tdep (gdbarch
)->core_features
;
358 return (misa
& (1 << (feature
- 'A'))) != 0;
361 /* Return the width in bytes of the general purpose registers for GDBARCH.
362 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
366 riscv_isa_xlen (struct gdbarch
*gdbarch
)
368 switch (gdbarch_tdep (gdbarch
)->abi
.fields
.base_len
)
371 warning (_("unknown xlen size, assuming 4 bytes"));
381 /* Return the width in bytes of the floating point registers for GDBARCH.
382 If this architecture has no floating point registers, then return 0.
383 Possible values are 4, 8, or 16 for depending on which of single, double
384 or quad floating point support is available. */
387 riscv_isa_flen (struct gdbarch
*gdbarch
)
389 if (riscv_has_feature (gdbarch
, 'Q'))
391 else if (riscv_has_feature (gdbarch
, 'D'))
393 else if (riscv_has_feature (gdbarch
, 'F'))
399 /* Return true if the target for GDBARCH has floating point hardware. */
402 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
404 return (riscv_isa_flen (gdbarch
) > 0);
407 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
410 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
412 return (gdbarch_tdep (gdbarch
)->abi
.fields
.float_abi
!= 0);
415 /* Implement the breakpoint_kind_from_pc gdbarch method. */
418 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
420 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
422 if (riscv_has_feature (gdbarch
, 'C'))
427 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
433 /* Implement the sw_breakpoint_from_kind gdbarch method. */
435 static const gdb_byte
*
436 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
438 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
439 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
449 gdb_assert_not_reached (_("unhandled breakpoint kind"));
453 /* Callback function for user_reg_add. */
455 static struct value
*
456 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
458 const int *reg_p
= (const int *) baton
;
459 return value_of_register (*reg_p
, frame
);
462 /* Implement the register_name gdbarch method. */
465 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
467 /* Prefer to use the alias. */
468 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_REGNUM
)
472 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
473 if (regnum
== riscv_register_aliases
[i
].regnum
)
474 return riscv_register_aliases
[i
].name
;
477 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
478 return riscv_gdb_reg_names
[regnum
];
480 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
484 xsnprintf (buf
, sizeof (buf
), "csr%d",
485 regnum
- RISCV_FIRST_CSR_REGNUM
);
489 if (regnum
== RISCV_PRIV_REGNUM
)
495 /* Implement the register_type gdbarch method. */
498 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
502 if (regnum
< RISCV_FIRST_FP_REGNUM
)
504 if (regnum
== gdbarch_pc_regnum (gdbarch
)
505 || regnum
== RISCV_RA_REGNUM
)
506 return builtin_type (gdbarch
)->builtin_func_ptr
;
508 if (regnum
== RISCV_FP_REGNUM
509 || regnum
== RISCV_SP_REGNUM
510 || regnum
== RISCV_GP_REGNUM
511 || regnum
== RISCV_TP_REGNUM
)
512 return builtin_type (gdbarch
)->builtin_data_ptr
;
514 /* Remaining GPRs vary in size based on the current ISA. */
515 regsize
= riscv_isa_xlen (gdbarch
);
519 return builtin_type (gdbarch
)->builtin_uint32
;
521 return builtin_type (gdbarch
)->builtin_uint64
;
523 return builtin_type (gdbarch
)->builtin_uint128
;
525 internal_error (__FILE__
, __LINE__
,
526 _("unknown isa regsize %i"), regsize
);
529 else if (regnum
<= RISCV_LAST_FP_REGNUM
)
531 regsize
= riscv_isa_xlen (gdbarch
);
535 return builtin_type (gdbarch
)->builtin_float
;
537 return builtin_type (gdbarch
)->builtin_double
;
539 return builtin_type (gdbarch
)->builtin_long_double
;
541 internal_error (__FILE__
, __LINE__
,
542 _("unknown isa regsize %i"), regsize
);
545 else if (regnum
== RISCV_PRIV_REGNUM
)
546 return builtin_type (gdbarch
)->builtin_int8
;
549 if (regnum
== RISCV_CSR_FFLAGS_REGNUM
550 || regnum
== RISCV_CSR_FRM_REGNUM
551 || regnum
== RISCV_CSR_FCSR_REGNUM
)
552 return builtin_type (gdbarch
)->builtin_int32
;
554 regsize
= riscv_isa_xlen (gdbarch
);
558 return builtin_type (gdbarch
)->builtin_int32
;
560 return builtin_type (gdbarch
)->builtin_int64
;
562 return builtin_type (gdbarch
)->builtin_int128
;
564 internal_error (__FILE__
, __LINE__
,
565 _("unknown isa regsize %i"), regsize
);
570 /* Helper for riscv_print_registers_info, prints info for a single register
574 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
575 struct ui_file
*file
,
576 struct frame_info
*frame
,
579 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
580 struct value
*val
= value_of_register (regnum
, frame
);
581 struct type
*regtype
= value_type (val
);
582 int print_raw_format
;
583 enum tab_stops
{ value_column_1
= 15 };
585 fputs_filtered (name
, file
);
586 print_spaces_filtered (value_column_1
- strlen (name
), file
);
588 print_raw_format
= (value_entirely_available (val
)
589 && !value_optimized_out (val
));
591 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
)
593 struct value_print_options opts
;
594 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
595 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
597 get_user_print_options (&opts
);
601 value_embedded_offset (val
), 0,
602 file
, 0, val
, &opts
, current_language
);
604 if (print_raw_format
)
606 fprintf_filtered (file
, "\t(raw ");
607 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
609 fprintf_filtered (file
, ")");
614 struct value_print_options opts
;
616 /* Print the register in hex. */
617 get_formatted_print_options (&opts
, 'x');
620 value_embedded_offset (val
), 0,
621 file
, 0, val
, &opts
, current_language
);
623 if (print_raw_format
)
625 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
628 int size
= register_size (gdbarch
, regnum
);
631 d
= value_as_long (val
);
633 fprintf_filtered (file
,
634 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
635 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
636 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
637 (int) ((d
>> (xlen
- 1)) & 0x1),
638 (int) ((d
>> 24) & 0x1f),
639 (int) ((d
>> 19) & 0x1),
640 (int) ((d
>> 18) & 0x1),
641 (int) ((d
>> 17) & 0x1),
642 (int) ((d
>> 15) & 0x3),
643 (int) ((d
>> 13) & 0x3),
644 (int) ((d
>> 11) & 0x3),
645 (int) ((d
>> 9) & 0x3),
646 (int) ((d
>> 8) & 0x1),
647 (int) ((d
>> 7) & 0x1),
648 (int) ((d
>> 6) & 0x1),
649 (int) ((d
>> 5) & 0x1),
650 (int) ((d
>> 4) & 0x1),
651 (int) ((d
>> 3) & 0x1),
652 (int) ((d
>> 2) & 0x1),
653 (int) ((d
>> 1) & 0x1),
654 (int) ((d
>> 0) & 0x1));
656 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
662 d
= value_as_long (val
);
666 for (; base
> 0; base
--)
668 fprintf_filtered (file
, "\tRV%d", xlen
);
670 for (i
= 0; i
< 26; i
++)
673 fprintf_filtered (file
, "%c", 'A' + i
);
676 else if (regnum
== RISCV_CSR_FCSR_REGNUM
677 || regnum
== RISCV_CSR_FFLAGS_REGNUM
678 || regnum
== RISCV_CSR_FRM_REGNUM
)
682 d
= value_as_long (val
);
684 fprintf_filtered (file
, "\t");
685 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
686 fprintf_filtered (file
,
687 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
688 (int) ((d
>> 5) & 0x7),
689 (int) ((d
>> 4) & 0x1),
690 (int) ((d
>> 3) & 0x1),
691 (int) ((d
>> 2) & 0x1),
692 (int) ((d
>> 1) & 0x1),
693 (int) ((d
>> 0) & 0x1));
695 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
697 static const char * const sfrm
[] =
699 "RNE (round to nearest; ties to even)",
700 "RTZ (Round towards zero)",
701 "RDN (Round down towards -INF)",
702 "RUP (Round up towards +INF)",
703 "RMM (Round to nearest; ties to max magnitude)",
706 "dynamic rounding mode",
708 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
709 ? (d
>> 5) : d
) & 0x3;
711 fprintf_filtered (file
, "%sFRM:%i [%s]",
712 (regnum
== RISCV_CSR_FCSR_REGNUM
717 else if (regnum
== RISCV_PRIV_REGNUM
)
722 d
= value_as_long (val
);
727 static const char * const sprv
[] =
734 fprintf_filtered (file
, "\tprv:%d [%s]",
738 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
742 /* If not a vector register, print it also according to its
744 if (TYPE_VECTOR (regtype
) == 0)
746 get_user_print_options (&opts
);
748 fprintf_filtered (file
, "\t");
750 value_embedded_offset (val
), 0,
751 file
, 0, val
, &opts
, current_language
);
756 fprintf_filtered (file
, "\n");
759 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
763 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
764 struct reggroup
*reggroup
)
770 /* Used by 'info registers' and 'info registers <groupname>'. */
772 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
773 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
776 if (reggroup
== all_reggroup
)
778 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
780 /* Only include CSRs that have aliases. */
781 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
783 if (regnum
== riscv_register_aliases
[i
].regnum
)
788 else if (reggroup
== float_reggroup
)
789 return ((regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
790 || (regnum
== RISCV_CSR_FCSR_REGNUM
791 || regnum
== RISCV_CSR_FFLAGS_REGNUM
792 || regnum
== RISCV_CSR_FRM_REGNUM
));
793 else if (reggroup
== general_reggroup
)
794 return regnum
< RISCV_FIRST_FP_REGNUM
;
795 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
797 if (riscv_has_fp_regs (gdbarch
))
798 return regnum
<= RISCV_LAST_FP_REGNUM
;
800 return regnum
< RISCV_FIRST_FP_REGNUM
;
802 else if (reggroup
== system_reggroup
)
804 if (regnum
== RISCV_PRIV_REGNUM
)
806 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
808 /* Only include CSRs that have aliases. */
809 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
811 if (regnum
== riscv_register_aliases
[i
].regnum
)
816 else if (reggroup
== vector_reggroup
)
822 /* Implement the print_registers_info gdbarch method. This is used by
823 'info registers' and 'info all-registers'. */
826 riscv_print_registers_info (struct gdbarch
*gdbarch
,
827 struct ui_file
*file
,
828 struct frame_info
*frame
,
829 int regnum
, int print_all
)
833 /* Print one specified register. */
834 gdb_assert (regnum
<= RISCV_LAST_REGNUM
);
835 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
836 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
837 error (_("Not a valid register for the current processor type"));
838 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
842 struct reggroup
*reggroup
;
845 reggroup
= all_reggroup
;
847 reggroup
= general_reggroup
;
849 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
851 /* Zero never changes, so might as well hide by default. */
852 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
855 /* Registers with no name are not valid on this ISA. */
856 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
857 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
860 /* Is the register in the group we're interested in? */
861 if (!riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
))
864 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
869 /* Class that handles one decoded RiscV instruction. */
875 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
878 /* Unknown value is used at initialisation time. */
881 /* These instructions are all the ones we are interested in during the
892 /* Other instructions are not interesting during the prologue scan, and
907 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
909 /* Get the length of the instruction in bytes. */
913 /* Get the opcode for this instruction. */
914 enum opcode
opcode () const
917 /* Get destination register field for this instruction. This is only
918 valid if the OPCODE implies there is such a field for this
923 /* Get the RS1 register field for this instruction. This is only valid
924 if the OPCODE implies there is such a field for this instruction. */
928 /* Get the RS2 register field for this instruction. This is only valid
929 if the OPCODE implies there is such a field for this instruction. */
933 /* Get the immediate for this instruction in signed form. This is only
934 valid if the OPCODE implies there is such a field for this
936 int imm_signed () const
941 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
942 int decode_register_index (unsigned long opcode
, int offset
)
944 return (opcode
>> offset
) & 0x1F;
947 /* Helper for DECODE, decode 32-bit R-type instruction. */
948 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
951 m_rd
= decode_register_index (ival
, OP_SH_RD
);
952 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
953 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
956 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
957 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
960 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
961 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
964 /* Helper for DECODE, decode 32-bit I-type instruction. */
965 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
968 m_rd
= decode_register_index (ival
, OP_SH_RD
);
969 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
970 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
973 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
974 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
977 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
978 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
981 /* Helper for DECODE, decode 32-bit S-type instruction. */
982 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
985 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
986 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
987 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
990 /* Helper for DECODE, decode 32-bit U-type instruction. */
991 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
994 m_rd
= decode_register_index (ival
, OP_SH_RD
);
995 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
998 /* Fetch instruction from target memory at ADDR, return the content of
999 the instruction, and update LEN with the instruction length. */
1000 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1001 CORE_ADDR addr
, int *len
);
1003 /* The length of the instruction in bytes. Should be 2 or 4. */
1006 /* The instruction opcode. */
1007 enum opcode m_opcode
;
1009 /* The three possible registers an instruction might reference. Not
1010 every instruction fills in all of these registers. Which fields are
1011 valid depends on the opcode. The naming of these fields matches the
1012 naming in the riscv isa manual. */
1017 /* Possible instruction immediate. This is only valid if the instruction
1018 format contains an immediate, not all instruction, whether this is
1019 valid depends on the opcode. Despite only having one format for now
1020 the immediate is packed into a union, later instructions might require
1021 an unsigned formatted immediate, having the union in place now will
1022 reduce the need for code churn later. */
1023 union riscv_insn_immediate
1025 riscv_insn_immediate ()
1035 /* Fetch instruction from target memory at ADDR, return the content of the
1036 instruction, and update LEN with the instruction length. */
1039 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1040 CORE_ADDR addr
, int *len
)
1042 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1044 int instlen
, status
;
1046 /* All insns are at least 16 bits. */
1047 status
= target_read_memory (addr
, buf
, 2);
1049 memory_error (TARGET_XFER_E_IO
, addr
);
1051 /* If we need more, grab it now. */
1052 instlen
= riscv_insn_length (buf
[0]);
1053 gdb_assert (instlen
<= sizeof (buf
));
1058 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1060 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1063 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1066 /* Fetch from target memory an instruction at PC and decode it. */
1069 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1073 /* Fetch the instruction, and the instructions length. */
1074 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1078 if (is_add_insn (ival
))
1079 decode_r_type_insn (ADD
, ival
);
1080 else if (is_addw_insn (ival
))
1081 decode_r_type_insn (ADDW
, ival
);
1082 else if (is_addi_insn (ival
))
1083 decode_i_type_insn (ADDI
, ival
);
1084 else if (is_addiw_insn (ival
))
1085 decode_i_type_insn (ADDIW
, ival
);
1086 else if (is_auipc_insn (ival
))
1087 decode_u_type_insn (AUIPC
, ival
);
1088 else if (is_lui_insn (ival
))
1089 decode_u_type_insn (LUI
, ival
);
1090 else if (is_sd_insn (ival
))
1091 decode_s_type_insn (SD
, ival
);
1092 else if (is_sw_insn (ival
))
1093 decode_s_type_insn (SW
, ival
);
1095 /* None of the other fields are valid in this case. */
1098 else if (m_length
== 2)
1100 if (is_c_add_insn (ival
))
1101 decode_cr_type_insn (ADD
, ival
);
1102 else if (is_c_addw_insn (ival
))
1103 decode_cr_type_insn (ADDW
, ival
);
1104 else if (is_c_addi_insn (ival
))
1105 decode_ci_type_insn (ADDI
, ival
);
1106 else if (is_c_addiw_insn (ival
))
1107 decode_ci_type_insn (ADDIW
, ival
);
1108 else if (is_c_addi16sp_insn (ival
))
1111 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1112 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1114 else if (is_lui_insn (ival
))
1116 else if (is_c_sd_insn (ival
))
1118 else if (is_sw_insn (ival
))
1121 /* None of the other fields of INSN are valid in this case. */
1125 internal_error (__FILE__
, __LINE__
,
1126 _("unable to decode %d byte instructions in "
1127 "prologue at %s"), m_length
,
1128 core_addr_to_string (pc
));
1131 /* The prologue scanner. This is currently only used for skipping the
1132 prologue of a function when the DWARF information is not sufficient.
1133 However, it is written with filling of the frame cache in mind, which
1134 is why different groups of stack setup instructions are split apart
1135 during the core of the inner loop. In the future, the intention is to
1136 extend this function to fully support building up a frame cache that
1137 can unwind register values when there is no DWARF information. */
1140 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1141 CORE_ADDR start_pc
, CORE_ADDR limit_pc
)
1143 CORE_ADDR cur_pc
, next_pc
;
1144 long frame_offset
= 0;
1145 CORE_ADDR end_prologue_addr
= 0;
1147 if (limit_pc
> start_pc
+ 200)
1148 limit_pc
= start_pc
+ 200;
1150 for (next_pc
= cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
= next_pc
)
1152 struct riscv_insn insn
;
1154 /* Decode the current instruction, and decide where the next
1155 instruction lives based on the size of this instruction. */
1156 insn
.decode (gdbarch
, cur_pc
);
1157 gdb_assert (insn
.length () > 0);
1158 next_pc
= cur_pc
+ insn
.length ();
1160 /* Look for common stack adjustment insns. */
1161 if ((insn
.opcode () == riscv_insn::ADDI
1162 || insn
.opcode () == riscv_insn::ADDIW
)
1163 && insn
.rd () == RISCV_SP_REGNUM
1164 && insn
.rs1 () == RISCV_SP_REGNUM
)
1166 /* Handle: addi sp, sp, -i
1167 or: addiw sp, sp, -i */
1168 if (insn
.imm_signed () < 0)
1169 frame_offset
+= insn
.imm_signed ();
1173 else if ((insn
.opcode () == riscv_insn::SW
1174 || insn
.opcode () == riscv_insn::SD
)
1175 && (insn
.rs1 () == RISCV_SP_REGNUM
1176 || insn
.rs1 () == RISCV_FP_REGNUM
))
1178 /* Handle: sw reg, offset(sp)
1179 or: sd reg, offset(sp)
1180 or: sw reg, offset(s0)
1181 or: sd reg, offset(s0) */
1182 /* Instruction storing a register onto the stack. */
1184 else if (insn
.opcode () == riscv_insn::ADDI
1185 && insn
.rd () == RISCV_FP_REGNUM
1186 && insn
.rs1 () == RISCV_SP_REGNUM
)
1188 /* Handle: addi s0, sp, size */
1189 /* Instructions setting up the frame pointer. */
1191 else if ((insn
.opcode () == riscv_insn::ADD
1192 || insn
.opcode () == riscv_insn::ADDW
)
1193 && insn
.rd () == RISCV_FP_REGNUM
1194 && insn
.rs1 () == RISCV_SP_REGNUM
1195 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1197 /* Handle: add s0, sp, 0
1198 or: addw s0, sp, 0 */
1199 /* Instructions setting up the frame pointer. */
1201 else if ((insn
.rd () == RISCV_GP_REGNUM
1202 && (insn
.opcode () == riscv_insn::AUIPC
1203 || insn
.opcode () == riscv_insn::LUI
1204 || (insn
.opcode () == riscv_insn::ADDI
1205 && insn
.rs1 () == RISCV_GP_REGNUM
)
1206 || (insn
.opcode () == riscv_insn::ADD
1207 && (insn
.rs1 () == RISCV_GP_REGNUM
1208 || insn
.rs2 () == RISCV_GP_REGNUM
))))
1209 || (insn
.opcode () == riscv_insn::ADDI
1210 && insn
.rd () == RISCV_ZERO_REGNUM
1211 && insn
.rs1 () == RISCV_ZERO_REGNUM
1212 && insn
.imm_signed () == 0))
1214 /* Handle: auipc gp, n
1219 or: add x0, x0, 0 (NOP) */
1220 /* These instructions are part of the prologue, but we don't need
1221 to do anything special to handle them. */
1225 if (end_prologue_addr
== 0)
1226 end_prologue_addr
= cur_pc
;
1230 if (end_prologue_addr
== 0)
1231 end_prologue_addr
= cur_pc
;
1233 return end_prologue_addr
;
1236 /* Implement the riscv_skip_prologue gdbarch method. */
1239 riscv_skip_prologue (struct gdbarch
*gdbarch
,
1243 CORE_ADDR func_addr
;
1245 /* See if we can determine the end of the prologue via the symbol
1246 table. If so, then return either PC, or the PC after the
1247 prologue, whichever is greater. */
1248 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1250 CORE_ADDR post_prologue_pc
1251 = skip_prologue_using_sal (gdbarch
, func_addr
);
1253 if (post_prologue_pc
!= 0)
1254 return std::max (pc
, post_prologue_pc
);
1257 /* Can't determine prologue from the symbol table, need to examine
1260 /* Find an upper limit on the function prologue using the debug
1261 information. If the debug information could not be used to provide
1262 that bound, then use an arbitrary large number as the upper bound. */
1263 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1265 limit_pc
= pc
+ 100; /* MAGIC! */
1267 return riscv_scan_prologue (gdbarch
, pc
, limit_pc
);
1270 /* Implement the gdbarch push dummy code callback. */
1273 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1274 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1275 struct type
*value_type
, CORE_ADDR
*real_pc
,
1276 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1278 /* Allocate space for a breakpoint, and keep the stack correctly
1286 /* Compute the alignment of the type T. Used while setting up the
1287 arguments for a dummy call. */
1290 riscv_type_alignment (struct type
*t
)
1292 t
= check_typedef (t
);
1293 switch (TYPE_CODE (t
))
1296 error (_("Could not compute alignment of type"));
1298 case TYPE_CODE_RVALUE_REF
:
1300 case TYPE_CODE_ENUM
:
1304 case TYPE_CODE_CHAR
:
1305 case TYPE_CODE_BOOL
:
1306 return TYPE_LENGTH (t
);
1308 case TYPE_CODE_ARRAY
:
1309 case TYPE_CODE_COMPLEX
:
1310 return riscv_type_alignment (TYPE_TARGET_TYPE (t
));
1312 case TYPE_CODE_STRUCT
:
1313 case TYPE_CODE_UNION
:
1318 for (i
= 0; i
< TYPE_NFIELDS (t
); ++i
)
1320 if (TYPE_FIELD_LOC_KIND (t
, i
) == FIELD_LOC_KIND_BITPOS
)
1322 int a
= riscv_type_alignment (TYPE_FIELD_TYPE (t
, i
));
1332 /* Holds information about a single argument either being passed to an
1333 inferior function, or returned from an inferior function. This includes
1334 information about the size, type, etc of the argument, and also
1335 information about how the argument will be passed (or returned). */
1337 struct riscv_arg_info
1339 /* Contents of the argument. */
1340 const gdb_byte
*contents
;
1342 /* Length of argument. */
1345 /* Alignment required for an argument of this type. */
1348 /* The type for this argument. */
1351 /* Each argument can have either 1 or 2 locations assigned to it. Each
1352 location describes where part of the argument will be placed. The
1353 second location is valid based on the LOC_TYPE and C_LENGTH fields
1354 of the first location (which is always valid). */
1357 /* What type of location this is. */
1360 /* Argument passed in a register. */
1363 /* Argument passed as an on stack argument. */
1366 /* Argument passed by reference. The second location is always
1367 valid for a BY_REF argument, and describes where the address
1368 of the BY_REF argument should be placed. */
1372 /* Information that depends on the location type. */
1375 /* Which register number to use. */
1378 /* The offset into the stack region. */
1382 /* The length of contents covered by this location. If this is less
1383 than the total length of the argument, then the second location
1384 will be valid, and will describe where the rest of the argument
1388 /* The offset within CONTENTS for this part of the argument. Will
1389 always be 0 for the first part. For the second part of the
1390 argument, this might be the C_LENGTH value of the first part,
1391 however, if we are passing a structure in two registers, and there's
1392 is padding between the first and second field, then this offset
1393 might be greater than the length of the first argument part. When
1394 the second argument location is not holding part of the argument
1395 value, but is instead holding the address of a reference argument,
1396 then this offset will be set to 0. */
1401 /* Information about a set of registers being used for passing arguments as
1402 part of a function call. The register set must be numerically
1403 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1404 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1406 struct riscv_arg_reg
1408 riscv_arg_reg (int first
, int last
)
1409 : next_regnum (first
),
1415 /* The GDB register number to use in this set. */
1418 /* The last GDB register number to use in this set. */
1422 /* Arguments can be passed as on stack arguments, or by reference. The
1423 on stack arguments must be in a continuous region starting from $sp,
1424 while the by reference arguments can be anywhere, but we'll put them
1425 on the stack after (at higher address) the on stack arguments.
1427 This might not be the right approach to take. The ABI is clear that
1428 an argument passed by reference can be modified by the callee, which
1429 us placing the argument (temporarily) onto the stack will not achieve
1430 (changes will be lost). There's also the possibility that very large
1431 arguments could overflow the stack.
1433 This struct is used to track offset into these two areas for where
1434 arguments are to be placed. */
1435 struct riscv_memory_offsets
1437 riscv_memory_offsets ()
1444 /* Offset into on stack argument area. */
1447 /* Offset into the pass by reference area. */
1451 /* Holds information about where arguments to a call will be placed. This
1452 is updated as arguments are added onto the call, and can be used to
1453 figure out where the next argument should be placed. */
1455 struct riscv_call_info
1457 riscv_call_info (struct gdbarch
*gdbarch
)
1458 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1459 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1461 xlen
= riscv_isa_xlen (gdbarch
);
1462 flen
= riscv_isa_flen (gdbarch
);
1464 /* Disable use of floating point registers if needed. */
1465 if (!riscv_has_fp_abi (gdbarch
))
1466 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1469 /* Track the memory areas used for holding in-memory arguments to a
1471 struct riscv_memory_offsets memory
;
1473 /* Holds information about the next integer register to use for passing
1475 struct riscv_arg_reg int_regs
;
1477 /* Holds information about the next floating point register to use for
1478 passing an argument. */
1479 struct riscv_arg_reg float_regs
;
1481 /* The XLEN and FLEN are copied in to this structure for convenience, and
1482 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1487 /* Return the number of registers available for use as parameters in the
1488 register set REG. Returned value can be 0 or more. */
1491 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1493 if (reg
->next_regnum
> reg
->last_regnum
)
1496 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1499 /* If there is at least one register available in the register set REG then
1500 the next register from REG is assigned to LOC and the length field of
1501 LOC is updated to LENGTH. The register set REG is updated to indicate
1502 that the assigned register is no longer available and the function
1505 If there are no registers available in REG then the function returns
1506 false, and LOC and REG are unchanged. */
1509 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1510 struct riscv_arg_reg
*reg
,
1511 int length
, int offset
)
1513 if (reg
->next_regnum
<= reg
->last_regnum
)
1515 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1516 loc
->loc_data
.regno
= reg
->next_regnum
;
1518 loc
->c_length
= length
;
1519 loc
->c_offset
= offset
;
1526 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1527 record that an area of stack has been used to hold the parameter
1530 The length field of LOC is updated to LENGTH, the length of the
1531 parameter being stored, and ALIGN is the alignment required by the
1532 parameter, which will affect how memory is allocated out of MEMORY. */
1535 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1536 struct riscv_memory_offsets
*memory
,
1537 int length
, int align
)
1539 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1541 = align_up (memory
->arg_offset
, align
);
1542 loc
->loc_data
.offset
= memory
->arg_offset
;
1543 memory
->arg_offset
+= length
;
1544 loc
->c_length
= length
;
1546 /* Offset is always 0, either we're the first location part, in which
1547 case we're reading content from the start of the argument, or we're
1548 passing the address of a reference argument, so 0. */
1552 /* Update AINFO, which describes an argument that should be passed or
1553 returned using the integer ABI. The argloc fields within AINFO are
1554 updated to describe the location in which the argument will be passed to
1555 a function, or returned from a function.
1557 The CINFO structure contains the ongoing call information, the holds
1558 information such as which argument registers are remaining to be
1559 assigned to parameter, and how much memory has been used by parameters
1562 By examining the state of CINFO a suitable location can be selected,
1563 and assigned to AINFO. */
1566 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1567 struct riscv_call_info
*cinfo
)
1569 if (ainfo
->length
> (2 * cinfo
->xlen
))
1571 /* Argument is going to be passed by reference. */
1572 ainfo
->argloc
[0].loc_type
1573 = riscv_arg_info::location::by_ref
;
1574 cinfo
->memory
.ref_offset
1575 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1576 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1577 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1578 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1580 /* The second location for this argument is given over to holding the
1581 address of the by-reference data. Pass 0 for the offset as this
1582 is not part of the actual argument value. */
1583 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1586 riscv_assign_stack_location (&ainfo
->argloc
[1],
1587 &cinfo
->memory
, cinfo
->xlen
,
1592 int len
= (ainfo
->length
> cinfo
->xlen
) ? cinfo
->xlen
: ainfo
->length
;
1594 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1595 &cinfo
->int_regs
, len
, 0))
1596 riscv_assign_stack_location (&ainfo
->argloc
[0],
1597 &cinfo
->memory
, len
, ainfo
->align
);
1599 if (len
< ainfo
->length
)
1601 len
= ainfo
->length
- len
;
1602 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1603 &cinfo
->int_regs
, len
,
1605 riscv_assign_stack_location (&ainfo
->argloc
[1],
1606 &cinfo
->memory
, len
, cinfo
->xlen
);
1611 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1612 is being passed with the floating point ABI. */
1615 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1616 struct riscv_call_info
*cinfo
)
1618 if (ainfo
->length
> cinfo
->flen
)
1619 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1622 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1625 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1629 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1630 is a complex floating point argument, and is therefore handled
1631 differently to other argument types. */
1634 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1635 struct riscv_call_info
*cinfo
)
1637 if (ainfo
->length
<= (2 * cinfo
->flen
)
1638 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1641 int len
= ainfo
->length
/ 2;
1643 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1644 &cinfo
->float_regs
, len
, len
);
1645 gdb_assert (result
);
1647 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1648 &cinfo
->float_regs
, len
, len
);
1649 gdb_assert (result
);
1652 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1655 /* A structure used for holding information about a structure type within
1656 the inferior program. The RiscV ABI has special rules for handling some
1657 structures with a single field or with two fields. The counting of
1658 fields here is done after flattening out all nested structures. */
1660 class riscv_struct_info
1663 riscv_struct_info ()
1664 : m_number_of_fields (0),
1665 m_types
{ nullptr, nullptr }
1670 /* Analyse TYPE descending into nested structures, count the number of
1671 scalar fields and record the types of the first two fields found. */
1672 void analyse (struct type
*type
);
1674 /* The number of scalar fields found in the analysed type. This is
1675 currently only accurate if the value returned is 0, 1, or 2 as the
1676 analysis stops counting when the number of fields is 3. This is
1677 because the RiscV ABI only has special cases for 1 or 2 fields,
1678 anything else we just don't care about. */
1679 int number_of_fields () const
1680 { return m_number_of_fields
; }
1682 /* Return the type for scalar field INDEX within the analysed type. Will
1683 return nullptr if there is no field at that index. Only INDEX values
1684 0 and 1 can be requested as the RiscV ABI only has special cases for
1685 structures with 1 or 2 fields. */
1686 struct type
*field_type (int index
) const
1688 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
1689 return m_types
[index
];
1693 /* The number of scalar fields found within the structure after recursing
1694 into nested structures. */
1695 int m_number_of_fields
;
1697 /* The types of the first two scalar fields found within the structure
1698 after recursing into nested structures. */
1699 struct type
*m_types
[2];
1702 /* Analyse TYPE descending into nested structures, count the number of
1703 scalar fields and record the types of the first two fields found. */
1706 riscv_struct_info::analyse (struct type
*type
)
1708 unsigned int count
= TYPE_NFIELDS (type
);
1711 for (i
= 0; i
< count
; ++i
)
1713 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
1716 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
1717 field_type
= check_typedef (field_type
);
1719 switch (TYPE_CODE (field_type
))
1721 case TYPE_CODE_STRUCT
:
1722 analyse (field_type
);
1726 /* RiscV only flattens out structures. Anything else does not
1727 need to be flattened, we just record the type, and when we
1728 look at the analysis results we'll realise this is not a
1729 structure we can special case, and pass the structure in
1731 if (m_number_of_fields
< 2)
1732 m_types
[m_number_of_fields
] = field_type
;
1733 m_number_of_fields
++;
1737 /* RiscV only has special handling for structures with 1 or 2 scalar
1738 fields, any more than that and the structure is just passed in
1739 memory. We can safely drop out early when we find 3 or more
1742 if (m_number_of_fields
> 2)
1747 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1748 is a structure. Small structures on RiscV have some special case
1749 handling in order that the structure might be passed in register.
1750 Larger structures are passed in memory. After assigning location
1751 information to AINFO, CINFO will have been updated. */
1754 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
1755 struct riscv_call_info
*cinfo
)
1757 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
1759 struct riscv_struct_info sinfo
;
1761 sinfo
.analyse (ainfo
->type
);
1762 if (sinfo
.number_of_fields () == 1
1763 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
1765 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1766 == TYPE_LENGTH (sinfo
.field_type (0)));
1767 return riscv_call_arg_complex_float (ainfo
, cinfo
);
1770 if (sinfo
.number_of_fields () == 1
1771 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
1773 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1774 == TYPE_LENGTH (sinfo
.field_type (0)));
1775 return riscv_call_arg_scalar_float (ainfo
, cinfo
);
1778 if (sinfo
.number_of_fields () == 2
1779 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1780 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1781 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1782 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
1783 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1785 int len0
, len1
, offset
;
1787 gdb_assert (TYPE_LENGTH (ainfo
->type
) <= (2 * cinfo
->flen
));
1789 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1790 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1791 &cinfo
->float_regs
, len0
, 0))
1792 error (_("failed during argument setup"));
1794 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1795 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1796 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
1797 - TYPE_LENGTH (sinfo
.field_type (0))));
1799 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1802 error (_("failed during argument setup"));
1806 if (sinfo
.number_of_fields () == 2
1807 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1808 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1809 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1810 && is_integral_type (sinfo
.field_type (1))
1811 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
1813 int len0
, len1
, offset
;
1815 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1816 <= (cinfo
->flen
+ cinfo
->xlen
));
1818 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1819 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1820 &cinfo
->float_regs
, len0
, 0))
1821 error (_("failed during argument setup"));
1823 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1824 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1825 gdb_assert (len1
<= cinfo
->xlen
);
1826 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1827 &cinfo
->int_regs
, len1
, offset
))
1828 error (_("failed during argument setup"));
1832 if (sinfo
.number_of_fields () == 2
1833 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1834 && (is_integral_type (sinfo
.field_type (0))
1835 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
1836 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1837 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
1839 int len0
, len1
, offset
;
1841 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1842 <= (cinfo
->flen
+ cinfo
->xlen
));
1844 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1845 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1846 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1848 gdb_assert (len0
<= cinfo
->xlen
);
1849 gdb_assert (len1
<= cinfo
->flen
);
1851 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1852 &cinfo
->int_regs
, len0
, 0))
1853 error (_("failed during argument setup"));
1855 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1858 error (_("failed during argument setup"));
1864 /* Non of the structure flattening cases apply, so we just pass using
1866 ainfo
->length
= align_up (ainfo
->length
, cinfo
->xlen
);
1867 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1870 /* Assign a location to call (or return) argument AINFO, the location is
1871 selected from CINFO which holds information about what call argument
1872 locations are available for use next. The TYPE is the type of the
1873 argument being passed, this information is recorded into AINFO (along
1874 with some additional information derived from the type).
1876 After assigning a location to AINFO, CINFO will have been updated. */
1879 riscv_arg_location (struct gdbarch
*gdbarch
,
1880 struct riscv_arg_info
*ainfo
,
1881 struct riscv_call_info
*cinfo
,
1885 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
1886 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1887 ainfo
->contents
= nullptr;
1889 switch (TYPE_CODE (ainfo
->type
))
1892 case TYPE_CODE_BOOL
:
1893 case TYPE_CODE_CHAR
:
1894 case TYPE_CODE_RANGE
:
1895 case TYPE_CODE_ENUM
:
1897 if (ainfo
->length
<= cinfo
->xlen
)
1899 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
1900 ainfo
->length
= cinfo
->xlen
;
1902 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
1904 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
1905 ainfo
->length
= 2 * cinfo
->xlen
;
1908 /* Recalculate the alignment requirement. */
1909 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1910 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1914 riscv_call_arg_scalar_float (ainfo
, cinfo
);
1917 case TYPE_CODE_COMPLEX
:
1918 riscv_call_arg_complex_float (ainfo
, cinfo
);
1921 case TYPE_CODE_STRUCT
:
1922 riscv_call_arg_struct (ainfo
, cinfo
);
1926 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1931 /* Used for printing debug information about the call argument location in
1932 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
1933 addresses for the location of pass-by-reference and
1934 arguments-on-the-stack memory areas. */
1937 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
1938 struct riscv_arg_info
*info
,
1939 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
1941 const char* type_name
= TYPE_NAME (info
->type
);
1942 if (type_name
== nullptr)
1945 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
1946 type_name
, info
->length
, info
->align
);
1947 switch (info
->argloc
[0].loc_type
)
1949 case riscv_arg_info::location::in_reg
:
1951 (stream
, ", register %s",
1952 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
1953 if (info
->argloc
[0].c_length
< info
->length
)
1955 switch (info
->argloc
[1].loc_type
)
1957 case riscv_arg_info::location::in_reg
:
1959 (stream
, ", register %s",
1960 gdbarch_register_name (gdbarch
,
1961 info
->argloc
[1].loc_data
.regno
));
1964 case riscv_arg_info::location::on_stack
:
1965 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1966 info
->argloc
[1].loc_data
.offset
);
1969 case riscv_arg_info::location::by_ref
:
1971 /* The second location should never be a reference, any
1972 argument being passed by reference just places its address
1973 in the first location and is done. */
1974 error (_("invalid argument location"));
1978 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
1979 fprintf_unfiltered (stream
, " (offset 0x%x)",
1980 info
->argloc
[1].c_offset
);
1984 case riscv_arg_info::location::on_stack
:
1985 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1986 info
->argloc
[0].loc_data
.offset
);
1989 case riscv_arg_info::location::by_ref
:
1991 (stream
, ", by reference, data at offset 0x%x (%s)",
1992 info
->argloc
[0].loc_data
.offset
,
1993 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
1994 if (info
->argloc
[1].loc_type
1995 == riscv_arg_info::location::in_reg
)
1997 (stream
, ", address in register %s",
1998 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2001 gdb_assert (info
->argloc
[1].loc_type
2002 == riscv_arg_info::location::on_stack
);
2004 (stream
, ", address on stack at offset 0x%x (%s)",
2005 info
->argloc
[1].loc_data
.offset
,
2006 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2011 gdb_assert_not_reached (_("unknown argument location type"));
2015 /* Implement the push dummy call gdbarch callback. */
2018 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2019 struct value
*function
,
2020 struct regcache
*regcache
,
2023 struct value
**args
,
2026 CORE_ADDR struct_addr
)
2029 CORE_ADDR sp_args
, sp_refs
;
2030 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2031 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2033 struct riscv_arg_info
*arg_info
=
2034 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2035 struct riscv_arg_info
*info
;
2037 struct riscv_call_info
call_info (gdbarch
);
2041 /* We'll use register $a0 if we're returning a struct. */
2043 ++call_info
.int_regs
.next_regnum
;
2045 for (i
= 0, info
= &arg_info
[0];
2049 struct value
*arg_value
;
2050 struct type
*arg_type
;
2052 arg_value
= args
[i
];
2053 arg_type
= check_typedef (value_type (arg_value
));
2055 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
);
2057 if (info
->type
!= arg_type
)
2058 arg_value
= value_cast (info
->type
, arg_value
);
2059 info
->contents
= value_contents (arg_value
);
2062 /* Adjust the stack pointer and align it. */
2063 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2064 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2066 if (riscv_debug_infcall
> 0)
2068 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2069 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2070 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2071 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2072 call_info
.xlen
, call_info
.flen
);
2074 fprintf_unfiltered (gdb_stdlog
,
2075 "[*] struct return pointer in register $A0\n");
2076 for (i
= 0; i
< nargs
; ++i
)
2078 struct riscv_arg_info
*info
= &arg_info
[i
];
2080 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2081 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2082 fprintf_unfiltered (gdb_stdlog
, "\n");
2084 if (call_info
.memory
.arg_offset
> 0
2085 || call_info
.memory
.ref_offset
> 0)
2087 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2088 core_addr_to_string (osp
));
2089 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2090 call_info
.memory
.arg_offset
);
2091 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2092 call_info
.memory
.ref_offset
);
2093 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2094 core_addr_to_string_nz (osp
- sp
));
2098 /* Now load the argument into registers, or onto the stack. */
2102 gdb_byte buf
[sizeof (LONGEST
)];
2104 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2105 regcache_cooked_write (regcache
, RISCV_A0_REGNUM
, buf
);
2108 for (i
= 0; i
< nargs
; ++i
)
2111 int second_arg_length
= 0;
2112 const gdb_byte
*second_arg_data
;
2113 struct riscv_arg_info
*info
= &arg_info
[i
];
2115 gdb_assert (info
->length
> 0);
2117 switch (info
->argloc
[0].loc_type
)
2119 case riscv_arg_info::location::in_reg
:
2121 gdb_byte tmp
[sizeof (ULONGEST
)];
2123 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2124 memset (tmp
, 0, sizeof (tmp
));
2125 memcpy (tmp
, info
->contents
, info
->argloc
[0].c_length
);
2126 regcache_cooked_write (regcache
,
2127 info
->argloc
[0].loc_data
.regno
,
2130 ((info
->argloc
[0].c_length
< info
->length
)
2131 ? info
->argloc
[1].c_length
: 0);
2132 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2136 case riscv_arg_info::location::on_stack
:
2137 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2138 write_memory (dst
, info
->contents
, info
->length
);
2139 second_arg_length
= 0;
2142 case riscv_arg_info::location::by_ref
:
2143 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2144 write_memory (dst
, info
->contents
, info
->length
);
2146 second_arg_length
= call_info
.xlen
;
2147 second_arg_data
= (gdb_byte
*) &dst
;
2151 gdb_assert_not_reached (_("unknown argument location type"));
2154 if (second_arg_length
> 0)
2156 switch (info
->argloc
[1].loc_type
)
2158 case riscv_arg_info::location::in_reg
:
2160 gdb_byte tmp
[sizeof (ULONGEST
)];
2162 gdb_assert (second_arg_length
<= call_info
.xlen
);
2163 memset (tmp
, 0, sizeof (tmp
));
2164 memcpy (tmp
, second_arg_data
, second_arg_length
);
2165 regcache_cooked_write (regcache
,
2166 info
->argloc
[1].loc_data
.regno
,
2171 case riscv_arg_info::location::on_stack
:
2175 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2176 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2180 case riscv_arg_info::location::by_ref
:
2182 /* The second location should never be a reference, any
2183 argument being passed by reference just places its address
2184 in the first location and is done. */
2185 error (_("invalid argument location"));
2191 /* Set the dummy return value to bp_addr.
2192 A dummy breakpoint will be setup to execute the call. */
2194 if (riscv_debug_infcall
> 0)
2195 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2196 core_addr_to_string (bp_addr
));
2197 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2199 /* Finally, update the stack pointer. */
2201 if (riscv_debug_infcall
> 0)
2202 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2203 core_addr_to_string (sp
));
2204 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2209 /* Implement the return_value gdbarch method. */
2211 static enum return_value_convention
2212 riscv_return_value (struct gdbarch
*gdbarch
,
2213 struct value
*function
,
2215 struct regcache
*regcache
,
2217 const gdb_byte
*writebuf
)
2219 enum type_code rv_type
= TYPE_CODE (type
);
2220 unsigned int rv_size
= TYPE_LENGTH (type
);
2221 int fp
, regnum
, flen
;
2223 struct riscv_call_info
call_info (gdbarch
);
2224 struct riscv_arg_info info
;
2225 struct type
*arg_type
;
2227 arg_type
= check_typedef (type
);
2228 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
);
2230 if (riscv_debug_infcall
> 0)
2232 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2233 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2234 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2235 fprintf_unfiltered (gdb_stdlog
, "\n");
2238 if (readbuf
!= nullptr || writebuf
!= nullptr)
2242 switch (info
.argloc
[0].loc_type
)
2244 /* Return value in register(s). */
2245 case riscv_arg_info::location::in_reg
:
2247 regnum
= info
.argloc
[0].loc_data
.regno
;
2250 regcache_cooked_read (regcache
, regnum
, readbuf
);
2253 regcache_cooked_write (regcache
, regnum
, writebuf
);
2255 /* A return value in register can have a second part in a
2257 if (info
.argloc
[0].c_length
< info
.length
)
2259 switch (info
.argloc
[1].loc_type
)
2261 case riscv_arg_info::location::in_reg
:
2262 regnum
= info
.argloc
[1].loc_data
.regno
;
2266 readbuf
+= info
.argloc
[1].c_offset
;
2267 regcache_cooked_read (regcache
, regnum
, readbuf
);
2272 writebuf
+= info
.argloc
[1].c_offset
;
2273 regcache_cooked_write (regcache
, regnum
, writebuf
);
2277 case riscv_arg_info::location::by_ref
:
2278 case riscv_arg_info::location::on_stack
:
2280 error (_("invalid argument location"));
2287 /* Return value by reference will have its address in A0. */
2288 case riscv_arg_info::location::by_ref
:
2292 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2294 if (readbuf
!= nullptr)
2295 read_memory (addr
, readbuf
, info
.length
);
2296 if (writebuf
!= nullptr)
2297 write_memory (addr
, writebuf
, info
.length
);
2301 case riscv_arg_info::location::on_stack
:
2303 error (_("invalid argument location"));
2308 switch (info
.argloc
[0].loc_type
)
2310 case riscv_arg_info::location::in_reg
:
2311 return RETURN_VALUE_REGISTER_CONVENTION
;
2312 case riscv_arg_info::location::by_ref
:
2313 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2314 case riscv_arg_info::location::on_stack
:
2316 error (_("invalid argument location"));
2320 /* Implement the frame_align gdbarch method. */
2323 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2325 return align_down (addr
, 16);
2328 /* Implement the unwind_pc gdbarch method. */
2331 riscv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2333 return frame_unwind_register_unsigned (next_frame
, RISCV_PC_REGNUM
);
2336 /* Implement the unwind_sp gdbarch method. */
2339 riscv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2341 return frame_unwind_register_unsigned (next_frame
, RISCV_SP_REGNUM
);
2344 /* Implement the dummy_id gdbarch method. */
2346 static struct frame_id
2347 riscv_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2349 return frame_id_build (get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
),
2350 get_frame_pc (this_frame
));
2353 /* Generate, or return the cached frame cache for the RiscV frame
2356 static struct trad_frame_cache
*
2357 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2360 CORE_ADDR start_addr
;
2361 CORE_ADDR stack_addr
;
2362 struct trad_frame_cache
*this_trad_cache
;
2363 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2365 if ((*this_cache
) != NULL
)
2366 return (struct trad_frame_cache
*) *this_cache
;
2367 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2368 (*this_cache
) = this_trad_cache
;
2370 trad_frame_set_reg_realreg (this_trad_cache
, gdbarch_pc_regnum (gdbarch
),
2373 pc
= get_frame_pc (this_frame
);
2374 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2375 stack_addr
= get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
);
2376 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2378 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2380 return this_trad_cache
;
2383 /* Implement the this_id callback for RiscV frame unwinder. */
2386 riscv_frame_this_id (struct frame_info
*this_frame
,
2387 void **prologue_cache
,
2388 struct frame_id
*this_id
)
2390 struct trad_frame_cache
*info
;
2392 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2393 trad_frame_get_id (info
, this_id
);
2396 /* Implement the prev_register callback for RiscV frame unwinder. */
2398 static struct value
*
2399 riscv_frame_prev_register (struct frame_info
*this_frame
,
2400 void **prologue_cache
,
2403 struct trad_frame_cache
*info
;
2405 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2406 return trad_frame_get_register (info
, this_frame
, regnum
);
2409 /* Structure defining the RiscV normal frame unwind functions. Since we
2410 are the fallback unwinder (DWARF unwinder is used first), we use the
2411 default frame sniffer, which always accepts the frame. */
2413 static const struct frame_unwind riscv_frame_unwind
=
2415 /*.type =*/ NORMAL_FRAME
,
2416 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2417 /*.this_id =*/ riscv_frame_this_id
,
2418 /*.prev_register =*/ riscv_frame_prev_register
,
2419 /*.unwind_data =*/ NULL
,
2420 /*.sniffer =*/ default_frame_sniffer
,
2421 /*.dealloc_cache =*/ NULL
,
2422 /*.prev_arch =*/ NULL
,
2425 /* Initialize the current architecture based on INFO. If possible,
2426 re-use an architecture from ARCHES, which is a list of
2427 architectures already created during this debugging session.
2429 Called e.g. at program startup, when reading a core file, and when
2430 reading a binary file. */
2432 static struct gdbarch
*
2433 riscv_gdbarch_init (struct gdbarch_info info
,
2434 struct gdbarch_list
*arches
)
2436 struct gdbarch
*gdbarch
;
2437 struct gdbarch_tdep
*tdep
;
2438 struct gdbarch_tdep tmp_tdep
;
2439 bool has_compressed_isa
= false;
2442 /* Ideally, we'd like to get as much information from the target for
2443 things like register size, and whether the target has floating point
2444 hardware. However, there are some things that the target can't tell
2445 us, like, what ABI is being used.
2447 So, for now, we take as much information as possible from the ELF,
2448 including things like register size, and FP hardware support, along
2449 with information about the ABI.
2451 Information about this target is built up in TMP_TDEP, and then we
2452 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2453 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2454 memset (&tmp_tdep
, 0, sizeof (tmp_tdep
));
2456 if (info
.abfd
!= NULL
2457 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2459 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2460 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2462 if (eclass
== ELFCLASS32
)
2463 tmp_tdep
.abi
.fields
.base_len
= 1;
2464 else if (eclass
== ELFCLASS64
)
2465 tmp_tdep
.abi
.fields
.base_len
= 2;
2467 internal_error (__FILE__
, __LINE__
,
2468 _("unknown ELF header class %d"), eclass
);
2470 if (e_flags
& EF_RISCV_RVC
)
2472 has_compressed_isa
= true;
2473 tmp_tdep
.core_features
|= (1 << ('C' - 'A'));
2476 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2478 tmp_tdep
.abi
.fields
.float_abi
= 2;
2479 tmp_tdep
.core_features
|= (1 << ('D' - 'A'));
2480 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2482 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2484 tmp_tdep
.abi
.fields
.float_abi
= 1;
2485 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2490 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2492 if (binfo
->bits_per_word
== 32)
2493 tmp_tdep
.abi
.fields
.base_len
= 1;
2494 else if (binfo
->bits_per_word
== 64)
2495 tmp_tdep
.abi
.fields
.base_len
= 2;
2497 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2498 binfo
->bits_per_word
);
2501 /* Find a candidate among the list of pre-declared architectures. */
2502 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2504 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2505 if (gdbarch_tdep (arches
->gdbarch
)->abi
.value
== tmp_tdep
.abi
.value
)
2506 return arches
->gdbarch
;
2508 /* None found, so create a new architecture from the information provided. */
2509 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof *tdep
);
2510 gdbarch
= gdbarch_alloc (&info
, tdep
);
2511 memcpy (tdep
, &tmp_tdep
, sizeof (tmp_tdep
));
2513 /* Target data types. */
2514 set_gdbarch_short_bit (gdbarch
, 16);
2515 set_gdbarch_int_bit (gdbarch
, 32);
2516 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2517 set_gdbarch_long_long_bit (gdbarch
, 64);
2518 set_gdbarch_float_bit (gdbarch
, 32);
2519 set_gdbarch_double_bit (gdbarch
, 64);
2520 set_gdbarch_long_double_bit (gdbarch
, 128);
2521 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
2522 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2523 set_gdbarch_char_signed (gdbarch
, 0);
2525 /* Information about the target architecture. */
2526 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
2527 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
2528 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
2530 /* Register architecture. */
2531 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
2532 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
2533 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
2534 set_gdbarch_ps_regnum (gdbarch
, RISCV_FP_REGNUM
);
2535 set_gdbarch_deprecated_fp_regnum (gdbarch
, RISCV_FP_REGNUM
);
2537 /* Functions to supply register information. */
2538 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
2539 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
2540 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
2541 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
2543 /* Functions to analyze frames. */
2544 set_gdbarch_decr_pc_after_break (gdbarch
, (has_compressed_isa
? 2 : 4));
2545 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
2546 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2547 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
2549 /* Functions to access frame data. */
2550 set_gdbarch_unwind_pc (gdbarch
, riscv_unwind_pc
);
2551 set_gdbarch_unwind_sp (gdbarch
, riscv_unwind_sp
);
2553 /* Functions handling dummy frames. */
2554 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2555 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
2556 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
2557 set_gdbarch_dummy_id (gdbarch
, riscv_dummy_id
);
2559 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2561 dwarf2_append_unwinders (gdbarch
);
2562 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
2564 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
2565 user_reg_add (gdbarch
, riscv_register_aliases
[i
].name
,
2566 value_of_riscv_user_reg
, &riscv_register_aliases
[i
].regnum
);
2572 /* Allocate new riscv_inferior_data object. */
2574 static struct riscv_inferior_data
*
2575 riscv_new_inferior_data (void)
2577 struct riscv_inferior_data
*inf_data
2578 = new (struct riscv_inferior_data
);
2579 inf_data
->misa_read
= false;
2583 /* Free inferior data. */
2586 riscv_inferior_data_cleanup (struct inferior
*inf
, void *data
)
2588 struct riscv_inferior_data
*inf_data
=
2589 static_cast <struct riscv_inferior_data
*> (data
);
2593 /* Return riscv_inferior_data for the given INFERIOR. If not yet created,
2596 struct riscv_inferior_data
*
2597 riscv_inferior_data (struct inferior
*const inf
)
2599 struct riscv_inferior_data
*inf_data
;
2601 gdb_assert (inf
!= NULL
);
2604 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2605 if (inf_data
== NULL
)
2607 inf_data
= riscv_new_inferior_data ();
2608 set_inferior_data (inf
, riscv_inferior_data_reg
, inf_data
);
2614 /* Free the inferior data when an inferior exits. */
2617 riscv_invalidate_inferior_data (struct inferior
*inf
)
2619 struct riscv_inferior_data
*inf_data
;
2621 gdb_assert (inf
!= NULL
);
2623 /* Don't call RISCV_INFERIOR_DATA as we don't want to create the data if
2624 we've not already created it by this point. */
2626 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2627 if (inf_data
!= NULL
)
2630 set_inferior_data (inf
, riscv_inferior_data_reg
, NULL
);
2635 _initialize_riscv_tdep (void)
2637 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
2639 /* Register per-inferior data. */
2640 riscv_inferior_data_reg
2641 = register_inferior_data_with_cleanup (NULL
, riscv_inferior_data_cleanup
);
2643 /* Observers used to invalidate the inferior data when needed. */
2644 gdb::observers::inferior_exit
.attach (riscv_invalidate_inferior_data
);
2645 gdb::observers::inferior_appeared
.attach (riscv_invalidate_inferior_data
);
2647 /* Add root prefix command for all "set debug riscv" and "show debug
2649 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
2650 _("RISC-V specific debug commands."),
2651 &setdebugriscvcmdlist
, "set debug riscv ", 0,
2654 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
2655 _("RISC-V specific debug commands."),
2656 &showdebugriscvcmdlist
, "show debug riscv ", 0,
2659 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
2660 &riscv_debug_infcall
, _("\
2661 Set riscv inferior call debugging."), _("\
2662 Show riscv inferior call debugging."), _("\
2663 When non-zero, print debugging information for the riscv specific parts\n\
2664 of the inferior call mechanism."),
2666 show_riscv_debug_variable
,
2667 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
2669 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2670 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
2671 _("RISC-V specific commands."),
2672 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
2674 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
2675 _("RISC-V specific commands."),
2676 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
2679 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
2680 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
2681 &use_compressed_breakpoints
,
2683 Set debugger's use of compressed breakpoints."), _(" \
2684 Show debugger's use of compressed breakpoints."), _("\
2685 Debugging compressed code requires compressed breakpoints to be used. If\n \
2686 left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2687 is supported. If that doesn't give the correct behavior, then this option\n\
2690 show_use_compressed_breakpoints
,