1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2/frame.h"
51 #include "user-regs.h"
53 #include "gdbsupport/common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
59 #include "riscv-ravenscar-thread.h"
61 /* The stack must be 16-byte aligned. */
62 #define SP_ALIGNMENT 16
64 /* The biggest alignment that the target supports. */
65 #define BIGGEST_ALIGNMENT 16
67 /* Define a series of is_XXX_insn functions to check if the value INSN
68 is an instance of instruction XXX. */
69 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
70 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
72 return (insn & INSN_MASK) == INSN_MATCH; \
74 #include "opcode/riscv-opc.h"
77 /* Cached information about a frame. */
79 struct riscv_unwind_cache
81 /* The register from which we can calculate the frame base. This is
82 usually $sp or $fp. */
85 /* The offset from the current value in register FRAME_BASE_REG to the
86 actual frame base address. */
87 int frame_base_offset
;
89 /* Information about previous register values. */
90 struct trad_frame_saved_reg
*regs
;
92 /* The id for this frame. */
93 struct frame_id this_id
;
95 /* The base (stack) address for this frame. This is the stack pointer
96 value on entry to this frame before any adjustments are made. */
100 /* RISC-V specific register group for CSRs. */
102 static reggroup
*csr_reggroup
= NULL
;
104 /* A set of registers that we expect to find in a tdesc_feature. These
105 are use in RISCV_GDBARCH_INIT when processing the target description. */
107 struct riscv_register_feature
109 /* Information for a single register. */
112 /* The GDB register number for this register. */
115 /* List of names for this register. The first name in this list is the
116 preferred name, the name GDB should use when describing this
118 std::vector
<const char *> names
;
120 /* When true this register is required in this feature set. */
124 /* The name for this feature. This is the name used to find this feature
125 within the target description. */
128 /* List of all the registers that we expect that we might find in this
130 std::vector
<struct register_info
> registers
;
133 /* The general x-registers feature set. */
135 static const struct riscv_register_feature riscv_xreg_feature
=
137 "org.gnu.gdb.riscv.cpu",
139 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" }, true },
140 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" }, true },
141 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" }, true },
142 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" }, true },
143 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" }, true },
144 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" }, true },
145 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" }, true },
146 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" }, true },
147 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" }, true },
148 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" }, true },
149 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" }, true },
150 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" }, true },
151 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" }, true },
152 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" }, true },
153 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" }, true },
154 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" }, true },
155 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" }, true },
156 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" }, true },
157 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" }, true },
158 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" }, true },
159 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" }, true },
160 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" }, true },
161 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" }, true },
162 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" }, true },
163 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" }, true },
164 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" }, true },
165 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" }, true },
166 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" }, true },
167 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" }, true },
168 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" }, true },
169 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" }, true },
170 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" }, true },
171 { RISCV_ZERO_REGNUM
+ 32, { "pc" }, true }
175 /* The f-registers feature set. */
177 static const struct riscv_register_feature riscv_freg_feature
=
179 "org.gnu.gdb.riscv.fpu",
181 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" }, true },
182 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" }, true },
183 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" }, true },
184 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" }, true },
185 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" }, true },
186 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" }, true },
187 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" }, true },
188 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" }, true },
189 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8" }, true },
190 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" }, true },
191 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" }, true },
192 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" }, true },
193 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" }, true },
194 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" }, true },
195 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" }, true },
196 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" }, true },
197 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" }, true },
198 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" }, true },
199 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" }, true },
200 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" }, true },
201 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" }, true },
202 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" }, true },
203 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" }, true },
204 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" }, true },
205 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" }, true },
206 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" }, true },
207 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" }, true },
208 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" }, true },
209 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" }, true },
210 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" }, true },
211 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" }, true },
212 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" }, true },
214 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags" }, true },
215 { RISCV_CSR_FRM_REGNUM
, { "frm" }, true },
216 { RISCV_CSR_FCSR_REGNUM
, { "fcsr" }, true },
221 /* Set of virtual registers. These are not physical registers on the
222 hardware, but might be available from the target. These are not pseudo
223 registers, reading these really does result in a register read from the
224 target, it is just that there might not be a physical register backing
227 static const struct riscv_register_feature riscv_virtual_feature
=
229 "org.gnu.gdb.riscv.virtual",
231 { RISCV_PRIV_REGNUM
, { "priv" }, false }
235 /* Feature set for CSRs. This set is NOT constant as the register names
236 list for each register is not complete. The aliases are computed
237 during RISCV_CREATE_CSR_ALIASES. */
239 static struct riscv_register_feature riscv_csr_feature
=
241 "org.gnu.gdb.riscv.csr",
243 #define DECLARE_CSR(NAME,VALUE,CLASS) \
244 { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
245 #include "opcode/riscv-opc.h"
250 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
251 to the name list for each register. */
254 riscv_create_csr_aliases ()
256 for (auto ®
: riscv_csr_feature
.registers
)
258 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
259 const char *alias
= xstrprintf ("csr%d", csr_num
);
260 reg
.names
.push_back (alias
);
264 /* Controls whether we place compressed breakpoints or not. When in auto
265 mode GDB tries to determine if the target supports compressed
266 breakpoints, and uses them if it does. */
268 static enum auto_boolean use_compressed_breakpoints
;
270 /* The show callback for 'show riscv use-compressed-breakpoints'. */
273 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
274 struct cmd_list_element
*c
,
277 fprintf_filtered (file
,
278 _("Debugger's use of compressed breakpoints is set "
282 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
284 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
285 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
287 /* The show callback for the 'show riscv' prefix command. */
290 show_riscv_command (const char *args
, int from_tty
)
292 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
295 /* The set callback for the 'set riscv' prefix command. */
298 set_riscv_command (const char *args
, int from_tty
)
301 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
302 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
305 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
307 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
308 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
310 /* The show callback for the 'show debug riscv' prefix command. */
313 show_debug_riscv_command (const char *args
, int from_tty
)
315 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
318 /* The set callback for the 'set debug riscv' prefix command. */
321 set_debug_riscv_command (const char *args
, int from_tty
)
324 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
325 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
328 /* The show callback for all 'show debug riscv VARNAME' variables. */
331 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
332 struct cmd_list_element
*c
,
335 fprintf_filtered (file
,
336 _("RiscV debug variable `%s' is set to: %s\n"),
340 /* When this is set to non-zero debugging information about breakpoint
341 kinds will be printed. */
343 static unsigned int riscv_debug_breakpoints
= 0;
345 /* When this is set to non-zero debugging information about inferior calls
348 static unsigned int riscv_debug_infcall
= 0;
350 /* When this is set to non-zero debugging information about stack unwinding
353 static unsigned int riscv_debug_unwinder
= 0;
355 /* When this is set to non-zero debugging information about gdbarch
356 initialisation will be printed. */
358 static unsigned int riscv_debug_gdbarch
= 0;
360 /* See riscv-tdep.h. */
363 riscv_isa_xlen (struct gdbarch
*gdbarch
)
365 return gdbarch_tdep (gdbarch
)->isa_features
.xlen
;
368 /* See riscv-tdep.h. */
371 riscv_abi_xlen (struct gdbarch
*gdbarch
)
373 return gdbarch_tdep (gdbarch
)->abi_features
.xlen
;
376 /* See riscv-tdep.h. */
379 riscv_isa_flen (struct gdbarch
*gdbarch
)
381 return gdbarch_tdep (gdbarch
)->isa_features
.flen
;
384 /* See riscv-tdep.h. */
387 riscv_abi_flen (struct gdbarch
*gdbarch
)
389 return gdbarch_tdep (gdbarch
)->abi_features
.flen
;
392 /* Return true if the target for GDBARCH has floating point hardware. */
395 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
397 return (riscv_isa_flen (gdbarch
) > 0);
400 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
403 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
405 return gdbarch_tdep (gdbarch
)->abi_features
.flen
> 0;
408 /* Return true if REGNO is a floating pointer register. */
411 riscv_is_fp_regno_p (int regno
)
413 return (regno
>= RISCV_FIRST_FP_REGNUM
414 && regno
<= RISCV_LAST_FP_REGNUM
);
417 /* Implement the breakpoint_kind_from_pc gdbarch method. */
420 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
422 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
424 bool unaligned_p
= false;
427 /* Some targets don't support unaligned reads. The address can only
428 be unaligned if the C extension is supported. So it is safe to
429 use a compressed breakpoint in this case. */
434 /* Read the opcode byte to determine the instruction length. If
435 the read fails this may be because we tried to set the
436 breakpoint at an invalid address, in this case we provide a
437 fake result which will give a breakpoint length of 4.
438 Hopefully when we try to actually insert the breakpoint we
439 will see a failure then too which will be reported to the
441 if (target_read_code (*pcptr
, buf
, 1) == -1)
443 read_code (*pcptr
, buf
, 1);
446 if (riscv_debug_breakpoints
)
448 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
449 ? "C.EBREAK" : "EBREAK");
451 fprintf_unfiltered (gdb_stdlog
, "Using %s for breakpoint at %s ",
452 bp
, paddress (gdbarch
, *pcptr
));
454 fprintf_unfiltered (gdb_stdlog
, "(unaligned address)\n");
456 fprintf_unfiltered (gdb_stdlog
, "(instruction length %d)\n",
457 riscv_insn_length (buf
[0]));
459 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
464 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
470 /* Implement the sw_breakpoint_from_kind gdbarch method. */
472 static const gdb_byte
*
473 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
475 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
476 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
486 gdb_assert_not_reached (_("unhandled breakpoint kind"));
490 /* Callback function for user_reg_add. */
492 static struct value
*
493 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
495 const int *reg_p
= (const int *) baton
;
496 return value_of_register (*reg_p
, frame
);
499 /* Implement the register_name gdbarch method. This is used instead of
500 the function supplied by calling TDESC_USE_REGISTERS so that we can
501 ensure the preferred names are offered. */
504 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
506 /* Lookup the name through the target description. If we get back NULL
507 then this is an unknown register. If we do get a name back then we
508 look up the registers preferred name below. */
509 const char *name
= tdesc_register_name (gdbarch
, regnum
);
510 if (name
== NULL
|| name
[0] == '\0')
513 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
515 gdb_assert (regnum
< riscv_xreg_feature
.registers
.size ());
516 return riscv_xreg_feature
.registers
[regnum
].names
[0];
519 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
521 if (riscv_has_fp_regs (gdbarch
))
523 regnum
-= RISCV_FIRST_FP_REGNUM
;
524 gdb_assert (regnum
< riscv_freg_feature
.registers
.size ());
525 return riscv_freg_feature
.registers
[regnum
].names
[0];
531 /* Check that there's no gap between the set of registers handled above,
532 and the set of registers handled next. */
533 gdb_assert ((RISCV_LAST_FP_REGNUM
+ 1) == RISCV_FIRST_CSR_REGNUM
);
535 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
537 #define DECLARE_CSR(NAME,VALUE,CLASS) \
538 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
542 #include "opcode/riscv-opc.h"
547 if (regnum
== RISCV_PRIV_REGNUM
)
550 /* It is possible that that the target provides some registers that GDB
551 is unaware of, in that case just return the NAME from the target
556 /* Construct a type for 64-bit FP registers. */
559 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
561 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
563 if (tdep
->riscv_fpreg_d_type
== nullptr)
565 const struct builtin_type
*bt
= builtin_type (gdbarch
);
567 /* The type we're building is this: */
569 union __gdb_builtin_type_fpreg_d
578 t
= arch_composite_type (gdbarch
,
579 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
580 append_composite_type_field (t
, "float", bt
->builtin_float
);
581 append_composite_type_field (t
, "double", bt
->builtin_double
);
583 TYPE_NAME (t
) = "builtin_type_fpreg_d";
584 tdep
->riscv_fpreg_d_type
= t
;
587 return tdep
->riscv_fpreg_d_type
;
590 /* Implement the register_type gdbarch method. This is installed as an
591 for the override setup by TDESC_USE_REGISTERS, for most registers we
592 delegate the type choice to the target description, but for a few
593 registers we try to improve the types if the target description has
594 taken a simplistic approach. */
597 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
599 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
600 int xlen
= riscv_isa_xlen (gdbarch
);
602 /* We want to perform some specific type "fixes" in cases where we feel
603 that we really can do better than the target description. For all
604 other cases we just return what the target description says. */
605 if (riscv_is_fp_regno_p (regnum
))
607 /* This spots the case for RV64 where the double is defined as
608 either 'ieee_double' or 'float' (which is the generic name that
609 converts to 'double' on 64-bit). In these cases its better to
610 present the registers using a union type. */
611 int flen
= riscv_isa_flen (gdbarch
);
613 && TYPE_CODE (type
) == TYPE_CODE_FLT
614 && TYPE_LENGTH (type
) == flen
615 && (strcmp (TYPE_NAME (type
), "builtin_type_ieee_double") == 0
616 || strcmp (TYPE_NAME (type
), "double") == 0))
617 type
= riscv_fpreg_d_type (gdbarch
);
620 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
621 || regnum
== RISCV_RA_REGNUM
622 || regnum
== RISCV_FP_REGNUM
623 || regnum
== RISCV_SP_REGNUM
624 || regnum
== RISCV_GP_REGNUM
625 || regnum
== RISCV_TP_REGNUM
)
626 && TYPE_CODE (type
) == TYPE_CODE_INT
627 && TYPE_LENGTH (type
) == xlen
)
629 /* This spots the case where some interesting registers are defined
630 as simple integers of the expected size, we force these registers
631 to be pointers as we believe that is more useful. */
632 if (regnum
== gdbarch_pc_regnum (gdbarch
)
633 || regnum
== RISCV_RA_REGNUM
)
634 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
635 else if (regnum
== RISCV_FP_REGNUM
636 || regnum
== RISCV_SP_REGNUM
637 || regnum
== RISCV_GP_REGNUM
638 || regnum
== RISCV_TP_REGNUM
)
639 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
645 /* Helper for riscv_print_registers_info, prints info for a single register
649 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
650 struct ui_file
*file
,
651 struct frame_info
*frame
,
654 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
656 struct type
*regtype
;
657 int print_raw_format
;
658 enum tab_stops
{ value_column_1
= 15 };
660 fputs_filtered (name
, file
);
661 print_spaces_filtered (value_column_1
- strlen (name
), file
);
665 val
= value_of_register (regnum
, frame
);
666 regtype
= value_type (val
);
668 catch (const gdb_exception_error
&ex
)
670 /* Handle failure to read a register without interrupting the entire
671 'info registers' flow. */
672 fprintf_filtered (file
, "%s\n", ex
.what ());
676 print_raw_format
= (value_entirely_available (val
)
677 && !value_optimized_out (val
));
679 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
680 || (TYPE_CODE (regtype
) == TYPE_CODE_UNION
681 && TYPE_NFIELDS (regtype
) == 2
682 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 0)) == TYPE_CODE_FLT
683 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 1)) == TYPE_CODE_FLT
)
684 || (TYPE_CODE (regtype
) == TYPE_CODE_UNION
685 && TYPE_NFIELDS (regtype
) == 3
686 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 0)) == TYPE_CODE_FLT
687 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 1)) == TYPE_CODE_FLT
688 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 2)) == TYPE_CODE_FLT
))
690 struct value_print_options opts
;
691 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
692 enum bfd_endian byte_order
= type_byte_order (regtype
);
694 get_user_print_options (&opts
);
697 common_val_print (val
, file
, 0, &opts
, current_language
);
699 if (print_raw_format
)
701 fprintf_filtered (file
, "\t(raw ");
702 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
704 fprintf_filtered (file
, ")");
709 struct value_print_options opts
;
711 /* Print the register in hex. */
712 get_formatted_print_options (&opts
, 'x');
714 common_val_print (val
, file
, 0, &opts
, current_language
);
716 if (print_raw_format
)
718 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
721 int size
= register_size (gdbarch
, regnum
);
724 /* The SD field is always in the upper bit of MSTATUS, regardless
725 of the number of bits in MSTATUS. */
726 d
= value_as_long (val
);
728 fprintf_filtered (file
,
729 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
730 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
731 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
732 (int) ((d
>> (xlen
- 1)) & 0x1),
733 (int) ((d
>> 24) & 0x1f),
734 (int) ((d
>> 19) & 0x1),
735 (int) ((d
>> 18) & 0x1),
736 (int) ((d
>> 17) & 0x1),
737 (int) ((d
>> 15) & 0x3),
738 (int) ((d
>> 13) & 0x3),
739 (int) ((d
>> 11) & 0x3),
740 (int) ((d
>> 9) & 0x3),
741 (int) ((d
>> 8) & 0x1),
742 (int) ((d
>> 7) & 0x1),
743 (int) ((d
>> 6) & 0x1),
744 (int) ((d
>> 5) & 0x1),
745 (int) ((d
>> 4) & 0x1),
746 (int) ((d
>> 3) & 0x1),
747 (int) ((d
>> 2) & 0x1),
748 (int) ((d
>> 1) & 0x1),
749 (int) ((d
>> 0) & 0x1));
751 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
756 int size
= register_size (gdbarch
, regnum
);
758 /* The MXL field is always in the upper two bits of MISA,
759 regardless of the number of bits in MISA. Mask out other
760 bits to ensure we have a positive value. */
761 d
= value_as_long (val
);
762 base
= (d
>> ((size
* 8) - 2)) & 0x3;
765 for (; base
> 0; base
--)
767 fprintf_filtered (file
, "\tRV%d", xlen
);
769 for (i
= 0; i
< 26; i
++)
772 fprintf_filtered (file
, "%c", 'A' + i
);
775 else if (regnum
== RISCV_CSR_FCSR_REGNUM
776 || regnum
== RISCV_CSR_FFLAGS_REGNUM
777 || regnum
== RISCV_CSR_FRM_REGNUM
)
781 d
= value_as_long (val
);
783 fprintf_filtered (file
, "\t");
784 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
785 fprintf_filtered (file
,
786 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
787 (int) ((d
>> 5) & 0x7),
788 (int) ((d
>> 4) & 0x1),
789 (int) ((d
>> 3) & 0x1),
790 (int) ((d
>> 2) & 0x1),
791 (int) ((d
>> 1) & 0x1),
792 (int) ((d
>> 0) & 0x1));
794 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
796 static const char * const sfrm
[] =
798 "RNE (round to nearest; ties to even)",
799 "RTZ (Round towards zero)",
800 "RDN (Round down towards -INF)",
801 "RUP (Round up towards +INF)",
802 "RMM (Round to nearest; ties to max magnitude)",
805 "dynamic rounding mode",
807 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
808 ? (d
>> 5) : d
) & 0x3;
810 fprintf_filtered (file
, "%sFRM:%i [%s]",
811 (regnum
== RISCV_CSR_FCSR_REGNUM
816 else if (regnum
== RISCV_PRIV_REGNUM
)
821 d
= value_as_long (val
);
826 static const char * const sprv
[] =
833 fprintf_filtered (file
, "\tprv:%d [%s]",
837 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
841 /* If not a vector register, print it also according to its
843 if (TYPE_VECTOR (regtype
) == 0)
845 get_user_print_options (&opts
);
847 fprintf_filtered (file
, "\t");
848 common_val_print (val
, file
, 0, &opts
, current_language
);
853 fprintf_filtered (file
, "\n");
856 /* Return true if REGNUM is a valid CSR register. The CSR register space
857 is sparsely populated, so not every number is a named CSR. */
860 riscv_is_regnum_a_named_csr (int regnum
)
862 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
863 && regnum
<= RISCV_LAST_CSR_REGNUM
);
867 #define DECLARE_CSR(name, num, class) case RISCV_ ## num ## _REGNUM:
868 #include "opcode/riscv-opc.h"
877 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
881 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
882 struct reggroup
*reggroup
)
884 /* Used by 'info registers' and 'info registers <groupname>'. */
886 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
887 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
890 if (regnum
> RISCV_LAST_REGNUM
)
892 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
896 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
899 if (reggroup
== all_reggroup
)
901 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
903 if (riscv_is_regnum_a_named_csr (regnum
))
907 else if (reggroup
== float_reggroup
)
908 return (riscv_is_fp_regno_p (regnum
)
909 || regnum
== RISCV_CSR_FCSR_REGNUM
910 || regnum
== RISCV_CSR_FFLAGS_REGNUM
911 || regnum
== RISCV_CSR_FRM_REGNUM
);
912 else if (reggroup
== general_reggroup
)
913 return regnum
< RISCV_FIRST_FP_REGNUM
;
914 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
916 if (riscv_has_fp_regs (gdbarch
))
917 return (regnum
<= RISCV_LAST_FP_REGNUM
918 || regnum
== RISCV_CSR_FCSR_REGNUM
919 || regnum
== RISCV_CSR_FFLAGS_REGNUM
920 || regnum
== RISCV_CSR_FRM_REGNUM
);
922 return regnum
< RISCV_FIRST_FP_REGNUM
;
924 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
926 if (regnum
== RISCV_PRIV_REGNUM
)
928 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
930 if (riscv_is_regnum_a_named_csr (regnum
))
934 else if (reggroup
== vector_reggroup
)
940 /* Implement the print_registers_info gdbarch method. This is used by
941 'info registers' and 'info all-registers'. */
944 riscv_print_registers_info (struct gdbarch
*gdbarch
,
945 struct ui_file
*file
,
946 struct frame_info
*frame
,
947 int regnum
, int print_all
)
951 /* Print one specified register. */
952 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
953 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
954 error (_("Not a valid register for the current processor type"));
955 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
959 struct reggroup
*reggroup
;
962 reggroup
= all_reggroup
;
964 reggroup
= general_reggroup
;
966 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
968 /* Zero never changes, so might as well hide by default. */
969 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
972 /* Registers with no name are not valid on this ISA. */
973 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
974 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
977 /* Is the register in the group we're interested in? */
978 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
981 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
986 /* Class that handles one decoded RiscV instruction. */
992 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
995 /* Unknown value is used at initialisation time. */
998 /* These instructions are all the ones we are interested in during the
1008 /* These are needed for software breakpoint support. */
1017 /* These are needed for stepping over atomic sequences. */
1021 /* Other instructions are not interesting during the prologue scan, and
1036 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1038 /* Get the length of the instruction in bytes. */
1040 { return m_length
; }
1042 /* Get the opcode for this instruction. */
1043 enum opcode
opcode () const
1044 { return m_opcode
; }
1046 /* Get destination register field for this instruction. This is only
1047 valid if the OPCODE implies there is such a field for this
1052 /* Get the RS1 register field for this instruction. This is only valid
1053 if the OPCODE implies there is such a field for this instruction. */
1057 /* Get the RS2 register field for this instruction. This is only valid
1058 if the OPCODE implies there is such a field for this instruction. */
1062 /* Get the immediate for this instruction in signed form. This is only
1063 valid if the OPCODE implies there is such a field for this
1065 int imm_signed () const
1070 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1071 int decode_register_index (unsigned long opcode
, int offset
)
1073 return (opcode
>> offset
) & 0x1F;
1076 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1077 int decode_register_index_short (unsigned long opcode
, int offset
)
1079 return ((opcode
>> offset
) & 0x7) + 8;
1082 /* Helper for DECODE, decode 32-bit R-type instruction. */
1083 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1086 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1087 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1088 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1091 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1092 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1095 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1096 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1099 /* Helper for DECODE, decode 32-bit I-type instruction. */
1100 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1103 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1104 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1105 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1108 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1109 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1112 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1113 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
1116 /* Helper for DECODE, decode 32-bit S-type instruction. */
1117 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1120 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1121 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1122 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1125 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1126 encoding is different for each CS format instruction, so extracting
1127 the immediate is left up to the caller, who should pass the extracted
1128 immediate value through in IMM. */
1129 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1133 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1134 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1137 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1138 encoding is different for each CSS format instruction, so extracting
1139 the immediate is left up to the caller, who should pass the extracted
1140 immediate value through in IMM. */
1141 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1145 m_rs1
= RISCV_SP_REGNUM
;
1146 /* Not a compressed register number in this case. */
1147 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1150 /* Helper for DECODE, decode 32-bit U-type instruction. */
1151 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1154 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1155 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1158 /* Helper for DECODE, decode 32-bit J-type instruction. */
1159 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1162 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1163 m_imm
.s
= EXTRACT_UJTYPE_IMM (ival
);
1166 /* Helper for DECODE, decode 32-bit J-type instruction. */
1167 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1170 m_imm
.s
= EXTRACT_RVC_J_IMM (ival
);
1173 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1176 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1177 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1178 m_imm
.s
= EXTRACT_SBTYPE_IMM (ival
);
1181 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1184 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1185 m_imm
.s
= EXTRACT_RVC_B_IMM (ival
);
1188 /* Fetch instruction from target memory at ADDR, return the content of
1189 the instruction, and update LEN with the instruction length. */
1190 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1191 CORE_ADDR addr
, int *len
);
1193 /* The length of the instruction in bytes. Should be 2 or 4. */
1196 /* The instruction opcode. */
1197 enum opcode m_opcode
;
1199 /* The three possible registers an instruction might reference. Not
1200 every instruction fills in all of these registers. Which fields are
1201 valid depends on the opcode. The naming of these fields matches the
1202 naming in the riscv isa manual. */
1207 /* Possible instruction immediate. This is only valid if the instruction
1208 format contains an immediate, not all instruction, whether this is
1209 valid depends on the opcode. Despite only having one format for now
1210 the immediate is packed into a union, later instructions might require
1211 an unsigned formatted immediate, having the union in place now will
1212 reduce the need for code churn later. */
1213 union riscv_insn_immediate
1215 riscv_insn_immediate ()
1225 /* Fetch instruction from target memory at ADDR, return the content of the
1226 instruction, and update LEN with the instruction length. */
1229 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1230 CORE_ADDR addr
, int *len
)
1232 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1234 int instlen
, status
;
1236 /* All insns are at least 16 bits. */
1237 status
= target_read_memory (addr
, buf
, 2);
1239 memory_error (TARGET_XFER_E_IO
, addr
);
1241 /* If we need more, grab it now. */
1242 instlen
= riscv_insn_length (buf
[0]);
1243 gdb_assert (instlen
<= sizeof (buf
));
1248 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1250 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1253 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1256 /* Fetch from target memory an instruction at PC and decode it. This can
1257 throw an error if the memory access fails, callers are responsible for
1258 handling this error if that is appropriate. */
1261 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1265 /* Fetch the instruction, and the instructions length. */
1266 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1270 if (is_add_insn (ival
))
1271 decode_r_type_insn (ADD
, ival
);
1272 else if (is_addw_insn (ival
))
1273 decode_r_type_insn (ADDW
, ival
);
1274 else if (is_addi_insn (ival
))
1275 decode_i_type_insn (ADDI
, ival
);
1276 else if (is_addiw_insn (ival
))
1277 decode_i_type_insn (ADDIW
, ival
);
1278 else if (is_auipc_insn (ival
))
1279 decode_u_type_insn (AUIPC
, ival
);
1280 else if (is_lui_insn (ival
))
1281 decode_u_type_insn (LUI
, ival
);
1282 else if (is_sd_insn (ival
))
1283 decode_s_type_insn (SD
, ival
);
1284 else if (is_sw_insn (ival
))
1285 decode_s_type_insn (SW
, ival
);
1286 else if (is_jal_insn (ival
))
1287 decode_j_type_insn (JAL
, ival
);
1288 else if (is_jalr_insn (ival
))
1289 decode_i_type_insn (JALR
, ival
);
1290 else if (is_beq_insn (ival
))
1291 decode_b_type_insn (BEQ
, ival
);
1292 else if (is_bne_insn (ival
))
1293 decode_b_type_insn (BNE
, ival
);
1294 else if (is_blt_insn (ival
))
1295 decode_b_type_insn (BLT
, ival
);
1296 else if (is_bge_insn (ival
))
1297 decode_b_type_insn (BGE
, ival
);
1298 else if (is_bltu_insn (ival
))
1299 decode_b_type_insn (BLTU
, ival
);
1300 else if (is_bgeu_insn (ival
))
1301 decode_b_type_insn (BGEU
, ival
);
1302 else if (is_lr_w_insn (ival
))
1303 decode_r_type_insn (LR
, ival
);
1304 else if (is_lr_d_insn (ival
))
1305 decode_r_type_insn (LR
, ival
);
1306 else if (is_sc_w_insn (ival
))
1307 decode_r_type_insn (SC
, ival
);
1308 else if (is_sc_d_insn (ival
))
1309 decode_r_type_insn (SC
, ival
);
1311 /* None of the other fields are valid in this case. */
1314 else if (m_length
== 2)
1316 int xlen
= riscv_isa_xlen (gdbarch
);
1318 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1319 C_JALR. So must try to match C_JALR first as it has more bits in
1321 if (is_c_jalr_insn (ival
))
1322 decode_cr_type_insn (JALR
, ival
);
1323 else if (is_c_add_insn (ival
))
1324 decode_cr_type_insn (ADD
, ival
);
1325 /* C_ADDW is RV64 and RV128 only. */
1326 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1327 decode_cr_type_insn (ADDW
, ival
);
1328 else if (is_c_addi_insn (ival
))
1329 decode_ci_type_insn (ADDI
, ival
);
1330 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1331 only and C_JAL is RV32 only. */
1332 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1333 decode_ci_type_insn (ADDIW
, ival
);
1334 else if (xlen
== 4 && is_c_jal_insn (ival
))
1335 decode_cj_type_insn (JAL
, ival
);
1336 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1337 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1339 else if (is_c_addi16sp_insn (ival
))
1342 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1343 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1345 else if (is_c_addi4spn_insn (ival
))
1348 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1349 m_rs1
= RISCV_SP_REGNUM
;
1350 m_imm
.s
= EXTRACT_RVC_ADDI4SPN_IMM (ival
);
1352 else if (is_c_lui_insn (ival
))
1355 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1356 m_imm
.s
= EXTRACT_RVC_LUI_IMM (ival
);
1358 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1359 and C_FSW is RV32 only. */
1360 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1361 decode_cs_type_insn (SD
, ival
, EXTRACT_RVC_LD_IMM (ival
));
1362 else if (is_c_sw_insn (ival
))
1363 decode_cs_type_insn (SW
, ival
, EXTRACT_RVC_LW_IMM (ival
));
1364 else if (is_c_swsp_insn (ival
))
1365 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SWSP_IMM (ival
));
1366 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1367 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SDSP_IMM (ival
));
1368 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1369 So must try to match C_JR first as it ahs more bits in mask. */
1370 else if (is_c_jr_insn (ival
))
1371 decode_cr_type_insn (JALR
, ival
);
1372 else if (is_c_j_insn (ival
))
1373 decode_cj_type_insn (JAL
, ival
);
1374 else if (is_c_beqz_insn (ival
))
1375 decode_cb_type_insn (BEQ
, ival
);
1376 else if (is_c_bnez_insn (ival
))
1377 decode_cb_type_insn (BNE
, ival
);
1379 /* None of the other fields of INSN are valid in this case. */
1384 /* This must be a 6 or 8 byte instruction, we don't currently decode
1385 any of these, so just ignore it. */
1386 gdb_assert (m_length
== 6 || m_length
== 8);
1391 /* The prologue scanner. This is currently only used for skipping the
1392 prologue of a function when the DWARF information is not sufficient.
1393 However, it is written with filling of the frame cache in mind, which
1394 is why different groups of stack setup instructions are split apart
1395 during the core of the inner loop. In the future, the intention is to
1396 extend this function to fully support building up a frame cache that
1397 can unwind register values when there is no DWARF information. */
1400 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1401 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1402 struct riscv_unwind_cache
*cache
)
1404 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1405 CORE_ADDR end_prologue_addr
= 0;
1407 /* Find an upper limit on the function prologue using the debug
1408 information. If the debug information could not be used to provide
1409 that bound, then use an arbitrary large number as the upper bound. */
1410 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1411 if (after_prologue_pc
== 0)
1412 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1413 if (after_prologue_pc
< end_pc
)
1414 end_pc
= after_prologue_pc
;
1416 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1417 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1418 regs
[regno
] = pv_register (regno
, 0);
1419 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1421 if (riscv_debug_unwinder
)
1424 "Prologue scan for function starting at %s (limit %s)\n",
1425 core_addr_to_string (start_pc
),
1426 core_addr_to_string (end_pc
));
1428 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1430 struct riscv_insn insn
;
1432 /* Decode the current instruction, and decide where the next
1433 instruction lives based on the size of this instruction. */
1434 insn
.decode (gdbarch
, cur_pc
);
1435 gdb_assert (insn
.length () > 0);
1436 next_pc
= cur_pc
+ insn
.length ();
1438 /* Look for common stack adjustment insns. */
1439 if ((insn
.opcode () == riscv_insn::ADDI
1440 || insn
.opcode () == riscv_insn::ADDIW
)
1441 && insn
.rd () == RISCV_SP_REGNUM
1442 && insn
.rs1 () == RISCV_SP_REGNUM
)
1444 /* Handle: addi sp, sp, -i
1445 or: addiw sp, sp, -i */
1446 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1447 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1449 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1451 else if ((insn
.opcode () == riscv_insn::SW
1452 || insn
.opcode () == riscv_insn::SD
)
1453 && (insn
.rs1 () == RISCV_SP_REGNUM
1454 || insn
.rs1 () == RISCV_FP_REGNUM
))
1456 /* Handle: sw reg, offset(sp)
1457 or: sd reg, offset(sp)
1458 or: sw reg, offset(s0)
1459 or: sd reg, offset(s0) */
1460 /* Instruction storing a register onto the stack. */
1461 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1462 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1463 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
1464 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
1467 else if (insn
.opcode () == riscv_insn::ADDI
1468 && insn
.rd () == RISCV_FP_REGNUM
1469 && insn
.rs1 () == RISCV_SP_REGNUM
)
1471 /* Handle: addi s0, sp, size */
1472 /* Instructions setting up the frame pointer. */
1473 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1474 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1476 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1478 else if ((insn
.opcode () == riscv_insn::ADD
1479 || insn
.opcode () == riscv_insn::ADDW
)
1480 && insn
.rd () == RISCV_FP_REGNUM
1481 && insn
.rs1 () == RISCV_SP_REGNUM
1482 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1484 /* Handle: add s0, sp, 0
1485 or: addw s0, sp, 0 */
1486 /* Instructions setting up the frame pointer. */
1487 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1488 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1489 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
1491 else if ((insn
.opcode () == riscv_insn::ADDI
1492 && insn
.rd () == RISCV_ZERO_REGNUM
1493 && insn
.rs1 () == RISCV_ZERO_REGNUM
1494 && insn
.imm_signed () == 0))
1496 /* Handle: add x0, x0, 0 (NOP) */
1498 else if (insn
.opcode () == riscv_insn::AUIPC
)
1500 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1501 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
1503 else if (insn
.opcode () == riscv_insn::LUI
)
1505 /* Handle: lui REG, n
1506 Where REG is not gp register. */
1507 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1508 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
1510 else if (insn
.opcode () == riscv_insn::ADDI
)
1512 /* Handle: addi REG1, REG2, IMM */
1513 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1514 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1516 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1518 else if (insn
.opcode () == riscv_insn::ADD
)
1520 /* Handle: addi REG1, REG2, IMM */
1521 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1522 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1523 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1524 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
1528 end_prologue_addr
= cur_pc
;
1533 if (end_prologue_addr
== 0)
1534 end_prologue_addr
= cur_pc
;
1536 if (riscv_debug_unwinder
)
1537 fprintf_unfiltered (gdb_stdlog
, "End of prologue at %s\n",
1538 core_addr_to_string (end_prologue_addr
));
1542 /* Figure out if it is a frame pointer or just a stack pointer. Also
1543 the offset held in the pv_t is from the original register value to
1544 the current value, which for a grows down stack means a negative
1545 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1546 from the current value to the original value. */
1547 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
1549 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
1550 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
1554 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
1555 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
1558 /* Assign offset from old SP to all saved registers. As we don't
1559 have the previous value for the frame base register at this
1560 point, we store the offset as the address in the trad_frame, and
1561 then convert this to an actual address later. */
1562 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
1565 if (stack
.find_reg (gdbarch
, i
, &offset
))
1567 if (riscv_debug_unwinder
)
1569 /* Display OFFSET as a signed value, the offsets are from
1570 the frame base address to the registers location on
1571 the stack, with a descending stack this means the
1572 offsets are always negative. */
1573 fprintf_unfiltered (gdb_stdlog
,
1574 "Register $%s at stack offset %s\n",
1575 gdbarch_register_name (gdbarch
, i
),
1576 plongest ((LONGEST
) offset
));
1578 trad_frame_set_addr (cache
->regs
, i
, offset
);
1583 return end_prologue_addr
;
1586 /* Implement the riscv_skip_prologue gdbarch method. */
1589 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1591 CORE_ADDR func_addr
;
1593 /* See if we can determine the end of the prologue via the symbol
1594 table. If so, then return either PC, or the PC after the
1595 prologue, whichever is greater. */
1596 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1598 CORE_ADDR post_prologue_pc
1599 = skip_prologue_using_sal (gdbarch
, func_addr
);
1601 if (post_prologue_pc
!= 0)
1602 return std::max (pc
, post_prologue_pc
);
1605 /* Can't determine prologue from the symbol table, need to examine
1606 instructions. Pass -1 for the end address to indicate the prologue
1607 scanner can scan as far as it needs to find the end of the prologue. */
1608 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
1611 /* Implement the gdbarch push dummy code callback. */
1614 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1615 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1616 struct type
*value_type
, CORE_ADDR
*real_pc
,
1617 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1619 /* A nop instruction is 'add x0, x0, 0'. */
1620 static const gdb_byte nop_insn
[] = { 0x13, 0x00, 0x00, 0x00 };
1622 /* Allocate space for a breakpoint, and keep the stack correctly
1623 aligned. The space allocated here must be at least big enough to
1624 accommodate the NOP_INSN defined above. */
1629 /* When we insert a breakpoint we select whether to use a compressed
1630 breakpoint or not based on the existing contents of the memory.
1632 If the breakpoint is being placed onto the stack as part of setting up
1633 for an inferior call from GDB, then the existing stack contents may
1634 randomly appear to be a compressed instruction, causing GDB to insert
1635 a compressed breakpoint. If this happens on a target that does not
1636 support compressed instructions then this could cause problems.
1638 To prevent this issue we write an uncompressed nop onto the stack at
1639 the location where the breakpoint will be inserted. In this way we
1640 ensure that we always use an uncompressed breakpoint, which should
1641 work on all targets.
1643 We call TARGET_WRITE_MEMORY here so that if the write fails we don't
1644 throw an exception. Instead we ignore the error and move on. The
1645 assumption is that either GDB will error later when actually trying to
1646 insert a software breakpoint, or GDB will use hardware breakpoints and
1647 there will be no need to write to memory later. */
1648 int status
= target_write_memory (*bp_addr
, nop_insn
, sizeof (nop_insn
));
1650 if (riscv_debug_breakpoints
|| riscv_debug_infcall
)
1651 fprintf_unfiltered (gdb_stdlog
,
1652 "Writing %s-byte nop instruction to %s: %s\n",
1653 plongest (sizeof (nop_insn
)),
1654 paddress (gdbarch
, *bp_addr
),
1655 (status
== 0 ? "success" : "failed"));
1660 /* Implement the gdbarch type alignment method, overrides the generic
1661 alignment algorithm for anything that is RISC-V specific. */
1664 riscv_type_align (gdbarch
*gdbarch
, type
*type
)
1666 type
= check_typedef (type
);
1667 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
))
1668 return std::min (TYPE_LENGTH (type
), (ULONGEST
) BIGGEST_ALIGNMENT
);
1670 /* Anything else will be aligned by the generic code. */
1674 /* Holds information about a single argument either being passed to an
1675 inferior function, or returned from an inferior function. This includes
1676 information about the size, type, etc of the argument, and also
1677 information about how the argument will be passed (or returned). */
1679 struct riscv_arg_info
1681 /* Contents of the argument. */
1682 const gdb_byte
*contents
;
1684 /* Length of argument. */
1687 /* Alignment required for an argument of this type. */
1690 /* The type for this argument. */
1693 /* Each argument can have either 1 or 2 locations assigned to it. Each
1694 location describes where part of the argument will be placed. The
1695 second location is valid based on the LOC_TYPE and C_LENGTH fields
1696 of the first location (which is always valid). */
1699 /* What type of location this is. */
1702 /* Argument passed in a register. */
1705 /* Argument passed as an on stack argument. */
1708 /* Argument passed by reference. The second location is always
1709 valid for a BY_REF argument, and describes where the address
1710 of the BY_REF argument should be placed. */
1714 /* Information that depends on the location type. */
1717 /* Which register number to use. */
1720 /* The offset into the stack region. */
1724 /* The length of contents covered by this location. If this is less
1725 than the total length of the argument, then the second location
1726 will be valid, and will describe where the rest of the argument
1730 /* The offset within CONTENTS for this part of the argument. Will
1731 always be 0 for the first part. For the second part of the
1732 argument, this might be the C_LENGTH value of the first part,
1733 however, if we are passing a structure in two registers, and there's
1734 is padding between the first and second field, then this offset
1735 might be greater than the length of the first argument part. When
1736 the second argument location is not holding part of the argument
1737 value, but is instead holding the address of a reference argument,
1738 then this offset will be set to 0. */
1742 /* TRUE if this is an unnamed argument. */
1746 /* Information about a set of registers being used for passing arguments as
1747 part of a function call. The register set must be numerically
1748 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1749 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1751 struct riscv_arg_reg
1753 riscv_arg_reg (int first
, int last
)
1754 : next_regnum (first
),
1760 /* The GDB register number to use in this set. */
1763 /* The last GDB register number to use in this set. */
1767 /* Arguments can be passed as on stack arguments, or by reference. The
1768 on stack arguments must be in a continuous region starting from $sp,
1769 while the by reference arguments can be anywhere, but we'll put them
1770 on the stack after (at higher address) the on stack arguments.
1772 This might not be the right approach to take. The ABI is clear that
1773 an argument passed by reference can be modified by the callee, which
1774 us placing the argument (temporarily) onto the stack will not achieve
1775 (changes will be lost). There's also the possibility that very large
1776 arguments could overflow the stack.
1778 This struct is used to track offset into these two areas for where
1779 arguments are to be placed. */
1780 struct riscv_memory_offsets
1782 riscv_memory_offsets ()
1789 /* Offset into on stack argument area. */
1792 /* Offset into the pass by reference area. */
1796 /* Holds information about where arguments to a call will be placed. This
1797 is updated as arguments are added onto the call, and can be used to
1798 figure out where the next argument should be placed. */
1800 struct riscv_call_info
1802 riscv_call_info (struct gdbarch
*gdbarch
)
1803 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1804 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1806 xlen
= riscv_abi_xlen (gdbarch
);
1807 flen
= riscv_abi_flen (gdbarch
);
1809 /* Disable use of floating point registers if needed. */
1810 if (!riscv_has_fp_abi (gdbarch
))
1811 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1814 /* Track the memory areas used for holding in-memory arguments to a
1816 struct riscv_memory_offsets memory
;
1818 /* Holds information about the next integer register to use for passing
1820 struct riscv_arg_reg int_regs
;
1822 /* Holds information about the next floating point register to use for
1823 passing an argument. */
1824 struct riscv_arg_reg float_regs
;
1826 /* The XLEN and FLEN are copied in to this structure for convenience, and
1827 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
1832 /* Return the number of registers available for use as parameters in the
1833 register set REG. Returned value can be 0 or more. */
1836 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1838 if (reg
->next_regnum
> reg
->last_regnum
)
1841 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1844 /* If there is at least one register available in the register set REG then
1845 the next register from REG is assigned to LOC and the length field of
1846 LOC is updated to LENGTH. The register set REG is updated to indicate
1847 that the assigned register is no longer available and the function
1850 If there are no registers available in REG then the function returns
1851 false, and LOC and REG are unchanged. */
1854 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1855 struct riscv_arg_reg
*reg
,
1856 int length
, int offset
)
1858 if (reg
->next_regnum
<= reg
->last_regnum
)
1860 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1861 loc
->loc_data
.regno
= reg
->next_regnum
;
1863 loc
->c_length
= length
;
1864 loc
->c_offset
= offset
;
1871 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1872 record that an area of stack has been used to hold the parameter
1875 The length field of LOC is updated to LENGTH, the length of the
1876 parameter being stored, and ALIGN is the alignment required by the
1877 parameter, which will affect how memory is allocated out of MEMORY. */
1880 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1881 struct riscv_memory_offsets
*memory
,
1882 int length
, int align
)
1884 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1886 = align_up (memory
->arg_offset
, align
);
1887 loc
->loc_data
.offset
= memory
->arg_offset
;
1888 memory
->arg_offset
+= length
;
1889 loc
->c_length
= length
;
1891 /* Offset is always 0, either we're the first location part, in which
1892 case we're reading content from the start of the argument, or we're
1893 passing the address of a reference argument, so 0. */
1897 /* Update AINFO, which describes an argument that should be passed or
1898 returned using the integer ABI. The argloc fields within AINFO are
1899 updated to describe the location in which the argument will be passed to
1900 a function, or returned from a function.
1902 The CINFO structure contains the ongoing call information, the holds
1903 information such as which argument registers are remaining to be
1904 assigned to parameter, and how much memory has been used by parameters
1907 By examining the state of CINFO a suitable location can be selected,
1908 and assigned to AINFO. */
1911 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1912 struct riscv_call_info
*cinfo
)
1914 if (ainfo
->length
> (2 * cinfo
->xlen
))
1916 /* Argument is going to be passed by reference. */
1917 ainfo
->argloc
[0].loc_type
1918 = riscv_arg_info::location::by_ref
;
1919 cinfo
->memory
.ref_offset
1920 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1921 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1922 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1923 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1925 /* The second location for this argument is given over to holding the
1926 address of the by-reference data. Pass 0 for the offset as this
1927 is not part of the actual argument value. */
1928 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1931 riscv_assign_stack_location (&ainfo
->argloc
[1],
1932 &cinfo
->memory
, cinfo
->xlen
,
1937 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
1938 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
1940 /* Unnamed arguments in registers that require 2*XLEN alignment are
1941 passed in an aligned register pair. */
1942 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
1943 && cinfo
->int_regs
.next_regnum
& 1)
1944 cinfo
->int_regs
.next_regnum
++;
1946 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1947 &cinfo
->int_regs
, len
, 0))
1948 riscv_assign_stack_location (&ainfo
->argloc
[0],
1949 &cinfo
->memory
, len
, align
);
1951 if (len
< ainfo
->length
)
1953 len
= ainfo
->length
- len
;
1954 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1955 &cinfo
->int_regs
, len
,
1957 riscv_assign_stack_location (&ainfo
->argloc
[1],
1958 &cinfo
->memory
, len
, cinfo
->xlen
);
1963 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1964 is being passed with the floating point ABI. */
1967 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1968 struct riscv_call_info
*cinfo
)
1970 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
1971 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1974 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1977 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1981 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1982 is a complex floating point argument, and is therefore handled
1983 differently to other argument types. */
1986 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1987 struct riscv_call_info
*cinfo
)
1989 if (ainfo
->length
<= (2 * cinfo
->flen
)
1990 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
1991 && !ainfo
->is_unnamed
)
1994 int len
= ainfo
->length
/ 2;
1996 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1997 &cinfo
->float_regs
, len
, 0);
1998 gdb_assert (result
);
2000 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2001 &cinfo
->float_regs
, len
, len
);
2002 gdb_assert (result
);
2005 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2008 /* A structure used for holding information about a structure type within
2009 the inferior program. The RiscV ABI has special rules for handling some
2010 structures with a single field or with two fields. The counting of
2011 fields here is done after flattening out all nested structures. */
2013 class riscv_struct_info
2016 riscv_struct_info ()
2017 : m_number_of_fields (0),
2018 m_types
{ nullptr, nullptr },
2024 /* Analyse TYPE descending into nested structures, count the number of
2025 scalar fields and record the types of the first two fields found. */
2026 void analyse (struct type
*type
)
2028 analyse_inner (type
, 0);
2031 /* The number of scalar fields found in the analysed type. This is
2032 currently only accurate if the value returned is 0, 1, or 2 as the
2033 analysis stops counting when the number of fields is 3. This is
2034 because the RiscV ABI only has special cases for 1 or 2 fields,
2035 anything else we just don't care about. */
2036 int number_of_fields () const
2037 { return m_number_of_fields
; }
2039 /* Return the type for scalar field INDEX within the analysed type. Will
2040 return nullptr if there is no field at that index. Only INDEX values
2041 0 and 1 can be requested as the RiscV ABI only has special cases for
2042 structures with 1 or 2 fields. */
2043 struct type
*field_type (int index
) const
2045 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2046 return m_types
[index
];
2049 /* Return the offset of scalar field INDEX within the analysed type. Will
2050 return 0 if there is no field at that index. Only INDEX values 0 and
2051 1 can be requested as the RiscV ABI only has special cases for
2052 structures with 1 or 2 fields. */
2053 int field_offset (int index
) const
2055 gdb_assert (index
< (sizeof (m_offsets
) / sizeof (m_offsets
[0])));
2056 return m_offsets
[index
];
2060 /* The number of scalar fields found within the structure after recursing
2061 into nested structures. */
2062 int m_number_of_fields
;
2064 /* The types of the first two scalar fields found within the structure
2065 after recursing into nested structures. */
2066 struct type
*m_types
[2];
2068 /* The offsets of the first two scalar fields found within the structure
2069 after recursing into nested structures. */
2072 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2073 offset from the start of the top level structure being analysed. */
2074 void analyse_inner (struct type
*type
, int offset
);
2077 /* See description in class declaration. */
2080 riscv_struct_info::analyse_inner (struct type
*type
, int offset
)
2082 unsigned int count
= TYPE_NFIELDS (type
);
2085 for (i
= 0; i
< count
; ++i
)
2087 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
2090 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
2091 field_type
= check_typedef (field_type
);
2093 = offset
+ TYPE_FIELD_BITPOS (type
, i
) / TARGET_CHAR_BIT
;
2095 switch (TYPE_CODE (field_type
))
2097 case TYPE_CODE_STRUCT
:
2098 analyse_inner (field_type
, field_offset
);
2102 /* RiscV only flattens out structures. Anything else does not
2103 need to be flattened, we just record the type, and when we
2104 look at the analysis results we'll realise this is not a
2105 structure we can special case, and pass the structure in
2107 if (m_number_of_fields
< 2)
2109 m_types
[m_number_of_fields
] = field_type
;
2110 m_offsets
[m_number_of_fields
] = field_offset
;
2112 m_number_of_fields
++;
2116 /* RiscV only has special handling for structures with 1 or 2 scalar
2117 fields, any more than that and the structure is just passed in
2118 memory. We can safely drop out early when we find 3 or more
2121 if (m_number_of_fields
> 2)
2126 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2127 is a structure. Small structures on RiscV have some special case
2128 handling in order that the structure might be passed in register.
2129 Larger structures are passed in memory. After assigning location
2130 information to AINFO, CINFO will have been updated. */
2133 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2134 struct riscv_call_info
*cinfo
)
2136 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2138 struct riscv_struct_info sinfo
;
2140 sinfo
.analyse (ainfo
->type
);
2141 if (sinfo
.number_of_fields () == 1
2142 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
2144 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2145 except we use the type of the complex field instead of the
2146 type from AINFO, and the first location might be at a non-zero
2148 if (TYPE_LENGTH (sinfo
.field_type (0)) <= (2 * cinfo
->flen
)
2149 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2150 && !ainfo
->is_unnamed
)
2153 int len
= TYPE_LENGTH (sinfo
.field_type (0)) / 2;
2154 int offset
= sinfo
.field_offset (0);
2156 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2157 &cinfo
->float_regs
, len
,
2159 gdb_assert (result
);
2161 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2162 &cinfo
->float_regs
, len
,
2164 gdb_assert (result
);
2167 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2171 if (sinfo
.number_of_fields () == 1
2172 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
2174 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2175 except we use the type of the first scalar field instead of
2176 the type from AINFO. Also the location might be at a non-zero
2178 if (TYPE_LENGTH (sinfo
.field_type (0)) > cinfo
->flen
2179 || ainfo
->is_unnamed
)
2180 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2183 int offset
= sinfo
.field_offset (0);
2184 int len
= TYPE_LENGTH (sinfo
.field_type (0));
2186 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2189 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2194 if (sinfo
.number_of_fields () == 2
2195 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
2196 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2197 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
2198 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
2199 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2201 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2202 int offset
= sinfo
.field_offset (0);
2203 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2204 &cinfo
->float_regs
, len0
, offset
))
2205 error (_("failed during argument setup"));
2207 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2208 offset
= sinfo
.field_offset (1);
2209 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
2210 - TYPE_LENGTH (sinfo
.field_type (0))));
2212 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2215 error (_("failed during argument setup"));
2219 if (sinfo
.number_of_fields () == 2
2220 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2221 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
2222 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2223 && is_integral_type (sinfo
.field_type (1))
2224 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
2226 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2227 int offset
= sinfo
.field_offset (0);
2228 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2229 &cinfo
->float_regs
, len0
, offset
))
2230 error (_("failed during argument setup"));
2232 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2233 offset
= sinfo
.field_offset (1);
2234 gdb_assert (len1
<= cinfo
->xlen
);
2235 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2236 &cinfo
->int_regs
, len1
, offset
))
2237 error (_("failed during argument setup"));
2241 if (sinfo
.number_of_fields () == 2
2242 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2243 && (is_integral_type (sinfo
.field_type (0))
2244 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
2245 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
2246 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
2248 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2249 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2251 gdb_assert (len0
<= cinfo
->xlen
);
2252 gdb_assert (len1
<= cinfo
->flen
);
2254 int offset
= sinfo
.field_offset (0);
2255 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2256 &cinfo
->int_regs
, len0
, offset
))
2257 error (_("failed during argument setup"));
2259 offset
= sinfo
.field_offset (1);
2260 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2263 error (_("failed during argument setup"));
2269 /* Non of the structure flattening cases apply, so we just pass using
2271 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2274 /* Assign a location to call (or return) argument AINFO, the location is
2275 selected from CINFO which holds information about what call argument
2276 locations are available for use next. The TYPE is the type of the
2277 argument being passed, this information is recorded into AINFO (along
2278 with some additional information derived from the type). IS_UNNAMED
2279 is true if this is an unnamed (stdarg) argument, this info is also
2280 recorded into AINFO.
2282 After assigning a location to AINFO, CINFO will have been updated. */
2285 riscv_arg_location (struct gdbarch
*gdbarch
,
2286 struct riscv_arg_info
*ainfo
,
2287 struct riscv_call_info
*cinfo
,
2288 struct type
*type
, bool is_unnamed
)
2291 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
2292 ainfo
->align
= type_align (ainfo
->type
);
2293 ainfo
->is_unnamed
= is_unnamed
;
2294 ainfo
->contents
= nullptr;
2295 ainfo
->argloc
[0].c_length
= 0;
2296 ainfo
->argloc
[1].c_length
= 0;
2298 switch (TYPE_CODE (ainfo
->type
))
2301 case TYPE_CODE_BOOL
:
2302 case TYPE_CODE_CHAR
:
2303 case TYPE_CODE_RANGE
:
2304 case TYPE_CODE_ENUM
:
2306 if (ainfo
->length
<= cinfo
->xlen
)
2308 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2309 ainfo
->length
= cinfo
->xlen
;
2311 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2313 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2314 ainfo
->length
= 2 * cinfo
->xlen
;
2317 /* Recalculate the alignment requirement. */
2318 ainfo
->align
= type_align (ainfo
->type
);
2319 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2323 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2326 case TYPE_CODE_COMPLEX
:
2327 riscv_call_arg_complex_float (ainfo
, cinfo
);
2330 case TYPE_CODE_STRUCT
:
2331 riscv_call_arg_struct (ainfo
, cinfo
);
2335 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2340 /* Used for printing debug information about the call argument location in
2341 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2342 addresses for the location of pass-by-reference and
2343 arguments-on-the-stack memory areas. */
2346 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2347 struct riscv_arg_info
*info
,
2348 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2350 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2351 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2352 switch (info
->argloc
[0].loc_type
)
2354 case riscv_arg_info::location::in_reg
:
2356 (stream
, ", register %s",
2357 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2358 if (info
->argloc
[0].c_length
< info
->length
)
2360 switch (info
->argloc
[1].loc_type
)
2362 case riscv_arg_info::location::in_reg
:
2364 (stream
, ", register %s",
2365 gdbarch_register_name (gdbarch
,
2366 info
->argloc
[1].loc_data
.regno
));
2369 case riscv_arg_info::location::on_stack
:
2370 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2371 info
->argloc
[1].loc_data
.offset
);
2374 case riscv_arg_info::location::by_ref
:
2376 /* The second location should never be a reference, any
2377 argument being passed by reference just places its address
2378 in the first location and is done. */
2379 error (_("invalid argument location"));
2383 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2384 fprintf_unfiltered (stream
, " (offset 0x%x)",
2385 info
->argloc
[1].c_offset
);
2389 case riscv_arg_info::location::on_stack
:
2390 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2391 info
->argloc
[0].loc_data
.offset
);
2394 case riscv_arg_info::location::by_ref
:
2396 (stream
, ", by reference, data at offset 0x%x (%s)",
2397 info
->argloc
[0].loc_data
.offset
,
2398 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2399 if (info
->argloc
[1].loc_type
2400 == riscv_arg_info::location::in_reg
)
2402 (stream
, ", address in register %s",
2403 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2406 gdb_assert (info
->argloc
[1].loc_type
2407 == riscv_arg_info::location::on_stack
);
2409 (stream
, ", address on stack at offset 0x%x (%s)",
2410 info
->argloc
[1].loc_data
.offset
,
2411 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2416 gdb_assert_not_reached (_("unknown argument location type"));
2420 /* Implement the push dummy call gdbarch callback. */
2423 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2424 struct value
*function
,
2425 struct regcache
*regcache
,
2428 struct value
**args
,
2430 function_call_return_method return_method
,
2431 CORE_ADDR struct_addr
)
2434 CORE_ADDR sp_args
, sp_refs
;
2435 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2437 struct riscv_arg_info
*arg_info
=
2438 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2440 struct riscv_call_info
call_info (gdbarch
);
2444 struct type
*ftype
= check_typedef (value_type (function
));
2446 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
2447 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
2449 /* We'll use register $a0 if we're returning a struct. */
2450 if (return_method
== return_method_struct
)
2451 ++call_info
.int_regs
.next_regnum
;
2453 for (i
= 0; i
< nargs
; ++i
)
2455 struct value
*arg_value
;
2456 struct type
*arg_type
;
2457 struct riscv_arg_info
*info
= &arg_info
[i
];
2459 arg_value
= args
[i
];
2460 arg_type
= check_typedef (value_type (arg_value
));
2462 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
2463 TYPE_VARARGS (ftype
) && i
>= TYPE_NFIELDS (ftype
));
2465 if (info
->type
!= arg_type
)
2466 arg_value
= value_cast (info
->type
, arg_value
);
2467 info
->contents
= value_contents (arg_value
);
2470 /* Adjust the stack pointer and align it. */
2471 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2472 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2474 if (riscv_debug_infcall
> 0)
2476 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2477 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2478 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2479 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2480 call_info
.xlen
, call_info
.flen
);
2481 if (return_method
== return_method_struct
)
2482 fprintf_unfiltered (gdb_stdlog
,
2483 "[*] struct return pointer in register $A0\n");
2484 for (i
= 0; i
< nargs
; ++i
)
2486 struct riscv_arg_info
*info
= &arg_info
[i
];
2488 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2489 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2490 fprintf_unfiltered (gdb_stdlog
, "\n");
2492 if (call_info
.memory
.arg_offset
> 0
2493 || call_info
.memory
.ref_offset
> 0)
2495 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2496 core_addr_to_string (osp
));
2497 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2498 call_info
.memory
.arg_offset
);
2499 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2500 call_info
.memory
.ref_offset
);
2501 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2502 core_addr_to_string_nz (osp
- sp
));
2506 /* Now load the argument into registers, or onto the stack. */
2508 if (return_method
== return_method_struct
)
2510 gdb_byte buf
[sizeof (LONGEST
)];
2512 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2513 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
2516 for (i
= 0; i
< nargs
; ++i
)
2519 int second_arg_length
= 0;
2520 const gdb_byte
*second_arg_data
;
2521 struct riscv_arg_info
*info
= &arg_info
[i
];
2523 gdb_assert (info
->length
> 0);
2525 switch (info
->argloc
[0].loc_type
)
2527 case riscv_arg_info::location::in_reg
:
2529 gdb_byte tmp
[sizeof (ULONGEST
)];
2531 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2532 /* FP values in FP registers must be NaN-boxed. */
2533 if (riscv_is_fp_regno_p (info
->argloc
[0].loc_data
.regno
)
2534 && info
->argloc
[0].c_length
< call_info
.flen
)
2535 memset (tmp
, -1, sizeof (tmp
));
2537 memset (tmp
, 0, sizeof (tmp
));
2538 memcpy (tmp
, (info
->contents
+ info
->argloc
[0].c_offset
),
2539 info
->argloc
[0].c_length
);
2540 regcache
->cooked_write (info
->argloc
[0].loc_data
.regno
, tmp
);
2542 (((info
->argloc
[0].c_length
+ info
->argloc
[0].c_offset
) < info
->length
)
2543 ? info
->argloc
[1].c_length
: 0);
2544 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2548 case riscv_arg_info::location::on_stack
:
2549 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2550 write_memory (dst
, info
->contents
, info
->length
);
2551 second_arg_length
= 0;
2554 case riscv_arg_info::location::by_ref
:
2555 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2556 write_memory (dst
, info
->contents
, info
->length
);
2558 second_arg_length
= call_info
.xlen
;
2559 second_arg_data
= (gdb_byte
*) &dst
;
2563 gdb_assert_not_reached (_("unknown argument location type"));
2566 if (second_arg_length
> 0)
2568 switch (info
->argloc
[1].loc_type
)
2570 case riscv_arg_info::location::in_reg
:
2572 gdb_byte tmp
[sizeof (ULONGEST
)];
2574 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2575 && second_arg_length
<= call_info
.flen
)
2576 || second_arg_length
<= call_info
.xlen
);
2577 /* FP values in FP registers must be NaN-boxed. */
2578 if (riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2579 && second_arg_length
< call_info
.flen
)
2580 memset (tmp
, -1, sizeof (tmp
));
2582 memset (tmp
, 0, sizeof (tmp
));
2583 memcpy (tmp
, second_arg_data
, second_arg_length
);
2584 regcache
->cooked_write (info
->argloc
[1].loc_data
.regno
, tmp
);
2588 case riscv_arg_info::location::on_stack
:
2592 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2593 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2597 case riscv_arg_info::location::by_ref
:
2599 /* The second location should never be a reference, any
2600 argument being passed by reference just places its address
2601 in the first location and is done. */
2602 error (_("invalid argument location"));
2608 /* Set the dummy return value to bp_addr.
2609 A dummy breakpoint will be setup to execute the call. */
2611 if (riscv_debug_infcall
> 0)
2612 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2613 core_addr_to_string (bp_addr
));
2614 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2616 /* Finally, update the stack pointer. */
2618 if (riscv_debug_infcall
> 0)
2619 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2620 core_addr_to_string (sp
));
2621 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2626 /* Implement the return_value gdbarch method. */
2628 static enum return_value_convention
2629 riscv_return_value (struct gdbarch
*gdbarch
,
2630 struct value
*function
,
2632 struct regcache
*regcache
,
2634 const gdb_byte
*writebuf
)
2636 struct riscv_call_info
call_info (gdbarch
);
2637 struct riscv_arg_info info
;
2638 struct type
*arg_type
;
2640 arg_type
= check_typedef (type
);
2641 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
2643 if (riscv_debug_infcall
> 0)
2645 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2646 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2647 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2648 fprintf_unfiltered (gdb_stdlog
, "\n");
2651 if (readbuf
!= nullptr || writebuf
!= nullptr)
2653 unsigned int arg_len
;
2654 struct value
*abi_val
;
2655 gdb_byte
*old_readbuf
= nullptr;
2658 /* We only do one thing at a time. */
2659 gdb_assert (readbuf
== nullptr || writebuf
== nullptr);
2661 /* In some cases the argument is not returned as the declared type,
2662 and we need to cast to or from the ABI type in order to
2663 correctly access the argument. When writing to the machine we
2664 do the cast here, when reading from the machine the cast occurs
2665 later, after extracting the value. As the ABI type can be
2666 larger than the declared type, then the read or write buffers
2667 passed in might be too small. Here we ensure that we are using
2668 buffers of sufficient size. */
2669 if (writebuf
!= nullptr)
2671 struct value
*arg_val
= value_from_contents (arg_type
, writebuf
);
2672 abi_val
= value_cast (info
.type
, arg_val
);
2673 writebuf
= value_contents_raw (abi_val
);
2677 abi_val
= allocate_value (info
.type
);
2678 old_readbuf
= readbuf
;
2679 readbuf
= value_contents_raw (abi_val
);
2681 arg_len
= TYPE_LENGTH (info
.type
);
2683 switch (info
.argloc
[0].loc_type
)
2685 /* Return value in register(s). */
2686 case riscv_arg_info::location::in_reg
:
2688 regnum
= info
.argloc
[0].loc_data
.regno
;
2689 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
2690 gdb_assert (info
.argloc
[0].c_length
2691 <= register_size (gdbarch
, regnum
));
2695 gdb_byte
*ptr
= readbuf
+ info
.argloc
[0].c_offset
;
2696 regcache
->cooked_read_part (regnum
, 0,
2697 info
.argloc
[0].c_length
,
2703 const gdb_byte
*ptr
= writebuf
+ info
.argloc
[0].c_offset
;
2704 regcache
->cooked_write_part (regnum
, 0,
2705 info
.argloc
[0].c_length
,
2709 /* A return value in register can have a second part in a
2711 if (info
.argloc
[1].c_length
> 0)
2713 switch (info
.argloc
[1].loc_type
)
2715 case riscv_arg_info::location::in_reg
:
2716 regnum
= info
.argloc
[1].loc_data
.regno
;
2718 gdb_assert ((info
.argloc
[0].c_length
2719 + info
.argloc
[1].c_length
) <= arg_len
);
2720 gdb_assert (info
.argloc
[1].c_length
2721 <= register_size (gdbarch
, regnum
));
2725 readbuf
+= info
.argloc
[1].c_offset
;
2726 regcache
->cooked_read_part (regnum
, 0,
2727 info
.argloc
[1].c_length
,
2733 writebuf
+= info
.argloc
[1].c_offset
;
2734 regcache
->cooked_write_part (regnum
, 0,
2735 info
.argloc
[1].c_length
,
2740 case riscv_arg_info::location::by_ref
:
2741 case riscv_arg_info::location::on_stack
:
2743 error (_("invalid argument location"));
2750 /* Return value by reference will have its address in A0. */
2751 case riscv_arg_info::location::by_ref
:
2755 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2757 if (readbuf
!= nullptr)
2758 read_memory (addr
, readbuf
, info
.length
);
2759 if (writebuf
!= nullptr)
2760 write_memory (addr
, writebuf
, info
.length
);
2764 case riscv_arg_info::location::on_stack
:
2766 error (_("invalid argument location"));
2770 /* This completes the cast from abi type back to the declared type
2771 in the case that we are reading from the machine. See the
2772 comment at the head of this block for more details. */
2773 if (readbuf
!= nullptr)
2775 struct value
*arg_val
= value_cast (arg_type
, abi_val
);
2776 memcpy (old_readbuf
, value_contents_raw (arg_val
),
2777 TYPE_LENGTH (arg_type
));
2781 switch (info
.argloc
[0].loc_type
)
2783 case riscv_arg_info::location::in_reg
:
2784 return RETURN_VALUE_REGISTER_CONVENTION
;
2785 case riscv_arg_info::location::by_ref
:
2786 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2787 case riscv_arg_info::location::on_stack
:
2789 error (_("invalid argument location"));
2793 /* Implement the frame_align gdbarch method. */
2796 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2798 return align_down (addr
, 16);
2801 /* Generate, or return the cached frame cache for the RiscV frame
2804 static struct riscv_unwind_cache
*
2805 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2807 CORE_ADDR pc
, start_addr
;
2808 struct riscv_unwind_cache
*cache
;
2809 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2812 if ((*this_cache
) != NULL
)
2813 return (struct riscv_unwind_cache
*) *this_cache
;
2815 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
2816 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
2817 (*this_cache
) = cache
;
2819 /* Scan the prologue, filling in the cache. */
2820 start_addr
= get_frame_func (this_frame
);
2821 pc
= get_frame_pc (this_frame
);
2822 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
2824 /* We can now calculate the frame base address. */
2826 = (get_frame_register_signed (this_frame
, cache
->frame_base_reg
)
2827 + cache
->frame_base_offset
);
2828 if (riscv_debug_unwinder
)
2829 fprintf_unfiltered (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
2830 core_addr_to_string (cache
->frame_base
),
2831 gdbarch_register_name (gdbarch
,
2832 cache
->frame_base_reg
),
2833 cache
->frame_base_offset
);
2835 /* The prologue scanner sets the address of registers stored to the stack
2836 as the offset of that register from the frame base. The prologue
2837 scanner doesn't know the actual frame base value, and so is unable to
2838 compute the exact address. We do now know the frame base value, so
2839 update the address of registers stored to the stack. */
2840 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
2841 for (regno
= 0; regno
< numregs
; ++regno
)
2843 if (trad_frame_addr_p (cache
->regs
, regno
))
2844 cache
->regs
[regno
].addr
+= cache
->frame_base
;
2847 /* The previous $pc can be found wherever the $ra value can be found.
2848 The previous $ra value is gone, this would have been stored be the
2849 previous frame if required. */
2850 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
2851 trad_frame_set_unknown (cache
->regs
, RISCV_RA_REGNUM
);
2853 /* Build the frame id. */
2854 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
2856 /* The previous $sp value is the frame base value. */
2857 trad_frame_set_value (cache
->regs
, gdbarch_sp_regnum (gdbarch
),
2863 /* Implement the this_id callback for RiscV frame unwinder. */
2866 riscv_frame_this_id (struct frame_info
*this_frame
,
2867 void **prologue_cache
,
2868 struct frame_id
*this_id
)
2870 struct riscv_unwind_cache
*cache
;
2874 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2875 *this_id
= cache
->this_id
;
2877 catch (const gdb_exception_error
&ex
)
2879 /* Ignore errors, this leaves the frame id as the predefined outer
2880 frame id which terminates the backtrace at this point. */
2884 /* Implement the prev_register callback for RiscV frame unwinder. */
2886 static struct value
*
2887 riscv_frame_prev_register (struct frame_info
*this_frame
,
2888 void **prologue_cache
,
2891 struct riscv_unwind_cache
*cache
;
2893 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2894 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
2897 /* Structure defining the RiscV normal frame unwind functions. Since we
2898 are the fallback unwinder (DWARF unwinder is used first), we use the
2899 default frame sniffer, which always accepts the frame. */
2901 static const struct frame_unwind riscv_frame_unwind
=
2903 /*.type =*/ NORMAL_FRAME
,
2904 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2905 /*.this_id =*/ riscv_frame_this_id
,
2906 /*.prev_register =*/ riscv_frame_prev_register
,
2907 /*.unwind_data =*/ NULL
,
2908 /*.sniffer =*/ default_frame_sniffer
,
2909 /*.dealloc_cache =*/ NULL
,
2910 /*.prev_arch =*/ NULL
,
2913 /* Extract a set of required target features out of INFO, specifically the
2914 bfd being executed is examined to see what target features it requires.
2915 IF there is no current bfd, or the bfd doesn't indicate any useful
2916 features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
2918 static struct riscv_gdbarch_features
2919 riscv_features_from_gdbarch_info (const struct gdbarch_info info
)
2921 struct riscv_gdbarch_features features
;
2923 /* Now try to improve on the defaults by looking at the binary we are
2924 going to execute. We assume the user knows what they are doing and
2925 that the target will match the binary. Remember, this code path is
2926 only used at all if the target hasn't given us a description, so this
2927 is really a last ditched effort to do something sane before giving
2929 if (info
.abfd
!= NULL
2930 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2932 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2933 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2935 if (eclass
== ELFCLASS32
)
2937 else if (eclass
== ELFCLASS64
)
2940 internal_error (__FILE__
, __LINE__
,
2941 _("unknown ELF header class %d"), eclass
);
2943 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2945 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2952 /* Find a suitable default target description. Use the contents of INFO,
2953 specifically the bfd object being executed, to guide the selection of a
2954 suitable default target description. */
2956 static const struct target_desc
*
2957 riscv_find_default_target_description (const struct gdbarch_info info
)
2959 /* Extract desired feature set from INFO. */
2960 struct riscv_gdbarch_features features
2961 = riscv_features_from_gdbarch_info (info
);
2963 /* If the XLEN field is still 0 then we got nothing useful from INFO. In
2964 this case we fall back to a minimal useful target, 8-byte x-registers,
2965 with no floating point. */
2966 if (features
.xlen
== 0)
2969 /* Now build a target description based on the feature set. */
2970 return riscv_lookup_target_description (features
);
2973 /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
2974 is updated with the register numbers for each register as listed in
2975 REG_SET. If any register marked as required in REG_SET is not found in
2976 FEATURE then this function returns false, otherwise, it returns true. */
2979 riscv_check_tdesc_feature (struct tdesc_arch_data
*tdesc_data
,
2980 const struct tdesc_feature
*feature
,
2981 const struct riscv_register_feature
*reg_set
)
2983 for (const auto ®
: reg_set
->registers
)
2987 for (const char *name
: reg
.names
)
2990 tdesc_numbered_register (feature
, tdesc_data
, reg
.regnum
, name
);
2996 if (!found
&& reg
.required_p
)
3003 /* Add all the expected register sets into GDBARCH. */
3006 riscv_add_reggroups (struct gdbarch
*gdbarch
)
3008 /* Add predefined register groups. */
3009 reggroup_add (gdbarch
, all_reggroup
);
3010 reggroup_add (gdbarch
, save_reggroup
);
3011 reggroup_add (gdbarch
, restore_reggroup
);
3012 reggroup_add (gdbarch
, system_reggroup
);
3013 reggroup_add (gdbarch
, vector_reggroup
);
3014 reggroup_add (gdbarch
, general_reggroup
);
3015 reggroup_add (gdbarch
, float_reggroup
);
3017 /* Add RISC-V specific register groups. */
3018 reggroup_add (gdbarch
, csr_reggroup
);
3021 /* Create register aliases for all the alternative names that exist for
3022 registers in REG_SET. */
3025 riscv_setup_register_aliases (struct gdbarch
*gdbarch
,
3026 const struct riscv_register_feature
*reg_set
)
3028 for (auto ®
: reg_set
->registers
)
3030 /* The first item in the names list is the preferred name for the
3031 register, this is what RISCV_REGISTER_NAME returns, and so we
3032 don't need to create an alias with that name here. */
3033 for (int i
= 1; i
< reg
.names
.size (); ++i
)
3034 user_reg_add (gdbarch
, reg
.names
[i
], value_of_riscv_user_reg
,
3039 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3042 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3044 if (reg
< RISCV_DWARF_REGNUM_X31
)
3045 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3047 else if (reg
< RISCV_DWARF_REGNUM_F31
)
3048 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3053 /* Implement the gcc_target_options method. We have to select the arch and abi
3054 from the feature info. We have enough feature info to select the abi, but
3055 not enough info for the arch given all of the possible architecture
3056 extensions. So choose reasonable defaults for now. */
3059 riscv_gcc_target_options (struct gdbarch
*gdbarch
)
3061 int isa_xlen
= riscv_isa_xlen (gdbarch
);
3062 int isa_flen
= riscv_isa_flen (gdbarch
);
3063 int abi_xlen
= riscv_abi_xlen (gdbarch
);
3064 int abi_flen
= riscv_abi_flen (gdbarch
);
3065 std::string target_options
;
3067 target_options
= "-march=rv";
3069 target_options
+= "64";
3071 target_options
+= "32";
3073 target_options
+= "gc";
3074 else if (isa_flen
== 4)
3075 target_options
+= "imafc";
3077 target_options
+= "imac";
3079 target_options
+= " -mabi=";
3081 target_options
+= "lp64";
3083 target_options
+= "ilp32";
3085 target_options
+= "d";
3086 else if (abi_flen
== 4)
3087 target_options
+= "f";
3089 /* The gdb loader doesn't handle link-time relaxation relocations. */
3090 target_options
+= " -mno-relax";
3092 return target_options
;
3095 /* Implement the gnu_triplet_regexp method. A single compiler supports both
3096 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
3097 recommended) riscv. */
3100 riscv_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
3102 return "riscv(32|64)?";
3105 /* Initialize the current architecture based on INFO. If possible,
3106 re-use an architecture from ARCHES, which is a list of
3107 architectures already created during this debugging session.
3109 Called e.g. at program startup, when reading a core file, and when
3110 reading a binary file. */
3112 static struct gdbarch
*
3113 riscv_gdbarch_init (struct gdbarch_info info
,
3114 struct gdbarch_list
*arches
)
3116 struct gdbarch
*gdbarch
;
3117 struct gdbarch_tdep
*tdep
;
3118 struct riscv_gdbarch_features features
;
3119 const struct target_desc
*tdesc
= info
.target_desc
;
3121 /* Ensure we always have a target description. */
3122 if (!tdesc_has_registers (tdesc
))
3123 tdesc
= riscv_find_default_target_description (info
);
3126 if (riscv_debug_gdbarch
)
3127 fprintf_unfiltered (gdb_stdlog
, "Have got a target description\n");
3129 const struct tdesc_feature
*feature_cpu
3130 = tdesc_find_feature (tdesc
, riscv_xreg_feature
.name
);
3131 const struct tdesc_feature
*feature_fpu
3132 = tdesc_find_feature (tdesc
, riscv_freg_feature
.name
);
3133 const struct tdesc_feature
*feature_virtual
3134 = tdesc_find_feature (tdesc
, riscv_virtual_feature
.name
);
3135 const struct tdesc_feature
*feature_csr
3136 = tdesc_find_feature (tdesc
, riscv_csr_feature
.name
);
3138 if (feature_cpu
== NULL
)
3141 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3143 bool valid_p
= riscv_check_tdesc_feature (tdesc_data
,
3145 &riscv_xreg_feature
);
3148 /* Check that all of the core cpu registers have the same bitsize. */
3149 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
3151 for (auto &tdesc_reg
: feature_cpu
->registers
)
3152 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
3154 if (riscv_debug_gdbarch
)
3157 "From target-description, xlen = %d\n", xlen_bitsize
);
3159 features
.xlen
= (xlen_bitsize
/ 8);
3162 if (feature_fpu
!= NULL
)
3164 valid_p
&= riscv_check_tdesc_feature (tdesc_data
, feature_fpu
,
3165 &riscv_freg_feature
);
3167 /* Search for the first floating point register (by any alias), to
3168 determine the bitsize. */
3170 const auto &fp0
= riscv_freg_feature
.registers
[0];
3172 for (const char *name
: fp0
.names
)
3174 if (tdesc_unnumbered_register (feature_fpu
, name
))
3176 bitsize
= tdesc_register_bitsize (feature_fpu
, name
);
3181 gdb_assert (bitsize
!= -1);
3182 features
.flen
= (bitsize
/ 8);
3184 if (riscv_debug_gdbarch
)
3187 "From target-description, flen = %d\n", bitsize
);
3193 if (riscv_debug_gdbarch
)
3196 "No FPU in target-description, assume soft-float ABI\n");
3199 if (feature_virtual
)
3200 riscv_check_tdesc_feature (tdesc_data
, feature_virtual
,
3201 &riscv_virtual_feature
);
3204 riscv_check_tdesc_feature (tdesc_data
, feature_csr
,
3205 &riscv_csr_feature
);
3209 if (riscv_debug_gdbarch
)
3210 fprintf_unfiltered (gdb_stdlog
, "Target description is not valid\n");
3211 tdesc_data_cleanup (tdesc_data
);
3215 /* Have a look at what the supplied (if any) bfd object requires of the
3216 target, then check that this matches with what the target is
3218 struct riscv_gdbarch_features abi_features
3219 = riscv_features_from_gdbarch_info (info
);
3220 /* In theory a binary compiled for RV32 could run on an RV64 target,
3221 however, this has not been tested in GDB yet, so for now we require
3222 that the requested xlen match the targets xlen. */
3223 if (abi_features
.xlen
!= 0 && abi_features
.xlen
!= features
.xlen
)
3224 error (_("bfd requires xlen %d, but target has xlen %d"),
3225 abi_features
.xlen
, features
.xlen
);
3226 /* We do support running binaries compiled for 32-bit float on targets
3227 with 64-bit float, so we only complain if the binary requires more
3228 than the target has available. */
3229 if (abi_features
.flen
> features
.flen
)
3230 error (_("bfd requires flen %d, but target has flen %d"),
3231 abi_features
.flen
, features
.flen
);
3233 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3234 features from the INFO object. In this case we assume that the xlen
3235 abi matches the hardware. */
3236 if (abi_features
.xlen
== 0)
3237 abi_features
.xlen
= features
.xlen
;
3239 /* Find a candidate among the list of pre-declared architectures. */
3240 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3242 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3244 /* Check that the feature set of the ARCHES matches the feature set
3245 we are looking for. If it doesn't then we can't reuse this
3247 struct gdbarch_tdep
*other_tdep
= gdbarch_tdep (arches
->gdbarch
);
3249 if (other_tdep
->isa_features
!= features
3250 || other_tdep
->abi_features
!= abi_features
)
3258 tdesc_data_cleanup (tdesc_data
);
3259 return arches
->gdbarch
;
3262 /* None found, so create a new architecture from the information provided. */
3263 tdep
= new (struct gdbarch_tdep
);
3264 gdbarch
= gdbarch_alloc (&info
, tdep
);
3265 tdep
->isa_features
= features
;
3266 tdep
->abi_features
= abi_features
;
3268 /* Target data types. */
3269 set_gdbarch_short_bit (gdbarch
, 16);
3270 set_gdbarch_int_bit (gdbarch
, 32);
3271 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3272 set_gdbarch_long_long_bit (gdbarch
, 64);
3273 set_gdbarch_float_bit (gdbarch
, 32);
3274 set_gdbarch_double_bit (gdbarch
, 64);
3275 set_gdbarch_long_double_bit (gdbarch
, 128);
3276 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3277 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3278 set_gdbarch_char_signed (gdbarch
, 0);
3279 set_gdbarch_type_align (gdbarch
, riscv_type_align
);
3281 /* Information about the target architecture. */
3282 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
3283 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3284 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3285 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3287 /* Functions to analyze frames. */
3288 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3289 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3290 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3292 /* Functions handling dummy frames. */
3293 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3294 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3295 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3297 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3299 dwarf2_append_unwinders (gdbarch
);
3300 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3302 /* Register architecture. */
3303 riscv_add_reggroups (gdbarch
);
3305 /* Internal <-> external register number maps. */
3306 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3308 /* We reserve all possible register numbers for the known registers.
3309 This means the target description mechanism will add any target
3310 specific registers after this number. This helps make debugging GDB
3311 just a little easier. */
3312 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3314 /* We don't have to provide the count of 0 here (its the default) but
3315 include this line to make it explicit that, right now, we don't have
3316 any pseudo registers on RISC-V. */
3317 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
3319 /* Some specific register numbers GDB likes to know about. */
3320 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3321 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3323 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3325 /* Finalise the target description registers. */
3326 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3328 /* Override the register type callback setup by the target description
3329 mechanism. This allows us to provide special type for floating point
3331 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3333 /* Override the register name callback setup by the target description
3334 mechanism. This allows us to force our preferred names for the
3335 registers, no matter what the target description called them. */
3336 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
3338 /* Override the register group callback setup by the target description
3339 mechanism. This allows us to force registers into the groups we
3340 want, ignoring what the target tells us. */
3341 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
3343 /* Create register aliases for alternative register names. */
3344 riscv_setup_register_aliases (gdbarch
, &riscv_xreg_feature
);
3345 if (riscv_has_fp_regs (gdbarch
))
3346 riscv_setup_register_aliases (gdbarch
, &riscv_freg_feature
);
3347 riscv_setup_register_aliases (gdbarch
, &riscv_csr_feature
);
3349 /* Compile command hooks. */
3350 set_gdbarch_gcc_target_options (gdbarch
, riscv_gcc_target_options
);
3351 set_gdbarch_gnu_triplet_regexp (gdbarch
, riscv_gnu_triplet_regexp
);
3353 /* Hook in OS ABI-specific overrides, if they have been registered. */
3354 gdbarch_init_osabi (info
, gdbarch
);
3356 register_riscv_ravenscar_ops (gdbarch
);
3361 /* This decodes the current instruction and determines the address of the
3362 next instruction. */
3365 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
3367 struct gdbarch
*gdbarch
= regcache
->arch ();
3368 struct riscv_insn insn
;
3371 insn
.decode (gdbarch
, pc
);
3372 next_pc
= pc
+ insn
.length ();
3374 if (insn
.opcode () == riscv_insn::JAL
)
3375 next_pc
= pc
+ insn
.imm_signed ();
3376 else if (insn
.opcode () == riscv_insn::JALR
)
3379 regcache
->cooked_read (insn
.rs1 (), &source
);
3380 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
3382 else if (insn
.opcode () == riscv_insn::BEQ
)
3385 regcache
->cooked_read (insn
.rs1 (), &src1
);
3386 regcache
->cooked_read (insn
.rs2 (), &src2
);
3388 next_pc
= pc
+ insn
.imm_signed ();
3390 else if (insn
.opcode () == riscv_insn::BNE
)
3393 regcache
->cooked_read (insn
.rs1 (), &src1
);
3394 regcache
->cooked_read (insn
.rs2 (), &src2
);
3396 next_pc
= pc
+ insn
.imm_signed ();
3398 else if (insn
.opcode () == riscv_insn::BLT
)
3401 regcache
->cooked_read (insn
.rs1 (), &src1
);
3402 regcache
->cooked_read (insn
.rs2 (), &src2
);
3404 next_pc
= pc
+ insn
.imm_signed ();
3406 else if (insn
.opcode () == riscv_insn::BGE
)
3409 regcache
->cooked_read (insn
.rs1 (), &src1
);
3410 regcache
->cooked_read (insn
.rs2 (), &src2
);
3412 next_pc
= pc
+ insn
.imm_signed ();
3414 else if (insn
.opcode () == riscv_insn::BLTU
)
3416 ULONGEST src1
, src2
;
3417 regcache
->cooked_read (insn
.rs1 (), &src1
);
3418 regcache
->cooked_read (insn
.rs2 (), &src2
);
3420 next_pc
= pc
+ insn
.imm_signed ();
3422 else if (insn
.opcode () == riscv_insn::BGEU
)
3424 ULONGEST src1
, src2
;
3425 regcache
->cooked_read (insn
.rs1 (), &src1
);
3426 regcache
->cooked_read (insn
.rs2 (), &src2
);
3428 next_pc
= pc
+ insn
.imm_signed ();
3434 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3435 for the end of the sequence and put the breakpoint there. */
3438 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
3441 struct gdbarch
*gdbarch
= regcache
->arch ();
3442 struct riscv_insn insn
;
3443 CORE_ADDR cur_step_pc
= pc
;
3444 CORE_ADDR last_addr
= 0;
3446 /* First instruction has to be a load reserved. */
3447 insn
.decode (gdbarch
, cur_step_pc
);
3448 if (insn
.opcode () != riscv_insn::LR
)
3450 cur_step_pc
= cur_step_pc
+ insn
.length ();
3452 /* Next instruction should be branch to exit. */
3453 insn
.decode (gdbarch
, cur_step_pc
);
3454 if (insn
.opcode () != riscv_insn::BNE
)
3456 last_addr
= cur_step_pc
+ insn
.imm_signed ();
3457 cur_step_pc
= cur_step_pc
+ insn
.length ();
3459 /* Next instruction should be store conditional. */
3460 insn
.decode (gdbarch
, cur_step_pc
);
3461 if (insn
.opcode () != riscv_insn::SC
)
3463 cur_step_pc
= cur_step_pc
+ insn
.length ();
3465 /* Next instruction should be branch to start. */
3466 insn
.decode (gdbarch
, cur_step_pc
);
3467 if (insn
.opcode () != riscv_insn::BNE
)
3469 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
3471 cur_step_pc
= cur_step_pc
+ insn
.length ();
3473 /* We should now be at the end of the sequence. */
3474 if (cur_step_pc
!= last_addr
)
3477 *next_pc
= cur_step_pc
;
3481 /* This is called just before we want to resume the inferior, if we want to
3482 single-step it but there is no hardware or kernel single-step support. We
3483 find the target of the coming instruction and breakpoint it. */
3485 std::vector
<CORE_ADDR
>
3486 riscv_software_single_step (struct regcache
*regcache
)
3488 CORE_ADDR pc
, next_pc
;
3490 pc
= regcache_read_pc (regcache
);
3492 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
3495 next_pc
= riscv_next_pc (regcache
, pc
);
3500 /* Create RISC-V specific reggroups. */
3503 riscv_init_reggroups ()
3505 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
3508 void _initialize_riscv_tdep ();
3510 _initialize_riscv_tdep ()
3512 riscv_create_csr_aliases ();
3513 riscv_init_reggroups ();
3515 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
3517 /* Add root prefix command for all "set debug riscv" and "show debug
3519 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
3520 _("RISC-V specific debug commands."),
3521 &setdebugriscvcmdlist
, "set debug riscv ", 0,
3524 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
3525 _("RISC-V specific debug commands."),
3526 &showdebugriscvcmdlist
, "show debug riscv ", 0,
3529 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
3530 &riscv_debug_breakpoints
, _("\
3531 Set riscv breakpoint debugging."), _("\
3532 Show riscv breakpoint debugging."), _("\
3533 When non-zero, print debugging information for the riscv specific parts\n\
3534 of the breakpoint mechanism."),
3536 show_riscv_debug_variable
,
3537 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3539 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
3540 &riscv_debug_infcall
, _("\
3541 Set riscv inferior call debugging."), _("\
3542 Show riscv inferior call debugging."), _("\
3543 When non-zero, print debugging information for the riscv specific parts\n\
3544 of the inferior call mechanism."),
3546 show_riscv_debug_variable
,
3547 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3549 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
3550 &riscv_debug_unwinder
, _("\
3551 Set riscv stack unwinding debugging."), _("\
3552 Show riscv stack unwinding debugging."), _("\
3553 When non-zero, print debugging information for the riscv specific parts\n\
3554 of the stack unwinding mechanism."),
3556 show_riscv_debug_variable
,
3557 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3559 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
3560 &riscv_debug_gdbarch
, _("\
3561 Set riscv gdbarch initialisation debugging."), _("\
3562 Show riscv gdbarch initialisation debugging."), _("\
3563 When non-zero, print debugging information for the riscv gdbarch\n\
3564 initialisation process."),
3566 show_riscv_debug_variable
,
3567 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3569 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3570 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
3571 _("RISC-V specific commands."),
3572 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
3574 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
3575 _("RISC-V specific commands."),
3576 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
3579 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
3580 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
3581 &use_compressed_breakpoints
,
3583 Set debugger's use of compressed breakpoints."), _(" \
3584 Show debugger's use of compressed breakpoints."), _("\
3585 Debugging compressed code requires compressed breakpoints to be used. If\n\
3586 left to 'auto' then gdb will use them if the existing instruction is a\n\
3587 compressed instruction. If that doesn't give the correct behavior, then\n\
3588 this option can be used."),
3590 show_use_compressed_breakpoints
,