1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
59 /* The stack must be 16-byte aligned. */
60 #define SP_ALIGNMENT 16
62 /* Forward declarations. */
63 static bool riscv_has_feature (struct gdbarch
*gdbarch
, char feature
);
65 /* Define a series of is_XXX_insn functions to check if the value INSN
66 is an instance of instruction XXX. */
67 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
68 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
70 return (insn & INSN_MASK) == INSN_MATCH; \
72 #include "opcode/riscv-opc.h"
75 /* Cached information about a frame. */
77 struct riscv_unwind_cache
79 /* The register from which we can calculate the frame base. This is
80 usually $sp or $fp. */
83 /* The offset from the current value in register FRAME_BASE_REG to the
84 actual frame base address. */
85 int frame_base_offset
;
87 /* Information about previous register values. */
88 struct trad_frame_saved_reg
*regs
;
90 /* The id for this frame. */
91 struct frame_id this_id
;
93 /* The base (stack) address for this frame. This is the stack pointer
94 value on entry to this frame before any adjustments are made. */
98 /* Architectural name for core registers. */
100 static const char * const riscv_gdb_reg_names
[RISCV_LAST_FP_REGNUM
+ 1] =
102 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
103 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
104 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
105 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
113 /* Maps "pretty" register names onto their GDB register number. */
115 struct register_alias
117 /* The register alias. Usually more descriptive than the
118 architectural name of the register. */
121 /* The GDB register number. */
125 /* Table of register aliases. */
127 static const struct register_alias riscv_register_aliases
[] =
195 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
196 #include "opcode/riscv-opc.h"
200 /* Controls whether we place compressed breakpoints or not. When in auto
201 mode GDB tries to determine if the target supports compressed
202 breakpoints, and uses them if it does. */
204 static enum auto_boolean use_compressed_breakpoints
;
206 /* The show callback for 'show riscv use-compressed-breakpoints'. */
209 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
210 struct cmd_list_element
*c
,
213 fprintf_filtered (file
,
214 _("Debugger's use of compressed breakpoints is set "
218 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
220 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
221 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
223 /* The show callback for the 'show riscv' prefix command. */
226 show_riscv_command (const char *args
, int from_tty
)
228 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
231 /* The set callback for the 'set riscv' prefix command. */
234 set_riscv_command (const char *args
, int from_tty
)
237 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
238 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
241 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
243 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
244 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
246 /* The show callback for the 'show debug riscv' prefix command. */
249 show_debug_riscv_command (const char *args
, int from_tty
)
251 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
254 /* The set callback for the 'set debug riscv' prefix command. */
257 set_debug_riscv_command (const char *args
, int from_tty
)
260 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
261 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
264 /* The show callback for all 'show debug riscv VARNAME' variables. */
267 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
268 struct cmd_list_element
*c
,
271 fprintf_filtered (file
,
272 _("RiscV debug variable `%s' is set to: %s\n"),
276 /* When this is set to non-zero debugging information about breakpoint
277 kinds will be printed. */
279 static unsigned int riscv_debug_breakpoints
= 0;
281 /* When this is set to non-zero debugging information about inferior calls
284 static unsigned int riscv_debug_infcall
= 0;
286 /* When this is set to non-zero debugging information about stack unwinding
289 static unsigned int riscv_debug_unwinder
= 0;
291 /* Read the MISA register from the target. The register will only be read
292 once, and the value read will be cached. If the register can't be read
293 from the target then a default value (0) will be returned. If the
294 pointer READ_P is not null, then the bool pointed to is updated to
295 indicate if the value returned was read from the target (true) or is the
299 riscv_read_misa_reg (bool *read_p
)
303 if (target_has_registers
)
305 struct frame_info
*frame
= get_current_frame ();
309 value
= get_frame_register_unsigned (frame
,
310 RISCV_CSR_MISA_REGNUM
);
312 CATCH (ex
, RETURN_MASK_ERROR
)
314 /* Old cores might have MISA located at a different offset. */
315 value
= get_frame_register_unsigned (frame
,
316 RISCV_CSR_LEGACY_MISA_REGNUM
);
324 /* Return true if FEATURE is available for the architecture GDBARCH. The
325 FEATURE should be one of the single character feature codes described in
326 the RiscV ISA manual, these are between 'A' and 'Z'. */
329 riscv_has_feature (struct gdbarch
*gdbarch
, char feature
)
331 bool have_read_misa
= false;
334 gdb_assert (feature
>= 'A' && feature
<= 'Z');
336 misa
= riscv_read_misa_reg (&have_read_misa
);
337 if (!have_read_misa
|| misa
== 0)
338 misa
= gdbarch_tdep (gdbarch
)->core_features
;
340 return (misa
& (1 << (feature
- 'A'))) != 0;
343 /* Return the width in bytes of the general purpose registers for GDBARCH.
344 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
348 riscv_isa_xlen (struct gdbarch
*gdbarch
)
350 switch (gdbarch_tdep (gdbarch
)->abi
.fields
.base_len
)
353 warning (_("unknown xlen size, assuming 4 bytes"));
364 /* Return the width in bytes of the floating point registers for GDBARCH.
365 If this architecture has no floating point registers, then return 0.
366 Possible values are 4, 8, or 16 for depending on which of single, double
367 or quad floating point support is available. */
370 riscv_isa_flen (struct gdbarch
*gdbarch
)
372 if (riscv_has_feature (gdbarch
, 'Q'))
374 else if (riscv_has_feature (gdbarch
, 'D'))
376 else if (riscv_has_feature (gdbarch
, 'F'))
382 /* Return true if the target for GDBARCH has floating point hardware. */
385 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
387 return (riscv_isa_flen (gdbarch
) > 0);
390 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
393 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
395 return (gdbarch_tdep (gdbarch
)->abi
.fields
.float_abi
!= 0);
398 /* Return true if REGNO is a floating pointer register. */
401 riscv_is_fp_regno_p (int regno
)
403 return (regno
>= RISCV_FIRST_FP_REGNUM
404 && regno
<= RISCV_LAST_FP_REGNUM
);
407 /* Implement the breakpoint_kind_from_pc gdbarch method. */
410 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
412 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
416 /* Read the opcode byte to determine the instruction length. */
417 read_code (*pcptr
, buf
, 1);
419 if (riscv_debug_breakpoints
)
422 "Using %s for breakpoint at %s (instruction length %d)\n",
423 riscv_insn_length (buf
[0]) == 2 ? "C.EBREAK" : "EBREAK",
424 paddress (gdbarch
, *pcptr
), riscv_insn_length (buf
[0]));
425 if (riscv_insn_length (buf
[0]) == 2)
430 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
436 /* Implement the sw_breakpoint_from_kind gdbarch method. */
438 static const gdb_byte
*
439 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
441 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
442 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
452 gdb_assert_not_reached (_("unhandled breakpoint kind"));
456 /* Callback function for user_reg_add. */
458 static struct value
*
459 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
461 const int *reg_p
= (const int *) baton
;
462 return value_of_register (*reg_p
, frame
);
465 /* Implement the register_name gdbarch method. */
468 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
470 /* Prefer to use the alias. */
471 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_REGNUM
)
475 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
476 if (regnum
== riscv_register_aliases
[i
].regnum
)
477 return riscv_register_aliases
[i
].name
;
480 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
481 return riscv_gdb_reg_names
[regnum
];
483 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
487 xsnprintf (buf
, sizeof (buf
), "csr%d",
488 regnum
- RISCV_FIRST_CSR_REGNUM
);
492 if (regnum
== RISCV_PRIV_REGNUM
)
498 /* Implement the register_type gdbarch method. */
501 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
505 if (regnum
< RISCV_FIRST_FP_REGNUM
)
507 if (regnum
== gdbarch_pc_regnum (gdbarch
)
508 || regnum
== RISCV_RA_REGNUM
)
509 return builtin_type (gdbarch
)->builtin_func_ptr
;
511 if (regnum
== RISCV_FP_REGNUM
512 || regnum
== RISCV_SP_REGNUM
513 || regnum
== RISCV_GP_REGNUM
514 || regnum
== RISCV_TP_REGNUM
)
515 return builtin_type (gdbarch
)->builtin_data_ptr
;
517 /* Remaining GPRs vary in size based on the current ISA. */
518 regsize
= riscv_isa_xlen (gdbarch
);
522 return builtin_type (gdbarch
)->builtin_uint32
;
524 return builtin_type (gdbarch
)->builtin_uint64
;
526 return builtin_type (gdbarch
)->builtin_uint128
;
528 internal_error (__FILE__
, __LINE__
,
529 _("unknown isa regsize %i"), regsize
);
532 else if (regnum
<= RISCV_LAST_FP_REGNUM
)
534 regsize
= riscv_isa_xlen (gdbarch
);
538 return builtin_type (gdbarch
)->builtin_float
;
540 return builtin_type (gdbarch
)->builtin_double
;
542 return builtin_type (gdbarch
)->builtin_long_double
;
544 internal_error (__FILE__
, __LINE__
,
545 _("unknown isa regsize %i"), regsize
);
548 else if (regnum
== RISCV_PRIV_REGNUM
)
549 return builtin_type (gdbarch
)->builtin_int8
;
552 if (regnum
== RISCV_CSR_FFLAGS_REGNUM
553 || regnum
== RISCV_CSR_FRM_REGNUM
554 || regnum
== RISCV_CSR_FCSR_REGNUM
)
555 return builtin_type (gdbarch
)->builtin_int32
;
557 regsize
= riscv_isa_xlen (gdbarch
);
561 return builtin_type (gdbarch
)->builtin_int32
;
563 return builtin_type (gdbarch
)->builtin_int64
;
565 return builtin_type (gdbarch
)->builtin_int128
;
567 internal_error (__FILE__
, __LINE__
,
568 _("unknown isa regsize %i"), regsize
);
573 /* Helper for riscv_print_registers_info, prints info for a single register
577 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
578 struct ui_file
*file
,
579 struct frame_info
*frame
,
582 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
583 struct value
*val
= value_of_register (regnum
, frame
);
584 struct type
*regtype
= value_type (val
);
585 int print_raw_format
;
586 enum tab_stops
{ value_column_1
= 15 };
588 fputs_filtered (name
, file
);
589 print_spaces_filtered (value_column_1
- strlen (name
), file
);
591 print_raw_format
= (value_entirely_available (val
)
592 && !value_optimized_out (val
));
594 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
)
596 struct value_print_options opts
;
597 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
598 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
600 get_user_print_options (&opts
);
604 value_embedded_offset (val
), 0,
605 file
, 0, val
, &opts
, current_language
);
607 if (print_raw_format
)
609 fprintf_filtered (file
, "\t(raw ");
610 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
612 fprintf_filtered (file
, ")");
617 struct value_print_options opts
;
619 /* Print the register in hex. */
620 get_formatted_print_options (&opts
, 'x');
623 value_embedded_offset (val
), 0,
624 file
, 0, val
, &opts
, current_language
);
626 if (print_raw_format
)
628 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
631 int size
= register_size (gdbarch
, regnum
);
634 d
= value_as_long (val
);
636 fprintf_filtered (file
,
637 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
638 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
639 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
640 (int) ((d
>> (xlen
- 1)) & 0x1),
641 (int) ((d
>> 24) & 0x1f),
642 (int) ((d
>> 19) & 0x1),
643 (int) ((d
>> 18) & 0x1),
644 (int) ((d
>> 17) & 0x1),
645 (int) ((d
>> 15) & 0x3),
646 (int) ((d
>> 13) & 0x3),
647 (int) ((d
>> 11) & 0x3),
648 (int) ((d
>> 9) & 0x3),
649 (int) ((d
>> 8) & 0x1),
650 (int) ((d
>> 7) & 0x1),
651 (int) ((d
>> 6) & 0x1),
652 (int) ((d
>> 5) & 0x1),
653 (int) ((d
>> 4) & 0x1),
654 (int) ((d
>> 3) & 0x1),
655 (int) ((d
>> 2) & 0x1),
656 (int) ((d
>> 1) & 0x1),
657 (int) ((d
>> 0) & 0x1));
659 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
665 d
= value_as_long (val
);
669 for (; base
> 0; base
--)
671 fprintf_filtered (file
, "\tRV%d", xlen
);
673 for (i
= 0; i
< 26; i
++)
676 fprintf_filtered (file
, "%c", 'A' + i
);
679 else if (regnum
== RISCV_CSR_FCSR_REGNUM
680 || regnum
== RISCV_CSR_FFLAGS_REGNUM
681 || regnum
== RISCV_CSR_FRM_REGNUM
)
685 d
= value_as_long (val
);
687 fprintf_filtered (file
, "\t");
688 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
689 fprintf_filtered (file
,
690 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
691 (int) ((d
>> 5) & 0x7),
692 (int) ((d
>> 4) & 0x1),
693 (int) ((d
>> 3) & 0x1),
694 (int) ((d
>> 2) & 0x1),
695 (int) ((d
>> 1) & 0x1),
696 (int) ((d
>> 0) & 0x1));
698 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
700 static const char * const sfrm
[] =
702 "RNE (round to nearest; ties to even)",
703 "RTZ (Round towards zero)",
704 "RDN (Round down towards -INF)",
705 "RUP (Round up towards +INF)",
706 "RMM (Round to nearest; ties to max magnitude)",
709 "dynamic rounding mode",
711 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
712 ? (d
>> 5) : d
) & 0x3;
714 fprintf_filtered (file
, "%sFRM:%i [%s]",
715 (regnum
== RISCV_CSR_FCSR_REGNUM
720 else if (regnum
== RISCV_PRIV_REGNUM
)
725 d
= value_as_long (val
);
730 static const char * const sprv
[] =
737 fprintf_filtered (file
, "\tprv:%d [%s]",
741 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
745 /* If not a vector register, print it also according to its
747 if (TYPE_VECTOR (regtype
) == 0)
749 get_user_print_options (&opts
);
751 fprintf_filtered (file
, "\t");
753 value_embedded_offset (val
), 0,
754 file
, 0, val
, &opts
, current_language
);
759 fprintf_filtered (file
, "\n");
762 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
766 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
767 struct reggroup
*reggroup
)
771 /* Used by 'info registers' and 'info registers <groupname>'. */
773 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
774 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
777 if (reggroup
== all_reggroup
)
779 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
781 /* Only include CSRs that have aliases. */
782 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
784 if (regnum
== riscv_register_aliases
[i
].regnum
)
789 else if (reggroup
== float_reggroup
)
790 return (riscv_is_fp_regno_p (regnum
)
791 || regnum
== RISCV_CSR_FCSR_REGNUM
792 || regnum
== RISCV_CSR_FFLAGS_REGNUM
793 || regnum
== RISCV_CSR_FRM_REGNUM
);
794 else if (reggroup
== general_reggroup
)
795 return regnum
< RISCV_FIRST_FP_REGNUM
;
796 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
798 if (riscv_has_fp_regs (gdbarch
))
799 return regnum
<= RISCV_LAST_FP_REGNUM
;
801 return regnum
< RISCV_FIRST_FP_REGNUM
;
803 else if (reggroup
== system_reggroup
)
805 if (regnum
== RISCV_PRIV_REGNUM
)
807 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
809 /* Only include CSRs that have aliases. */
810 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
812 if (regnum
== riscv_register_aliases
[i
].regnum
)
817 else if (reggroup
== vector_reggroup
)
823 /* Implement the print_registers_info gdbarch method. This is used by
824 'info registers' and 'info all-registers'. */
827 riscv_print_registers_info (struct gdbarch
*gdbarch
,
828 struct ui_file
*file
,
829 struct frame_info
*frame
,
830 int regnum
, int print_all
)
834 /* Print one specified register. */
835 gdb_assert (regnum
<= RISCV_LAST_REGNUM
);
836 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
837 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
838 error (_("Not a valid register for the current processor type"));
839 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
843 struct reggroup
*reggroup
;
846 reggroup
= all_reggroup
;
848 reggroup
= general_reggroup
;
850 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
852 /* Zero never changes, so might as well hide by default. */
853 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
856 /* Registers with no name are not valid on this ISA. */
857 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
858 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
861 /* Is the register in the group we're interested in? */
862 if (!riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
))
865 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
870 /* Class that handles one decoded RiscV instruction. */
876 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
879 /* Unknown value is used at initialisation time. */
882 /* These instructions are all the ones we are interested in during the
892 /* These are needed for software breakopint support. */
901 /* These are needed for stepping over atomic sequences. */
905 /* Other instructions are not interesting during the prologue scan, and
920 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
922 /* Get the length of the instruction in bytes. */
926 /* Get the opcode for this instruction. */
927 enum opcode
opcode () const
930 /* Get destination register field for this instruction. This is only
931 valid if the OPCODE implies there is such a field for this
936 /* Get the RS1 register field for this instruction. This is only valid
937 if the OPCODE implies there is such a field for this instruction. */
941 /* Get the RS2 register field for this instruction. This is only valid
942 if the OPCODE implies there is such a field for this instruction. */
946 /* Get the immediate for this instruction in signed form. This is only
947 valid if the OPCODE implies there is such a field for this
949 int imm_signed () const
954 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
955 int decode_register_index (unsigned long opcode
, int offset
)
957 return (opcode
>> offset
) & 0x1F;
960 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
961 int decode_register_index_short (unsigned long opcode
, int offset
)
963 return ((opcode
>> offset
) & 0x7) + 8;
966 /* Helper for DECODE, decode 32-bit R-type instruction. */
967 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
970 m_rd
= decode_register_index (ival
, OP_SH_RD
);
971 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
972 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
975 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
976 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
979 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
980 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
983 /* Helper for DECODE, decode 32-bit I-type instruction. */
984 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
987 m_rd
= decode_register_index (ival
, OP_SH_RD
);
988 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
989 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
992 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
993 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
996 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
997 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
1000 /* Helper for DECODE, decode 32-bit S-type instruction. */
1001 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1004 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1005 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1006 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1009 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1010 encoding is different for each CS format instruction, so extracting
1011 the immediate is left up to the caller, who should pass the extracted
1012 immediate value through in IMM. */
1013 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1017 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1018 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1021 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1022 encoding is different for each CSS format instruction, so extracting
1023 the immediate is left up to the caller, who should pass the extracted
1024 immediate value through in IMM. */
1025 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1029 m_rs1
= RISCV_SP_REGNUM
;
1030 /* Not a compressed register number in this case. */
1031 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1034 /* Helper for DECODE, decode 32-bit U-type instruction. */
1035 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1038 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1039 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1042 /* Helper for DECODE, decode 32-bit J-type instruction. */
1043 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1046 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1047 m_imm
.s
= EXTRACT_UJTYPE_IMM (ival
);
1050 /* Helper for DECODE, decode 32-bit J-type instruction. */
1051 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1054 m_imm
.s
= EXTRACT_RVC_J_IMM (ival
);
1057 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1060 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1061 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1062 m_imm
.s
= EXTRACT_SBTYPE_IMM (ival
);
1065 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1068 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1069 m_imm
.s
= EXTRACT_RVC_B_IMM (ival
);
1072 /* Fetch instruction from target memory at ADDR, return the content of
1073 the instruction, and update LEN with the instruction length. */
1074 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1075 CORE_ADDR addr
, int *len
);
1077 /* The length of the instruction in bytes. Should be 2 or 4. */
1080 /* The instruction opcode. */
1081 enum opcode m_opcode
;
1083 /* The three possible registers an instruction might reference. Not
1084 every instruction fills in all of these registers. Which fields are
1085 valid depends on the opcode. The naming of these fields matches the
1086 naming in the riscv isa manual. */
1091 /* Possible instruction immediate. This is only valid if the instruction
1092 format contains an immediate, not all instruction, whether this is
1093 valid depends on the opcode. Despite only having one format for now
1094 the immediate is packed into a union, later instructions might require
1095 an unsigned formatted immediate, having the union in place now will
1096 reduce the need for code churn later. */
1097 union riscv_insn_immediate
1099 riscv_insn_immediate ()
1109 /* Fetch instruction from target memory at ADDR, return the content of the
1110 instruction, and update LEN with the instruction length. */
1113 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1114 CORE_ADDR addr
, int *len
)
1116 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1118 int instlen
, status
;
1120 /* All insns are at least 16 bits. */
1121 status
= target_read_memory (addr
, buf
, 2);
1123 memory_error (TARGET_XFER_E_IO
, addr
);
1125 /* If we need more, grab it now. */
1126 instlen
= riscv_insn_length (buf
[0]);
1127 gdb_assert (instlen
<= sizeof (buf
));
1132 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1134 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1137 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1140 /* Fetch from target memory an instruction at PC and decode it. */
1143 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1147 /* Fetch the instruction, and the instructions length. */
1148 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1152 if (is_add_insn (ival
))
1153 decode_r_type_insn (ADD
, ival
);
1154 else if (is_addw_insn (ival
))
1155 decode_r_type_insn (ADDW
, ival
);
1156 else if (is_addi_insn (ival
))
1157 decode_i_type_insn (ADDI
, ival
);
1158 else if (is_addiw_insn (ival
))
1159 decode_i_type_insn (ADDIW
, ival
);
1160 else if (is_auipc_insn (ival
))
1161 decode_u_type_insn (AUIPC
, ival
);
1162 else if (is_lui_insn (ival
))
1163 decode_u_type_insn (LUI
, ival
);
1164 else if (is_sd_insn (ival
))
1165 decode_s_type_insn (SD
, ival
);
1166 else if (is_sw_insn (ival
))
1167 decode_s_type_insn (SW
, ival
);
1168 else if (is_jal_insn (ival
))
1169 decode_j_type_insn (JAL
, ival
);
1170 else if (is_jalr_insn (ival
))
1171 decode_i_type_insn (JALR
, ival
);
1172 else if (is_beq_insn (ival
))
1173 decode_b_type_insn (BEQ
, ival
);
1174 else if (is_bne_insn (ival
))
1175 decode_b_type_insn (BNE
, ival
);
1176 else if (is_blt_insn (ival
))
1177 decode_b_type_insn (BLT
, ival
);
1178 else if (is_bge_insn (ival
))
1179 decode_b_type_insn (BGE
, ival
);
1180 else if (is_bltu_insn (ival
))
1181 decode_b_type_insn (BLTU
, ival
);
1182 else if (is_bgeu_insn (ival
))
1183 decode_b_type_insn (BGEU
, ival
);
1184 else if (is_lr_w_insn (ival
))
1185 decode_r_type_insn (LR
, ival
);
1186 else if (is_lr_d_insn (ival
))
1187 decode_r_type_insn (LR
, ival
);
1188 else if (is_sc_w_insn (ival
))
1189 decode_r_type_insn (SC
, ival
);
1190 else if (is_sc_d_insn (ival
))
1191 decode_r_type_insn (SC
, ival
);
1193 /* None of the other fields are valid in this case. */
1196 else if (m_length
== 2)
1198 int xlen
= riscv_isa_xlen (gdbarch
);
1200 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1201 C_JALR. So must try to match C_JALR first as it has more bits in
1203 if (is_c_jalr_insn (ival
))
1204 decode_cr_type_insn (JALR
, ival
);
1205 else if (is_c_add_insn (ival
))
1206 decode_cr_type_insn (ADD
, ival
);
1207 /* C_ADDW is RV64 and RV128 only. */
1208 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1209 decode_cr_type_insn (ADDW
, ival
);
1210 else if (is_c_addi_insn (ival
))
1211 decode_ci_type_insn (ADDI
, ival
);
1212 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1213 only and C_JAL is RV32 only. */
1214 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1215 decode_ci_type_insn (ADDIW
, ival
);
1216 else if (xlen
== 4 && is_c_jal_insn (ival
))
1217 decode_cj_type_insn (JAL
, ival
);
1218 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1219 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1221 else if (is_c_addi16sp_insn (ival
))
1224 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1225 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1227 else if (is_c_addi4spn_insn (ival
))
1230 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1231 m_rs1
= RISCV_SP_REGNUM
;
1232 m_imm
.s
= EXTRACT_RVC_ADDI4SPN_IMM (ival
);
1234 else if (is_c_lui_insn (ival
))
1237 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1238 m_imm
.s
= EXTRACT_RVC_LUI_IMM (ival
);
1240 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1241 and C_FSW is RV32 only. */
1242 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1243 decode_cs_type_insn (SD
, ival
, EXTRACT_RVC_LD_IMM (ival
));
1244 else if (is_c_sw_insn (ival
))
1245 decode_cs_type_insn (SW
, ival
, EXTRACT_RVC_LW_IMM (ival
));
1246 else if (is_c_swsp_insn (ival
))
1247 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SWSP_IMM (ival
));
1248 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1249 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SDSP_IMM (ival
));
1250 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1251 So must try to match C_JR first as it ahs more bits in mask. */
1252 else if (is_c_jr_insn (ival
))
1253 decode_cr_type_insn (JALR
, ival
);
1254 else if (is_c_j_insn (ival
))
1255 decode_cj_type_insn (JAL
, ival
);
1256 else if (is_c_beqz_insn (ival
))
1257 decode_cb_type_insn (BEQ
, ival
);
1258 else if (is_c_bnez_insn (ival
))
1259 decode_cb_type_insn (BNE
, ival
);
1261 /* None of the other fields of INSN are valid in this case. */
1265 internal_error (__FILE__
, __LINE__
,
1266 _("unable to decode %d byte instructions in "
1267 "prologue at %s"), m_length
,
1268 core_addr_to_string (pc
));
1271 /* The prologue scanner. This is currently only used for skipping the
1272 prologue of a function when the DWARF information is not sufficient.
1273 However, it is written with filling of the frame cache in mind, which
1274 is why different groups of stack setup instructions are split apart
1275 during the core of the inner loop. In the future, the intention is to
1276 extend this function to fully support building up a frame cache that
1277 can unwind register values when there is no DWARF information. */
1280 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1281 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1282 struct riscv_unwind_cache
*cache
)
1284 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1285 CORE_ADDR end_prologue_addr
= 0;
1287 /* Find an upper limit on the function prologue using the debug
1288 information. If the debug information could not be used to provide
1289 that bound, then use an arbitrary large number as the upper bound. */
1290 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1291 if (after_prologue_pc
== 0)
1292 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1293 if (after_prologue_pc
< end_pc
)
1294 end_pc
= after_prologue_pc
;
1296 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1297 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1298 regs
[regno
] = pv_register (regno
, 0);
1299 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1301 if (riscv_debug_unwinder
)
1304 "Prologue scan for function starting at %s (limit %s)\n",
1305 core_addr_to_string (start_pc
),
1306 core_addr_to_string (end_pc
));
1308 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1310 struct riscv_insn insn
;
1312 /* Decode the current instruction, and decide where the next
1313 instruction lives based on the size of this instruction. */
1314 insn
.decode (gdbarch
, cur_pc
);
1315 gdb_assert (insn
.length () > 0);
1316 next_pc
= cur_pc
+ insn
.length ();
1318 /* Look for common stack adjustment insns. */
1319 if ((insn
.opcode () == riscv_insn::ADDI
1320 || insn
.opcode () == riscv_insn::ADDIW
)
1321 && insn
.rd () == RISCV_SP_REGNUM
1322 && insn
.rs1 () == RISCV_SP_REGNUM
)
1324 /* Handle: addi sp, sp, -i
1325 or: addiw sp, sp, -i */
1326 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1327 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1329 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1331 else if ((insn
.opcode () == riscv_insn::SW
1332 || insn
.opcode () == riscv_insn::SD
)
1333 && (insn
.rs1 () == RISCV_SP_REGNUM
1334 || insn
.rs1 () == RISCV_FP_REGNUM
))
1336 /* Handle: sw reg, offset(sp)
1337 or: sd reg, offset(sp)
1338 or: sw reg, offset(s0)
1339 or: sd reg, offset(s0) */
1340 /* Instruction storing a register onto the stack. */
1341 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1342 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1343 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
1344 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
1347 else if (insn
.opcode () == riscv_insn::ADDI
1348 && insn
.rd () == RISCV_FP_REGNUM
1349 && insn
.rs1 () == RISCV_SP_REGNUM
)
1351 /* Handle: addi s0, sp, size */
1352 /* Instructions setting up the frame pointer. */
1353 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1354 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1356 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1358 else if ((insn
.opcode () == riscv_insn::ADD
1359 || insn
.opcode () == riscv_insn::ADDW
)
1360 && insn
.rd () == RISCV_FP_REGNUM
1361 && insn
.rs1 () == RISCV_SP_REGNUM
1362 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1364 /* Handle: add s0, sp, 0
1365 or: addw s0, sp, 0 */
1366 /* Instructions setting up the frame pointer. */
1367 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1368 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1369 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
1371 else if ((insn
.opcode () == riscv_insn::ADDI
1372 && insn
.rd () == RISCV_ZERO_REGNUM
1373 && insn
.rs1 () == RISCV_ZERO_REGNUM
1374 && insn
.imm_signed () == 0))
1376 /* Handle: add x0, x0, 0 (NOP) */
1378 else if (insn
.opcode () == riscv_insn::AUIPC
)
1380 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1381 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
1383 else if (insn
.opcode () == riscv_insn::LUI
)
1385 /* Handle: lui REG, n
1386 Where REG is not gp register. */
1387 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1388 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
1390 else if (insn
.opcode () == riscv_insn::ADDI
)
1392 /* Handle: addi REG1, REG2, IMM */
1393 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1394 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1396 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1398 else if (insn
.opcode () == riscv_insn::ADD
)
1400 /* Handle: addi REG1, REG2, IMM */
1401 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1402 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1403 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1404 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
1408 end_prologue_addr
= cur_pc
;
1413 if (end_prologue_addr
== 0)
1414 end_prologue_addr
= cur_pc
;
1416 if (riscv_debug_unwinder
)
1417 fprintf_unfiltered (gdb_stdlog
, "End of prologue at %s\n",
1418 core_addr_to_string (end_prologue_addr
));
1422 /* Figure out if it is a frame pointer or just a stack pointer. Also
1423 the offset held in the pv_t is from the original register value to
1424 the current value, which for a grows down stack means a negative
1425 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1426 from the current value to the original value. */
1427 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
1429 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
1430 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
1434 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
1435 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
1438 /* Assign offset from old SP to all saved registers. As we don't
1439 have the previous value for the frame base register at this
1440 point, we store the offset as the address in the trad_frame, and
1441 then convert this to an actual address later. */
1442 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
1445 if (stack
.find_reg (gdbarch
, i
, &offset
))
1447 if (riscv_debug_unwinder
)
1448 fprintf_unfiltered (gdb_stdlog
,
1449 "Register $%s at stack offset %ld\n",
1450 gdbarch_register_name (gdbarch
, i
),
1452 trad_frame_set_addr (cache
->regs
, i
, offset
);
1457 return end_prologue_addr
;
1460 /* Implement the riscv_skip_prologue gdbarch method. */
1463 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1465 CORE_ADDR func_addr
;
1467 /* See if we can determine the end of the prologue via the symbol
1468 table. If so, then return either PC, or the PC after the
1469 prologue, whichever is greater. */
1470 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1472 CORE_ADDR post_prologue_pc
1473 = skip_prologue_using_sal (gdbarch
, func_addr
);
1475 if (post_prologue_pc
!= 0)
1476 return std::max (pc
, post_prologue_pc
);
1479 /* Can't determine prologue from the symbol table, need to examine
1480 instructions. Pass -1 for the end address to indicate the prologue
1481 scanner can scan as far as it needs to find the end of the prologue. */
1482 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
1485 /* Implement the gdbarch push dummy code callback. */
1488 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1489 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1490 struct type
*value_type
, CORE_ADDR
*real_pc
,
1491 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1493 /* Allocate space for a breakpoint, and keep the stack correctly
1501 /* Compute the alignment of the type T. Used while setting up the
1502 arguments for a dummy call. */
1505 riscv_type_alignment (struct type
*t
)
1507 t
= check_typedef (t
);
1508 switch (TYPE_CODE (t
))
1511 error (_("Could not compute alignment of type"));
1513 case TYPE_CODE_RVALUE_REF
:
1515 case TYPE_CODE_ENUM
:
1519 case TYPE_CODE_CHAR
:
1520 case TYPE_CODE_BOOL
:
1521 return TYPE_LENGTH (t
);
1523 case TYPE_CODE_ARRAY
:
1524 case TYPE_CODE_COMPLEX
:
1525 return riscv_type_alignment (TYPE_TARGET_TYPE (t
));
1527 case TYPE_CODE_STRUCT
:
1528 case TYPE_CODE_UNION
:
1533 for (i
= 0; i
< TYPE_NFIELDS (t
); ++i
)
1535 if (TYPE_FIELD_LOC_KIND (t
, i
) == FIELD_LOC_KIND_BITPOS
)
1537 int a
= riscv_type_alignment (TYPE_FIELD_TYPE (t
, i
));
1547 /* Holds information about a single argument either being passed to an
1548 inferior function, or returned from an inferior function. This includes
1549 information about the size, type, etc of the argument, and also
1550 information about how the argument will be passed (or returned). */
1552 struct riscv_arg_info
1554 /* Contents of the argument. */
1555 const gdb_byte
*contents
;
1557 /* Length of argument. */
1560 /* Alignment required for an argument of this type. */
1563 /* The type for this argument. */
1566 /* Each argument can have either 1 or 2 locations assigned to it. Each
1567 location describes where part of the argument will be placed. The
1568 second location is valid based on the LOC_TYPE and C_LENGTH fields
1569 of the first location (which is always valid). */
1572 /* What type of location this is. */
1575 /* Argument passed in a register. */
1578 /* Argument passed as an on stack argument. */
1581 /* Argument passed by reference. The second location is always
1582 valid for a BY_REF argument, and describes where the address
1583 of the BY_REF argument should be placed. */
1587 /* Information that depends on the location type. */
1590 /* Which register number to use. */
1593 /* The offset into the stack region. */
1597 /* The length of contents covered by this location. If this is less
1598 than the total length of the argument, then the second location
1599 will be valid, and will describe where the rest of the argument
1603 /* The offset within CONTENTS for this part of the argument. Will
1604 always be 0 for the first part. For the second part of the
1605 argument, this might be the C_LENGTH value of the first part,
1606 however, if we are passing a structure in two registers, and there's
1607 is padding between the first and second field, then this offset
1608 might be greater than the length of the first argument part. When
1609 the second argument location is not holding part of the argument
1610 value, but is instead holding the address of a reference argument,
1611 then this offset will be set to 0. */
1616 /* Information about a set of registers being used for passing arguments as
1617 part of a function call. The register set must be numerically
1618 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1619 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1621 struct riscv_arg_reg
1623 riscv_arg_reg (int first
, int last
)
1624 : next_regnum (first
),
1630 /* The GDB register number to use in this set. */
1633 /* The last GDB register number to use in this set. */
1637 /* Arguments can be passed as on stack arguments, or by reference. The
1638 on stack arguments must be in a continuous region starting from $sp,
1639 while the by reference arguments can be anywhere, but we'll put them
1640 on the stack after (at higher address) the on stack arguments.
1642 This might not be the right approach to take. The ABI is clear that
1643 an argument passed by reference can be modified by the callee, which
1644 us placing the argument (temporarily) onto the stack will not achieve
1645 (changes will be lost). There's also the possibility that very large
1646 arguments could overflow the stack.
1648 This struct is used to track offset into these two areas for where
1649 arguments are to be placed. */
1650 struct riscv_memory_offsets
1652 riscv_memory_offsets ()
1659 /* Offset into on stack argument area. */
1662 /* Offset into the pass by reference area. */
1666 /* Holds information about where arguments to a call will be placed. This
1667 is updated as arguments are added onto the call, and can be used to
1668 figure out where the next argument should be placed. */
1670 struct riscv_call_info
1672 riscv_call_info (struct gdbarch
*gdbarch
)
1673 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1674 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1676 xlen
= riscv_isa_xlen (gdbarch
);
1677 flen
= riscv_isa_flen (gdbarch
);
1679 /* Disable use of floating point registers if needed. */
1680 if (!riscv_has_fp_abi (gdbarch
))
1681 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1684 /* Track the memory areas used for holding in-memory arguments to a
1686 struct riscv_memory_offsets memory
;
1688 /* Holds information about the next integer register to use for passing
1690 struct riscv_arg_reg int_regs
;
1692 /* Holds information about the next floating point register to use for
1693 passing an argument. */
1694 struct riscv_arg_reg float_regs
;
1696 /* The XLEN and FLEN are copied in to this structure for convenience, and
1697 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1702 /* Return the number of registers available for use as parameters in the
1703 register set REG. Returned value can be 0 or more. */
1706 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1708 if (reg
->next_regnum
> reg
->last_regnum
)
1711 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1714 /* If there is at least one register available in the register set REG then
1715 the next register from REG is assigned to LOC and the length field of
1716 LOC is updated to LENGTH. The register set REG is updated to indicate
1717 that the assigned register is no longer available and the function
1720 If there are no registers available in REG then the function returns
1721 false, and LOC and REG are unchanged. */
1724 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1725 struct riscv_arg_reg
*reg
,
1726 int length
, int offset
)
1728 if (reg
->next_regnum
<= reg
->last_regnum
)
1730 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1731 loc
->loc_data
.regno
= reg
->next_regnum
;
1733 loc
->c_length
= length
;
1734 loc
->c_offset
= offset
;
1741 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1742 record that an area of stack has been used to hold the parameter
1745 The length field of LOC is updated to LENGTH, the length of the
1746 parameter being stored, and ALIGN is the alignment required by the
1747 parameter, which will affect how memory is allocated out of MEMORY. */
1750 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1751 struct riscv_memory_offsets
*memory
,
1752 int length
, int align
)
1754 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1756 = align_up (memory
->arg_offset
, align
);
1757 loc
->loc_data
.offset
= memory
->arg_offset
;
1758 memory
->arg_offset
+= length
;
1759 loc
->c_length
= length
;
1761 /* Offset is always 0, either we're the first location part, in which
1762 case we're reading content from the start of the argument, or we're
1763 passing the address of a reference argument, so 0. */
1767 /* Update AINFO, which describes an argument that should be passed or
1768 returned using the integer ABI. The argloc fields within AINFO are
1769 updated to describe the location in which the argument will be passed to
1770 a function, or returned from a function.
1772 The CINFO structure contains the ongoing call information, the holds
1773 information such as which argument registers are remaining to be
1774 assigned to parameter, and how much memory has been used by parameters
1777 By examining the state of CINFO a suitable location can be selected,
1778 and assigned to AINFO. */
1781 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1782 struct riscv_call_info
*cinfo
)
1784 if (ainfo
->length
> (2 * cinfo
->xlen
))
1786 /* Argument is going to be passed by reference. */
1787 ainfo
->argloc
[0].loc_type
1788 = riscv_arg_info::location::by_ref
;
1789 cinfo
->memory
.ref_offset
1790 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1791 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1792 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1793 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1795 /* The second location for this argument is given over to holding the
1796 address of the by-reference data. Pass 0 for the offset as this
1797 is not part of the actual argument value. */
1798 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1801 riscv_assign_stack_location (&ainfo
->argloc
[1],
1802 &cinfo
->memory
, cinfo
->xlen
,
1807 int len
= (ainfo
->length
> cinfo
->xlen
) ? cinfo
->xlen
: ainfo
->length
;
1809 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1810 &cinfo
->int_regs
, len
, 0))
1811 riscv_assign_stack_location (&ainfo
->argloc
[0],
1812 &cinfo
->memory
, len
, ainfo
->align
);
1814 if (len
< ainfo
->length
)
1816 len
= ainfo
->length
- len
;
1817 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1818 &cinfo
->int_regs
, len
,
1820 riscv_assign_stack_location (&ainfo
->argloc
[1],
1821 &cinfo
->memory
, len
, cinfo
->xlen
);
1826 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1827 is being passed with the floating point ABI. */
1830 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1831 struct riscv_call_info
*cinfo
)
1833 if (ainfo
->length
> cinfo
->flen
)
1834 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1837 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1840 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1844 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1845 is a complex floating point argument, and is therefore handled
1846 differently to other argument types. */
1849 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1850 struct riscv_call_info
*cinfo
)
1852 if (ainfo
->length
<= (2 * cinfo
->flen
)
1853 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1856 int len
= ainfo
->length
/ 2;
1858 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1859 &cinfo
->float_regs
, len
, len
);
1860 gdb_assert (result
);
1862 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1863 &cinfo
->float_regs
, len
, len
);
1864 gdb_assert (result
);
1867 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1870 /* A structure used for holding information about a structure type within
1871 the inferior program. The RiscV ABI has special rules for handling some
1872 structures with a single field or with two fields. The counting of
1873 fields here is done after flattening out all nested structures. */
1875 class riscv_struct_info
1878 riscv_struct_info ()
1879 : m_number_of_fields (0),
1880 m_types
{ nullptr, nullptr }
1885 /* Analyse TYPE descending into nested structures, count the number of
1886 scalar fields and record the types of the first two fields found. */
1887 void analyse (struct type
*type
);
1889 /* The number of scalar fields found in the analysed type. This is
1890 currently only accurate if the value returned is 0, 1, or 2 as the
1891 analysis stops counting when the number of fields is 3. This is
1892 because the RiscV ABI only has special cases for 1 or 2 fields,
1893 anything else we just don't care about. */
1894 int number_of_fields () const
1895 { return m_number_of_fields
; }
1897 /* Return the type for scalar field INDEX within the analysed type. Will
1898 return nullptr if there is no field at that index. Only INDEX values
1899 0 and 1 can be requested as the RiscV ABI only has special cases for
1900 structures with 1 or 2 fields. */
1901 struct type
*field_type (int index
) const
1903 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
1904 return m_types
[index
];
1908 /* The number of scalar fields found within the structure after recursing
1909 into nested structures. */
1910 int m_number_of_fields
;
1912 /* The types of the first two scalar fields found within the structure
1913 after recursing into nested structures. */
1914 struct type
*m_types
[2];
1917 /* Analyse TYPE descending into nested structures, count the number of
1918 scalar fields and record the types of the first two fields found. */
1921 riscv_struct_info::analyse (struct type
*type
)
1923 unsigned int count
= TYPE_NFIELDS (type
);
1926 for (i
= 0; i
< count
; ++i
)
1928 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
1931 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
1932 field_type
= check_typedef (field_type
);
1934 switch (TYPE_CODE (field_type
))
1936 case TYPE_CODE_STRUCT
:
1937 analyse (field_type
);
1941 /* RiscV only flattens out structures. Anything else does not
1942 need to be flattened, we just record the type, and when we
1943 look at the analysis results we'll realise this is not a
1944 structure we can special case, and pass the structure in
1946 if (m_number_of_fields
< 2)
1947 m_types
[m_number_of_fields
] = field_type
;
1948 m_number_of_fields
++;
1952 /* RiscV only has special handling for structures with 1 or 2 scalar
1953 fields, any more than that and the structure is just passed in
1954 memory. We can safely drop out early when we find 3 or more
1957 if (m_number_of_fields
> 2)
1962 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1963 is a structure. Small structures on RiscV have some special case
1964 handling in order that the structure might be passed in register.
1965 Larger structures are passed in memory. After assigning location
1966 information to AINFO, CINFO will have been updated. */
1969 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
1970 struct riscv_call_info
*cinfo
)
1972 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
1974 struct riscv_struct_info sinfo
;
1976 sinfo
.analyse (ainfo
->type
);
1977 if (sinfo
.number_of_fields () == 1
1978 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
1980 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1981 == TYPE_LENGTH (sinfo
.field_type (0)));
1982 return riscv_call_arg_complex_float (ainfo
, cinfo
);
1985 if (sinfo
.number_of_fields () == 1
1986 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
1988 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1989 == TYPE_LENGTH (sinfo
.field_type (0)));
1990 return riscv_call_arg_scalar_float (ainfo
, cinfo
);
1993 if (sinfo
.number_of_fields () == 2
1994 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1995 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1996 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1997 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
1998 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2000 int len0
, len1
, offset
;
2002 gdb_assert (TYPE_LENGTH (ainfo
->type
) <= (2 * cinfo
->flen
));
2004 len0
= TYPE_LENGTH (sinfo
.field_type (0));
2005 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2006 &cinfo
->float_regs
, len0
, 0))
2007 error (_("failed during argument setup"));
2009 len1
= TYPE_LENGTH (sinfo
.field_type (1));
2010 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
2011 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
2012 - TYPE_LENGTH (sinfo
.field_type (0))));
2014 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2017 error (_("failed during argument setup"));
2021 if (sinfo
.number_of_fields () == 2
2022 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2023 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
2024 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2025 && is_integral_type (sinfo
.field_type (1))
2026 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
2028 int len0
, len1
, offset
;
2030 gdb_assert (TYPE_LENGTH (ainfo
->type
)
2031 <= (cinfo
->flen
+ cinfo
->xlen
));
2033 len0
= TYPE_LENGTH (sinfo
.field_type (0));
2034 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2035 &cinfo
->float_regs
, len0
, 0))
2036 error (_("failed during argument setup"));
2038 len1
= TYPE_LENGTH (sinfo
.field_type (1));
2039 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
2040 gdb_assert (len1
<= cinfo
->xlen
);
2041 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2042 &cinfo
->int_regs
, len1
, offset
))
2043 error (_("failed during argument setup"));
2047 if (sinfo
.number_of_fields () == 2
2048 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2049 && (is_integral_type (sinfo
.field_type (0))
2050 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
2051 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
2052 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
2054 int len0
, len1
, offset
;
2056 gdb_assert (TYPE_LENGTH (ainfo
->type
)
2057 <= (cinfo
->flen
+ cinfo
->xlen
));
2059 len0
= TYPE_LENGTH (sinfo
.field_type (0));
2060 len1
= TYPE_LENGTH (sinfo
.field_type (1));
2061 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
2063 gdb_assert (len0
<= cinfo
->xlen
);
2064 gdb_assert (len1
<= cinfo
->flen
);
2066 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2067 &cinfo
->int_regs
, len0
, 0))
2068 error (_("failed during argument setup"));
2070 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2073 error (_("failed during argument setup"));
2079 /* Non of the structure flattening cases apply, so we just pass using
2081 ainfo
->length
= align_up (ainfo
->length
, cinfo
->xlen
);
2082 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2085 /* Assign a location to call (or return) argument AINFO, the location is
2086 selected from CINFO which holds information about what call argument
2087 locations are available for use next. The TYPE is the type of the
2088 argument being passed, this information is recorded into AINFO (along
2089 with some additional information derived from the type).
2091 After assigning a location to AINFO, CINFO will have been updated. */
2094 riscv_arg_location (struct gdbarch
*gdbarch
,
2095 struct riscv_arg_info
*ainfo
,
2096 struct riscv_call_info
*cinfo
,
2100 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
2101 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
2102 ainfo
->contents
= nullptr;
2104 switch (TYPE_CODE (ainfo
->type
))
2107 case TYPE_CODE_BOOL
:
2108 case TYPE_CODE_CHAR
:
2109 case TYPE_CODE_RANGE
:
2110 case TYPE_CODE_ENUM
:
2112 if (ainfo
->length
<= cinfo
->xlen
)
2114 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2115 ainfo
->length
= cinfo
->xlen
;
2117 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2119 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2120 ainfo
->length
= 2 * cinfo
->xlen
;
2123 /* Recalculate the alignment requirement. */
2124 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
2125 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2129 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2132 case TYPE_CODE_COMPLEX
:
2133 riscv_call_arg_complex_float (ainfo
, cinfo
);
2136 case TYPE_CODE_STRUCT
:
2137 riscv_call_arg_struct (ainfo
, cinfo
);
2141 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2146 /* Used for printing debug information about the call argument location in
2147 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2148 addresses for the location of pass-by-reference and
2149 arguments-on-the-stack memory areas. */
2152 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2153 struct riscv_arg_info
*info
,
2154 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2156 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2157 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2158 switch (info
->argloc
[0].loc_type
)
2160 case riscv_arg_info::location::in_reg
:
2162 (stream
, ", register %s",
2163 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2164 if (info
->argloc
[0].c_length
< info
->length
)
2166 switch (info
->argloc
[1].loc_type
)
2168 case riscv_arg_info::location::in_reg
:
2170 (stream
, ", register %s",
2171 gdbarch_register_name (gdbarch
,
2172 info
->argloc
[1].loc_data
.regno
));
2175 case riscv_arg_info::location::on_stack
:
2176 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2177 info
->argloc
[1].loc_data
.offset
);
2180 case riscv_arg_info::location::by_ref
:
2182 /* The second location should never be a reference, any
2183 argument being passed by reference just places its address
2184 in the first location and is done. */
2185 error (_("invalid argument location"));
2189 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2190 fprintf_unfiltered (stream
, " (offset 0x%x)",
2191 info
->argloc
[1].c_offset
);
2195 case riscv_arg_info::location::on_stack
:
2196 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2197 info
->argloc
[0].loc_data
.offset
);
2200 case riscv_arg_info::location::by_ref
:
2202 (stream
, ", by reference, data at offset 0x%x (%s)",
2203 info
->argloc
[0].loc_data
.offset
,
2204 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2205 if (info
->argloc
[1].loc_type
2206 == riscv_arg_info::location::in_reg
)
2208 (stream
, ", address in register %s",
2209 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2212 gdb_assert (info
->argloc
[1].loc_type
2213 == riscv_arg_info::location::on_stack
);
2215 (stream
, ", address on stack at offset 0x%x (%s)",
2216 info
->argloc
[1].loc_data
.offset
,
2217 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2222 gdb_assert_not_reached (_("unknown argument location type"));
2226 /* Implement the push dummy call gdbarch callback. */
2229 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2230 struct value
*function
,
2231 struct regcache
*regcache
,
2234 struct value
**args
,
2237 CORE_ADDR struct_addr
)
2240 CORE_ADDR sp_args
, sp_refs
;
2241 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2243 struct riscv_arg_info
*arg_info
=
2244 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2245 struct riscv_arg_info
*info
;
2247 struct riscv_call_info
call_info (gdbarch
);
2251 /* We'll use register $a0 if we're returning a struct. */
2253 ++call_info
.int_regs
.next_regnum
;
2255 for (i
= 0, info
= &arg_info
[0];
2259 struct value
*arg_value
;
2260 struct type
*arg_type
;
2262 arg_value
= args
[i
];
2263 arg_type
= check_typedef (value_type (arg_value
));
2265 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
);
2267 if (info
->type
!= arg_type
)
2268 arg_value
= value_cast (info
->type
, arg_value
);
2269 info
->contents
= value_contents (arg_value
);
2272 /* Adjust the stack pointer and align it. */
2273 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2274 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2276 if (riscv_debug_infcall
> 0)
2278 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2279 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2280 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2281 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2282 call_info
.xlen
, call_info
.flen
);
2284 fprintf_unfiltered (gdb_stdlog
,
2285 "[*] struct return pointer in register $A0\n");
2286 for (i
= 0; i
< nargs
; ++i
)
2288 struct riscv_arg_info
*info
= &arg_info
[i
];
2290 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2291 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2292 fprintf_unfiltered (gdb_stdlog
, "\n");
2294 if (call_info
.memory
.arg_offset
> 0
2295 || call_info
.memory
.ref_offset
> 0)
2297 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2298 core_addr_to_string (osp
));
2299 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2300 call_info
.memory
.arg_offset
);
2301 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2302 call_info
.memory
.ref_offset
);
2303 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2304 core_addr_to_string_nz (osp
- sp
));
2308 /* Now load the argument into registers, or onto the stack. */
2312 gdb_byte buf
[sizeof (LONGEST
)];
2314 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2315 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
2318 for (i
= 0; i
< nargs
; ++i
)
2321 int second_arg_length
= 0;
2322 const gdb_byte
*second_arg_data
;
2323 struct riscv_arg_info
*info
= &arg_info
[i
];
2325 gdb_assert (info
->length
> 0);
2327 switch (info
->argloc
[0].loc_type
)
2329 case riscv_arg_info::location::in_reg
:
2331 gdb_byte tmp
[sizeof (ULONGEST
)];
2333 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2334 memset (tmp
, 0, sizeof (tmp
));
2335 memcpy (tmp
, info
->contents
, info
->argloc
[0].c_length
);
2336 regcache
->cooked_write (info
->argloc
[0].loc_data
.regno
, tmp
);
2338 ((info
->argloc
[0].c_length
< info
->length
)
2339 ? info
->argloc
[1].c_length
: 0);
2340 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2344 case riscv_arg_info::location::on_stack
:
2345 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2346 write_memory (dst
, info
->contents
, info
->length
);
2347 second_arg_length
= 0;
2350 case riscv_arg_info::location::by_ref
:
2351 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2352 write_memory (dst
, info
->contents
, info
->length
);
2354 second_arg_length
= call_info
.xlen
;
2355 second_arg_data
= (gdb_byte
*) &dst
;
2359 gdb_assert_not_reached (_("unknown argument location type"));
2362 if (second_arg_length
> 0)
2364 switch (info
->argloc
[1].loc_type
)
2366 case riscv_arg_info::location::in_reg
:
2368 gdb_byte tmp
[sizeof (ULONGEST
)];
2370 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2371 && second_arg_length
<= call_info
.flen
)
2372 || second_arg_length
<= call_info
.xlen
);
2373 memset (tmp
, 0, sizeof (tmp
));
2374 memcpy (tmp
, second_arg_data
, second_arg_length
);
2375 regcache
->cooked_write (info
->argloc
[1].loc_data
.regno
, tmp
);
2379 case riscv_arg_info::location::on_stack
:
2383 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2384 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2388 case riscv_arg_info::location::by_ref
:
2390 /* The second location should never be a reference, any
2391 argument being passed by reference just places its address
2392 in the first location and is done. */
2393 error (_("invalid argument location"));
2399 /* Set the dummy return value to bp_addr.
2400 A dummy breakpoint will be setup to execute the call. */
2402 if (riscv_debug_infcall
> 0)
2403 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2404 core_addr_to_string (bp_addr
));
2405 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2407 /* Finally, update the stack pointer. */
2409 if (riscv_debug_infcall
> 0)
2410 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2411 core_addr_to_string (sp
));
2412 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2417 /* Implement the return_value gdbarch method. */
2419 static enum return_value_convention
2420 riscv_return_value (struct gdbarch
*gdbarch
,
2421 struct value
*function
,
2423 struct regcache
*regcache
,
2425 const gdb_byte
*writebuf
)
2427 struct riscv_call_info
call_info (gdbarch
);
2428 struct riscv_arg_info info
;
2429 struct type
*arg_type
;
2431 arg_type
= check_typedef (type
);
2432 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
);
2434 if (riscv_debug_infcall
> 0)
2436 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2437 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2438 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2439 fprintf_unfiltered (gdb_stdlog
, "\n");
2442 if (readbuf
!= nullptr || writebuf
!= nullptr)
2446 switch (info
.argloc
[0].loc_type
)
2448 /* Return value in register(s). */
2449 case riscv_arg_info::location::in_reg
:
2451 regnum
= info
.argloc
[0].loc_data
.regno
;
2454 regcache
->cooked_read (regnum
, readbuf
);
2457 regcache
->cooked_write (regnum
, writebuf
);
2459 /* A return value in register can have a second part in a
2461 if (info
.argloc
[0].c_length
< info
.length
)
2463 switch (info
.argloc
[1].loc_type
)
2465 case riscv_arg_info::location::in_reg
:
2466 regnum
= info
.argloc
[1].loc_data
.regno
;
2470 readbuf
+= info
.argloc
[1].c_offset
;
2471 regcache
->cooked_read (regnum
, readbuf
);
2476 writebuf
+= info
.argloc
[1].c_offset
;
2477 regcache
->cooked_write (regnum
, writebuf
);
2481 case riscv_arg_info::location::by_ref
:
2482 case riscv_arg_info::location::on_stack
:
2484 error (_("invalid argument location"));
2491 /* Return value by reference will have its address in A0. */
2492 case riscv_arg_info::location::by_ref
:
2496 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2498 if (readbuf
!= nullptr)
2499 read_memory (addr
, readbuf
, info
.length
);
2500 if (writebuf
!= nullptr)
2501 write_memory (addr
, writebuf
, info
.length
);
2505 case riscv_arg_info::location::on_stack
:
2507 error (_("invalid argument location"));
2512 switch (info
.argloc
[0].loc_type
)
2514 case riscv_arg_info::location::in_reg
:
2515 return RETURN_VALUE_REGISTER_CONVENTION
;
2516 case riscv_arg_info::location::by_ref
:
2517 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2518 case riscv_arg_info::location::on_stack
:
2520 error (_("invalid argument location"));
2524 /* Implement the frame_align gdbarch method. */
2527 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2529 return align_down (addr
, 16);
2532 /* Implement the unwind_pc gdbarch method. */
2535 riscv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2537 return frame_unwind_register_unsigned (next_frame
, RISCV_PC_REGNUM
);
2540 /* Implement the unwind_sp gdbarch method. */
2543 riscv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2545 return frame_unwind_register_unsigned (next_frame
, RISCV_SP_REGNUM
);
2548 /* Implement the dummy_id gdbarch method. */
2550 static struct frame_id
2551 riscv_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2553 return frame_id_build (get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
),
2554 get_frame_pc (this_frame
));
2557 /* Generate, or return the cached frame cache for the RiscV frame
2560 static struct riscv_unwind_cache
*
2561 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2563 CORE_ADDR pc
, start_addr
;
2564 struct riscv_unwind_cache
*cache
;
2565 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2568 if ((*this_cache
) != NULL
)
2569 return (struct riscv_unwind_cache
*) *this_cache
;
2571 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
2572 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
2573 (*this_cache
) = cache
;
2575 /* Scan the prologue, filling in the cache. */
2576 start_addr
= get_frame_func (this_frame
);
2577 pc
= get_frame_pc (this_frame
);
2578 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
2580 /* We can now calculate the frame base address. */
2582 = (get_frame_register_signed (this_frame
, cache
->frame_base_reg
)
2583 + cache
->frame_base_offset
);
2584 if (riscv_debug_unwinder
)
2585 fprintf_unfiltered (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
2586 core_addr_to_string (cache
->frame_base
),
2587 gdbarch_register_name (gdbarch
,
2588 cache
->frame_base_reg
),
2589 cache
->frame_base_offset
);
2591 /* The prologue scanner sets the address of registers stored to the stack
2592 as the offset of that register from the frame base. The prologue
2593 scanner doesn't know the actual frame base value, and so is unable to
2594 compute the exact address. We do now know the frame base value, so
2595 update the address of registers stored to the stack. */
2596 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
2597 for (regno
= 0; regno
< numregs
; ++regno
)
2599 if (trad_frame_addr_p (cache
->regs
, regno
))
2600 cache
->regs
[regno
].addr
+= cache
->frame_base
;
2603 /* The previous $pc can be found wherever the $ra value can be found.
2604 The previous $ra value is gone, this would have been stored be the
2605 previous frame if required. */
2606 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
2607 trad_frame_set_unknown (cache
->regs
, RISCV_RA_REGNUM
);
2609 /* Build the frame id. */
2610 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
2612 /* The previous $sp value is the frame base value. */
2613 trad_frame_set_value (cache
->regs
, gdbarch_sp_regnum (gdbarch
),
2619 /* Implement the this_id callback for RiscV frame unwinder. */
2622 riscv_frame_this_id (struct frame_info
*this_frame
,
2623 void **prologue_cache
,
2624 struct frame_id
*this_id
)
2626 struct riscv_unwind_cache
*cache
;
2628 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2629 *this_id
= cache
->this_id
;
2632 /* Implement the prev_register callback for RiscV frame unwinder. */
2634 static struct value
*
2635 riscv_frame_prev_register (struct frame_info
*this_frame
,
2636 void **prologue_cache
,
2639 struct riscv_unwind_cache
*cache
;
2641 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2642 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
2645 /* Structure defining the RiscV normal frame unwind functions. Since we
2646 are the fallback unwinder (DWARF unwinder is used first), we use the
2647 default frame sniffer, which always accepts the frame. */
2649 static const struct frame_unwind riscv_frame_unwind
=
2651 /*.type =*/ NORMAL_FRAME
,
2652 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2653 /*.this_id =*/ riscv_frame_this_id
,
2654 /*.prev_register =*/ riscv_frame_prev_register
,
2655 /*.unwind_data =*/ NULL
,
2656 /*.sniffer =*/ default_frame_sniffer
,
2657 /*.dealloc_cache =*/ NULL
,
2658 /*.prev_arch =*/ NULL
,
2661 /* Initialize the current architecture based on INFO. If possible,
2662 re-use an architecture from ARCHES, which is a list of
2663 architectures already created during this debugging session.
2665 Called e.g. at program startup, when reading a core file, and when
2666 reading a binary file. */
2668 static struct gdbarch
*
2669 riscv_gdbarch_init (struct gdbarch_info info
,
2670 struct gdbarch_list
*arches
)
2672 struct gdbarch
*gdbarch
;
2673 struct gdbarch_tdep
*tdep
;
2674 struct gdbarch_tdep tmp_tdep
;
2677 /* Ideally, we'd like to get as much information from the target for
2678 things like register size, and whether the target has floating point
2679 hardware. However, there are some things that the target can't tell
2680 us, like, what ABI is being used.
2682 So, for now, we take as much information as possible from the ELF,
2683 including things like register size, and FP hardware support, along
2684 with information about the ABI.
2686 Information about this target is built up in TMP_TDEP, and then we
2687 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2688 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2689 memset (&tmp_tdep
, 0, sizeof (tmp_tdep
));
2691 if (info
.abfd
!= NULL
2692 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2694 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2695 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2697 if (eclass
== ELFCLASS32
)
2698 tmp_tdep
.abi
.fields
.base_len
= 1;
2699 else if (eclass
== ELFCLASS64
)
2700 tmp_tdep
.abi
.fields
.base_len
= 2;
2702 internal_error (__FILE__
, __LINE__
,
2703 _("unknown ELF header class %d"), eclass
);
2705 if (e_flags
& EF_RISCV_RVC
)
2706 tmp_tdep
.core_features
|= (1 << ('C' - 'A'));
2708 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2710 tmp_tdep
.abi
.fields
.float_abi
= 2;
2711 tmp_tdep
.core_features
|= (1 << ('D' - 'A'));
2712 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2714 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2716 tmp_tdep
.abi
.fields
.float_abi
= 1;
2717 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2722 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2724 if (binfo
->bits_per_word
== 32)
2725 tmp_tdep
.abi
.fields
.base_len
= 1;
2726 else if (binfo
->bits_per_word
== 64)
2727 tmp_tdep
.abi
.fields
.base_len
= 2;
2729 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2730 binfo
->bits_per_word
);
2733 /* Find a candidate among the list of pre-declared architectures. */
2734 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2736 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2737 if (gdbarch_tdep (arches
->gdbarch
)->abi
.value
== tmp_tdep
.abi
.value
)
2738 return arches
->gdbarch
;
2740 /* None found, so create a new architecture from the information provided. */
2741 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof *tdep
);
2742 gdbarch
= gdbarch_alloc (&info
, tdep
);
2743 memcpy (tdep
, &tmp_tdep
, sizeof (tmp_tdep
));
2745 /* Target data types. */
2746 set_gdbarch_short_bit (gdbarch
, 16);
2747 set_gdbarch_int_bit (gdbarch
, 32);
2748 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2749 set_gdbarch_long_long_bit (gdbarch
, 64);
2750 set_gdbarch_float_bit (gdbarch
, 32);
2751 set_gdbarch_double_bit (gdbarch
, 64);
2752 set_gdbarch_long_double_bit (gdbarch
, 128);
2753 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
2754 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2755 set_gdbarch_char_signed (gdbarch
, 0);
2757 /* Information about the target architecture. */
2758 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
2759 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
2760 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
2762 /* Register architecture. */
2763 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
2764 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
2765 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
2766 set_gdbarch_ps_regnum (gdbarch
, RISCV_FP_REGNUM
);
2767 set_gdbarch_deprecated_fp_regnum (gdbarch
, RISCV_FP_REGNUM
);
2769 /* Functions to supply register information. */
2770 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
2771 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
2772 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
2773 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
2775 /* Functions to analyze frames. */
2776 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
2777 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2778 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
2780 /* Functions to access frame data. */
2781 set_gdbarch_unwind_pc (gdbarch
, riscv_unwind_pc
);
2782 set_gdbarch_unwind_sp (gdbarch
, riscv_unwind_sp
);
2784 /* Functions handling dummy frames. */
2785 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2786 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
2787 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
2788 set_gdbarch_dummy_id (gdbarch
, riscv_dummy_id
);
2790 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2792 dwarf2_append_unwinders (gdbarch
);
2793 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
2795 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
2796 user_reg_add (gdbarch
, riscv_register_aliases
[i
].name
,
2797 value_of_riscv_user_reg
, &riscv_register_aliases
[i
].regnum
);
2799 /* Hook in OS ABI-specific overrides, if they have been registered. */
2800 gdbarch_init_osabi (info
, gdbarch
);
2805 /* This decodes the current instruction and determines the address of the
2806 next instruction. */
2809 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2811 struct gdbarch
*gdbarch
= regcache
->arch ();
2812 struct riscv_insn insn
;
2815 insn
.decode (gdbarch
, pc
);
2816 next_pc
= pc
+ insn
.length ();
2818 if (insn
.opcode () == riscv_insn::JAL
)
2819 next_pc
= pc
+ insn
.imm_signed ();
2820 else if (insn
.opcode () == riscv_insn::JALR
)
2823 regcache
->cooked_read (insn
.rs1 (), &source
);
2824 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
2826 else if (insn
.opcode () == riscv_insn::BEQ
)
2829 regcache
->cooked_read (insn
.rs1 (), &src1
);
2830 regcache
->cooked_read (insn
.rs2 (), &src2
);
2832 next_pc
= pc
+ insn
.imm_signed ();
2834 else if (insn
.opcode () == riscv_insn::BNE
)
2837 regcache
->cooked_read (insn
.rs1 (), &src1
);
2838 regcache
->cooked_read (insn
.rs2 (), &src2
);
2840 next_pc
= pc
+ insn
.imm_signed ();
2842 else if (insn
.opcode () == riscv_insn::BLT
)
2845 regcache
->cooked_read (insn
.rs1 (), &src1
);
2846 regcache
->cooked_read (insn
.rs2 (), &src2
);
2848 next_pc
= pc
+ insn
.imm_signed ();
2850 else if (insn
.opcode () == riscv_insn::BGE
)
2853 regcache
->cooked_read (insn
.rs1 (), &src1
);
2854 regcache
->cooked_read (insn
.rs2 (), &src2
);
2856 next_pc
= pc
+ insn
.imm_signed ();
2858 else if (insn
.opcode () == riscv_insn::BLTU
)
2860 ULONGEST src1
, src2
;
2861 regcache
->cooked_read (insn
.rs1 (), &src1
);
2862 regcache
->cooked_read (insn
.rs2 (), &src2
);
2864 next_pc
= pc
+ insn
.imm_signed ();
2866 else if (insn
.opcode () == riscv_insn::BGEU
)
2868 ULONGEST src1
, src2
;
2869 regcache
->cooked_read (insn
.rs1 (), &src1
);
2870 regcache
->cooked_read (insn
.rs2 (), &src2
);
2872 next_pc
= pc
+ insn
.imm_signed ();
2878 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
2879 for the end of the sequence and put the breakpoint there. */
2882 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
2885 struct gdbarch
*gdbarch
= regcache
->arch ();
2886 struct riscv_insn insn
;
2887 CORE_ADDR cur_step_pc
= pc
;
2888 CORE_ADDR last_addr
= 0;
2890 /* First instruction has to be a load reserved. */
2891 insn
.decode (gdbarch
, cur_step_pc
);
2892 if (insn
.opcode () != riscv_insn::LR
)
2894 cur_step_pc
= cur_step_pc
+ insn
.length ();
2896 /* Next instruction should be branch to exit. */
2897 insn
.decode (gdbarch
, cur_step_pc
);
2898 if (insn
.opcode () != riscv_insn::BNE
)
2900 last_addr
= cur_step_pc
+ insn
.imm_signed ();
2901 cur_step_pc
= cur_step_pc
+ insn
.length ();
2903 /* Next instruction should be store conditional. */
2904 insn
.decode (gdbarch
, cur_step_pc
);
2905 if (insn
.opcode () != riscv_insn::SC
)
2907 cur_step_pc
= cur_step_pc
+ insn
.length ();
2909 /* Next instruction should be branch to start. */
2910 insn
.decode (gdbarch
, cur_step_pc
);
2911 if (insn
.opcode () != riscv_insn::BNE
)
2913 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
2915 cur_step_pc
= cur_step_pc
+ insn
.length ();
2917 /* We should now be at the end of the sequence. */
2918 if (cur_step_pc
!= last_addr
)
2921 *next_pc
= cur_step_pc
;
2925 /* This is called just before we want to resume the inferior, if we want to
2926 single-step it but there is no hardware or kernel single-step support. We
2927 find the target of the coming instruction and breakpoint it. */
2929 std::vector
<CORE_ADDR
>
2930 riscv_software_single_step (struct regcache
*regcache
)
2932 CORE_ADDR pc
, next_pc
;
2934 pc
= regcache_read_pc (regcache
);
2936 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
2939 next_pc
= riscv_next_pc (regcache
, pc
);
2945 _initialize_riscv_tdep (void)
2947 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
2949 /* Add root prefix command for all "set debug riscv" and "show debug
2951 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
2952 _("RISC-V specific debug commands."),
2953 &setdebugriscvcmdlist
, "set debug riscv ", 0,
2956 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
2957 _("RISC-V specific debug commands."),
2958 &showdebugriscvcmdlist
, "show debug riscv ", 0,
2961 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
2962 &riscv_debug_breakpoints
, _("\
2963 Set riscv breakpoint debugging."), _("\
2964 Show riscv breakpoint debugging."), _("\
2965 When non-zero, print debugging information for the riscv specific parts\n\
2966 of the breakpoint mechanism."),
2968 show_riscv_debug_variable
,
2969 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
2971 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
2972 &riscv_debug_infcall
, _("\
2973 Set riscv inferior call debugging."), _("\
2974 Show riscv inferior call debugging."), _("\
2975 When non-zero, print debugging information for the riscv specific parts\n\
2976 of the inferior call mechanism."),
2978 show_riscv_debug_variable
,
2979 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
2981 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
2982 &riscv_debug_unwinder
, _("\
2983 Set riscv stack unwinding debugging."), _("\
2984 Show riscv stack unwinding debugging."), _("\
2985 When non-zero, print debugging information for the riscv specific parts\n\
2986 of the stack unwinding mechanism."),
2988 show_riscv_debug_variable
,
2989 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
2991 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2992 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
2993 _("RISC-V specific commands."),
2994 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
2996 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
2997 _("RISC-V specific commands."),
2998 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
3001 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
3002 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
3003 &use_compressed_breakpoints
,
3005 Set debugger's use of compressed breakpoints."), _(" \
3006 Show debugger's use of compressed breakpoints."), _("\
3007 Debugging compressed code requires compressed breakpoints to be used. If\n\
3008 left to 'auto' then gdb will use them if the existing instruction is a\n\
3009 compressed instruction. If that doesn't give the correct behavior, then\n\
3010 this option can be used."),
3012 show_use_compressed_breakpoints
,