1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
58 /* The stack must be 16-byte aligned. */
59 #define SP_ALIGNMENT 16
61 /* Forward declarations. */
62 static bool riscv_has_feature (struct gdbarch
*gdbarch
, char feature
);
64 /* Define a series of is_XXX_insn functions to check if the value INSN
65 is an instance of instruction XXX. */
66 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
67 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
69 return (insn & INSN_MASK) == INSN_MATCH; \
71 #include "opcode/riscv-opc.h"
74 /* Architectural name for core registers. */
76 static const char * const riscv_gdb_reg_names
[RISCV_LAST_FP_REGNUM
+ 1] =
78 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
79 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
80 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
81 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
83 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
84 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
85 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
86 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
89 /* Maps "pretty" register names onto their GDB register number. */
93 /* The register alias. Usually more descriptive than the
94 architectural name of the register. */
97 /* The GDB register number. */
101 /* Table of register aliases. */
103 static const struct register_alias riscv_register_aliases
[] =
171 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
172 #include "opcode/riscv-opc.h"
176 /* Controls whether we place compressed breakpoints or not. When in auto
177 mode GDB tries to determine if the target supports compressed
178 breakpoints, and uses them if it does. */
180 static enum auto_boolean use_compressed_breakpoints
;
182 /* The show callback for 'show riscv use-compressed-breakpoints'. */
185 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
186 struct cmd_list_element
*c
,
189 const char *additional_info
;
190 struct gdbarch
*gdbarch
= target_gdbarch ();
192 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
193 if (riscv_has_feature (gdbarch
, 'C'))
194 additional_info
= _(" (currently on)");
196 additional_info
= _(" (currently off)");
198 additional_info
= "";
200 fprintf_filtered (file
,
201 _("Debugger's use of compressed breakpoints is set "
202 "to %s%s.\n"), value
, additional_info
);
205 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
207 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
208 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
210 /* The show callback for the 'show riscv' prefix command. */
213 show_riscv_command (const char *args
, int from_tty
)
215 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
218 /* The set callback for the 'set riscv' prefix command. */
221 set_riscv_command (const char *args
, int from_tty
)
224 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
225 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
228 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
230 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
231 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
233 /* The show callback for the 'show debug riscv' prefix command. */
236 show_debug_riscv_command (const char *args
, int from_tty
)
238 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
241 /* The set callback for the 'set debug riscv' prefix command. */
244 set_debug_riscv_command (const char *args
, int from_tty
)
247 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
248 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
251 /* The show callback for all 'show debug riscv VARNAME' variables. */
254 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
255 struct cmd_list_element
*c
,
258 fprintf_filtered (file
,
259 _("RiscV debug variable `%s' is set to: %s\n"),
263 /* When this is set to non-zero debugging information about inferior calls
266 static unsigned int riscv_debug_infcall
= 0;
268 /* Read the MISA register from the target. The register will only be read
269 once, and the value read will be cached. If the register can't be read
270 from the target then a default value (0) will be returned. If the
271 pointer READ_P is not null, then the bool pointed to is updated to
272 indicate if the value returned was read from the target (true) or is the
276 riscv_read_misa_reg (bool *read_p
)
280 if (target_has_registers
)
282 struct frame_info
*frame
= get_current_frame ();
286 value
= get_frame_register_unsigned (frame
,
287 RISCV_CSR_MISA_REGNUM
);
289 CATCH (ex
, RETURN_MASK_ERROR
)
291 /* Old cores might have MISA located at a different offset. */
292 value
= get_frame_register_unsigned (frame
,
293 RISCV_CSR_LEGACY_MISA_REGNUM
);
301 /* Return true if FEATURE is available for the architecture GDBARCH. The
302 FEATURE should be one of the single character feature codes described in
303 the RiscV ISA manual, these are between 'A' and 'Z'. */
306 riscv_has_feature (struct gdbarch
*gdbarch
, char feature
)
308 bool have_read_misa
= false;
311 gdb_assert (feature
>= 'A' && feature
<= 'Z');
313 misa
= riscv_read_misa_reg (&have_read_misa
);
314 if (!have_read_misa
|| misa
== 0)
315 misa
= gdbarch_tdep (gdbarch
)->core_features
;
317 return (misa
& (1 << (feature
- 'A'))) != 0;
320 /* Return the width in bytes of the general purpose registers for GDBARCH.
321 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
325 riscv_isa_xlen (struct gdbarch
*gdbarch
)
327 switch (gdbarch_tdep (gdbarch
)->abi
.fields
.base_len
)
330 warning (_("unknown xlen size, assuming 4 bytes"));
341 /* Return the width in bytes of the floating point registers for GDBARCH.
342 If this architecture has no floating point registers, then return 0.
343 Possible values are 4, 8, or 16 for depending on which of single, double
344 or quad floating point support is available. */
347 riscv_isa_flen (struct gdbarch
*gdbarch
)
349 if (riscv_has_feature (gdbarch
, 'Q'))
351 else if (riscv_has_feature (gdbarch
, 'D'))
353 else if (riscv_has_feature (gdbarch
, 'F'))
359 /* Return true if the target for GDBARCH has floating point hardware. */
362 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
364 return (riscv_isa_flen (gdbarch
) > 0);
367 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
370 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
372 return (gdbarch_tdep (gdbarch
)->abi
.fields
.float_abi
!= 0);
375 /* Return true if REGNO is a floating pointer register. */
378 riscv_is_fp_regno_p (int regno
)
380 return (regno
>= RISCV_FIRST_FP_REGNUM
381 && regno
<= RISCV_LAST_FP_REGNUM
);
384 /* Implement the breakpoint_kind_from_pc gdbarch method. */
387 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
389 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
391 if (riscv_has_feature (gdbarch
, 'C'))
396 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
402 /* Implement the sw_breakpoint_from_kind gdbarch method. */
404 static const gdb_byte
*
405 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
407 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
408 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
418 gdb_assert_not_reached (_("unhandled breakpoint kind"));
422 /* Callback function for user_reg_add. */
424 static struct value
*
425 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
427 const int *reg_p
= (const int *) baton
;
428 return value_of_register (*reg_p
, frame
);
431 /* Implement the register_name gdbarch method. */
434 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
436 /* Prefer to use the alias. */
437 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_REGNUM
)
441 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
442 if (regnum
== riscv_register_aliases
[i
].regnum
)
443 return riscv_register_aliases
[i
].name
;
446 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
447 return riscv_gdb_reg_names
[regnum
];
449 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
453 xsnprintf (buf
, sizeof (buf
), "csr%d",
454 regnum
- RISCV_FIRST_CSR_REGNUM
);
458 if (regnum
== RISCV_PRIV_REGNUM
)
464 /* Implement the register_type gdbarch method. */
467 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
471 if (regnum
< RISCV_FIRST_FP_REGNUM
)
473 if (regnum
== gdbarch_pc_regnum (gdbarch
)
474 || regnum
== RISCV_RA_REGNUM
)
475 return builtin_type (gdbarch
)->builtin_func_ptr
;
477 if (regnum
== RISCV_FP_REGNUM
478 || regnum
== RISCV_SP_REGNUM
479 || regnum
== RISCV_GP_REGNUM
480 || regnum
== RISCV_TP_REGNUM
)
481 return builtin_type (gdbarch
)->builtin_data_ptr
;
483 /* Remaining GPRs vary in size based on the current ISA. */
484 regsize
= riscv_isa_xlen (gdbarch
);
488 return builtin_type (gdbarch
)->builtin_uint32
;
490 return builtin_type (gdbarch
)->builtin_uint64
;
492 return builtin_type (gdbarch
)->builtin_uint128
;
494 internal_error (__FILE__
, __LINE__
,
495 _("unknown isa regsize %i"), regsize
);
498 else if (regnum
<= RISCV_LAST_FP_REGNUM
)
500 regsize
= riscv_isa_xlen (gdbarch
);
504 return builtin_type (gdbarch
)->builtin_float
;
506 return builtin_type (gdbarch
)->builtin_double
;
508 return builtin_type (gdbarch
)->builtin_long_double
;
510 internal_error (__FILE__
, __LINE__
,
511 _("unknown isa regsize %i"), regsize
);
514 else if (regnum
== RISCV_PRIV_REGNUM
)
515 return builtin_type (gdbarch
)->builtin_int8
;
518 if (regnum
== RISCV_CSR_FFLAGS_REGNUM
519 || regnum
== RISCV_CSR_FRM_REGNUM
520 || regnum
== RISCV_CSR_FCSR_REGNUM
)
521 return builtin_type (gdbarch
)->builtin_int32
;
523 regsize
= riscv_isa_xlen (gdbarch
);
527 return builtin_type (gdbarch
)->builtin_int32
;
529 return builtin_type (gdbarch
)->builtin_int64
;
531 return builtin_type (gdbarch
)->builtin_int128
;
533 internal_error (__FILE__
, __LINE__
,
534 _("unknown isa regsize %i"), regsize
);
539 /* Helper for riscv_print_registers_info, prints info for a single register
543 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
544 struct ui_file
*file
,
545 struct frame_info
*frame
,
548 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
549 struct value
*val
= value_of_register (regnum
, frame
);
550 struct type
*regtype
= value_type (val
);
551 int print_raw_format
;
552 enum tab_stops
{ value_column_1
= 15 };
554 fputs_filtered (name
, file
);
555 print_spaces_filtered (value_column_1
- strlen (name
), file
);
557 print_raw_format
= (value_entirely_available (val
)
558 && !value_optimized_out (val
));
560 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
)
562 struct value_print_options opts
;
563 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
564 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
566 get_user_print_options (&opts
);
570 value_embedded_offset (val
), 0,
571 file
, 0, val
, &opts
, current_language
);
573 if (print_raw_format
)
575 fprintf_filtered (file
, "\t(raw ");
576 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
578 fprintf_filtered (file
, ")");
583 struct value_print_options opts
;
585 /* Print the register in hex. */
586 get_formatted_print_options (&opts
, 'x');
589 value_embedded_offset (val
), 0,
590 file
, 0, val
, &opts
, current_language
);
592 if (print_raw_format
)
594 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
597 int size
= register_size (gdbarch
, regnum
);
600 d
= value_as_long (val
);
602 fprintf_filtered (file
,
603 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
604 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
605 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
606 (int) ((d
>> (xlen
- 1)) & 0x1),
607 (int) ((d
>> 24) & 0x1f),
608 (int) ((d
>> 19) & 0x1),
609 (int) ((d
>> 18) & 0x1),
610 (int) ((d
>> 17) & 0x1),
611 (int) ((d
>> 15) & 0x3),
612 (int) ((d
>> 13) & 0x3),
613 (int) ((d
>> 11) & 0x3),
614 (int) ((d
>> 9) & 0x3),
615 (int) ((d
>> 8) & 0x1),
616 (int) ((d
>> 7) & 0x1),
617 (int) ((d
>> 6) & 0x1),
618 (int) ((d
>> 5) & 0x1),
619 (int) ((d
>> 4) & 0x1),
620 (int) ((d
>> 3) & 0x1),
621 (int) ((d
>> 2) & 0x1),
622 (int) ((d
>> 1) & 0x1),
623 (int) ((d
>> 0) & 0x1));
625 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
631 d
= value_as_long (val
);
635 for (; base
> 0; base
--)
637 fprintf_filtered (file
, "\tRV%d", xlen
);
639 for (i
= 0; i
< 26; i
++)
642 fprintf_filtered (file
, "%c", 'A' + i
);
645 else if (regnum
== RISCV_CSR_FCSR_REGNUM
646 || regnum
== RISCV_CSR_FFLAGS_REGNUM
647 || regnum
== RISCV_CSR_FRM_REGNUM
)
651 d
= value_as_long (val
);
653 fprintf_filtered (file
, "\t");
654 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
655 fprintf_filtered (file
,
656 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
657 (int) ((d
>> 5) & 0x7),
658 (int) ((d
>> 4) & 0x1),
659 (int) ((d
>> 3) & 0x1),
660 (int) ((d
>> 2) & 0x1),
661 (int) ((d
>> 1) & 0x1),
662 (int) ((d
>> 0) & 0x1));
664 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
666 static const char * const sfrm
[] =
668 "RNE (round to nearest; ties to even)",
669 "RTZ (Round towards zero)",
670 "RDN (Round down towards -INF)",
671 "RUP (Round up towards +INF)",
672 "RMM (Round to nearest; ties to max magnitude)",
675 "dynamic rounding mode",
677 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
678 ? (d
>> 5) : d
) & 0x3;
680 fprintf_filtered (file
, "%sFRM:%i [%s]",
681 (regnum
== RISCV_CSR_FCSR_REGNUM
686 else if (regnum
== RISCV_PRIV_REGNUM
)
691 d
= value_as_long (val
);
696 static const char * const sprv
[] =
703 fprintf_filtered (file
, "\tprv:%d [%s]",
707 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
711 /* If not a vector register, print it also according to its
713 if (TYPE_VECTOR (regtype
) == 0)
715 get_user_print_options (&opts
);
717 fprintf_filtered (file
, "\t");
719 value_embedded_offset (val
), 0,
720 file
, 0, val
, &opts
, current_language
);
725 fprintf_filtered (file
, "\n");
728 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
732 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
733 struct reggroup
*reggroup
)
737 /* Used by 'info registers' and 'info registers <groupname>'. */
739 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
740 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
743 if (reggroup
== all_reggroup
)
745 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
747 /* Only include CSRs that have aliases. */
748 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
750 if (regnum
== riscv_register_aliases
[i
].regnum
)
755 else if (reggroup
== float_reggroup
)
756 return (riscv_is_fp_regno_p (regnum
)
757 || regnum
== RISCV_CSR_FCSR_REGNUM
758 || regnum
== RISCV_CSR_FFLAGS_REGNUM
759 || regnum
== RISCV_CSR_FRM_REGNUM
);
760 else if (reggroup
== general_reggroup
)
761 return regnum
< RISCV_FIRST_FP_REGNUM
;
762 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
764 if (riscv_has_fp_regs (gdbarch
))
765 return regnum
<= RISCV_LAST_FP_REGNUM
;
767 return regnum
< RISCV_FIRST_FP_REGNUM
;
769 else if (reggroup
== system_reggroup
)
771 if (regnum
== RISCV_PRIV_REGNUM
)
773 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
775 /* Only include CSRs that have aliases. */
776 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
778 if (regnum
== riscv_register_aliases
[i
].regnum
)
783 else if (reggroup
== vector_reggroup
)
789 /* Implement the print_registers_info gdbarch method. This is used by
790 'info registers' and 'info all-registers'. */
793 riscv_print_registers_info (struct gdbarch
*gdbarch
,
794 struct ui_file
*file
,
795 struct frame_info
*frame
,
796 int regnum
, int print_all
)
800 /* Print one specified register. */
801 gdb_assert (regnum
<= RISCV_LAST_REGNUM
);
802 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
803 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
804 error (_("Not a valid register for the current processor type"));
805 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
809 struct reggroup
*reggroup
;
812 reggroup
= all_reggroup
;
814 reggroup
= general_reggroup
;
816 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
818 /* Zero never changes, so might as well hide by default. */
819 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
822 /* Registers with no name are not valid on this ISA. */
823 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
824 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
827 /* Is the register in the group we're interested in? */
828 if (!riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
))
831 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
836 /* Class that handles one decoded RiscV instruction. */
842 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
845 /* Unknown value is used at initialisation time. */
848 /* These instructions are all the ones we are interested in during the
858 /* These are needed for software breakopint support. */
867 /* These are needed for stepping over atomic sequences. */
871 /* Other instructions are not interesting during the prologue scan, and
886 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
888 /* Get the length of the instruction in bytes. */
892 /* Get the opcode for this instruction. */
893 enum opcode
opcode () const
896 /* Get destination register field for this instruction. This is only
897 valid if the OPCODE implies there is such a field for this
902 /* Get the RS1 register field for this instruction. This is only valid
903 if the OPCODE implies there is such a field for this instruction. */
907 /* Get the RS2 register field for this instruction. This is only valid
908 if the OPCODE implies there is such a field for this instruction. */
912 /* Get the immediate for this instruction in signed form. This is only
913 valid if the OPCODE implies there is such a field for this
915 int imm_signed () const
920 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
921 int decode_register_index (unsigned long opcode
, int offset
)
923 return (opcode
>> offset
) & 0x1F;
926 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
927 int decode_register_index_short (unsigned long opcode
, int offset
)
929 return ((opcode
>> offset
) & 0x7) + 8;
932 /* Helper for DECODE, decode 32-bit R-type instruction. */
933 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
936 m_rd
= decode_register_index (ival
, OP_SH_RD
);
937 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
938 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
941 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
942 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
945 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
946 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
949 /* Helper for DECODE, decode 32-bit I-type instruction. */
950 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
953 m_rd
= decode_register_index (ival
, OP_SH_RD
);
954 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
955 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
958 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
959 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
962 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
963 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
966 /* Helper for DECODE, decode 32-bit S-type instruction. */
967 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
970 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
971 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
972 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
975 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
976 encoding is different for each CS format instruction, so extracting
977 the immediate is left up to the caller, who should pass the extracted
978 immediate value through in IMM. */
979 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
983 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
984 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
987 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
988 encoding is different for each CSS format instruction, so extracting
989 the immediate is left up to the caller, who should pass the extracted
990 immediate value through in IMM. */
991 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
995 m_rs1
= RISCV_SP_REGNUM
;
996 /* Not a compressed register number in this case. */
997 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1000 /* Helper for DECODE, decode 32-bit U-type instruction. */
1001 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1004 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1005 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1008 /* Helper for DECODE, decode 32-bit J-type instruction. */
1009 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1012 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1013 m_imm
.s
= EXTRACT_UJTYPE_IMM (ival
);
1016 /* Helper for DECODE, decode 32-bit J-type instruction. */
1017 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1020 m_imm
.s
= EXTRACT_RVC_J_IMM (ival
);
1023 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1026 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1027 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1028 m_imm
.s
= EXTRACT_SBTYPE_IMM (ival
);
1031 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1034 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1035 m_imm
.s
= EXTRACT_RVC_B_IMM (ival
);
1038 /* Fetch instruction from target memory at ADDR, return the content of
1039 the instruction, and update LEN with the instruction length. */
1040 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1041 CORE_ADDR addr
, int *len
);
1043 /* The length of the instruction in bytes. Should be 2 or 4. */
1046 /* The instruction opcode. */
1047 enum opcode m_opcode
;
1049 /* The three possible registers an instruction might reference. Not
1050 every instruction fills in all of these registers. Which fields are
1051 valid depends on the opcode. The naming of these fields matches the
1052 naming in the riscv isa manual. */
1057 /* Possible instruction immediate. This is only valid if the instruction
1058 format contains an immediate, not all instruction, whether this is
1059 valid depends on the opcode. Despite only having one format for now
1060 the immediate is packed into a union, later instructions might require
1061 an unsigned formatted immediate, having the union in place now will
1062 reduce the need for code churn later. */
1063 union riscv_insn_immediate
1065 riscv_insn_immediate ()
1075 /* Fetch instruction from target memory at ADDR, return the content of the
1076 instruction, and update LEN with the instruction length. */
1079 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1080 CORE_ADDR addr
, int *len
)
1082 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1084 int instlen
, status
;
1086 /* All insns are at least 16 bits. */
1087 status
= target_read_memory (addr
, buf
, 2);
1089 memory_error (TARGET_XFER_E_IO
, addr
);
1091 /* If we need more, grab it now. */
1092 instlen
= riscv_insn_length (buf
[0]);
1093 gdb_assert (instlen
<= sizeof (buf
));
1098 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1100 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1103 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1106 /* Fetch from target memory an instruction at PC and decode it. */
1109 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1113 /* Fetch the instruction, and the instructions length. */
1114 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1118 if (is_add_insn (ival
))
1119 decode_r_type_insn (ADD
, ival
);
1120 else if (is_addw_insn (ival
))
1121 decode_r_type_insn (ADDW
, ival
);
1122 else if (is_addi_insn (ival
))
1123 decode_i_type_insn (ADDI
, ival
);
1124 else if (is_addiw_insn (ival
))
1125 decode_i_type_insn (ADDIW
, ival
);
1126 else if (is_auipc_insn (ival
))
1127 decode_u_type_insn (AUIPC
, ival
);
1128 else if (is_lui_insn (ival
))
1129 decode_u_type_insn (LUI
, ival
);
1130 else if (is_sd_insn (ival
))
1131 decode_s_type_insn (SD
, ival
);
1132 else if (is_sw_insn (ival
))
1133 decode_s_type_insn (SW
, ival
);
1134 else if (is_jal_insn (ival
))
1135 decode_j_type_insn (JAL
, ival
);
1136 else if (is_jalr_insn (ival
))
1137 decode_i_type_insn (JALR
, ival
);
1138 else if (is_beq_insn (ival
))
1139 decode_b_type_insn (BEQ
, ival
);
1140 else if (is_bne_insn (ival
))
1141 decode_b_type_insn (BNE
, ival
);
1142 else if (is_blt_insn (ival
))
1143 decode_b_type_insn (BLT
, ival
);
1144 else if (is_bge_insn (ival
))
1145 decode_b_type_insn (BGE
, ival
);
1146 else if (is_bltu_insn (ival
))
1147 decode_b_type_insn (BLTU
, ival
);
1148 else if (is_bgeu_insn (ival
))
1149 decode_b_type_insn (BGEU
, ival
);
1150 else if (is_lr_w_insn (ival
))
1151 decode_r_type_insn (LR
, ival
);
1152 else if (is_lr_d_insn (ival
))
1153 decode_r_type_insn (LR
, ival
);
1154 else if (is_sc_w_insn (ival
))
1155 decode_r_type_insn (SC
, ival
);
1156 else if (is_sc_d_insn (ival
))
1157 decode_r_type_insn (SC
, ival
);
1159 /* None of the other fields are valid in this case. */
1162 else if (m_length
== 2)
1164 int xlen
= riscv_isa_xlen (gdbarch
);
1166 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1167 C_JALR. So must try to match C_JALR first as it has more bits in
1169 if (is_c_jalr_insn (ival
))
1170 decode_cr_type_insn (JALR
, ival
);
1171 else if (is_c_add_insn (ival
))
1172 decode_cr_type_insn (ADD
, ival
);
1173 /* C_ADDW is RV64 and RV128 only. */
1174 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1175 decode_cr_type_insn (ADDW
, ival
);
1176 else if (is_c_addi_insn (ival
))
1177 decode_ci_type_insn (ADDI
, ival
);
1178 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1179 only and C_JAL is RV32 only. */
1180 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1181 decode_ci_type_insn (ADDIW
, ival
);
1182 else if (xlen
== 4 && is_c_jal_insn (ival
))
1183 decode_cj_type_insn (JAL
, ival
);
1184 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1185 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1187 else if (is_c_addi16sp_insn (ival
))
1190 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1191 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1193 else if (is_c_addi4spn_insn (ival
))
1196 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1197 m_rs1
= RISCV_SP_REGNUM
;
1198 m_imm
.s
= EXTRACT_RVC_ADDI4SPN_IMM (ival
);
1200 else if (is_c_lui_insn (ival
))
1202 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1203 and C_FSW is RV32 only. */
1204 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1205 decode_cs_type_insn (SD
, ival
, EXTRACT_RVC_LD_IMM (ival
));
1206 else if (is_c_sw_insn (ival
))
1207 decode_cs_type_insn (SW
, ival
, EXTRACT_RVC_LW_IMM (ival
));
1208 else if (is_c_swsp_insn (ival
))
1209 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SWSP_IMM (ival
));
1210 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1211 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SDSP_IMM (ival
));
1212 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1213 So must try to match C_JR first as it ahs more bits in mask. */
1214 else if (is_c_jr_insn (ival
))
1215 decode_cr_type_insn (JALR
, ival
);
1216 else if (is_c_j_insn (ival
))
1217 decode_cj_type_insn (JAL
, ival
);
1218 else if (is_c_beqz_insn (ival
))
1219 decode_cb_type_insn (BEQ
, ival
);
1220 else if (is_c_bnez_insn (ival
))
1221 decode_cb_type_insn (BNE
, ival
);
1223 /* None of the other fields of INSN are valid in this case. */
1227 internal_error (__FILE__
, __LINE__
,
1228 _("unable to decode %d byte instructions in "
1229 "prologue at %s"), m_length
,
1230 core_addr_to_string (pc
));
1233 /* The prologue scanner. This is currently only used for skipping the
1234 prologue of a function when the DWARF information is not sufficient.
1235 However, it is written with filling of the frame cache in mind, which
1236 is why different groups of stack setup instructions are split apart
1237 during the core of the inner loop. In the future, the intention is to
1238 extend this function to fully support building up a frame cache that
1239 can unwind register values when there is no DWARF information. */
1242 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1243 CORE_ADDR start_pc
, CORE_ADDR limit_pc
)
1245 CORE_ADDR cur_pc
, next_pc
;
1246 long frame_offset
= 0;
1247 CORE_ADDR end_prologue_addr
= 0;
1249 if (limit_pc
> start_pc
+ 200)
1250 limit_pc
= start_pc
+ 200;
1252 for (next_pc
= cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
= next_pc
)
1254 struct riscv_insn insn
;
1256 /* Decode the current instruction, and decide where the next
1257 instruction lives based on the size of this instruction. */
1258 insn
.decode (gdbarch
, cur_pc
);
1259 gdb_assert (insn
.length () > 0);
1260 next_pc
= cur_pc
+ insn
.length ();
1262 /* Look for common stack adjustment insns. */
1263 if ((insn
.opcode () == riscv_insn::ADDI
1264 || insn
.opcode () == riscv_insn::ADDIW
)
1265 && insn
.rd () == RISCV_SP_REGNUM
1266 && insn
.rs1 () == RISCV_SP_REGNUM
)
1268 /* Handle: addi sp, sp, -i
1269 or: addiw sp, sp, -i */
1270 if (insn
.imm_signed () < 0)
1271 frame_offset
+= insn
.imm_signed ();
1275 else if ((insn
.opcode () == riscv_insn::SW
1276 || insn
.opcode () == riscv_insn::SD
)
1277 && (insn
.rs1 () == RISCV_SP_REGNUM
1278 || insn
.rs1 () == RISCV_FP_REGNUM
))
1280 /* Handle: sw reg, offset(sp)
1281 or: sd reg, offset(sp)
1282 or: sw reg, offset(s0)
1283 or: sd reg, offset(s0) */
1284 /* Instruction storing a register onto the stack. */
1286 else if (insn
.opcode () == riscv_insn::ADDI
1287 && insn
.rd () == RISCV_FP_REGNUM
1288 && insn
.rs1 () == RISCV_SP_REGNUM
)
1290 /* Handle: addi s0, sp, size */
1291 /* Instructions setting up the frame pointer. */
1293 else if ((insn
.opcode () == riscv_insn::ADD
1294 || insn
.opcode () == riscv_insn::ADDW
)
1295 && insn
.rd () == RISCV_FP_REGNUM
1296 && insn
.rs1 () == RISCV_SP_REGNUM
1297 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1299 /* Handle: add s0, sp, 0
1300 or: addw s0, sp, 0 */
1301 /* Instructions setting up the frame pointer. */
1303 else if ((insn
.rd () == RISCV_GP_REGNUM
1304 && (insn
.opcode () == riscv_insn::AUIPC
1305 || insn
.opcode () == riscv_insn::LUI
1306 || (insn
.opcode () == riscv_insn::ADDI
1307 && insn
.rs1 () == RISCV_GP_REGNUM
)
1308 || (insn
.opcode () == riscv_insn::ADD
1309 && (insn
.rs1 () == RISCV_GP_REGNUM
1310 || insn
.rs2 () == RISCV_GP_REGNUM
))))
1311 || (insn
.opcode () == riscv_insn::ADDI
1312 && insn
.rd () == RISCV_ZERO_REGNUM
1313 && insn
.rs1 () == RISCV_ZERO_REGNUM
1314 && insn
.imm_signed () == 0))
1316 /* Handle: auipc gp, n
1321 or: add x0, x0, 0 (NOP) */
1322 /* These instructions are part of the prologue, but we don't need
1323 to do anything special to handle them. */
1327 if (end_prologue_addr
== 0)
1328 end_prologue_addr
= cur_pc
;
1332 if (end_prologue_addr
== 0)
1333 end_prologue_addr
= cur_pc
;
1335 return end_prologue_addr
;
1338 /* Implement the riscv_skip_prologue gdbarch method. */
1341 riscv_skip_prologue (struct gdbarch
*gdbarch
,
1345 CORE_ADDR func_addr
;
1347 /* See if we can determine the end of the prologue via the symbol
1348 table. If so, then return either PC, or the PC after the
1349 prologue, whichever is greater. */
1350 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1352 CORE_ADDR post_prologue_pc
1353 = skip_prologue_using_sal (gdbarch
, func_addr
);
1355 if (post_prologue_pc
!= 0)
1356 return std::max (pc
, post_prologue_pc
);
1359 /* Can't determine prologue from the symbol table, need to examine
1362 /* Find an upper limit on the function prologue using the debug
1363 information. If the debug information could not be used to provide
1364 that bound, then use an arbitrary large number as the upper bound. */
1365 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1367 limit_pc
= pc
+ 100; /* MAGIC! */
1369 return riscv_scan_prologue (gdbarch
, pc
, limit_pc
);
1372 /* Implement the gdbarch push dummy code callback. */
1375 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1376 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1377 struct type
*value_type
, CORE_ADDR
*real_pc
,
1378 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1380 /* Allocate space for a breakpoint, and keep the stack correctly
1388 /* Compute the alignment of the type T. Used while setting up the
1389 arguments for a dummy call. */
1392 riscv_type_alignment (struct type
*t
)
1394 t
= check_typedef (t
);
1395 switch (TYPE_CODE (t
))
1398 error (_("Could not compute alignment of type"));
1400 case TYPE_CODE_RVALUE_REF
:
1402 case TYPE_CODE_ENUM
:
1406 case TYPE_CODE_CHAR
:
1407 case TYPE_CODE_BOOL
:
1408 return TYPE_LENGTH (t
);
1410 case TYPE_CODE_ARRAY
:
1411 case TYPE_CODE_COMPLEX
:
1412 return riscv_type_alignment (TYPE_TARGET_TYPE (t
));
1414 case TYPE_CODE_STRUCT
:
1415 case TYPE_CODE_UNION
:
1420 for (i
= 0; i
< TYPE_NFIELDS (t
); ++i
)
1422 if (TYPE_FIELD_LOC_KIND (t
, i
) == FIELD_LOC_KIND_BITPOS
)
1424 int a
= riscv_type_alignment (TYPE_FIELD_TYPE (t
, i
));
1434 /* Holds information about a single argument either being passed to an
1435 inferior function, or returned from an inferior function. This includes
1436 information about the size, type, etc of the argument, and also
1437 information about how the argument will be passed (or returned). */
1439 struct riscv_arg_info
1441 /* Contents of the argument. */
1442 const gdb_byte
*contents
;
1444 /* Length of argument. */
1447 /* Alignment required for an argument of this type. */
1450 /* The type for this argument. */
1453 /* Each argument can have either 1 or 2 locations assigned to it. Each
1454 location describes where part of the argument will be placed. The
1455 second location is valid based on the LOC_TYPE and C_LENGTH fields
1456 of the first location (which is always valid). */
1459 /* What type of location this is. */
1462 /* Argument passed in a register. */
1465 /* Argument passed as an on stack argument. */
1468 /* Argument passed by reference. The second location is always
1469 valid for a BY_REF argument, and describes where the address
1470 of the BY_REF argument should be placed. */
1474 /* Information that depends on the location type. */
1477 /* Which register number to use. */
1480 /* The offset into the stack region. */
1484 /* The length of contents covered by this location. If this is less
1485 than the total length of the argument, then the second location
1486 will be valid, and will describe where the rest of the argument
1490 /* The offset within CONTENTS for this part of the argument. Will
1491 always be 0 for the first part. For the second part of the
1492 argument, this might be the C_LENGTH value of the first part,
1493 however, if we are passing a structure in two registers, and there's
1494 is padding between the first and second field, then this offset
1495 might be greater than the length of the first argument part. When
1496 the second argument location is not holding part of the argument
1497 value, but is instead holding the address of a reference argument,
1498 then this offset will be set to 0. */
1503 /* Information about a set of registers being used for passing arguments as
1504 part of a function call. The register set must be numerically
1505 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1506 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1508 struct riscv_arg_reg
1510 riscv_arg_reg (int first
, int last
)
1511 : next_regnum (first
),
1517 /* The GDB register number to use in this set. */
1520 /* The last GDB register number to use in this set. */
1524 /* Arguments can be passed as on stack arguments, or by reference. The
1525 on stack arguments must be in a continuous region starting from $sp,
1526 while the by reference arguments can be anywhere, but we'll put them
1527 on the stack after (at higher address) the on stack arguments.
1529 This might not be the right approach to take. The ABI is clear that
1530 an argument passed by reference can be modified by the callee, which
1531 us placing the argument (temporarily) onto the stack will not achieve
1532 (changes will be lost). There's also the possibility that very large
1533 arguments could overflow the stack.
1535 This struct is used to track offset into these two areas for where
1536 arguments are to be placed. */
1537 struct riscv_memory_offsets
1539 riscv_memory_offsets ()
1546 /* Offset into on stack argument area. */
1549 /* Offset into the pass by reference area. */
1553 /* Holds information about where arguments to a call will be placed. This
1554 is updated as arguments are added onto the call, and can be used to
1555 figure out where the next argument should be placed. */
1557 struct riscv_call_info
1559 riscv_call_info (struct gdbarch
*gdbarch
)
1560 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1561 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1563 xlen
= riscv_isa_xlen (gdbarch
);
1564 flen
= riscv_isa_flen (gdbarch
);
1566 /* Disable use of floating point registers if needed. */
1567 if (!riscv_has_fp_abi (gdbarch
))
1568 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1571 /* Track the memory areas used for holding in-memory arguments to a
1573 struct riscv_memory_offsets memory
;
1575 /* Holds information about the next integer register to use for passing
1577 struct riscv_arg_reg int_regs
;
1579 /* Holds information about the next floating point register to use for
1580 passing an argument. */
1581 struct riscv_arg_reg float_regs
;
1583 /* The XLEN and FLEN are copied in to this structure for convenience, and
1584 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1589 /* Return the number of registers available for use as parameters in the
1590 register set REG. Returned value can be 0 or more. */
1593 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1595 if (reg
->next_regnum
> reg
->last_regnum
)
1598 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1601 /* If there is at least one register available in the register set REG then
1602 the next register from REG is assigned to LOC and the length field of
1603 LOC is updated to LENGTH. The register set REG is updated to indicate
1604 that the assigned register is no longer available and the function
1607 If there are no registers available in REG then the function returns
1608 false, and LOC and REG are unchanged. */
1611 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1612 struct riscv_arg_reg
*reg
,
1613 int length
, int offset
)
1615 if (reg
->next_regnum
<= reg
->last_regnum
)
1617 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1618 loc
->loc_data
.regno
= reg
->next_regnum
;
1620 loc
->c_length
= length
;
1621 loc
->c_offset
= offset
;
1628 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1629 record that an area of stack has been used to hold the parameter
1632 The length field of LOC is updated to LENGTH, the length of the
1633 parameter being stored, and ALIGN is the alignment required by the
1634 parameter, which will affect how memory is allocated out of MEMORY. */
1637 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1638 struct riscv_memory_offsets
*memory
,
1639 int length
, int align
)
1641 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1643 = align_up (memory
->arg_offset
, align
);
1644 loc
->loc_data
.offset
= memory
->arg_offset
;
1645 memory
->arg_offset
+= length
;
1646 loc
->c_length
= length
;
1648 /* Offset is always 0, either we're the first location part, in which
1649 case we're reading content from the start of the argument, or we're
1650 passing the address of a reference argument, so 0. */
1654 /* Update AINFO, which describes an argument that should be passed or
1655 returned using the integer ABI. The argloc fields within AINFO are
1656 updated to describe the location in which the argument will be passed to
1657 a function, or returned from a function.
1659 The CINFO structure contains the ongoing call information, the holds
1660 information such as which argument registers are remaining to be
1661 assigned to parameter, and how much memory has been used by parameters
1664 By examining the state of CINFO a suitable location can be selected,
1665 and assigned to AINFO. */
1668 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1669 struct riscv_call_info
*cinfo
)
1671 if (ainfo
->length
> (2 * cinfo
->xlen
))
1673 /* Argument is going to be passed by reference. */
1674 ainfo
->argloc
[0].loc_type
1675 = riscv_arg_info::location::by_ref
;
1676 cinfo
->memory
.ref_offset
1677 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1678 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1679 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1680 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1682 /* The second location for this argument is given over to holding the
1683 address of the by-reference data. Pass 0 for the offset as this
1684 is not part of the actual argument value. */
1685 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1688 riscv_assign_stack_location (&ainfo
->argloc
[1],
1689 &cinfo
->memory
, cinfo
->xlen
,
1694 int len
= (ainfo
->length
> cinfo
->xlen
) ? cinfo
->xlen
: ainfo
->length
;
1696 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1697 &cinfo
->int_regs
, len
, 0))
1698 riscv_assign_stack_location (&ainfo
->argloc
[0],
1699 &cinfo
->memory
, len
, ainfo
->align
);
1701 if (len
< ainfo
->length
)
1703 len
= ainfo
->length
- len
;
1704 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1705 &cinfo
->int_regs
, len
,
1707 riscv_assign_stack_location (&ainfo
->argloc
[1],
1708 &cinfo
->memory
, len
, cinfo
->xlen
);
1713 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1714 is being passed with the floating point ABI. */
1717 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1718 struct riscv_call_info
*cinfo
)
1720 if (ainfo
->length
> cinfo
->flen
)
1721 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1724 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1727 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1731 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1732 is a complex floating point argument, and is therefore handled
1733 differently to other argument types. */
1736 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1737 struct riscv_call_info
*cinfo
)
1739 if (ainfo
->length
<= (2 * cinfo
->flen
)
1740 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1743 int len
= ainfo
->length
/ 2;
1745 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1746 &cinfo
->float_regs
, len
, len
);
1747 gdb_assert (result
);
1749 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1750 &cinfo
->float_regs
, len
, len
);
1751 gdb_assert (result
);
1754 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1757 /* A structure used for holding information about a structure type within
1758 the inferior program. The RiscV ABI has special rules for handling some
1759 structures with a single field or with two fields. The counting of
1760 fields here is done after flattening out all nested structures. */
1762 class riscv_struct_info
1765 riscv_struct_info ()
1766 : m_number_of_fields (0),
1767 m_types
{ nullptr, nullptr }
1772 /* Analyse TYPE descending into nested structures, count the number of
1773 scalar fields and record the types of the first two fields found. */
1774 void analyse (struct type
*type
);
1776 /* The number of scalar fields found in the analysed type. This is
1777 currently only accurate if the value returned is 0, 1, or 2 as the
1778 analysis stops counting when the number of fields is 3. This is
1779 because the RiscV ABI only has special cases for 1 or 2 fields,
1780 anything else we just don't care about. */
1781 int number_of_fields () const
1782 { return m_number_of_fields
; }
1784 /* Return the type for scalar field INDEX within the analysed type. Will
1785 return nullptr if there is no field at that index. Only INDEX values
1786 0 and 1 can be requested as the RiscV ABI only has special cases for
1787 structures with 1 or 2 fields. */
1788 struct type
*field_type (int index
) const
1790 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
1791 return m_types
[index
];
1795 /* The number of scalar fields found within the structure after recursing
1796 into nested structures. */
1797 int m_number_of_fields
;
1799 /* The types of the first two scalar fields found within the structure
1800 after recursing into nested structures. */
1801 struct type
*m_types
[2];
1804 /* Analyse TYPE descending into nested structures, count the number of
1805 scalar fields and record the types of the first two fields found. */
1808 riscv_struct_info::analyse (struct type
*type
)
1810 unsigned int count
= TYPE_NFIELDS (type
);
1813 for (i
= 0; i
< count
; ++i
)
1815 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
1818 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
1819 field_type
= check_typedef (field_type
);
1821 switch (TYPE_CODE (field_type
))
1823 case TYPE_CODE_STRUCT
:
1824 analyse (field_type
);
1828 /* RiscV only flattens out structures. Anything else does not
1829 need to be flattened, we just record the type, and when we
1830 look at the analysis results we'll realise this is not a
1831 structure we can special case, and pass the structure in
1833 if (m_number_of_fields
< 2)
1834 m_types
[m_number_of_fields
] = field_type
;
1835 m_number_of_fields
++;
1839 /* RiscV only has special handling for structures with 1 or 2 scalar
1840 fields, any more than that and the structure is just passed in
1841 memory. We can safely drop out early when we find 3 or more
1844 if (m_number_of_fields
> 2)
1849 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1850 is a structure. Small structures on RiscV have some special case
1851 handling in order that the structure might be passed in register.
1852 Larger structures are passed in memory. After assigning location
1853 information to AINFO, CINFO will have been updated. */
1856 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
1857 struct riscv_call_info
*cinfo
)
1859 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
1861 struct riscv_struct_info sinfo
;
1863 sinfo
.analyse (ainfo
->type
);
1864 if (sinfo
.number_of_fields () == 1
1865 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
1867 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1868 == TYPE_LENGTH (sinfo
.field_type (0)));
1869 return riscv_call_arg_complex_float (ainfo
, cinfo
);
1872 if (sinfo
.number_of_fields () == 1
1873 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
1875 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1876 == TYPE_LENGTH (sinfo
.field_type (0)));
1877 return riscv_call_arg_scalar_float (ainfo
, cinfo
);
1880 if (sinfo
.number_of_fields () == 2
1881 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1882 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1883 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1884 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
1885 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1887 int len0
, len1
, offset
;
1889 gdb_assert (TYPE_LENGTH (ainfo
->type
) <= (2 * cinfo
->flen
));
1891 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1892 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1893 &cinfo
->float_regs
, len0
, 0))
1894 error (_("failed during argument setup"));
1896 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1897 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1898 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
1899 - TYPE_LENGTH (sinfo
.field_type (0))));
1901 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1904 error (_("failed during argument setup"));
1908 if (sinfo
.number_of_fields () == 2
1909 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1910 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1911 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1912 && is_integral_type (sinfo
.field_type (1))
1913 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
1915 int len0
, len1
, offset
;
1917 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1918 <= (cinfo
->flen
+ cinfo
->xlen
));
1920 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1921 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1922 &cinfo
->float_regs
, len0
, 0))
1923 error (_("failed during argument setup"));
1925 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1926 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1927 gdb_assert (len1
<= cinfo
->xlen
);
1928 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1929 &cinfo
->int_regs
, len1
, offset
))
1930 error (_("failed during argument setup"));
1934 if (sinfo
.number_of_fields () == 2
1935 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1936 && (is_integral_type (sinfo
.field_type (0))
1937 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
1938 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1939 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
1941 int len0
, len1
, offset
;
1943 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1944 <= (cinfo
->flen
+ cinfo
->xlen
));
1946 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1947 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1948 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1950 gdb_assert (len0
<= cinfo
->xlen
);
1951 gdb_assert (len1
<= cinfo
->flen
);
1953 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1954 &cinfo
->int_regs
, len0
, 0))
1955 error (_("failed during argument setup"));
1957 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1960 error (_("failed during argument setup"));
1966 /* Non of the structure flattening cases apply, so we just pass using
1968 ainfo
->length
= align_up (ainfo
->length
, cinfo
->xlen
);
1969 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1972 /* Assign a location to call (or return) argument AINFO, the location is
1973 selected from CINFO which holds information about what call argument
1974 locations are available for use next. The TYPE is the type of the
1975 argument being passed, this information is recorded into AINFO (along
1976 with some additional information derived from the type).
1978 After assigning a location to AINFO, CINFO will have been updated. */
1981 riscv_arg_location (struct gdbarch
*gdbarch
,
1982 struct riscv_arg_info
*ainfo
,
1983 struct riscv_call_info
*cinfo
,
1987 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
1988 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1989 ainfo
->contents
= nullptr;
1991 switch (TYPE_CODE (ainfo
->type
))
1994 case TYPE_CODE_BOOL
:
1995 case TYPE_CODE_CHAR
:
1996 case TYPE_CODE_RANGE
:
1997 case TYPE_CODE_ENUM
:
1999 if (ainfo
->length
<= cinfo
->xlen
)
2001 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2002 ainfo
->length
= cinfo
->xlen
;
2004 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2006 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2007 ainfo
->length
= 2 * cinfo
->xlen
;
2010 /* Recalculate the alignment requirement. */
2011 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
2012 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2016 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2019 case TYPE_CODE_COMPLEX
:
2020 riscv_call_arg_complex_float (ainfo
, cinfo
);
2023 case TYPE_CODE_STRUCT
:
2024 riscv_call_arg_struct (ainfo
, cinfo
);
2028 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2033 /* Used for printing debug information about the call argument location in
2034 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2035 addresses for the location of pass-by-reference and
2036 arguments-on-the-stack memory areas. */
2039 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2040 struct riscv_arg_info
*info
,
2041 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2043 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2044 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2045 switch (info
->argloc
[0].loc_type
)
2047 case riscv_arg_info::location::in_reg
:
2049 (stream
, ", register %s",
2050 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2051 if (info
->argloc
[0].c_length
< info
->length
)
2053 switch (info
->argloc
[1].loc_type
)
2055 case riscv_arg_info::location::in_reg
:
2057 (stream
, ", register %s",
2058 gdbarch_register_name (gdbarch
,
2059 info
->argloc
[1].loc_data
.regno
));
2062 case riscv_arg_info::location::on_stack
:
2063 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2064 info
->argloc
[1].loc_data
.offset
);
2067 case riscv_arg_info::location::by_ref
:
2069 /* The second location should never be a reference, any
2070 argument being passed by reference just places its address
2071 in the first location and is done. */
2072 error (_("invalid argument location"));
2076 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2077 fprintf_unfiltered (stream
, " (offset 0x%x)",
2078 info
->argloc
[1].c_offset
);
2082 case riscv_arg_info::location::on_stack
:
2083 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2084 info
->argloc
[0].loc_data
.offset
);
2087 case riscv_arg_info::location::by_ref
:
2089 (stream
, ", by reference, data at offset 0x%x (%s)",
2090 info
->argloc
[0].loc_data
.offset
,
2091 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2092 if (info
->argloc
[1].loc_type
2093 == riscv_arg_info::location::in_reg
)
2095 (stream
, ", address in register %s",
2096 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2099 gdb_assert (info
->argloc
[1].loc_type
2100 == riscv_arg_info::location::on_stack
);
2102 (stream
, ", address on stack at offset 0x%x (%s)",
2103 info
->argloc
[1].loc_data
.offset
,
2104 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2109 gdb_assert_not_reached (_("unknown argument location type"));
2113 /* Implement the push dummy call gdbarch callback. */
2116 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2117 struct value
*function
,
2118 struct regcache
*regcache
,
2121 struct value
**args
,
2124 CORE_ADDR struct_addr
)
2127 CORE_ADDR sp_args
, sp_refs
;
2128 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2130 struct riscv_arg_info
*arg_info
=
2131 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2132 struct riscv_arg_info
*info
;
2134 struct riscv_call_info
call_info (gdbarch
);
2138 /* We'll use register $a0 if we're returning a struct. */
2140 ++call_info
.int_regs
.next_regnum
;
2142 for (i
= 0, info
= &arg_info
[0];
2146 struct value
*arg_value
;
2147 struct type
*arg_type
;
2149 arg_value
= args
[i
];
2150 arg_type
= check_typedef (value_type (arg_value
));
2152 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
);
2154 if (info
->type
!= arg_type
)
2155 arg_value
= value_cast (info
->type
, arg_value
);
2156 info
->contents
= value_contents (arg_value
);
2159 /* Adjust the stack pointer and align it. */
2160 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2161 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2163 if (riscv_debug_infcall
> 0)
2165 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2166 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2167 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2168 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2169 call_info
.xlen
, call_info
.flen
);
2171 fprintf_unfiltered (gdb_stdlog
,
2172 "[*] struct return pointer in register $A0\n");
2173 for (i
= 0; i
< nargs
; ++i
)
2175 struct riscv_arg_info
*info
= &arg_info
[i
];
2177 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2178 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2179 fprintf_unfiltered (gdb_stdlog
, "\n");
2181 if (call_info
.memory
.arg_offset
> 0
2182 || call_info
.memory
.ref_offset
> 0)
2184 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2185 core_addr_to_string (osp
));
2186 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2187 call_info
.memory
.arg_offset
);
2188 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2189 call_info
.memory
.ref_offset
);
2190 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2191 core_addr_to_string_nz (osp
- sp
));
2195 /* Now load the argument into registers, or onto the stack. */
2199 gdb_byte buf
[sizeof (LONGEST
)];
2201 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2202 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
2205 for (i
= 0; i
< nargs
; ++i
)
2208 int second_arg_length
= 0;
2209 const gdb_byte
*second_arg_data
;
2210 struct riscv_arg_info
*info
= &arg_info
[i
];
2212 gdb_assert (info
->length
> 0);
2214 switch (info
->argloc
[0].loc_type
)
2216 case riscv_arg_info::location::in_reg
:
2218 gdb_byte tmp
[sizeof (ULONGEST
)];
2220 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2221 memset (tmp
, 0, sizeof (tmp
));
2222 memcpy (tmp
, info
->contents
, info
->argloc
[0].c_length
);
2223 regcache
->cooked_write (info
->argloc
[0].loc_data
.regno
, tmp
);
2225 ((info
->argloc
[0].c_length
< info
->length
)
2226 ? info
->argloc
[1].c_length
: 0);
2227 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2231 case riscv_arg_info::location::on_stack
:
2232 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2233 write_memory (dst
, info
->contents
, info
->length
);
2234 second_arg_length
= 0;
2237 case riscv_arg_info::location::by_ref
:
2238 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2239 write_memory (dst
, info
->contents
, info
->length
);
2241 second_arg_length
= call_info
.xlen
;
2242 second_arg_data
= (gdb_byte
*) &dst
;
2246 gdb_assert_not_reached (_("unknown argument location type"));
2249 if (second_arg_length
> 0)
2251 switch (info
->argloc
[1].loc_type
)
2253 case riscv_arg_info::location::in_reg
:
2255 gdb_byte tmp
[sizeof (ULONGEST
)];
2257 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2258 && second_arg_length
<= call_info
.flen
)
2259 || second_arg_length
<= call_info
.xlen
);
2260 memset (tmp
, 0, sizeof (tmp
));
2261 memcpy (tmp
, second_arg_data
, second_arg_length
);
2262 regcache
->cooked_write (info
->argloc
[1].loc_data
.regno
, tmp
);
2266 case riscv_arg_info::location::on_stack
:
2270 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2271 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2275 case riscv_arg_info::location::by_ref
:
2277 /* The second location should never be a reference, any
2278 argument being passed by reference just places its address
2279 in the first location and is done. */
2280 error (_("invalid argument location"));
2286 /* Set the dummy return value to bp_addr.
2287 A dummy breakpoint will be setup to execute the call. */
2289 if (riscv_debug_infcall
> 0)
2290 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2291 core_addr_to_string (bp_addr
));
2292 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2294 /* Finally, update the stack pointer. */
2296 if (riscv_debug_infcall
> 0)
2297 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2298 core_addr_to_string (sp
));
2299 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2304 /* Implement the return_value gdbarch method. */
2306 static enum return_value_convention
2307 riscv_return_value (struct gdbarch
*gdbarch
,
2308 struct value
*function
,
2310 struct regcache
*regcache
,
2312 const gdb_byte
*writebuf
)
2314 struct riscv_call_info
call_info (gdbarch
);
2315 struct riscv_arg_info info
;
2316 struct type
*arg_type
;
2318 arg_type
= check_typedef (type
);
2319 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
);
2321 if (riscv_debug_infcall
> 0)
2323 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2324 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2325 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2326 fprintf_unfiltered (gdb_stdlog
, "\n");
2329 if (readbuf
!= nullptr || writebuf
!= nullptr)
2333 switch (info
.argloc
[0].loc_type
)
2335 /* Return value in register(s). */
2336 case riscv_arg_info::location::in_reg
:
2338 regnum
= info
.argloc
[0].loc_data
.regno
;
2341 regcache
->cooked_read (regnum
, readbuf
);
2344 regcache
->cooked_write (regnum
, writebuf
);
2346 /* A return value in register can have a second part in a
2348 if (info
.argloc
[0].c_length
< info
.length
)
2350 switch (info
.argloc
[1].loc_type
)
2352 case riscv_arg_info::location::in_reg
:
2353 regnum
= info
.argloc
[1].loc_data
.regno
;
2357 readbuf
+= info
.argloc
[1].c_offset
;
2358 regcache
->cooked_read (regnum
, readbuf
);
2363 writebuf
+= info
.argloc
[1].c_offset
;
2364 regcache
->cooked_write (regnum
, writebuf
);
2368 case riscv_arg_info::location::by_ref
:
2369 case riscv_arg_info::location::on_stack
:
2371 error (_("invalid argument location"));
2378 /* Return value by reference will have its address in A0. */
2379 case riscv_arg_info::location::by_ref
:
2383 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2385 if (readbuf
!= nullptr)
2386 read_memory (addr
, readbuf
, info
.length
);
2387 if (writebuf
!= nullptr)
2388 write_memory (addr
, writebuf
, info
.length
);
2392 case riscv_arg_info::location::on_stack
:
2394 error (_("invalid argument location"));
2399 switch (info
.argloc
[0].loc_type
)
2401 case riscv_arg_info::location::in_reg
:
2402 return RETURN_VALUE_REGISTER_CONVENTION
;
2403 case riscv_arg_info::location::by_ref
:
2404 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2405 case riscv_arg_info::location::on_stack
:
2407 error (_("invalid argument location"));
2411 /* Implement the frame_align gdbarch method. */
2414 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2416 return align_down (addr
, 16);
2419 /* Implement the unwind_pc gdbarch method. */
2422 riscv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2424 return frame_unwind_register_unsigned (next_frame
, RISCV_PC_REGNUM
);
2427 /* Implement the unwind_sp gdbarch method. */
2430 riscv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2432 return frame_unwind_register_unsigned (next_frame
, RISCV_SP_REGNUM
);
2435 /* Implement the dummy_id gdbarch method. */
2437 static struct frame_id
2438 riscv_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2440 return frame_id_build (get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
),
2441 get_frame_pc (this_frame
));
2444 /* Generate, or return the cached frame cache for the RiscV frame
2447 static struct trad_frame_cache
*
2448 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2451 CORE_ADDR start_addr
;
2452 CORE_ADDR stack_addr
;
2453 struct trad_frame_cache
*this_trad_cache
;
2454 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2456 if ((*this_cache
) != NULL
)
2457 return (struct trad_frame_cache
*) *this_cache
;
2458 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2459 (*this_cache
) = this_trad_cache
;
2461 trad_frame_set_reg_realreg (this_trad_cache
, gdbarch_pc_regnum (gdbarch
),
2464 pc
= get_frame_pc (this_frame
);
2465 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2466 stack_addr
= get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
);
2467 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2469 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2471 return this_trad_cache
;
2474 /* Implement the this_id callback for RiscV frame unwinder. */
2477 riscv_frame_this_id (struct frame_info
*this_frame
,
2478 void **prologue_cache
,
2479 struct frame_id
*this_id
)
2481 struct trad_frame_cache
*info
;
2483 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2484 trad_frame_get_id (info
, this_id
);
2487 /* Implement the prev_register callback for RiscV frame unwinder. */
2489 static struct value
*
2490 riscv_frame_prev_register (struct frame_info
*this_frame
,
2491 void **prologue_cache
,
2494 struct trad_frame_cache
*info
;
2496 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2497 return trad_frame_get_register (info
, this_frame
, regnum
);
2500 /* Structure defining the RiscV normal frame unwind functions. Since we
2501 are the fallback unwinder (DWARF unwinder is used first), we use the
2502 default frame sniffer, which always accepts the frame. */
2504 static const struct frame_unwind riscv_frame_unwind
=
2506 /*.type =*/ NORMAL_FRAME
,
2507 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2508 /*.this_id =*/ riscv_frame_this_id
,
2509 /*.prev_register =*/ riscv_frame_prev_register
,
2510 /*.unwind_data =*/ NULL
,
2511 /*.sniffer =*/ default_frame_sniffer
,
2512 /*.dealloc_cache =*/ NULL
,
2513 /*.prev_arch =*/ NULL
,
2516 /* Initialize the current architecture based on INFO. If possible,
2517 re-use an architecture from ARCHES, which is a list of
2518 architectures already created during this debugging session.
2520 Called e.g. at program startup, when reading a core file, and when
2521 reading a binary file. */
2523 static struct gdbarch
*
2524 riscv_gdbarch_init (struct gdbarch_info info
,
2525 struct gdbarch_list
*arches
)
2527 struct gdbarch
*gdbarch
;
2528 struct gdbarch_tdep
*tdep
;
2529 struct gdbarch_tdep tmp_tdep
;
2532 /* Ideally, we'd like to get as much information from the target for
2533 things like register size, and whether the target has floating point
2534 hardware. However, there are some things that the target can't tell
2535 us, like, what ABI is being used.
2537 So, for now, we take as much information as possible from the ELF,
2538 including things like register size, and FP hardware support, along
2539 with information about the ABI.
2541 Information about this target is built up in TMP_TDEP, and then we
2542 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2543 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2544 memset (&tmp_tdep
, 0, sizeof (tmp_tdep
));
2546 if (info
.abfd
!= NULL
2547 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2549 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2550 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2552 if (eclass
== ELFCLASS32
)
2553 tmp_tdep
.abi
.fields
.base_len
= 1;
2554 else if (eclass
== ELFCLASS64
)
2555 tmp_tdep
.abi
.fields
.base_len
= 2;
2557 internal_error (__FILE__
, __LINE__
,
2558 _("unknown ELF header class %d"), eclass
);
2560 if (e_flags
& EF_RISCV_RVC
)
2561 tmp_tdep
.core_features
|= (1 << ('C' - 'A'));
2563 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2565 tmp_tdep
.abi
.fields
.float_abi
= 2;
2566 tmp_tdep
.core_features
|= (1 << ('D' - 'A'));
2567 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2569 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2571 tmp_tdep
.abi
.fields
.float_abi
= 1;
2572 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2577 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2579 if (binfo
->bits_per_word
== 32)
2580 tmp_tdep
.abi
.fields
.base_len
= 1;
2581 else if (binfo
->bits_per_word
== 64)
2582 tmp_tdep
.abi
.fields
.base_len
= 2;
2584 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2585 binfo
->bits_per_word
);
2588 /* Find a candidate among the list of pre-declared architectures. */
2589 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2591 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2592 if (gdbarch_tdep (arches
->gdbarch
)->abi
.value
== tmp_tdep
.abi
.value
)
2593 return arches
->gdbarch
;
2595 /* None found, so create a new architecture from the information provided. */
2596 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof *tdep
);
2597 gdbarch
= gdbarch_alloc (&info
, tdep
);
2598 memcpy (tdep
, &tmp_tdep
, sizeof (tmp_tdep
));
2600 /* Target data types. */
2601 set_gdbarch_short_bit (gdbarch
, 16);
2602 set_gdbarch_int_bit (gdbarch
, 32);
2603 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2604 set_gdbarch_long_long_bit (gdbarch
, 64);
2605 set_gdbarch_float_bit (gdbarch
, 32);
2606 set_gdbarch_double_bit (gdbarch
, 64);
2607 set_gdbarch_long_double_bit (gdbarch
, 128);
2608 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
2609 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2610 set_gdbarch_char_signed (gdbarch
, 0);
2612 /* Information about the target architecture. */
2613 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
2614 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
2615 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
2617 /* Register architecture. */
2618 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
2619 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
2620 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
2621 set_gdbarch_ps_regnum (gdbarch
, RISCV_FP_REGNUM
);
2622 set_gdbarch_deprecated_fp_regnum (gdbarch
, RISCV_FP_REGNUM
);
2624 /* Functions to supply register information. */
2625 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
2626 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
2627 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
2628 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
2630 /* Functions to analyze frames. */
2631 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
2632 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2633 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
2635 /* Functions to access frame data. */
2636 set_gdbarch_unwind_pc (gdbarch
, riscv_unwind_pc
);
2637 set_gdbarch_unwind_sp (gdbarch
, riscv_unwind_sp
);
2639 /* Functions handling dummy frames. */
2640 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2641 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
2642 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
2643 set_gdbarch_dummy_id (gdbarch
, riscv_dummy_id
);
2645 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2647 dwarf2_append_unwinders (gdbarch
);
2648 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
2650 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
2651 user_reg_add (gdbarch
, riscv_register_aliases
[i
].name
,
2652 value_of_riscv_user_reg
, &riscv_register_aliases
[i
].regnum
);
2654 /* Hook in OS ABI-specific overrides, if they have been registered. */
2655 gdbarch_init_osabi (info
, gdbarch
);
2660 /* This decodes the current instruction and determines the address of the
2661 next instruction. */
2664 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2666 struct gdbarch
*gdbarch
= regcache
->arch ();
2667 struct riscv_insn insn
;
2670 insn
.decode (gdbarch
, pc
);
2671 next_pc
= pc
+ insn
.length ();
2673 if (insn
.opcode () == riscv_insn::JAL
)
2674 next_pc
= pc
+ insn
.imm_signed ();
2675 else if (insn
.opcode () == riscv_insn::JALR
)
2678 regcache
->cooked_read (insn
.rs1 (), &source
);
2679 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
2681 else if (insn
.opcode () == riscv_insn::BEQ
)
2684 regcache
->cooked_read (insn
.rs1 (), &src1
);
2685 regcache
->cooked_read (insn
.rs2 (), &src2
);
2687 next_pc
= pc
+ insn
.imm_signed ();
2689 else if (insn
.opcode () == riscv_insn::BNE
)
2692 regcache
->cooked_read (insn
.rs1 (), &src1
);
2693 regcache
->cooked_read (insn
.rs2 (), &src2
);
2695 next_pc
= pc
+ insn
.imm_signed ();
2697 else if (insn
.opcode () == riscv_insn::BLT
)
2700 regcache
->cooked_read (insn
.rs1 (), &src1
);
2701 regcache
->cooked_read (insn
.rs2 (), &src2
);
2703 next_pc
= pc
+ insn
.imm_signed ();
2705 else if (insn
.opcode () == riscv_insn::BGE
)
2708 regcache
->cooked_read (insn
.rs1 (), &src1
);
2709 regcache
->cooked_read (insn
.rs2 (), &src2
);
2711 next_pc
= pc
+ insn
.imm_signed ();
2713 else if (insn
.opcode () == riscv_insn::BLTU
)
2715 ULONGEST src1
, src2
;
2716 regcache
->cooked_read (insn
.rs1 (), &src1
);
2717 regcache
->cooked_read (insn
.rs2 (), &src2
);
2719 next_pc
= pc
+ insn
.imm_signed ();
2721 else if (insn
.opcode () == riscv_insn::BGEU
)
2723 ULONGEST src1
, src2
;
2724 regcache
->cooked_read (insn
.rs1 (), &src1
);
2725 regcache
->cooked_read (insn
.rs2 (), &src2
);
2727 next_pc
= pc
+ insn
.imm_signed ();
2733 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
2734 for the end of the sequence and put the breakpoint there. */
2737 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
2740 struct gdbarch
*gdbarch
= regcache
->arch ();
2741 struct riscv_insn insn
;
2742 CORE_ADDR cur_step_pc
= pc
;
2743 CORE_ADDR last_addr
= 0;
2745 /* First instruction has to be a load reserved. */
2746 insn
.decode (gdbarch
, cur_step_pc
);
2747 if (insn
.opcode () != riscv_insn::LR
)
2749 cur_step_pc
= cur_step_pc
+ insn
.length ();
2751 /* Next instruction should be branch to exit. */
2752 insn
.decode (gdbarch
, cur_step_pc
);
2753 if (insn
.opcode () != riscv_insn::BNE
)
2755 last_addr
= cur_step_pc
+ insn
.imm_signed ();
2756 cur_step_pc
= cur_step_pc
+ insn
.length ();
2758 /* Next instruction should be store conditional. */
2759 insn
.decode (gdbarch
, cur_step_pc
);
2760 if (insn
.opcode () != riscv_insn::SC
)
2762 cur_step_pc
= cur_step_pc
+ insn
.length ();
2764 /* Next instruction should be branch to start. */
2765 insn
.decode (gdbarch
, cur_step_pc
);
2766 if (insn
.opcode () != riscv_insn::BNE
)
2768 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
2770 cur_step_pc
= cur_step_pc
+ insn
.length ();
2772 /* We should now be at the end of the sequence. */
2773 if (cur_step_pc
!= last_addr
)
2776 *next_pc
= cur_step_pc
;
2780 /* This is called just before we want to resume the inferior, if we want to
2781 single-step it but there is no hardware or kernel single-step support. We
2782 find the target of the coming instruction and breakpoint it. */
2784 std::vector
<CORE_ADDR
>
2785 riscv_software_single_step (struct regcache
*regcache
)
2787 CORE_ADDR pc
, next_pc
;
2789 pc
= regcache_read_pc (regcache
);
2791 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
2794 next_pc
= riscv_next_pc (regcache
, pc
);
2800 _initialize_riscv_tdep (void)
2802 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
2804 /* Add root prefix command for all "set debug riscv" and "show debug
2806 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
2807 _("RISC-V specific debug commands."),
2808 &setdebugriscvcmdlist
, "set debug riscv ", 0,
2811 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
2812 _("RISC-V specific debug commands."),
2813 &showdebugriscvcmdlist
, "show debug riscv ", 0,
2816 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
2817 &riscv_debug_infcall
, _("\
2818 Set riscv inferior call debugging."), _("\
2819 Show riscv inferior call debugging."), _("\
2820 When non-zero, print debugging information for the riscv specific parts\n\
2821 of the inferior call mechanism."),
2823 show_riscv_debug_variable
,
2824 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
2826 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2827 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
2828 _("RISC-V specific commands."),
2829 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
2831 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
2832 _("RISC-V specific commands."),
2833 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
2836 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
2837 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
2838 &use_compressed_breakpoints
,
2840 Set debugger's use of compressed breakpoints."), _(" \
2841 Show debugger's use of compressed breakpoints."), _("\
2842 Debugging compressed code requires compressed breakpoints to be used. If\n \
2843 left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2844 is supported. If that doesn't give the correct behavior, then this option\n\
2847 show_use_compressed_breakpoints
,