1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
58 /* The stack must be 16-byte aligned. */
59 #define SP_ALIGNMENT 16
61 /* Forward declarations. */
62 static bool riscv_has_feature (struct gdbarch
*gdbarch
, char feature
);
63 struct riscv_inferior_data
;
64 struct riscv_inferior_data
* riscv_inferior_data (struct inferior
*const inf
);
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Per inferior information for RiscV. */
78 struct riscv_inferior_data
80 /* True when MISA_VALUE is valid, otherwise false. */
83 /* If MISA_READ is true then MISA_VALUE holds the value of the MISA
84 register read from the target. */
88 /* Key created when the RiscV per-inferior data is registered. */
90 static const struct inferior_data
*riscv_inferior_data_reg
;
92 /* Architectural name for core registers. */
94 static const char * const riscv_gdb_reg_names
[RISCV_LAST_FP_REGNUM
+ 1] =
96 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
97 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
98 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
99 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
101 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
102 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
103 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
104 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
107 /* Maps "pretty" register names onto their GDB register number. */
109 struct register_alias
111 /* The register alias. Usually more descriptive than the
112 architectural name of the register. */
115 /* The GDB register number. */
119 /* Table of register aliases. */
121 static const struct register_alias riscv_register_aliases
[] =
189 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
190 #include "opcode/riscv-opc.h"
194 /* Controls whether we place compressed breakpoints or not. When in auto
195 mode GDB tries to determine if the target supports compressed
196 breakpoints, and uses them if it does. */
198 static enum auto_boolean use_compressed_breakpoints
;
200 /* The show callback for 'show riscv use-compressed-breakpoints'. */
203 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
204 struct cmd_list_element
*c
,
207 const char *additional_info
;
208 struct gdbarch
*gdbarch
= target_gdbarch ();
210 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
211 if (riscv_has_feature (gdbarch
, 'C'))
212 additional_info
= _(" (currently on)");
214 additional_info
= _(" (currently off)");
216 additional_info
= "";
218 fprintf_filtered (file
,
219 _("Debugger's use of compressed breakpoints is set "
220 "to %s%s.\n"), value
, additional_info
);
223 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
225 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
226 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
228 /* The show callback for the 'show riscv' prefix command. */
231 show_riscv_command (const char *args
, int from_tty
)
233 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
236 /* The set callback for the 'set riscv' prefix command. */
239 set_riscv_command (const char *args
, int from_tty
)
242 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
243 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
246 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
248 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
249 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
251 /* The show callback for the 'show debug riscv' prefix command. */
254 show_debug_riscv_command (const char *args
, int from_tty
)
256 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
259 /* The set callback for the 'set debug riscv' prefix command. */
262 set_debug_riscv_command (const char *args
, int from_tty
)
265 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
266 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
269 /* The show callback for all 'show debug riscv VARNAME' variables. */
272 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
273 struct cmd_list_element
*c
,
276 fprintf_filtered (file
,
277 _("RiscV debug variable `%s' is set to: %s\n"),
281 /* When this is set to non-zero debugging information about inferior calls
284 static unsigned int riscv_debug_infcall
= 0;
286 /* Read the MISA register from the target. The register will only be read
287 once, and the value read will be cached. If the register can't be read
288 from the target then a default value (0) will be returned. If the
289 pointer READ_P is not null, then the bool pointed to is updated to
290 indicate if the value returned was read from the target (true) or is the
294 riscv_read_misa_reg (bool *read_p
)
296 struct riscv_inferior_data
*inf_data
297 = riscv_inferior_data (current_inferior ());
299 if (!inf_data
->misa_read
&& target_has_registers
)
302 struct frame_info
*frame
= get_current_frame ();
306 value
= get_frame_register_unsigned (frame
, RISCV_CSR_MISA_REGNUM
);
308 CATCH (ex
, RETURN_MASK_ERROR
)
310 /* Old cores might have MISA located at a different offset. */
311 value
= get_frame_register_unsigned (frame
,
312 RISCV_CSR_LEGACY_MISA_REGNUM
);
316 inf_data
->misa_read
= true;
317 inf_data
->misa_value
= value
;
320 if (read_p
!= nullptr)
321 *read_p
= inf_data
->misa_read
;
323 return inf_data
->misa_value
;
326 /* Return true if FEATURE is available for the architecture GDBARCH. The
327 FEATURE should be one of the single character feature codes described in
328 the RiscV ISA manual, these are between 'A' and 'Z'. */
331 riscv_has_feature (struct gdbarch
*gdbarch
, char feature
)
333 bool have_read_misa
= false;
336 gdb_assert (feature
>= 'A' && feature
<= 'Z');
338 misa
= riscv_read_misa_reg (&have_read_misa
);
339 if (!have_read_misa
|| misa
== 0)
340 misa
= gdbarch_tdep (gdbarch
)->core_features
;
342 return (misa
& (1 << (feature
- 'A'))) != 0;
345 /* Return the width in bytes of the general purpose registers for GDBARCH.
346 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
350 riscv_isa_xlen (struct gdbarch
*gdbarch
)
352 switch (gdbarch_tdep (gdbarch
)->abi
.fields
.base_len
)
355 warning (_("unknown xlen size, assuming 4 bytes"));
366 /* Return the width in bytes of the floating point registers for GDBARCH.
367 If this architecture has no floating point registers, then return 0.
368 Possible values are 4, 8, or 16 for depending on which of single, double
369 or quad floating point support is available. */
372 riscv_isa_flen (struct gdbarch
*gdbarch
)
374 if (riscv_has_feature (gdbarch
, 'Q'))
376 else if (riscv_has_feature (gdbarch
, 'D'))
378 else if (riscv_has_feature (gdbarch
, 'F'))
384 /* Return true if the target for GDBARCH has floating point hardware. */
387 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
389 return (riscv_isa_flen (gdbarch
) > 0);
392 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
395 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
397 return (gdbarch_tdep (gdbarch
)->abi
.fields
.float_abi
!= 0);
400 /* Return true if REGNO is a floating pointer register. */
403 riscv_is_fp_regno_p (int regno
)
405 return (regno
>= RISCV_FIRST_FP_REGNUM
406 && regno
<= RISCV_LAST_FP_REGNUM
);
409 /* Implement the breakpoint_kind_from_pc gdbarch method. */
412 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
414 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
416 if (riscv_has_feature (gdbarch
, 'C'))
421 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
427 /* Implement the sw_breakpoint_from_kind gdbarch method. */
429 static const gdb_byte
*
430 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
432 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
433 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
443 gdb_assert_not_reached (_("unhandled breakpoint kind"));
447 /* Callback function for user_reg_add. */
449 static struct value
*
450 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
452 const int *reg_p
= (const int *) baton
;
453 return value_of_register (*reg_p
, frame
);
456 /* Implement the register_name gdbarch method. */
459 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
461 /* Prefer to use the alias. */
462 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_REGNUM
)
466 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
467 if (regnum
== riscv_register_aliases
[i
].regnum
)
468 return riscv_register_aliases
[i
].name
;
471 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
472 return riscv_gdb_reg_names
[regnum
];
474 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
478 xsnprintf (buf
, sizeof (buf
), "csr%d",
479 regnum
- RISCV_FIRST_CSR_REGNUM
);
483 if (regnum
== RISCV_PRIV_REGNUM
)
489 /* Implement the register_type gdbarch method. */
492 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
496 if (regnum
< RISCV_FIRST_FP_REGNUM
)
498 if (regnum
== gdbarch_pc_regnum (gdbarch
)
499 || regnum
== RISCV_RA_REGNUM
)
500 return builtin_type (gdbarch
)->builtin_func_ptr
;
502 if (regnum
== RISCV_FP_REGNUM
503 || regnum
== RISCV_SP_REGNUM
504 || regnum
== RISCV_GP_REGNUM
505 || regnum
== RISCV_TP_REGNUM
)
506 return builtin_type (gdbarch
)->builtin_data_ptr
;
508 /* Remaining GPRs vary in size based on the current ISA. */
509 regsize
= riscv_isa_xlen (gdbarch
);
513 return builtin_type (gdbarch
)->builtin_uint32
;
515 return builtin_type (gdbarch
)->builtin_uint64
;
517 return builtin_type (gdbarch
)->builtin_uint128
;
519 internal_error (__FILE__
, __LINE__
,
520 _("unknown isa regsize %i"), regsize
);
523 else if (regnum
<= RISCV_LAST_FP_REGNUM
)
525 regsize
= riscv_isa_xlen (gdbarch
);
529 return builtin_type (gdbarch
)->builtin_float
;
531 return builtin_type (gdbarch
)->builtin_double
;
533 return builtin_type (gdbarch
)->builtin_long_double
;
535 internal_error (__FILE__
, __LINE__
,
536 _("unknown isa regsize %i"), regsize
);
539 else if (regnum
== RISCV_PRIV_REGNUM
)
540 return builtin_type (gdbarch
)->builtin_int8
;
543 if (regnum
== RISCV_CSR_FFLAGS_REGNUM
544 || regnum
== RISCV_CSR_FRM_REGNUM
545 || regnum
== RISCV_CSR_FCSR_REGNUM
)
546 return builtin_type (gdbarch
)->builtin_int32
;
548 regsize
= riscv_isa_xlen (gdbarch
);
552 return builtin_type (gdbarch
)->builtin_int32
;
554 return builtin_type (gdbarch
)->builtin_int64
;
556 return builtin_type (gdbarch
)->builtin_int128
;
558 internal_error (__FILE__
, __LINE__
,
559 _("unknown isa regsize %i"), regsize
);
564 /* Helper for riscv_print_registers_info, prints info for a single register
568 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
569 struct ui_file
*file
,
570 struct frame_info
*frame
,
573 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
574 struct value
*val
= value_of_register (regnum
, frame
);
575 struct type
*regtype
= value_type (val
);
576 int print_raw_format
;
577 enum tab_stops
{ value_column_1
= 15 };
579 fputs_filtered (name
, file
);
580 print_spaces_filtered (value_column_1
- strlen (name
), file
);
582 print_raw_format
= (value_entirely_available (val
)
583 && !value_optimized_out (val
));
585 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
)
587 struct value_print_options opts
;
588 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
589 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
591 get_user_print_options (&opts
);
595 value_embedded_offset (val
), 0,
596 file
, 0, val
, &opts
, current_language
);
598 if (print_raw_format
)
600 fprintf_filtered (file
, "\t(raw ");
601 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
603 fprintf_filtered (file
, ")");
608 struct value_print_options opts
;
610 /* Print the register in hex. */
611 get_formatted_print_options (&opts
, 'x');
614 value_embedded_offset (val
), 0,
615 file
, 0, val
, &opts
, current_language
);
617 if (print_raw_format
)
619 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
622 int size
= register_size (gdbarch
, regnum
);
625 d
= value_as_long (val
);
627 fprintf_filtered (file
,
628 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
629 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
630 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
631 (int) ((d
>> (xlen
- 1)) & 0x1),
632 (int) ((d
>> 24) & 0x1f),
633 (int) ((d
>> 19) & 0x1),
634 (int) ((d
>> 18) & 0x1),
635 (int) ((d
>> 17) & 0x1),
636 (int) ((d
>> 15) & 0x3),
637 (int) ((d
>> 13) & 0x3),
638 (int) ((d
>> 11) & 0x3),
639 (int) ((d
>> 9) & 0x3),
640 (int) ((d
>> 8) & 0x1),
641 (int) ((d
>> 7) & 0x1),
642 (int) ((d
>> 6) & 0x1),
643 (int) ((d
>> 5) & 0x1),
644 (int) ((d
>> 4) & 0x1),
645 (int) ((d
>> 3) & 0x1),
646 (int) ((d
>> 2) & 0x1),
647 (int) ((d
>> 1) & 0x1),
648 (int) ((d
>> 0) & 0x1));
650 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
656 d
= value_as_long (val
);
660 for (; base
> 0; base
--)
662 fprintf_filtered (file
, "\tRV%d", xlen
);
664 for (i
= 0; i
< 26; i
++)
667 fprintf_filtered (file
, "%c", 'A' + i
);
670 else if (regnum
== RISCV_CSR_FCSR_REGNUM
671 || regnum
== RISCV_CSR_FFLAGS_REGNUM
672 || regnum
== RISCV_CSR_FRM_REGNUM
)
676 d
= value_as_long (val
);
678 fprintf_filtered (file
, "\t");
679 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
680 fprintf_filtered (file
,
681 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
682 (int) ((d
>> 5) & 0x7),
683 (int) ((d
>> 4) & 0x1),
684 (int) ((d
>> 3) & 0x1),
685 (int) ((d
>> 2) & 0x1),
686 (int) ((d
>> 1) & 0x1),
687 (int) ((d
>> 0) & 0x1));
689 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
691 static const char * const sfrm
[] =
693 "RNE (round to nearest; ties to even)",
694 "RTZ (Round towards zero)",
695 "RDN (Round down towards -INF)",
696 "RUP (Round up towards +INF)",
697 "RMM (Round to nearest; ties to max magnitude)",
700 "dynamic rounding mode",
702 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
703 ? (d
>> 5) : d
) & 0x3;
705 fprintf_filtered (file
, "%sFRM:%i [%s]",
706 (regnum
== RISCV_CSR_FCSR_REGNUM
711 else if (regnum
== RISCV_PRIV_REGNUM
)
716 d
= value_as_long (val
);
721 static const char * const sprv
[] =
728 fprintf_filtered (file
, "\tprv:%d [%s]",
732 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
736 /* If not a vector register, print it also according to its
738 if (TYPE_VECTOR (regtype
) == 0)
740 get_user_print_options (&opts
);
742 fprintf_filtered (file
, "\t");
744 value_embedded_offset (val
), 0,
745 file
, 0, val
, &opts
, current_language
);
750 fprintf_filtered (file
, "\n");
753 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
757 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
758 struct reggroup
*reggroup
)
762 /* Used by 'info registers' and 'info registers <groupname>'. */
764 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
765 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
768 if (reggroup
== all_reggroup
)
770 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
772 /* Only include CSRs that have aliases. */
773 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
775 if (regnum
== riscv_register_aliases
[i
].regnum
)
780 else if (reggroup
== float_reggroup
)
781 return (riscv_is_fp_regno_p (regnum
)
782 || regnum
== RISCV_CSR_FCSR_REGNUM
783 || regnum
== RISCV_CSR_FFLAGS_REGNUM
784 || regnum
== RISCV_CSR_FRM_REGNUM
);
785 else if (reggroup
== general_reggroup
)
786 return regnum
< RISCV_FIRST_FP_REGNUM
;
787 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
789 if (riscv_has_fp_regs (gdbarch
))
790 return regnum
<= RISCV_LAST_FP_REGNUM
;
792 return regnum
< RISCV_FIRST_FP_REGNUM
;
794 else if (reggroup
== system_reggroup
)
796 if (regnum
== RISCV_PRIV_REGNUM
)
798 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
800 /* Only include CSRs that have aliases. */
801 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
803 if (regnum
== riscv_register_aliases
[i
].regnum
)
808 else if (reggroup
== vector_reggroup
)
814 /* Implement the print_registers_info gdbarch method. This is used by
815 'info registers' and 'info all-registers'. */
818 riscv_print_registers_info (struct gdbarch
*gdbarch
,
819 struct ui_file
*file
,
820 struct frame_info
*frame
,
821 int regnum
, int print_all
)
825 /* Print one specified register. */
826 gdb_assert (regnum
<= RISCV_LAST_REGNUM
);
827 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
828 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
829 error (_("Not a valid register for the current processor type"));
830 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
834 struct reggroup
*reggroup
;
837 reggroup
= all_reggroup
;
839 reggroup
= general_reggroup
;
841 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
843 /* Zero never changes, so might as well hide by default. */
844 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
847 /* Registers with no name are not valid on this ISA. */
848 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
849 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
852 /* Is the register in the group we're interested in? */
853 if (!riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
))
856 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
861 /* Class that handles one decoded RiscV instruction. */
867 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
870 /* Unknown value is used at initialisation time. */
873 /* These instructions are all the ones we are interested in during the
884 /* Other instructions are not interesting during the prologue scan, and
899 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
901 /* Get the length of the instruction in bytes. */
905 /* Get the opcode for this instruction. */
906 enum opcode
opcode () const
909 /* Get destination register field for this instruction. This is only
910 valid if the OPCODE implies there is such a field for this
915 /* Get the RS1 register field for this instruction. This is only valid
916 if the OPCODE implies there is such a field for this instruction. */
920 /* Get the RS2 register field for this instruction. This is only valid
921 if the OPCODE implies there is such a field for this instruction. */
925 /* Get the immediate for this instruction in signed form. This is only
926 valid if the OPCODE implies there is such a field for this
928 int imm_signed () const
933 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
934 int decode_register_index (unsigned long opcode
, int offset
)
936 return (opcode
>> offset
) & 0x1F;
939 /* Helper for DECODE, decode 32-bit R-type instruction. */
940 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
943 m_rd
= decode_register_index (ival
, OP_SH_RD
);
944 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
945 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
948 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
949 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
952 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
953 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
956 /* Helper for DECODE, decode 32-bit I-type instruction. */
957 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
960 m_rd
= decode_register_index (ival
, OP_SH_RD
);
961 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
962 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
965 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
966 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
969 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
970 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
973 /* Helper for DECODE, decode 32-bit S-type instruction. */
974 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
977 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
978 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
979 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
982 /* Helper for DECODE, decode 32-bit U-type instruction. */
983 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
986 m_rd
= decode_register_index (ival
, OP_SH_RD
);
987 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
990 /* Fetch instruction from target memory at ADDR, return the content of
991 the instruction, and update LEN with the instruction length. */
992 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
993 CORE_ADDR addr
, int *len
);
995 /* The length of the instruction in bytes. Should be 2 or 4. */
998 /* The instruction opcode. */
999 enum opcode m_opcode
;
1001 /* The three possible registers an instruction might reference. Not
1002 every instruction fills in all of these registers. Which fields are
1003 valid depends on the opcode. The naming of these fields matches the
1004 naming in the riscv isa manual. */
1009 /* Possible instruction immediate. This is only valid if the instruction
1010 format contains an immediate, not all instruction, whether this is
1011 valid depends on the opcode. Despite only having one format for now
1012 the immediate is packed into a union, later instructions might require
1013 an unsigned formatted immediate, having the union in place now will
1014 reduce the need for code churn later. */
1015 union riscv_insn_immediate
1017 riscv_insn_immediate ()
1027 /* Fetch instruction from target memory at ADDR, return the content of the
1028 instruction, and update LEN with the instruction length. */
1031 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1032 CORE_ADDR addr
, int *len
)
1034 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1036 int instlen
, status
;
1038 /* All insns are at least 16 bits. */
1039 status
= target_read_memory (addr
, buf
, 2);
1041 memory_error (TARGET_XFER_E_IO
, addr
);
1043 /* If we need more, grab it now. */
1044 instlen
= riscv_insn_length (buf
[0]);
1045 gdb_assert (instlen
<= sizeof (buf
));
1050 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1052 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1055 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1058 /* Fetch from target memory an instruction at PC and decode it. */
1061 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1065 /* Fetch the instruction, and the instructions length. */
1066 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1070 if (is_add_insn (ival
))
1071 decode_r_type_insn (ADD
, ival
);
1072 else if (is_addw_insn (ival
))
1073 decode_r_type_insn (ADDW
, ival
);
1074 else if (is_addi_insn (ival
))
1075 decode_i_type_insn (ADDI
, ival
);
1076 else if (is_addiw_insn (ival
))
1077 decode_i_type_insn (ADDIW
, ival
);
1078 else if (is_auipc_insn (ival
))
1079 decode_u_type_insn (AUIPC
, ival
);
1080 else if (is_lui_insn (ival
))
1081 decode_u_type_insn (LUI
, ival
);
1082 else if (is_sd_insn (ival
))
1083 decode_s_type_insn (SD
, ival
);
1084 else if (is_sw_insn (ival
))
1085 decode_s_type_insn (SW
, ival
);
1087 /* None of the other fields are valid in this case. */
1090 else if (m_length
== 2)
1092 if (is_c_add_insn (ival
))
1093 decode_cr_type_insn (ADD
, ival
);
1094 else if (is_c_addw_insn (ival
))
1095 decode_cr_type_insn (ADDW
, ival
);
1096 else if (is_c_addi_insn (ival
))
1097 decode_ci_type_insn (ADDI
, ival
);
1098 else if (is_c_addiw_insn (ival
))
1099 decode_ci_type_insn (ADDIW
, ival
);
1100 else if (is_c_addi16sp_insn (ival
))
1103 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1104 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1106 else if (is_lui_insn (ival
))
1108 else if (is_c_sd_insn (ival
))
1110 else if (is_sw_insn (ival
))
1113 /* None of the other fields of INSN are valid in this case. */
1117 internal_error (__FILE__
, __LINE__
,
1118 _("unable to decode %d byte instructions in "
1119 "prologue at %s"), m_length
,
1120 core_addr_to_string (pc
));
1123 /* The prologue scanner. This is currently only used for skipping the
1124 prologue of a function when the DWARF information is not sufficient.
1125 However, it is written with filling of the frame cache in mind, which
1126 is why different groups of stack setup instructions are split apart
1127 during the core of the inner loop. In the future, the intention is to
1128 extend this function to fully support building up a frame cache that
1129 can unwind register values when there is no DWARF information. */
1132 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1133 CORE_ADDR start_pc
, CORE_ADDR limit_pc
)
1135 CORE_ADDR cur_pc
, next_pc
;
1136 long frame_offset
= 0;
1137 CORE_ADDR end_prologue_addr
= 0;
1139 if (limit_pc
> start_pc
+ 200)
1140 limit_pc
= start_pc
+ 200;
1142 for (next_pc
= cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
= next_pc
)
1144 struct riscv_insn insn
;
1146 /* Decode the current instruction, and decide where the next
1147 instruction lives based on the size of this instruction. */
1148 insn
.decode (gdbarch
, cur_pc
);
1149 gdb_assert (insn
.length () > 0);
1150 next_pc
= cur_pc
+ insn
.length ();
1152 /* Look for common stack adjustment insns. */
1153 if ((insn
.opcode () == riscv_insn::ADDI
1154 || insn
.opcode () == riscv_insn::ADDIW
)
1155 && insn
.rd () == RISCV_SP_REGNUM
1156 && insn
.rs1 () == RISCV_SP_REGNUM
)
1158 /* Handle: addi sp, sp, -i
1159 or: addiw sp, sp, -i */
1160 if (insn
.imm_signed () < 0)
1161 frame_offset
+= insn
.imm_signed ();
1165 else if ((insn
.opcode () == riscv_insn::SW
1166 || insn
.opcode () == riscv_insn::SD
)
1167 && (insn
.rs1 () == RISCV_SP_REGNUM
1168 || insn
.rs1 () == RISCV_FP_REGNUM
))
1170 /* Handle: sw reg, offset(sp)
1171 or: sd reg, offset(sp)
1172 or: sw reg, offset(s0)
1173 or: sd reg, offset(s0) */
1174 /* Instruction storing a register onto the stack. */
1176 else if (insn
.opcode () == riscv_insn::ADDI
1177 && insn
.rd () == RISCV_FP_REGNUM
1178 && insn
.rs1 () == RISCV_SP_REGNUM
)
1180 /* Handle: addi s0, sp, size */
1181 /* Instructions setting up the frame pointer. */
1183 else if ((insn
.opcode () == riscv_insn::ADD
1184 || insn
.opcode () == riscv_insn::ADDW
)
1185 && insn
.rd () == RISCV_FP_REGNUM
1186 && insn
.rs1 () == RISCV_SP_REGNUM
1187 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1189 /* Handle: add s0, sp, 0
1190 or: addw s0, sp, 0 */
1191 /* Instructions setting up the frame pointer. */
1193 else if ((insn
.rd () == RISCV_GP_REGNUM
1194 && (insn
.opcode () == riscv_insn::AUIPC
1195 || insn
.opcode () == riscv_insn::LUI
1196 || (insn
.opcode () == riscv_insn::ADDI
1197 && insn
.rs1 () == RISCV_GP_REGNUM
)
1198 || (insn
.opcode () == riscv_insn::ADD
1199 && (insn
.rs1 () == RISCV_GP_REGNUM
1200 || insn
.rs2 () == RISCV_GP_REGNUM
))))
1201 || (insn
.opcode () == riscv_insn::ADDI
1202 && insn
.rd () == RISCV_ZERO_REGNUM
1203 && insn
.rs1 () == RISCV_ZERO_REGNUM
1204 && insn
.imm_signed () == 0))
1206 /* Handle: auipc gp, n
1211 or: add x0, x0, 0 (NOP) */
1212 /* These instructions are part of the prologue, but we don't need
1213 to do anything special to handle them. */
1217 if (end_prologue_addr
== 0)
1218 end_prologue_addr
= cur_pc
;
1222 if (end_prologue_addr
== 0)
1223 end_prologue_addr
= cur_pc
;
1225 return end_prologue_addr
;
1228 /* Implement the riscv_skip_prologue gdbarch method. */
1231 riscv_skip_prologue (struct gdbarch
*gdbarch
,
1235 CORE_ADDR func_addr
;
1237 /* See if we can determine the end of the prologue via the symbol
1238 table. If so, then return either PC, or the PC after the
1239 prologue, whichever is greater. */
1240 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1242 CORE_ADDR post_prologue_pc
1243 = skip_prologue_using_sal (gdbarch
, func_addr
);
1245 if (post_prologue_pc
!= 0)
1246 return std::max (pc
, post_prologue_pc
);
1249 /* Can't determine prologue from the symbol table, need to examine
1252 /* Find an upper limit on the function prologue using the debug
1253 information. If the debug information could not be used to provide
1254 that bound, then use an arbitrary large number as the upper bound. */
1255 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1257 limit_pc
= pc
+ 100; /* MAGIC! */
1259 return riscv_scan_prologue (gdbarch
, pc
, limit_pc
);
1262 /* Implement the gdbarch push dummy code callback. */
1265 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1266 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1267 struct type
*value_type
, CORE_ADDR
*real_pc
,
1268 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1270 /* Allocate space for a breakpoint, and keep the stack correctly
1278 /* Compute the alignment of the type T. Used while setting up the
1279 arguments for a dummy call. */
1282 riscv_type_alignment (struct type
*t
)
1284 t
= check_typedef (t
);
1285 switch (TYPE_CODE (t
))
1288 error (_("Could not compute alignment of type"));
1290 case TYPE_CODE_RVALUE_REF
:
1292 case TYPE_CODE_ENUM
:
1296 case TYPE_CODE_CHAR
:
1297 case TYPE_CODE_BOOL
:
1298 return TYPE_LENGTH (t
);
1300 case TYPE_CODE_ARRAY
:
1301 case TYPE_CODE_COMPLEX
:
1302 return riscv_type_alignment (TYPE_TARGET_TYPE (t
));
1304 case TYPE_CODE_STRUCT
:
1305 case TYPE_CODE_UNION
:
1310 for (i
= 0; i
< TYPE_NFIELDS (t
); ++i
)
1312 if (TYPE_FIELD_LOC_KIND (t
, i
) == FIELD_LOC_KIND_BITPOS
)
1314 int a
= riscv_type_alignment (TYPE_FIELD_TYPE (t
, i
));
1324 /* Holds information about a single argument either being passed to an
1325 inferior function, or returned from an inferior function. This includes
1326 information about the size, type, etc of the argument, and also
1327 information about how the argument will be passed (or returned). */
1329 struct riscv_arg_info
1331 /* Contents of the argument. */
1332 const gdb_byte
*contents
;
1334 /* Length of argument. */
1337 /* Alignment required for an argument of this type. */
1340 /* The type for this argument. */
1343 /* Each argument can have either 1 or 2 locations assigned to it. Each
1344 location describes where part of the argument will be placed. The
1345 second location is valid based on the LOC_TYPE and C_LENGTH fields
1346 of the first location (which is always valid). */
1349 /* What type of location this is. */
1352 /* Argument passed in a register. */
1355 /* Argument passed as an on stack argument. */
1358 /* Argument passed by reference. The second location is always
1359 valid for a BY_REF argument, and describes where the address
1360 of the BY_REF argument should be placed. */
1364 /* Information that depends on the location type. */
1367 /* Which register number to use. */
1370 /* The offset into the stack region. */
1374 /* The length of contents covered by this location. If this is less
1375 than the total length of the argument, then the second location
1376 will be valid, and will describe where the rest of the argument
1380 /* The offset within CONTENTS for this part of the argument. Will
1381 always be 0 for the first part. For the second part of the
1382 argument, this might be the C_LENGTH value of the first part,
1383 however, if we are passing a structure in two registers, and there's
1384 is padding between the first and second field, then this offset
1385 might be greater than the length of the first argument part. When
1386 the second argument location is not holding part of the argument
1387 value, but is instead holding the address of a reference argument,
1388 then this offset will be set to 0. */
1393 /* Information about a set of registers being used for passing arguments as
1394 part of a function call. The register set must be numerically
1395 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1396 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1398 struct riscv_arg_reg
1400 riscv_arg_reg (int first
, int last
)
1401 : next_regnum (first
),
1407 /* The GDB register number to use in this set. */
1410 /* The last GDB register number to use in this set. */
1414 /* Arguments can be passed as on stack arguments, or by reference. The
1415 on stack arguments must be in a continuous region starting from $sp,
1416 while the by reference arguments can be anywhere, but we'll put them
1417 on the stack after (at higher address) the on stack arguments.
1419 This might not be the right approach to take. The ABI is clear that
1420 an argument passed by reference can be modified by the callee, which
1421 us placing the argument (temporarily) onto the stack will not achieve
1422 (changes will be lost). There's also the possibility that very large
1423 arguments could overflow the stack.
1425 This struct is used to track offset into these two areas for where
1426 arguments are to be placed. */
1427 struct riscv_memory_offsets
1429 riscv_memory_offsets ()
1436 /* Offset into on stack argument area. */
1439 /* Offset into the pass by reference area. */
1443 /* Holds information about where arguments to a call will be placed. This
1444 is updated as arguments are added onto the call, and can be used to
1445 figure out where the next argument should be placed. */
1447 struct riscv_call_info
1449 riscv_call_info (struct gdbarch
*gdbarch
)
1450 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1451 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1453 xlen
= riscv_isa_xlen (gdbarch
);
1454 flen
= riscv_isa_flen (gdbarch
);
1456 /* Disable use of floating point registers if needed. */
1457 if (!riscv_has_fp_abi (gdbarch
))
1458 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1461 /* Track the memory areas used for holding in-memory arguments to a
1463 struct riscv_memory_offsets memory
;
1465 /* Holds information about the next integer register to use for passing
1467 struct riscv_arg_reg int_regs
;
1469 /* Holds information about the next floating point register to use for
1470 passing an argument. */
1471 struct riscv_arg_reg float_regs
;
1473 /* The XLEN and FLEN are copied in to this structure for convenience, and
1474 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1479 /* Return the number of registers available for use as parameters in the
1480 register set REG. Returned value can be 0 or more. */
1483 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1485 if (reg
->next_regnum
> reg
->last_regnum
)
1488 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1491 /* If there is at least one register available in the register set REG then
1492 the next register from REG is assigned to LOC and the length field of
1493 LOC is updated to LENGTH. The register set REG is updated to indicate
1494 that the assigned register is no longer available and the function
1497 If there are no registers available in REG then the function returns
1498 false, and LOC and REG are unchanged. */
1501 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1502 struct riscv_arg_reg
*reg
,
1503 int length
, int offset
)
1505 if (reg
->next_regnum
<= reg
->last_regnum
)
1507 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1508 loc
->loc_data
.regno
= reg
->next_regnum
;
1510 loc
->c_length
= length
;
1511 loc
->c_offset
= offset
;
1518 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1519 record that an area of stack has been used to hold the parameter
1522 The length field of LOC is updated to LENGTH, the length of the
1523 parameter being stored, and ALIGN is the alignment required by the
1524 parameter, which will affect how memory is allocated out of MEMORY. */
1527 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1528 struct riscv_memory_offsets
*memory
,
1529 int length
, int align
)
1531 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1533 = align_up (memory
->arg_offset
, align
);
1534 loc
->loc_data
.offset
= memory
->arg_offset
;
1535 memory
->arg_offset
+= length
;
1536 loc
->c_length
= length
;
1538 /* Offset is always 0, either we're the first location part, in which
1539 case we're reading content from the start of the argument, or we're
1540 passing the address of a reference argument, so 0. */
1544 /* Update AINFO, which describes an argument that should be passed or
1545 returned using the integer ABI. The argloc fields within AINFO are
1546 updated to describe the location in which the argument will be passed to
1547 a function, or returned from a function.
1549 The CINFO structure contains the ongoing call information, the holds
1550 information such as which argument registers are remaining to be
1551 assigned to parameter, and how much memory has been used by parameters
1554 By examining the state of CINFO a suitable location can be selected,
1555 and assigned to AINFO. */
1558 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1559 struct riscv_call_info
*cinfo
)
1561 if (ainfo
->length
> (2 * cinfo
->xlen
))
1563 /* Argument is going to be passed by reference. */
1564 ainfo
->argloc
[0].loc_type
1565 = riscv_arg_info::location::by_ref
;
1566 cinfo
->memory
.ref_offset
1567 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1568 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1569 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1570 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1572 /* The second location for this argument is given over to holding the
1573 address of the by-reference data. Pass 0 for the offset as this
1574 is not part of the actual argument value. */
1575 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1578 riscv_assign_stack_location (&ainfo
->argloc
[1],
1579 &cinfo
->memory
, cinfo
->xlen
,
1584 int len
= (ainfo
->length
> cinfo
->xlen
) ? cinfo
->xlen
: ainfo
->length
;
1586 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1587 &cinfo
->int_regs
, len
, 0))
1588 riscv_assign_stack_location (&ainfo
->argloc
[0],
1589 &cinfo
->memory
, len
, ainfo
->align
);
1591 if (len
< ainfo
->length
)
1593 len
= ainfo
->length
- len
;
1594 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1595 &cinfo
->int_regs
, len
,
1597 riscv_assign_stack_location (&ainfo
->argloc
[1],
1598 &cinfo
->memory
, len
, cinfo
->xlen
);
1603 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1604 is being passed with the floating point ABI. */
1607 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1608 struct riscv_call_info
*cinfo
)
1610 if (ainfo
->length
> cinfo
->flen
)
1611 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1614 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1617 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1621 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1622 is a complex floating point argument, and is therefore handled
1623 differently to other argument types. */
1626 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1627 struct riscv_call_info
*cinfo
)
1629 if (ainfo
->length
<= (2 * cinfo
->flen
)
1630 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1633 int len
= ainfo
->length
/ 2;
1635 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1636 &cinfo
->float_regs
, len
, len
);
1637 gdb_assert (result
);
1639 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1640 &cinfo
->float_regs
, len
, len
);
1641 gdb_assert (result
);
1644 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1647 /* A structure used for holding information about a structure type within
1648 the inferior program. The RiscV ABI has special rules for handling some
1649 structures with a single field or with two fields. The counting of
1650 fields here is done after flattening out all nested structures. */
1652 class riscv_struct_info
1655 riscv_struct_info ()
1656 : m_number_of_fields (0),
1657 m_types
{ nullptr, nullptr }
1662 /* Analyse TYPE descending into nested structures, count the number of
1663 scalar fields and record the types of the first two fields found. */
1664 void analyse (struct type
*type
);
1666 /* The number of scalar fields found in the analysed type. This is
1667 currently only accurate if the value returned is 0, 1, or 2 as the
1668 analysis stops counting when the number of fields is 3. This is
1669 because the RiscV ABI only has special cases for 1 or 2 fields,
1670 anything else we just don't care about. */
1671 int number_of_fields () const
1672 { return m_number_of_fields
; }
1674 /* Return the type for scalar field INDEX within the analysed type. Will
1675 return nullptr if there is no field at that index. Only INDEX values
1676 0 and 1 can be requested as the RiscV ABI only has special cases for
1677 structures with 1 or 2 fields. */
1678 struct type
*field_type (int index
) const
1680 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
1681 return m_types
[index
];
1685 /* The number of scalar fields found within the structure after recursing
1686 into nested structures. */
1687 int m_number_of_fields
;
1689 /* The types of the first two scalar fields found within the structure
1690 after recursing into nested structures. */
1691 struct type
*m_types
[2];
1694 /* Analyse TYPE descending into nested structures, count the number of
1695 scalar fields and record the types of the first two fields found. */
1698 riscv_struct_info::analyse (struct type
*type
)
1700 unsigned int count
= TYPE_NFIELDS (type
);
1703 for (i
= 0; i
< count
; ++i
)
1705 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
1708 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
1709 field_type
= check_typedef (field_type
);
1711 switch (TYPE_CODE (field_type
))
1713 case TYPE_CODE_STRUCT
:
1714 analyse (field_type
);
1718 /* RiscV only flattens out structures. Anything else does not
1719 need to be flattened, we just record the type, and when we
1720 look at the analysis results we'll realise this is not a
1721 structure we can special case, and pass the structure in
1723 if (m_number_of_fields
< 2)
1724 m_types
[m_number_of_fields
] = field_type
;
1725 m_number_of_fields
++;
1729 /* RiscV only has special handling for structures with 1 or 2 scalar
1730 fields, any more than that and the structure is just passed in
1731 memory. We can safely drop out early when we find 3 or more
1734 if (m_number_of_fields
> 2)
1739 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1740 is a structure. Small structures on RiscV have some special case
1741 handling in order that the structure might be passed in register.
1742 Larger structures are passed in memory. After assigning location
1743 information to AINFO, CINFO will have been updated. */
1746 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
1747 struct riscv_call_info
*cinfo
)
1749 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
1751 struct riscv_struct_info sinfo
;
1753 sinfo
.analyse (ainfo
->type
);
1754 if (sinfo
.number_of_fields () == 1
1755 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
1757 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1758 == TYPE_LENGTH (sinfo
.field_type (0)));
1759 return riscv_call_arg_complex_float (ainfo
, cinfo
);
1762 if (sinfo
.number_of_fields () == 1
1763 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
1765 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1766 == TYPE_LENGTH (sinfo
.field_type (0)));
1767 return riscv_call_arg_scalar_float (ainfo
, cinfo
);
1770 if (sinfo
.number_of_fields () == 2
1771 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1772 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1773 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1774 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
1775 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1777 int len0
, len1
, offset
;
1779 gdb_assert (TYPE_LENGTH (ainfo
->type
) <= (2 * cinfo
->flen
));
1781 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1782 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1783 &cinfo
->float_regs
, len0
, 0))
1784 error (_("failed during argument setup"));
1786 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1787 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1788 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
1789 - TYPE_LENGTH (sinfo
.field_type (0))));
1791 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1794 error (_("failed during argument setup"));
1798 if (sinfo
.number_of_fields () == 2
1799 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1800 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1801 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1802 && is_integral_type (sinfo
.field_type (1))
1803 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
1805 int len0
, len1
, offset
;
1807 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1808 <= (cinfo
->flen
+ cinfo
->xlen
));
1810 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1811 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1812 &cinfo
->float_regs
, len0
, 0))
1813 error (_("failed during argument setup"));
1815 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1816 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1817 gdb_assert (len1
<= cinfo
->xlen
);
1818 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1819 &cinfo
->int_regs
, len1
, offset
))
1820 error (_("failed during argument setup"));
1824 if (sinfo
.number_of_fields () == 2
1825 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1826 && (is_integral_type (sinfo
.field_type (0))
1827 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
1828 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1829 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
1831 int len0
, len1
, offset
;
1833 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1834 <= (cinfo
->flen
+ cinfo
->xlen
));
1836 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1837 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1838 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1840 gdb_assert (len0
<= cinfo
->xlen
);
1841 gdb_assert (len1
<= cinfo
->flen
);
1843 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1844 &cinfo
->int_regs
, len0
, 0))
1845 error (_("failed during argument setup"));
1847 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1850 error (_("failed during argument setup"));
1856 /* Non of the structure flattening cases apply, so we just pass using
1858 ainfo
->length
= align_up (ainfo
->length
, cinfo
->xlen
);
1859 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1862 /* Assign a location to call (or return) argument AINFO, the location is
1863 selected from CINFO which holds information about what call argument
1864 locations are available for use next. The TYPE is the type of the
1865 argument being passed, this information is recorded into AINFO (along
1866 with some additional information derived from the type).
1868 After assigning a location to AINFO, CINFO will have been updated. */
1871 riscv_arg_location (struct gdbarch
*gdbarch
,
1872 struct riscv_arg_info
*ainfo
,
1873 struct riscv_call_info
*cinfo
,
1877 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
1878 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1879 ainfo
->contents
= nullptr;
1881 switch (TYPE_CODE (ainfo
->type
))
1884 case TYPE_CODE_BOOL
:
1885 case TYPE_CODE_CHAR
:
1886 case TYPE_CODE_RANGE
:
1887 case TYPE_CODE_ENUM
:
1889 if (ainfo
->length
<= cinfo
->xlen
)
1891 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
1892 ainfo
->length
= cinfo
->xlen
;
1894 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
1896 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
1897 ainfo
->length
= 2 * cinfo
->xlen
;
1900 /* Recalculate the alignment requirement. */
1901 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1902 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1906 riscv_call_arg_scalar_float (ainfo
, cinfo
);
1909 case TYPE_CODE_COMPLEX
:
1910 riscv_call_arg_complex_float (ainfo
, cinfo
);
1913 case TYPE_CODE_STRUCT
:
1914 riscv_call_arg_struct (ainfo
, cinfo
);
1918 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1923 /* Used for printing debug information about the call argument location in
1924 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
1925 addresses for the location of pass-by-reference and
1926 arguments-on-the-stack memory areas. */
1929 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
1930 struct riscv_arg_info
*info
,
1931 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
1933 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
1934 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
1935 switch (info
->argloc
[0].loc_type
)
1937 case riscv_arg_info::location::in_reg
:
1939 (stream
, ", register %s",
1940 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
1941 if (info
->argloc
[0].c_length
< info
->length
)
1943 switch (info
->argloc
[1].loc_type
)
1945 case riscv_arg_info::location::in_reg
:
1947 (stream
, ", register %s",
1948 gdbarch_register_name (gdbarch
,
1949 info
->argloc
[1].loc_data
.regno
));
1952 case riscv_arg_info::location::on_stack
:
1953 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1954 info
->argloc
[1].loc_data
.offset
);
1957 case riscv_arg_info::location::by_ref
:
1959 /* The second location should never be a reference, any
1960 argument being passed by reference just places its address
1961 in the first location and is done. */
1962 error (_("invalid argument location"));
1966 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
1967 fprintf_unfiltered (stream
, " (offset 0x%x)",
1968 info
->argloc
[1].c_offset
);
1972 case riscv_arg_info::location::on_stack
:
1973 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1974 info
->argloc
[0].loc_data
.offset
);
1977 case riscv_arg_info::location::by_ref
:
1979 (stream
, ", by reference, data at offset 0x%x (%s)",
1980 info
->argloc
[0].loc_data
.offset
,
1981 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
1982 if (info
->argloc
[1].loc_type
1983 == riscv_arg_info::location::in_reg
)
1985 (stream
, ", address in register %s",
1986 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
1989 gdb_assert (info
->argloc
[1].loc_type
1990 == riscv_arg_info::location::on_stack
);
1992 (stream
, ", address on stack at offset 0x%x (%s)",
1993 info
->argloc
[1].loc_data
.offset
,
1994 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
1999 gdb_assert_not_reached (_("unknown argument location type"));
2003 /* Implement the push dummy call gdbarch callback. */
2006 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2007 struct value
*function
,
2008 struct regcache
*regcache
,
2011 struct value
**args
,
2014 CORE_ADDR struct_addr
)
2017 CORE_ADDR sp_args
, sp_refs
;
2018 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2020 struct riscv_arg_info
*arg_info
=
2021 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2022 struct riscv_arg_info
*info
;
2024 struct riscv_call_info
call_info (gdbarch
);
2028 /* We'll use register $a0 if we're returning a struct. */
2030 ++call_info
.int_regs
.next_regnum
;
2032 for (i
= 0, info
= &arg_info
[0];
2036 struct value
*arg_value
;
2037 struct type
*arg_type
;
2039 arg_value
= args
[i
];
2040 arg_type
= check_typedef (value_type (arg_value
));
2042 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
);
2044 if (info
->type
!= arg_type
)
2045 arg_value
= value_cast (info
->type
, arg_value
);
2046 info
->contents
= value_contents (arg_value
);
2049 /* Adjust the stack pointer and align it. */
2050 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2051 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2053 if (riscv_debug_infcall
> 0)
2055 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2056 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2057 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2058 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2059 call_info
.xlen
, call_info
.flen
);
2061 fprintf_unfiltered (gdb_stdlog
,
2062 "[*] struct return pointer in register $A0\n");
2063 for (i
= 0; i
< nargs
; ++i
)
2065 struct riscv_arg_info
*info
= &arg_info
[i
];
2067 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2068 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2069 fprintf_unfiltered (gdb_stdlog
, "\n");
2071 if (call_info
.memory
.arg_offset
> 0
2072 || call_info
.memory
.ref_offset
> 0)
2074 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2075 core_addr_to_string (osp
));
2076 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2077 call_info
.memory
.arg_offset
);
2078 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2079 call_info
.memory
.ref_offset
);
2080 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2081 core_addr_to_string_nz (osp
- sp
));
2085 /* Now load the argument into registers, or onto the stack. */
2089 gdb_byte buf
[sizeof (LONGEST
)];
2091 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2092 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
2095 for (i
= 0; i
< nargs
; ++i
)
2098 int second_arg_length
= 0;
2099 const gdb_byte
*second_arg_data
;
2100 struct riscv_arg_info
*info
= &arg_info
[i
];
2102 gdb_assert (info
->length
> 0);
2104 switch (info
->argloc
[0].loc_type
)
2106 case riscv_arg_info::location::in_reg
:
2108 gdb_byte tmp
[sizeof (ULONGEST
)];
2110 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2111 memset (tmp
, 0, sizeof (tmp
));
2112 memcpy (tmp
, info
->contents
, info
->argloc
[0].c_length
);
2113 regcache
->cooked_write (info
->argloc
[0].loc_data
.regno
, tmp
);
2115 ((info
->argloc
[0].c_length
< info
->length
)
2116 ? info
->argloc
[1].c_length
: 0);
2117 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2121 case riscv_arg_info::location::on_stack
:
2122 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2123 write_memory (dst
, info
->contents
, info
->length
);
2124 second_arg_length
= 0;
2127 case riscv_arg_info::location::by_ref
:
2128 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2129 write_memory (dst
, info
->contents
, info
->length
);
2131 second_arg_length
= call_info
.xlen
;
2132 second_arg_data
= (gdb_byte
*) &dst
;
2136 gdb_assert_not_reached (_("unknown argument location type"));
2139 if (second_arg_length
> 0)
2141 switch (info
->argloc
[1].loc_type
)
2143 case riscv_arg_info::location::in_reg
:
2145 gdb_byte tmp
[sizeof (ULONGEST
)];
2147 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2148 && second_arg_length
<= call_info
.flen
)
2149 || second_arg_length
<= call_info
.xlen
);
2150 memset (tmp
, 0, sizeof (tmp
));
2151 memcpy (tmp
, second_arg_data
, second_arg_length
);
2152 regcache
->cooked_write (info
->argloc
[1].loc_data
.regno
, tmp
);
2156 case riscv_arg_info::location::on_stack
:
2160 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2161 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2165 case riscv_arg_info::location::by_ref
:
2167 /* The second location should never be a reference, any
2168 argument being passed by reference just places its address
2169 in the first location and is done. */
2170 error (_("invalid argument location"));
2176 /* Set the dummy return value to bp_addr.
2177 A dummy breakpoint will be setup to execute the call. */
2179 if (riscv_debug_infcall
> 0)
2180 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2181 core_addr_to_string (bp_addr
));
2182 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2184 /* Finally, update the stack pointer. */
2186 if (riscv_debug_infcall
> 0)
2187 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2188 core_addr_to_string (sp
));
2189 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2194 /* Implement the return_value gdbarch method. */
2196 static enum return_value_convention
2197 riscv_return_value (struct gdbarch
*gdbarch
,
2198 struct value
*function
,
2200 struct regcache
*regcache
,
2202 const gdb_byte
*writebuf
)
2204 struct riscv_call_info
call_info (gdbarch
);
2205 struct riscv_arg_info info
;
2206 struct type
*arg_type
;
2208 arg_type
= check_typedef (type
);
2209 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
);
2211 if (riscv_debug_infcall
> 0)
2213 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2214 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2215 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2216 fprintf_unfiltered (gdb_stdlog
, "\n");
2219 if (readbuf
!= nullptr || writebuf
!= nullptr)
2223 switch (info
.argloc
[0].loc_type
)
2225 /* Return value in register(s). */
2226 case riscv_arg_info::location::in_reg
:
2228 regnum
= info
.argloc
[0].loc_data
.regno
;
2231 regcache
->cooked_read (regnum
, readbuf
);
2234 regcache
->cooked_write (regnum
, writebuf
);
2236 /* A return value in register can have a second part in a
2238 if (info
.argloc
[0].c_length
< info
.length
)
2240 switch (info
.argloc
[1].loc_type
)
2242 case riscv_arg_info::location::in_reg
:
2243 regnum
= info
.argloc
[1].loc_data
.regno
;
2247 readbuf
+= info
.argloc
[1].c_offset
;
2248 regcache
->cooked_read (regnum
, readbuf
);
2253 writebuf
+= info
.argloc
[1].c_offset
;
2254 regcache
->cooked_write (regnum
, writebuf
);
2258 case riscv_arg_info::location::by_ref
:
2259 case riscv_arg_info::location::on_stack
:
2261 error (_("invalid argument location"));
2268 /* Return value by reference will have its address in A0. */
2269 case riscv_arg_info::location::by_ref
:
2273 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2275 if (readbuf
!= nullptr)
2276 read_memory (addr
, readbuf
, info
.length
);
2277 if (writebuf
!= nullptr)
2278 write_memory (addr
, writebuf
, info
.length
);
2282 case riscv_arg_info::location::on_stack
:
2284 error (_("invalid argument location"));
2289 switch (info
.argloc
[0].loc_type
)
2291 case riscv_arg_info::location::in_reg
:
2292 return RETURN_VALUE_REGISTER_CONVENTION
;
2293 case riscv_arg_info::location::by_ref
:
2294 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2295 case riscv_arg_info::location::on_stack
:
2297 error (_("invalid argument location"));
2301 /* Implement the frame_align gdbarch method. */
2304 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2306 return align_down (addr
, 16);
2309 /* Implement the unwind_pc gdbarch method. */
2312 riscv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2314 return frame_unwind_register_unsigned (next_frame
, RISCV_PC_REGNUM
);
2317 /* Implement the unwind_sp gdbarch method. */
2320 riscv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2322 return frame_unwind_register_unsigned (next_frame
, RISCV_SP_REGNUM
);
2325 /* Implement the dummy_id gdbarch method. */
2327 static struct frame_id
2328 riscv_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2330 return frame_id_build (get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
),
2331 get_frame_pc (this_frame
));
2334 /* Generate, or return the cached frame cache for the RiscV frame
2337 static struct trad_frame_cache
*
2338 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2341 CORE_ADDR start_addr
;
2342 CORE_ADDR stack_addr
;
2343 struct trad_frame_cache
*this_trad_cache
;
2344 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2346 if ((*this_cache
) != NULL
)
2347 return (struct trad_frame_cache
*) *this_cache
;
2348 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2349 (*this_cache
) = this_trad_cache
;
2351 trad_frame_set_reg_realreg (this_trad_cache
, gdbarch_pc_regnum (gdbarch
),
2354 pc
= get_frame_pc (this_frame
);
2355 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2356 stack_addr
= get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
);
2357 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2359 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2361 return this_trad_cache
;
2364 /* Implement the this_id callback for RiscV frame unwinder. */
2367 riscv_frame_this_id (struct frame_info
*this_frame
,
2368 void **prologue_cache
,
2369 struct frame_id
*this_id
)
2371 struct trad_frame_cache
*info
;
2373 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2374 trad_frame_get_id (info
, this_id
);
2377 /* Implement the prev_register callback for RiscV frame unwinder. */
2379 static struct value
*
2380 riscv_frame_prev_register (struct frame_info
*this_frame
,
2381 void **prologue_cache
,
2384 struct trad_frame_cache
*info
;
2386 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2387 return trad_frame_get_register (info
, this_frame
, regnum
);
2390 /* Structure defining the RiscV normal frame unwind functions. Since we
2391 are the fallback unwinder (DWARF unwinder is used first), we use the
2392 default frame sniffer, which always accepts the frame. */
2394 static const struct frame_unwind riscv_frame_unwind
=
2396 /*.type =*/ NORMAL_FRAME
,
2397 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2398 /*.this_id =*/ riscv_frame_this_id
,
2399 /*.prev_register =*/ riscv_frame_prev_register
,
2400 /*.unwind_data =*/ NULL
,
2401 /*.sniffer =*/ default_frame_sniffer
,
2402 /*.dealloc_cache =*/ NULL
,
2403 /*.prev_arch =*/ NULL
,
2406 /* Initialize the current architecture based on INFO. If possible,
2407 re-use an architecture from ARCHES, which is a list of
2408 architectures already created during this debugging session.
2410 Called e.g. at program startup, when reading a core file, and when
2411 reading a binary file. */
2413 static struct gdbarch
*
2414 riscv_gdbarch_init (struct gdbarch_info info
,
2415 struct gdbarch_list
*arches
)
2417 struct gdbarch
*gdbarch
;
2418 struct gdbarch_tdep
*tdep
;
2419 struct gdbarch_tdep tmp_tdep
;
2422 /* Ideally, we'd like to get as much information from the target for
2423 things like register size, and whether the target has floating point
2424 hardware. However, there are some things that the target can't tell
2425 us, like, what ABI is being used.
2427 So, for now, we take as much information as possible from the ELF,
2428 including things like register size, and FP hardware support, along
2429 with information about the ABI.
2431 Information about this target is built up in TMP_TDEP, and then we
2432 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2433 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2434 memset (&tmp_tdep
, 0, sizeof (tmp_tdep
));
2436 if (info
.abfd
!= NULL
2437 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2439 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2440 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2442 if (eclass
== ELFCLASS32
)
2443 tmp_tdep
.abi
.fields
.base_len
= 1;
2444 else if (eclass
== ELFCLASS64
)
2445 tmp_tdep
.abi
.fields
.base_len
= 2;
2447 internal_error (__FILE__
, __LINE__
,
2448 _("unknown ELF header class %d"), eclass
);
2450 if (e_flags
& EF_RISCV_RVC
)
2451 tmp_tdep
.core_features
|= (1 << ('C' - 'A'));
2453 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2455 tmp_tdep
.abi
.fields
.float_abi
= 2;
2456 tmp_tdep
.core_features
|= (1 << ('D' - 'A'));
2457 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2459 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2461 tmp_tdep
.abi
.fields
.float_abi
= 1;
2462 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2467 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2469 if (binfo
->bits_per_word
== 32)
2470 tmp_tdep
.abi
.fields
.base_len
= 1;
2471 else if (binfo
->bits_per_word
== 64)
2472 tmp_tdep
.abi
.fields
.base_len
= 2;
2474 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2475 binfo
->bits_per_word
);
2478 /* Find a candidate among the list of pre-declared architectures. */
2479 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2481 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2482 if (gdbarch_tdep (arches
->gdbarch
)->abi
.value
== tmp_tdep
.abi
.value
)
2483 return arches
->gdbarch
;
2485 /* None found, so create a new architecture from the information provided. */
2486 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof *tdep
);
2487 gdbarch
= gdbarch_alloc (&info
, tdep
);
2488 memcpy (tdep
, &tmp_tdep
, sizeof (tmp_tdep
));
2490 /* Target data types. */
2491 set_gdbarch_short_bit (gdbarch
, 16);
2492 set_gdbarch_int_bit (gdbarch
, 32);
2493 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2494 set_gdbarch_long_long_bit (gdbarch
, 64);
2495 set_gdbarch_float_bit (gdbarch
, 32);
2496 set_gdbarch_double_bit (gdbarch
, 64);
2497 set_gdbarch_long_double_bit (gdbarch
, 128);
2498 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
2499 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2500 set_gdbarch_char_signed (gdbarch
, 0);
2502 /* Information about the target architecture. */
2503 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
2504 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
2505 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
2507 /* Register architecture. */
2508 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
2509 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
2510 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
2511 set_gdbarch_ps_regnum (gdbarch
, RISCV_FP_REGNUM
);
2512 set_gdbarch_deprecated_fp_regnum (gdbarch
, RISCV_FP_REGNUM
);
2514 /* Functions to supply register information. */
2515 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
2516 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
2517 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
2518 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
2520 /* Functions to analyze frames. */
2521 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
2522 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2523 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
2525 /* Functions to access frame data. */
2526 set_gdbarch_unwind_pc (gdbarch
, riscv_unwind_pc
);
2527 set_gdbarch_unwind_sp (gdbarch
, riscv_unwind_sp
);
2529 /* Functions handling dummy frames. */
2530 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2531 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
2532 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
2533 set_gdbarch_dummy_id (gdbarch
, riscv_dummy_id
);
2535 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2537 dwarf2_append_unwinders (gdbarch
);
2538 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
2540 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
2541 user_reg_add (gdbarch
, riscv_register_aliases
[i
].name
,
2542 value_of_riscv_user_reg
, &riscv_register_aliases
[i
].regnum
);
2544 /* Hook in OS ABI-specific overrides, if they have been registered. */
2545 gdbarch_init_osabi (info
, gdbarch
);
2551 /* Allocate new riscv_inferior_data object. */
2553 static struct riscv_inferior_data
*
2554 riscv_new_inferior_data (void)
2556 struct riscv_inferior_data
*inf_data
2557 = new (struct riscv_inferior_data
);
2558 inf_data
->misa_read
= false;
2562 /* Free inferior data. */
2565 riscv_inferior_data_cleanup (struct inferior
*inf
, void *data
)
2567 struct riscv_inferior_data
*inf_data
=
2568 static_cast <struct riscv_inferior_data
*> (data
);
2572 /* Return riscv_inferior_data for the given INFERIOR. If not yet created,
2575 struct riscv_inferior_data
*
2576 riscv_inferior_data (struct inferior
*const inf
)
2578 struct riscv_inferior_data
*inf_data
;
2580 gdb_assert (inf
!= NULL
);
2583 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2584 if (inf_data
== NULL
)
2586 inf_data
= riscv_new_inferior_data ();
2587 set_inferior_data (inf
, riscv_inferior_data_reg
, inf_data
);
2593 /* Free the inferior data when an inferior exits. */
2596 riscv_invalidate_inferior_data (struct inferior
*inf
)
2598 struct riscv_inferior_data
*inf_data
;
2600 gdb_assert (inf
!= NULL
);
2602 /* Don't call RISCV_INFERIOR_DATA as we don't want to create the data if
2603 we've not already created it by this point. */
2605 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2606 if (inf_data
!= NULL
)
2609 set_inferior_data (inf
, riscv_inferior_data_reg
, NULL
);
2614 _initialize_riscv_tdep (void)
2616 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
2618 /* Register per-inferior data. */
2619 riscv_inferior_data_reg
2620 = register_inferior_data_with_cleanup (NULL
, riscv_inferior_data_cleanup
);
2622 /* Observers used to invalidate the inferior data when needed. */
2623 gdb::observers::inferior_exit
.attach (riscv_invalidate_inferior_data
);
2624 gdb::observers::inferior_appeared
.attach (riscv_invalidate_inferior_data
);
2626 /* Add root prefix command for all "set debug riscv" and "show debug
2628 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
2629 _("RISC-V specific debug commands."),
2630 &setdebugriscvcmdlist
, "set debug riscv ", 0,
2633 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
2634 _("RISC-V specific debug commands."),
2635 &showdebugriscvcmdlist
, "show debug riscv ", 0,
2638 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
2639 &riscv_debug_infcall
, _("\
2640 Set riscv inferior call debugging."), _("\
2641 Show riscv inferior call debugging."), _("\
2642 When non-zero, print debugging information for the riscv specific parts\n\
2643 of the inferior call mechanism."),
2645 show_riscv_debug_variable
,
2646 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
2648 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2649 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
2650 _("RISC-V specific commands."),
2651 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
2653 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
2654 _("RISC-V specific commands."),
2655 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
2658 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
2659 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
2660 &use_compressed_breakpoints
,
2662 Set debugger's use of compressed breakpoints."), _(" \
2663 Show debugger's use of compressed breakpoints."), _("\
2664 Debugging compressed code requires compressed breakpoints to be used. If\n \
2665 left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2666 is supported. If that doesn't give the correct behavior, then this option\n\
2669 show_use_compressed_breakpoints
,