1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common/common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
60 /* The stack must be 16-byte aligned. */
61 #define SP_ALIGNMENT 16
63 /* The biggest alignment that the target supports. */
64 #define BIGGEST_ALIGNMENT 16
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Cached information about a frame. */
78 struct riscv_unwind_cache
80 /* The register from which we can calculate the frame base. This is
81 usually $sp or $fp. */
84 /* The offset from the current value in register FRAME_BASE_REG to the
85 actual frame base address. */
86 int frame_base_offset
;
88 /* Information about previous register values. */
89 struct trad_frame_saved_reg
*regs
;
91 /* The id for this frame. */
92 struct frame_id this_id
;
94 /* The base (stack) address for this frame. This is the stack pointer
95 value on entry to this frame before any adjustments are made. */
99 /* RISC-V specific register group for CSRs. */
101 static reggroup
*csr_reggroup
= NULL
;
103 /* A set of registers that we expect to find in a tdesc_feature. These
104 are use in RISCV_GDBARCH_INIT when processing the target description. */
106 struct riscv_register_feature
108 /* Information for a single register. */
111 /* The GDB register number for this register. */
114 /* List of names for this register. The first name in this list is the
115 preferred name, the name GDB should use when describing this
117 std::vector
<const char *> names
;
119 /* When true this register is required in this feature set. */
123 /* The name for this feature. This is the name used to find this feature
124 within the target description. */
127 /* List of all the registers that we expect that we might find in this
129 std::vector
<struct register_info
> registers
;
132 /* The general x-registers feature set. */
134 static const struct riscv_register_feature riscv_xreg_feature
=
136 "org.gnu.gdb.riscv.cpu",
138 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" }, true },
139 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" }, true },
140 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" }, true },
141 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" }, true },
142 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" }, true },
143 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" }, true },
144 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" }, true },
145 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" }, true },
146 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" }, true },
147 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" }, true },
148 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" }, true },
149 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" }, true },
150 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" }, true },
151 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" }, true },
152 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" }, true },
153 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" }, true },
154 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" }, true },
155 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" }, true },
156 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" }, true },
157 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" }, true },
158 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" }, true },
159 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" }, true },
160 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" }, true },
161 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" }, true },
162 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" }, true },
163 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" }, true },
164 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" }, true },
165 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" }, true },
166 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" }, true },
167 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" }, true },
168 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" }, true },
169 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" }, true },
170 { RISCV_ZERO_REGNUM
+ 32, { "pc" }, true }
174 /* The f-registers feature set. */
176 static const struct riscv_register_feature riscv_freg_feature
=
178 "org.gnu.gdb.riscv.fpu",
180 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" }, true },
181 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" }, true },
182 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" }, true },
183 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" }, true },
184 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" }, true },
185 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" }, true },
186 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" }, true },
187 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" }, true },
188 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8" }, true },
189 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" }, true },
190 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" }, true },
191 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" }, true },
192 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" }, true },
193 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" }, true },
194 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" }, true },
195 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" }, true },
196 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" }, true },
197 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" }, true },
198 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" }, true },
199 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" }, true },
200 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" }, true },
201 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" }, true },
202 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" }, true },
203 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" }, true },
204 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" }, true },
205 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" }, true },
206 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" }, true },
207 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" }, true },
208 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" }, true },
209 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" }, true },
210 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" }, true },
211 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" }, true },
213 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags" }, true },
214 { RISCV_CSR_FRM_REGNUM
, { "frm" }, true },
215 { RISCV_CSR_FCSR_REGNUM
, { "fcsr" }, true },
220 /* Set of virtual registers. These are not physical registers on the
221 hardware, but might be available from the target. These are not pseudo
222 registers, reading these really does result in a register read from the
223 target, it is just that there might not be a physical register backing
226 static const struct riscv_register_feature riscv_virtual_feature
=
228 "org.gnu.gdb.riscv.virtual",
230 { RISCV_PRIV_REGNUM
, { "priv" }, false }
234 /* Feature set for CSRs. This set is NOT constant as the register names
235 list for each register is not complete. The aliases are computed
236 during RISCV_CREATE_CSR_ALIASES. */
238 static struct riscv_register_feature riscv_csr_feature
=
240 "org.gnu.gdb.riscv.csr",
242 #define DECLARE_CSR(NAME,VALUE) \
243 { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
244 #include "opcode/riscv-opc.h"
249 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
250 to the name list for each register. */
253 riscv_create_csr_aliases ()
255 for (auto ®
: riscv_csr_feature
.registers
)
257 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
258 const char *alias
= xstrprintf ("csr%d", csr_num
);
259 reg
.names
.push_back (alias
);
263 /* Controls whether we place compressed breakpoints or not. When in auto
264 mode GDB tries to determine if the target supports compressed
265 breakpoints, and uses them if it does. */
267 static enum auto_boolean use_compressed_breakpoints
;
269 /* The show callback for 'show riscv use-compressed-breakpoints'. */
272 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
273 struct cmd_list_element
*c
,
276 fprintf_filtered (file
,
277 _("Debugger's use of compressed breakpoints is set "
281 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
283 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
284 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
286 /* The show callback for the 'show riscv' prefix command. */
289 show_riscv_command (const char *args
, int from_tty
)
291 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
294 /* The set callback for the 'set riscv' prefix command. */
297 set_riscv_command (const char *args
, int from_tty
)
300 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
301 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
304 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
306 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
307 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
309 /* The show callback for the 'show debug riscv' prefix command. */
312 show_debug_riscv_command (const char *args
, int from_tty
)
314 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
317 /* The set callback for the 'set debug riscv' prefix command. */
320 set_debug_riscv_command (const char *args
, int from_tty
)
323 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
324 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
327 /* The show callback for all 'show debug riscv VARNAME' variables. */
330 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
331 struct cmd_list_element
*c
,
334 fprintf_filtered (file
,
335 _("RiscV debug variable `%s' is set to: %s\n"),
339 /* When this is set to non-zero debugging information about breakpoint
340 kinds will be printed. */
342 static unsigned int riscv_debug_breakpoints
= 0;
344 /* When this is set to non-zero debugging information about inferior calls
347 static unsigned int riscv_debug_infcall
= 0;
349 /* When this is set to non-zero debugging information about stack unwinding
352 static unsigned int riscv_debug_unwinder
= 0;
354 /* When this is set to non-zero debugging information about gdbarch
355 initialisation will be printed. */
357 static unsigned int riscv_debug_gdbarch
= 0;
359 /* See riscv-tdep.h. */
362 riscv_isa_xlen (struct gdbarch
*gdbarch
)
364 return gdbarch_tdep (gdbarch
)->isa_features
.xlen
;
367 /* See riscv-tdep.h. */
370 riscv_abi_xlen (struct gdbarch
*gdbarch
)
372 return gdbarch_tdep (gdbarch
)->abi_features
.xlen
;
375 /* See riscv-tdep.h. */
378 riscv_isa_flen (struct gdbarch
*gdbarch
)
380 return gdbarch_tdep (gdbarch
)->isa_features
.flen
;
383 /* See riscv-tdep.h. */
386 riscv_abi_flen (struct gdbarch
*gdbarch
)
388 return gdbarch_tdep (gdbarch
)->abi_features
.flen
;
391 /* Return true if the target for GDBARCH has floating point hardware. */
394 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
396 return (riscv_isa_flen (gdbarch
) > 0);
399 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
402 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
404 return gdbarch_tdep (gdbarch
)->abi_features
.flen
> 0;
407 /* Return true if REGNO is a floating pointer register. */
410 riscv_is_fp_regno_p (int regno
)
412 return (regno
>= RISCV_FIRST_FP_REGNUM
413 && regno
<= RISCV_LAST_FP_REGNUM
);
416 /* Implement the breakpoint_kind_from_pc gdbarch method. */
419 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
421 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
423 bool unaligned_p
= false;
426 /* Some targets don't support unaligned reads. The address can only
427 be unaligned if the C extension is supported. So it is safe to
428 use a compressed breakpoint in this case. */
433 /* Read the opcode byte to determine the instruction length. If
434 the read fails this may be because we tried to set the
435 breakpoint at an invalid address, in this case we provide a
436 fake result which will give a breakpoint length of 4.
437 Hopefully when we try to actually insert the breakpoint we
438 will see a failure then too which will be reported to the
440 if (target_read_code (*pcptr
, buf
, 1) == -1)
442 read_code (*pcptr
, buf
, 1);
445 if (riscv_debug_breakpoints
)
447 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
448 ? "C.EBREAK" : "EBREAK");
450 fprintf_unfiltered (gdb_stdlog
, "Using %s for breakpoint at %s ",
451 bp
, paddress (gdbarch
, *pcptr
));
453 fprintf_unfiltered (gdb_stdlog
, "(unaligned address)\n");
455 fprintf_unfiltered (gdb_stdlog
, "(instruction length %d)\n",
456 riscv_insn_length (buf
[0]));
458 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
463 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
469 /* Implement the sw_breakpoint_from_kind gdbarch method. */
471 static const gdb_byte
*
472 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
474 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
475 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
485 gdb_assert_not_reached (_("unhandled breakpoint kind"));
489 /* Callback function for user_reg_add. */
491 static struct value
*
492 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
494 const int *reg_p
= (const int *) baton
;
495 return value_of_register (*reg_p
, frame
);
498 /* Implement the register_name gdbarch method. This is used instead of
499 the function supplied by calling TDESC_USE_REGISTERS so that we can
500 ensure the preferred names are offered. */
503 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
505 /* Lookup the name through the target description. If we get back NULL
506 then this is an unknown register. If we do get a name back then we
507 look up the registers preferred name below. */
508 const char *name
= tdesc_register_name (gdbarch
, regnum
);
509 if (name
== NULL
|| name
[0] == '\0')
512 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
514 gdb_assert (regnum
< riscv_xreg_feature
.registers
.size ());
515 return riscv_xreg_feature
.registers
[regnum
].names
[0];
518 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
520 if (riscv_has_fp_regs (gdbarch
))
522 regnum
-= RISCV_FIRST_FP_REGNUM
;
523 gdb_assert (regnum
< riscv_freg_feature
.registers
.size ());
524 return riscv_freg_feature
.registers
[regnum
].names
[0];
530 /* Check that there's no gap between the set of registers handled above,
531 and the set of registers handled next. */
532 gdb_assert ((RISCV_LAST_FP_REGNUM
+ 1) == RISCV_FIRST_CSR_REGNUM
);
534 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
536 #define DECLARE_CSR(NAME,VALUE) \
537 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
541 #include "opcode/riscv-opc.h"
546 if (regnum
== RISCV_PRIV_REGNUM
)
549 /* It is possible that that the target provides some registers that GDB
550 is unaware of, in that case just return the NAME from the target
555 /* Construct a type for 64-bit FP registers. */
558 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
560 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
562 if (tdep
->riscv_fpreg_d_type
== nullptr)
564 const struct builtin_type
*bt
= builtin_type (gdbarch
);
566 /* The type we're building is this: */
568 union __gdb_builtin_type_fpreg_d
577 t
= arch_composite_type (gdbarch
,
578 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
579 append_composite_type_field (t
, "float", bt
->builtin_float
);
580 append_composite_type_field (t
, "double", bt
->builtin_double
);
582 TYPE_NAME (t
) = "builtin_type_fpreg_d";
583 tdep
->riscv_fpreg_d_type
= t
;
586 return tdep
->riscv_fpreg_d_type
;
589 /* Implement the register_type gdbarch method. This is installed as an
590 for the override setup by TDESC_USE_REGISTERS, for most registers we
591 delegate the type choice to the target description, but for a few
592 registers we try to improve the types if the target description has
593 taken a simplistic approach. */
596 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
598 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
599 int xlen
= riscv_isa_xlen (gdbarch
);
601 /* We want to perform some specific type "fixes" in cases where we feel
602 that we really can do better than the target description. For all
603 other cases we just return what the target description says. */
604 if (riscv_is_fp_regno_p (regnum
))
606 /* This spots the case for RV64 where the double is defined as
607 either 'ieee_double' or 'float' (which is the generic name that
608 converts to 'double' on 64-bit). In these cases its better to
609 present the registers using a union type. */
610 int flen
= riscv_isa_flen (gdbarch
);
612 && TYPE_CODE (type
) == TYPE_CODE_FLT
613 && TYPE_LENGTH (type
) == flen
614 && (strcmp (TYPE_NAME (type
), "builtin_type_ieee_double") == 0
615 || strcmp (TYPE_NAME (type
), "double") == 0))
616 type
= riscv_fpreg_d_type (gdbarch
);
619 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
620 || regnum
== RISCV_RA_REGNUM
621 || regnum
== RISCV_FP_REGNUM
622 || regnum
== RISCV_SP_REGNUM
623 || regnum
== RISCV_GP_REGNUM
624 || regnum
== RISCV_TP_REGNUM
)
625 && TYPE_CODE (type
) == TYPE_CODE_INT
626 && TYPE_LENGTH (type
) == xlen
)
628 /* This spots the case where some interesting registers are defined
629 as simple integers of the expected size, we force these registers
630 to be pointers as we believe that is more useful. */
631 if (regnum
== gdbarch_pc_regnum (gdbarch
)
632 || regnum
== RISCV_RA_REGNUM
)
633 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
634 else if (regnum
== RISCV_FP_REGNUM
635 || regnum
== RISCV_SP_REGNUM
636 || regnum
== RISCV_GP_REGNUM
637 || regnum
== RISCV_TP_REGNUM
)
638 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
644 /* Helper for riscv_print_registers_info, prints info for a single register
648 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
649 struct ui_file
*file
,
650 struct frame_info
*frame
,
653 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
655 struct type
*regtype
;
656 int print_raw_format
;
657 enum tab_stops
{ value_column_1
= 15 };
659 fputs_filtered (name
, file
);
660 print_spaces_filtered (value_column_1
- strlen (name
), file
);
664 val
= value_of_register (regnum
, frame
);
665 regtype
= value_type (val
);
667 catch (const gdb_exception_error
&ex
)
669 /* Handle failure to read a register without interrupting the entire
670 'info registers' flow. */
671 fprintf_filtered (file
, "%s\n", ex
.what ());
675 print_raw_format
= (value_entirely_available (val
)
676 && !value_optimized_out (val
));
678 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
679 || (TYPE_CODE (regtype
) == TYPE_CODE_UNION
680 && TYPE_NFIELDS (regtype
) == 2
681 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 0)) == TYPE_CODE_FLT
682 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 1)) == TYPE_CODE_FLT
)
683 || (TYPE_CODE (regtype
) == TYPE_CODE_UNION
684 && TYPE_NFIELDS (regtype
) == 3
685 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 0)) == TYPE_CODE_FLT
686 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 1)) == TYPE_CODE_FLT
687 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 2)) == TYPE_CODE_FLT
))
689 struct value_print_options opts
;
690 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
691 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
693 get_user_print_options (&opts
);
697 value_embedded_offset (val
), 0,
698 file
, 0, val
, &opts
, current_language
);
700 if (print_raw_format
)
702 fprintf_filtered (file
, "\t(raw ");
703 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
705 fprintf_filtered (file
, ")");
710 struct value_print_options opts
;
712 /* Print the register in hex. */
713 get_formatted_print_options (&opts
, 'x');
716 value_embedded_offset (val
), 0,
717 file
, 0, val
, &opts
, current_language
);
719 if (print_raw_format
)
721 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
724 int size
= register_size (gdbarch
, regnum
);
727 /* The SD field is always in the upper bit of MSTATUS, regardless
728 of the number of bits in MSTATUS. */
729 d
= value_as_long (val
);
731 fprintf_filtered (file
,
732 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
733 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
734 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
735 (int) ((d
>> (xlen
- 1)) & 0x1),
736 (int) ((d
>> 24) & 0x1f),
737 (int) ((d
>> 19) & 0x1),
738 (int) ((d
>> 18) & 0x1),
739 (int) ((d
>> 17) & 0x1),
740 (int) ((d
>> 15) & 0x3),
741 (int) ((d
>> 13) & 0x3),
742 (int) ((d
>> 11) & 0x3),
743 (int) ((d
>> 9) & 0x3),
744 (int) ((d
>> 8) & 0x1),
745 (int) ((d
>> 7) & 0x1),
746 (int) ((d
>> 6) & 0x1),
747 (int) ((d
>> 5) & 0x1),
748 (int) ((d
>> 4) & 0x1),
749 (int) ((d
>> 3) & 0x1),
750 (int) ((d
>> 2) & 0x1),
751 (int) ((d
>> 1) & 0x1),
752 (int) ((d
>> 0) & 0x1));
754 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
759 int size
= register_size (gdbarch
, regnum
);
761 /* The MXL field is always in the upper two bits of MISA,
762 regardless of the number of bits in MISA. Mask out other
763 bits to ensure we have a positive value. */
764 d
= value_as_long (val
);
765 base
= (d
>> ((size
* 8) - 2)) & 0x3;
768 for (; base
> 0; base
--)
770 fprintf_filtered (file
, "\tRV%d", xlen
);
772 for (i
= 0; i
< 26; i
++)
775 fprintf_filtered (file
, "%c", 'A' + i
);
778 else if (regnum
== RISCV_CSR_FCSR_REGNUM
779 || regnum
== RISCV_CSR_FFLAGS_REGNUM
780 || regnum
== RISCV_CSR_FRM_REGNUM
)
784 d
= value_as_long (val
);
786 fprintf_filtered (file
, "\t");
787 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
788 fprintf_filtered (file
,
789 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
790 (int) ((d
>> 5) & 0x7),
791 (int) ((d
>> 4) & 0x1),
792 (int) ((d
>> 3) & 0x1),
793 (int) ((d
>> 2) & 0x1),
794 (int) ((d
>> 1) & 0x1),
795 (int) ((d
>> 0) & 0x1));
797 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
799 static const char * const sfrm
[] =
801 "RNE (round to nearest; ties to even)",
802 "RTZ (Round towards zero)",
803 "RDN (Round down towards -INF)",
804 "RUP (Round up towards +INF)",
805 "RMM (Round to nearest; ties to max magnitude)",
808 "dynamic rounding mode",
810 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
811 ? (d
>> 5) : d
) & 0x3;
813 fprintf_filtered (file
, "%sFRM:%i [%s]",
814 (regnum
== RISCV_CSR_FCSR_REGNUM
819 else if (regnum
== RISCV_PRIV_REGNUM
)
824 d
= value_as_long (val
);
829 static const char * const sprv
[] =
836 fprintf_filtered (file
, "\tprv:%d [%s]",
840 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
844 /* If not a vector register, print it also according to its
846 if (TYPE_VECTOR (regtype
) == 0)
848 get_user_print_options (&opts
);
850 fprintf_filtered (file
, "\t");
852 value_embedded_offset (val
), 0,
853 file
, 0, val
, &opts
, current_language
);
858 fprintf_filtered (file
, "\n");
861 /* Return true if REGNUM is a valid CSR register. The CSR register space
862 is sparsely populated, so not every number is a named CSR. */
865 riscv_is_regnum_a_named_csr (int regnum
)
867 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
868 && regnum
<= RISCV_LAST_CSR_REGNUM
);
872 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
873 #include "opcode/riscv-opc.h"
882 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
886 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
887 struct reggroup
*reggroup
)
889 /* Used by 'info registers' and 'info registers <groupname>'. */
891 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
892 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
895 if (regnum
> RISCV_LAST_REGNUM
)
897 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
901 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
904 if (reggroup
== all_reggroup
)
906 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
908 if (riscv_is_regnum_a_named_csr (regnum
))
912 else if (reggroup
== float_reggroup
)
913 return (riscv_is_fp_regno_p (regnum
)
914 || regnum
== RISCV_CSR_FCSR_REGNUM
915 || regnum
== RISCV_CSR_FFLAGS_REGNUM
916 || regnum
== RISCV_CSR_FRM_REGNUM
);
917 else if (reggroup
== general_reggroup
)
918 return regnum
< RISCV_FIRST_FP_REGNUM
;
919 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
921 if (riscv_has_fp_regs (gdbarch
))
922 return (regnum
<= RISCV_LAST_FP_REGNUM
923 || regnum
== RISCV_CSR_FCSR_REGNUM
924 || regnum
== RISCV_CSR_FFLAGS_REGNUM
925 || regnum
== RISCV_CSR_FRM_REGNUM
);
927 return regnum
< RISCV_FIRST_FP_REGNUM
;
929 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
931 if (regnum
== RISCV_PRIV_REGNUM
)
933 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
935 if (riscv_is_regnum_a_named_csr (regnum
))
939 else if (reggroup
== vector_reggroup
)
945 /* Implement the print_registers_info gdbarch method. This is used by
946 'info registers' and 'info all-registers'. */
949 riscv_print_registers_info (struct gdbarch
*gdbarch
,
950 struct ui_file
*file
,
951 struct frame_info
*frame
,
952 int regnum
, int print_all
)
956 /* Print one specified register. */
957 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
958 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
959 error (_("Not a valid register for the current processor type"));
960 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
964 struct reggroup
*reggroup
;
967 reggroup
= all_reggroup
;
969 reggroup
= general_reggroup
;
971 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
973 /* Zero never changes, so might as well hide by default. */
974 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
977 /* Registers with no name are not valid on this ISA. */
978 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
979 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
982 /* Is the register in the group we're interested in? */
983 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
986 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
991 /* Class that handles one decoded RiscV instruction. */
997 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
1000 /* Unknown value is used at initialisation time. */
1003 /* These instructions are all the ones we are interested in during the
1013 /* These are needed for software breakopint support. */
1022 /* These are needed for stepping over atomic sequences. */
1026 /* Other instructions are not interesting during the prologue scan, and
1041 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1043 /* Get the length of the instruction in bytes. */
1045 { return m_length
; }
1047 /* Get the opcode for this instruction. */
1048 enum opcode
opcode () const
1049 { return m_opcode
; }
1051 /* Get destination register field for this instruction. This is only
1052 valid if the OPCODE implies there is such a field for this
1057 /* Get the RS1 register field for this instruction. This is only valid
1058 if the OPCODE implies there is such a field for this instruction. */
1062 /* Get the RS2 register field for this instruction. This is only valid
1063 if the OPCODE implies there is such a field for this instruction. */
1067 /* Get the immediate for this instruction in signed form. This is only
1068 valid if the OPCODE implies there is such a field for this
1070 int imm_signed () const
1075 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1076 int decode_register_index (unsigned long opcode
, int offset
)
1078 return (opcode
>> offset
) & 0x1F;
1081 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1082 int decode_register_index_short (unsigned long opcode
, int offset
)
1084 return ((opcode
>> offset
) & 0x7) + 8;
1087 /* Helper for DECODE, decode 32-bit R-type instruction. */
1088 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1091 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1092 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1093 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1096 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1097 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1100 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1101 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1104 /* Helper for DECODE, decode 32-bit I-type instruction. */
1105 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1108 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1109 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1110 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1113 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1114 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1117 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1118 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
1121 /* Helper for DECODE, decode 32-bit S-type instruction. */
1122 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1125 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1126 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1127 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1130 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1131 encoding is different for each CS format instruction, so extracting
1132 the immediate is left up to the caller, who should pass the extracted
1133 immediate value through in IMM. */
1134 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1138 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1139 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1142 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1143 encoding is different for each CSS format instruction, so extracting
1144 the immediate is left up to the caller, who should pass the extracted
1145 immediate value through in IMM. */
1146 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1150 m_rs1
= RISCV_SP_REGNUM
;
1151 /* Not a compressed register number in this case. */
1152 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1155 /* Helper for DECODE, decode 32-bit U-type instruction. */
1156 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1159 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1160 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1163 /* Helper for DECODE, decode 32-bit J-type instruction. */
1164 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1167 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1168 m_imm
.s
= EXTRACT_UJTYPE_IMM (ival
);
1171 /* Helper for DECODE, decode 32-bit J-type instruction. */
1172 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1175 m_imm
.s
= EXTRACT_RVC_J_IMM (ival
);
1178 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1181 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1182 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1183 m_imm
.s
= EXTRACT_SBTYPE_IMM (ival
);
1186 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1189 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1190 m_imm
.s
= EXTRACT_RVC_B_IMM (ival
);
1193 /* Fetch instruction from target memory at ADDR, return the content of
1194 the instruction, and update LEN with the instruction length. */
1195 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1196 CORE_ADDR addr
, int *len
);
1198 /* The length of the instruction in bytes. Should be 2 or 4. */
1201 /* The instruction opcode. */
1202 enum opcode m_opcode
;
1204 /* The three possible registers an instruction might reference. Not
1205 every instruction fills in all of these registers. Which fields are
1206 valid depends on the opcode. The naming of these fields matches the
1207 naming in the riscv isa manual. */
1212 /* Possible instruction immediate. This is only valid if the instruction
1213 format contains an immediate, not all instruction, whether this is
1214 valid depends on the opcode. Despite only having one format for now
1215 the immediate is packed into a union, later instructions might require
1216 an unsigned formatted immediate, having the union in place now will
1217 reduce the need for code churn later. */
1218 union riscv_insn_immediate
1220 riscv_insn_immediate ()
1230 /* Fetch instruction from target memory at ADDR, return the content of the
1231 instruction, and update LEN with the instruction length. */
1234 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1235 CORE_ADDR addr
, int *len
)
1237 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1239 int instlen
, status
;
1241 /* All insns are at least 16 bits. */
1242 status
= target_read_memory (addr
, buf
, 2);
1244 memory_error (TARGET_XFER_E_IO
, addr
);
1246 /* If we need more, grab it now. */
1247 instlen
= riscv_insn_length (buf
[0]);
1248 gdb_assert (instlen
<= sizeof (buf
));
1253 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1255 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1258 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1261 /* Fetch from target memory an instruction at PC and decode it. This can
1262 throw an error if the memory access fails, callers are responsible for
1263 handling this error if that is appropriate. */
1266 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1270 /* Fetch the instruction, and the instructions length. */
1271 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1275 if (is_add_insn (ival
))
1276 decode_r_type_insn (ADD
, ival
);
1277 else if (is_addw_insn (ival
))
1278 decode_r_type_insn (ADDW
, ival
);
1279 else if (is_addi_insn (ival
))
1280 decode_i_type_insn (ADDI
, ival
);
1281 else if (is_addiw_insn (ival
))
1282 decode_i_type_insn (ADDIW
, ival
);
1283 else if (is_auipc_insn (ival
))
1284 decode_u_type_insn (AUIPC
, ival
);
1285 else if (is_lui_insn (ival
))
1286 decode_u_type_insn (LUI
, ival
);
1287 else if (is_sd_insn (ival
))
1288 decode_s_type_insn (SD
, ival
);
1289 else if (is_sw_insn (ival
))
1290 decode_s_type_insn (SW
, ival
);
1291 else if (is_jal_insn (ival
))
1292 decode_j_type_insn (JAL
, ival
);
1293 else if (is_jalr_insn (ival
))
1294 decode_i_type_insn (JALR
, ival
);
1295 else if (is_beq_insn (ival
))
1296 decode_b_type_insn (BEQ
, ival
);
1297 else if (is_bne_insn (ival
))
1298 decode_b_type_insn (BNE
, ival
);
1299 else if (is_blt_insn (ival
))
1300 decode_b_type_insn (BLT
, ival
);
1301 else if (is_bge_insn (ival
))
1302 decode_b_type_insn (BGE
, ival
);
1303 else if (is_bltu_insn (ival
))
1304 decode_b_type_insn (BLTU
, ival
);
1305 else if (is_bgeu_insn (ival
))
1306 decode_b_type_insn (BGEU
, ival
);
1307 else if (is_lr_w_insn (ival
))
1308 decode_r_type_insn (LR
, ival
);
1309 else if (is_lr_d_insn (ival
))
1310 decode_r_type_insn (LR
, ival
);
1311 else if (is_sc_w_insn (ival
))
1312 decode_r_type_insn (SC
, ival
);
1313 else if (is_sc_d_insn (ival
))
1314 decode_r_type_insn (SC
, ival
);
1316 /* None of the other fields are valid in this case. */
1319 else if (m_length
== 2)
1321 int xlen
= riscv_isa_xlen (gdbarch
);
1323 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1324 C_JALR. So must try to match C_JALR first as it has more bits in
1326 if (is_c_jalr_insn (ival
))
1327 decode_cr_type_insn (JALR
, ival
);
1328 else if (is_c_add_insn (ival
))
1329 decode_cr_type_insn (ADD
, ival
);
1330 /* C_ADDW is RV64 and RV128 only. */
1331 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1332 decode_cr_type_insn (ADDW
, ival
);
1333 else if (is_c_addi_insn (ival
))
1334 decode_ci_type_insn (ADDI
, ival
);
1335 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1336 only and C_JAL is RV32 only. */
1337 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1338 decode_ci_type_insn (ADDIW
, ival
);
1339 else if (xlen
== 4 && is_c_jal_insn (ival
))
1340 decode_cj_type_insn (JAL
, ival
);
1341 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1342 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1344 else if (is_c_addi16sp_insn (ival
))
1347 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1348 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1350 else if (is_c_addi4spn_insn (ival
))
1353 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1354 m_rs1
= RISCV_SP_REGNUM
;
1355 m_imm
.s
= EXTRACT_RVC_ADDI4SPN_IMM (ival
);
1357 else if (is_c_lui_insn (ival
))
1360 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1361 m_imm
.s
= EXTRACT_RVC_LUI_IMM (ival
);
1363 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1364 and C_FSW is RV32 only. */
1365 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1366 decode_cs_type_insn (SD
, ival
, EXTRACT_RVC_LD_IMM (ival
));
1367 else if (is_c_sw_insn (ival
))
1368 decode_cs_type_insn (SW
, ival
, EXTRACT_RVC_LW_IMM (ival
));
1369 else if (is_c_swsp_insn (ival
))
1370 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SWSP_IMM (ival
));
1371 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1372 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SDSP_IMM (ival
));
1373 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1374 So must try to match C_JR first as it ahs more bits in mask. */
1375 else if (is_c_jr_insn (ival
))
1376 decode_cr_type_insn (JALR
, ival
);
1377 else if (is_c_j_insn (ival
))
1378 decode_cj_type_insn (JAL
, ival
);
1379 else if (is_c_beqz_insn (ival
))
1380 decode_cb_type_insn (BEQ
, ival
);
1381 else if (is_c_bnez_insn (ival
))
1382 decode_cb_type_insn (BNE
, ival
);
1384 /* None of the other fields of INSN are valid in this case. */
1389 /* This must be a 6 or 8 byte instruction, we don't currently decode
1390 any of these, so just ignore it. */
1391 gdb_assert (m_length
== 6 || m_length
== 8);
1396 /* The prologue scanner. This is currently only used for skipping the
1397 prologue of a function when the DWARF information is not sufficient.
1398 However, it is written with filling of the frame cache in mind, which
1399 is why different groups of stack setup instructions are split apart
1400 during the core of the inner loop. In the future, the intention is to
1401 extend this function to fully support building up a frame cache that
1402 can unwind register values when there is no DWARF information. */
1405 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1406 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1407 struct riscv_unwind_cache
*cache
)
1409 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1410 CORE_ADDR end_prologue_addr
= 0;
1412 /* Find an upper limit on the function prologue using the debug
1413 information. If the debug information could not be used to provide
1414 that bound, then use an arbitrary large number as the upper bound. */
1415 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1416 if (after_prologue_pc
== 0)
1417 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1418 if (after_prologue_pc
< end_pc
)
1419 end_pc
= after_prologue_pc
;
1421 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1422 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1423 regs
[regno
] = pv_register (regno
, 0);
1424 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1426 if (riscv_debug_unwinder
)
1429 "Prologue scan for function starting at %s (limit %s)\n",
1430 core_addr_to_string (start_pc
),
1431 core_addr_to_string (end_pc
));
1433 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1435 struct riscv_insn insn
;
1437 /* Decode the current instruction, and decide where the next
1438 instruction lives based on the size of this instruction. */
1439 insn
.decode (gdbarch
, cur_pc
);
1440 gdb_assert (insn
.length () > 0);
1441 next_pc
= cur_pc
+ insn
.length ();
1443 /* Look for common stack adjustment insns. */
1444 if ((insn
.opcode () == riscv_insn::ADDI
1445 || insn
.opcode () == riscv_insn::ADDIW
)
1446 && insn
.rd () == RISCV_SP_REGNUM
1447 && insn
.rs1 () == RISCV_SP_REGNUM
)
1449 /* Handle: addi sp, sp, -i
1450 or: addiw sp, sp, -i */
1451 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1452 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1454 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1456 else if ((insn
.opcode () == riscv_insn::SW
1457 || insn
.opcode () == riscv_insn::SD
)
1458 && (insn
.rs1 () == RISCV_SP_REGNUM
1459 || insn
.rs1 () == RISCV_FP_REGNUM
))
1461 /* Handle: sw reg, offset(sp)
1462 or: sd reg, offset(sp)
1463 or: sw reg, offset(s0)
1464 or: sd reg, offset(s0) */
1465 /* Instruction storing a register onto the stack. */
1466 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1467 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1468 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
1469 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
1472 else if (insn
.opcode () == riscv_insn::ADDI
1473 && insn
.rd () == RISCV_FP_REGNUM
1474 && insn
.rs1 () == RISCV_SP_REGNUM
)
1476 /* Handle: addi s0, sp, size */
1477 /* Instructions setting up the frame pointer. */
1478 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1479 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1481 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1483 else if ((insn
.opcode () == riscv_insn::ADD
1484 || insn
.opcode () == riscv_insn::ADDW
)
1485 && insn
.rd () == RISCV_FP_REGNUM
1486 && insn
.rs1 () == RISCV_SP_REGNUM
1487 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1489 /* Handle: add s0, sp, 0
1490 or: addw s0, sp, 0 */
1491 /* Instructions setting up the frame pointer. */
1492 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1493 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1494 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
1496 else if ((insn
.opcode () == riscv_insn::ADDI
1497 && insn
.rd () == RISCV_ZERO_REGNUM
1498 && insn
.rs1 () == RISCV_ZERO_REGNUM
1499 && insn
.imm_signed () == 0))
1501 /* Handle: add x0, x0, 0 (NOP) */
1503 else if (insn
.opcode () == riscv_insn::AUIPC
)
1505 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1506 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
1508 else if (insn
.opcode () == riscv_insn::LUI
)
1510 /* Handle: lui REG, n
1511 Where REG is not gp register. */
1512 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1513 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
1515 else if (insn
.opcode () == riscv_insn::ADDI
)
1517 /* Handle: addi REG1, REG2, IMM */
1518 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1519 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1521 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1523 else if (insn
.opcode () == riscv_insn::ADD
)
1525 /* Handle: addi REG1, REG2, IMM */
1526 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1527 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1528 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1529 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
1533 end_prologue_addr
= cur_pc
;
1538 if (end_prologue_addr
== 0)
1539 end_prologue_addr
= cur_pc
;
1541 if (riscv_debug_unwinder
)
1542 fprintf_unfiltered (gdb_stdlog
, "End of prologue at %s\n",
1543 core_addr_to_string (end_prologue_addr
));
1547 /* Figure out if it is a frame pointer or just a stack pointer. Also
1548 the offset held in the pv_t is from the original register value to
1549 the current value, which for a grows down stack means a negative
1550 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1551 from the current value to the original value. */
1552 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
1554 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
1555 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
1559 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
1560 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
1563 /* Assign offset from old SP to all saved registers. As we don't
1564 have the previous value for the frame base register at this
1565 point, we store the offset as the address in the trad_frame, and
1566 then convert this to an actual address later. */
1567 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
1570 if (stack
.find_reg (gdbarch
, i
, &offset
))
1572 if (riscv_debug_unwinder
)
1574 /* Display OFFSET as a signed value, the offsets are from
1575 the frame base address to the registers location on
1576 the stack, with a descending stack this means the
1577 offsets are always negative. */
1578 fprintf_unfiltered (gdb_stdlog
,
1579 "Register $%s at stack offset %s\n",
1580 gdbarch_register_name (gdbarch
, i
),
1581 plongest ((LONGEST
) offset
));
1583 trad_frame_set_addr (cache
->regs
, i
, offset
);
1588 return end_prologue_addr
;
1591 /* Implement the riscv_skip_prologue gdbarch method. */
1594 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1596 CORE_ADDR func_addr
;
1598 /* See if we can determine the end of the prologue via the symbol
1599 table. If so, then return either PC, or the PC after the
1600 prologue, whichever is greater. */
1601 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1603 CORE_ADDR post_prologue_pc
1604 = skip_prologue_using_sal (gdbarch
, func_addr
);
1606 if (post_prologue_pc
!= 0)
1607 return std::max (pc
, post_prologue_pc
);
1610 /* Can't determine prologue from the symbol table, need to examine
1611 instructions. Pass -1 for the end address to indicate the prologue
1612 scanner can scan as far as it needs to find the end of the prologue. */
1613 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
1616 /* Implement the gdbarch push dummy code callback. */
1619 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1620 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1621 struct type
*value_type
, CORE_ADDR
*real_pc
,
1622 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1624 /* Allocate space for a breakpoint, and keep the stack correctly
1632 /* Implement the gdbarch type alignment method, overrides the generic
1633 alignment algorithm for anything that is RISC-V specific. */
1636 riscv_type_align (gdbarch
*gdbarch
, type
*type
)
1638 type
= check_typedef (type
);
1639 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
))
1640 return std::min (TYPE_LENGTH (type
), (ULONGEST
) BIGGEST_ALIGNMENT
);
1642 /* Anything else will be aligned by the generic code. */
1646 /* Holds information about a single argument either being passed to an
1647 inferior function, or returned from an inferior function. This includes
1648 information about the size, type, etc of the argument, and also
1649 information about how the argument will be passed (or returned). */
1651 struct riscv_arg_info
1653 /* Contents of the argument. */
1654 const gdb_byte
*contents
;
1656 /* Length of argument. */
1659 /* Alignment required for an argument of this type. */
1662 /* The type for this argument. */
1665 /* Each argument can have either 1 or 2 locations assigned to it. Each
1666 location describes where part of the argument will be placed. The
1667 second location is valid based on the LOC_TYPE and C_LENGTH fields
1668 of the first location (which is always valid). */
1671 /* What type of location this is. */
1674 /* Argument passed in a register. */
1677 /* Argument passed as an on stack argument. */
1680 /* Argument passed by reference. The second location is always
1681 valid for a BY_REF argument, and describes where the address
1682 of the BY_REF argument should be placed. */
1686 /* Information that depends on the location type. */
1689 /* Which register number to use. */
1692 /* The offset into the stack region. */
1696 /* The length of contents covered by this location. If this is less
1697 than the total length of the argument, then the second location
1698 will be valid, and will describe where the rest of the argument
1702 /* The offset within CONTENTS for this part of the argument. Will
1703 always be 0 for the first part. For the second part of the
1704 argument, this might be the C_LENGTH value of the first part,
1705 however, if we are passing a structure in two registers, and there's
1706 is padding between the first and second field, then this offset
1707 might be greater than the length of the first argument part. When
1708 the second argument location is not holding part of the argument
1709 value, but is instead holding the address of a reference argument,
1710 then this offset will be set to 0. */
1714 /* TRUE if this is an unnamed argument. */
1718 /* Information about a set of registers being used for passing arguments as
1719 part of a function call. The register set must be numerically
1720 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1721 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1723 struct riscv_arg_reg
1725 riscv_arg_reg (int first
, int last
)
1726 : next_regnum (first
),
1732 /* The GDB register number to use in this set. */
1735 /* The last GDB register number to use in this set. */
1739 /* Arguments can be passed as on stack arguments, or by reference. The
1740 on stack arguments must be in a continuous region starting from $sp,
1741 while the by reference arguments can be anywhere, but we'll put them
1742 on the stack after (at higher address) the on stack arguments.
1744 This might not be the right approach to take. The ABI is clear that
1745 an argument passed by reference can be modified by the callee, which
1746 us placing the argument (temporarily) onto the stack will not achieve
1747 (changes will be lost). There's also the possibility that very large
1748 arguments could overflow the stack.
1750 This struct is used to track offset into these two areas for where
1751 arguments are to be placed. */
1752 struct riscv_memory_offsets
1754 riscv_memory_offsets ()
1761 /* Offset into on stack argument area. */
1764 /* Offset into the pass by reference area. */
1768 /* Holds information about where arguments to a call will be placed. This
1769 is updated as arguments are added onto the call, and can be used to
1770 figure out where the next argument should be placed. */
1772 struct riscv_call_info
1774 riscv_call_info (struct gdbarch
*gdbarch
)
1775 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1776 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1778 xlen
= riscv_abi_xlen (gdbarch
);
1779 flen
= riscv_abi_flen (gdbarch
);
1781 /* Disable use of floating point registers if needed. */
1782 if (!riscv_has_fp_abi (gdbarch
))
1783 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1786 /* Track the memory areas used for holding in-memory arguments to a
1788 struct riscv_memory_offsets memory
;
1790 /* Holds information about the next integer register to use for passing
1792 struct riscv_arg_reg int_regs
;
1794 /* Holds information about the next floating point register to use for
1795 passing an argument. */
1796 struct riscv_arg_reg float_regs
;
1798 /* The XLEN and FLEN are copied in to this structure for convenience, and
1799 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
1804 /* Return the number of registers available for use as parameters in the
1805 register set REG. Returned value can be 0 or more. */
1808 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1810 if (reg
->next_regnum
> reg
->last_regnum
)
1813 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1816 /* If there is at least one register available in the register set REG then
1817 the next register from REG is assigned to LOC and the length field of
1818 LOC is updated to LENGTH. The register set REG is updated to indicate
1819 that the assigned register is no longer available and the function
1822 If there are no registers available in REG then the function returns
1823 false, and LOC and REG are unchanged. */
1826 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1827 struct riscv_arg_reg
*reg
,
1828 int length
, int offset
)
1830 if (reg
->next_regnum
<= reg
->last_regnum
)
1832 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1833 loc
->loc_data
.regno
= reg
->next_regnum
;
1835 loc
->c_length
= length
;
1836 loc
->c_offset
= offset
;
1843 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1844 record that an area of stack has been used to hold the parameter
1847 The length field of LOC is updated to LENGTH, the length of the
1848 parameter being stored, and ALIGN is the alignment required by the
1849 parameter, which will affect how memory is allocated out of MEMORY. */
1852 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1853 struct riscv_memory_offsets
*memory
,
1854 int length
, int align
)
1856 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1858 = align_up (memory
->arg_offset
, align
);
1859 loc
->loc_data
.offset
= memory
->arg_offset
;
1860 memory
->arg_offset
+= length
;
1861 loc
->c_length
= length
;
1863 /* Offset is always 0, either we're the first location part, in which
1864 case we're reading content from the start of the argument, or we're
1865 passing the address of a reference argument, so 0. */
1869 /* Update AINFO, which describes an argument that should be passed or
1870 returned using the integer ABI. The argloc fields within AINFO are
1871 updated to describe the location in which the argument will be passed to
1872 a function, or returned from a function.
1874 The CINFO structure contains the ongoing call information, the holds
1875 information such as which argument registers are remaining to be
1876 assigned to parameter, and how much memory has been used by parameters
1879 By examining the state of CINFO a suitable location can be selected,
1880 and assigned to AINFO. */
1883 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1884 struct riscv_call_info
*cinfo
)
1886 if (ainfo
->length
> (2 * cinfo
->xlen
))
1888 /* Argument is going to be passed by reference. */
1889 ainfo
->argloc
[0].loc_type
1890 = riscv_arg_info::location::by_ref
;
1891 cinfo
->memory
.ref_offset
1892 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1893 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1894 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1895 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1897 /* The second location for this argument is given over to holding the
1898 address of the by-reference data. Pass 0 for the offset as this
1899 is not part of the actual argument value. */
1900 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1903 riscv_assign_stack_location (&ainfo
->argloc
[1],
1904 &cinfo
->memory
, cinfo
->xlen
,
1909 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
1910 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
1912 /* Unnamed arguments in registers that require 2*XLEN alignment are
1913 passed in an aligned register pair. */
1914 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
1915 && cinfo
->int_regs
.next_regnum
& 1)
1916 cinfo
->int_regs
.next_regnum
++;
1918 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1919 &cinfo
->int_regs
, len
, 0))
1920 riscv_assign_stack_location (&ainfo
->argloc
[0],
1921 &cinfo
->memory
, len
, align
);
1923 if (len
< ainfo
->length
)
1925 len
= ainfo
->length
- len
;
1926 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1927 &cinfo
->int_regs
, len
,
1929 riscv_assign_stack_location (&ainfo
->argloc
[1],
1930 &cinfo
->memory
, len
, cinfo
->xlen
);
1935 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1936 is being passed with the floating point ABI. */
1939 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1940 struct riscv_call_info
*cinfo
)
1942 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
1943 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1946 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1949 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1953 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1954 is a complex floating point argument, and is therefore handled
1955 differently to other argument types. */
1958 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1959 struct riscv_call_info
*cinfo
)
1961 if (ainfo
->length
<= (2 * cinfo
->flen
)
1962 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
1963 && !ainfo
->is_unnamed
)
1966 int len
= ainfo
->length
/ 2;
1968 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1969 &cinfo
->float_regs
, len
, 0);
1970 gdb_assert (result
);
1972 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1973 &cinfo
->float_regs
, len
, len
);
1974 gdb_assert (result
);
1977 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1980 /* A structure used for holding information about a structure type within
1981 the inferior program. The RiscV ABI has special rules for handling some
1982 structures with a single field or with two fields. The counting of
1983 fields here is done after flattening out all nested structures. */
1985 class riscv_struct_info
1988 riscv_struct_info ()
1989 : m_number_of_fields (0),
1990 m_types
{ nullptr, nullptr },
1996 /* Analyse TYPE descending into nested structures, count the number of
1997 scalar fields and record the types of the first two fields found. */
1998 void analyse (struct type
*type
)
2000 analyse_inner (type
, 0);
2003 /* The number of scalar fields found in the analysed type. This is
2004 currently only accurate if the value returned is 0, 1, or 2 as the
2005 analysis stops counting when the number of fields is 3. This is
2006 because the RiscV ABI only has special cases for 1 or 2 fields,
2007 anything else we just don't care about. */
2008 int number_of_fields () const
2009 { return m_number_of_fields
; }
2011 /* Return the type for scalar field INDEX within the analysed type. Will
2012 return nullptr if there is no field at that index. Only INDEX values
2013 0 and 1 can be requested as the RiscV ABI only has special cases for
2014 structures with 1 or 2 fields. */
2015 struct type
*field_type (int index
) const
2017 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2018 return m_types
[index
];
2021 /* Return the offset of scalar field INDEX within the analysed type. Will
2022 return 0 if there is no field at that index. Only INDEX values 0 and
2023 1 can be requested as the RiscV ABI only has special cases for
2024 structures with 1 or 2 fields. */
2025 int field_offset (int index
) const
2027 gdb_assert (index
< (sizeof (m_offsets
) / sizeof (m_offsets
[0])));
2028 return m_offsets
[index
];
2032 /* The number of scalar fields found within the structure after recursing
2033 into nested structures. */
2034 int m_number_of_fields
;
2036 /* The types of the first two scalar fields found within the structure
2037 after recursing into nested structures. */
2038 struct type
*m_types
[2];
2040 /* The offsets of the first two scalar fields found within the structure
2041 after recursing into nested structures. */
2044 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2045 offset from the start of the top level structure being analysed. */
2046 void analyse_inner (struct type
*type
, int offset
);
2049 /* See description in class declaration. */
2052 riscv_struct_info::analyse_inner (struct type
*type
, int offset
)
2054 unsigned int count
= TYPE_NFIELDS (type
);
2057 for (i
= 0; i
< count
; ++i
)
2059 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
2062 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
2063 field_type
= check_typedef (field_type
);
2065 = offset
+ TYPE_FIELD_BITPOS (type
, i
) / TARGET_CHAR_BIT
;
2067 switch (TYPE_CODE (field_type
))
2069 case TYPE_CODE_STRUCT
:
2070 analyse_inner (field_type
, field_offset
);
2074 /* RiscV only flattens out structures. Anything else does not
2075 need to be flattened, we just record the type, and when we
2076 look at the analysis results we'll realise this is not a
2077 structure we can special case, and pass the structure in
2079 if (m_number_of_fields
< 2)
2081 m_types
[m_number_of_fields
] = field_type
;
2082 m_offsets
[m_number_of_fields
] = field_offset
;
2084 m_number_of_fields
++;
2088 /* RiscV only has special handling for structures with 1 or 2 scalar
2089 fields, any more than that and the structure is just passed in
2090 memory. We can safely drop out early when we find 3 or more
2093 if (m_number_of_fields
> 2)
2098 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2099 is a structure. Small structures on RiscV have some special case
2100 handling in order that the structure might be passed in register.
2101 Larger structures are passed in memory. After assigning location
2102 information to AINFO, CINFO will have been updated. */
2105 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2106 struct riscv_call_info
*cinfo
)
2108 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2110 struct riscv_struct_info sinfo
;
2112 sinfo
.analyse (ainfo
->type
);
2113 if (sinfo
.number_of_fields () == 1
2114 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
2116 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2117 except we use the type of the complex field instead of the
2118 type from AINFO, and the first location might be at a non-zero
2120 if (TYPE_LENGTH (sinfo
.field_type (0)) <= (2 * cinfo
->flen
)
2121 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2122 && !ainfo
->is_unnamed
)
2125 int len
= TYPE_LENGTH (sinfo
.field_type (0)) / 2;
2126 int offset
= sinfo
.field_offset (0);
2128 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2129 &cinfo
->float_regs
, len
,
2131 gdb_assert (result
);
2133 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2134 &cinfo
->float_regs
, len
,
2136 gdb_assert (result
);
2139 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2143 if (sinfo
.number_of_fields () == 1
2144 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
2146 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2147 except we use the type of the first scalar field instead of
2148 the type from AINFO. Also the location might be at a non-zero
2150 if (TYPE_LENGTH (sinfo
.field_type (0)) > cinfo
->flen
2151 || ainfo
->is_unnamed
)
2152 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2155 int offset
= sinfo
.field_offset (0);
2156 int len
= TYPE_LENGTH (sinfo
.field_type (0));
2158 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2161 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2166 if (sinfo
.number_of_fields () == 2
2167 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
2168 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2169 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
2170 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
2171 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2173 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2174 int offset
= sinfo
.field_offset (0);
2175 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2176 &cinfo
->float_regs
, len0
, offset
))
2177 error (_("failed during argument setup"));
2179 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2180 offset
= sinfo
.field_offset (1);
2181 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
2182 - TYPE_LENGTH (sinfo
.field_type (0))));
2184 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2187 error (_("failed during argument setup"));
2191 if (sinfo
.number_of_fields () == 2
2192 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2193 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
2194 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2195 && is_integral_type (sinfo
.field_type (1))
2196 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
2198 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2199 int offset
= sinfo
.field_offset (0);
2200 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2201 &cinfo
->float_regs
, len0
, offset
))
2202 error (_("failed during argument setup"));
2204 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2205 offset
= sinfo
.field_offset (1);
2206 gdb_assert (len1
<= cinfo
->xlen
);
2207 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2208 &cinfo
->int_regs
, len1
, offset
))
2209 error (_("failed during argument setup"));
2213 if (sinfo
.number_of_fields () == 2
2214 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2215 && (is_integral_type (sinfo
.field_type (0))
2216 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
2217 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
2218 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
2220 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2221 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2223 gdb_assert (len0
<= cinfo
->xlen
);
2224 gdb_assert (len1
<= cinfo
->flen
);
2226 int offset
= sinfo
.field_offset (0);
2227 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2228 &cinfo
->int_regs
, len0
, offset
))
2229 error (_("failed during argument setup"));
2231 offset
= sinfo
.field_offset (1);
2232 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2235 error (_("failed during argument setup"));
2241 /* Non of the structure flattening cases apply, so we just pass using
2243 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2246 /* Assign a location to call (or return) argument AINFO, the location is
2247 selected from CINFO which holds information about what call argument
2248 locations are available for use next. The TYPE is the type of the
2249 argument being passed, this information is recorded into AINFO (along
2250 with some additional information derived from the type). IS_UNNAMED
2251 is true if this is an unnamed (stdarg) argument, this info is also
2252 recorded into AINFO.
2254 After assigning a location to AINFO, CINFO will have been updated. */
2257 riscv_arg_location (struct gdbarch
*gdbarch
,
2258 struct riscv_arg_info
*ainfo
,
2259 struct riscv_call_info
*cinfo
,
2260 struct type
*type
, bool is_unnamed
)
2263 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
2264 ainfo
->align
= type_align (ainfo
->type
);
2265 ainfo
->is_unnamed
= is_unnamed
;
2266 ainfo
->contents
= nullptr;
2267 ainfo
->argloc
[0].c_length
= 0;
2268 ainfo
->argloc
[1].c_length
= 0;
2270 switch (TYPE_CODE (ainfo
->type
))
2273 case TYPE_CODE_BOOL
:
2274 case TYPE_CODE_CHAR
:
2275 case TYPE_CODE_RANGE
:
2276 case TYPE_CODE_ENUM
:
2278 if (ainfo
->length
<= cinfo
->xlen
)
2280 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2281 ainfo
->length
= cinfo
->xlen
;
2283 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2285 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2286 ainfo
->length
= 2 * cinfo
->xlen
;
2289 /* Recalculate the alignment requirement. */
2290 ainfo
->align
= type_align (ainfo
->type
);
2291 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2295 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2298 case TYPE_CODE_COMPLEX
:
2299 riscv_call_arg_complex_float (ainfo
, cinfo
);
2302 case TYPE_CODE_STRUCT
:
2303 riscv_call_arg_struct (ainfo
, cinfo
);
2307 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2312 /* Used for printing debug information about the call argument location in
2313 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2314 addresses for the location of pass-by-reference and
2315 arguments-on-the-stack memory areas. */
2318 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2319 struct riscv_arg_info
*info
,
2320 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2322 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2323 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2324 switch (info
->argloc
[0].loc_type
)
2326 case riscv_arg_info::location::in_reg
:
2328 (stream
, ", register %s",
2329 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2330 if (info
->argloc
[0].c_length
< info
->length
)
2332 switch (info
->argloc
[1].loc_type
)
2334 case riscv_arg_info::location::in_reg
:
2336 (stream
, ", register %s",
2337 gdbarch_register_name (gdbarch
,
2338 info
->argloc
[1].loc_data
.regno
));
2341 case riscv_arg_info::location::on_stack
:
2342 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2343 info
->argloc
[1].loc_data
.offset
);
2346 case riscv_arg_info::location::by_ref
:
2348 /* The second location should never be a reference, any
2349 argument being passed by reference just places its address
2350 in the first location and is done. */
2351 error (_("invalid argument location"));
2355 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2356 fprintf_unfiltered (stream
, " (offset 0x%x)",
2357 info
->argloc
[1].c_offset
);
2361 case riscv_arg_info::location::on_stack
:
2362 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2363 info
->argloc
[0].loc_data
.offset
);
2366 case riscv_arg_info::location::by_ref
:
2368 (stream
, ", by reference, data at offset 0x%x (%s)",
2369 info
->argloc
[0].loc_data
.offset
,
2370 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2371 if (info
->argloc
[1].loc_type
2372 == riscv_arg_info::location::in_reg
)
2374 (stream
, ", address in register %s",
2375 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2378 gdb_assert (info
->argloc
[1].loc_type
2379 == riscv_arg_info::location::on_stack
);
2381 (stream
, ", address on stack at offset 0x%x (%s)",
2382 info
->argloc
[1].loc_data
.offset
,
2383 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2388 gdb_assert_not_reached (_("unknown argument location type"));
2392 /* Implement the push dummy call gdbarch callback. */
2395 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2396 struct value
*function
,
2397 struct regcache
*regcache
,
2400 struct value
**args
,
2402 function_call_return_method return_method
,
2403 CORE_ADDR struct_addr
)
2406 CORE_ADDR sp_args
, sp_refs
;
2407 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2409 struct riscv_arg_info
*arg_info
=
2410 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2412 struct riscv_call_info
call_info (gdbarch
);
2416 struct type
*ftype
= check_typedef (value_type (function
));
2418 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
2419 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
2421 /* We'll use register $a0 if we're returning a struct. */
2422 if (return_method
== return_method_struct
)
2423 ++call_info
.int_regs
.next_regnum
;
2425 for (i
= 0; i
< nargs
; ++i
)
2427 struct value
*arg_value
;
2428 struct type
*arg_type
;
2429 struct riscv_arg_info
*info
= &arg_info
[i
];
2431 arg_value
= args
[i
];
2432 arg_type
= check_typedef (value_type (arg_value
));
2434 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
2435 TYPE_VARARGS (ftype
) && i
>= TYPE_NFIELDS (ftype
));
2437 if (info
->type
!= arg_type
)
2438 arg_value
= value_cast (info
->type
, arg_value
);
2439 info
->contents
= value_contents (arg_value
);
2442 /* Adjust the stack pointer and align it. */
2443 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2444 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2446 if (riscv_debug_infcall
> 0)
2448 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2449 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2450 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2451 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2452 call_info
.xlen
, call_info
.flen
);
2453 if (return_method
== return_method_struct
)
2454 fprintf_unfiltered (gdb_stdlog
,
2455 "[*] struct return pointer in register $A0\n");
2456 for (i
= 0; i
< nargs
; ++i
)
2458 struct riscv_arg_info
*info
= &arg_info
[i
];
2460 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2461 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2462 fprintf_unfiltered (gdb_stdlog
, "\n");
2464 if (call_info
.memory
.arg_offset
> 0
2465 || call_info
.memory
.ref_offset
> 0)
2467 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2468 core_addr_to_string (osp
));
2469 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2470 call_info
.memory
.arg_offset
);
2471 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2472 call_info
.memory
.ref_offset
);
2473 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2474 core_addr_to_string_nz (osp
- sp
));
2478 /* Now load the argument into registers, or onto the stack. */
2480 if (return_method
== return_method_struct
)
2482 gdb_byte buf
[sizeof (LONGEST
)];
2484 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2485 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
2488 for (i
= 0; i
< nargs
; ++i
)
2491 int second_arg_length
= 0;
2492 const gdb_byte
*second_arg_data
;
2493 struct riscv_arg_info
*info
= &arg_info
[i
];
2495 gdb_assert (info
->length
> 0);
2497 switch (info
->argloc
[0].loc_type
)
2499 case riscv_arg_info::location::in_reg
:
2501 gdb_byte tmp
[sizeof (ULONGEST
)];
2503 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2504 /* FP values in FP registers must be NaN-boxed. */
2505 if (riscv_is_fp_regno_p (info
->argloc
[0].loc_data
.regno
)
2506 && info
->argloc
[0].c_length
< call_info
.flen
)
2507 memset (tmp
, -1, sizeof (tmp
));
2509 memset (tmp
, 0, sizeof (tmp
));
2510 memcpy (tmp
, (info
->contents
+ info
->argloc
[0].c_offset
),
2511 info
->argloc
[0].c_length
);
2512 regcache
->cooked_write (info
->argloc
[0].loc_data
.regno
, tmp
);
2514 (((info
->argloc
[0].c_length
+ info
->argloc
[0].c_offset
) < info
->length
)
2515 ? info
->argloc
[1].c_length
: 0);
2516 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2520 case riscv_arg_info::location::on_stack
:
2521 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2522 write_memory (dst
, info
->contents
, info
->length
);
2523 second_arg_length
= 0;
2526 case riscv_arg_info::location::by_ref
:
2527 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2528 write_memory (dst
, info
->contents
, info
->length
);
2530 second_arg_length
= call_info
.xlen
;
2531 second_arg_data
= (gdb_byte
*) &dst
;
2535 gdb_assert_not_reached (_("unknown argument location type"));
2538 if (second_arg_length
> 0)
2540 switch (info
->argloc
[1].loc_type
)
2542 case riscv_arg_info::location::in_reg
:
2544 gdb_byte tmp
[sizeof (ULONGEST
)];
2546 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2547 && second_arg_length
<= call_info
.flen
)
2548 || second_arg_length
<= call_info
.xlen
);
2549 /* FP values in FP registers must be NaN-boxed. */
2550 if (riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2551 && second_arg_length
< call_info
.flen
)
2552 memset (tmp
, -1, sizeof (tmp
));
2554 memset (tmp
, 0, sizeof (tmp
));
2555 memcpy (tmp
, second_arg_data
, second_arg_length
);
2556 regcache
->cooked_write (info
->argloc
[1].loc_data
.regno
, tmp
);
2560 case riscv_arg_info::location::on_stack
:
2564 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2565 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2569 case riscv_arg_info::location::by_ref
:
2571 /* The second location should never be a reference, any
2572 argument being passed by reference just places its address
2573 in the first location and is done. */
2574 error (_("invalid argument location"));
2580 /* Set the dummy return value to bp_addr.
2581 A dummy breakpoint will be setup to execute the call. */
2583 if (riscv_debug_infcall
> 0)
2584 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2585 core_addr_to_string (bp_addr
));
2586 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2588 /* Finally, update the stack pointer. */
2590 if (riscv_debug_infcall
> 0)
2591 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2592 core_addr_to_string (sp
));
2593 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2598 /* Implement the return_value gdbarch method. */
2600 static enum return_value_convention
2601 riscv_return_value (struct gdbarch
*gdbarch
,
2602 struct value
*function
,
2604 struct regcache
*regcache
,
2606 const gdb_byte
*writebuf
)
2608 struct riscv_call_info
call_info (gdbarch
);
2609 struct riscv_arg_info info
;
2610 struct type
*arg_type
;
2612 arg_type
= check_typedef (type
);
2613 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
2615 if (riscv_debug_infcall
> 0)
2617 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2618 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2619 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2620 fprintf_unfiltered (gdb_stdlog
, "\n");
2623 if (readbuf
!= nullptr || writebuf
!= nullptr)
2625 unsigned int arg_len
;
2626 struct value
*abi_val
;
2627 gdb_byte
*old_readbuf
= nullptr;
2630 /* We only do one thing at a time. */
2631 gdb_assert (readbuf
== nullptr || writebuf
== nullptr);
2633 /* In some cases the argument is not returned as the declared type,
2634 and we need to cast to or from the ABI type in order to
2635 correctly access the argument. When writing to the machine we
2636 do the cast here, when reading from the machine the cast occurs
2637 later, after extracting the value. As the ABI type can be
2638 larger than the declared type, then the read or write buffers
2639 passed in might be too small. Here we ensure that we are using
2640 buffers of sufficient size. */
2641 if (writebuf
!= nullptr)
2643 struct value
*arg_val
= value_from_contents (arg_type
, writebuf
);
2644 abi_val
= value_cast (info
.type
, arg_val
);
2645 writebuf
= value_contents_raw (abi_val
);
2649 abi_val
= allocate_value (info
.type
);
2650 old_readbuf
= readbuf
;
2651 readbuf
= value_contents_raw (abi_val
);
2653 arg_len
= TYPE_LENGTH (info
.type
);
2655 switch (info
.argloc
[0].loc_type
)
2657 /* Return value in register(s). */
2658 case riscv_arg_info::location::in_reg
:
2660 regnum
= info
.argloc
[0].loc_data
.regno
;
2661 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
2662 gdb_assert (info
.argloc
[0].c_length
2663 <= register_size (gdbarch
, regnum
));
2667 gdb_byte
*ptr
= readbuf
+ info
.argloc
[0].c_offset
;
2668 regcache
->cooked_read_part (regnum
, 0,
2669 info
.argloc
[0].c_length
,
2675 const gdb_byte
*ptr
= writebuf
+ info
.argloc
[0].c_offset
;
2676 regcache
->cooked_write_part (regnum
, 0,
2677 info
.argloc
[0].c_length
,
2681 /* A return value in register can have a second part in a
2683 if (info
.argloc
[1].c_length
> 0)
2685 switch (info
.argloc
[1].loc_type
)
2687 case riscv_arg_info::location::in_reg
:
2688 regnum
= info
.argloc
[1].loc_data
.regno
;
2690 gdb_assert ((info
.argloc
[0].c_length
2691 + info
.argloc
[1].c_length
) <= arg_len
);
2692 gdb_assert (info
.argloc
[1].c_length
2693 <= register_size (gdbarch
, regnum
));
2697 readbuf
+= info
.argloc
[1].c_offset
;
2698 regcache
->cooked_read_part (regnum
, 0,
2699 info
.argloc
[1].c_length
,
2705 writebuf
+= info
.argloc
[1].c_offset
;
2706 regcache
->cooked_write_part (regnum
, 0,
2707 info
.argloc
[1].c_length
,
2712 case riscv_arg_info::location::by_ref
:
2713 case riscv_arg_info::location::on_stack
:
2715 error (_("invalid argument location"));
2722 /* Return value by reference will have its address in A0. */
2723 case riscv_arg_info::location::by_ref
:
2727 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2729 if (readbuf
!= nullptr)
2730 read_memory (addr
, readbuf
, info
.length
);
2731 if (writebuf
!= nullptr)
2732 write_memory (addr
, writebuf
, info
.length
);
2736 case riscv_arg_info::location::on_stack
:
2738 error (_("invalid argument location"));
2742 /* This completes the cast from abi type back to the declared type
2743 in the case that we are reading from the machine. See the
2744 comment at the head of this block for more details. */
2745 if (readbuf
!= nullptr)
2747 struct value
*arg_val
= value_cast (arg_type
, abi_val
);
2748 memcpy (old_readbuf
, value_contents_raw (arg_val
),
2749 TYPE_LENGTH (arg_type
));
2753 switch (info
.argloc
[0].loc_type
)
2755 case riscv_arg_info::location::in_reg
:
2756 return RETURN_VALUE_REGISTER_CONVENTION
;
2757 case riscv_arg_info::location::by_ref
:
2758 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2759 case riscv_arg_info::location::on_stack
:
2761 error (_("invalid argument location"));
2765 /* Implement the frame_align gdbarch method. */
2768 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2770 return align_down (addr
, 16);
2773 /* Generate, or return the cached frame cache for the RiscV frame
2776 static struct riscv_unwind_cache
*
2777 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2779 CORE_ADDR pc
, start_addr
;
2780 struct riscv_unwind_cache
*cache
;
2781 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2784 if ((*this_cache
) != NULL
)
2785 return (struct riscv_unwind_cache
*) *this_cache
;
2787 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
2788 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
2789 (*this_cache
) = cache
;
2791 /* Scan the prologue, filling in the cache. */
2792 start_addr
= get_frame_func (this_frame
);
2793 pc
= get_frame_pc (this_frame
);
2794 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
2796 /* We can now calculate the frame base address. */
2798 = (get_frame_register_signed (this_frame
, cache
->frame_base_reg
)
2799 + cache
->frame_base_offset
);
2800 if (riscv_debug_unwinder
)
2801 fprintf_unfiltered (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
2802 core_addr_to_string (cache
->frame_base
),
2803 gdbarch_register_name (gdbarch
,
2804 cache
->frame_base_reg
),
2805 cache
->frame_base_offset
);
2807 /* The prologue scanner sets the address of registers stored to the stack
2808 as the offset of that register from the frame base. The prologue
2809 scanner doesn't know the actual frame base value, and so is unable to
2810 compute the exact address. We do now know the frame base value, so
2811 update the address of registers stored to the stack. */
2812 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
2813 for (regno
= 0; regno
< numregs
; ++regno
)
2815 if (trad_frame_addr_p (cache
->regs
, regno
))
2816 cache
->regs
[regno
].addr
+= cache
->frame_base
;
2819 /* The previous $pc can be found wherever the $ra value can be found.
2820 The previous $ra value is gone, this would have been stored be the
2821 previous frame if required. */
2822 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
2823 trad_frame_set_unknown (cache
->regs
, RISCV_RA_REGNUM
);
2825 /* Build the frame id. */
2826 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
2828 /* The previous $sp value is the frame base value. */
2829 trad_frame_set_value (cache
->regs
, gdbarch_sp_regnum (gdbarch
),
2835 /* Implement the this_id callback for RiscV frame unwinder. */
2838 riscv_frame_this_id (struct frame_info
*this_frame
,
2839 void **prologue_cache
,
2840 struct frame_id
*this_id
)
2842 struct riscv_unwind_cache
*cache
;
2846 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2847 *this_id
= cache
->this_id
;
2849 catch (const gdb_exception_error
&ex
)
2851 /* Ignore errors, this leaves the frame id as the predefined outer
2852 frame id which terminates the backtrace at this point. */
2856 /* Implement the prev_register callback for RiscV frame unwinder. */
2858 static struct value
*
2859 riscv_frame_prev_register (struct frame_info
*this_frame
,
2860 void **prologue_cache
,
2863 struct riscv_unwind_cache
*cache
;
2865 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2866 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
2869 /* Structure defining the RiscV normal frame unwind functions. Since we
2870 are the fallback unwinder (DWARF unwinder is used first), we use the
2871 default frame sniffer, which always accepts the frame. */
2873 static const struct frame_unwind riscv_frame_unwind
=
2875 /*.type =*/ NORMAL_FRAME
,
2876 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2877 /*.this_id =*/ riscv_frame_this_id
,
2878 /*.prev_register =*/ riscv_frame_prev_register
,
2879 /*.unwind_data =*/ NULL
,
2880 /*.sniffer =*/ default_frame_sniffer
,
2881 /*.dealloc_cache =*/ NULL
,
2882 /*.prev_arch =*/ NULL
,
2885 /* Extract a set of required target features out of INFO, specifically the
2886 bfd being executed is examined to see what target features it requires.
2887 IF there is no current bfd, or the bfd doesn't indicate any useful
2888 features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
2890 static struct riscv_gdbarch_features
2891 riscv_features_from_gdbarch_info (const struct gdbarch_info info
)
2893 struct riscv_gdbarch_features features
;
2895 /* Now try to improve on the defaults by looking at the binary we are
2896 going to execute. We assume the user knows what they are doing and
2897 that the target will match the binary. Remember, this code path is
2898 only used at all if the target hasn't given us a description, so this
2899 is really a last ditched effort to do something sane before giving
2901 if (info
.abfd
!= NULL
2902 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2904 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2905 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2907 if (eclass
== ELFCLASS32
)
2909 else if (eclass
== ELFCLASS64
)
2912 internal_error (__FILE__
, __LINE__
,
2913 _("unknown ELF header class %d"), eclass
);
2915 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2917 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2922 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2924 if (binfo
->bits_per_word
== 32)
2926 else if (binfo
->bits_per_word
== 64)
2929 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2930 binfo
->bits_per_word
);
2936 /* Find a suitable default target description. Use the contents of INFO,
2937 specifically the bfd object being executed, to guide the selection of a
2938 suitable default target description. */
2940 static const struct target_desc
*
2941 riscv_find_default_target_description (const struct gdbarch_info info
)
2943 /* Extract desired feature set from INFO. */
2944 struct riscv_gdbarch_features features
2945 = riscv_features_from_gdbarch_info (info
);
2947 /* If the XLEN field is still 0 then we got nothing useful from INFO. In
2948 this case we fall back to a minimal useful target, 8-byte x-registers,
2949 with no floating point. */
2950 if (features
.xlen
== 0)
2953 /* Now build a target description based on the feature set. */
2954 return riscv_create_target_description (features
);
2957 /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
2958 is updated with the register numbers for each register as listed in
2959 REG_SET. If any register marked as required in REG_SET is not found in
2960 FEATURE then this function returns false, otherwise, it returns true. */
2963 riscv_check_tdesc_feature (struct tdesc_arch_data
*tdesc_data
,
2964 const struct tdesc_feature
*feature
,
2965 const struct riscv_register_feature
*reg_set
)
2967 for (const auto ®
: reg_set
->registers
)
2971 for (const char *name
: reg
.names
)
2974 tdesc_numbered_register (feature
, tdesc_data
, reg
.regnum
, name
);
2980 if (!found
&& reg
.required_p
)
2987 /* Add all the expected register sets into GDBARCH. */
2990 riscv_add_reggroups (struct gdbarch
*gdbarch
)
2992 /* Add predefined register groups. */
2993 reggroup_add (gdbarch
, all_reggroup
);
2994 reggroup_add (gdbarch
, save_reggroup
);
2995 reggroup_add (gdbarch
, restore_reggroup
);
2996 reggroup_add (gdbarch
, system_reggroup
);
2997 reggroup_add (gdbarch
, vector_reggroup
);
2998 reggroup_add (gdbarch
, general_reggroup
);
2999 reggroup_add (gdbarch
, float_reggroup
);
3001 /* Add RISC-V specific register groups. */
3002 reggroup_add (gdbarch
, csr_reggroup
);
3005 /* Create register aliases for all the alternative names that exist for
3006 registers in REG_SET. */
3009 riscv_setup_register_aliases (struct gdbarch
*gdbarch
,
3010 const struct riscv_register_feature
*reg_set
)
3012 for (auto ®
: reg_set
->registers
)
3014 /* The first item in the names list is the preferred name for the
3015 register, this is what RISCV_REGISTER_NAME returns, and so we
3016 don't need to create an alias with that name here. */
3017 for (int i
= 1; i
< reg
.names
.size (); ++i
)
3018 user_reg_add (gdbarch
, reg
.names
[i
], value_of_riscv_user_reg
,
3023 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3026 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3028 if (reg
< RISCV_DWARF_REGNUM_X31
)
3029 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3031 else if (reg
< RISCV_DWARF_REGNUM_F31
)
3032 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3037 /* Initialize the current architecture based on INFO. If possible,
3038 re-use an architecture from ARCHES, which is a list of
3039 architectures already created during this debugging session.
3041 Called e.g. at program startup, when reading a core file, and when
3042 reading a binary file. */
3044 static struct gdbarch
*
3045 riscv_gdbarch_init (struct gdbarch_info info
,
3046 struct gdbarch_list
*arches
)
3048 struct gdbarch
*gdbarch
;
3049 struct gdbarch_tdep
*tdep
;
3050 struct riscv_gdbarch_features features
;
3051 const struct target_desc
*tdesc
= info
.target_desc
;
3053 /* Ensure we always have a target description. */
3054 if (!tdesc_has_registers (tdesc
))
3055 tdesc
= riscv_find_default_target_description (info
);
3058 if (riscv_debug_gdbarch
)
3059 fprintf_unfiltered (gdb_stdlog
, "Have got a target description\n");
3061 const struct tdesc_feature
*feature_cpu
3062 = tdesc_find_feature (tdesc
, riscv_xreg_feature
.name
);
3063 const struct tdesc_feature
*feature_fpu
3064 = tdesc_find_feature (tdesc
, riscv_freg_feature
.name
);
3065 const struct tdesc_feature
*feature_virtual
3066 = tdesc_find_feature (tdesc
, riscv_virtual_feature
.name
);
3067 const struct tdesc_feature
*feature_csr
3068 = tdesc_find_feature (tdesc
, riscv_csr_feature
.name
);
3070 if (feature_cpu
== NULL
)
3073 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3075 bool valid_p
= riscv_check_tdesc_feature (tdesc_data
,
3077 &riscv_xreg_feature
);
3080 /* Check that all of the core cpu registers have the same bitsize. */
3081 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
3083 for (auto &tdesc_reg
: feature_cpu
->registers
)
3084 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
3086 if (riscv_debug_gdbarch
)
3089 "From target-description, xlen = %d\n", xlen_bitsize
);
3091 features
.xlen
= (xlen_bitsize
/ 8);
3094 if (feature_fpu
!= NULL
)
3096 valid_p
&= riscv_check_tdesc_feature (tdesc_data
, feature_fpu
,
3097 &riscv_freg_feature
);
3099 /* Search for the first floating point register (by any alias), to
3100 determine the bitsize. */
3102 const auto &fp0
= riscv_freg_feature
.registers
[0];
3104 for (const char *name
: fp0
.names
)
3106 if (tdesc_unnumbered_register (feature_fpu
, name
))
3108 bitsize
= tdesc_register_bitsize (feature_fpu
, name
);
3113 gdb_assert (bitsize
!= -1);
3114 features
.flen
= (bitsize
/ 8);
3116 if (riscv_debug_gdbarch
)
3119 "From target-description, flen = %d\n", bitsize
);
3125 if (riscv_debug_gdbarch
)
3128 "No FPU in target-description, assume soft-float ABI\n");
3131 if (feature_virtual
)
3132 riscv_check_tdesc_feature (tdesc_data
, feature_virtual
,
3133 &riscv_virtual_feature
);
3136 riscv_check_tdesc_feature (tdesc_data
, feature_csr
,
3137 &riscv_csr_feature
);
3141 if (riscv_debug_gdbarch
)
3142 fprintf_unfiltered (gdb_stdlog
, "Target description is not valid\n");
3143 tdesc_data_cleanup (tdesc_data
);
3147 /* Have a look at what the supplied (if any) bfd object requires of the
3148 target, then check that this matches with what the target is
3150 struct riscv_gdbarch_features abi_features
3151 = riscv_features_from_gdbarch_info (info
);
3152 /* In theory a binary compiled for RV32 could run on an RV64 target,
3153 however, this has not been tested in GDB yet, so for now we require
3154 that the requested xlen match the targets xlen. */
3155 if (abi_features
.xlen
!= 0 && abi_features
.xlen
!= features
.xlen
)
3156 error (_("bfd requires xlen %d, but target has xlen %d"),
3157 abi_features
.xlen
, features
.xlen
);
3158 /* We do support running binaries compiled for 32-bit float on targets
3159 with 64-bit float, so we only complain if the binary requires more
3160 than the target has available. */
3161 if (abi_features
.flen
> features
.flen
)
3162 error (_("bfd requires flen %d, but target has flen %d"),
3163 abi_features
.flen
, features
.flen
);
3165 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3166 features from the INFO object. In this case we assume that the xlen
3167 abi matches the hardware. */
3168 if (abi_features
.xlen
== 0)
3169 abi_features
.xlen
= features
.xlen
;
3171 /* Find a candidate among the list of pre-declared architectures. */
3172 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3174 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3176 /* Check that the feature set of the ARCHES matches the feature set
3177 we are looking for. If it doesn't then we can't reuse this
3179 struct gdbarch_tdep
*other_tdep
= gdbarch_tdep (arches
->gdbarch
);
3181 if (other_tdep
->isa_features
!= features
3182 || other_tdep
->abi_features
!= abi_features
)
3190 tdesc_data_cleanup (tdesc_data
);
3191 return arches
->gdbarch
;
3194 /* None found, so create a new architecture from the information provided. */
3195 tdep
= new (struct gdbarch_tdep
);
3196 gdbarch
= gdbarch_alloc (&info
, tdep
);
3197 tdep
->isa_features
= features
;
3198 tdep
->abi_features
= abi_features
;
3200 /* Target data types. */
3201 set_gdbarch_short_bit (gdbarch
, 16);
3202 set_gdbarch_int_bit (gdbarch
, 32);
3203 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3204 set_gdbarch_long_long_bit (gdbarch
, 64);
3205 set_gdbarch_float_bit (gdbarch
, 32);
3206 set_gdbarch_double_bit (gdbarch
, 64);
3207 set_gdbarch_long_double_bit (gdbarch
, 128);
3208 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3209 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3210 set_gdbarch_char_signed (gdbarch
, 0);
3211 set_gdbarch_type_align (gdbarch
, riscv_type_align
);
3213 /* Information about the target architecture. */
3214 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
3215 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3216 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3217 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3219 /* Functions to analyze frames. */
3220 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3221 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3222 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3224 /* Functions handling dummy frames. */
3225 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3226 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3227 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3229 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3231 dwarf2_append_unwinders (gdbarch
);
3232 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3234 /* Register architecture. */
3235 riscv_add_reggroups (gdbarch
);
3237 /* Internal <-> external register number maps. */
3238 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3240 /* We reserve all possible register numbers for the known registers.
3241 This means the target description mechanism will add any target
3242 specific registers after this number. This helps make debugging GDB
3243 just a little easier. */
3244 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3246 /* We don't have to provide the count of 0 here (its the default) but
3247 include this line to make it explicit that, right now, we don't have
3248 any pseudo registers on RISC-V. */
3249 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
3251 /* Some specific register numbers GDB likes to know about. */
3252 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3253 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3255 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3257 /* Finalise the target description registers. */
3258 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3260 /* Override the register type callback setup by the target description
3261 mechanism. This allows us to provide special type for floating point
3263 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3265 /* Override the register name callback setup by the target description
3266 mechanism. This allows us to force our preferred names for the
3267 registers, no matter what the target description called them. */
3268 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
3270 /* Override the register group callback setup by the target description
3271 mechanism. This allows us to force registers into the groups we
3272 want, ignoring what the target tells us. */
3273 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
3275 /* Create register aliases for alternative register names. */
3276 riscv_setup_register_aliases (gdbarch
, &riscv_xreg_feature
);
3277 if (riscv_has_fp_regs (gdbarch
))
3278 riscv_setup_register_aliases (gdbarch
, &riscv_freg_feature
);
3279 riscv_setup_register_aliases (gdbarch
, &riscv_csr_feature
);
3281 /* Hook in OS ABI-specific overrides, if they have been registered. */
3282 gdbarch_init_osabi (info
, gdbarch
);
3287 /* This decodes the current instruction and determines the address of the
3288 next instruction. */
3291 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
3293 struct gdbarch
*gdbarch
= regcache
->arch ();
3294 struct riscv_insn insn
;
3297 insn
.decode (gdbarch
, pc
);
3298 next_pc
= pc
+ insn
.length ();
3300 if (insn
.opcode () == riscv_insn::JAL
)
3301 next_pc
= pc
+ insn
.imm_signed ();
3302 else if (insn
.opcode () == riscv_insn::JALR
)
3305 regcache
->cooked_read (insn
.rs1 (), &source
);
3306 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
3308 else if (insn
.opcode () == riscv_insn::BEQ
)
3311 regcache
->cooked_read (insn
.rs1 (), &src1
);
3312 regcache
->cooked_read (insn
.rs2 (), &src2
);
3314 next_pc
= pc
+ insn
.imm_signed ();
3316 else if (insn
.opcode () == riscv_insn::BNE
)
3319 regcache
->cooked_read (insn
.rs1 (), &src1
);
3320 regcache
->cooked_read (insn
.rs2 (), &src2
);
3322 next_pc
= pc
+ insn
.imm_signed ();
3324 else if (insn
.opcode () == riscv_insn::BLT
)
3327 regcache
->cooked_read (insn
.rs1 (), &src1
);
3328 regcache
->cooked_read (insn
.rs2 (), &src2
);
3330 next_pc
= pc
+ insn
.imm_signed ();
3332 else if (insn
.opcode () == riscv_insn::BGE
)
3335 regcache
->cooked_read (insn
.rs1 (), &src1
);
3336 regcache
->cooked_read (insn
.rs2 (), &src2
);
3338 next_pc
= pc
+ insn
.imm_signed ();
3340 else if (insn
.opcode () == riscv_insn::BLTU
)
3342 ULONGEST src1
, src2
;
3343 regcache
->cooked_read (insn
.rs1 (), &src1
);
3344 regcache
->cooked_read (insn
.rs2 (), &src2
);
3346 next_pc
= pc
+ insn
.imm_signed ();
3348 else if (insn
.opcode () == riscv_insn::BGEU
)
3350 ULONGEST src1
, src2
;
3351 regcache
->cooked_read (insn
.rs1 (), &src1
);
3352 regcache
->cooked_read (insn
.rs2 (), &src2
);
3354 next_pc
= pc
+ insn
.imm_signed ();
3360 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3361 for the end of the sequence and put the breakpoint there. */
3364 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
3367 struct gdbarch
*gdbarch
= regcache
->arch ();
3368 struct riscv_insn insn
;
3369 CORE_ADDR cur_step_pc
= pc
;
3370 CORE_ADDR last_addr
= 0;
3372 /* First instruction has to be a load reserved. */
3373 insn
.decode (gdbarch
, cur_step_pc
);
3374 if (insn
.opcode () != riscv_insn::LR
)
3376 cur_step_pc
= cur_step_pc
+ insn
.length ();
3378 /* Next instruction should be branch to exit. */
3379 insn
.decode (gdbarch
, cur_step_pc
);
3380 if (insn
.opcode () != riscv_insn::BNE
)
3382 last_addr
= cur_step_pc
+ insn
.imm_signed ();
3383 cur_step_pc
= cur_step_pc
+ insn
.length ();
3385 /* Next instruction should be store conditional. */
3386 insn
.decode (gdbarch
, cur_step_pc
);
3387 if (insn
.opcode () != riscv_insn::SC
)
3389 cur_step_pc
= cur_step_pc
+ insn
.length ();
3391 /* Next instruction should be branch to start. */
3392 insn
.decode (gdbarch
, cur_step_pc
);
3393 if (insn
.opcode () != riscv_insn::BNE
)
3395 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
3397 cur_step_pc
= cur_step_pc
+ insn
.length ();
3399 /* We should now be at the end of the sequence. */
3400 if (cur_step_pc
!= last_addr
)
3403 *next_pc
= cur_step_pc
;
3407 /* This is called just before we want to resume the inferior, if we want to
3408 single-step it but there is no hardware or kernel single-step support. We
3409 find the target of the coming instruction and breakpoint it. */
3411 std::vector
<CORE_ADDR
>
3412 riscv_software_single_step (struct regcache
*regcache
)
3414 CORE_ADDR pc
, next_pc
;
3416 pc
= regcache_read_pc (regcache
);
3418 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
3421 next_pc
= riscv_next_pc (regcache
, pc
);
3426 /* Create RISC-V specific reggroups. */
3429 riscv_init_reggroups ()
3431 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
3435 _initialize_riscv_tdep (void)
3437 riscv_create_csr_aliases ();
3438 riscv_init_reggroups ();
3440 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
3442 /* Add root prefix command for all "set debug riscv" and "show debug
3444 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
3445 _("RISC-V specific debug commands."),
3446 &setdebugriscvcmdlist
, "set debug riscv ", 0,
3449 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
3450 _("RISC-V specific debug commands."),
3451 &showdebugriscvcmdlist
, "show debug riscv ", 0,
3454 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
3455 &riscv_debug_breakpoints
, _("\
3456 Set riscv breakpoint debugging."), _("\
3457 Show riscv breakpoint debugging."), _("\
3458 When non-zero, print debugging information for the riscv specific parts\n\
3459 of the breakpoint mechanism."),
3461 show_riscv_debug_variable
,
3462 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3464 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
3465 &riscv_debug_infcall
, _("\
3466 Set riscv inferior call debugging."), _("\
3467 Show riscv inferior call debugging."), _("\
3468 When non-zero, print debugging information for the riscv specific parts\n\
3469 of the inferior call mechanism."),
3471 show_riscv_debug_variable
,
3472 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3474 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
3475 &riscv_debug_unwinder
, _("\
3476 Set riscv stack unwinding debugging."), _("\
3477 Show riscv stack unwinding debugging."), _("\
3478 When non-zero, print debugging information for the riscv specific parts\n\
3479 of the stack unwinding mechanism."),
3481 show_riscv_debug_variable
,
3482 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3484 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
3485 &riscv_debug_gdbarch
, _("\
3486 Set riscv gdbarch initialisation debugging."), _("\
3487 Show riscv gdbarch initialisation debugging."), _("\
3488 When non-zero, print debugging information for the riscv gdbarch\n\
3489 initialisation process."),
3491 show_riscv_debug_variable
,
3492 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3494 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3495 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
3496 _("RISC-V specific commands."),
3497 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
3499 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
3500 _("RISC-V specific commands."),
3501 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
3504 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
3505 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
3506 &use_compressed_breakpoints
,
3508 Set debugger's use of compressed breakpoints."), _(" \
3509 Show debugger's use of compressed breakpoints."), _("\
3510 Debugging compressed code requires compressed breakpoints to be used. If\n\
3511 left to 'auto' then gdb will use them if the existing instruction is a\n\
3512 compressed instruction. If that doesn't give the correct behavior, then\n\
3513 this option can be used."),
3515 show_use_compressed_breakpoints
,