Include scoped_fd.h in debuginfod-support.h
[deliverable/binutils-gdb.git] / gdb / riscv-tdep.c
1 /* Target-dependent code for the RISC-V architecture, for GDB.
2
3 Copyright (C) 2018-2021 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "frame.h"
22 #include "inferior.h"
23 #include "symtab.h"
24 #include "value.h"
25 #include "gdbcmd.h"
26 #include "language.h"
27 #include "gdbcore.h"
28 #include "symfile.h"
29 #include "objfiles.h"
30 #include "gdbtypes.h"
31 #include "target.h"
32 #include "arch-utils.h"
33 #include "regcache.h"
34 #include "osabi.h"
35 #include "riscv-tdep.h"
36 #include "block.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
40 #include "elf-bfd.h"
41 #include "symcat.h"
42 #include "dis-asm.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
46 #include "infcall.h"
47 #include "floatformat.h"
48 #include "remote.h"
49 #include "target-descriptions.h"
50 #include "dwarf2/frame.h"
51 #include "user-regs.h"
52 #include "valprint.h"
53 #include "gdbsupport/common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
59 #include "riscv-ravenscar-thread.h"
60
61 /* The stack must be 16-byte aligned. */
62 #define SP_ALIGNMENT 16
63
64 /* The biggest alignment that the target supports. */
65 #define BIGGEST_ALIGNMENT 16
66
67 /* Define a series of is_XXX_insn functions to check if the value INSN
68 is an instance of instruction XXX. */
69 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
70 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 { \
72 return (insn & INSN_MASK) == INSN_MATCH; \
73 }
74 #include "opcode/riscv-opc.h"
75 #undef DECLARE_INSN
76
77 /* When this is set to non-zero debugging information about breakpoint
78 kinds will be printed. */
79
80 static unsigned int riscv_debug_breakpoints = 0;
81
82 /* When this is set to non-zero debugging information about inferior calls
83 will be printed. */
84
85 static unsigned int riscv_debug_infcall = 0;
86
87 /* When this is set to non-zero debugging information about stack unwinding
88 will be printed. */
89
90 static unsigned int riscv_debug_unwinder = 0;
91
92 /* When this is set to non-zero debugging information about gdbarch
93 initialisation will be printed. */
94
95 static unsigned int riscv_debug_gdbarch = 0;
96
97 /* The names of the RISC-V target description features. */
98 const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr";
99 static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu";
100 static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu";
101 static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual";
102
103 /* Cached information about a frame. */
104
105 struct riscv_unwind_cache
106 {
107 /* The register from which we can calculate the frame base. This is
108 usually $sp or $fp. */
109 int frame_base_reg;
110
111 /* The offset from the current value in register FRAME_BASE_REG to the
112 actual frame base address. */
113 int frame_base_offset;
114
115 /* Information about previous register values. */
116 trad_frame_saved_reg *regs;
117
118 /* The id for this frame. */
119 struct frame_id this_id;
120
121 /* The base (stack) address for this frame. This is the stack pointer
122 value on entry to this frame before any adjustments are made. */
123 CORE_ADDR frame_base;
124 };
125
126 /* RISC-V specific register group for CSRs. */
127
128 static reggroup *csr_reggroup = NULL;
129
130 /* Callback function for user_reg_add. */
131
132 static struct value *
133 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
134 {
135 const int *reg_p = (const int *) baton;
136 return value_of_register (*reg_p, frame);
137 }
138
139 /* Information about a register alias that needs to be set up for this
140 target. These are collected when the target's XML description is
141 analysed, and then processed later, once the gdbarch has been created. */
142
143 class riscv_pending_register_alias
144 {
145 public:
146 /* Constructor. */
147
148 riscv_pending_register_alias (const char *name, const void *baton)
149 : m_name (name),
150 m_baton (baton)
151 { /* Nothing. */ }
152
153 /* Convert this into a user register for GDBARCH. */
154
155 void create (struct gdbarch *gdbarch) const
156 {
157 user_reg_add (gdbarch, m_name, value_of_riscv_user_reg, m_baton);
158 }
159
160 private:
161 /* The name for this alias. */
162 const char *m_name;
163
164 /* The baton value for passing to user_reg_add. This must point to some
165 data that will live for at least as long as the gdbarch object to
166 which the user register is attached. */
167 const void *m_baton;
168 };
169
170 /* A set of registers that we expect to find in a tdesc_feature. These
171 are use in RISCV_GDBARCH_INIT when processing the target description. */
172
173 struct riscv_register_feature
174 {
175 explicit riscv_register_feature (const char *feature_name)
176 : m_feature_name (feature_name)
177 { /* Delete. */ }
178
179 riscv_register_feature () = delete;
180 DISABLE_COPY_AND_ASSIGN (riscv_register_feature);
181
182 /* Information for a single register. */
183 struct register_info
184 {
185 /* The GDB register number for this register. */
186 int regnum;
187
188 /* List of names for this register. The first name in this list is the
189 preferred name, the name GDB should use when describing this
190 register. */
191 std::vector<const char *> names;
192
193 /* Look in FEATURE for a register with a name from this classes names
194 list. If the register is found then register its number with
195 TDESC_DATA and add all its aliases to the ALIASES list.
196 PREFER_FIRST_NAME_P is used when deciding which aliases to create. */
197 bool check (struct tdesc_arch_data *tdesc_data,
198 const struct tdesc_feature *feature,
199 bool prefer_first_name_p,
200 std::vector<riscv_pending_register_alias> *aliases) const;
201 };
202
203 /* Return the name of this feature. */
204 const char *name () const
205 { return m_feature_name; }
206
207 protected:
208
209 /* Return a target description feature extracted from TDESC for this
210 register feature. Will return nullptr if there is no feature in TDESC
211 with the name M_FEATURE_NAME. */
212 const struct tdesc_feature *tdesc_feature (const struct target_desc *tdesc) const
213 {
214 return tdesc_find_feature (tdesc, name ());
215 }
216
217 /* List of all the registers that we expect that we might find in this
218 register set. */
219 std::vector<struct register_info> m_registers;
220
221 private:
222
223 /* The name for this feature. This is the name used to find this feature
224 within the target description. */
225 const char *m_feature_name;
226 };
227
228 /* See description in the class declaration above. */
229
230 bool
231 riscv_register_feature::register_info::check
232 (struct tdesc_arch_data *tdesc_data,
233 const struct tdesc_feature *feature,
234 bool prefer_first_name_p,
235 std::vector<riscv_pending_register_alias> *aliases) const
236 {
237 for (const char *name : this->names)
238 {
239 bool found = tdesc_numbered_register (feature, tdesc_data,
240 this->regnum, name);
241 if (found)
242 {
243 /* We know that the target description mentions this
244 register. In RISCV_REGISTER_NAME we ensure that GDB
245 always uses the first name for each register, so here we
246 add aliases for all of the remaining names. */
247 int start_index = prefer_first_name_p ? 1 : 0;
248 for (int i = start_index; i < this->names.size (); ++i)
249 {
250 const char *alias = this->names[i];
251 if (alias == name && !prefer_first_name_p)
252 continue;
253 aliases->emplace_back (alias, (void *) &this->regnum);
254 }
255 return true;
256 }
257 }
258 return false;
259 }
260
261 /* Class representing the x-registers feature set. */
262
263 struct riscv_xreg_feature : public riscv_register_feature
264 {
265 riscv_xreg_feature ()
266 : riscv_register_feature (riscv_feature_name_cpu)
267 {
268 m_registers = {
269 { RISCV_ZERO_REGNUM + 0, { "zero", "x0" } },
270 { RISCV_ZERO_REGNUM + 1, { "ra", "x1" } },
271 { RISCV_ZERO_REGNUM + 2, { "sp", "x2" } },
272 { RISCV_ZERO_REGNUM + 3, { "gp", "x3" } },
273 { RISCV_ZERO_REGNUM + 4, { "tp", "x4" } },
274 { RISCV_ZERO_REGNUM + 5, { "t0", "x5" } },
275 { RISCV_ZERO_REGNUM + 6, { "t1", "x6" } },
276 { RISCV_ZERO_REGNUM + 7, { "t2", "x7" } },
277 { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" } },
278 { RISCV_ZERO_REGNUM + 9, { "s1", "x9" } },
279 { RISCV_ZERO_REGNUM + 10, { "a0", "x10" } },
280 { RISCV_ZERO_REGNUM + 11, { "a1", "x11" } },
281 { RISCV_ZERO_REGNUM + 12, { "a2", "x12" } },
282 { RISCV_ZERO_REGNUM + 13, { "a3", "x13" } },
283 { RISCV_ZERO_REGNUM + 14, { "a4", "x14" } },
284 { RISCV_ZERO_REGNUM + 15, { "a5", "x15" } },
285 { RISCV_ZERO_REGNUM + 16, { "a6", "x16" } },
286 { RISCV_ZERO_REGNUM + 17, { "a7", "x17" } },
287 { RISCV_ZERO_REGNUM + 18, { "s2", "x18" } },
288 { RISCV_ZERO_REGNUM + 19, { "s3", "x19" } },
289 { RISCV_ZERO_REGNUM + 20, { "s4", "x20" } },
290 { RISCV_ZERO_REGNUM + 21, { "s5", "x21" } },
291 { RISCV_ZERO_REGNUM + 22, { "s6", "x22" } },
292 { RISCV_ZERO_REGNUM + 23, { "s7", "x23" } },
293 { RISCV_ZERO_REGNUM + 24, { "s8", "x24" } },
294 { RISCV_ZERO_REGNUM + 25, { "s9", "x25" } },
295 { RISCV_ZERO_REGNUM + 26, { "s10", "x26" } },
296 { RISCV_ZERO_REGNUM + 27, { "s11", "x27" } },
297 { RISCV_ZERO_REGNUM + 28, { "t3", "x28" } },
298 { RISCV_ZERO_REGNUM + 29, { "t4", "x29" } },
299 { RISCV_ZERO_REGNUM + 30, { "t5", "x30" } },
300 { RISCV_ZERO_REGNUM + 31, { "t6", "x31" } },
301 { RISCV_ZERO_REGNUM + 32, { "pc" } }
302 };
303 }
304
305 /* Return the preferred name for the register with gdb register number
306 REGNUM, which must be in the inclusive range RISCV_ZERO_REGNUM to
307 RISCV_PC_REGNUM. */
308 const char *register_name (int regnum) const
309 {
310 gdb_assert (regnum >= RISCV_ZERO_REGNUM && regnum <= m_registers.size ());
311 return m_registers[regnum].names[0];
312 }
313
314 /* Check this feature within TDESC, record the registers from this
315 feature into TDESC_DATA and update ALIASES and FEATURES. */
316 bool check (const struct target_desc *tdesc,
317 struct tdesc_arch_data *tdesc_data,
318 std::vector<riscv_pending_register_alias> *aliases,
319 struct riscv_gdbarch_features *features) const
320 {
321 const struct tdesc_feature *feature_cpu = tdesc_feature (tdesc);
322
323 if (feature_cpu == nullptr)
324 return false;
325
326 bool seen_an_optional_reg_p = false;
327 for (const auto &reg : m_registers)
328 {
329 bool found = reg.check (tdesc_data, feature_cpu, true, aliases);
330
331 bool is_optional_reg_p = (reg.regnum >= RISCV_ZERO_REGNUM + 16
332 && reg.regnum < RISCV_ZERO_REGNUM + 32);
333
334 if (!found && (!is_optional_reg_p || seen_an_optional_reg_p))
335 return false;
336 else if (found && is_optional_reg_p)
337 seen_an_optional_reg_p = true;
338 }
339
340 /* Check that all of the core cpu registers have the same bitsize. */
341 int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc");
342
343 bool valid_p = true;
344 for (auto &tdesc_reg : feature_cpu->registers)
345 valid_p &= (tdesc_reg->bitsize == xlen_bitsize);
346
347 features->xlen = (xlen_bitsize / 8);
348 features->embedded = !seen_an_optional_reg_p;
349
350 return valid_p;
351 }
352 };
353
354 /* An instance of the x-register feature set. */
355
356 static const struct riscv_xreg_feature riscv_xreg_feature;
357
358 /* Class representing the f-registers feature set. */
359
360 struct riscv_freg_feature : public riscv_register_feature
361 {
362 riscv_freg_feature ()
363 : riscv_register_feature (riscv_feature_name_fpu)
364 {
365 m_registers = {
366 { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" } },
367 { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" } },
368 { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" } },
369 { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" } },
370 { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" } },
371 { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" } },
372 { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" } },
373 { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" } },
374 { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" } },
375 { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" } },
376 { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" } },
377 { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" } },
378 { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" } },
379 { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" } },
380 { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" } },
381 { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" } },
382 { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" } },
383 { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" } },
384 { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" } },
385 { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" } },
386 { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" } },
387 { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" } },
388 { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" } },
389 { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" } },
390 { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" } },
391 { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" } },
392 { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" } },
393 { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" } },
394 { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" } },
395 { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" } },
396 { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" } },
397 { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" } },
398 { RISCV_CSR_FFLAGS_REGNUM, { "fflags", "csr1" } },
399 { RISCV_CSR_FRM_REGNUM, { "frm", "csr2" } },
400 { RISCV_CSR_FCSR_REGNUM, { "fcsr", "csr3" } },
401 };
402 }
403
404 /* Return the preferred name for the register with gdb register number
405 REGNUM, which must be in the inclusive range RISCV_FIRST_FP_REGNUM to
406 RISCV_LAST_FP_REGNUM. */
407 const char *register_name (int regnum) const
408 {
409 gdb_static_assert (RISCV_LAST_FP_REGNUM == RISCV_FIRST_FP_REGNUM + 31);
410 gdb_assert (regnum >= RISCV_FIRST_FP_REGNUM
411 && regnum <= RISCV_LAST_FP_REGNUM);
412 regnum -= RISCV_FIRST_FP_REGNUM;
413 return m_registers[regnum].names[0];
414 }
415
416 /* Check this feature within TDESC, record the registers from this
417 feature into TDESC_DATA and update ALIASES and FEATURES. */
418 bool check (const struct target_desc *tdesc,
419 struct tdesc_arch_data *tdesc_data,
420 std::vector<riscv_pending_register_alias> *aliases,
421 struct riscv_gdbarch_features *features) const
422 {
423 const struct tdesc_feature *feature_fpu = tdesc_feature (tdesc);
424
425 /* It's fine if this feature is missing. Update the architecture
426 feature set and return. */
427 if (feature_fpu == nullptr)
428 {
429 features->flen = 0;
430 return true;
431 }
432
433 /* Check all of the floating pointer registers are present. We also
434 check that the floating point CSRs are present too, though if these
435 are missing this is not fatal. */
436 for (const auto &reg : m_registers)
437 {
438 bool found = reg.check (tdesc_data, feature_fpu, true, aliases);
439
440 bool is_ctrl_reg_p = reg.regnum > RISCV_LAST_FP_REGNUM;
441
442 if (!found && !is_ctrl_reg_p)
443 return false;
444 }
445
446 /* Look through all of the floating point registers (not the FP CSRs
447 though), and check they all have the same bitsize. Use this bitsize
448 to update the feature set for this gdbarch. */
449 int fp_bitsize = -1;
450 for (const auto &reg : m_registers)
451 {
452 /* Stop once we get to the CSRs which are at the end of the
453 M_REGISTERS list. */
454 if (reg.regnum > RISCV_LAST_FP_REGNUM)
455 break;
456
457 int reg_bitsize = -1;
458 for (const char *name : reg.names)
459 {
460 if (tdesc_unnumbered_register (feature_fpu, name))
461 {
462 reg_bitsize = tdesc_register_bitsize (feature_fpu, name);
463 break;
464 }
465 }
466 gdb_assert (reg_bitsize != -1);
467 if (fp_bitsize == -1)
468 fp_bitsize = reg_bitsize;
469 else if (fp_bitsize != reg_bitsize)
470 return false;
471 }
472
473 features->flen = (fp_bitsize / 8);
474 return true;
475 }
476 };
477
478 /* An instance of the f-register feature set. */
479
480 static const struct riscv_freg_feature riscv_freg_feature;
481
482 /* Class representing the virtual registers. These are not physical
483 registers on the hardware, but might be available from the target.
484 These are not pseudo registers, reading these really does result in a
485 register read from the target, it is just that there might not be a
486 physical register backing the result. */
487
488 struct riscv_virtual_feature : public riscv_register_feature
489 {
490 riscv_virtual_feature ()
491 : riscv_register_feature (riscv_feature_name_virtual)
492 {
493 m_registers = {
494 { RISCV_PRIV_REGNUM, { "priv" } }
495 };
496 }
497
498 bool check (const struct target_desc *tdesc,
499 struct tdesc_arch_data *tdesc_data,
500 std::vector<riscv_pending_register_alias> *aliases,
501 struct riscv_gdbarch_features *features) const
502 {
503 const struct tdesc_feature *feature_virtual = tdesc_feature (tdesc);
504
505 /* It's fine if this feature is missing. */
506 if (feature_virtual == nullptr)
507 return true;
508
509 /* We don't check the return value from the call to check here, all the
510 registers in this feature are optional. */
511 for (const auto &reg : m_registers)
512 reg.check (tdesc_data, feature_virtual, true, aliases);
513
514 return true;
515 }
516 };
517
518 /* An instance of the virtual register feature. */
519
520 static const struct riscv_virtual_feature riscv_virtual_feature;
521
522 /* Class representing the CSR feature. */
523
524 struct riscv_csr_feature : public riscv_register_feature
525 {
526 riscv_csr_feature ()
527 : riscv_register_feature (riscv_feature_name_csr)
528 {
529 m_registers = {
530 #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
531 { RISCV_ ## VALUE ## _REGNUM, { # NAME } },
532 #include "opcode/riscv-opc.h"
533 #undef DECLARE_CSR
534 };
535 riscv_create_csr_aliases ();
536 }
537
538 bool check (const struct target_desc *tdesc,
539 struct tdesc_arch_data *tdesc_data,
540 std::vector<riscv_pending_register_alias> *aliases,
541 struct riscv_gdbarch_features *features) const
542 {
543 const struct tdesc_feature *feature_csr = tdesc_feature (tdesc);
544
545 /* It's fine if this feature is missing. */
546 if (feature_csr == nullptr)
547 return true;
548
549 /* We don't check the return value from the call to check here, all the
550 registers in this feature are optional. */
551 for (const auto &reg : m_registers)
552 reg.check (tdesc_data, feature_csr, true, aliases);
553
554 return true;
555 }
556
557 private:
558
559 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
560 to the name list for each register. */
561
562 void
563 riscv_create_csr_aliases ()
564 {
565 for (auto &reg : m_registers)
566 {
567 int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
568 const char *alias = xstrprintf ("csr%d", csr_num);
569 reg.names.push_back (alias);
570 }
571 }
572 };
573
574 /* An instance of the csr register feature. */
575
576 static const struct riscv_csr_feature riscv_csr_feature;
577
578 /* Controls whether we place compressed breakpoints or not. When in auto
579 mode GDB tries to determine if the target supports compressed
580 breakpoints, and uses them if it does. */
581
582 static enum auto_boolean use_compressed_breakpoints;
583
584 /* The show callback for 'show riscv use-compressed-breakpoints'. */
585
586 static void
587 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
588 struct cmd_list_element *c,
589 const char *value)
590 {
591 fprintf_filtered (file,
592 _("Debugger's use of compressed breakpoints is set "
593 "to %s.\n"), value);
594 }
595
596 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
597
598 static struct cmd_list_element *setriscvcmdlist = NULL;
599 static struct cmd_list_element *showriscvcmdlist = NULL;
600
601 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
602
603 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
604 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
605
606 /* The show callback for all 'show debug riscv VARNAME' variables. */
607
608 static void
609 show_riscv_debug_variable (struct ui_file *file, int from_tty,
610 struct cmd_list_element *c,
611 const char *value)
612 {
613 fprintf_filtered (file,
614 _("RiscV debug variable `%s' is set to: %s\n"),
615 c->name, value);
616 }
617
618 /* See riscv-tdep.h. */
619
620 int
621 riscv_isa_xlen (struct gdbarch *gdbarch)
622 {
623 return gdbarch_tdep (gdbarch)->isa_features.xlen;
624 }
625
626 /* See riscv-tdep.h. */
627
628 int
629 riscv_abi_xlen (struct gdbarch *gdbarch)
630 {
631 return gdbarch_tdep (gdbarch)->abi_features.xlen;
632 }
633
634 /* See riscv-tdep.h. */
635
636 int
637 riscv_isa_flen (struct gdbarch *gdbarch)
638 {
639 return gdbarch_tdep (gdbarch)->isa_features.flen;
640 }
641
642 /* See riscv-tdep.h. */
643
644 int
645 riscv_abi_flen (struct gdbarch *gdbarch)
646 {
647 return gdbarch_tdep (gdbarch)->abi_features.flen;
648 }
649
650 /* See riscv-tdep.h. */
651
652 bool
653 riscv_abi_embedded (struct gdbarch *gdbarch)
654 {
655 return gdbarch_tdep (gdbarch)->abi_features.embedded;
656 }
657
658 /* Return true if the target for GDBARCH has floating point hardware. */
659
660 static bool
661 riscv_has_fp_regs (struct gdbarch *gdbarch)
662 {
663 return (riscv_isa_flen (gdbarch) > 0);
664 }
665
666 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
667
668 static bool
669 riscv_has_fp_abi (struct gdbarch *gdbarch)
670 {
671 return gdbarch_tdep (gdbarch)->abi_features.flen > 0;
672 }
673
674 /* Return true if REGNO is a floating pointer register. */
675
676 static bool
677 riscv_is_fp_regno_p (int regno)
678 {
679 return (regno >= RISCV_FIRST_FP_REGNUM
680 && regno <= RISCV_LAST_FP_REGNUM);
681 }
682
683 /* Implement the breakpoint_kind_from_pc gdbarch method. */
684
685 static int
686 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
687 {
688 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
689 {
690 bool unaligned_p = false;
691 gdb_byte buf[1];
692
693 /* Some targets don't support unaligned reads. The address can only
694 be unaligned if the C extension is supported. So it is safe to
695 use a compressed breakpoint in this case. */
696 if (*pcptr & 0x2)
697 unaligned_p = true;
698 else
699 {
700 /* Read the opcode byte to determine the instruction length. If
701 the read fails this may be because we tried to set the
702 breakpoint at an invalid address, in this case we provide a
703 fake result which will give a breakpoint length of 4.
704 Hopefully when we try to actually insert the breakpoint we
705 will see a failure then too which will be reported to the
706 user. */
707 if (target_read_code (*pcptr, buf, 1) == -1)
708 buf[0] = 0;
709 read_code (*pcptr, buf, 1);
710 }
711
712 if (riscv_debug_breakpoints)
713 {
714 const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
715 ? "C.EBREAK" : "EBREAK");
716
717 fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ",
718 bp, paddress (gdbarch, *pcptr));
719 if (unaligned_p)
720 fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n");
721 else
722 fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n",
723 riscv_insn_length (buf[0]));
724 }
725 if (unaligned_p || riscv_insn_length (buf[0]) == 2)
726 return 2;
727 else
728 return 4;
729 }
730 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
731 return 2;
732 else
733 return 4;
734 }
735
736 /* Implement the sw_breakpoint_from_kind gdbarch method. */
737
738 static const gdb_byte *
739 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
740 {
741 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
742 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
743
744 *size = kind;
745 switch (kind)
746 {
747 case 2:
748 return c_ebreak;
749 case 4:
750 return ebreak;
751 default:
752 gdb_assert_not_reached (_("unhandled breakpoint kind"));
753 }
754 }
755
756 /* Implement the register_name gdbarch method. This is used instead of
757 the function supplied by calling TDESC_USE_REGISTERS so that we can
758 ensure the preferred names are offered for x-regs and f-regs. */
759
760 static const char *
761 riscv_register_name (struct gdbarch *gdbarch, int regnum)
762 {
763 /* Lookup the name through the target description. If we get back NULL
764 then this is an unknown register. If we do get a name back then we
765 look up the registers preferred name below. */
766 const char *name = tdesc_register_name (gdbarch, regnum);
767 if (name == NULL || name[0] == '\0')
768 return NULL;
769
770 /* We want GDB to use the ABI names for registers even if the target
771 gives us a target description with the architectural name. For
772 example we want to see 'ra' instead of 'x1' whatever the target
773 description called it. */
774 if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM)
775 return riscv_xreg_feature.register_name (regnum);
776
777 /* Like with the x-regs we prefer the abi names for the floating point
778 registers. */
779 if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
780 {
781 if (riscv_has_fp_regs (gdbarch))
782 return riscv_freg_feature.register_name (regnum);
783 else
784 return NULL;
785 }
786
787 /* Some targets (QEMU) are reporting these three registers twice, once
788 in the FPU feature, and once in the CSR feature. Both of these read
789 the same underlying state inside the target, but naming the register
790 twice in the target description results in GDB having two registers
791 with the same name, only one of which can ever be accessed, but both
792 will show up in 'info register all'. Unless, we identify the
793 duplicate copies of these registers (in riscv_tdesc_unknown_reg) and
794 then hide the registers here by giving them no name. */
795 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
796 if (tdep->duplicate_fflags_regnum == regnum)
797 return NULL;
798 if (tdep->duplicate_frm_regnum == regnum)
799 return NULL;
800 if (tdep->duplicate_fcsr_regnum == regnum)
801 return NULL;
802
803 /* The remaining registers are different. For all other registers on the
804 machine we prefer to see the names that the target description
805 provides. This is particularly important for CSRs which might be
806 renamed over time. If GDB keeps track of the "latest" name, but a
807 particular target provides an older name then we don't want to force
808 users to see the newer name in register output.
809
810 The other case that reaches here are any registers that the target
811 provided that GDB is completely unaware of. For these we have no
812 choice but to accept the target description name.
813
814 Just accept whatever name TDESC_REGISTER_NAME returned. */
815 return name;
816 }
817
818 /* Construct a type for 64-bit FP registers. */
819
820 static struct type *
821 riscv_fpreg_d_type (struct gdbarch *gdbarch)
822 {
823 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
824
825 if (tdep->riscv_fpreg_d_type == nullptr)
826 {
827 const struct builtin_type *bt = builtin_type (gdbarch);
828
829 /* The type we're building is this: */
830 #if 0
831 union __gdb_builtin_type_fpreg_d
832 {
833 float f;
834 double d;
835 };
836 #endif
837
838 struct type *t;
839
840 t = arch_composite_type (gdbarch,
841 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
842 append_composite_type_field (t, "float", bt->builtin_float);
843 append_composite_type_field (t, "double", bt->builtin_double);
844 t->set_is_vector (true);
845 t->set_name ("builtin_type_fpreg_d");
846 tdep->riscv_fpreg_d_type = t;
847 }
848
849 return tdep->riscv_fpreg_d_type;
850 }
851
852 /* Implement the register_type gdbarch method. This is installed as an
853 for the override setup by TDESC_USE_REGISTERS, for most registers we
854 delegate the type choice to the target description, but for a few
855 registers we try to improve the types if the target description has
856 taken a simplistic approach. */
857
858 static struct type *
859 riscv_register_type (struct gdbarch *gdbarch, int regnum)
860 {
861 struct type *type = tdesc_register_type (gdbarch, regnum);
862 int xlen = riscv_isa_xlen (gdbarch);
863
864 /* We want to perform some specific type "fixes" in cases where we feel
865 that we really can do better than the target description. For all
866 other cases we just return what the target description says. */
867 if (riscv_is_fp_regno_p (regnum))
868 {
869 /* This spots the case for RV64 where the double is defined as
870 either 'ieee_double' or 'float' (which is the generic name that
871 converts to 'double' on 64-bit). In these cases its better to
872 present the registers using a union type. */
873 int flen = riscv_isa_flen (gdbarch);
874 if (flen == 8
875 && type->code () == TYPE_CODE_FLT
876 && TYPE_LENGTH (type) == flen
877 && (strcmp (type->name (), "builtin_type_ieee_double") == 0
878 || strcmp (type->name (), "double") == 0))
879 type = riscv_fpreg_d_type (gdbarch);
880 }
881
882 if ((regnum == gdbarch_pc_regnum (gdbarch)
883 || regnum == RISCV_RA_REGNUM
884 || regnum == RISCV_FP_REGNUM
885 || regnum == RISCV_SP_REGNUM
886 || regnum == RISCV_GP_REGNUM
887 || regnum == RISCV_TP_REGNUM)
888 && type->code () == TYPE_CODE_INT
889 && TYPE_LENGTH (type) == xlen)
890 {
891 /* This spots the case where some interesting registers are defined
892 as simple integers of the expected size, we force these registers
893 to be pointers as we believe that is more useful. */
894 if (regnum == gdbarch_pc_regnum (gdbarch)
895 || regnum == RISCV_RA_REGNUM)
896 type = builtin_type (gdbarch)->builtin_func_ptr;
897 else if (regnum == RISCV_FP_REGNUM
898 || regnum == RISCV_SP_REGNUM
899 || regnum == RISCV_GP_REGNUM
900 || regnum == RISCV_TP_REGNUM)
901 type = builtin_type (gdbarch)->builtin_data_ptr;
902 }
903
904 return type;
905 }
906
907 /* Helper for riscv_print_registers_info, prints info for a single register
908 REGNUM. */
909
910 static void
911 riscv_print_one_register_info (struct gdbarch *gdbarch,
912 struct ui_file *file,
913 struct frame_info *frame,
914 int regnum)
915 {
916 const char *name = gdbarch_register_name (gdbarch, regnum);
917 struct value *val;
918 struct type *regtype;
919 int print_raw_format;
920 enum tab_stops { value_column_1 = 15 };
921
922 fputs_filtered (name, file);
923 print_spaces_filtered (value_column_1 - strlen (name), file);
924
925 try
926 {
927 val = value_of_register (regnum, frame);
928 regtype = value_type (val);
929 }
930 catch (const gdb_exception_error &ex)
931 {
932 /* Handle failure to read a register without interrupting the entire
933 'info registers' flow. */
934 fprintf_filtered (file, "%s\n", ex.what ());
935 return;
936 }
937
938 print_raw_format = (value_entirely_available (val)
939 && !value_optimized_out (val));
940
941 if (regtype->code () == TYPE_CODE_FLT
942 || (regtype->code () == TYPE_CODE_UNION
943 && regtype->num_fields () == 2
944 && regtype->field (0).type ()->code () == TYPE_CODE_FLT
945 && regtype->field (1).type ()->code () == TYPE_CODE_FLT)
946 || (regtype->code () == TYPE_CODE_UNION
947 && regtype->num_fields () == 3
948 && regtype->field (0).type ()->code () == TYPE_CODE_FLT
949 && regtype->field (1).type ()->code () == TYPE_CODE_FLT
950 && regtype->field (2).type ()->code () == TYPE_CODE_FLT))
951 {
952 struct value_print_options opts;
953 const gdb_byte *valaddr = value_contents_for_printing (val);
954 enum bfd_endian byte_order = type_byte_order (regtype);
955
956 get_user_print_options (&opts);
957 opts.deref_ref = 1;
958
959 common_val_print (val, file, 0, &opts, current_language);
960
961 if (print_raw_format)
962 {
963 fprintf_filtered (file, "\t(raw ");
964 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
965 true);
966 fprintf_filtered (file, ")");
967 }
968 }
969 else
970 {
971 struct value_print_options opts;
972
973 /* Print the register in hex. */
974 get_formatted_print_options (&opts, 'x');
975 opts.deref_ref = 1;
976 common_val_print (val, file, 0, &opts, current_language);
977
978 if (print_raw_format)
979 {
980 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
981 {
982 LONGEST d;
983 int size = register_size (gdbarch, regnum);
984 unsigned xlen;
985
986 /* The SD field is always in the upper bit of MSTATUS, regardless
987 of the number of bits in MSTATUS. */
988 d = value_as_long (val);
989 xlen = size * 8;
990 fprintf_filtered (file,
991 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
992 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
993 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
994 (int) ((d >> (xlen - 1)) & 0x1),
995 (int) ((d >> 24) & 0x1f),
996 (int) ((d >> 19) & 0x1),
997 (int) ((d >> 18) & 0x1),
998 (int) ((d >> 17) & 0x1),
999 (int) ((d >> 15) & 0x3),
1000 (int) ((d >> 13) & 0x3),
1001 (int) ((d >> 11) & 0x3),
1002 (int) ((d >> 9) & 0x3),
1003 (int) ((d >> 8) & 0x1),
1004 (int) ((d >> 7) & 0x1),
1005 (int) ((d >> 6) & 0x1),
1006 (int) ((d >> 5) & 0x1),
1007 (int) ((d >> 4) & 0x1),
1008 (int) ((d >> 3) & 0x1),
1009 (int) ((d >> 2) & 0x1),
1010 (int) ((d >> 1) & 0x1),
1011 (int) ((d >> 0) & 0x1));
1012 }
1013 else if (regnum == RISCV_CSR_MISA_REGNUM)
1014 {
1015 int base;
1016 unsigned xlen, i;
1017 LONGEST d;
1018 int size = register_size (gdbarch, regnum);
1019
1020 /* The MXL field is always in the upper two bits of MISA,
1021 regardless of the number of bits in MISA. Mask out other
1022 bits to ensure we have a positive value. */
1023 d = value_as_long (val);
1024 base = (d >> ((size * 8) - 2)) & 0x3;
1025 xlen = 16;
1026
1027 for (; base > 0; base--)
1028 xlen *= 2;
1029 fprintf_filtered (file, "\tRV%d", xlen);
1030
1031 for (i = 0; i < 26; i++)
1032 {
1033 if (d & (1 << i))
1034 fprintf_filtered (file, "%c", 'A' + i);
1035 }
1036 }
1037 else if (regnum == RISCV_CSR_FCSR_REGNUM
1038 || regnum == RISCV_CSR_FFLAGS_REGNUM
1039 || regnum == RISCV_CSR_FRM_REGNUM)
1040 {
1041 LONGEST d;
1042
1043 d = value_as_long (val);
1044
1045 fprintf_filtered (file, "\t");
1046 if (regnum != RISCV_CSR_FRM_REGNUM)
1047 fprintf_filtered (file,
1048 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
1049 (int) ((d >> 5) & 0x7),
1050 (int) ((d >> 4) & 0x1),
1051 (int) ((d >> 3) & 0x1),
1052 (int) ((d >> 2) & 0x1),
1053 (int) ((d >> 1) & 0x1),
1054 (int) ((d >> 0) & 0x1));
1055
1056 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
1057 {
1058 static const char * const sfrm[] =
1059 {
1060 "RNE (round to nearest; ties to even)",
1061 "RTZ (Round towards zero)",
1062 "RDN (Round down towards -INF)",
1063 "RUP (Round up towards +INF)",
1064 "RMM (Round to nearest; ties to max magnitude)",
1065 "INVALID[5]",
1066 "INVALID[6]",
1067 "dynamic rounding mode",
1068 };
1069 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
1070 ? (d >> 5) : d) & 0x3;
1071
1072 fprintf_filtered (file, "%sFRM:%i [%s]",
1073 (regnum == RISCV_CSR_FCSR_REGNUM
1074 ? " " : ""),
1075 frm, sfrm[frm]);
1076 }
1077 }
1078 else if (regnum == RISCV_PRIV_REGNUM)
1079 {
1080 LONGEST d;
1081 uint8_t priv;
1082
1083 d = value_as_long (val);
1084 priv = d & 0xff;
1085
1086 if (priv < 4)
1087 {
1088 static const char * const sprv[] =
1089 {
1090 "User/Application",
1091 "Supervisor",
1092 "Hypervisor",
1093 "Machine"
1094 };
1095 fprintf_filtered (file, "\tprv:%d [%s]",
1096 priv, sprv[priv]);
1097 }
1098 else
1099 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
1100 }
1101 else
1102 {
1103 /* If not a vector register, print it also according to its
1104 natural format. */
1105 if (regtype->is_vector () == 0)
1106 {
1107 get_user_print_options (&opts);
1108 opts.deref_ref = 1;
1109 fprintf_filtered (file, "\t");
1110 common_val_print (val, file, 0, &opts, current_language);
1111 }
1112 }
1113 }
1114 }
1115 fprintf_filtered (file, "\n");
1116 }
1117
1118 /* Return true if REGNUM is a valid CSR register. The CSR register space
1119 is sparsely populated, so not every number is a named CSR. */
1120
1121 static bool
1122 riscv_is_regnum_a_named_csr (int regnum)
1123 {
1124 gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
1125 && regnum <= RISCV_LAST_CSR_REGNUM);
1126
1127 switch (regnum)
1128 {
1129 #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
1130 #include "opcode/riscv-opc.h"
1131 #undef DECLARE_CSR
1132 return true;
1133
1134 default:
1135 return false;
1136 }
1137 }
1138
1139 /* Return true if REGNUM is an unknown CSR identified in
1140 riscv_tdesc_unknown_reg for GDBARCH. */
1141
1142 static bool
1143 riscv_is_unknown_csr (struct gdbarch *gdbarch, int regnum)
1144 {
1145 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1146 return (regnum >= tdep->unknown_csrs_first_regnum
1147 && regnum < (tdep->unknown_csrs_first_regnum
1148 + tdep->unknown_csrs_count));
1149 }
1150
1151 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
1152 of REGGROUP? */
1153
1154 static int
1155 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1156 struct reggroup *reggroup)
1157 {
1158 /* Used by 'info registers' and 'info registers <groupname>'. */
1159
1160 if (gdbarch_register_name (gdbarch, regnum) == NULL
1161 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
1162 return 0;
1163
1164 if (regnum > RISCV_LAST_REGNUM)
1165 {
1166 /* Any extra registers from the CSR tdesc_feature (identified in
1167 riscv_tdesc_unknown_reg) are removed from the save/restore groups
1168 as some targets (QEMU) report CSRs which then can't be read and
1169 having unreadable registers in the save/restore group breaks
1170 things like inferior calls.
1171
1172 The unknown CSRs are also removed from the general group, and
1173 added into both the csr and system group. This is inline with the
1174 known CSRs (see below). */
1175 if (riscv_is_unknown_csr (gdbarch, regnum))
1176 {
1177 if (reggroup == restore_reggroup || reggroup == save_reggroup
1178 || reggroup == general_reggroup)
1179 return 0;
1180 else if (reggroup == system_reggroup || reggroup == csr_reggroup)
1181 return 1;
1182 }
1183
1184 /* This is some other unknown register from the target description.
1185 In this case we trust whatever the target description says about
1186 which groups this register should be in. */
1187 int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
1188 if (ret != -1)
1189 return ret;
1190
1191 return default_register_reggroup_p (gdbarch, regnum, reggroup);
1192 }
1193
1194 if (reggroup == all_reggroup)
1195 {
1196 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
1197 return 1;
1198 if (riscv_is_regnum_a_named_csr (regnum))
1199 return 1;
1200 return 0;
1201 }
1202 else if (reggroup == float_reggroup)
1203 return (riscv_is_fp_regno_p (regnum)
1204 || regnum == RISCV_CSR_FCSR_REGNUM
1205 || regnum == RISCV_CSR_FFLAGS_REGNUM
1206 || regnum == RISCV_CSR_FRM_REGNUM);
1207 else if (reggroup == general_reggroup)
1208 return regnum < RISCV_FIRST_FP_REGNUM;
1209 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
1210 {
1211 if (riscv_has_fp_regs (gdbarch))
1212 return (regnum <= RISCV_LAST_FP_REGNUM
1213 || regnum == RISCV_CSR_FCSR_REGNUM
1214 || regnum == RISCV_CSR_FFLAGS_REGNUM
1215 || regnum == RISCV_CSR_FRM_REGNUM);
1216 else
1217 return regnum < RISCV_FIRST_FP_REGNUM;
1218 }
1219 else if (reggroup == system_reggroup || reggroup == csr_reggroup)
1220 {
1221 if (regnum == RISCV_PRIV_REGNUM)
1222 return 1;
1223 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
1224 return 0;
1225 if (riscv_is_regnum_a_named_csr (regnum))
1226 return 1;
1227 return 0;
1228 }
1229 else if (reggroup == vector_reggroup)
1230 return 0;
1231 else
1232 return 0;
1233 }
1234
1235 /* Implement the print_registers_info gdbarch method. This is used by
1236 'info registers' and 'info all-registers'. */
1237
1238 static void
1239 riscv_print_registers_info (struct gdbarch *gdbarch,
1240 struct ui_file *file,
1241 struct frame_info *frame,
1242 int regnum, int print_all)
1243 {
1244 if (regnum != -1)
1245 {
1246 /* Print one specified register. */
1247 if (gdbarch_register_name (gdbarch, regnum) == NULL
1248 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
1249 error (_("Not a valid register for the current processor type"));
1250 riscv_print_one_register_info (gdbarch, file, frame, regnum);
1251 }
1252 else
1253 {
1254 struct reggroup *reggroup;
1255
1256 if (print_all)
1257 reggroup = all_reggroup;
1258 else
1259 reggroup = general_reggroup;
1260
1261 for (regnum = 0; regnum < gdbarch_num_cooked_regs (gdbarch); ++regnum)
1262 {
1263 /* Zero never changes, so might as well hide by default. */
1264 if (regnum == RISCV_ZERO_REGNUM && !print_all)
1265 continue;
1266
1267 /* Registers with no name are not valid on this ISA. */
1268 if (gdbarch_register_name (gdbarch, regnum) == NULL
1269 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
1270 continue;
1271
1272 /* Is the register in the group we're interested in? */
1273 if (!gdbarch_register_reggroup_p (gdbarch, regnum, reggroup))
1274 continue;
1275
1276 riscv_print_one_register_info (gdbarch, file, frame, regnum);
1277 }
1278 }
1279 }
1280
1281 /* Class that handles one decoded RiscV instruction. */
1282
1283 class riscv_insn
1284 {
1285 public:
1286
1287 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
1288 enum opcode
1289 {
1290 /* Unknown value is used at initialisation time. */
1291 UNKNOWN = 0,
1292
1293 /* These instructions are all the ones we are interested in during the
1294 prologue scan. */
1295 ADD,
1296 ADDI,
1297 ADDIW,
1298 ADDW,
1299 AUIPC,
1300 LUI,
1301 SD,
1302 SW,
1303 /* These are needed for software breakpoint support. */
1304 JAL,
1305 JALR,
1306 BEQ,
1307 BNE,
1308 BLT,
1309 BGE,
1310 BLTU,
1311 BGEU,
1312 /* These are needed for stepping over atomic sequences. */
1313 LR,
1314 SC,
1315
1316 /* Other instructions are not interesting during the prologue scan, and
1317 are ignored. */
1318 OTHER
1319 };
1320
1321 riscv_insn ()
1322 : m_length (0),
1323 m_opcode (OTHER),
1324 m_rd (0),
1325 m_rs1 (0),
1326 m_rs2 (0)
1327 {
1328 /* Nothing. */
1329 }
1330
1331 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1332
1333 /* Get the length of the instruction in bytes. */
1334 int length () const
1335 { return m_length; }
1336
1337 /* Get the opcode for this instruction. */
1338 enum opcode opcode () const
1339 { return m_opcode; }
1340
1341 /* Get destination register field for this instruction. This is only
1342 valid if the OPCODE implies there is such a field for this
1343 instruction. */
1344 int rd () const
1345 { return m_rd; }
1346
1347 /* Get the RS1 register field for this instruction. This is only valid
1348 if the OPCODE implies there is such a field for this instruction. */
1349 int rs1 () const
1350 { return m_rs1; }
1351
1352 /* Get the RS2 register field for this instruction. This is only valid
1353 if the OPCODE implies there is such a field for this instruction. */
1354 int rs2 () const
1355 { return m_rs2; }
1356
1357 /* Get the immediate for this instruction in signed form. This is only
1358 valid if the OPCODE implies there is such a field for this
1359 instruction. */
1360 int imm_signed () const
1361 { return m_imm.s; }
1362
1363 private:
1364
1365 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1366 int decode_register_index (unsigned long opcode, int offset)
1367 {
1368 return (opcode >> offset) & 0x1F;
1369 }
1370
1371 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1372 int decode_register_index_short (unsigned long opcode, int offset)
1373 {
1374 return ((opcode >> offset) & 0x7) + 8;
1375 }
1376
1377 /* Helper for DECODE, decode 32-bit R-type instruction. */
1378 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1379 {
1380 m_opcode = opcode;
1381 m_rd = decode_register_index (ival, OP_SH_RD);
1382 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1383 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1384 }
1385
1386 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1387 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1388 {
1389 m_opcode = opcode;
1390 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1391 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1392 }
1393
1394 /* Helper for DECODE, decode 32-bit I-type instruction. */
1395 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1396 {
1397 m_opcode = opcode;
1398 m_rd = decode_register_index (ival, OP_SH_RD);
1399 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1400 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1401 }
1402
1403 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1404 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1405 {
1406 m_opcode = opcode;
1407 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1408 m_imm.s = EXTRACT_CITYPE_IMM (ival);
1409 }
1410
1411 /* Helper for DECODE, decode 32-bit S-type instruction. */
1412 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1413 {
1414 m_opcode = opcode;
1415 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1416 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1417 m_imm.s = EXTRACT_STYPE_IMM (ival);
1418 }
1419
1420 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1421 encoding is different for each CS format instruction, so extracting
1422 the immediate is left up to the caller, who should pass the extracted
1423 immediate value through in IMM. */
1424 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1425 {
1426 m_opcode = opcode;
1427 m_imm.s = imm;
1428 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1429 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1430 }
1431
1432 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1433 encoding is different for each CSS format instruction, so extracting
1434 the immediate is left up to the caller, who should pass the extracted
1435 immediate value through in IMM. */
1436 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1437 {
1438 m_opcode = opcode;
1439 m_imm.s = imm;
1440 m_rs1 = RISCV_SP_REGNUM;
1441 /* Not a compressed register number in this case. */
1442 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1443 }
1444
1445 /* Helper for DECODE, decode 32-bit U-type instruction. */
1446 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1447 {
1448 m_opcode = opcode;
1449 m_rd = decode_register_index (ival, OP_SH_RD);
1450 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1451 }
1452
1453 /* Helper for DECODE, decode 32-bit J-type instruction. */
1454 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1455 {
1456 m_opcode = opcode;
1457 m_rd = decode_register_index (ival, OP_SH_RD);
1458 m_imm.s = EXTRACT_JTYPE_IMM (ival);
1459 }
1460
1461 /* Helper for DECODE, decode 32-bit J-type instruction. */
1462 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1463 {
1464 m_opcode = opcode;
1465 m_imm.s = EXTRACT_CJTYPE_IMM (ival);
1466 }
1467
1468 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1469 {
1470 m_opcode = opcode;
1471 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1472 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1473 m_imm.s = EXTRACT_BTYPE_IMM (ival);
1474 }
1475
1476 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1477 {
1478 m_opcode = opcode;
1479 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1480 m_imm.s = EXTRACT_CBTYPE_IMM (ival);
1481 }
1482
1483 /* Fetch instruction from target memory at ADDR, return the content of
1484 the instruction, and update LEN with the instruction length. */
1485 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1486 CORE_ADDR addr, int *len);
1487
1488 /* The length of the instruction in bytes. Should be 2 or 4. */
1489 int m_length;
1490
1491 /* The instruction opcode. */
1492 enum opcode m_opcode;
1493
1494 /* The three possible registers an instruction might reference. Not
1495 every instruction fills in all of these registers. Which fields are
1496 valid depends on the opcode. The naming of these fields matches the
1497 naming in the riscv isa manual. */
1498 int m_rd;
1499 int m_rs1;
1500 int m_rs2;
1501
1502 /* Possible instruction immediate. This is only valid if the instruction
1503 format contains an immediate, not all instruction, whether this is
1504 valid depends on the opcode. Despite only having one format for now
1505 the immediate is packed into a union, later instructions might require
1506 an unsigned formatted immediate, having the union in place now will
1507 reduce the need for code churn later. */
1508 union riscv_insn_immediate
1509 {
1510 riscv_insn_immediate ()
1511 : s (0)
1512 {
1513 /* Nothing. */
1514 }
1515
1516 int s;
1517 } m_imm;
1518 };
1519
1520 /* Fetch instruction from target memory at ADDR, return the content of the
1521 instruction, and update LEN with the instruction length. */
1522
1523 ULONGEST
1524 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1525 CORE_ADDR addr, int *len)
1526 {
1527 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1528 gdb_byte buf[8];
1529 int instlen, status;
1530
1531 /* All insns are at least 16 bits. */
1532 status = target_read_memory (addr, buf, 2);
1533 if (status)
1534 memory_error (TARGET_XFER_E_IO, addr);
1535
1536 /* If we need more, grab it now. */
1537 instlen = riscv_insn_length (buf[0]);
1538 gdb_assert (instlen <= sizeof (buf));
1539 *len = instlen;
1540
1541 if (instlen > 2)
1542 {
1543 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1544 if (status)
1545 memory_error (TARGET_XFER_E_IO, addr + 2);
1546 }
1547
1548 return extract_unsigned_integer (buf, instlen, byte_order);
1549 }
1550
1551 /* Fetch from target memory an instruction at PC and decode it. This can
1552 throw an error if the memory access fails, callers are responsible for
1553 handling this error if that is appropriate. */
1554
1555 void
1556 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1557 {
1558 ULONGEST ival;
1559
1560 /* Fetch the instruction, and the instructions length. */
1561 ival = fetch_instruction (gdbarch, pc, &m_length);
1562
1563 if (m_length == 4)
1564 {
1565 if (is_add_insn (ival))
1566 decode_r_type_insn (ADD, ival);
1567 else if (is_addw_insn (ival))
1568 decode_r_type_insn (ADDW, ival);
1569 else if (is_addi_insn (ival))
1570 decode_i_type_insn (ADDI, ival);
1571 else if (is_addiw_insn (ival))
1572 decode_i_type_insn (ADDIW, ival);
1573 else if (is_auipc_insn (ival))
1574 decode_u_type_insn (AUIPC, ival);
1575 else if (is_lui_insn (ival))
1576 decode_u_type_insn (LUI, ival);
1577 else if (is_sd_insn (ival))
1578 decode_s_type_insn (SD, ival);
1579 else if (is_sw_insn (ival))
1580 decode_s_type_insn (SW, ival);
1581 else if (is_jal_insn (ival))
1582 decode_j_type_insn (JAL, ival);
1583 else if (is_jalr_insn (ival))
1584 decode_i_type_insn (JALR, ival);
1585 else if (is_beq_insn (ival))
1586 decode_b_type_insn (BEQ, ival);
1587 else if (is_bne_insn (ival))
1588 decode_b_type_insn (BNE, ival);
1589 else if (is_blt_insn (ival))
1590 decode_b_type_insn (BLT, ival);
1591 else if (is_bge_insn (ival))
1592 decode_b_type_insn (BGE, ival);
1593 else if (is_bltu_insn (ival))
1594 decode_b_type_insn (BLTU, ival);
1595 else if (is_bgeu_insn (ival))
1596 decode_b_type_insn (BGEU, ival);
1597 else if (is_lr_w_insn (ival))
1598 decode_r_type_insn (LR, ival);
1599 else if (is_lr_d_insn (ival))
1600 decode_r_type_insn (LR, ival);
1601 else if (is_sc_w_insn (ival))
1602 decode_r_type_insn (SC, ival);
1603 else if (is_sc_d_insn (ival))
1604 decode_r_type_insn (SC, ival);
1605 else
1606 /* None of the other fields are valid in this case. */
1607 m_opcode = OTHER;
1608 }
1609 else if (m_length == 2)
1610 {
1611 int xlen = riscv_isa_xlen (gdbarch);
1612
1613 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1614 C_JALR. So must try to match C_JALR first as it has more bits in
1615 mask. */
1616 if (is_c_jalr_insn (ival))
1617 decode_cr_type_insn (JALR, ival);
1618 else if (is_c_add_insn (ival))
1619 decode_cr_type_insn (ADD, ival);
1620 /* C_ADDW is RV64 and RV128 only. */
1621 else if (xlen != 4 && is_c_addw_insn (ival))
1622 decode_cr_type_insn (ADDW, ival);
1623 else if (is_c_addi_insn (ival))
1624 decode_ci_type_insn (ADDI, ival);
1625 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1626 only and C_JAL is RV32 only. */
1627 else if (xlen != 4 && is_c_addiw_insn (ival))
1628 decode_ci_type_insn (ADDIW, ival);
1629 else if (xlen == 4 && is_c_jal_insn (ival))
1630 decode_cj_type_insn (JAL, ival);
1631 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1632 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1633 in mask. */
1634 else if (is_c_addi16sp_insn (ival))
1635 {
1636 m_opcode = ADDI;
1637 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1638 m_imm.s = EXTRACT_CITYPE_ADDI16SP_IMM (ival);
1639 }
1640 else if (is_c_addi4spn_insn (ival))
1641 {
1642 m_opcode = ADDI;
1643 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1644 m_rs1 = RISCV_SP_REGNUM;
1645 m_imm.s = EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival);
1646 }
1647 else if (is_c_lui_insn (ival))
1648 {
1649 m_opcode = LUI;
1650 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1651 m_imm.s = EXTRACT_CITYPE_LUI_IMM (ival);
1652 }
1653 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1654 and C_FSW is RV32 only. */
1655 else if (xlen != 4 && is_c_sd_insn (ival))
1656 decode_cs_type_insn (SD, ival, EXTRACT_CLTYPE_LD_IMM (ival));
1657 else if (is_c_sw_insn (ival))
1658 decode_cs_type_insn (SW, ival, EXTRACT_CLTYPE_LW_IMM (ival));
1659 else if (is_c_swsp_insn (ival))
1660 decode_css_type_insn (SW, ival, EXTRACT_CSSTYPE_SWSP_IMM (ival));
1661 else if (xlen != 4 && is_c_sdsp_insn (ival))
1662 decode_css_type_insn (SD, ival, EXTRACT_CSSTYPE_SDSP_IMM (ival));
1663 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1664 So must try to match C_JR first as it ahs more bits in mask. */
1665 else if (is_c_jr_insn (ival))
1666 decode_cr_type_insn (JALR, ival);
1667 else if (is_c_j_insn (ival))
1668 decode_cj_type_insn (JAL, ival);
1669 else if (is_c_beqz_insn (ival))
1670 decode_cb_type_insn (BEQ, ival);
1671 else if (is_c_bnez_insn (ival))
1672 decode_cb_type_insn (BNE, ival);
1673 else
1674 /* None of the other fields of INSN are valid in this case. */
1675 m_opcode = OTHER;
1676 }
1677 else
1678 {
1679 /* This must be a 6 or 8 byte instruction, we don't currently decode
1680 any of these, so just ignore it. */
1681 gdb_assert (m_length == 6 || m_length == 8);
1682 m_opcode = OTHER;
1683 }
1684 }
1685
1686 /* The prologue scanner. This is currently only used for skipping the
1687 prologue of a function when the DWARF information is not sufficient.
1688 However, it is written with filling of the frame cache in mind, which
1689 is why different groups of stack setup instructions are split apart
1690 during the core of the inner loop. In the future, the intention is to
1691 extend this function to fully support building up a frame cache that
1692 can unwind register values when there is no DWARF information. */
1693
1694 static CORE_ADDR
1695 riscv_scan_prologue (struct gdbarch *gdbarch,
1696 CORE_ADDR start_pc, CORE_ADDR end_pc,
1697 struct riscv_unwind_cache *cache)
1698 {
1699 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1700 CORE_ADDR end_prologue_addr = 0;
1701
1702 /* Find an upper limit on the function prologue using the debug
1703 information. If the debug information could not be used to provide
1704 that bound, then use an arbitrary large number as the upper bound. */
1705 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1706 if (after_prologue_pc == 0)
1707 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1708 if (after_prologue_pc < end_pc)
1709 end_pc = after_prologue_pc;
1710
1711 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1712 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1713 regs[regno] = pv_register (regno, 0);
1714 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1715
1716 if (riscv_debug_unwinder)
1717 fprintf_unfiltered
1718 (gdb_stdlog,
1719 "Prologue scan for function starting at %s (limit %s)\n",
1720 core_addr_to_string (start_pc),
1721 core_addr_to_string (end_pc));
1722
1723 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1724 {
1725 struct riscv_insn insn;
1726
1727 /* Decode the current instruction, and decide where the next
1728 instruction lives based on the size of this instruction. */
1729 insn.decode (gdbarch, cur_pc);
1730 gdb_assert (insn.length () > 0);
1731 next_pc = cur_pc + insn.length ();
1732
1733 /* Look for common stack adjustment insns. */
1734 if ((insn.opcode () == riscv_insn::ADDI
1735 || insn.opcode () == riscv_insn::ADDIW)
1736 && insn.rd () == RISCV_SP_REGNUM
1737 && insn.rs1 () == RISCV_SP_REGNUM)
1738 {
1739 /* Handle: addi sp, sp, -i
1740 or: addiw sp, sp, -i */
1741 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1742 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1743 regs[insn.rd ()]
1744 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1745 }
1746 else if ((insn.opcode () == riscv_insn::SW
1747 || insn.opcode () == riscv_insn::SD)
1748 && (insn.rs1 () == RISCV_SP_REGNUM
1749 || insn.rs1 () == RISCV_FP_REGNUM))
1750 {
1751 /* Handle: sw reg, offset(sp)
1752 or: sd reg, offset(sp)
1753 or: sw reg, offset(s0)
1754 or: sd reg, offset(s0) */
1755 /* Instruction storing a register onto the stack. */
1756 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1757 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1758 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1759 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1760 regs[insn.rs2 ()]);
1761 }
1762 else if (insn.opcode () == riscv_insn::ADDI
1763 && insn.rd () == RISCV_FP_REGNUM
1764 && insn.rs1 () == RISCV_SP_REGNUM)
1765 {
1766 /* Handle: addi s0, sp, size */
1767 /* Instructions setting up the frame pointer. */
1768 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1769 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1770 regs[insn.rd ()]
1771 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1772 }
1773 else if ((insn.opcode () == riscv_insn::ADD
1774 || insn.opcode () == riscv_insn::ADDW)
1775 && insn.rd () == RISCV_FP_REGNUM
1776 && insn.rs1 () == RISCV_SP_REGNUM
1777 && insn.rs2 () == RISCV_ZERO_REGNUM)
1778 {
1779 /* Handle: add s0, sp, 0
1780 or: addw s0, sp, 0 */
1781 /* Instructions setting up the frame pointer. */
1782 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1783 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1784 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1785 }
1786 else if ((insn.opcode () == riscv_insn::ADDI
1787 && insn.rd () == RISCV_ZERO_REGNUM
1788 && insn.rs1 () == RISCV_ZERO_REGNUM
1789 && insn.imm_signed () == 0))
1790 {
1791 /* Handle: add x0, x0, 0 (NOP) */
1792 }
1793 else if (insn.opcode () == riscv_insn::AUIPC)
1794 {
1795 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1796 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1797 }
1798 else if (insn.opcode () == riscv_insn::LUI)
1799 {
1800 /* Handle: lui REG, n
1801 Where REG is not gp register. */
1802 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1803 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1804 }
1805 else if (insn.opcode () == riscv_insn::ADDI)
1806 {
1807 /* Handle: addi REG1, REG2, IMM */
1808 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1809 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1810 regs[insn.rd ()]
1811 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1812 }
1813 else if (insn.opcode () == riscv_insn::ADD)
1814 {
1815 /* Handle: addi REG1, REG2, IMM */
1816 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1817 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1818 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1819 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1820 }
1821 else
1822 {
1823 end_prologue_addr = cur_pc;
1824 break;
1825 }
1826 }
1827
1828 if (end_prologue_addr == 0)
1829 end_prologue_addr = cur_pc;
1830
1831 if (riscv_debug_unwinder)
1832 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1833 core_addr_to_string (end_prologue_addr));
1834
1835 if (cache != NULL)
1836 {
1837 /* Figure out if it is a frame pointer or just a stack pointer. Also
1838 the offset held in the pv_t is from the original register value to
1839 the current value, which for a grows down stack means a negative
1840 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1841 from the current value to the original value. */
1842 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1843 {
1844 cache->frame_base_reg = RISCV_FP_REGNUM;
1845 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1846 }
1847 else
1848 {
1849 cache->frame_base_reg = RISCV_SP_REGNUM;
1850 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1851 }
1852
1853 /* Assign offset from old SP to all saved registers. As we don't
1854 have the previous value for the frame base register at this
1855 point, we store the offset as the address in the trad_frame, and
1856 then convert this to an actual address later. */
1857 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1858 {
1859 CORE_ADDR offset;
1860 if (stack.find_reg (gdbarch, i, &offset))
1861 {
1862 if (riscv_debug_unwinder)
1863 {
1864 /* Display OFFSET as a signed value, the offsets are from
1865 the frame base address to the registers location on
1866 the stack, with a descending stack this means the
1867 offsets are always negative. */
1868 fprintf_unfiltered (gdb_stdlog,
1869 "Register $%s at stack offset %s\n",
1870 gdbarch_register_name (gdbarch, i),
1871 plongest ((LONGEST) offset));
1872 }
1873 cache->regs[i].set_addr (offset);
1874 }
1875 }
1876 }
1877
1878 return end_prologue_addr;
1879 }
1880
1881 /* Implement the riscv_skip_prologue gdbarch method. */
1882
1883 static CORE_ADDR
1884 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1885 {
1886 CORE_ADDR func_addr;
1887
1888 /* See if we can determine the end of the prologue via the symbol
1889 table. If so, then return either PC, or the PC after the
1890 prologue, whichever is greater. */
1891 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1892 {
1893 CORE_ADDR post_prologue_pc
1894 = skip_prologue_using_sal (gdbarch, func_addr);
1895
1896 if (post_prologue_pc != 0)
1897 return std::max (pc, post_prologue_pc);
1898 }
1899
1900 /* Can't determine prologue from the symbol table, need to examine
1901 instructions. Pass -1 for the end address to indicate the prologue
1902 scanner can scan as far as it needs to find the end of the prologue. */
1903 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1904 }
1905
1906 /* Implement the gdbarch push dummy code callback. */
1907
1908 static CORE_ADDR
1909 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1910 CORE_ADDR funaddr, struct value **args, int nargs,
1911 struct type *value_type, CORE_ADDR *real_pc,
1912 CORE_ADDR *bp_addr, struct regcache *regcache)
1913 {
1914 /* A nop instruction is 'add x0, x0, 0'. */
1915 static const gdb_byte nop_insn[] = { 0x13, 0x00, 0x00, 0x00 };
1916
1917 /* Allocate space for a breakpoint, and keep the stack correctly
1918 aligned. The space allocated here must be at least big enough to
1919 accommodate the NOP_INSN defined above. */
1920 sp -= 16;
1921 *bp_addr = sp;
1922 *real_pc = funaddr;
1923
1924 /* When we insert a breakpoint we select whether to use a compressed
1925 breakpoint or not based on the existing contents of the memory.
1926
1927 If the breakpoint is being placed onto the stack as part of setting up
1928 for an inferior call from GDB, then the existing stack contents may
1929 randomly appear to be a compressed instruction, causing GDB to insert
1930 a compressed breakpoint. If this happens on a target that does not
1931 support compressed instructions then this could cause problems.
1932
1933 To prevent this issue we write an uncompressed nop onto the stack at
1934 the location where the breakpoint will be inserted. In this way we
1935 ensure that we always use an uncompressed breakpoint, which should
1936 work on all targets.
1937
1938 We call TARGET_WRITE_MEMORY here so that if the write fails we don't
1939 throw an exception. Instead we ignore the error and move on. The
1940 assumption is that either GDB will error later when actually trying to
1941 insert a software breakpoint, or GDB will use hardware breakpoints and
1942 there will be no need to write to memory later. */
1943 int status = target_write_memory (*bp_addr, nop_insn, sizeof (nop_insn));
1944
1945 if (riscv_debug_breakpoints || riscv_debug_infcall)
1946 fprintf_unfiltered (gdb_stdlog,
1947 "Writing %s-byte nop instruction to %s: %s\n",
1948 plongest (sizeof (nop_insn)),
1949 paddress (gdbarch, *bp_addr),
1950 (status == 0 ? "success" : "failed"));
1951
1952 return sp;
1953 }
1954
1955 /* Implement the gdbarch type alignment method, overrides the generic
1956 alignment algorithm for anything that is RISC-V specific. */
1957
1958 static ULONGEST
1959 riscv_type_align (gdbarch *gdbarch, type *type)
1960 {
1961 type = check_typedef (type);
1962 if (type->code () == TYPE_CODE_ARRAY && type->is_vector ())
1963 return std::min (TYPE_LENGTH (type), (ULONGEST) BIGGEST_ALIGNMENT);
1964
1965 /* Anything else will be aligned by the generic code. */
1966 return 0;
1967 }
1968
1969 /* Holds information about a single argument either being passed to an
1970 inferior function, or returned from an inferior function. This includes
1971 information about the size, type, etc of the argument, and also
1972 information about how the argument will be passed (or returned). */
1973
1974 struct riscv_arg_info
1975 {
1976 /* Contents of the argument. */
1977 const gdb_byte *contents;
1978
1979 /* Length of argument. */
1980 int length;
1981
1982 /* Alignment required for an argument of this type. */
1983 int align;
1984
1985 /* The type for this argument. */
1986 struct type *type;
1987
1988 /* Each argument can have either 1 or 2 locations assigned to it. Each
1989 location describes where part of the argument will be placed. The
1990 second location is valid based on the LOC_TYPE and C_LENGTH fields
1991 of the first location (which is always valid). */
1992 struct location
1993 {
1994 /* What type of location this is. */
1995 enum location_type
1996 {
1997 /* Argument passed in a register. */
1998 in_reg,
1999
2000 /* Argument passed as an on stack argument. */
2001 on_stack,
2002
2003 /* Argument passed by reference. The second location is always
2004 valid for a BY_REF argument, and describes where the address
2005 of the BY_REF argument should be placed. */
2006 by_ref
2007 } loc_type;
2008
2009 /* Information that depends on the location type. */
2010 union
2011 {
2012 /* Which register number to use. */
2013 int regno;
2014
2015 /* The offset into the stack region. */
2016 int offset;
2017 } loc_data;
2018
2019 /* The length of contents covered by this location. If this is less
2020 than the total length of the argument, then the second location
2021 will be valid, and will describe where the rest of the argument
2022 will go. */
2023 int c_length;
2024
2025 /* The offset within CONTENTS for this part of the argument. This can
2026 be non-zero even for the first part (the first field of a struct can
2027 have a non-zero offset due to padding). For the second part of the
2028 argument, this might be the C_LENGTH value of the first part,
2029 however, if we are passing a structure in two registers, and there's
2030 is padding between the first and second field, then this offset
2031 might be greater than the length of the first argument part. When
2032 the second argument location is not holding part of the argument
2033 value, but is instead holding the address of a reference argument,
2034 then this offset will be set to 0. */
2035 int c_offset;
2036 } argloc[2];
2037
2038 /* TRUE if this is an unnamed argument. */
2039 bool is_unnamed;
2040 };
2041
2042 /* Information about a set of registers being used for passing arguments as
2043 part of a function call. The register set must be numerically
2044 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
2045 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
2046
2047 struct riscv_arg_reg
2048 {
2049 riscv_arg_reg (int first, int last)
2050 : next_regnum (first),
2051 last_regnum (last)
2052 {
2053 /* Nothing. */
2054 }
2055
2056 /* The GDB register number to use in this set. */
2057 int next_regnum;
2058
2059 /* The last GDB register number to use in this set. */
2060 int last_regnum;
2061 };
2062
2063 /* Arguments can be passed as on stack arguments, or by reference. The
2064 on stack arguments must be in a continuous region starting from $sp,
2065 while the by reference arguments can be anywhere, but we'll put them
2066 on the stack after (at higher address) the on stack arguments.
2067
2068 This might not be the right approach to take. The ABI is clear that
2069 an argument passed by reference can be modified by the callee, which
2070 us placing the argument (temporarily) onto the stack will not achieve
2071 (changes will be lost). There's also the possibility that very large
2072 arguments could overflow the stack.
2073
2074 This struct is used to track offset into these two areas for where
2075 arguments are to be placed. */
2076 struct riscv_memory_offsets
2077 {
2078 riscv_memory_offsets ()
2079 : arg_offset (0),
2080 ref_offset (0)
2081 {
2082 /* Nothing. */
2083 }
2084
2085 /* Offset into on stack argument area. */
2086 int arg_offset;
2087
2088 /* Offset into the pass by reference area. */
2089 int ref_offset;
2090 };
2091
2092 /* Holds information about where arguments to a call will be placed. This
2093 is updated as arguments are added onto the call, and can be used to
2094 figure out where the next argument should be placed. */
2095
2096 struct riscv_call_info
2097 {
2098 riscv_call_info (struct gdbarch *gdbarch)
2099 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
2100 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
2101 {
2102 xlen = riscv_abi_xlen (gdbarch);
2103 flen = riscv_abi_flen (gdbarch);
2104
2105 /* Reduce the number of integer argument registers when using the
2106 embedded abi (i.e. rv32e). */
2107 if (riscv_abi_embedded (gdbarch))
2108 int_regs.last_regnum = RISCV_A0_REGNUM + 5;
2109
2110 /* Disable use of floating point registers if needed. */
2111 if (!riscv_has_fp_abi (gdbarch))
2112 float_regs.next_regnum = float_regs.last_regnum + 1;
2113 }
2114
2115 /* Track the memory areas used for holding in-memory arguments to a
2116 call. */
2117 struct riscv_memory_offsets memory;
2118
2119 /* Holds information about the next integer register to use for passing
2120 an argument. */
2121 struct riscv_arg_reg int_regs;
2122
2123 /* Holds information about the next floating point register to use for
2124 passing an argument. */
2125 struct riscv_arg_reg float_regs;
2126
2127 /* The XLEN and FLEN are copied in to this structure for convenience, and
2128 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
2129 int xlen;
2130 int flen;
2131 };
2132
2133 /* Return the number of registers available for use as parameters in the
2134 register set REG. Returned value can be 0 or more. */
2135
2136 static int
2137 riscv_arg_regs_available (struct riscv_arg_reg *reg)
2138 {
2139 if (reg->next_regnum > reg->last_regnum)
2140 return 0;
2141
2142 return (reg->last_regnum - reg->next_regnum + 1);
2143 }
2144
2145 /* If there is at least one register available in the register set REG then
2146 the next register from REG is assigned to LOC and the length field of
2147 LOC is updated to LENGTH. The register set REG is updated to indicate
2148 that the assigned register is no longer available and the function
2149 returns true.
2150
2151 If there are no registers available in REG then the function returns
2152 false, and LOC and REG are unchanged. */
2153
2154 static bool
2155 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
2156 struct riscv_arg_reg *reg,
2157 int length, int offset)
2158 {
2159 if (reg->next_regnum <= reg->last_regnum)
2160 {
2161 loc->loc_type = riscv_arg_info::location::in_reg;
2162 loc->loc_data.regno = reg->next_regnum;
2163 reg->next_regnum++;
2164 loc->c_length = length;
2165 loc->c_offset = offset;
2166 return true;
2167 }
2168
2169 return false;
2170 }
2171
2172 /* Assign LOC a location as the next stack parameter, and update MEMORY to
2173 record that an area of stack has been used to hold the parameter
2174 described by LOC.
2175
2176 The length field of LOC is updated to LENGTH, the length of the
2177 parameter being stored, and ALIGN is the alignment required by the
2178 parameter, which will affect how memory is allocated out of MEMORY. */
2179
2180 static void
2181 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
2182 struct riscv_memory_offsets *memory,
2183 int length, int align)
2184 {
2185 loc->loc_type = riscv_arg_info::location::on_stack;
2186 memory->arg_offset
2187 = align_up (memory->arg_offset, align);
2188 loc->loc_data.offset = memory->arg_offset;
2189 memory->arg_offset += length;
2190 loc->c_length = length;
2191
2192 /* Offset is always 0, either we're the first location part, in which
2193 case we're reading content from the start of the argument, or we're
2194 passing the address of a reference argument, so 0. */
2195 loc->c_offset = 0;
2196 }
2197
2198 /* Update AINFO, which describes an argument that should be passed or
2199 returned using the integer ABI. The argloc fields within AINFO are
2200 updated to describe the location in which the argument will be passed to
2201 a function, or returned from a function.
2202
2203 The CINFO structure contains the ongoing call information, the holds
2204 information such as which argument registers are remaining to be
2205 assigned to parameter, and how much memory has been used by parameters
2206 so far.
2207
2208 By examining the state of CINFO a suitable location can be selected,
2209 and assigned to AINFO. */
2210
2211 static void
2212 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
2213 struct riscv_call_info *cinfo)
2214 {
2215 if (ainfo->length > (2 * cinfo->xlen))
2216 {
2217 /* Argument is going to be passed by reference. */
2218 ainfo->argloc[0].loc_type
2219 = riscv_arg_info::location::by_ref;
2220 cinfo->memory.ref_offset
2221 = align_up (cinfo->memory.ref_offset, ainfo->align);
2222 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
2223 cinfo->memory.ref_offset += ainfo->length;
2224 ainfo->argloc[0].c_length = ainfo->length;
2225
2226 /* The second location for this argument is given over to holding the
2227 address of the by-reference data. Pass 0 for the offset as this
2228 is not part of the actual argument value. */
2229 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2230 &cinfo->int_regs,
2231 cinfo->xlen, 0))
2232 riscv_assign_stack_location (&ainfo->argloc[1],
2233 &cinfo->memory, cinfo->xlen,
2234 cinfo->xlen);
2235 }
2236 else
2237 {
2238 int len = std::min (ainfo->length, cinfo->xlen);
2239 int align = std::max (ainfo->align, cinfo->xlen);
2240
2241 /* Unnamed arguments in registers that require 2*XLEN alignment are
2242 passed in an aligned register pair. */
2243 if (ainfo->is_unnamed && (align == cinfo->xlen * 2)
2244 && cinfo->int_regs.next_regnum & 1)
2245 cinfo->int_regs.next_regnum++;
2246
2247 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2248 &cinfo->int_regs, len, 0))
2249 riscv_assign_stack_location (&ainfo->argloc[0],
2250 &cinfo->memory, len, align);
2251
2252 if (len < ainfo->length)
2253 {
2254 len = ainfo->length - len;
2255 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2256 &cinfo->int_regs, len,
2257 cinfo->xlen))
2258 riscv_assign_stack_location (&ainfo->argloc[1],
2259 &cinfo->memory, len, cinfo->xlen);
2260 }
2261 }
2262 }
2263
2264 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2265 is being passed with the floating point ABI. */
2266
2267 static void
2268 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
2269 struct riscv_call_info *cinfo)
2270 {
2271 if (ainfo->length > cinfo->flen || ainfo->is_unnamed)
2272 return riscv_call_arg_scalar_int (ainfo, cinfo);
2273 else
2274 {
2275 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2276 &cinfo->float_regs,
2277 ainfo->length, 0))
2278 return riscv_call_arg_scalar_int (ainfo, cinfo);
2279 }
2280 }
2281
2282 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2283 is a complex floating point argument, and is therefore handled
2284 differently to other argument types. */
2285
2286 static void
2287 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
2288 struct riscv_call_info *cinfo)
2289 {
2290 if (ainfo->length <= (2 * cinfo->flen)
2291 && riscv_arg_regs_available (&cinfo->float_regs) >= 2
2292 && !ainfo->is_unnamed)
2293 {
2294 bool result;
2295 int len = ainfo->length / 2;
2296
2297 result = riscv_assign_reg_location (&ainfo->argloc[0],
2298 &cinfo->float_regs, len, 0);
2299 gdb_assert (result);
2300
2301 result = riscv_assign_reg_location (&ainfo->argloc[1],
2302 &cinfo->float_regs, len, len);
2303 gdb_assert (result);
2304 }
2305 else
2306 return riscv_call_arg_scalar_int (ainfo, cinfo);
2307 }
2308
2309 /* A structure used for holding information about a structure type within
2310 the inferior program. The RiscV ABI has special rules for handling some
2311 structures with a single field or with two fields. The counting of
2312 fields here is done after flattening out all nested structures. */
2313
2314 class riscv_struct_info
2315 {
2316 public:
2317 riscv_struct_info ()
2318 : m_number_of_fields (0),
2319 m_types { nullptr, nullptr },
2320 m_offsets { 0, 0 }
2321 {
2322 /* Nothing. */
2323 }
2324
2325 /* Analyse TYPE descending into nested structures, count the number of
2326 scalar fields and record the types of the first two fields found. */
2327 void analyse (struct type *type)
2328 {
2329 analyse_inner (type, 0);
2330 }
2331
2332 /* The number of scalar fields found in the analysed type. This is
2333 currently only accurate if the value returned is 0, 1, or 2 as the
2334 analysis stops counting when the number of fields is 3. This is
2335 because the RiscV ABI only has special cases for 1 or 2 fields,
2336 anything else we just don't care about. */
2337 int number_of_fields () const
2338 { return m_number_of_fields; }
2339
2340 /* Return the type for scalar field INDEX within the analysed type. Will
2341 return nullptr if there is no field at that index. Only INDEX values
2342 0 and 1 can be requested as the RiscV ABI only has special cases for
2343 structures with 1 or 2 fields. */
2344 struct type *field_type (int index) const
2345 {
2346 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
2347 return m_types[index];
2348 }
2349
2350 /* Return the offset of scalar field INDEX within the analysed type. Will
2351 return 0 if there is no field at that index. Only INDEX values 0 and
2352 1 can be requested as the RiscV ABI only has special cases for
2353 structures with 1 or 2 fields. */
2354 int field_offset (int index) const
2355 {
2356 gdb_assert (index < (sizeof (m_offsets) / sizeof (m_offsets[0])));
2357 return m_offsets[index];
2358 }
2359
2360 private:
2361 /* The number of scalar fields found within the structure after recursing
2362 into nested structures. */
2363 int m_number_of_fields;
2364
2365 /* The types of the first two scalar fields found within the structure
2366 after recursing into nested structures. */
2367 struct type *m_types[2];
2368
2369 /* The offsets of the first two scalar fields found within the structure
2370 after recursing into nested structures. */
2371 int m_offsets[2];
2372
2373 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2374 offset from the start of the top level structure being analysed. */
2375 void analyse_inner (struct type *type, int offset);
2376 };
2377
2378 /* See description in class declaration. */
2379
2380 void
2381 riscv_struct_info::analyse_inner (struct type *type, int offset)
2382 {
2383 unsigned int count = type->num_fields ();
2384 unsigned int i;
2385
2386 for (i = 0; i < count; ++i)
2387 {
2388 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
2389 continue;
2390
2391 struct type *field_type = type->field (i).type ();
2392 field_type = check_typedef (field_type);
2393 int field_offset
2394 = offset + TYPE_FIELD_BITPOS (type, i) / TARGET_CHAR_BIT;
2395
2396 switch (field_type->code ())
2397 {
2398 case TYPE_CODE_STRUCT:
2399 analyse_inner (field_type, field_offset);
2400 break;
2401
2402 default:
2403 /* RiscV only flattens out structures. Anything else does not
2404 need to be flattened, we just record the type, and when we
2405 look at the analysis results we'll realise this is not a
2406 structure we can special case, and pass the structure in
2407 memory. */
2408 if (m_number_of_fields < 2)
2409 {
2410 m_types[m_number_of_fields] = field_type;
2411 m_offsets[m_number_of_fields] = field_offset;
2412 }
2413 m_number_of_fields++;
2414 break;
2415 }
2416
2417 /* RiscV only has special handling for structures with 1 or 2 scalar
2418 fields, any more than that and the structure is just passed in
2419 memory. We can safely drop out early when we find 3 or more
2420 fields then. */
2421
2422 if (m_number_of_fields > 2)
2423 return;
2424 }
2425 }
2426
2427 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2428 is a structure. Small structures on RiscV have some special case
2429 handling in order that the structure might be passed in register.
2430 Larger structures are passed in memory. After assigning location
2431 information to AINFO, CINFO will have been updated. */
2432
2433 static void
2434 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
2435 struct riscv_call_info *cinfo)
2436 {
2437 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2438 {
2439 struct riscv_struct_info sinfo;
2440
2441 sinfo.analyse (ainfo->type);
2442 if (sinfo.number_of_fields () == 1
2443 && sinfo.field_type(0)->code () == TYPE_CODE_COMPLEX)
2444 {
2445 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2446 except we use the type of the complex field instead of the
2447 type from AINFO, and the first location might be at a non-zero
2448 offset. */
2449 if (TYPE_LENGTH (sinfo.field_type (0)) <= (2 * cinfo->flen)
2450 && riscv_arg_regs_available (&cinfo->float_regs) >= 2
2451 && !ainfo->is_unnamed)
2452 {
2453 bool result;
2454 int len = TYPE_LENGTH (sinfo.field_type (0)) / 2;
2455 int offset = sinfo.field_offset (0);
2456
2457 result = riscv_assign_reg_location (&ainfo->argloc[0],
2458 &cinfo->float_regs, len,
2459 offset);
2460 gdb_assert (result);
2461
2462 result = riscv_assign_reg_location (&ainfo->argloc[1],
2463 &cinfo->float_regs, len,
2464 (offset + len));
2465 gdb_assert (result);
2466 }
2467 else
2468 riscv_call_arg_scalar_int (ainfo, cinfo);
2469 return;
2470 }
2471
2472 if (sinfo.number_of_fields () == 1
2473 && sinfo.field_type(0)->code () == TYPE_CODE_FLT)
2474 {
2475 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2476 except we use the type of the first scalar field instead of
2477 the type from AINFO. Also the location might be at a non-zero
2478 offset. */
2479 if (TYPE_LENGTH (sinfo.field_type (0)) > cinfo->flen
2480 || ainfo->is_unnamed)
2481 riscv_call_arg_scalar_int (ainfo, cinfo);
2482 else
2483 {
2484 int offset = sinfo.field_offset (0);
2485 int len = TYPE_LENGTH (sinfo.field_type (0));
2486
2487 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2488 &cinfo->float_regs,
2489 len, offset))
2490 riscv_call_arg_scalar_int (ainfo, cinfo);
2491 }
2492 return;
2493 }
2494
2495 if (sinfo.number_of_fields () == 2
2496 && sinfo.field_type(0)->code () == TYPE_CODE_FLT
2497 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2498 && sinfo.field_type(1)->code () == TYPE_CODE_FLT
2499 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
2500 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2501 {
2502 int len0 = TYPE_LENGTH (sinfo.field_type (0));
2503 int offset = sinfo.field_offset (0);
2504 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2505 &cinfo->float_regs, len0, offset))
2506 error (_("failed during argument setup"));
2507
2508 int len1 = TYPE_LENGTH (sinfo.field_type (1));
2509 offset = sinfo.field_offset (1);
2510 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2511 - TYPE_LENGTH (sinfo.field_type (0))));
2512
2513 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2514 &cinfo->float_regs,
2515 len1, offset))
2516 error (_("failed during argument setup"));
2517 return;
2518 }
2519
2520 if (sinfo.number_of_fields () == 2
2521 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2522 && (sinfo.field_type(0)->code () == TYPE_CODE_FLT
2523 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2524 && is_integral_type (sinfo.field_type (1))
2525 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2526 {
2527 int len0 = TYPE_LENGTH (sinfo.field_type (0));
2528 int offset = sinfo.field_offset (0);
2529 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2530 &cinfo->float_regs, len0, offset))
2531 error (_("failed during argument setup"));
2532
2533 int len1 = TYPE_LENGTH (sinfo.field_type (1));
2534 offset = sinfo.field_offset (1);
2535 gdb_assert (len1 <= cinfo->xlen);
2536 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2537 &cinfo->int_regs, len1, offset))
2538 error (_("failed during argument setup"));
2539 return;
2540 }
2541
2542 if (sinfo.number_of_fields () == 2
2543 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2544 && (is_integral_type (sinfo.field_type (0))
2545 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2546 && sinfo.field_type(1)->code () == TYPE_CODE_FLT
2547 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2548 {
2549 int len0 = TYPE_LENGTH (sinfo.field_type (0));
2550 int len1 = TYPE_LENGTH (sinfo.field_type (1));
2551
2552 gdb_assert (len0 <= cinfo->xlen);
2553 gdb_assert (len1 <= cinfo->flen);
2554
2555 int offset = sinfo.field_offset (0);
2556 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2557 &cinfo->int_regs, len0, offset))
2558 error (_("failed during argument setup"));
2559
2560 offset = sinfo.field_offset (1);
2561 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2562 &cinfo->float_regs,
2563 len1, offset))
2564 error (_("failed during argument setup"));
2565
2566 return;
2567 }
2568 }
2569
2570 /* Non of the structure flattening cases apply, so we just pass using
2571 the integer ABI. */
2572 riscv_call_arg_scalar_int (ainfo, cinfo);
2573 }
2574
2575 /* Assign a location to call (or return) argument AINFO, the location is
2576 selected from CINFO which holds information about what call argument
2577 locations are available for use next. The TYPE is the type of the
2578 argument being passed, this information is recorded into AINFO (along
2579 with some additional information derived from the type). IS_UNNAMED
2580 is true if this is an unnamed (stdarg) argument, this info is also
2581 recorded into AINFO.
2582
2583 After assigning a location to AINFO, CINFO will have been updated. */
2584
2585 static void
2586 riscv_arg_location (struct gdbarch *gdbarch,
2587 struct riscv_arg_info *ainfo,
2588 struct riscv_call_info *cinfo,
2589 struct type *type, bool is_unnamed)
2590 {
2591 ainfo->type = type;
2592 ainfo->length = TYPE_LENGTH (ainfo->type);
2593 ainfo->align = type_align (ainfo->type);
2594 ainfo->is_unnamed = is_unnamed;
2595 ainfo->contents = nullptr;
2596 ainfo->argloc[0].c_length = 0;
2597 ainfo->argloc[1].c_length = 0;
2598
2599 switch (ainfo->type->code ())
2600 {
2601 case TYPE_CODE_INT:
2602 case TYPE_CODE_BOOL:
2603 case TYPE_CODE_CHAR:
2604 case TYPE_CODE_RANGE:
2605 case TYPE_CODE_ENUM:
2606 case TYPE_CODE_PTR:
2607 if (ainfo->length <= cinfo->xlen)
2608 {
2609 ainfo->type = builtin_type (gdbarch)->builtin_long;
2610 ainfo->length = cinfo->xlen;
2611 }
2612 else if (ainfo->length <= (2 * cinfo->xlen))
2613 {
2614 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2615 ainfo->length = 2 * cinfo->xlen;
2616 }
2617
2618 /* Recalculate the alignment requirement. */
2619 ainfo->align = type_align (ainfo->type);
2620 riscv_call_arg_scalar_int (ainfo, cinfo);
2621 break;
2622
2623 case TYPE_CODE_FLT:
2624 riscv_call_arg_scalar_float (ainfo, cinfo);
2625 break;
2626
2627 case TYPE_CODE_COMPLEX:
2628 riscv_call_arg_complex_float (ainfo, cinfo);
2629 break;
2630
2631 case TYPE_CODE_STRUCT:
2632 riscv_call_arg_struct (ainfo, cinfo);
2633 break;
2634
2635 default:
2636 riscv_call_arg_scalar_int (ainfo, cinfo);
2637 break;
2638 }
2639 }
2640
2641 /* Used for printing debug information about the call argument location in
2642 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2643 addresses for the location of pass-by-reference and
2644 arguments-on-the-stack memory areas. */
2645
2646 static void
2647 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2648 struct riscv_arg_info *info,
2649 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2650 {
2651 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2652 TYPE_SAFE_NAME (info->type), info->length, info->align);
2653 switch (info->argloc[0].loc_type)
2654 {
2655 case riscv_arg_info::location::in_reg:
2656 fprintf_unfiltered
2657 (stream, ", register %s",
2658 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2659 if (info->argloc[0].c_length < info->length)
2660 {
2661 switch (info->argloc[1].loc_type)
2662 {
2663 case riscv_arg_info::location::in_reg:
2664 fprintf_unfiltered
2665 (stream, ", register %s",
2666 gdbarch_register_name (gdbarch,
2667 info->argloc[1].loc_data.regno));
2668 break;
2669
2670 case riscv_arg_info::location::on_stack:
2671 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2672 info->argloc[1].loc_data.offset);
2673 break;
2674
2675 case riscv_arg_info::location::by_ref:
2676 default:
2677 /* The second location should never be a reference, any
2678 argument being passed by reference just places its address
2679 in the first location and is done. */
2680 error (_("invalid argument location"));
2681 break;
2682 }
2683
2684 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2685 fprintf_unfiltered (stream, " (offset 0x%x)",
2686 info->argloc[1].c_offset);
2687 }
2688 break;
2689
2690 case riscv_arg_info::location::on_stack:
2691 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2692 info->argloc[0].loc_data.offset);
2693 break;
2694
2695 case riscv_arg_info::location::by_ref:
2696 fprintf_unfiltered
2697 (stream, ", by reference, data at offset 0x%x (%s)",
2698 info->argloc[0].loc_data.offset,
2699 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2700 if (info->argloc[1].loc_type
2701 == riscv_arg_info::location::in_reg)
2702 fprintf_unfiltered
2703 (stream, ", address in register %s",
2704 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2705 else
2706 {
2707 gdb_assert (info->argloc[1].loc_type
2708 == riscv_arg_info::location::on_stack);
2709 fprintf_unfiltered
2710 (stream, ", address on stack at offset 0x%x (%s)",
2711 info->argloc[1].loc_data.offset,
2712 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2713 }
2714 break;
2715
2716 default:
2717 gdb_assert_not_reached (_("unknown argument location type"));
2718 }
2719 }
2720
2721 /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA
2722 into a buffer that is at least as big as the register REGNUM, padding
2723 out the DATA with either 0x00, or 0xff. For floating point registers
2724 0xff is used, for everyone else 0x00 is used. */
2725
2726 static void
2727 riscv_regcache_cooked_write (int regnum, const gdb_byte *data, int len,
2728 struct regcache *regcache, int flen)
2729 {
2730 gdb_byte tmp [sizeof (ULONGEST)];
2731
2732 /* FP values in FP registers must be NaN-boxed. */
2733 if (riscv_is_fp_regno_p (regnum) && len < flen)
2734 memset (tmp, -1, sizeof (tmp));
2735 else
2736 memset (tmp, 0, sizeof (tmp));
2737 memcpy (tmp, data, len);
2738 regcache->cooked_write (regnum, tmp);
2739 }
2740
2741 /* Implement the push dummy call gdbarch callback. */
2742
2743 static CORE_ADDR
2744 riscv_push_dummy_call (struct gdbarch *gdbarch,
2745 struct value *function,
2746 struct regcache *regcache,
2747 CORE_ADDR bp_addr,
2748 int nargs,
2749 struct value **args,
2750 CORE_ADDR sp,
2751 function_call_return_method return_method,
2752 CORE_ADDR struct_addr)
2753 {
2754 int i;
2755 CORE_ADDR sp_args, sp_refs;
2756 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2757
2758 struct riscv_arg_info *arg_info =
2759 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2760
2761 struct riscv_call_info call_info (gdbarch);
2762
2763 CORE_ADDR osp = sp;
2764
2765 struct type *ftype = check_typedef (value_type (function));
2766
2767 if (ftype->code () == TYPE_CODE_PTR)
2768 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
2769
2770 /* We'll use register $a0 if we're returning a struct. */
2771 if (return_method == return_method_struct)
2772 ++call_info.int_regs.next_regnum;
2773
2774 for (i = 0; i < nargs; ++i)
2775 {
2776 struct value *arg_value;
2777 struct type *arg_type;
2778 struct riscv_arg_info *info = &arg_info[i];
2779
2780 arg_value = args[i];
2781 arg_type = check_typedef (value_type (arg_value));
2782
2783 riscv_arg_location (gdbarch, info, &call_info, arg_type,
2784 ftype->has_varargs () && i >= ftype->num_fields ());
2785
2786 if (info->type != arg_type)
2787 arg_value = value_cast (info->type, arg_value);
2788 info->contents = value_contents (arg_value);
2789 }
2790
2791 /* Adjust the stack pointer and align it. */
2792 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2793 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2794
2795 if (riscv_debug_infcall > 0)
2796 {
2797 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2798 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2799 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2800 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2801 call_info.xlen, call_info.flen);
2802 if (return_method == return_method_struct)
2803 fprintf_unfiltered (gdb_stdlog,
2804 "[*] struct return pointer in register $A0\n");
2805 for (i = 0; i < nargs; ++i)
2806 {
2807 struct riscv_arg_info *info = &arg_info [i];
2808
2809 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2810 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2811 fprintf_unfiltered (gdb_stdlog, "\n");
2812 }
2813 if (call_info.memory.arg_offset > 0
2814 || call_info.memory.ref_offset > 0)
2815 {
2816 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2817 core_addr_to_string (osp));
2818 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2819 call_info.memory.arg_offset);
2820 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2821 call_info.memory.ref_offset);
2822 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2823 core_addr_to_string_nz (osp - sp));
2824 }
2825 }
2826
2827 /* Now load the argument into registers, or onto the stack. */
2828
2829 if (return_method == return_method_struct)
2830 {
2831 gdb_byte buf[sizeof (LONGEST)];
2832
2833 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2834 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2835 }
2836
2837 for (i = 0; i < nargs; ++i)
2838 {
2839 CORE_ADDR dst;
2840 int second_arg_length = 0;
2841 const gdb_byte *second_arg_data;
2842 struct riscv_arg_info *info = &arg_info [i];
2843
2844 gdb_assert (info->length > 0);
2845
2846 switch (info->argloc[0].loc_type)
2847 {
2848 case riscv_arg_info::location::in_reg:
2849 {
2850 gdb_assert (info->argloc[0].c_length <= info->length);
2851
2852 riscv_regcache_cooked_write (info->argloc[0].loc_data.regno,
2853 (info->contents
2854 + info->argloc[0].c_offset),
2855 info->argloc[0].c_length,
2856 regcache, call_info.flen);
2857 second_arg_length =
2858 (((info->argloc[0].c_length + info->argloc[0].c_offset) < info->length)
2859 ? info->argloc[1].c_length : 0);
2860 second_arg_data = info->contents + info->argloc[1].c_offset;
2861 }
2862 break;
2863
2864 case riscv_arg_info::location::on_stack:
2865 dst = sp_args + info->argloc[0].loc_data.offset;
2866 write_memory (dst, info->contents, info->length);
2867 second_arg_length = 0;
2868 break;
2869
2870 case riscv_arg_info::location::by_ref:
2871 dst = sp_refs + info->argloc[0].loc_data.offset;
2872 write_memory (dst, info->contents, info->length);
2873
2874 second_arg_length = call_info.xlen;
2875 second_arg_data = (gdb_byte *) &dst;
2876 break;
2877
2878 default:
2879 gdb_assert_not_reached (_("unknown argument location type"));
2880 }
2881
2882 if (second_arg_length > 0)
2883 {
2884 switch (info->argloc[1].loc_type)
2885 {
2886 case riscv_arg_info::location::in_reg:
2887 {
2888 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2889 && second_arg_length <= call_info.flen)
2890 || second_arg_length <= call_info.xlen);
2891 riscv_regcache_cooked_write (info->argloc[1].loc_data.regno,
2892 second_arg_data,
2893 second_arg_length,
2894 regcache, call_info.flen);
2895 }
2896 break;
2897
2898 case riscv_arg_info::location::on_stack:
2899 {
2900 CORE_ADDR arg_addr;
2901
2902 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2903 write_memory (arg_addr, second_arg_data, second_arg_length);
2904 break;
2905 }
2906
2907 case riscv_arg_info::location::by_ref:
2908 default:
2909 /* The second location should never be a reference, any
2910 argument being passed by reference just places its address
2911 in the first location and is done. */
2912 error (_("invalid argument location"));
2913 break;
2914 }
2915 }
2916 }
2917
2918 /* Set the dummy return value to bp_addr.
2919 A dummy breakpoint will be setup to execute the call. */
2920
2921 if (riscv_debug_infcall > 0)
2922 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2923 core_addr_to_string (bp_addr));
2924 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2925
2926 /* Finally, update the stack pointer. */
2927
2928 if (riscv_debug_infcall > 0)
2929 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2930 core_addr_to_string (sp));
2931 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2932
2933 return sp;
2934 }
2935
2936 /* Implement the return_value gdbarch method. */
2937
2938 static enum return_value_convention
2939 riscv_return_value (struct gdbarch *gdbarch,
2940 struct value *function,
2941 struct type *type,
2942 struct regcache *regcache,
2943 gdb_byte *readbuf,
2944 const gdb_byte *writebuf)
2945 {
2946 struct riscv_call_info call_info (gdbarch);
2947 struct riscv_arg_info info;
2948 struct type *arg_type;
2949
2950 arg_type = check_typedef (type);
2951 riscv_arg_location (gdbarch, &info, &call_info, arg_type, false);
2952
2953 if (riscv_debug_infcall > 0)
2954 {
2955 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2956 fprintf_unfiltered (gdb_stdlog, "[R] ");
2957 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2958 fprintf_unfiltered (gdb_stdlog, "\n");
2959 }
2960
2961 if (readbuf != nullptr || writebuf != nullptr)
2962 {
2963 unsigned int arg_len;
2964 struct value *abi_val;
2965 gdb_byte *old_readbuf = nullptr;
2966 int regnum;
2967
2968 /* We only do one thing at a time. */
2969 gdb_assert (readbuf == nullptr || writebuf == nullptr);
2970
2971 /* In some cases the argument is not returned as the declared type,
2972 and we need to cast to or from the ABI type in order to
2973 correctly access the argument. When writing to the machine we
2974 do the cast here, when reading from the machine the cast occurs
2975 later, after extracting the value. As the ABI type can be
2976 larger than the declared type, then the read or write buffers
2977 passed in might be too small. Here we ensure that we are using
2978 buffers of sufficient size. */
2979 if (writebuf != nullptr)
2980 {
2981 struct value *arg_val = value_from_contents (arg_type, writebuf);
2982 abi_val = value_cast (info.type, arg_val);
2983 writebuf = value_contents_raw (abi_val);
2984 }
2985 else
2986 {
2987 abi_val = allocate_value (info.type);
2988 old_readbuf = readbuf;
2989 readbuf = value_contents_raw (abi_val);
2990 }
2991 arg_len = TYPE_LENGTH (info.type);
2992
2993 switch (info.argloc[0].loc_type)
2994 {
2995 /* Return value in register(s). */
2996 case riscv_arg_info::location::in_reg:
2997 {
2998 regnum = info.argloc[0].loc_data.regno;
2999 gdb_assert (info.argloc[0].c_length <= arg_len);
3000 gdb_assert (info.argloc[0].c_length
3001 <= register_size (gdbarch, regnum));
3002
3003 if (readbuf)
3004 {
3005 gdb_byte *ptr = readbuf + info.argloc[0].c_offset;
3006 regcache->cooked_read_part (regnum, 0,
3007 info.argloc[0].c_length,
3008 ptr);
3009 }
3010
3011 if (writebuf)
3012 {
3013 const gdb_byte *ptr = writebuf + info.argloc[0].c_offset;
3014 riscv_regcache_cooked_write (regnum, ptr,
3015 info.argloc[0].c_length,
3016 regcache, call_info.flen);
3017 }
3018
3019 /* A return value in register can have a second part in a
3020 second register. */
3021 if (info.argloc[1].c_length > 0)
3022 {
3023 switch (info.argloc[1].loc_type)
3024 {
3025 case riscv_arg_info::location::in_reg:
3026 regnum = info.argloc[1].loc_data.regno;
3027
3028 gdb_assert ((info.argloc[0].c_length
3029 + info.argloc[1].c_length) <= arg_len);
3030 gdb_assert (info.argloc[1].c_length
3031 <= register_size (gdbarch, regnum));
3032
3033 if (readbuf)
3034 {
3035 readbuf += info.argloc[1].c_offset;
3036 regcache->cooked_read_part (regnum, 0,
3037 info.argloc[1].c_length,
3038 readbuf);
3039 }
3040
3041 if (writebuf)
3042 {
3043 const gdb_byte *ptr
3044 = writebuf + info.argloc[1].c_offset;
3045 riscv_regcache_cooked_write
3046 (regnum, ptr, info.argloc[1].c_length,
3047 regcache, call_info.flen);
3048 }
3049 break;
3050
3051 case riscv_arg_info::location::by_ref:
3052 case riscv_arg_info::location::on_stack:
3053 default:
3054 error (_("invalid argument location"));
3055 break;
3056 }
3057 }
3058 }
3059 break;
3060
3061 /* Return value by reference will have its address in A0. */
3062 case riscv_arg_info::location::by_ref:
3063 {
3064 ULONGEST addr;
3065
3066 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
3067 &addr);
3068 if (readbuf != nullptr)
3069 read_memory (addr, readbuf, info.length);
3070 if (writebuf != nullptr)
3071 write_memory (addr, writebuf, info.length);
3072 }
3073 break;
3074
3075 case riscv_arg_info::location::on_stack:
3076 default:
3077 error (_("invalid argument location"));
3078 break;
3079 }
3080
3081 /* This completes the cast from abi type back to the declared type
3082 in the case that we are reading from the machine. See the
3083 comment at the head of this block for more details. */
3084 if (readbuf != nullptr)
3085 {
3086 struct value *arg_val = value_cast (arg_type, abi_val);
3087 memcpy (old_readbuf, value_contents_raw (arg_val),
3088 TYPE_LENGTH (arg_type));
3089 }
3090 }
3091
3092 switch (info.argloc[0].loc_type)
3093 {
3094 case riscv_arg_info::location::in_reg:
3095 return RETURN_VALUE_REGISTER_CONVENTION;
3096 case riscv_arg_info::location::by_ref:
3097 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
3098 case riscv_arg_info::location::on_stack:
3099 default:
3100 error (_("invalid argument location"));
3101 }
3102 }
3103
3104 /* Implement the frame_align gdbarch method. */
3105
3106 static CORE_ADDR
3107 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
3108 {
3109 return align_down (addr, 16);
3110 }
3111
3112 /* Generate, or return the cached frame cache for the RiscV frame
3113 unwinder. */
3114
3115 static struct riscv_unwind_cache *
3116 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
3117 {
3118 CORE_ADDR pc, start_addr;
3119 struct riscv_unwind_cache *cache;
3120 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3121 int numregs, regno;
3122
3123 if ((*this_cache) != NULL)
3124 return (struct riscv_unwind_cache *) *this_cache;
3125
3126 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
3127 cache->regs = trad_frame_alloc_saved_regs (this_frame);
3128 (*this_cache) = cache;
3129
3130 /* Scan the prologue, filling in the cache. */
3131 start_addr = get_frame_func (this_frame);
3132 pc = get_frame_pc (this_frame);
3133 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
3134
3135 /* We can now calculate the frame base address. */
3136 cache->frame_base
3137 = (get_frame_register_unsigned (this_frame, cache->frame_base_reg)
3138 + cache->frame_base_offset);
3139 if (riscv_debug_unwinder)
3140 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
3141 core_addr_to_string (cache->frame_base),
3142 gdbarch_register_name (gdbarch,
3143 cache->frame_base_reg),
3144 cache->frame_base_offset);
3145
3146 /* The prologue scanner sets the address of registers stored to the stack
3147 as the offset of that register from the frame base. The prologue
3148 scanner doesn't know the actual frame base value, and so is unable to
3149 compute the exact address. We do now know the frame base value, so
3150 update the address of registers stored to the stack. */
3151 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
3152 for (regno = 0; regno < numregs; ++regno)
3153 {
3154 if (cache->regs[regno].is_addr ())
3155 cache->regs[regno].set_addr (cache->regs[regno].addr ()
3156 + cache->frame_base);
3157 }
3158
3159 /* The previous $pc can be found wherever the $ra value can be found.
3160 The previous $ra value is gone, this would have been stored be the
3161 previous frame if required. */
3162 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
3163 cache->regs[RISCV_RA_REGNUM].set_unknown ();
3164
3165 /* Build the frame id. */
3166 cache->this_id = frame_id_build (cache->frame_base, start_addr);
3167
3168 /* The previous $sp value is the frame base value. */
3169 cache->regs[gdbarch_sp_regnum (gdbarch)].set_value (cache->frame_base);
3170
3171 return cache;
3172 }
3173
3174 /* Implement the this_id callback for RiscV frame unwinder. */
3175
3176 static void
3177 riscv_frame_this_id (struct frame_info *this_frame,
3178 void **prologue_cache,
3179 struct frame_id *this_id)
3180 {
3181 struct riscv_unwind_cache *cache;
3182
3183 try
3184 {
3185 cache = riscv_frame_cache (this_frame, prologue_cache);
3186 *this_id = cache->this_id;
3187 }
3188 catch (const gdb_exception_error &ex)
3189 {
3190 /* Ignore errors, this leaves the frame id as the predefined outer
3191 frame id which terminates the backtrace at this point. */
3192 }
3193 }
3194
3195 /* Implement the prev_register callback for RiscV frame unwinder. */
3196
3197 static struct value *
3198 riscv_frame_prev_register (struct frame_info *this_frame,
3199 void **prologue_cache,
3200 int regnum)
3201 {
3202 struct riscv_unwind_cache *cache;
3203
3204 cache = riscv_frame_cache (this_frame, prologue_cache);
3205 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
3206 }
3207
3208 /* Structure defining the RiscV normal frame unwind functions. Since we
3209 are the fallback unwinder (DWARF unwinder is used first), we use the
3210 default frame sniffer, which always accepts the frame. */
3211
3212 static const struct frame_unwind riscv_frame_unwind =
3213 {
3214 /*.type =*/ NORMAL_FRAME,
3215 /*.stop_reason =*/ default_frame_unwind_stop_reason,
3216 /*.this_id =*/ riscv_frame_this_id,
3217 /*.prev_register =*/ riscv_frame_prev_register,
3218 /*.unwind_data =*/ NULL,
3219 /*.sniffer =*/ default_frame_sniffer,
3220 /*.dealloc_cache =*/ NULL,
3221 /*.prev_arch =*/ NULL,
3222 };
3223
3224 /* Extract a set of required target features out of ABFD. If ABFD is
3225 nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state. */
3226
3227 static struct riscv_gdbarch_features
3228 riscv_features_from_bfd (const bfd *abfd)
3229 {
3230 struct riscv_gdbarch_features features;
3231
3232 /* Now try to improve on the defaults by looking at the binary we are
3233 going to execute. We assume the user knows what they are doing and
3234 that the target will match the binary. Remember, this code path is
3235 only used at all if the target hasn't given us a description, so this
3236 is really a last ditched effort to do something sane before giving
3237 up. */
3238 if (abfd != nullptr && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
3239 {
3240 unsigned char eclass = elf_elfheader (abfd)->e_ident[EI_CLASS];
3241 int e_flags = elf_elfheader (abfd)->e_flags;
3242
3243 if (eclass == ELFCLASS32)
3244 features.xlen = 4;
3245 else if (eclass == ELFCLASS64)
3246 features.xlen = 8;
3247 else
3248 internal_error (__FILE__, __LINE__,
3249 _("unknown ELF header class %d"), eclass);
3250
3251 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
3252 features.flen = 8;
3253 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
3254 features.flen = 4;
3255
3256 if (e_flags & EF_RISCV_RVE)
3257 {
3258 if (features.xlen == 8)
3259 {
3260 warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit"));
3261 features.xlen = 4;
3262 }
3263 features.embedded = true;
3264 }
3265 }
3266
3267 return features;
3268 }
3269
3270 /* Find a suitable default target description. Use the contents of INFO,
3271 specifically the bfd object being executed, to guide the selection of a
3272 suitable default target description. */
3273
3274 static const struct target_desc *
3275 riscv_find_default_target_description (const struct gdbarch_info info)
3276 {
3277 /* Extract desired feature set from INFO. */
3278 struct riscv_gdbarch_features features
3279 = riscv_features_from_bfd (info.abfd);
3280
3281 /* If the XLEN field is still 0 then we got nothing useful from INFO.BFD,
3282 maybe there was no bfd object. In this case we fall back to a minimal
3283 useful target with no floating point, the x-register size is selected
3284 based on the architecture from INFO. */
3285 if (features.xlen == 0)
3286 features.xlen = info.bfd_arch_info->bits_per_word == 32 ? 4 : 8;
3287
3288 /* Now build a target description based on the feature set. */
3289 return riscv_lookup_target_description (features);
3290 }
3291
3292 /* Add all the expected register sets into GDBARCH. */
3293
3294 static void
3295 riscv_add_reggroups (struct gdbarch *gdbarch)
3296 {
3297 /* Add predefined register groups. */
3298 reggroup_add (gdbarch, all_reggroup);
3299 reggroup_add (gdbarch, save_reggroup);
3300 reggroup_add (gdbarch, restore_reggroup);
3301 reggroup_add (gdbarch, system_reggroup);
3302 reggroup_add (gdbarch, vector_reggroup);
3303 reggroup_add (gdbarch, general_reggroup);
3304 reggroup_add (gdbarch, float_reggroup);
3305
3306 /* Add RISC-V specific register groups. */
3307 reggroup_add (gdbarch, csr_reggroup);
3308 }
3309
3310 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3311
3312 static int
3313 riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
3314 {
3315 if (reg < RISCV_DWARF_REGNUM_X31)
3316 return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
3317
3318 else if (reg < RISCV_DWARF_REGNUM_F31)
3319 return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
3320
3321 else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR)
3322 return RISCV_FIRST_CSR_REGNUM + (reg - RISCV_DWARF_FIRST_CSR);
3323
3324 return -1;
3325 }
3326
3327 /* Implement the gcc_target_options method. We have to select the arch and abi
3328 from the feature info. We have enough feature info to select the abi, but
3329 not enough info for the arch given all of the possible architecture
3330 extensions. So choose reasonable defaults for now. */
3331
3332 static std::string
3333 riscv_gcc_target_options (struct gdbarch *gdbarch)
3334 {
3335 int isa_xlen = riscv_isa_xlen (gdbarch);
3336 int isa_flen = riscv_isa_flen (gdbarch);
3337 int abi_xlen = riscv_abi_xlen (gdbarch);
3338 int abi_flen = riscv_abi_flen (gdbarch);
3339 std::string target_options;
3340
3341 target_options = "-march=rv";
3342 if (isa_xlen == 8)
3343 target_options += "64";
3344 else
3345 target_options += "32";
3346 if (isa_flen == 8)
3347 target_options += "gc";
3348 else if (isa_flen == 4)
3349 target_options += "imafc";
3350 else
3351 target_options += "imac";
3352
3353 target_options += " -mabi=";
3354 if (abi_xlen == 8)
3355 target_options += "lp64";
3356 else
3357 target_options += "ilp32";
3358 if (abi_flen == 8)
3359 target_options += "d";
3360 else if (abi_flen == 4)
3361 target_options += "f";
3362
3363 /* The gdb loader doesn't handle link-time relaxation relocations. */
3364 target_options += " -mno-relax";
3365
3366 return target_options;
3367 }
3368
3369 /* Call back from tdesc_use_registers, called for each unknown register
3370 found in the target description.
3371
3372 See target-description.h (typedef tdesc_unknown_register_ftype) for a
3373 discussion of the arguments and return values. */
3374
3375 static int
3376 riscv_tdesc_unknown_reg (struct gdbarch *gdbarch, tdesc_feature *feature,
3377 const char *reg_name, int possible_regnum)
3378 {
3379 /* At one point in time GDB had an incorrect default target description
3380 that duplicated the fflags, frm, and fcsr registers in both the FPU
3381 and CSR register sets.
3382
3383 Some targets (QEMU) copied these target descriptions into their source
3384 tree, and so we're currently stuck working with some targets that
3385 declare the same registers twice.
3386
3387 There's not much we can do about this any more. Assuming the target
3388 will direct a request for either register number to the correct
3389 underlying hardware register then it doesn't matter which one GDB
3390 uses, so long as we (GDB) are consistent (so that we don't end up with
3391 invalid cache misses).
3392
3393 As we always scan the FPU registers first, then the CSRs, if the
3394 target has included the offending registers in both sets then we will
3395 always see the FPU copies here, as the CSR versions will replace them
3396 in the register list.
3397
3398 To prevent these duplicates showing up in any of the register list,
3399 record their register numbers here. */
3400 if (strcmp (tdesc_feature_name (feature), riscv_freg_feature.name ()) == 0)
3401 {
3402 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3403 int *regnum_ptr = nullptr;
3404
3405 if (strcmp (reg_name, "fflags") == 0)
3406 regnum_ptr = &tdep->duplicate_fflags_regnum;
3407 else if (strcmp (reg_name, "frm") == 0)
3408 regnum_ptr = &tdep->duplicate_frm_regnum;
3409 else if (strcmp (reg_name, "fcsr") == 0)
3410 regnum_ptr = &tdep->duplicate_fcsr_regnum;
3411
3412 if (regnum_ptr != nullptr)
3413 {
3414 /* This means the register appears more than twice in the target
3415 description. Just let GDB add this as another register.
3416 We'll have duplicates in the register name list, but there's
3417 not much more we can do. */
3418 if (*regnum_ptr != -1)
3419 return -1;
3420
3421 /* Record the number assigned to this register, then return the
3422 number (so it actually gets assigned to this register). */
3423 *regnum_ptr = possible_regnum;
3424 return possible_regnum;
3425 }
3426 }
3427
3428 /* Any unknown registers in the CSR feature are recorded within a single
3429 block so we can easily identify these registers when making choices
3430 about register groups in riscv_register_reggroup_p. */
3431 if (strcmp (tdesc_feature_name (feature), riscv_csr_feature.name ()) == 0)
3432 {
3433 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3434 if (tdep->unknown_csrs_first_regnum == -1)
3435 tdep->unknown_csrs_first_regnum = possible_regnum;
3436 gdb_assert (tdep->unknown_csrs_first_regnum
3437 + tdep->unknown_csrs_count == possible_regnum);
3438 tdep->unknown_csrs_count++;
3439 return possible_regnum;
3440 }
3441
3442 /* Some other unknown register. Don't assign this a number now, it will
3443 be assigned a number automatically later by the target description
3444 handling code. */
3445 return -1;
3446 }
3447
3448 /* Implement the gnu_triplet_regexp method. A single compiler supports both
3449 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
3450 recommended) riscv. */
3451
3452 static const char *
3453 riscv_gnu_triplet_regexp (struct gdbarch *gdbarch)
3454 {
3455 return "riscv(32|64)?";
3456 }
3457
3458 /* Initialize the current architecture based on INFO. If possible,
3459 re-use an architecture from ARCHES, which is a list of
3460 architectures already created during this debugging session.
3461
3462 Called e.g. at program startup, when reading a core file, and when
3463 reading a binary file. */
3464
3465 static struct gdbarch *
3466 riscv_gdbarch_init (struct gdbarch_info info,
3467 struct gdbarch_list *arches)
3468 {
3469 struct gdbarch *gdbarch;
3470 struct gdbarch_tdep *tdep;
3471 struct riscv_gdbarch_features features;
3472 const struct target_desc *tdesc = info.target_desc;
3473
3474 /* Ensure we always have a target description. */
3475 if (!tdesc_has_registers (tdesc))
3476 tdesc = riscv_find_default_target_description (info);
3477 gdb_assert (tdesc != nullptr);
3478
3479 if (riscv_debug_gdbarch)
3480 fprintf_unfiltered (gdb_stdlog, "Have got a target description\n");
3481
3482 tdesc_arch_data_up tdesc_data = tdesc_data_alloc ();
3483 std::vector<riscv_pending_register_alias> pending_aliases;
3484
3485 bool valid_p = (riscv_xreg_feature.check (tdesc, tdesc_data.get (),
3486 &pending_aliases, &features)
3487 && riscv_freg_feature.check (tdesc, tdesc_data.get (),
3488 &pending_aliases, &features)
3489 && riscv_virtual_feature.check (tdesc, tdesc_data.get (),
3490 &pending_aliases, &features)
3491 && riscv_csr_feature.check (tdesc, tdesc_data.get (),
3492 &pending_aliases, &features));
3493 if (!valid_p)
3494 {
3495 if (riscv_debug_gdbarch)
3496 fprintf_unfiltered (gdb_stdlog, "Target description is not valid\n");
3497 return NULL;
3498 }
3499
3500 /* Have a look at what the supplied (if any) bfd object requires of the
3501 target, then check that this matches with what the target is
3502 providing. */
3503 struct riscv_gdbarch_features abi_features
3504 = riscv_features_from_bfd (info.abfd);
3505
3506 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3507 features from the INFO object. In this case we just treat the
3508 hardware features as defining the abi. */
3509 if (abi_features.xlen == 0)
3510 abi_features = features;
3511
3512 /* In theory a binary compiled for RV32 could run on an RV64 target,
3513 however, this has not been tested in GDB yet, so for now we require
3514 that the requested xlen match the targets xlen. */
3515 if (abi_features.xlen != features.xlen)
3516 error (_("bfd requires xlen %d, but target has xlen %d"),
3517 abi_features.xlen, features.xlen);
3518 /* We do support running binaries compiled for 32-bit float on targets
3519 with 64-bit float, so we only complain if the binary requires more
3520 than the target has available. */
3521 if (abi_features.flen > features.flen)
3522 error (_("bfd requires flen %d, but target has flen %d"),
3523 abi_features.flen, features.flen);
3524
3525 /* Find a candidate among the list of pre-declared architectures. */
3526 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3527 arches != NULL;
3528 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3529 {
3530 /* Check that the feature set of the ARCHES matches the feature set
3531 we are looking for. If it doesn't then we can't reuse this
3532 gdbarch. */
3533 struct gdbarch_tdep *other_tdep = gdbarch_tdep (arches->gdbarch);
3534
3535 if (other_tdep->isa_features != features
3536 || other_tdep->abi_features != abi_features)
3537 continue;
3538
3539 break;
3540 }
3541
3542 if (arches != NULL)
3543 return arches->gdbarch;
3544
3545 /* None found, so create a new architecture from the information provided. */
3546 tdep = new (struct gdbarch_tdep);
3547 gdbarch = gdbarch_alloc (&info, tdep);
3548 tdep->isa_features = features;
3549 tdep->abi_features = abi_features;
3550
3551 /* Target data types. */
3552 set_gdbarch_short_bit (gdbarch, 16);
3553 set_gdbarch_int_bit (gdbarch, 32);
3554 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
3555 set_gdbarch_long_long_bit (gdbarch, 64);
3556 set_gdbarch_float_bit (gdbarch, 32);
3557 set_gdbarch_double_bit (gdbarch, 64);
3558 set_gdbarch_long_double_bit (gdbarch, 128);
3559 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
3560 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
3561 set_gdbarch_char_signed (gdbarch, 0);
3562 set_gdbarch_type_align (gdbarch, riscv_type_align);
3563
3564 /* Information about the target architecture. */
3565 set_gdbarch_return_value (gdbarch, riscv_return_value);
3566 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
3567 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
3568 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3569
3570 /* Functions to analyze frames. */
3571 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
3572 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3573 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
3574
3575 /* Functions handling dummy frames. */
3576 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
3577 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
3578 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
3579
3580 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3581 unwinder. */
3582 dwarf2_append_unwinders (gdbarch);
3583 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
3584
3585 /* Register architecture. */
3586 riscv_add_reggroups (gdbarch);
3587
3588 /* Internal <-> external register number maps. */
3589 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum);
3590
3591 /* We reserve all possible register numbers for the known registers.
3592 This means the target description mechanism will add any target
3593 specific registers after this number. This helps make debugging GDB
3594 just a little easier. */
3595 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
3596
3597 /* We don't have to provide the count of 0 here (its the default) but
3598 include this line to make it explicit that, right now, we don't have
3599 any pseudo registers on RISC-V. */
3600 set_gdbarch_num_pseudo_regs (gdbarch, 0);
3601
3602 /* Some specific register numbers GDB likes to know about. */
3603 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
3604 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
3605
3606 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
3607
3608 /* Finalise the target description registers. */
3609 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data),
3610 riscv_tdesc_unknown_reg);
3611
3612 /* Override the register type callback setup by the target description
3613 mechanism. This allows us to provide special type for floating point
3614 registers. */
3615 set_gdbarch_register_type (gdbarch, riscv_register_type);
3616
3617 /* Override the register name callback setup by the target description
3618 mechanism. This allows us to force our preferred names for the
3619 registers, no matter what the target description called them. */
3620 set_gdbarch_register_name (gdbarch, riscv_register_name);
3621
3622 /* Override the register group callback setup by the target description
3623 mechanism. This allows us to force registers into the groups we
3624 want, ignoring what the target tells us. */
3625 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
3626
3627 /* Create register aliases for alternative register names. We only
3628 create aliases for registers which were mentioned in the target
3629 description. */
3630 for (const auto &alias : pending_aliases)
3631 alias.create (gdbarch);
3632
3633 /* Compile command hooks. */
3634 set_gdbarch_gcc_target_options (gdbarch, riscv_gcc_target_options);
3635 set_gdbarch_gnu_triplet_regexp (gdbarch, riscv_gnu_triplet_regexp);
3636
3637 /* Hook in OS ABI-specific overrides, if they have been registered. */
3638 gdbarch_init_osabi (info, gdbarch);
3639
3640 register_riscv_ravenscar_ops (gdbarch);
3641
3642 return gdbarch;
3643 }
3644
3645 /* This decodes the current instruction and determines the address of the
3646 next instruction. */
3647
3648 static CORE_ADDR
3649 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
3650 {
3651 struct gdbarch *gdbarch = regcache->arch ();
3652 struct riscv_insn insn;
3653 CORE_ADDR next_pc;
3654
3655 insn.decode (gdbarch, pc);
3656 next_pc = pc + insn.length ();
3657
3658 if (insn.opcode () == riscv_insn::JAL)
3659 next_pc = pc + insn.imm_signed ();
3660 else if (insn.opcode () == riscv_insn::JALR)
3661 {
3662 LONGEST source;
3663 regcache->cooked_read (insn.rs1 (), &source);
3664 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
3665 }
3666 else if (insn.opcode () == riscv_insn::BEQ)
3667 {
3668 LONGEST src1, src2;
3669 regcache->cooked_read (insn.rs1 (), &src1);
3670 regcache->cooked_read (insn.rs2 (), &src2);
3671 if (src1 == src2)
3672 next_pc = pc + insn.imm_signed ();
3673 }
3674 else if (insn.opcode () == riscv_insn::BNE)
3675 {
3676 LONGEST src1, src2;
3677 regcache->cooked_read (insn.rs1 (), &src1);
3678 regcache->cooked_read (insn.rs2 (), &src2);
3679 if (src1 != src2)
3680 next_pc = pc + insn.imm_signed ();
3681 }
3682 else if (insn.opcode () == riscv_insn::BLT)
3683 {
3684 LONGEST src1, src2;
3685 regcache->cooked_read (insn.rs1 (), &src1);
3686 regcache->cooked_read (insn.rs2 (), &src2);
3687 if (src1 < src2)
3688 next_pc = pc + insn.imm_signed ();
3689 }
3690 else if (insn.opcode () == riscv_insn::BGE)
3691 {
3692 LONGEST src1, src2;
3693 regcache->cooked_read (insn.rs1 (), &src1);
3694 regcache->cooked_read (insn.rs2 (), &src2);
3695 if (src1 >= src2)
3696 next_pc = pc + insn.imm_signed ();
3697 }
3698 else if (insn.opcode () == riscv_insn::BLTU)
3699 {
3700 ULONGEST src1, src2;
3701 regcache->cooked_read (insn.rs1 (), &src1);
3702 regcache->cooked_read (insn.rs2 (), &src2);
3703 if (src1 < src2)
3704 next_pc = pc + insn.imm_signed ();
3705 }
3706 else if (insn.opcode () == riscv_insn::BGEU)
3707 {
3708 ULONGEST src1, src2;
3709 regcache->cooked_read (insn.rs1 (), &src1);
3710 regcache->cooked_read (insn.rs2 (), &src2);
3711 if (src1 >= src2)
3712 next_pc = pc + insn.imm_signed ();
3713 }
3714
3715 return next_pc;
3716 }
3717
3718 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3719 for the end of the sequence and put the breakpoint there. */
3720
3721 static bool
3722 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
3723 CORE_ADDR *next_pc)
3724 {
3725 struct gdbarch *gdbarch = regcache->arch ();
3726 struct riscv_insn insn;
3727 CORE_ADDR cur_step_pc = pc;
3728 CORE_ADDR last_addr = 0;
3729
3730 /* First instruction has to be a load reserved. */
3731 insn.decode (gdbarch, cur_step_pc);
3732 if (insn.opcode () != riscv_insn::LR)
3733 return false;
3734 cur_step_pc = cur_step_pc + insn.length ();
3735
3736 /* Next instruction should be branch to exit. */
3737 insn.decode (gdbarch, cur_step_pc);
3738 if (insn.opcode () != riscv_insn::BNE)
3739 return false;
3740 last_addr = cur_step_pc + insn.imm_signed ();
3741 cur_step_pc = cur_step_pc + insn.length ();
3742
3743 /* Next instruction should be store conditional. */
3744 insn.decode (gdbarch, cur_step_pc);
3745 if (insn.opcode () != riscv_insn::SC)
3746 return false;
3747 cur_step_pc = cur_step_pc + insn.length ();
3748
3749 /* Next instruction should be branch to start. */
3750 insn.decode (gdbarch, cur_step_pc);
3751 if (insn.opcode () != riscv_insn::BNE)
3752 return false;
3753 if (pc != (cur_step_pc + insn.imm_signed ()))
3754 return false;
3755 cur_step_pc = cur_step_pc + insn.length ();
3756
3757 /* We should now be at the end of the sequence. */
3758 if (cur_step_pc != last_addr)
3759 return false;
3760
3761 *next_pc = cur_step_pc;
3762 return true;
3763 }
3764
3765 /* This is called just before we want to resume the inferior, if we want to
3766 single-step it but there is no hardware or kernel single-step support. We
3767 find the target of the coming instruction and breakpoint it. */
3768
3769 std::vector<CORE_ADDR>
3770 riscv_software_single_step (struct regcache *regcache)
3771 {
3772 CORE_ADDR pc, next_pc;
3773
3774 pc = regcache_read_pc (regcache);
3775
3776 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
3777 return {next_pc};
3778
3779 next_pc = riscv_next_pc (regcache, pc);
3780
3781 return {next_pc};
3782 }
3783
3784 /* Create RISC-V specific reggroups. */
3785
3786 static void
3787 riscv_init_reggroups ()
3788 {
3789 csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
3790 }
3791
3792 /* See riscv-tdep.h. */
3793
3794 void
3795 riscv_supply_regset (const struct regset *regset,
3796 struct regcache *regcache, int regnum,
3797 const void *regs, size_t len)
3798 {
3799 regcache->supply_regset (regset, regnum, regs, len);
3800
3801 if (regnum == -1 || regnum == RISCV_ZERO_REGNUM)
3802 regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
3803
3804 if (regnum == -1 || regnum == RISCV_CSR_FFLAGS_REGNUM
3805 || regnum == RISCV_CSR_FRM_REGNUM)
3806 {
3807 int fcsr_regnum = RISCV_CSR_FCSR_REGNUM;
3808
3809 /* Ensure that FCSR has been read into REGCACHE. */
3810 if (regnum != -1)
3811 regcache->supply_regset (regset, fcsr_regnum, regs, len);
3812
3813 /* Grab the FCSR value if it is now in the regcache. We must check
3814 the status first as, if the register was not supplied by REGSET,
3815 this call will trigger a recursive attempt to fetch the
3816 registers. */
3817 if (regcache->get_register_status (fcsr_regnum) == REG_VALID)
3818 {
3819 ULONGEST fcsr_val;
3820 regcache->raw_read (fcsr_regnum, &fcsr_val);
3821
3822 /* Extract the fflags and frm values. */
3823 ULONGEST fflags_val = fcsr_val & 0x1f;
3824 ULONGEST frm_val = (fcsr_val >> 5) & 0x7;
3825
3826 /* And supply these if needed. */
3827 if (regnum == -1 || regnum == RISCV_CSR_FFLAGS_REGNUM)
3828 regcache->raw_supply_integer (RISCV_CSR_FFLAGS_REGNUM,
3829 (gdb_byte *) &fflags_val,
3830 sizeof (fflags_val),
3831 /* is_signed */ false);
3832
3833 if (regnum == -1 || regnum == RISCV_CSR_FRM_REGNUM)
3834 regcache->raw_supply_integer (RISCV_CSR_FRM_REGNUM,
3835 (gdb_byte *)&frm_val,
3836 sizeof (fflags_val),
3837 /* is_signed */ false);
3838 }
3839 }
3840 }
3841
3842 void _initialize_riscv_tdep ();
3843 void
3844 _initialize_riscv_tdep ()
3845 {
3846 riscv_init_reggroups ();
3847
3848 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
3849
3850 /* Add root prefix command for all "set debug riscv" and "show debug
3851 riscv" commands. */
3852 add_basic_prefix_cmd ("riscv", no_class,
3853 _("RISC-V specific debug commands."),
3854 &setdebugriscvcmdlist, "set debug riscv ", 0,
3855 &setdebuglist);
3856
3857 add_show_prefix_cmd ("riscv", no_class,
3858 _("RISC-V specific debug commands."),
3859 &showdebugriscvcmdlist, "show debug riscv ", 0,
3860 &showdebuglist);
3861
3862 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
3863 &riscv_debug_breakpoints, _("\
3864 Set riscv breakpoint debugging."), _("\
3865 Show riscv breakpoint debugging."), _("\
3866 When non-zero, print debugging information for the riscv specific parts\n\
3867 of the breakpoint mechanism."),
3868 NULL,
3869 show_riscv_debug_variable,
3870 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3871
3872 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
3873 &riscv_debug_infcall, _("\
3874 Set riscv inferior call debugging."), _("\
3875 Show riscv inferior call debugging."), _("\
3876 When non-zero, print debugging information for the riscv specific parts\n\
3877 of the inferior call mechanism."),
3878 NULL,
3879 show_riscv_debug_variable,
3880 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3881
3882 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
3883 &riscv_debug_unwinder, _("\
3884 Set riscv stack unwinding debugging."), _("\
3885 Show riscv stack unwinding debugging."), _("\
3886 When non-zero, print debugging information for the riscv specific parts\n\
3887 of the stack unwinding mechanism."),
3888 NULL,
3889 show_riscv_debug_variable,
3890 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3891
3892 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance,
3893 &riscv_debug_gdbarch, _("\
3894 Set riscv gdbarch initialisation debugging."), _("\
3895 Show riscv gdbarch initialisation debugging."), _("\
3896 When non-zero, print debugging information for the riscv gdbarch\n\
3897 initialisation process."),
3898 NULL,
3899 show_riscv_debug_variable,
3900 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3901
3902 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3903 add_basic_prefix_cmd ("riscv", no_class,
3904 _("RISC-V specific commands."),
3905 &setriscvcmdlist, "set riscv ", 0, &setlist);
3906
3907 add_show_prefix_cmd ("riscv", no_class,
3908 _("RISC-V specific commands."),
3909 &showriscvcmdlist, "show riscv ", 0, &showlist);
3910
3911
3912 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
3913 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
3914 &use_compressed_breakpoints,
3915 _("\
3916 Set debugger's use of compressed breakpoints."), _(" \
3917 Show debugger's use of compressed breakpoints."), _("\
3918 Debugging compressed code requires compressed breakpoints to be used. If\n\
3919 left to 'auto' then gdb will use them if the existing instruction is a\n\
3920 compressed instruction. If that doesn't give the correct behavior, then\n\
3921 this option can be used."),
3922 NULL,
3923 show_use_compressed_breakpoints,
3924 &setriscvcmdlist,
3925 &showriscvcmdlist);
3926 }
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