1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
7 and by Todd Snyder <todd@bluespec.com>
8 and by Mike Frysinger <vapier@gentoo.org>.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
37 #include "arch-utils.h"
40 #include "riscv-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/riscv.h"
44 #include "elf/riscv.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
52 #include "floatformat.h"
54 #include "target-descriptions.h"
55 #include "dwarf2-frame.h"
56 #include "user-regs.h"
58 #include "common-defs.h"
59 #include "opcode/riscv-opc.h"
60 #include "cli/cli-decode.h"
63 /* The stack must be 16-byte aligned. */
64 #define SP_ALIGNMENT 16
66 /* Forward declarations. */
67 static bool riscv_has_feature (struct gdbarch
*gdbarch
, char feature
);
68 struct riscv_inferior_data
;
69 struct riscv_inferior_data
* riscv_inferior_data (struct inferior
*const inf
);
71 /* Define a series of is_XXX_insn functions to check if the value INSN
72 is an instance of instruction XXX. */
73 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
74 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
76 return (insn & INSN_MASK) == INSN_MATCH; \
78 #include "opcode/riscv-opc.h"
81 /* Per inferior information for RiscV. */
83 struct riscv_inferior_data
85 /* True when MISA_VALUE is valid, otherwise false. */
88 /* If MISA_READ is true then MISA_VALUE holds the value of the MISA
89 register read from the target. */
93 /* Key created when the RiscV per-inferior data is registered. */
95 static const struct inferior_data
*riscv_inferior_data_reg
;
97 /* Architectural name for core registers. */
99 static const char * const riscv_gdb_reg_names
[RISCV_LAST_FP_REGNUM
+ 1] =
101 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
102 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
103 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
104 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
106 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
107 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
108 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
109 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
112 /* Maps "pretty" register names onto their GDB register number. */
114 struct register_alias
116 /* The register alias. Usually more descriptive than the
117 architectural name of the register. */
120 /* The GDB register number. */
124 /* Table of register aliases. */
126 static const struct register_alias riscv_register_aliases
[] =
194 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
195 #include "opcode/riscv-opc.h"
199 /* Controls whether we place compressed breakpoints or not. When in auto
200 mode GDB tries to determine if the target supports compressed
201 breakpoints, and uses them if it does. */
203 static enum auto_boolean use_compressed_breakpoints
;
205 /* The show callback for 'show riscv use-compressed-breakpoints'. */
208 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
209 struct cmd_list_element
*c
,
212 const char *additional_info
;
213 struct gdbarch
*gdbarch
= target_gdbarch ();
215 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
216 if (riscv_has_feature (gdbarch
, 'C'))
217 additional_info
= _(" (currently on)");
219 additional_info
= _(" (currently off)");
221 additional_info
= "";
223 fprintf_filtered (file
,
224 _("Debugger's use of compressed breakpoints is set "
225 "to %s%s.\n"), value
, additional_info
);
228 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
230 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
231 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
233 /* The show callback for the 'show riscv' prefix command. */
236 show_riscv_command (const char *args
, int from_tty
)
238 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
241 /* The set callback for the 'set riscv' prefix command. */
244 set_riscv_command (const char *args
, int from_tty
)
247 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
248 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
251 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
253 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
254 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
256 /* The show callback for the 'show debug riscv' prefix command. */
259 show_debug_riscv_command (const char *args
, int from_tty
)
261 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
264 /* The set callback for the 'set debug riscv' prefix command. */
267 set_debug_riscv_command (const char *args
, int from_tty
)
270 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
271 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
274 /* The show callback for all 'show debug riscv VARNAME' variables. */
277 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
278 struct cmd_list_element
*c
,
281 fprintf_filtered (file
,
282 _("RiscV debug variable `%s' is set to: %s\n"),
286 /* When this is set to non-zero debugging information about inferior calls
289 static unsigned int riscv_debug_infcall
= 0;
291 /* Read the MISA register from the target. The register will only be read
292 once, and the value read will be cached. If the register can't be read
293 from the target then a default value (0) will be returned. If the
294 pointer READ_P is not null, then the bool pointed to is updated to
295 indicate if the value returned was read from the target (true) or is the
299 riscv_read_misa_reg (bool *read_p
)
301 struct riscv_inferior_data
*inf_data
302 = riscv_inferior_data (current_inferior ());
304 if (!inf_data
->misa_read
&& target_has_registers
)
307 struct frame_info
*frame
= get_current_frame ();
311 value
= get_frame_register_unsigned (frame
, RISCV_CSR_MISA_REGNUM
);
313 CATCH (ex
, RETURN_MASK_ERROR
)
315 /* Old cores might have MISA located at a different offset. */
316 value
= get_frame_register_unsigned (frame
,
317 RISCV_CSR_LEGACY_MISA_REGNUM
);
321 inf_data
->misa_read
= true;
322 inf_data
->misa_value
= value
;
325 if (read_p
!= nullptr)
326 *read_p
= inf_data
->misa_read
;
328 return inf_data
->misa_value
;
331 /* Return true if FEATURE is available for the architecture GDBARCH. The
332 FEATURE should be one of the single character feature codes described in
333 the RiscV ISA manual, these are between 'A' and 'Z'. */
336 riscv_has_feature (struct gdbarch
*gdbarch
, char feature
)
338 bool have_read_misa
= false;
341 gdb_assert (feature
>= 'A' && feature
<= 'Z');
343 /* It would be nice to always check with the real target where possible,
344 however, for compressed instructions this is a bad idea.
346 The call to `set_gdbarch_decr_pc_after_break' is made just once per
347 GDBARCH and we decide at that point if we should decrement by 2 or 4
348 bytes based on whether the BFD has compressed instruction support or
351 If the BFD was not compiled with compressed instruction support, but we
352 are running on a target with compressed instructions then we might
353 place a 4-byte breakpoint, then decrement the $pc by 2 bytes leading to
356 It's safer if we just make decisions about compressed instruction
357 support based on the BFD. */
359 misa
= riscv_read_misa_reg (&have_read_misa
);
360 if (!have_read_misa
|| misa
== 0)
361 misa
= gdbarch_tdep (gdbarch
)->core_features
;
363 return (misa
& (1 << (feature
- 'A'))) != 0;
366 /* Return the width in bytes of the general purpose registers for GDBARCH.
367 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
371 riscv_isa_xlen (struct gdbarch
*gdbarch
)
373 switch (gdbarch_tdep (gdbarch
)->abi
.fields
.base_len
)
376 warning (_("unknown xlen size, assuming 4 bytes"));
386 /* Return the width in bytes of the floating point registers for GDBARCH.
387 If this architecture has no floating point registers, then return 0.
388 Possible values are 4, 8, or 16 for depending on which of single, double
389 or quad floating point support is available. */
392 riscv_isa_flen (struct gdbarch
*gdbarch
)
394 if (riscv_has_feature (gdbarch
, 'Q'))
396 else if (riscv_has_feature (gdbarch
, 'D'))
398 else if (riscv_has_feature (gdbarch
, 'F'))
404 /* Return true if the target for GDBARCH has floating point hardware. */
407 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
409 return (riscv_isa_flen (gdbarch
) > 0);
412 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
415 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
417 return (gdbarch_tdep (gdbarch
)->abi
.fields
.float_abi
!= 0);
420 /* Implement the breakpoint_kind_from_pc gdbarch method. */
423 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
425 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
427 if (riscv_has_feature (gdbarch
, 'C'))
432 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
438 /* Implement the sw_breakpoint_from_kind gdbarch method. */
440 static const gdb_byte
*
441 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
443 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
444 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
454 gdb_assert_not_reached ("unhandled breakpoint kind");
458 /* Callback function for user_reg_add. */
460 static struct value
*
461 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
463 const int *reg_p
= (const int *) baton
;
464 return value_of_register (*reg_p
, frame
);
467 /* Implement the register_name gdbarch method. */
470 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
472 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
473 return tdesc_register_name (gdbarch
, regnum
);
475 /* Prefer to use the alias. */
476 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_REGNUM
)
480 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
481 if (regnum
== riscv_register_aliases
[i
].regnum
)
482 return riscv_register_aliases
[i
].name
;
485 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
486 return riscv_gdb_reg_names
[regnum
];
488 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
492 sprintf (buf
, "csr%d", regnum
- RISCV_FIRST_CSR_REGNUM
);
496 if (regnum
== RISCV_PRIV_REGNUM
)
502 /* Implement the register_type gdbarch method. */
505 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
509 if (regnum
< RISCV_FIRST_FP_REGNUM
)
511 if (regnum
== gdbarch_pc_regnum (gdbarch
)
512 || regnum
== RISCV_RA_REGNUM
)
513 return builtin_type (gdbarch
)->builtin_func_ptr
;
515 if (regnum
== RISCV_FP_REGNUM
516 || regnum
== RISCV_SP_REGNUM
517 || regnum
== RISCV_GP_REGNUM
518 || regnum
== RISCV_TP_REGNUM
)
519 return builtin_type (gdbarch
)->builtin_data_ptr
;
521 /* Remaining GPRs vary in size based on the current ISA. */
522 regsize
= riscv_isa_xlen (gdbarch
);
526 return builtin_type (gdbarch
)->builtin_uint32
;
528 return builtin_type (gdbarch
)->builtin_uint64
;
530 return builtin_type (gdbarch
)->builtin_uint128
;
532 internal_error (__FILE__
, __LINE__
,
533 _("unknown isa regsize %i"), regsize
);
536 else if (regnum
<= RISCV_LAST_FP_REGNUM
)
538 regsize
= riscv_isa_xlen (gdbarch
);
542 return builtin_type (gdbarch
)->builtin_float
;
544 return builtin_type (gdbarch
)->builtin_double
;
546 return builtin_type (gdbarch
)->builtin_long_double
;
548 internal_error (__FILE__
, __LINE__
,
549 _("unknown isa regsize %i"), regsize
);
552 else if (regnum
== RISCV_PRIV_REGNUM
)
553 return builtin_type (gdbarch
)->builtin_int8
;
556 if (regnum
== RISCV_CSR_FFLAGS_REGNUM
557 || regnum
== RISCV_CSR_FRM_REGNUM
558 || regnum
== RISCV_CSR_FCSR_REGNUM
)
559 return builtin_type (gdbarch
)->builtin_int32
;
561 regsize
= riscv_isa_xlen (gdbarch
);
565 return builtin_type (gdbarch
)->builtin_int32
;
567 return builtin_type (gdbarch
)->builtin_int64
;
569 return builtin_type (gdbarch
)->builtin_int128
;
571 internal_error (__FILE__
, __LINE__
,
572 _("unknown isa regsize %i"), regsize
);
577 /* Helper for riscv_print_registers_info, prints info for a single register
581 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
582 struct ui_file
*file
,
583 struct frame_info
*frame
,
586 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
587 struct value
*val
= value_of_register (regnum
, frame
);
588 struct type
*regtype
= value_type (val
);
589 int print_raw_format
;
590 enum tab_stops
{ value_column_1
= 15 };
592 fputs_filtered (name
, file
);
593 print_spaces_filtered (value_column_1
- strlen (name
), file
);
595 print_raw_format
= (value_entirely_available (val
)
596 && !value_optimized_out (val
));
598 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
)
600 struct value_print_options opts
;
601 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
602 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
604 get_user_print_options (&opts
);
608 value_embedded_offset (val
), 0,
609 file
, 0, val
, &opts
, current_language
);
611 if (print_raw_format
)
613 fprintf_filtered (file
, "\t(raw ");
614 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
616 fprintf_filtered (file
, ")");
621 struct value_print_options opts
;
623 /* Print the register in hex. */
624 get_formatted_print_options (&opts
, 'x');
627 value_embedded_offset (val
), 0,
628 file
, 0, val
, &opts
, current_language
);
630 if (print_raw_format
)
632 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
635 int size
= register_size (gdbarch
, regnum
);
638 d
= value_as_long (val
);
640 fprintf_filtered (file
,
641 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
642 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
643 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
644 (int) ((d
>> (xlen
- 1)) & 0x1),
645 (int) ((d
>> 24) & 0x1f),
646 (int) ((d
>> 19) & 0x1),
647 (int) ((d
>> 18) & 0x1),
648 (int) ((d
>> 17) & 0x1),
649 (int) ((d
>> 15) & 0x3),
650 (int) ((d
>> 13) & 0x3),
651 (int) ((d
>> 11) & 0x3),
652 (int) ((d
>> 9) & 0x3),
653 (int) ((d
>> 8) & 0x1),
654 (int) ((d
>> 7) & 0x1),
655 (int) ((d
>> 6) & 0x1),
656 (int) ((d
>> 5) & 0x1),
657 (int) ((d
>> 4) & 0x1),
658 (int) ((d
>> 3) & 0x1),
659 (int) ((d
>> 2) & 0x1),
660 (int) ((d
>> 1) & 0x1),
661 (int) ((d
>> 0) & 0x1));
663 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
669 d
= value_as_long (val
);
673 for (; base
> 0; base
--)
675 fprintf_filtered (file
, "\tRV%d", xlen
);
677 for (i
= 0; i
< 26; i
++)
680 fprintf_filtered (file
, "%c", 'A' + i
);
683 else if (regnum
== RISCV_CSR_FCSR_REGNUM
684 || regnum
== RISCV_CSR_FFLAGS_REGNUM
685 || regnum
== RISCV_CSR_FRM_REGNUM
)
689 d
= value_as_long (val
);
691 fprintf_filtered (file
, "\t");
692 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
693 fprintf_filtered (file
,
694 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
695 (int) ((d
>> 5) & 0x7),
696 (int) ((d
>> 4) & 0x1),
697 (int) ((d
>> 3) & 0x1),
698 (int) ((d
>> 2) & 0x1),
699 (int) ((d
>> 1) & 0x1),
700 (int) ((d
>> 0) & 0x1));
702 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
704 static const char * const sfrm
[] =
706 "RNE (round to nearest; ties to even)",
707 "RTZ (Round towards zero)",
708 "RDN (Round down towards -INF)",
709 "RUP (Round up towards +INF)",
710 "RMM (Round to nearest; ties to max magnitude)",
713 "dynamic rounding mode",
715 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
716 ? (d
>> 5) : d
) & 0x3;
718 fprintf_filtered (file
, "%sFRM:%i [%s]",
719 (regnum
== RISCV_CSR_FCSR_REGNUM
724 else if (regnum
== RISCV_PRIV_REGNUM
)
729 d
= value_as_long (val
);
734 static const char * const sprv
[] =
741 fprintf_filtered (file
, "\tprv:%d [%s]",
745 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
749 /* If not a vector register, print it also according to its
751 if (TYPE_VECTOR (regtype
) == 0)
753 get_user_print_options (&opts
);
755 fprintf_filtered (file
, "\t");
757 value_embedded_offset (val
), 0,
758 file
, 0, val
, &opts
, current_language
);
763 fprintf_filtered (file
, "\n");
766 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
770 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
771 struct reggroup
*reggroup
)
777 /* Used by 'info registers' and 'info registers <groupname>'. */
779 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
780 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
783 if (reggroup
== all_reggroup
)
785 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
787 /* Only include CSRs that have aliases. */
788 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
790 if (regnum
== riscv_register_aliases
[i
].regnum
)
795 else if (reggroup
== float_reggroup
)
796 return ((regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
797 || (regnum
== RISCV_CSR_FCSR_REGNUM
798 || regnum
== RISCV_CSR_FFLAGS_REGNUM
799 || regnum
== RISCV_CSR_FRM_REGNUM
));
800 else if (reggroup
== general_reggroup
)
801 return regnum
< RISCV_FIRST_FP_REGNUM
;
802 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
804 if (riscv_has_fp_regs (gdbarch
))
805 return regnum
<= RISCV_LAST_FP_REGNUM
;
807 return regnum
< RISCV_FIRST_FP_REGNUM
;
809 else if (reggroup
== system_reggroup
)
811 if (regnum
== RISCV_PRIV_REGNUM
)
813 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
815 /* Only include CSRs that have aliases. */
816 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
818 if (regnum
== riscv_register_aliases
[i
].regnum
)
823 else if (reggroup
== vector_reggroup
)
829 /* Implement the print_registers_info gdbarch method. This is used by
830 'info registers' and 'info all-registers'. */
833 riscv_print_registers_info (struct gdbarch
*gdbarch
,
834 struct ui_file
*file
,
835 struct frame_info
*frame
,
836 int regnum
, int print_all
)
840 /* Print one specified register. */
841 gdb_assert (regnum
<= RISCV_LAST_REGNUM
);
842 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
843 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
844 error (_("Not a valid register for the current processor type"));
845 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
849 struct reggroup
*reggroup
;
852 reggroup
= all_reggroup
;
854 reggroup
= general_reggroup
;
856 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
858 /* Zero never changes, so might as well hide by default. */
859 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
862 /* Registers with no name are not valid on this ISA. */
863 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
864 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
867 /* Is the register in the group we're interested in? */
868 if (!riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
))
871 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
876 /* Class that handles one decoded RiscV instruction. */
882 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
885 /* Unknown value is used at initialisation time. */
888 /* These instructions are all the ones we are interested in during the
899 /* Other instructions are not interesting during the prologue scan, and
914 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
916 /* Get the length of the instruction in bytes. */
920 /* Get the opcode for this instruction. */
921 enum opcode
opcode () const
924 /* Get destination register field for this instruction. This is only
925 valid if the OPCODE implies there is such a field for this
930 /* Get the RS1 register field for this instruction. This is only valid
931 if the OPCODE implies there is such a field for this instruction. */
935 /* Get the RS2 register field for this instruction. This is only valid
936 if the OPCODE implies there is such a field for this instruction. */
940 /* Get the immediate for this instruction in signed form. This is only
941 valid if the OPCODE implies there is such a field for this
943 int imm_signed () const
948 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
949 int decode_register_index (unsigned long opcode
, int offset
)
951 return (opcode
>> offset
) & 0x1F;
954 /* Helper for DECODE, decode 32-bit R-type instruction. */
955 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
958 m_rd
= decode_register_index (ival
, OP_SH_RD
);
959 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
960 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
963 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
964 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
967 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
968 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
971 /* Helper for DECODE, decode 32-bit I-type instruction. */
972 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
975 m_rd
= decode_register_index (ival
, OP_SH_RD
);
976 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
977 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
980 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
981 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
984 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
985 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
988 /* Helper for DECODE, decode 32-bit S-type instruction. */
989 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
992 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
993 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
994 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
997 /* Helper for DECODE, decode 32-bit U-type instruction. */
998 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1001 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1002 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1005 /* Fetch instruction from target memory at ADDR, return the content of
1006 the instruction, and update LEN with the instruction length. */
1007 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1008 CORE_ADDR addr
, int *len
);
1010 /* The length of the instruction in bytes. Should be 2 or 4. */
1013 /* The instruction opcode. */
1014 enum opcode m_opcode
;
1016 /* The three possible registers an instruction might reference. Not
1017 every instruction fills in all of these registers. Which fields are
1018 valid depends on the opcode. The naming of these fields matches the
1019 naming in the riscv isa manual. */
1024 /* Possible instruction immediate. This is only valid if the instruction
1025 format contains an immediate, not all instruction, whether this is
1026 valid depends on the opcode. Despite only having one format for now
1027 the immediate is packed into a union, later instructions might require
1028 an unsigned formatted immediate, having the union in place now will
1029 reduce the need for code churn later. */
1030 union riscv_insn_immediate
1032 riscv_insn_immediate ()
1042 /* Fetch instruction from target memory at ADDR, return the content of the
1043 instruction, and update LEN with the instruction length. */
1046 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1047 CORE_ADDR addr
, int *len
)
1049 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1051 int instlen
, status
;
1053 /* All insns are at least 16 bits. */
1054 status
= target_read_memory (addr
, buf
, 2);
1056 memory_error (TARGET_XFER_E_IO
, addr
);
1058 /* If we need more, grab it now. */
1059 instlen
= riscv_insn_length (buf
[0]);
1061 if (instlen
> sizeof (buf
))
1062 internal_error (__FILE__
, __LINE__
,
1063 _("%s: riscv_insn_length returned %i"),
1065 else if (instlen
> 2)
1067 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1069 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1072 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1075 /* Fetch from target memory an instruction at PC and decode it. */
1078 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1082 /* Fetch the instruction, and the instructions length. */
1083 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1087 if (is_add_insn (ival
))
1088 decode_r_type_insn (ADD
, ival
);
1089 else if (is_addw_insn (ival
))
1090 decode_r_type_insn (ADDW
, ival
);
1091 else if (is_addi_insn (ival
))
1092 decode_i_type_insn (ADDI
, ival
);
1093 else if (is_addiw_insn (ival
))
1094 decode_i_type_insn (ADDIW
, ival
);
1095 else if (is_auipc_insn (ival
))
1096 decode_u_type_insn (AUIPC
, ival
);
1097 else if (is_lui_insn (ival
))
1098 decode_u_type_insn (LUI
, ival
);
1099 else if (is_sd_insn (ival
))
1100 decode_s_type_insn (SD
, ival
);
1101 else if (is_sw_insn (ival
))
1102 decode_s_type_insn (SW
, ival
);
1104 /* None of the other fields are valid in this case. */
1107 else if (m_length
== 2)
1109 if (is_c_add_insn (ival
))
1110 decode_cr_type_insn (ADD
, ival
);
1111 else if (is_c_addw_insn (ival
))
1112 decode_cr_type_insn (ADDW
, ival
);
1113 else if (is_c_addi_insn (ival
))
1114 decode_ci_type_insn (ADDI
, ival
);
1115 else if (is_c_addiw_insn (ival
))
1116 decode_ci_type_insn (ADDIW
, ival
);
1117 else if (is_c_addi16sp_insn (ival
))
1120 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1121 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1123 else if (is_lui_insn (ival
))
1125 else if (is_c_sd_insn (ival
))
1127 else if (is_sw_insn (ival
))
1130 /* None of the other fields of INSN are valid in this case. */
1134 internal_error (__FILE__
, __LINE__
,
1135 _("unable to decode %d byte instructions in "
1136 "prologue at %s"), m_length
,
1137 core_addr_to_string (pc
));
1140 /* The prologue scanner. This is currently only used for skipping the
1141 prologue of a function when the DWARF information is not sufficient.
1142 However, it is written with filling of the frame cache in mind, which
1143 is why different groups of stack setup instructions are split apart
1144 during the core of the inner loop. In the future, the intention is to
1145 extend this function to fully support building up a frame cache that
1146 can unwind register values when there is no DWARF information. */
1149 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1150 CORE_ADDR start_pc
, CORE_ADDR limit_pc
)
1152 CORE_ADDR cur_pc
, next_pc
;
1153 long frame_offset
= 0;
1154 CORE_ADDR end_prologue_addr
= 0;
1156 if (limit_pc
> start_pc
+ 200)
1157 limit_pc
= start_pc
+ 200;
1159 for (next_pc
= cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
= next_pc
)
1161 struct riscv_insn insn
;
1163 /* Decode the current instruction, and decide where the next
1164 instruction lives based on the size of this instruction. */
1165 insn
.decode (gdbarch
, cur_pc
);
1166 gdb_assert (insn
.length () > 0);
1167 next_pc
= cur_pc
+ insn
.length ();
1169 /* Look for common stack adjustment insns. */
1170 if ((insn
.opcode () == riscv_insn::ADDI
1171 || insn
.opcode () == riscv_insn::ADDIW
)
1172 && insn
.rd () == RISCV_SP_REGNUM
1173 && insn
.rs1 () == RISCV_SP_REGNUM
)
1175 /* Handle: addi sp, sp, -i
1176 or: addiw sp, sp, -i */
1177 if (insn
.imm_signed () < 0)
1178 frame_offset
+= insn
.imm_signed ();
1182 else if ((insn
.opcode () == riscv_insn::SW
1183 || insn
.opcode () == riscv_insn::SD
)
1184 && (insn
.rs1 () == RISCV_SP_REGNUM
1185 || insn
.rs1 () == RISCV_FP_REGNUM
))
1187 /* Handle: sw reg, offset(sp)
1188 or: sd reg, offset(sp)
1189 or: sw reg, offset(s0)
1190 or: sd reg, offset(s0) */
1191 /* Instruction storing a register onto the stack. */
1193 else if (insn
.opcode () == riscv_insn::ADDI
1194 && insn
.rd () == RISCV_FP_REGNUM
1195 && insn
.rs1 () == RISCV_SP_REGNUM
)
1197 /* Handle: addi s0, sp, size */
1198 /* Instructions setting up the frame pointer. */
1200 else if ((insn
.opcode () == riscv_insn::ADD
1201 || insn
.opcode () == riscv_insn::ADDW
)
1202 && insn
.rd () == RISCV_FP_REGNUM
1203 && insn
.rs1 () == RISCV_SP_REGNUM
1204 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1206 /* Handle: add s0, sp, 0
1207 or: addw s0, sp, 0 */
1208 /* Instructions setting up the frame pointer. */
1210 else if ((insn
.rd () == RISCV_GP_REGNUM
1211 && (insn
.opcode () == riscv_insn::AUIPC
1212 || insn
.opcode () == riscv_insn::LUI
1213 || (insn
.opcode () == riscv_insn::ADDI
1214 && insn
.rs1 () == RISCV_GP_REGNUM
)
1215 || (insn
.opcode () == riscv_insn::ADD
1216 && (insn
.rs1 () == RISCV_GP_REGNUM
1217 || insn
.rs2 () == RISCV_GP_REGNUM
))))
1218 || (insn
.opcode () == riscv_insn::ADDI
1219 && insn
.rd () == RISCV_ZERO_REGNUM
1220 && insn
.rs1 () == RISCV_ZERO_REGNUM
1221 && insn
.imm_signed () == 0))
1223 /* Handle: auipc gp, n
1228 or: add x0, x0, 0 (NOP) */
1229 /* These instructions are part of the prologue, but we don't need
1230 to do anything special to handle them. */
1234 if (end_prologue_addr
== 0)
1235 end_prologue_addr
= cur_pc
;
1239 if (end_prologue_addr
== 0)
1240 end_prologue_addr
= cur_pc
;
1242 return end_prologue_addr
;
1245 /* Implement the riscv_skip_prologue gdbarch method. */
1248 riscv_skip_prologue (struct gdbarch
*gdbarch
,
1252 CORE_ADDR func_addr
;
1254 /* See if we can determine the end of the prologue via the symbol
1255 table. If so, then return either PC, or the PC after the
1256 prologue, whichever is greater. */
1257 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1259 CORE_ADDR post_prologue_pc
1260 = skip_prologue_using_sal (gdbarch
, func_addr
);
1262 if (post_prologue_pc
!= 0)
1263 return std::max (pc
, post_prologue_pc
);
1266 /* Can't determine prologue from the symbol table, need to examine
1269 /* Find an upper limit on the function prologue using the debug
1270 information. If the debug information could not be used to provide
1271 that bound, then use an arbitrary large number as the upper bound. */
1272 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1274 limit_pc
= pc
+ 100; /* MAGIC! */
1276 return riscv_scan_prologue (gdbarch
, pc
, limit_pc
);
1279 /* Implement the gdbarch push dummy code callback. */
1282 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1283 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1284 struct type
*value_type
, CORE_ADDR
*real_pc
,
1285 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1287 /* Allocate space for a breakpoint, and keep the stack correctly
1295 /* Compute the alignment of the type T. Used while setting up the
1296 arguments for a dummy call. */
1299 riscv_type_alignment (struct type
*t
)
1301 t
= check_typedef (t
);
1302 switch (TYPE_CODE (t
))
1305 error (_("Could not compute alignment of type"));
1307 case TYPE_CODE_RVALUE_REF
:
1309 case TYPE_CODE_ENUM
:
1313 case TYPE_CODE_CHAR
:
1314 case TYPE_CODE_BOOL
:
1315 return TYPE_LENGTH (t
);
1317 case TYPE_CODE_ARRAY
:
1318 case TYPE_CODE_COMPLEX
:
1319 return riscv_type_alignment (TYPE_TARGET_TYPE (t
));
1321 case TYPE_CODE_STRUCT
:
1322 case TYPE_CODE_UNION
:
1327 for (i
= 0; i
< TYPE_NFIELDS (t
); ++i
)
1329 if (TYPE_FIELD_LOC_KIND (t
, i
) == FIELD_LOC_KIND_BITPOS
)
1331 int a
= riscv_type_alignment (TYPE_FIELD_TYPE (t
, i
));
1341 /* Holds information about a single argument either being passed to an
1342 inferior function, or returned from an inferior function. This includes
1343 information about the size, type, etc of the argument, and also
1344 information about how the argument will be passed (or returned). */
1346 struct riscv_arg_info
1348 /* Contents of the argument. */
1349 const gdb_byte
*contents
;
1351 /* Length of argument. */
1354 /* Alignment required for an argument of this type. */
1357 /* The type for this argument. */
1360 /* Each argument can have either 1 or 2 locations assigned to it. Each
1361 location describes where part of the argument will be placed. The
1362 second location is valid based on the LOC_TYPE and C_LENGTH fields
1363 of the first location (which is always valid). */
1366 /* What type of location this is. */
1369 /* Argument passed in a register. */
1372 /* Argument passed as an on stack argument. */
1375 /* Argument passed by reference. The second location is always
1376 valid for a BY_REF argument, and describes where the address
1377 of the BY_REF argument should be placed. */
1381 /* Information that depends on the location type. */
1384 /* Which register number to use. */
1387 /* The offset into the stack region. */
1391 /* The length of contents covered by this location. If this is less
1392 than the total length of the argument, then the second location
1393 will be valid, and will describe where the rest of the argument
1397 /* The offset within CONTENTS for this part of the argument. Will
1398 always be 0 for the first part. For the second part of the
1399 argument, this might be the C_LENGTH value of the first part,
1400 however, if we are passing a structure in two registers, and there's
1401 is padding between the first and second field, then this offset
1402 might be greater than the length of the first argument part. When
1403 the second argument location is not holding part of the argument
1404 value, but is instead holding the address of a reference argument,
1405 then this offset will be set to 0. */
1410 /* Information about a set of registers being used for passing arguments as
1411 part of a function call. The register set must be numerically
1412 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1413 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1415 struct riscv_arg_reg
1417 riscv_arg_reg (int first
, int last
)
1418 : next_regnum (first
),
1424 /* The GDB register number to use in this set. */
1427 /* The last GDB register number to use in this set. */
1431 /* Arguments can be passed as on stack arguments, or by reference. The
1432 on stack arguments must be in a continuous region starting from $sp,
1433 while the by reference arguments can be anywhere, but we'll put them
1434 on the stack after (at higher address) the on stack arguments.
1436 This might not be the right approach to take. The ABI is clear that
1437 an argument passed by reference can be modified by the callee, which
1438 us placing the argument (temporarily) onto the stack will not achieve
1439 (changes will be lost). There's also the possibility that very large
1440 arguments could overflow the stack.
1442 This struct is used to track offset into these two areas for where
1443 arguments are to be placed. */
1444 struct riscv_memory_offsets
1446 riscv_memory_offsets ()
1453 /* Offset into on stack argument area. */
1456 /* Offset into the pass by reference area. */
1460 /* Holds information about where arguments to a call will be placed. This
1461 is updated as arguments are added onto the call, and can be used to
1462 figure out where the next argument should be placed. */
1464 struct riscv_call_info
1466 riscv_call_info (struct gdbarch
*gdbarch
)
1467 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1468 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1470 xlen
= riscv_isa_xlen (gdbarch
);
1471 flen
= riscv_isa_flen (gdbarch
);
1473 /* Disable use of floating point registers if needed. */
1474 if (!riscv_has_fp_abi (gdbarch
))
1475 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1478 /* Track the memory areas used for holding in-memory arguments to a
1480 struct riscv_memory_offsets memory
;
1482 /* Holds information about the next integer register to use for passing
1484 struct riscv_arg_reg int_regs
;
1486 /* Holds information about the next floating point register to use for
1487 passing an argument. */
1488 struct riscv_arg_reg float_regs
;
1490 /* The XLEN and FLEN are copied in to this structure for convenience, and
1491 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1496 /* Return the number of registers available for use as parameters in the
1497 register set REG. Returned value can be 0 or more. */
1500 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1502 if (reg
->next_regnum
> reg
->last_regnum
)
1505 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1508 /* If there is at least one register available in the register set REG then
1509 the next register from REG is assigned to LOC and the length field of
1510 LOC is updated to LENGTH. The register set REG is updated to indicate
1511 that the assigned register is no longer available and the function
1514 If there are no registers available in REG then the function returns
1515 false, and LOC and REG are unchanged. */
1518 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1519 struct riscv_arg_reg
*reg
,
1520 int length
, int offset
)
1522 if (reg
->next_regnum
<= reg
->last_regnum
)
1524 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1525 loc
->loc_data
.regno
= reg
->next_regnum
;
1527 loc
->c_length
= length
;
1528 loc
->c_offset
= offset
;
1535 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1536 record that an area of stack has been used to hold the parameter
1539 The length field of LOC is updated to LENGTH, the length of the
1540 parameter being stored, and ALIGN is the alignment required by the
1541 parameter, which will affect how memory is allocated out of MEMORY. */
1544 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1545 struct riscv_memory_offsets
*memory
,
1546 int length
, int align
)
1548 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1550 = align_up (memory
->arg_offset
, align
);
1551 loc
->loc_data
.offset
= memory
->arg_offset
;
1552 memory
->arg_offset
+= length
;
1553 loc
->c_length
= length
;
1555 /* Offset is always 0, either we're the first location part, in which
1556 case we're reading content from the start of the argument, or we're
1557 passing the address of a reference argument, so 0. */
1561 /* Update AINFO, which describes an argument that should be passed or
1562 returned using the integer ABI. The argloc fields within AINFO are
1563 updated to describe the location in which the argument will be passed to
1564 a function, or returned from a function.
1566 The CINFO structure contains the ongoing call information, the holds
1567 information such as which argument registers are remaining to be
1568 assigned to parameter, and how much memory has been used by parameters
1571 By examining the state of CINFO a suitable location can be selected,
1572 and assigned to AINFO. */
1575 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1576 struct riscv_call_info
*cinfo
)
1578 if (ainfo
->length
> (2 * cinfo
->xlen
))
1580 /* Argument is going to be passed by reference. */
1581 ainfo
->argloc
[0].loc_type
1582 = riscv_arg_info::location::by_ref
;
1583 cinfo
->memory
.ref_offset
1584 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1585 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1586 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1587 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1589 /* The second location for this argument is given over to holding the
1590 address of the by-reference data. Pass 0 for the offset as this
1591 is not part of the actual argument value. */
1592 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1595 riscv_assign_stack_location (&ainfo
->argloc
[1],
1596 &cinfo
->memory
, cinfo
->xlen
,
1601 int len
= (ainfo
->length
> cinfo
->xlen
) ? cinfo
->xlen
: ainfo
->length
;
1603 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1604 &cinfo
->int_regs
, len
, 0))
1605 riscv_assign_stack_location (&ainfo
->argloc
[0],
1606 &cinfo
->memory
, len
, ainfo
->align
);
1608 if (len
< ainfo
->length
)
1610 len
= ainfo
->length
- len
;
1611 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1612 &cinfo
->int_regs
, len
,
1614 riscv_assign_stack_location (&ainfo
->argloc
[1],
1615 &cinfo
->memory
, len
, cinfo
->xlen
);
1620 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1621 is being passed with the floating point ABI. */
1624 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1625 struct riscv_call_info
*cinfo
)
1627 if (ainfo
->length
> cinfo
->flen
)
1628 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1631 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1634 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1638 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1639 is a complex floating point argument, and is therefore handled
1640 differently to other argument types. */
1643 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1644 struct riscv_call_info
*cinfo
)
1646 if (ainfo
->length
<= (2 * cinfo
->flen
)
1647 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1650 int len
= ainfo
->length
/ 2;
1652 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1653 &cinfo
->float_regs
, len
, len
);
1654 gdb_assert (result
);
1656 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1657 &cinfo
->float_regs
, len
, len
);
1658 gdb_assert (result
);
1661 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1664 /* A structure used for holding information about a structure type within
1665 the inferior program. The RiscV ABI has special rules for handling some
1666 structures with a single field or with two fields. The counting of
1667 fields here is done after flattening out all nested structures. */
1669 class riscv_struct_info
1672 riscv_struct_info ()
1673 : m_number_of_fields (0),
1674 m_types
{ nullptr, nullptr }
1679 /* Analyse TYPE descending into nested structures, count the number of
1680 scalar fields and record the types of the first two fields found. */
1681 void analyse (struct type
*type
);
1683 /* The number of scalar fields found in the analysed type. This is
1684 currently only accurate if the value returned is 0, 1, or 2 as the
1685 analysis stops counting when the number of fields is 3. This is
1686 because the RiscV ABI only has special cases for 1 or 2 fields,
1687 anything else we just don't care about. */
1688 int number_of_fields () const
1689 { return m_number_of_fields
; }
1691 /* Return the type for scalar field INDEX within the analysed type. Will
1692 return nullptr if there is no field at that index. Only INDEX values
1693 0 and 1 can be requested as the RiscV ABI only has special cases for
1694 structures with 1 or 2 fields. */
1695 struct type
*field_type (int index
) const
1697 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
1698 return m_types
[index
];
1702 /* The number of scalar fields found within the structure after recursing
1703 into nested structures. */
1704 int m_number_of_fields
;
1706 /* The types of the first two scalar fields found within the structure
1707 after recursing into nested structures. */
1708 struct type
*m_types
[2];
1711 /* Analyse TYPE descending into nested structures, count the number of
1712 scalar fields and record the types of the first two fields found. */
1715 riscv_struct_info::analyse (struct type
*type
)
1717 unsigned int count
= TYPE_NFIELDS (type
);
1720 for (i
= 0; i
< count
; ++i
)
1722 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
1725 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
1726 field_type
= check_typedef (field_type
);
1728 switch (TYPE_CODE (field_type
))
1730 case TYPE_CODE_STRUCT
:
1731 analyse (field_type
);
1735 /* RiscV only flattens out structures. Anything else does not
1736 need to be flattened, we just record the type, and when we
1737 look at the analysis results we'll realise this is not a
1738 structure we can special case, and pass the structure in
1740 if (m_number_of_fields
< 2)
1741 m_types
[m_number_of_fields
] = field_type
;
1742 m_number_of_fields
++;
1746 /* RiscV only has special handling for structures with 1 or 2 scalar
1747 fields, any more than that and the structure is just passed in
1748 memory. We can safely drop out early when we find 3 or more
1751 if (m_number_of_fields
> 2)
1756 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1757 is a structure. Small structures on RiscV have some special case
1758 handling in order that the structure might be passed in register.
1759 Larger structures are passed in memory. After assigning location
1760 information to AINFO, CINFO will have been updated. */
1763 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
1764 struct riscv_call_info
*cinfo
)
1766 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
1768 struct riscv_struct_info sinfo
;
1770 sinfo
.analyse (ainfo
->type
);
1771 if (sinfo
.number_of_fields () == 1
1772 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
1774 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1775 == TYPE_LENGTH (sinfo
.field_type (0)));
1776 return riscv_call_arg_complex_float (ainfo
, cinfo
);
1779 if (sinfo
.number_of_fields () == 1
1780 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
1782 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1783 == TYPE_LENGTH (sinfo
.field_type (0)));
1784 return riscv_call_arg_scalar_float (ainfo
, cinfo
);
1787 if (sinfo
.number_of_fields () == 2
1788 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1789 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1790 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1791 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
1792 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1794 int len0
, len1
, offset
;
1796 gdb_assert (TYPE_LENGTH (ainfo
->type
) <= (2 * cinfo
->flen
));
1798 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1799 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1800 &cinfo
->float_regs
, len0
, 0))
1801 error (_("failed during argument setup"));
1803 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1804 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1805 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
1806 - TYPE_LENGTH (sinfo
.field_type (0))));
1808 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1811 error (_("failed during argument setup"));
1815 if (sinfo
.number_of_fields () == 2
1816 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1817 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1818 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1819 && is_integral_type (sinfo
.field_type (1))
1820 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
1822 int len0
, len1
, offset
;
1824 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1825 <= (cinfo
->flen
+ cinfo
->xlen
));
1827 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1828 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1829 &cinfo
->float_regs
, len0
, 0))
1830 error (_("failed during argument setup"));
1832 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1833 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1834 gdb_assert (len1
<= cinfo
->xlen
);
1835 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1836 &cinfo
->int_regs
, len1
, offset
))
1837 error (_("failed during argument setup"));
1841 if (sinfo
.number_of_fields () == 2
1842 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1843 && (is_integral_type (sinfo
.field_type (0))
1844 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
1845 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1846 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
1848 int len0
, len1
, offset
;
1850 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1851 <= (cinfo
->flen
+ cinfo
->xlen
));
1853 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1854 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1855 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1857 gdb_assert (len0
<= cinfo
->xlen
);
1858 gdb_assert (len1
<= cinfo
->flen
);
1860 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1861 &cinfo
->int_regs
, len0
, 0))
1862 error (_("failed during argument setup"));
1864 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1867 error (_("failed during argument setup"));
1873 /* Non of the structure flattening cases apply, so we just pass using
1875 ainfo
->length
= align_up (ainfo
->length
, cinfo
->xlen
);
1876 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1879 /* Assign a location to call (or return) argument AINFO, the location is
1880 selected from CINFO which holds information about what call argument
1881 locations are available for use next. The TYPE is the type of the
1882 argument being passed, this information is recorded into AINFO (along
1883 with some additional information derived from the type).
1885 After assigning a location to AINFO, CINFO will have been updated. */
1888 riscv_arg_location (struct gdbarch
*gdbarch
,
1889 struct riscv_arg_info
*ainfo
,
1890 struct riscv_call_info
*cinfo
,
1894 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
1895 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1896 ainfo
->contents
= nullptr;
1898 switch (TYPE_CODE (ainfo
->type
))
1901 case TYPE_CODE_BOOL
:
1902 case TYPE_CODE_CHAR
:
1903 case TYPE_CODE_RANGE
:
1904 case TYPE_CODE_ENUM
:
1906 if (ainfo
->length
<= cinfo
->xlen
)
1908 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
1909 ainfo
->length
= cinfo
->xlen
;
1911 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
1913 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
1914 ainfo
->length
= 2 * cinfo
->xlen
;
1917 /* Recalculate the alignment requirement. */
1918 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1919 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1923 riscv_call_arg_scalar_float (ainfo
, cinfo
);
1926 case TYPE_CODE_COMPLEX
:
1927 riscv_call_arg_complex_float (ainfo
, cinfo
);
1930 case TYPE_CODE_STRUCT
:
1931 riscv_call_arg_struct (ainfo
, cinfo
);
1935 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1940 /* Used for printing debug information about the call argument location in
1941 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
1942 addresses for the location of pass-by-reference and
1943 arguments-on-the-stack memory areas. */
1946 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
1947 struct riscv_arg_info
*info
,
1948 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
1950 const char* type_name
= TYPE_NAME (info
->type
);
1951 if (type_name
== nullptr)
1954 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
1955 type_name
, info
->length
, info
->align
);
1956 switch (info
->argloc
[0].loc_type
)
1958 case riscv_arg_info::location::in_reg
:
1960 (stream
, ", register %s",
1961 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
1962 if (info
->argloc
[0].c_length
< info
->length
)
1964 switch (info
->argloc
[1].loc_type
)
1966 case riscv_arg_info::location::in_reg
:
1968 (stream
, ", register %s",
1969 gdbarch_register_name (gdbarch
,
1970 info
->argloc
[1].loc_data
.regno
));
1973 case riscv_arg_info::location::on_stack
:
1974 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1975 info
->argloc
[1].loc_data
.offset
);
1978 case riscv_arg_info::location::by_ref
:
1980 /* The second location should never be a reference, any
1981 argument being passed by reference just places its address
1982 in the first location and is done. */
1983 error (_("invalid argument location"));
1987 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
1988 fprintf_unfiltered (stream
, " (offset 0x%x)",
1989 info
->argloc
[1].c_offset
);
1993 case riscv_arg_info::location::on_stack
:
1994 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1995 info
->argloc
[0].loc_data
.offset
);
1998 case riscv_arg_info::location::by_ref
:
2000 (stream
, ", by reference, data at offset 0x%x (%s)",
2001 info
->argloc
[0].loc_data
.offset
,
2002 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2003 if (info
->argloc
[1].loc_type
2004 == riscv_arg_info::location::in_reg
)
2006 (stream
, ", address in register %s",
2007 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2010 gdb_assert (info
->argloc
[1].loc_type
2011 == riscv_arg_info::location::on_stack
);
2013 (stream
, ", address on stack at offset 0x%x (%s)",
2014 info
->argloc
[1].loc_data
.offset
,
2015 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2020 error ("unknown argument location type");
2024 /* Implement the push dummy call gdbarch callback. */
2027 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2028 struct value
*function
,
2029 struct regcache
*regcache
,
2032 struct value
**args
,
2035 CORE_ADDR struct_addr
)
2038 CORE_ADDR sp_args
, sp_refs
;
2039 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2040 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2042 struct riscv_arg_info
*arg_info
=
2043 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2044 struct riscv_arg_info
*info
;
2046 struct riscv_call_info
call_info (gdbarch
);
2050 /* We'll use register $a0 if we're returning a struct. */
2052 ++call_info
.int_regs
.next_regnum
;
2054 for (i
= 0, info
= &arg_info
[0];
2058 struct value
*arg_value
;
2059 struct type
*arg_type
;
2061 arg_value
= args
[i
];
2062 arg_type
= check_typedef (value_type (arg_value
));
2064 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
);
2066 if (info
->type
!= arg_type
)
2067 arg_value
= value_cast (info
->type
, arg_value
);
2068 info
->contents
= value_contents (arg_value
);
2071 /* Adjust the stack pointer and align it. */
2072 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2073 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2075 if (riscv_debug_infcall
> 0)
2077 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2078 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2079 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2080 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2081 call_info
.xlen
, call_info
.flen
);
2083 fprintf_unfiltered (gdb_stdlog
,
2084 "[*] struct return pointer in register $A0\n");
2085 for (i
= 0; i
< nargs
; ++i
)
2087 struct riscv_arg_info
*info
= &arg_info
[i
];
2089 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2090 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2091 fprintf_unfiltered (gdb_stdlog
, "\n");
2093 if (call_info
.memory
.arg_offset
> 0
2094 || call_info
.memory
.ref_offset
> 0)
2096 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2097 core_addr_to_string (osp
));
2098 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2099 call_info
.memory
.arg_offset
);
2100 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2101 call_info
.memory
.ref_offset
);
2102 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2103 core_addr_to_string_nz (osp
- sp
));
2107 /* Now load the argument into registers, or onto the stack. */
2111 gdb_byte buf
[sizeof (LONGEST
)];
2113 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2114 regcache_cooked_write (regcache
, RISCV_A0_REGNUM
, buf
);
2117 for (i
= 0; i
< nargs
; ++i
)
2120 int second_arg_length
= 0;
2121 const gdb_byte
*second_arg_data
;
2122 struct riscv_arg_info
*info
= &arg_info
[i
];
2124 gdb_assert (info
->length
> 0);
2126 switch (info
->argloc
[0].loc_type
)
2128 case riscv_arg_info::location::in_reg
:
2130 gdb_byte tmp
[sizeof (ULONGEST
)];
2132 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2133 memset (tmp
, 0, sizeof (tmp
));
2134 memcpy (tmp
, info
->contents
, info
->argloc
[0].c_length
);
2135 regcache_cooked_write (regcache
,
2136 info
->argloc
[0].loc_data
.regno
,
2139 ((info
->argloc
[0].c_length
< info
->length
)
2140 ? info
->argloc
[1].c_length
: 0);
2141 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2145 case riscv_arg_info::location::on_stack
:
2146 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2147 write_memory (dst
, info
->contents
, info
->length
);
2148 second_arg_length
= 0;
2151 case riscv_arg_info::location::by_ref
:
2152 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2153 write_memory (dst
, info
->contents
, info
->length
);
2155 second_arg_length
= call_info
.xlen
;
2156 second_arg_data
= (gdb_byte
*) &dst
;
2160 error ("unknown argument location type");
2163 if (second_arg_length
> 0)
2165 switch (info
->argloc
[1].loc_type
)
2167 case riscv_arg_info::location::in_reg
:
2169 gdb_byte tmp
[sizeof (ULONGEST
)];
2171 gdb_assert (second_arg_length
<= call_info
.xlen
);
2172 memset (tmp
, 0, sizeof (tmp
));
2173 memcpy (tmp
, second_arg_data
, second_arg_length
);
2174 regcache_cooked_write (regcache
,
2175 info
->argloc
[1].loc_data
.regno
,
2180 case riscv_arg_info::location::on_stack
:
2184 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2185 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2189 case riscv_arg_info::location::by_ref
:
2191 /* The second location should never be a reference, any
2192 argument being passed by reference just places its address
2193 in the first location and is done. */
2194 error (_("invalid argument location"));
2200 /* Set the dummy return value to bp_addr.
2201 A dummy breakpoint will be setup to execute the call. */
2203 if (riscv_debug_infcall
> 0)
2204 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2205 core_addr_to_string (bp_addr
));
2206 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2208 /* Finally, update the stack pointer. */
2210 if (riscv_debug_infcall
> 0)
2211 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2212 core_addr_to_string (sp
));
2213 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2218 /* Implement the return_value gdbarch method. */
2220 static enum return_value_convention
2221 riscv_return_value (struct gdbarch
*gdbarch
,
2222 struct value
*function
,
2224 struct regcache
*regcache
,
2226 const gdb_byte
*writebuf
)
2228 enum type_code rv_type
= TYPE_CODE (type
);
2229 unsigned int rv_size
= TYPE_LENGTH (type
);
2230 int fp
, regnum
, flen
;
2232 struct riscv_call_info
call_info (gdbarch
);
2233 struct riscv_arg_info info
;
2234 struct type
*arg_type
;
2236 arg_type
= check_typedef (type
);
2237 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
);
2239 if (riscv_debug_infcall
> 0)
2241 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2242 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2243 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2244 fprintf_unfiltered (gdb_stdlog
, "\n");
2247 if (readbuf
!= nullptr || writebuf
!= nullptr)
2251 switch (info
.argloc
[0].loc_type
)
2253 /* Return value in register(s). */
2254 case riscv_arg_info::location::in_reg
:
2256 regnum
= info
.argloc
[0].loc_data
.regno
;
2259 regcache_cooked_read (regcache
, regnum
, readbuf
);
2262 regcache_cooked_write (regcache
, regnum
, writebuf
);
2264 /* A return value in register can have a second part in a
2266 if (info
.argloc
[0].c_length
< info
.length
)
2268 switch (info
.argloc
[1].loc_type
)
2270 case riscv_arg_info::location::in_reg
:
2271 regnum
= info
.argloc
[1].loc_data
.regno
;
2275 readbuf
+= info
.argloc
[1].c_offset
;
2276 regcache_cooked_read (regcache
, regnum
, readbuf
);
2281 writebuf
+= info
.argloc
[1].c_offset
;
2282 regcache_cooked_write (regcache
, regnum
, writebuf
);
2286 case riscv_arg_info::location::by_ref
:
2287 case riscv_arg_info::location::on_stack
:
2289 error (_("invalid argument location"));
2296 /* Return value by reference will have its address in A0. */
2297 case riscv_arg_info::location::by_ref
:
2301 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2303 if (readbuf
!= nullptr)
2304 read_memory (addr
, readbuf
, info
.length
);
2305 if (writebuf
!= nullptr)
2306 write_memory (addr
, writebuf
, info
.length
);
2310 case riscv_arg_info::location::on_stack
:
2312 error (_("invalid argument location"));
2317 switch (info
.argloc
[0].loc_type
)
2319 case riscv_arg_info::location::in_reg
:
2320 return RETURN_VALUE_REGISTER_CONVENTION
;
2321 case riscv_arg_info::location::by_ref
:
2322 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2323 case riscv_arg_info::location::on_stack
:
2325 error (_("invalid argument location"));
2329 /* Implement the frame_align gdbarch method. */
2332 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2334 return align_down (addr
, 16);
2337 /* Implement the unwind_pc gdbarch method. */
2340 riscv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2342 return frame_unwind_register_unsigned (next_frame
, RISCV_PC_REGNUM
);
2345 /* Implement the unwind_sp gdbarch method. */
2348 riscv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2350 return frame_unwind_register_unsigned (next_frame
, RISCV_SP_REGNUM
);
2353 /* Implement the dummy_id gdbarch method. */
2355 static struct frame_id
2356 riscv_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2358 return frame_id_build (get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
),
2359 get_frame_pc (this_frame
));
2362 /* Generate, or return the cached frame cache for the RiscV frame
2365 static struct trad_frame_cache
*
2366 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2369 CORE_ADDR start_addr
;
2370 CORE_ADDR stack_addr
;
2371 struct trad_frame_cache
*this_trad_cache
;
2372 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2374 if ((*this_cache
) != NULL
)
2375 return (struct trad_frame_cache
*) *this_cache
;
2376 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2377 (*this_cache
) = this_trad_cache
;
2379 trad_frame_set_reg_realreg (this_trad_cache
, gdbarch_pc_regnum (gdbarch
),
2382 pc
= get_frame_pc (this_frame
);
2383 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2384 stack_addr
= get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
);
2385 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2387 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2389 return this_trad_cache
;
2392 /* Implement the this_id callback for RiscV frame unwinder. */
2395 riscv_frame_this_id (struct frame_info
*this_frame
,
2396 void **prologue_cache
,
2397 struct frame_id
*this_id
)
2399 struct trad_frame_cache
*info
;
2401 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2402 trad_frame_get_id (info
, this_id
);
2405 /* Implement the prev_register callback for RiscV frame unwinder. */
2407 static struct value
*
2408 riscv_frame_prev_register (struct frame_info
*this_frame
,
2409 void **prologue_cache
,
2412 struct trad_frame_cache
*info
;
2414 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2415 return trad_frame_get_register (info
, this_frame
, regnum
);
2418 /* Structure defining the RiscV normal frame unwind functions. Since we
2419 are the fallback unwinder (DWARF unwinder is used first), we use the
2420 default frame sniffer, which always accepts the frame. */
2422 static const struct frame_unwind riscv_frame_unwind
=
2424 /*.type =*/ NORMAL_FRAME
,
2425 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2426 /*.this_id =*/ riscv_frame_this_id
,
2427 /*.prev_register =*/ riscv_frame_prev_register
,
2428 /*.unwind_data =*/ NULL
,
2429 /*.sniffer =*/ default_frame_sniffer
,
2430 /*.dealloc_cache =*/ NULL
,
2431 /*.prev_arch =*/ NULL
,
2434 /* Initialize the current architecture based on INFO. If possible,
2435 re-use an architecture from ARCHES, which is a list of
2436 architectures already created during this debugging session.
2438 Called e.g. at program startup, when reading a core file, and when
2439 reading a binary file. */
2441 static struct gdbarch
*
2442 riscv_gdbarch_init (struct gdbarch_info info
,
2443 struct gdbarch_list
*arches
)
2445 struct gdbarch
*gdbarch
;
2446 struct gdbarch_tdep
*tdep
;
2447 struct gdbarch_tdep tmp_tdep
;
2448 bool has_compressed_isa
= false;
2451 /* Ideally, we'd like to get as much information from the target for
2452 things like register size, and whether the target has floating point
2453 hardware. However, there are some things that the target can't tell
2454 us, like, what ABI is being used.
2456 So, for now, we take as much information as possible from the ELF,
2457 including things like register size, and FP hardware support, along
2458 with information about the ABI.
2460 Information about this target is built up in TMP_TDEP, and then we
2461 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2462 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2463 memset (&tmp_tdep
, 0, sizeof (tmp_tdep
));
2465 if (info
.abfd
!= NULL
2466 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2468 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2469 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2471 if (eclass
== ELFCLASS32
)
2472 tmp_tdep
.abi
.fields
.base_len
= 1;
2473 else if (eclass
== ELFCLASS64
)
2474 tmp_tdep
.abi
.fields
.base_len
= 2;
2476 internal_error (__FILE__
, __LINE__
,
2477 _("unknown ELF header class %d"), eclass
);
2479 if (e_flags
& EF_RISCV_RVC
)
2481 has_compressed_isa
= true;
2482 tmp_tdep
.core_features
|= (1 << ('C' - 'A'));
2485 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2487 tmp_tdep
.abi
.fields
.float_abi
= 2;
2488 tmp_tdep
.core_features
|= (1 << ('D' - 'A'));
2489 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2491 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2493 tmp_tdep
.abi
.fields
.float_abi
= 1;
2494 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2499 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2501 if (binfo
->bits_per_word
== 32)
2502 tmp_tdep
.abi
.fields
.base_len
= 1;
2503 else if (binfo
->bits_per_word
== 64)
2504 tmp_tdep
.abi
.fields
.base_len
= 2;
2506 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2507 binfo
->bits_per_word
);
2510 /* Find a candidate among the list of pre-declared architectures. */
2511 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2513 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2514 if (gdbarch_tdep (arches
->gdbarch
)->abi
.value
== tmp_tdep
.abi
.value
)
2515 return arches
->gdbarch
;
2517 /* None found, so create a new architecture from the information provided. */
2518 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof *tdep
);
2519 gdbarch
= gdbarch_alloc (&info
, tdep
);
2520 memcpy (tdep
, &tmp_tdep
, sizeof (tmp_tdep
));
2522 /* Target data types. */
2523 set_gdbarch_short_bit (gdbarch
, 16);
2524 set_gdbarch_int_bit (gdbarch
, 32);
2525 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2526 set_gdbarch_long_long_bit (gdbarch
, 64);
2527 set_gdbarch_float_bit (gdbarch
, 32);
2528 set_gdbarch_double_bit (gdbarch
, 64);
2529 set_gdbarch_long_double_bit (gdbarch
, 128);
2530 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
2531 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2532 set_gdbarch_char_signed (gdbarch
, 0);
2534 /* Information about the target architecture. */
2535 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
2536 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
2537 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
2539 /* Register architecture. */
2540 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
2541 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
2542 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
2543 set_gdbarch_ps_regnum (gdbarch
, RISCV_FP_REGNUM
);
2544 set_gdbarch_deprecated_fp_regnum (gdbarch
, RISCV_FP_REGNUM
);
2546 /* Functions to supply register information. */
2547 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
2548 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
2549 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
2550 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
2552 /* Functions to analyze frames. */
2553 set_gdbarch_decr_pc_after_break (gdbarch
, (has_compressed_isa
? 2 : 4));
2554 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
2555 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2556 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
2558 /* Functions to access frame data. */
2559 set_gdbarch_unwind_pc (gdbarch
, riscv_unwind_pc
);
2560 set_gdbarch_unwind_sp (gdbarch
, riscv_unwind_sp
);
2562 /* Functions handling dummy frames. */
2563 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2564 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
2565 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
2566 set_gdbarch_dummy_id (gdbarch
, riscv_dummy_id
);
2568 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2570 dwarf2_append_unwinders (gdbarch
);
2571 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
2573 /* Check any target description for validity. */
2574 if (tdesc_has_registers (info
.target_desc
))
2576 const struct tdesc_feature
*feature
;
2577 struct tdesc_arch_data
*tdesc_data
;
2580 feature
= tdesc_find_feature (info
.target_desc
, "org.gnu.gdb.riscv.cpu");
2581 if (feature
== NULL
)
2584 tdesc_data
= tdesc_data_alloc ();
2587 for (i
= RISCV_ZERO_REGNUM
; i
<= RISCV_LAST_FP_REGNUM
; ++i
)
2588 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2589 riscv_gdb_reg_names
[i
]);
2590 for (i
= RISCV_FIRST_CSR_REGNUM
; i
<= RISCV_LAST_CSR_REGNUM
; ++i
)
2594 sprintf (buf
, "csr%d", i
- RISCV_FIRST_CSR_REGNUM
);
2595 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, buf
);
2598 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "priv");
2601 tdesc_data_cleanup (tdesc_data
);
2603 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
2607 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
2608 user_reg_add (gdbarch
, riscv_register_aliases
[i
].name
,
2609 value_of_riscv_user_reg
, &riscv_register_aliases
[i
].regnum
);
2615 /* Allocate new riscv_inferior_data object. */
2617 static struct riscv_inferior_data
*
2618 riscv_new_inferior_data (void)
2620 struct riscv_inferior_data
*inf_data
2621 = new (struct riscv_inferior_data
);
2622 inf_data
->misa_read
= false;
2626 /* Free inferior data. */
2629 riscv_inferior_data_cleanup (struct inferior
*inf
, void *data
)
2631 struct riscv_inferior_data
*inf_data
=
2632 static_cast <struct riscv_inferior_data
*> (data
);
2636 /* Return riscv_inferior_data for the given INFERIOR. If not yet created,
2639 struct riscv_inferior_data
*
2640 riscv_inferior_data (struct inferior
*const inf
)
2642 struct riscv_inferior_data
*inf_data
;
2644 gdb_assert (inf
!= NULL
);
2647 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2648 if (inf_data
== NULL
)
2650 inf_data
= riscv_new_inferior_data ();
2651 set_inferior_data (inf
, riscv_inferior_data_reg
, inf_data
);
2657 /* Free the inferior data when an inferior exits. */
2660 riscv_invalidate_inferior_data (struct inferior
*inf
)
2662 struct riscv_inferior_data
*inf_data
;
2664 gdb_assert (inf
!= NULL
);
2666 /* Don't call RISCV_INFERIOR_DATA as we don't want to create the data if
2667 we've not already created it by this point. */
2669 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2670 if (inf_data
!= NULL
)
2673 set_inferior_data (inf
, riscv_inferior_data_reg
, NULL
);
2678 _initialize_riscv_tdep (void)
2680 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
2682 /* Register per-inferior data. */
2683 riscv_inferior_data_reg
2684 = register_inferior_data_with_cleanup (NULL
, riscv_inferior_data_cleanup
);
2686 /* Observers used to invalidate the inferior data when needed. */
2687 observer_attach_inferior_exit (riscv_invalidate_inferior_data
);
2688 observer_attach_inferior_appeared (riscv_invalidate_inferior_data
);
2690 /* Add root prefix command for all "set debug riscv" and "show debug
2692 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
2693 _("RISC-V specific debug commands."),
2694 &setdebugriscvcmdlist
, "set debug riscv ", 0,
2697 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
2698 _("RISC-V specific debug commands."),
2699 &showdebugriscvcmdlist
, "show debug riscv ", 0,
2702 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
2703 &riscv_debug_infcall
, _("\
2704 Set riscv inferior call debugging."), _("\
2705 Show riscv inferior call debugging."), _("\
2706 When non-zero, print debugging information for the riscv specific parts\n\
2707 of the inferior call mechanism."),
2709 show_riscv_debug_variable
,
2710 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
2712 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2713 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
2714 _("RISC-V specific commands."),
2715 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
2717 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
2718 _("RISC-V specific commands."),
2719 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
2722 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
2723 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
2724 &use_compressed_breakpoints
,
2726 Set debugger's use of compressed breakpoints."), _(" \
2727 Show debugger's use of compressed breakpoints."), _("\
2728 Debugging compressed code requires compressed breakpoints to be used. If\n \
2729 left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2730 is supported. If that doesn't give the correct behavior, then this option\n\
2733 show_use_compressed_breakpoints
,