1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
60 /* The stack must be 16-byte aligned. */
61 #define SP_ALIGNMENT 16
63 /* The biggest alignment that the target supports. */
64 #define BIGGEST_ALIGNMENT 16
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Cached information about a frame. */
78 struct riscv_unwind_cache
80 /* The register from which we can calculate the frame base. This is
81 usually $sp or $fp. */
84 /* The offset from the current value in register FRAME_BASE_REG to the
85 actual frame base address. */
86 int frame_base_offset
;
88 /* Information about previous register values. */
89 struct trad_frame_saved_reg
*regs
;
91 /* The id for this frame. */
92 struct frame_id this_id
;
94 /* The base (stack) address for this frame. This is the stack pointer
95 value on entry to this frame before any adjustments are made. */
99 /* RISC-V specific register group for CSRs. */
101 static reggroup
*csr_reggroup
= NULL
;
103 /* A set of registers that we expect to find in a tdesc_feature. These
104 are use in RISCV_GDBARCH_INIT when processing the target description. */
106 struct riscv_register_feature
108 /* Information for a single register. */
111 /* The GDB register number for this register. */
114 /* List of names for this register. The first name in this list is the
115 preferred name, the name GDB should use when describing this
117 std::vector
<const char *> names
;
119 /* When true this register is required in this feature set. */
123 /* The name for this feature. This is the name used to find this feature
124 within the target description. */
127 /* List of all the registers that we expect that we might find in this
129 std::vector
<struct register_info
> registers
;
132 /* The general x-registers feature set. */
134 static const struct riscv_register_feature riscv_xreg_feature
=
136 "org.gnu.gdb.riscv.cpu",
138 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" }, true },
139 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" }, true },
140 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" }, true },
141 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" }, true },
142 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" }, true },
143 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" }, true },
144 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" }, true },
145 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" }, true },
146 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" }, true },
147 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" }, true },
148 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" }, true },
149 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" }, true },
150 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" }, true },
151 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" }, true },
152 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" }, true },
153 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" }, true },
154 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" }, true },
155 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" }, true },
156 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" }, true },
157 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" }, true },
158 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" }, true },
159 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" }, true },
160 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" }, true },
161 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" }, true },
162 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" }, true },
163 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" }, true },
164 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" }, true },
165 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" }, true },
166 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" }, true },
167 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" }, true },
168 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" }, true },
169 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" }, true },
170 { RISCV_ZERO_REGNUM
+ 32, { "pc" }, true }
174 /* The f-registers feature set. */
176 static const struct riscv_register_feature riscv_freg_feature
=
178 "org.gnu.gdb.riscv.fpu",
180 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" }, true },
181 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" }, true },
182 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" }, true },
183 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" }, true },
184 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" }, true },
185 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" }, true },
186 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" }, true },
187 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" }, true },
188 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8", "s0" }, true },
189 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" }, true },
190 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" }, true },
191 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" }, true },
192 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" }, true },
193 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" }, true },
194 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" }, true },
195 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" }, true },
196 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" }, true },
197 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" }, true },
198 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" }, true },
199 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" }, true },
200 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" }, true },
201 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" }, true },
202 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" }, true },
203 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" }, true },
204 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" }, true },
205 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" }, true },
206 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" }, true },
207 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" }, true },
208 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" }, true },
209 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" }, true },
210 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" }, true },
211 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" }, true },
213 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags" }, true },
214 { RISCV_CSR_FRM_REGNUM
, { "frm" }, true },
215 { RISCV_CSR_FCSR_REGNUM
, { "fcsr" }, true },
220 /* Set of virtual registers. These are not physical registers on the
221 hardware, but might be available from the target. These are not pseudo
222 registers, reading these really does result in a register read from the
223 target, it is just that there might not be a physical register backing
226 static const struct riscv_register_feature riscv_virtual_feature
=
228 "org.gnu.gdb.riscv.virtual",
230 { RISCV_PRIV_REGNUM
, { "priv" }, false }
234 /* Feature set for CSRs. This set is NOT constant as the register names
235 list for each register is not complete. The aliases are computed
236 during RISCV_CREATE_CSR_ALIASES. */
238 static struct riscv_register_feature riscv_csr_feature
=
240 "org.gnu.gdb.riscv.csr",
242 #define DECLARE_CSR(NAME,VALUE) \
243 { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
244 #include "opcode/riscv-opc.h"
249 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
250 to the name list for each register. */
253 riscv_create_csr_aliases ()
255 for (auto ®
: riscv_csr_feature
.registers
)
257 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
258 const char *alias
= xstrprintf ("csr%d", csr_num
);
259 reg
.names
.push_back (alias
);
263 /* Controls whether we place compressed breakpoints or not. When in auto
264 mode GDB tries to determine if the target supports compressed
265 breakpoints, and uses them if it does. */
267 static enum auto_boolean use_compressed_breakpoints
;
269 /* The show callback for 'show riscv use-compressed-breakpoints'. */
272 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
273 struct cmd_list_element
*c
,
276 fprintf_filtered (file
,
277 _("Debugger's use of compressed breakpoints is set "
281 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
283 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
284 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
286 /* The show callback for the 'show riscv' prefix command. */
289 show_riscv_command (const char *args
, int from_tty
)
291 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
294 /* The set callback for the 'set riscv' prefix command. */
297 set_riscv_command (const char *args
, int from_tty
)
300 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
301 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
304 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
306 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
307 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
309 /* The show callback for the 'show debug riscv' prefix command. */
312 show_debug_riscv_command (const char *args
, int from_tty
)
314 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
317 /* The set callback for the 'set debug riscv' prefix command. */
320 set_debug_riscv_command (const char *args
, int from_tty
)
323 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
324 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
327 /* The show callback for all 'show debug riscv VARNAME' variables. */
330 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
331 struct cmd_list_element
*c
,
334 fprintf_filtered (file
,
335 _("RiscV debug variable `%s' is set to: %s\n"),
339 /* When this is set to non-zero debugging information about breakpoint
340 kinds will be printed. */
342 static unsigned int riscv_debug_breakpoints
= 0;
344 /* When this is set to non-zero debugging information about inferior calls
347 static unsigned int riscv_debug_infcall
= 0;
349 /* When this is set to non-zero debugging information about stack unwinding
352 static unsigned int riscv_debug_unwinder
= 0;
354 /* When this is set to non-zero debugging information about gdbarch
355 initialisation will be printed. */
357 static unsigned int riscv_debug_gdbarch
= 0;
359 /* See riscv-tdep.h. */
362 riscv_isa_xlen (struct gdbarch
*gdbarch
)
364 return gdbarch_tdep (gdbarch
)->features
.xlen
;
367 /* See riscv-tdep.h. */
370 riscv_isa_flen (struct gdbarch
*gdbarch
)
372 return gdbarch_tdep (gdbarch
)->features
.flen
;
375 /* Return true if the target for GDBARCH has floating point hardware. */
378 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
380 return (riscv_isa_flen (gdbarch
) > 0);
383 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
386 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
388 return gdbarch_tdep (gdbarch
)->features
.hw_float_abi
;
391 /* Return true if REGNO is a floating pointer register. */
394 riscv_is_fp_regno_p (int regno
)
396 return (regno
>= RISCV_FIRST_FP_REGNUM
397 && regno
<= RISCV_LAST_FP_REGNUM
);
400 /* Implement the breakpoint_kind_from_pc gdbarch method. */
403 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
405 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
407 bool unaligned_p
= false;
410 /* Some targets don't support unaligned reads. The address can only
411 be unaligned if the C extension is supported. So it is safe to
412 use a compressed breakpoint in this case. */
417 /* Read the opcode byte to determine the instruction length. */
418 read_code (*pcptr
, buf
, 1);
421 if (riscv_debug_breakpoints
)
423 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
424 ? "C.EBREAK" : "EBREAK");
426 fprintf_unfiltered (gdb_stdlog
, "Using %s for breakpoint at %s ",
427 bp
, paddress (gdbarch
, *pcptr
));
429 fprintf_unfiltered (gdb_stdlog
, "(unaligned address)\n");
431 fprintf_unfiltered (gdb_stdlog
, "(instruction length %d)\n",
432 riscv_insn_length (buf
[0]));
434 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
439 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
445 /* Implement the sw_breakpoint_from_kind gdbarch method. */
447 static const gdb_byte
*
448 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
450 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
451 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
461 gdb_assert_not_reached (_("unhandled breakpoint kind"));
465 /* Callback function for user_reg_add. */
467 static struct value
*
468 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
470 const int *reg_p
= (const int *) baton
;
471 return value_of_register (*reg_p
, frame
);
474 /* Implement the register_name gdbarch method. This is used instead of
475 the function supplied by calling TDESC_USE_REGISTERS so that we can
476 ensure the preferred names are offered. */
479 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
481 /* Lookup the name through the target description. If we get back NULL
482 then this is an unknown register. If we do get a name back then we
483 look up the registers preferred name below. */
484 const char *name
= tdesc_register_name (gdbarch
, regnum
);
485 if (name
== NULL
|| name
[0] == '\0')
488 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
490 gdb_assert (regnum
< riscv_xreg_feature
.registers
.size ());
491 return riscv_xreg_feature
.registers
[regnum
].names
[0];
494 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
496 if (riscv_has_fp_regs (gdbarch
))
498 regnum
-= RISCV_FIRST_FP_REGNUM
;
499 gdb_assert (regnum
< riscv_freg_feature
.registers
.size ());
500 return riscv_freg_feature
.registers
[regnum
].names
[0];
506 /* Check that there's no gap between the set of registers handled above,
507 and the set of registers handled next. */
508 gdb_assert ((RISCV_LAST_FP_REGNUM
+ 1) == RISCV_FIRST_CSR_REGNUM
);
510 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
512 #define DECLARE_CSR(NAME,VALUE) \
513 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
517 #include "opcode/riscv-opc.h"
522 if (regnum
== RISCV_PRIV_REGNUM
)
525 /* It is possible that that the target provides some registers that GDB
526 is unaware of, in that case just return the NAME from the target
531 /* Construct a type for 64-bit FP registers. */
534 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
536 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
538 if (tdep
->riscv_fpreg_d_type
== nullptr)
540 const struct builtin_type
*bt
= builtin_type (gdbarch
);
542 /* The type we're building is this: */
544 union __gdb_builtin_type_fpreg_d
553 t
= arch_composite_type (gdbarch
,
554 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
555 append_composite_type_field (t
, "float", bt
->builtin_float
);
556 append_composite_type_field (t
, "double", bt
->builtin_double
);
558 TYPE_NAME (t
) = "builtin_type_fpreg_d";
559 tdep
->riscv_fpreg_d_type
= t
;
562 return tdep
->riscv_fpreg_d_type
;
565 /* Implement the register_type gdbarch method. This is installed as an
566 for the override setup by TDESC_USE_REGISTERS, for most registers we
567 delegate the type choice to the target description, but for a few
568 registers we try to improve the types if the target description has
569 taken a simplistic approach. */
572 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
574 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
575 int xlen
= riscv_isa_xlen (gdbarch
);
577 /* We want to perform some specific type "fixes" in cases where we feel
578 that we really can do better than the target description. For all
579 other cases we just return what the target description says. */
580 if (riscv_is_fp_regno_p (regnum
))
582 /* This spots the case for RV64 where the double is defined as
583 either 'ieee_double' or 'float' (which is the generic name that
584 converts to 'double' on 64-bit). In these cases its better to
585 present the registers using a union type. */
586 int flen
= riscv_isa_flen (gdbarch
);
588 && TYPE_CODE (type
) == TYPE_CODE_FLT
589 && TYPE_LENGTH (type
) == flen
590 && (strcmp (TYPE_NAME (type
), "builtin_type_ieee_double") == 0
591 || strcmp (TYPE_NAME (type
), "double") == 0))
592 type
= riscv_fpreg_d_type (gdbarch
);
595 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
596 || regnum
== RISCV_RA_REGNUM
597 || regnum
== RISCV_FP_REGNUM
598 || regnum
== RISCV_SP_REGNUM
599 || regnum
== RISCV_GP_REGNUM
600 || regnum
== RISCV_TP_REGNUM
)
601 && TYPE_CODE (type
) == TYPE_CODE_INT
602 && TYPE_LENGTH (type
) == xlen
)
604 /* This spots the case where some interesting registers are defined
605 as simple integers of the expected size, we force these registers
606 to be pointers as we believe that is more useful. */
607 if (regnum
== gdbarch_pc_regnum (gdbarch
)
608 || regnum
== RISCV_RA_REGNUM
)
609 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
610 else if (regnum
== RISCV_FP_REGNUM
611 || regnum
== RISCV_SP_REGNUM
612 || regnum
== RISCV_GP_REGNUM
613 || regnum
== RISCV_TP_REGNUM
)
614 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
620 /* Helper for riscv_print_registers_info, prints info for a single register
624 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
625 struct ui_file
*file
,
626 struct frame_info
*frame
,
629 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
631 struct type
*regtype
;
632 int print_raw_format
;
633 enum tab_stops
{ value_column_1
= 15 };
635 fputs_filtered (name
, file
);
636 print_spaces_filtered (value_column_1
- strlen (name
), file
);
640 val
= value_of_register (regnum
, frame
);
641 regtype
= value_type (val
);
643 CATCH (ex
, RETURN_MASK_ERROR
)
645 /* Handle failure to read a register without interrupting the entire
646 'info registers' flow. */
647 fprintf_filtered (file
, "%s\n", ex
.message
);
652 print_raw_format
= (value_entirely_available (val
)
653 && !value_optimized_out (val
));
655 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
656 || (TYPE_CODE (regtype
) == TYPE_CODE_UNION
657 && TYPE_NFIELDS (regtype
) == 2
658 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 0)) == TYPE_CODE_FLT
659 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 1)) == TYPE_CODE_FLT
)
660 || (TYPE_CODE (regtype
) == TYPE_CODE_UNION
661 && TYPE_NFIELDS (regtype
) == 3
662 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 0)) == TYPE_CODE_FLT
663 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 1)) == TYPE_CODE_FLT
664 && TYPE_CODE (TYPE_FIELD_TYPE (regtype
, 2)) == TYPE_CODE_FLT
))
666 struct value_print_options opts
;
667 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
668 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
670 get_user_print_options (&opts
);
674 value_embedded_offset (val
), 0,
675 file
, 0, val
, &opts
, current_language
);
677 if (print_raw_format
)
679 fprintf_filtered (file
, "\t(raw ");
680 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
682 fprintf_filtered (file
, ")");
687 struct value_print_options opts
;
689 /* Print the register in hex. */
690 get_formatted_print_options (&opts
, 'x');
693 value_embedded_offset (val
), 0,
694 file
, 0, val
, &opts
, current_language
);
696 if (print_raw_format
)
698 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
701 int size
= register_size (gdbarch
, regnum
);
704 /* The SD field is always in the upper bit of MSTATUS, regardless
705 of the number of bits in MSTATUS. */
706 d
= value_as_long (val
);
708 fprintf_filtered (file
,
709 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
710 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
711 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
712 (int) ((d
>> (xlen
- 1)) & 0x1),
713 (int) ((d
>> 24) & 0x1f),
714 (int) ((d
>> 19) & 0x1),
715 (int) ((d
>> 18) & 0x1),
716 (int) ((d
>> 17) & 0x1),
717 (int) ((d
>> 15) & 0x3),
718 (int) ((d
>> 13) & 0x3),
719 (int) ((d
>> 11) & 0x3),
720 (int) ((d
>> 9) & 0x3),
721 (int) ((d
>> 8) & 0x1),
722 (int) ((d
>> 7) & 0x1),
723 (int) ((d
>> 6) & 0x1),
724 (int) ((d
>> 5) & 0x1),
725 (int) ((d
>> 4) & 0x1),
726 (int) ((d
>> 3) & 0x1),
727 (int) ((d
>> 2) & 0x1),
728 (int) ((d
>> 1) & 0x1),
729 (int) ((d
>> 0) & 0x1));
731 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
736 int size
= register_size (gdbarch
, regnum
);
738 /* The MXL field is always in the upper two bits of MISA,
739 regardless of the number of bits in MISA. Mask out other
740 bits to ensure we have a positive value. */
741 d
= value_as_long (val
);
742 base
= (d
>> ((size
* 8) - 2)) & 0x3;
745 for (; base
> 0; base
--)
747 fprintf_filtered (file
, "\tRV%d", xlen
);
749 for (i
= 0; i
< 26; i
++)
752 fprintf_filtered (file
, "%c", 'A' + i
);
755 else if (regnum
== RISCV_CSR_FCSR_REGNUM
756 || regnum
== RISCV_CSR_FFLAGS_REGNUM
757 || regnum
== RISCV_CSR_FRM_REGNUM
)
761 d
= value_as_long (val
);
763 fprintf_filtered (file
, "\t");
764 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
765 fprintf_filtered (file
,
766 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
767 (int) ((d
>> 5) & 0x7),
768 (int) ((d
>> 4) & 0x1),
769 (int) ((d
>> 3) & 0x1),
770 (int) ((d
>> 2) & 0x1),
771 (int) ((d
>> 1) & 0x1),
772 (int) ((d
>> 0) & 0x1));
774 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
776 static const char * const sfrm
[] =
778 "RNE (round to nearest; ties to even)",
779 "RTZ (Round towards zero)",
780 "RDN (Round down towards -INF)",
781 "RUP (Round up towards +INF)",
782 "RMM (Round to nearest; ties to max magnitude)",
785 "dynamic rounding mode",
787 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
788 ? (d
>> 5) : d
) & 0x3;
790 fprintf_filtered (file
, "%sFRM:%i [%s]",
791 (regnum
== RISCV_CSR_FCSR_REGNUM
796 else if (regnum
== RISCV_PRIV_REGNUM
)
801 d
= value_as_long (val
);
806 static const char * const sprv
[] =
813 fprintf_filtered (file
, "\tprv:%d [%s]",
817 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
821 /* If not a vector register, print it also according to its
823 if (TYPE_VECTOR (regtype
) == 0)
825 get_user_print_options (&opts
);
827 fprintf_filtered (file
, "\t");
829 value_embedded_offset (val
), 0,
830 file
, 0, val
, &opts
, current_language
);
835 fprintf_filtered (file
, "\n");
838 /* Return true if REGNUM is a valid CSR register. The CSR register space
839 is sparsely populated, so not every number is a named CSR. */
842 riscv_is_regnum_a_named_csr (int regnum
)
844 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
845 && regnum
<= RISCV_LAST_CSR_REGNUM
);
849 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
850 #include "opcode/riscv-opc.h"
859 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
863 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
864 struct reggroup
*reggroup
)
866 /* Used by 'info registers' and 'info registers <groupname>'. */
868 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
869 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
872 if (regnum
> RISCV_LAST_REGNUM
)
874 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
878 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
881 if (reggroup
== all_reggroup
)
883 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
885 if (riscv_is_regnum_a_named_csr (regnum
))
889 else if (reggroup
== float_reggroup
)
890 return (riscv_is_fp_regno_p (regnum
)
891 || regnum
== RISCV_CSR_FCSR_REGNUM
892 || regnum
== RISCV_CSR_FFLAGS_REGNUM
893 || regnum
== RISCV_CSR_FRM_REGNUM
);
894 else if (reggroup
== general_reggroup
)
895 return regnum
< RISCV_FIRST_FP_REGNUM
;
896 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
898 if (riscv_has_fp_regs (gdbarch
))
899 return (regnum
<= RISCV_LAST_FP_REGNUM
900 || regnum
== RISCV_CSR_FCSR_REGNUM
901 || regnum
== RISCV_CSR_FFLAGS_REGNUM
902 || regnum
== RISCV_CSR_FRM_REGNUM
);
904 return regnum
< RISCV_FIRST_FP_REGNUM
;
906 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
908 if (regnum
== RISCV_PRIV_REGNUM
)
910 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
912 if (riscv_is_regnum_a_named_csr (regnum
))
916 else if (reggroup
== vector_reggroup
)
922 /* Implement the print_registers_info gdbarch method. This is used by
923 'info registers' and 'info all-registers'. */
926 riscv_print_registers_info (struct gdbarch
*gdbarch
,
927 struct ui_file
*file
,
928 struct frame_info
*frame
,
929 int regnum
, int print_all
)
933 /* Print one specified register. */
934 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
935 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
936 error (_("Not a valid register for the current processor type"));
937 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
941 struct reggroup
*reggroup
;
944 reggroup
= all_reggroup
;
946 reggroup
= general_reggroup
;
948 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
950 /* Zero never changes, so might as well hide by default. */
951 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
954 /* Registers with no name are not valid on this ISA. */
955 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
956 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
959 /* Is the register in the group we're interested in? */
960 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
963 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
968 /* Class that handles one decoded RiscV instruction. */
974 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
977 /* Unknown value is used at initialisation time. */
980 /* These instructions are all the ones we are interested in during the
990 /* These are needed for software breakopint support. */
999 /* These are needed for stepping over atomic sequences. */
1003 /* Other instructions are not interesting during the prologue scan, and
1018 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1020 /* Get the length of the instruction in bytes. */
1022 { return m_length
; }
1024 /* Get the opcode for this instruction. */
1025 enum opcode
opcode () const
1026 { return m_opcode
; }
1028 /* Get destination register field for this instruction. This is only
1029 valid if the OPCODE implies there is such a field for this
1034 /* Get the RS1 register field for this instruction. This is only valid
1035 if the OPCODE implies there is such a field for this instruction. */
1039 /* Get the RS2 register field for this instruction. This is only valid
1040 if the OPCODE implies there is such a field for this instruction. */
1044 /* Get the immediate for this instruction in signed form. This is only
1045 valid if the OPCODE implies there is such a field for this
1047 int imm_signed () const
1052 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1053 int decode_register_index (unsigned long opcode
, int offset
)
1055 return (opcode
>> offset
) & 0x1F;
1058 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1059 int decode_register_index_short (unsigned long opcode
, int offset
)
1061 return ((opcode
>> offset
) & 0x7) + 8;
1064 /* Helper for DECODE, decode 32-bit R-type instruction. */
1065 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1068 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1069 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1070 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1073 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1074 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1077 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1078 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1081 /* Helper for DECODE, decode 32-bit I-type instruction. */
1082 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1085 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1086 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1087 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1090 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1091 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1094 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1095 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
1098 /* Helper for DECODE, decode 32-bit S-type instruction. */
1099 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1102 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1103 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1104 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1107 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1108 encoding is different for each CS format instruction, so extracting
1109 the immediate is left up to the caller, who should pass the extracted
1110 immediate value through in IMM. */
1111 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1115 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1116 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1119 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1120 encoding is different for each CSS format instruction, so extracting
1121 the immediate is left up to the caller, who should pass the extracted
1122 immediate value through in IMM. */
1123 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1127 m_rs1
= RISCV_SP_REGNUM
;
1128 /* Not a compressed register number in this case. */
1129 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1132 /* Helper for DECODE, decode 32-bit U-type instruction. */
1133 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1136 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1137 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1140 /* Helper for DECODE, decode 32-bit J-type instruction. */
1141 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1144 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1145 m_imm
.s
= EXTRACT_UJTYPE_IMM (ival
);
1148 /* Helper for DECODE, decode 32-bit J-type instruction. */
1149 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1152 m_imm
.s
= EXTRACT_RVC_J_IMM (ival
);
1155 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1158 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1159 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1160 m_imm
.s
= EXTRACT_SBTYPE_IMM (ival
);
1163 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1166 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1167 m_imm
.s
= EXTRACT_RVC_B_IMM (ival
);
1170 /* Fetch instruction from target memory at ADDR, return the content of
1171 the instruction, and update LEN with the instruction length. */
1172 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1173 CORE_ADDR addr
, int *len
);
1175 /* The length of the instruction in bytes. Should be 2 or 4. */
1178 /* The instruction opcode. */
1179 enum opcode m_opcode
;
1181 /* The three possible registers an instruction might reference. Not
1182 every instruction fills in all of these registers. Which fields are
1183 valid depends on the opcode. The naming of these fields matches the
1184 naming in the riscv isa manual. */
1189 /* Possible instruction immediate. This is only valid if the instruction
1190 format contains an immediate, not all instruction, whether this is
1191 valid depends on the opcode. Despite only having one format for now
1192 the immediate is packed into a union, later instructions might require
1193 an unsigned formatted immediate, having the union in place now will
1194 reduce the need for code churn later. */
1195 union riscv_insn_immediate
1197 riscv_insn_immediate ()
1207 /* Fetch instruction from target memory at ADDR, return the content of the
1208 instruction, and update LEN with the instruction length. */
1211 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1212 CORE_ADDR addr
, int *len
)
1214 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1216 int instlen
, status
;
1218 /* All insns are at least 16 bits. */
1219 status
= target_read_memory (addr
, buf
, 2);
1221 memory_error (TARGET_XFER_E_IO
, addr
);
1223 /* If we need more, grab it now. */
1224 instlen
= riscv_insn_length (buf
[0]);
1225 gdb_assert (instlen
<= sizeof (buf
));
1230 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1232 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1235 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1238 /* Fetch from target memory an instruction at PC and decode it. This can
1239 throw an error if the memory access fails, callers are responsible for
1240 handling this error if that is appropriate. */
1243 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1247 /* Fetch the instruction, and the instructions length. */
1248 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1252 if (is_add_insn (ival
))
1253 decode_r_type_insn (ADD
, ival
);
1254 else if (is_addw_insn (ival
))
1255 decode_r_type_insn (ADDW
, ival
);
1256 else if (is_addi_insn (ival
))
1257 decode_i_type_insn (ADDI
, ival
);
1258 else if (is_addiw_insn (ival
))
1259 decode_i_type_insn (ADDIW
, ival
);
1260 else if (is_auipc_insn (ival
))
1261 decode_u_type_insn (AUIPC
, ival
);
1262 else if (is_lui_insn (ival
))
1263 decode_u_type_insn (LUI
, ival
);
1264 else if (is_sd_insn (ival
))
1265 decode_s_type_insn (SD
, ival
);
1266 else if (is_sw_insn (ival
))
1267 decode_s_type_insn (SW
, ival
);
1268 else if (is_jal_insn (ival
))
1269 decode_j_type_insn (JAL
, ival
);
1270 else if (is_jalr_insn (ival
))
1271 decode_i_type_insn (JALR
, ival
);
1272 else if (is_beq_insn (ival
))
1273 decode_b_type_insn (BEQ
, ival
);
1274 else if (is_bne_insn (ival
))
1275 decode_b_type_insn (BNE
, ival
);
1276 else if (is_blt_insn (ival
))
1277 decode_b_type_insn (BLT
, ival
);
1278 else if (is_bge_insn (ival
))
1279 decode_b_type_insn (BGE
, ival
);
1280 else if (is_bltu_insn (ival
))
1281 decode_b_type_insn (BLTU
, ival
);
1282 else if (is_bgeu_insn (ival
))
1283 decode_b_type_insn (BGEU
, ival
);
1284 else if (is_lr_w_insn (ival
))
1285 decode_r_type_insn (LR
, ival
);
1286 else if (is_lr_d_insn (ival
))
1287 decode_r_type_insn (LR
, ival
);
1288 else if (is_sc_w_insn (ival
))
1289 decode_r_type_insn (SC
, ival
);
1290 else if (is_sc_d_insn (ival
))
1291 decode_r_type_insn (SC
, ival
);
1293 /* None of the other fields are valid in this case. */
1296 else if (m_length
== 2)
1298 int xlen
= riscv_isa_xlen (gdbarch
);
1300 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1301 C_JALR. So must try to match C_JALR first as it has more bits in
1303 if (is_c_jalr_insn (ival
))
1304 decode_cr_type_insn (JALR
, ival
);
1305 else if (is_c_add_insn (ival
))
1306 decode_cr_type_insn (ADD
, ival
);
1307 /* C_ADDW is RV64 and RV128 only. */
1308 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1309 decode_cr_type_insn (ADDW
, ival
);
1310 else if (is_c_addi_insn (ival
))
1311 decode_ci_type_insn (ADDI
, ival
);
1312 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1313 only and C_JAL is RV32 only. */
1314 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1315 decode_ci_type_insn (ADDIW
, ival
);
1316 else if (xlen
== 4 && is_c_jal_insn (ival
))
1317 decode_cj_type_insn (JAL
, ival
);
1318 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1319 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1321 else if (is_c_addi16sp_insn (ival
))
1324 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1325 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1327 else if (is_c_addi4spn_insn (ival
))
1330 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1331 m_rs1
= RISCV_SP_REGNUM
;
1332 m_imm
.s
= EXTRACT_RVC_ADDI4SPN_IMM (ival
);
1334 else if (is_c_lui_insn (ival
))
1337 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1338 m_imm
.s
= EXTRACT_RVC_LUI_IMM (ival
);
1340 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1341 and C_FSW is RV32 only. */
1342 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1343 decode_cs_type_insn (SD
, ival
, EXTRACT_RVC_LD_IMM (ival
));
1344 else if (is_c_sw_insn (ival
))
1345 decode_cs_type_insn (SW
, ival
, EXTRACT_RVC_LW_IMM (ival
));
1346 else if (is_c_swsp_insn (ival
))
1347 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SWSP_IMM (ival
));
1348 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1349 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SDSP_IMM (ival
));
1350 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1351 So must try to match C_JR first as it ahs more bits in mask. */
1352 else if (is_c_jr_insn (ival
))
1353 decode_cr_type_insn (JALR
, ival
);
1354 else if (is_c_j_insn (ival
))
1355 decode_cj_type_insn (JAL
, ival
);
1356 else if (is_c_beqz_insn (ival
))
1357 decode_cb_type_insn (BEQ
, ival
);
1358 else if (is_c_bnez_insn (ival
))
1359 decode_cb_type_insn (BNE
, ival
);
1361 /* None of the other fields of INSN are valid in this case. */
1365 internal_error (__FILE__
, __LINE__
,
1366 _("unable to decode %d byte instructions in "
1367 "prologue at %s"), m_length
,
1368 core_addr_to_string (pc
));
1371 /* The prologue scanner. This is currently only used for skipping the
1372 prologue of a function when the DWARF information is not sufficient.
1373 However, it is written with filling of the frame cache in mind, which
1374 is why different groups of stack setup instructions are split apart
1375 during the core of the inner loop. In the future, the intention is to
1376 extend this function to fully support building up a frame cache that
1377 can unwind register values when there is no DWARF information. */
1380 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1381 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1382 struct riscv_unwind_cache
*cache
)
1384 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1385 CORE_ADDR end_prologue_addr
= 0;
1387 /* Find an upper limit on the function prologue using the debug
1388 information. If the debug information could not be used to provide
1389 that bound, then use an arbitrary large number as the upper bound. */
1390 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1391 if (after_prologue_pc
== 0)
1392 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1393 if (after_prologue_pc
< end_pc
)
1394 end_pc
= after_prologue_pc
;
1396 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1397 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1398 regs
[regno
] = pv_register (regno
, 0);
1399 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1401 if (riscv_debug_unwinder
)
1404 "Prologue scan for function starting at %s (limit %s)\n",
1405 core_addr_to_string (start_pc
),
1406 core_addr_to_string (end_pc
));
1408 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1410 struct riscv_insn insn
;
1412 /* Decode the current instruction, and decide where the next
1413 instruction lives based on the size of this instruction. */
1414 insn
.decode (gdbarch
, cur_pc
);
1415 gdb_assert (insn
.length () > 0);
1416 next_pc
= cur_pc
+ insn
.length ();
1418 /* Look for common stack adjustment insns. */
1419 if ((insn
.opcode () == riscv_insn::ADDI
1420 || insn
.opcode () == riscv_insn::ADDIW
)
1421 && insn
.rd () == RISCV_SP_REGNUM
1422 && insn
.rs1 () == RISCV_SP_REGNUM
)
1424 /* Handle: addi sp, sp, -i
1425 or: addiw sp, sp, -i */
1426 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1427 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1429 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1431 else if ((insn
.opcode () == riscv_insn::SW
1432 || insn
.opcode () == riscv_insn::SD
)
1433 && (insn
.rs1 () == RISCV_SP_REGNUM
1434 || insn
.rs1 () == RISCV_FP_REGNUM
))
1436 /* Handle: sw reg, offset(sp)
1437 or: sd reg, offset(sp)
1438 or: sw reg, offset(s0)
1439 or: sd reg, offset(s0) */
1440 /* Instruction storing a register onto the stack. */
1441 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1442 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1443 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
1444 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
1447 else if (insn
.opcode () == riscv_insn::ADDI
1448 && insn
.rd () == RISCV_FP_REGNUM
1449 && insn
.rs1 () == RISCV_SP_REGNUM
)
1451 /* Handle: addi s0, sp, size */
1452 /* Instructions setting up the frame pointer. */
1453 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1454 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1456 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1458 else if ((insn
.opcode () == riscv_insn::ADD
1459 || insn
.opcode () == riscv_insn::ADDW
)
1460 && insn
.rd () == RISCV_FP_REGNUM
1461 && insn
.rs1 () == RISCV_SP_REGNUM
1462 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1464 /* Handle: add s0, sp, 0
1465 or: addw s0, sp, 0 */
1466 /* Instructions setting up the frame pointer. */
1467 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1468 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1469 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
1471 else if ((insn
.opcode () == riscv_insn::ADDI
1472 && insn
.rd () == RISCV_ZERO_REGNUM
1473 && insn
.rs1 () == RISCV_ZERO_REGNUM
1474 && insn
.imm_signed () == 0))
1476 /* Handle: add x0, x0, 0 (NOP) */
1478 else if (insn
.opcode () == riscv_insn::AUIPC
)
1480 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1481 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
1483 else if (insn
.opcode () == riscv_insn::LUI
)
1485 /* Handle: lui REG, n
1486 Where REG is not gp register. */
1487 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1488 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
1490 else if (insn
.opcode () == riscv_insn::ADDI
)
1492 /* Handle: addi REG1, REG2, IMM */
1493 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1494 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1496 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1498 else if (insn
.opcode () == riscv_insn::ADD
)
1500 /* Handle: addi REG1, REG2, IMM */
1501 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1502 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1503 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1504 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
1508 end_prologue_addr
= cur_pc
;
1513 if (end_prologue_addr
== 0)
1514 end_prologue_addr
= cur_pc
;
1516 if (riscv_debug_unwinder
)
1517 fprintf_unfiltered (gdb_stdlog
, "End of prologue at %s\n",
1518 core_addr_to_string (end_prologue_addr
));
1522 /* Figure out if it is a frame pointer or just a stack pointer. Also
1523 the offset held in the pv_t is from the original register value to
1524 the current value, which for a grows down stack means a negative
1525 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1526 from the current value to the original value. */
1527 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
1529 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
1530 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
1534 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
1535 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
1538 /* Assign offset from old SP to all saved registers. As we don't
1539 have the previous value for the frame base register at this
1540 point, we store the offset as the address in the trad_frame, and
1541 then convert this to an actual address later. */
1542 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
1545 if (stack
.find_reg (gdbarch
, i
, &offset
))
1547 if (riscv_debug_unwinder
)
1549 /* Display OFFSET as a signed value, the offsets are from
1550 the frame base address to the registers location on
1551 the stack, with a descending stack this means the
1552 offsets are always negative. */
1553 fprintf_unfiltered (gdb_stdlog
,
1554 "Register $%s at stack offset %s\n",
1555 gdbarch_register_name (gdbarch
, i
),
1556 plongest ((LONGEST
) offset
));
1558 trad_frame_set_addr (cache
->regs
, i
, offset
);
1563 return end_prologue_addr
;
1566 /* Implement the riscv_skip_prologue gdbarch method. */
1569 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1571 CORE_ADDR func_addr
;
1573 /* See if we can determine the end of the prologue via the symbol
1574 table. If so, then return either PC, or the PC after the
1575 prologue, whichever is greater. */
1576 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1578 CORE_ADDR post_prologue_pc
1579 = skip_prologue_using_sal (gdbarch
, func_addr
);
1581 if (post_prologue_pc
!= 0)
1582 return std::max (pc
, post_prologue_pc
);
1585 /* Can't determine prologue from the symbol table, need to examine
1586 instructions. Pass -1 for the end address to indicate the prologue
1587 scanner can scan as far as it needs to find the end of the prologue. */
1588 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
1591 /* Implement the gdbarch push dummy code callback. */
1594 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1595 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1596 struct type
*value_type
, CORE_ADDR
*real_pc
,
1597 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1599 /* Allocate space for a breakpoint, and keep the stack correctly
1607 /* Compute the alignment of the type T. Used while setting up the
1608 arguments for a dummy call. */
1611 riscv_type_alignment (struct type
*t
)
1613 t
= check_typedef (t
);
1614 switch (TYPE_CODE (t
))
1617 error (_("Could not compute alignment of type"));
1619 case TYPE_CODE_RVALUE_REF
:
1621 case TYPE_CODE_ENUM
:
1625 case TYPE_CODE_CHAR
:
1626 case TYPE_CODE_BOOL
:
1627 return TYPE_LENGTH (t
);
1629 case TYPE_CODE_ARRAY
:
1630 if (TYPE_VECTOR (t
))
1631 return std::min (TYPE_LENGTH (t
), (unsigned) BIGGEST_ALIGNMENT
);
1634 case TYPE_CODE_COMPLEX
:
1635 return riscv_type_alignment (TYPE_TARGET_TYPE (t
));
1637 case TYPE_CODE_STRUCT
:
1638 case TYPE_CODE_UNION
:
1643 for (i
= 0; i
< TYPE_NFIELDS (t
); ++i
)
1645 if (TYPE_FIELD_LOC_KIND (t
, i
) == FIELD_LOC_KIND_BITPOS
)
1647 int a
= riscv_type_alignment (TYPE_FIELD_TYPE (t
, i
));
1657 /* Holds information about a single argument either being passed to an
1658 inferior function, or returned from an inferior function. This includes
1659 information about the size, type, etc of the argument, and also
1660 information about how the argument will be passed (or returned). */
1662 struct riscv_arg_info
1664 /* Contents of the argument. */
1665 const gdb_byte
*contents
;
1667 /* Length of argument. */
1670 /* Alignment required for an argument of this type. */
1673 /* The type for this argument. */
1676 /* Each argument can have either 1 or 2 locations assigned to it. Each
1677 location describes where part of the argument will be placed. The
1678 second location is valid based on the LOC_TYPE and C_LENGTH fields
1679 of the first location (which is always valid). */
1682 /* What type of location this is. */
1685 /* Argument passed in a register. */
1688 /* Argument passed as an on stack argument. */
1691 /* Argument passed by reference. The second location is always
1692 valid for a BY_REF argument, and describes where the address
1693 of the BY_REF argument should be placed. */
1697 /* Information that depends on the location type. */
1700 /* Which register number to use. */
1703 /* The offset into the stack region. */
1707 /* The length of contents covered by this location. If this is less
1708 than the total length of the argument, then the second location
1709 will be valid, and will describe where the rest of the argument
1713 /* The offset within CONTENTS for this part of the argument. Will
1714 always be 0 for the first part. For the second part of the
1715 argument, this might be the C_LENGTH value of the first part,
1716 however, if we are passing a structure in two registers, and there's
1717 is padding between the first and second field, then this offset
1718 might be greater than the length of the first argument part. When
1719 the second argument location is not holding part of the argument
1720 value, but is instead holding the address of a reference argument,
1721 then this offset will be set to 0. */
1725 /* TRUE if this is an unnamed argument. */
1729 /* Information about a set of registers being used for passing arguments as
1730 part of a function call. The register set must be numerically
1731 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1732 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1734 struct riscv_arg_reg
1736 riscv_arg_reg (int first
, int last
)
1737 : next_regnum (first
),
1743 /* The GDB register number to use in this set. */
1746 /* The last GDB register number to use in this set. */
1750 /* Arguments can be passed as on stack arguments, or by reference. The
1751 on stack arguments must be in a continuous region starting from $sp,
1752 while the by reference arguments can be anywhere, but we'll put them
1753 on the stack after (at higher address) the on stack arguments.
1755 This might not be the right approach to take. The ABI is clear that
1756 an argument passed by reference can be modified by the callee, which
1757 us placing the argument (temporarily) onto the stack will not achieve
1758 (changes will be lost). There's also the possibility that very large
1759 arguments could overflow the stack.
1761 This struct is used to track offset into these two areas for where
1762 arguments are to be placed. */
1763 struct riscv_memory_offsets
1765 riscv_memory_offsets ()
1772 /* Offset into on stack argument area. */
1775 /* Offset into the pass by reference area. */
1779 /* Holds information about where arguments to a call will be placed. This
1780 is updated as arguments are added onto the call, and can be used to
1781 figure out where the next argument should be placed. */
1783 struct riscv_call_info
1785 riscv_call_info (struct gdbarch
*gdbarch
)
1786 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1787 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1789 xlen
= riscv_isa_xlen (gdbarch
);
1790 flen
= riscv_isa_flen (gdbarch
);
1792 /* Disable use of floating point registers if needed. */
1793 if (!riscv_has_fp_abi (gdbarch
))
1794 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1797 /* Track the memory areas used for holding in-memory arguments to a
1799 struct riscv_memory_offsets memory
;
1801 /* Holds information about the next integer register to use for passing
1803 struct riscv_arg_reg int_regs
;
1805 /* Holds information about the next floating point register to use for
1806 passing an argument. */
1807 struct riscv_arg_reg float_regs
;
1809 /* The XLEN and FLEN are copied in to this structure for convenience, and
1810 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1815 /* Return the number of registers available for use as parameters in the
1816 register set REG. Returned value can be 0 or more. */
1819 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1821 if (reg
->next_regnum
> reg
->last_regnum
)
1824 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1827 /* If there is at least one register available in the register set REG then
1828 the next register from REG is assigned to LOC and the length field of
1829 LOC is updated to LENGTH. The register set REG is updated to indicate
1830 that the assigned register is no longer available and the function
1833 If there are no registers available in REG then the function returns
1834 false, and LOC and REG are unchanged. */
1837 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1838 struct riscv_arg_reg
*reg
,
1839 int length
, int offset
)
1841 if (reg
->next_regnum
<= reg
->last_regnum
)
1843 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1844 loc
->loc_data
.regno
= reg
->next_regnum
;
1846 loc
->c_length
= length
;
1847 loc
->c_offset
= offset
;
1854 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1855 record that an area of stack has been used to hold the parameter
1858 The length field of LOC is updated to LENGTH, the length of the
1859 parameter being stored, and ALIGN is the alignment required by the
1860 parameter, which will affect how memory is allocated out of MEMORY. */
1863 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1864 struct riscv_memory_offsets
*memory
,
1865 int length
, int align
)
1867 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1869 = align_up (memory
->arg_offset
, align
);
1870 loc
->loc_data
.offset
= memory
->arg_offset
;
1871 memory
->arg_offset
+= length
;
1872 loc
->c_length
= length
;
1874 /* Offset is always 0, either we're the first location part, in which
1875 case we're reading content from the start of the argument, or we're
1876 passing the address of a reference argument, so 0. */
1880 /* Update AINFO, which describes an argument that should be passed or
1881 returned using the integer ABI. The argloc fields within AINFO are
1882 updated to describe the location in which the argument will be passed to
1883 a function, or returned from a function.
1885 The CINFO structure contains the ongoing call information, the holds
1886 information such as which argument registers are remaining to be
1887 assigned to parameter, and how much memory has been used by parameters
1890 By examining the state of CINFO a suitable location can be selected,
1891 and assigned to AINFO. */
1894 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1895 struct riscv_call_info
*cinfo
)
1897 if (ainfo
->length
> (2 * cinfo
->xlen
))
1899 /* Argument is going to be passed by reference. */
1900 ainfo
->argloc
[0].loc_type
1901 = riscv_arg_info::location::by_ref
;
1902 cinfo
->memory
.ref_offset
1903 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1904 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1905 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1906 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1908 /* The second location for this argument is given over to holding the
1909 address of the by-reference data. Pass 0 for the offset as this
1910 is not part of the actual argument value. */
1911 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1914 riscv_assign_stack_location (&ainfo
->argloc
[1],
1915 &cinfo
->memory
, cinfo
->xlen
,
1920 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
1921 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
1923 /* Unnamed arguments in registers that require 2*XLEN alignment are
1924 passed in an aligned register pair. */
1925 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
1926 && cinfo
->int_regs
.next_regnum
& 1)
1927 cinfo
->int_regs
.next_regnum
++;
1929 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1930 &cinfo
->int_regs
, len
, 0))
1931 riscv_assign_stack_location (&ainfo
->argloc
[0],
1932 &cinfo
->memory
, len
, align
);
1934 if (len
< ainfo
->length
)
1936 len
= ainfo
->length
- len
;
1937 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1938 &cinfo
->int_regs
, len
,
1940 riscv_assign_stack_location (&ainfo
->argloc
[1],
1941 &cinfo
->memory
, len
, cinfo
->xlen
);
1946 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1947 is being passed with the floating point ABI. */
1950 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1951 struct riscv_call_info
*cinfo
)
1953 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
1954 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1957 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1960 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1964 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1965 is a complex floating point argument, and is therefore handled
1966 differently to other argument types. */
1969 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1970 struct riscv_call_info
*cinfo
)
1972 if (ainfo
->length
<= (2 * cinfo
->flen
)
1973 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
1974 && !ainfo
->is_unnamed
)
1977 int len
= ainfo
->length
/ 2;
1979 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1980 &cinfo
->float_regs
, len
, len
);
1981 gdb_assert (result
);
1983 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1984 &cinfo
->float_regs
, len
, len
);
1985 gdb_assert (result
);
1988 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1991 /* A structure used for holding information about a structure type within
1992 the inferior program. The RiscV ABI has special rules for handling some
1993 structures with a single field or with two fields. The counting of
1994 fields here is done after flattening out all nested structures. */
1996 class riscv_struct_info
1999 riscv_struct_info ()
2000 : m_number_of_fields (0),
2001 m_types
{ nullptr, nullptr }
2006 /* Analyse TYPE descending into nested structures, count the number of
2007 scalar fields and record the types of the first two fields found. */
2008 void analyse (struct type
*type
);
2010 /* The number of scalar fields found in the analysed type. This is
2011 currently only accurate if the value returned is 0, 1, or 2 as the
2012 analysis stops counting when the number of fields is 3. This is
2013 because the RiscV ABI only has special cases for 1 or 2 fields,
2014 anything else we just don't care about. */
2015 int number_of_fields () const
2016 { return m_number_of_fields
; }
2018 /* Return the type for scalar field INDEX within the analysed type. Will
2019 return nullptr if there is no field at that index. Only INDEX values
2020 0 and 1 can be requested as the RiscV ABI only has special cases for
2021 structures with 1 or 2 fields. */
2022 struct type
*field_type (int index
) const
2024 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2025 return m_types
[index
];
2029 /* The number of scalar fields found within the structure after recursing
2030 into nested structures. */
2031 int m_number_of_fields
;
2033 /* The types of the first two scalar fields found within the structure
2034 after recursing into nested structures. */
2035 struct type
*m_types
[2];
2038 /* Analyse TYPE descending into nested structures, count the number of
2039 scalar fields and record the types of the first two fields found. */
2042 riscv_struct_info::analyse (struct type
*type
)
2044 unsigned int count
= TYPE_NFIELDS (type
);
2047 for (i
= 0; i
< count
; ++i
)
2049 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
2052 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
2053 field_type
= check_typedef (field_type
);
2055 switch (TYPE_CODE (field_type
))
2057 case TYPE_CODE_STRUCT
:
2058 analyse (field_type
);
2062 /* RiscV only flattens out structures. Anything else does not
2063 need to be flattened, we just record the type, and when we
2064 look at the analysis results we'll realise this is not a
2065 structure we can special case, and pass the structure in
2067 if (m_number_of_fields
< 2)
2068 m_types
[m_number_of_fields
] = field_type
;
2069 m_number_of_fields
++;
2073 /* RiscV only has special handling for structures with 1 or 2 scalar
2074 fields, any more than that and the structure is just passed in
2075 memory. We can safely drop out early when we find 3 or more
2078 if (m_number_of_fields
> 2)
2083 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2084 is a structure. Small structures on RiscV have some special case
2085 handling in order that the structure might be passed in register.
2086 Larger structures are passed in memory. After assigning location
2087 information to AINFO, CINFO will have been updated. */
2090 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2091 struct riscv_call_info
*cinfo
)
2093 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2095 struct riscv_struct_info sinfo
;
2097 sinfo
.analyse (ainfo
->type
);
2098 if (sinfo
.number_of_fields () == 1
2099 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
2101 gdb_assert (TYPE_LENGTH (ainfo
->type
)
2102 == TYPE_LENGTH (sinfo
.field_type (0)));
2103 return riscv_call_arg_complex_float (ainfo
, cinfo
);
2106 if (sinfo
.number_of_fields () == 1
2107 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
2109 gdb_assert (TYPE_LENGTH (ainfo
->type
)
2110 == TYPE_LENGTH (sinfo
.field_type (0)));
2111 return riscv_call_arg_scalar_float (ainfo
, cinfo
);
2114 if (sinfo
.number_of_fields () == 2
2115 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
2116 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2117 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
2118 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
2119 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2121 int len0
, len1
, offset
;
2123 gdb_assert (TYPE_LENGTH (ainfo
->type
) <= (2 * cinfo
->flen
));
2125 len0
= TYPE_LENGTH (sinfo
.field_type (0));
2126 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2127 &cinfo
->float_regs
, len0
, 0))
2128 error (_("failed during argument setup"));
2130 len1
= TYPE_LENGTH (sinfo
.field_type (1));
2131 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
2132 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
2133 - TYPE_LENGTH (sinfo
.field_type (0))));
2135 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2138 error (_("failed during argument setup"));
2142 if (sinfo
.number_of_fields () == 2
2143 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2144 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
2145 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2146 && is_integral_type (sinfo
.field_type (1))
2147 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
2149 int len0
, len1
, offset
;
2151 gdb_assert (TYPE_LENGTH (ainfo
->type
)
2152 <= (cinfo
->flen
+ cinfo
->xlen
));
2154 len0
= TYPE_LENGTH (sinfo
.field_type (0));
2155 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2156 &cinfo
->float_regs
, len0
, 0))
2157 error (_("failed during argument setup"));
2159 len1
= TYPE_LENGTH (sinfo
.field_type (1));
2160 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
2161 gdb_assert (len1
<= cinfo
->xlen
);
2162 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2163 &cinfo
->int_regs
, len1
, offset
))
2164 error (_("failed during argument setup"));
2168 if (sinfo
.number_of_fields () == 2
2169 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2170 && (is_integral_type (sinfo
.field_type (0))
2171 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
2172 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
2173 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
2175 int len0
, len1
, offset
;
2177 gdb_assert (TYPE_LENGTH (ainfo
->type
)
2178 <= (cinfo
->flen
+ cinfo
->xlen
));
2180 len0
= TYPE_LENGTH (sinfo
.field_type (0));
2181 len1
= TYPE_LENGTH (sinfo
.field_type (1));
2182 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
2184 gdb_assert (len0
<= cinfo
->xlen
);
2185 gdb_assert (len1
<= cinfo
->flen
);
2187 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2188 &cinfo
->int_regs
, len0
, 0))
2189 error (_("failed during argument setup"));
2191 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2194 error (_("failed during argument setup"));
2200 /* Non of the structure flattening cases apply, so we just pass using
2202 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2205 /* Assign a location to call (or return) argument AINFO, the location is
2206 selected from CINFO which holds information about what call argument
2207 locations are available for use next. The TYPE is the type of the
2208 argument being passed, this information is recorded into AINFO (along
2209 with some additional information derived from the type). IS_UNNAMED
2210 is true if this is an unnamed (stdarg) argument, this info is also
2211 recorded into AINFO.
2213 After assigning a location to AINFO, CINFO will have been updated. */
2216 riscv_arg_location (struct gdbarch
*gdbarch
,
2217 struct riscv_arg_info
*ainfo
,
2218 struct riscv_call_info
*cinfo
,
2219 struct type
*type
, bool is_unnamed
)
2222 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
2223 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
2224 ainfo
->is_unnamed
= is_unnamed
;
2225 ainfo
->contents
= nullptr;
2227 switch (TYPE_CODE (ainfo
->type
))
2230 case TYPE_CODE_BOOL
:
2231 case TYPE_CODE_CHAR
:
2232 case TYPE_CODE_RANGE
:
2233 case TYPE_CODE_ENUM
:
2235 if (ainfo
->length
<= cinfo
->xlen
)
2237 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2238 ainfo
->length
= cinfo
->xlen
;
2240 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2242 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2243 ainfo
->length
= 2 * cinfo
->xlen
;
2246 /* Recalculate the alignment requirement. */
2247 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
2248 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2252 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2255 case TYPE_CODE_COMPLEX
:
2256 riscv_call_arg_complex_float (ainfo
, cinfo
);
2259 case TYPE_CODE_STRUCT
:
2260 riscv_call_arg_struct (ainfo
, cinfo
);
2264 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2269 /* Used for printing debug information about the call argument location in
2270 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2271 addresses for the location of pass-by-reference and
2272 arguments-on-the-stack memory areas. */
2275 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2276 struct riscv_arg_info
*info
,
2277 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2279 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2280 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2281 switch (info
->argloc
[0].loc_type
)
2283 case riscv_arg_info::location::in_reg
:
2285 (stream
, ", register %s",
2286 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2287 if (info
->argloc
[0].c_length
< info
->length
)
2289 switch (info
->argloc
[1].loc_type
)
2291 case riscv_arg_info::location::in_reg
:
2293 (stream
, ", register %s",
2294 gdbarch_register_name (gdbarch
,
2295 info
->argloc
[1].loc_data
.regno
));
2298 case riscv_arg_info::location::on_stack
:
2299 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2300 info
->argloc
[1].loc_data
.offset
);
2303 case riscv_arg_info::location::by_ref
:
2305 /* The second location should never be a reference, any
2306 argument being passed by reference just places its address
2307 in the first location and is done. */
2308 error (_("invalid argument location"));
2312 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2313 fprintf_unfiltered (stream
, " (offset 0x%x)",
2314 info
->argloc
[1].c_offset
);
2318 case riscv_arg_info::location::on_stack
:
2319 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2320 info
->argloc
[0].loc_data
.offset
);
2323 case riscv_arg_info::location::by_ref
:
2325 (stream
, ", by reference, data at offset 0x%x (%s)",
2326 info
->argloc
[0].loc_data
.offset
,
2327 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2328 if (info
->argloc
[1].loc_type
2329 == riscv_arg_info::location::in_reg
)
2331 (stream
, ", address in register %s",
2332 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2335 gdb_assert (info
->argloc
[1].loc_type
2336 == riscv_arg_info::location::on_stack
);
2338 (stream
, ", address on stack at offset 0x%x (%s)",
2339 info
->argloc
[1].loc_data
.offset
,
2340 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2345 gdb_assert_not_reached (_("unknown argument location type"));
2349 /* Implement the push dummy call gdbarch callback. */
2352 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2353 struct value
*function
,
2354 struct regcache
*regcache
,
2357 struct value
**args
,
2359 function_call_return_method return_method
,
2360 CORE_ADDR struct_addr
)
2363 CORE_ADDR sp_args
, sp_refs
;
2364 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2366 struct riscv_arg_info
*arg_info
=
2367 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2369 struct riscv_call_info
call_info (gdbarch
);
2373 struct type
*ftype
= check_typedef (value_type (function
));
2375 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
2376 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
2378 /* We'll use register $a0 if we're returning a struct. */
2379 if (return_method
== return_method_struct
)
2380 ++call_info
.int_regs
.next_regnum
;
2382 for (i
= 0; i
< nargs
; ++i
)
2384 struct value
*arg_value
;
2385 struct type
*arg_type
;
2386 struct riscv_arg_info
*info
= &arg_info
[i
];
2388 arg_value
= args
[i
];
2389 arg_type
= check_typedef (value_type (arg_value
));
2391 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
2392 TYPE_VARARGS (ftype
) && i
>= TYPE_NFIELDS (ftype
));
2394 if (info
->type
!= arg_type
)
2395 arg_value
= value_cast (info
->type
, arg_value
);
2396 info
->contents
= value_contents (arg_value
);
2399 /* Adjust the stack pointer and align it. */
2400 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2401 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2403 if (riscv_debug_infcall
> 0)
2405 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2406 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2407 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2408 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2409 call_info
.xlen
, call_info
.flen
);
2410 if (return_method
== return_method_struct
)
2411 fprintf_unfiltered (gdb_stdlog
,
2412 "[*] struct return pointer in register $A0\n");
2413 for (i
= 0; i
< nargs
; ++i
)
2415 struct riscv_arg_info
*info
= &arg_info
[i
];
2417 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2418 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2419 fprintf_unfiltered (gdb_stdlog
, "\n");
2421 if (call_info
.memory
.arg_offset
> 0
2422 || call_info
.memory
.ref_offset
> 0)
2424 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2425 core_addr_to_string (osp
));
2426 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2427 call_info
.memory
.arg_offset
);
2428 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2429 call_info
.memory
.ref_offset
);
2430 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2431 core_addr_to_string_nz (osp
- sp
));
2435 /* Now load the argument into registers, or onto the stack. */
2437 if (return_method
== return_method_struct
)
2439 gdb_byte buf
[sizeof (LONGEST
)];
2441 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2442 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
2445 for (i
= 0; i
< nargs
; ++i
)
2448 int second_arg_length
= 0;
2449 const gdb_byte
*second_arg_data
;
2450 struct riscv_arg_info
*info
= &arg_info
[i
];
2452 gdb_assert (info
->length
> 0);
2454 switch (info
->argloc
[0].loc_type
)
2456 case riscv_arg_info::location::in_reg
:
2458 gdb_byte tmp
[sizeof (ULONGEST
)];
2460 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2461 /* FP values in FP registers must be NaN-boxed. */
2462 if (riscv_is_fp_regno_p (info
->argloc
[0].loc_data
.regno
)
2463 && info
->argloc
[0].c_length
< call_info
.flen
)
2464 memset (tmp
, -1, sizeof (tmp
));
2466 memset (tmp
, 0, sizeof (tmp
));
2467 memcpy (tmp
, info
->contents
, info
->argloc
[0].c_length
);
2468 regcache
->cooked_write (info
->argloc
[0].loc_data
.regno
, tmp
);
2470 ((info
->argloc
[0].c_length
< info
->length
)
2471 ? info
->argloc
[1].c_length
: 0);
2472 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2476 case riscv_arg_info::location::on_stack
:
2477 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2478 write_memory (dst
, info
->contents
, info
->length
);
2479 second_arg_length
= 0;
2482 case riscv_arg_info::location::by_ref
:
2483 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2484 write_memory (dst
, info
->contents
, info
->length
);
2486 second_arg_length
= call_info
.xlen
;
2487 second_arg_data
= (gdb_byte
*) &dst
;
2491 gdb_assert_not_reached (_("unknown argument location type"));
2494 if (second_arg_length
> 0)
2496 switch (info
->argloc
[1].loc_type
)
2498 case riscv_arg_info::location::in_reg
:
2500 gdb_byte tmp
[sizeof (ULONGEST
)];
2502 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2503 && second_arg_length
<= call_info
.flen
)
2504 || second_arg_length
<= call_info
.xlen
);
2505 /* FP values in FP registers must be NaN-boxed. */
2506 if (riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2507 && second_arg_length
< call_info
.flen
)
2508 memset (tmp
, -1, sizeof (tmp
));
2510 memset (tmp
, 0, sizeof (tmp
));
2511 memcpy (tmp
, second_arg_data
, second_arg_length
);
2512 regcache
->cooked_write (info
->argloc
[1].loc_data
.regno
, tmp
);
2516 case riscv_arg_info::location::on_stack
:
2520 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2521 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2525 case riscv_arg_info::location::by_ref
:
2527 /* The second location should never be a reference, any
2528 argument being passed by reference just places its address
2529 in the first location and is done. */
2530 error (_("invalid argument location"));
2536 /* Set the dummy return value to bp_addr.
2537 A dummy breakpoint will be setup to execute the call. */
2539 if (riscv_debug_infcall
> 0)
2540 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2541 core_addr_to_string (bp_addr
));
2542 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2544 /* Finally, update the stack pointer. */
2546 if (riscv_debug_infcall
> 0)
2547 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2548 core_addr_to_string (sp
));
2549 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2554 /* Implement the return_value gdbarch method. */
2556 static enum return_value_convention
2557 riscv_return_value (struct gdbarch
*gdbarch
,
2558 struct value
*function
,
2560 struct regcache
*regcache
,
2562 const gdb_byte
*writebuf
)
2564 struct riscv_call_info
call_info (gdbarch
);
2565 struct riscv_arg_info info
;
2566 struct type
*arg_type
;
2568 arg_type
= check_typedef (type
);
2569 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
2571 if (riscv_debug_infcall
> 0)
2573 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2574 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2575 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2576 fprintf_unfiltered (gdb_stdlog
, "\n");
2579 if (readbuf
!= nullptr || writebuf
!= nullptr)
2581 unsigned int arg_len
;
2582 struct value
*abi_val
;
2583 gdb_byte
*old_readbuf
= nullptr;
2586 /* We only do one thing at a time. */
2587 gdb_assert (readbuf
== nullptr || writebuf
== nullptr);
2589 /* In some cases the argument is not returned as the declared type,
2590 and we need to cast to or from the ABI type in order to
2591 correctly access the argument. When writing to the machine we
2592 do the cast here, when reading from the machine the cast occurs
2593 later, after extracting the value. As the ABI type can be
2594 larger than the declared type, then the read or write buffers
2595 passed in might be too small. Here we ensure that we are using
2596 buffers of sufficient size. */
2597 if (writebuf
!= nullptr)
2599 struct value
*arg_val
= value_from_contents (arg_type
, writebuf
);
2600 abi_val
= value_cast (info
.type
, arg_val
);
2601 writebuf
= value_contents_raw (abi_val
);
2605 abi_val
= allocate_value (info
.type
);
2606 old_readbuf
= readbuf
;
2607 readbuf
= value_contents_raw (abi_val
);
2609 arg_len
= TYPE_LENGTH (info
.type
);
2611 switch (info
.argloc
[0].loc_type
)
2613 /* Return value in register(s). */
2614 case riscv_arg_info::location::in_reg
:
2616 regnum
= info
.argloc
[0].loc_data
.regno
;
2617 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
2618 gdb_assert (info
.argloc
[0].c_length
2619 <= register_size (gdbarch
, regnum
));
2622 regcache
->cooked_read_part (regnum
, 0,
2623 info
.argloc
[0].c_length
,
2627 regcache
->cooked_write_part (regnum
, 0,
2628 info
.argloc
[0].c_length
,
2631 /* A return value in register can have a second part in a
2633 if (info
.argloc
[0].c_length
< info
.length
)
2635 switch (info
.argloc
[1].loc_type
)
2637 case riscv_arg_info::location::in_reg
:
2638 regnum
= info
.argloc
[1].loc_data
.regno
;
2640 gdb_assert ((info
.argloc
[0].c_length
2641 + info
.argloc
[1].c_length
) <= arg_len
);
2642 gdb_assert (info
.argloc
[1].c_length
2643 <= register_size (gdbarch
, regnum
));
2647 readbuf
+= info
.argloc
[1].c_offset
;
2648 regcache
->cooked_read_part (regnum
, 0,
2649 info
.argloc
[1].c_length
,
2655 writebuf
+= info
.argloc
[1].c_offset
;
2656 regcache
->cooked_write_part (regnum
, 0,
2657 info
.argloc
[1].c_length
,
2662 case riscv_arg_info::location::by_ref
:
2663 case riscv_arg_info::location::on_stack
:
2665 error (_("invalid argument location"));
2672 /* Return value by reference will have its address in A0. */
2673 case riscv_arg_info::location::by_ref
:
2677 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2679 if (readbuf
!= nullptr)
2680 read_memory (addr
, readbuf
, info
.length
);
2681 if (writebuf
!= nullptr)
2682 write_memory (addr
, writebuf
, info
.length
);
2686 case riscv_arg_info::location::on_stack
:
2688 error (_("invalid argument location"));
2692 /* This completes the cast from abi type back to the declared type
2693 in the case that we are reading from the machine. See the
2694 comment at the head of this block for more details. */
2695 if (readbuf
!= nullptr)
2697 struct value
*arg_val
= value_cast (arg_type
, abi_val
);
2698 memcpy (old_readbuf
, value_contents_raw (arg_val
),
2699 TYPE_LENGTH (arg_type
));
2703 switch (info
.argloc
[0].loc_type
)
2705 case riscv_arg_info::location::in_reg
:
2706 return RETURN_VALUE_REGISTER_CONVENTION
;
2707 case riscv_arg_info::location::by_ref
:
2708 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2709 case riscv_arg_info::location::on_stack
:
2711 error (_("invalid argument location"));
2715 /* Implement the frame_align gdbarch method. */
2718 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2720 return align_down (addr
, 16);
2723 /* Implement the unwind_pc gdbarch method. */
2726 riscv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2728 return frame_unwind_register_unsigned (next_frame
, RISCV_PC_REGNUM
);
2731 /* Implement the unwind_sp gdbarch method. */
2734 riscv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2736 return frame_unwind_register_unsigned (next_frame
, RISCV_SP_REGNUM
);
2739 /* Implement the dummy_id gdbarch method. */
2741 static struct frame_id
2742 riscv_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2744 return frame_id_build (get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
),
2745 get_frame_pc (this_frame
));
2748 /* Generate, or return the cached frame cache for the RiscV frame
2751 static struct riscv_unwind_cache
*
2752 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2754 CORE_ADDR pc
, start_addr
;
2755 struct riscv_unwind_cache
*cache
;
2756 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2759 if ((*this_cache
) != NULL
)
2760 return (struct riscv_unwind_cache
*) *this_cache
;
2762 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
2763 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
2764 (*this_cache
) = cache
;
2766 /* Scan the prologue, filling in the cache. */
2767 start_addr
= get_frame_func (this_frame
);
2768 pc
= get_frame_pc (this_frame
);
2769 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
2771 /* We can now calculate the frame base address. */
2773 = (get_frame_register_signed (this_frame
, cache
->frame_base_reg
)
2774 + cache
->frame_base_offset
);
2775 if (riscv_debug_unwinder
)
2776 fprintf_unfiltered (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
2777 core_addr_to_string (cache
->frame_base
),
2778 gdbarch_register_name (gdbarch
,
2779 cache
->frame_base_reg
),
2780 cache
->frame_base_offset
);
2782 /* The prologue scanner sets the address of registers stored to the stack
2783 as the offset of that register from the frame base. The prologue
2784 scanner doesn't know the actual frame base value, and so is unable to
2785 compute the exact address. We do now know the frame base value, so
2786 update the address of registers stored to the stack. */
2787 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
2788 for (regno
= 0; regno
< numregs
; ++regno
)
2790 if (trad_frame_addr_p (cache
->regs
, regno
))
2791 cache
->regs
[regno
].addr
+= cache
->frame_base
;
2794 /* The previous $pc can be found wherever the $ra value can be found.
2795 The previous $ra value is gone, this would have been stored be the
2796 previous frame if required. */
2797 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
2798 trad_frame_set_unknown (cache
->regs
, RISCV_RA_REGNUM
);
2800 /* Build the frame id. */
2801 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
2803 /* The previous $sp value is the frame base value. */
2804 trad_frame_set_value (cache
->regs
, gdbarch_sp_regnum (gdbarch
),
2810 /* Implement the this_id callback for RiscV frame unwinder. */
2813 riscv_frame_this_id (struct frame_info
*this_frame
,
2814 void **prologue_cache
,
2815 struct frame_id
*this_id
)
2817 struct riscv_unwind_cache
*cache
;
2821 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2822 *this_id
= cache
->this_id
;
2824 CATCH (ex
, RETURN_MASK_ERROR
)
2826 /* Ignore errors, this leaves the frame id as the predefined outer
2827 frame id which terminates the backtrace at this point. */
2832 /* Implement the prev_register callback for RiscV frame unwinder. */
2834 static struct value
*
2835 riscv_frame_prev_register (struct frame_info
*this_frame
,
2836 void **prologue_cache
,
2839 struct riscv_unwind_cache
*cache
;
2841 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2842 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
2845 /* Structure defining the RiscV normal frame unwind functions. Since we
2846 are the fallback unwinder (DWARF unwinder is used first), we use the
2847 default frame sniffer, which always accepts the frame. */
2849 static const struct frame_unwind riscv_frame_unwind
=
2851 /*.type =*/ NORMAL_FRAME
,
2852 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2853 /*.this_id =*/ riscv_frame_this_id
,
2854 /*.prev_register =*/ riscv_frame_prev_register
,
2855 /*.unwind_data =*/ NULL
,
2856 /*.sniffer =*/ default_frame_sniffer
,
2857 /*.dealloc_cache =*/ NULL
,
2858 /*.prev_arch =*/ NULL
,
2861 /* Extract a set of required target features out of INFO, specifically the
2862 bfd being executed is examined to see what target features it requires.
2863 IF there is no current bfd, or the bfd doesn't indicate any useful
2864 features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
2866 static struct riscv_gdbarch_features
2867 riscv_features_from_gdbarch_info (const struct gdbarch_info info
)
2869 struct riscv_gdbarch_features features
;
2871 /* Now try to improve on the defaults by looking at the binary we are
2872 going to execute. We assume the user knows what they are doing and
2873 that the target will match the binary. Remember, this code path is
2874 only used at all if the target hasn't given us a description, so this
2875 is really a last ditched effort to do something sane before giving
2877 if (info
.abfd
!= NULL
2878 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2880 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2881 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2883 if (eclass
== ELFCLASS32
)
2885 else if (eclass
== ELFCLASS64
)
2888 internal_error (__FILE__
, __LINE__
,
2889 _("unknown ELF header class %d"), eclass
);
2891 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2894 features
.hw_float_abi
= true;
2896 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2899 features
.hw_float_abi
= true;
2904 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2906 if (binfo
->bits_per_word
== 32)
2908 else if (binfo
->bits_per_word
== 64)
2911 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2912 binfo
->bits_per_word
);
2918 /* Find a suitable default target description. Use the contents of INFO,
2919 specifically the bfd object being executed, to guide the selection of a
2920 suitable default target description. */
2922 static const struct target_desc
*
2923 riscv_find_default_target_description (const struct gdbarch_info info
)
2925 /* Extract desired feature set from INFO. */
2926 struct riscv_gdbarch_features features
2927 = riscv_features_from_gdbarch_info (info
);
2929 /* If the XLEN field is still 0 then we got nothing useful from INFO. In
2930 this case we fall back to a minimal useful target, 8-byte x-registers,
2931 with no floating point. */
2932 if (features
.xlen
== 0)
2935 /* Now build a target description based on the feature set. */
2936 return riscv_create_target_description (features
);
2939 /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
2940 is updated with the register numbers for each register as listed in
2941 REG_SET. If any register marked as required in REG_SET is not found in
2942 FEATURE then this function returns false, otherwise, it returns true. */
2945 riscv_check_tdesc_feature (struct tdesc_arch_data
*tdesc_data
,
2946 const struct tdesc_feature
*feature
,
2947 const struct riscv_register_feature
*reg_set
)
2949 for (const auto ®
: reg_set
->registers
)
2953 for (const char *name
: reg
.names
)
2956 tdesc_numbered_register (feature
, tdesc_data
, reg
.regnum
, name
);
2962 if (!found
&& reg
.required_p
)
2969 /* Add all the expected register sets into GDBARCH. */
2972 riscv_add_reggroups (struct gdbarch
*gdbarch
)
2974 /* Add predefined register groups. */
2975 reggroup_add (gdbarch
, all_reggroup
);
2976 reggroup_add (gdbarch
, save_reggroup
);
2977 reggroup_add (gdbarch
, restore_reggroup
);
2978 reggroup_add (gdbarch
, system_reggroup
);
2979 reggroup_add (gdbarch
, vector_reggroup
);
2980 reggroup_add (gdbarch
, general_reggroup
);
2981 reggroup_add (gdbarch
, float_reggroup
);
2983 /* Add RISC-V specific register groups. */
2984 reggroup_add (gdbarch
, csr_reggroup
);
2987 /* Create register aliases for all the alternative names that exist for
2988 registers in REG_SET. */
2991 riscv_setup_register_aliases (struct gdbarch
*gdbarch
,
2992 const struct riscv_register_feature
*reg_set
)
2994 for (auto ®
: reg_set
->registers
)
2996 /* The first item in the names list is the preferred name for the
2997 register, this is what RISCV_REGISTER_NAME returns, and so we
2998 don't need to create an alias with that name here. */
2999 for (int i
= 1; i
< reg
.names
.size (); ++i
)
3000 user_reg_add (gdbarch
, reg
.names
[i
], value_of_riscv_user_reg
,
3005 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3008 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3010 if (reg
< RISCV_DWARF_REGNUM_X31
)
3011 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3013 else if (reg
< RISCV_DWARF_REGNUM_F31
)
3014 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3019 /* Initialize the current architecture based on INFO. If possible,
3020 re-use an architecture from ARCHES, which is a list of
3021 architectures already created during this debugging session.
3023 Called e.g. at program startup, when reading a core file, and when
3024 reading a binary file. */
3026 static struct gdbarch
*
3027 riscv_gdbarch_init (struct gdbarch_info info
,
3028 struct gdbarch_list
*arches
)
3030 struct gdbarch
*gdbarch
;
3031 struct gdbarch_tdep
*tdep
;
3032 struct riscv_gdbarch_features features
;
3033 const struct target_desc
*tdesc
= info
.target_desc
;
3035 /* Ensure we always have a target description. */
3036 if (!tdesc_has_registers (tdesc
))
3037 tdesc
= riscv_find_default_target_description (info
);
3040 if (riscv_debug_gdbarch
)
3041 fprintf_unfiltered (gdb_stdlog
, "Have got a target description\n");
3043 const struct tdesc_feature
*feature_cpu
3044 = tdesc_find_feature (tdesc
, riscv_xreg_feature
.name
);
3045 const struct tdesc_feature
*feature_fpu
3046 = tdesc_find_feature (tdesc
, riscv_freg_feature
.name
);
3047 const struct tdesc_feature
*feature_virtual
3048 = tdesc_find_feature (tdesc
, riscv_virtual_feature
.name
);
3049 const struct tdesc_feature
*feature_csr
3050 = tdesc_find_feature (tdesc
, riscv_csr_feature
.name
);
3052 if (feature_cpu
== NULL
)
3055 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3057 bool valid_p
= riscv_check_tdesc_feature (tdesc_data
,
3059 &riscv_xreg_feature
);
3062 /* Check that all of the core cpu registers have the same bitsize. */
3063 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
3065 for (auto &tdesc_reg
: feature_cpu
->registers
)
3066 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
3068 if (riscv_debug_gdbarch
)
3071 "From target-description, xlen = %d\n", xlen_bitsize
);
3073 features
.xlen
= (xlen_bitsize
/ 8);
3076 if (feature_fpu
!= NULL
)
3078 valid_p
&= riscv_check_tdesc_feature (tdesc_data
, feature_fpu
,
3079 &riscv_freg_feature
);
3081 int bitsize
= tdesc_register_bitsize (feature_fpu
, "ft0");
3082 features
.flen
= (bitsize
/ 8);
3084 if (riscv_debug_gdbarch
)
3087 "From target-description, flen = %d\n", bitsize
);
3093 if (riscv_debug_gdbarch
)
3096 "No FPU in target-description, assume soft-float ABI\n");
3099 if (feature_virtual
)
3100 riscv_check_tdesc_feature (tdesc_data
, feature_virtual
,
3101 &riscv_virtual_feature
);
3104 riscv_check_tdesc_feature (tdesc_data
, feature_csr
,
3105 &riscv_csr_feature
);
3109 if (riscv_debug_gdbarch
)
3110 fprintf_unfiltered (gdb_stdlog
, "Target description is not valid\n");
3111 tdesc_data_cleanup (tdesc_data
);
3115 /* Have a look at what the supplied (if any) bfd object requires of the
3116 target, then check that this matches with what the target is
3118 struct riscv_gdbarch_features info_features
3119 = riscv_features_from_gdbarch_info (info
);
3120 if (info_features
.xlen
!= 0 && info_features
.xlen
!= features
.xlen
)
3121 error (_("bfd requires xlen %d, but target has xlen %d"),
3122 info_features
.xlen
, features
.xlen
);
3123 if (info_features
.flen
!= 0 && info_features
.flen
!= features
.flen
)
3124 error (_("bfd requires flen %d, but target has flen %d"),
3125 info_features
.flen
, features
.flen
);
3127 /* If the xlen from INFO_FEATURES is 0 then this indicates either there
3128 is no bfd object, or nothing useful could be extracted from it, in
3129 this case we enable hardware float abi if the target has floating
3132 If the xlen from INFO_FEATURES is not 0, and the flen in
3133 INFO_FEATURES is also not 0, then this indicates that the supplied
3134 bfd does require hardware floating point abi. */
3135 if (info_features
.xlen
== 0 || info_features
.flen
!= 0)
3136 features
.hw_float_abi
= (features
.flen
> 0);
3138 /* Find a candidate among the list of pre-declared architectures. */
3139 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3141 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3143 /* Check that the feature set of the ARCHES matches the feature set
3144 we are looking for. If it doesn't then we can't reuse this
3146 struct gdbarch_tdep
*other_tdep
= gdbarch_tdep (arches
->gdbarch
);
3148 if (other_tdep
->features
!= features
)
3156 tdesc_data_cleanup (tdesc_data
);
3157 return arches
->gdbarch
;
3160 /* None found, so create a new architecture from the information provided. */
3161 tdep
= new (struct gdbarch_tdep
);
3162 gdbarch
= gdbarch_alloc (&info
, tdep
);
3163 tdep
->features
= features
;
3165 /* Target data types. */
3166 set_gdbarch_short_bit (gdbarch
, 16);
3167 set_gdbarch_int_bit (gdbarch
, 32);
3168 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3169 set_gdbarch_long_long_bit (gdbarch
, 64);
3170 set_gdbarch_float_bit (gdbarch
, 32);
3171 set_gdbarch_double_bit (gdbarch
, 64);
3172 set_gdbarch_long_double_bit (gdbarch
, 128);
3173 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3174 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3175 set_gdbarch_char_signed (gdbarch
, 0);
3177 /* Information about the target architecture. */
3178 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
3179 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3180 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3181 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3183 /* Functions to analyze frames. */
3184 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3185 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3186 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3188 /* Functions to access frame data. */
3189 set_gdbarch_unwind_pc (gdbarch
, riscv_unwind_pc
);
3190 set_gdbarch_unwind_sp (gdbarch
, riscv_unwind_sp
);
3192 /* Functions handling dummy frames. */
3193 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3194 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3195 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3196 set_gdbarch_dummy_id (gdbarch
, riscv_dummy_id
);
3198 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3200 dwarf2_append_unwinders (gdbarch
);
3201 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3203 /* Register architecture. */
3204 riscv_add_reggroups (gdbarch
);
3206 /* Internal <-> external register number maps. */
3207 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3209 /* We reserve all possible register numbers for the known registers.
3210 This means the target description mechanism will add any target
3211 specific registers after this number. This helps make debugging GDB
3212 just a little easier. */
3213 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3215 /* We don't have to provide the count of 0 here (its the default) but
3216 include this line to make it explicit that, right now, we don't have
3217 any pseudo registers on RISC-V. */
3218 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
3220 /* Some specific register numbers GDB likes to know about. */
3221 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3222 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3224 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3226 /* Finalise the target description registers. */
3227 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3229 /* Override the register type callback setup by the target description
3230 mechanism. This allows us to provide special type for floating point
3232 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3234 /* Override the register name callback setup by the target description
3235 mechanism. This allows us to force our preferred names for the
3236 registers, no matter what the target description called them. */
3237 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
3239 /* Override the register group callback setup by the target description
3240 mechanism. This allows us to force registers into the groups we
3241 want, ignoring what the target tells us. */
3242 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
3244 /* Create register aliases for alternative register names. */
3245 riscv_setup_register_aliases (gdbarch
, &riscv_xreg_feature
);
3246 if (riscv_has_fp_regs (gdbarch
))
3247 riscv_setup_register_aliases (gdbarch
, &riscv_freg_feature
);
3248 riscv_setup_register_aliases (gdbarch
, &riscv_csr_feature
);
3250 /* Hook in OS ABI-specific overrides, if they have been registered. */
3251 gdbarch_init_osabi (info
, gdbarch
);
3256 /* This decodes the current instruction and determines the address of the
3257 next instruction. */
3260 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
3262 struct gdbarch
*gdbarch
= regcache
->arch ();
3263 struct riscv_insn insn
;
3266 insn
.decode (gdbarch
, pc
);
3267 next_pc
= pc
+ insn
.length ();
3269 if (insn
.opcode () == riscv_insn::JAL
)
3270 next_pc
= pc
+ insn
.imm_signed ();
3271 else if (insn
.opcode () == riscv_insn::JALR
)
3274 regcache
->cooked_read (insn
.rs1 (), &source
);
3275 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
3277 else if (insn
.opcode () == riscv_insn::BEQ
)
3280 regcache
->cooked_read (insn
.rs1 (), &src1
);
3281 regcache
->cooked_read (insn
.rs2 (), &src2
);
3283 next_pc
= pc
+ insn
.imm_signed ();
3285 else if (insn
.opcode () == riscv_insn::BNE
)
3288 regcache
->cooked_read (insn
.rs1 (), &src1
);
3289 regcache
->cooked_read (insn
.rs2 (), &src2
);
3291 next_pc
= pc
+ insn
.imm_signed ();
3293 else if (insn
.opcode () == riscv_insn::BLT
)
3296 regcache
->cooked_read (insn
.rs1 (), &src1
);
3297 regcache
->cooked_read (insn
.rs2 (), &src2
);
3299 next_pc
= pc
+ insn
.imm_signed ();
3301 else if (insn
.opcode () == riscv_insn::BGE
)
3304 regcache
->cooked_read (insn
.rs1 (), &src1
);
3305 regcache
->cooked_read (insn
.rs2 (), &src2
);
3307 next_pc
= pc
+ insn
.imm_signed ();
3309 else if (insn
.opcode () == riscv_insn::BLTU
)
3311 ULONGEST src1
, src2
;
3312 regcache
->cooked_read (insn
.rs1 (), &src1
);
3313 regcache
->cooked_read (insn
.rs2 (), &src2
);
3315 next_pc
= pc
+ insn
.imm_signed ();
3317 else if (insn
.opcode () == riscv_insn::BGEU
)
3319 ULONGEST src1
, src2
;
3320 regcache
->cooked_read (insn
.rs1 (), &src1
);
3321 regcache
->cooked_read (insn
.rs2 (), &src2
);
3323 next_pc
= pc
+ insn
.imm_signed ();
3329 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3330 for the end of the sequence and put the breakpoint there. */
3333 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
3336 struct gdbarch
*gdbarch
= regcache
->arch ();
3337 struct riscv_insn insn
;
3338 CORE_ADDR cur_step_pc
= pc
;
3339 CORE_ADDR last_addr
= 0;
3341 /* First instruction has to be a load reserved. */
3342 insn
.decode (gdbarch
, cur_step_pc
);
3343 if (insn
.opcode () != riscv_insn::LR
)
3345 cur_step_pc
= cur_step_pc
+ insn
.length ();
3347 /* Next instruction should be branch to exit. */
3348 insn
.decode (gdbarch
, cur_step_pc
);
3349 if (insn
.opcode () != riscv_insn::BNE
)
3351 last_addr
= cur_step_pc
+ insn
.imm_signed ();
3352 cur_step_pc
= cur_step_pc
+ insn
.length ();
3354 /* Next instruction should be store conditional. */
3355 insn
.decode (gdbarch
, cur_step_pc
);
3356 if (insn
.opcode () != riscv_insn::SC
)
3358 cur_step_pc
= cur_step_pc
+ insn
.length ();
3360 /* Next instruction should be branch to start. */
3361 insn
.decode (gdbarch
, cur_step_pc
);
3362 if (insn
.opcode () != riscv_insn::BNE
)
3364 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
3366 cur_step_pc
= cur_step_pc
+ insn
.length ();
3368 /* We should now be at the end of the sequence. */
3369 if (cur_step_pc
!= last_addr
)
3372 *next_pc
= cur_step_pc
;
3376 /* This is called just before we want to resume the inferior, if we want to
3377 single-step it but there is no hardware or kernel single-step support. We
3378 find the target of the coming instruction and breakpoint it. */
3380 std::vector
<CORE_ADDR
>
3381 riscv_software_single_step (struct regcache
*regcache
)
3383 CORE_ADDR pc
, next_pc
;
3385 pc
= regcache_read_pc (regcache
);
3387 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
3390 next_pc
= riscv_next_pc (regcache
, pc
);
3395 /* Create RISC-V specific reggroups. */
3398 riscv_init_reggroups ()
3400 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
3404 _initialize_riscv_tdep (void)
3406 riscv_create_csr_aliases ();
3407 riscv_init_reggroups ();
3409 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
3411 /* Add root prefix command for all "set debug riscv" and "show debug
3413 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
3414 _("RISC-V specific debug commands."),
3415 &setdebugriscvcmdlist
, "set debug riscv ", 0,
3418 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
3419 _("RISC-V specific debug commands."),
3420 &showdebugriscvcmdlist
, "show debug riscv ", 0,
3423 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
3424 &riscv_debug_breakpoints
, _("\
3425 Set riscv breakpoint debugging."), _("\
3426 Show riscv breakpoint debugging."), _("\
3427 When non-zero, print debugging information for the riscv specific parts\n\
3428 of the breakpoint mechanism."),
3430 show_riscv_debug_variable
,
3431 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3433 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
3434 &riscv_debug_infcall
, _("\
3435 Set riscv inferior call debugging."), _("\
3436 Show riscv inferior call debugging."), _("\
3437 When non-zero, print debugging information for the riscv specific parts\n\
3438 of the inferior call mechanism."),
3440 show_riscv_debug_variable
,
3441 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3443 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
3444 &riscv_debug_unwinder
, _("\
3445 Set riscv stack unwinding debugging."), _("\
3446 Show riscv stack unwinding debugging."), _("\
3447 When non-zero, print debugging information for the riscv specific parts\n\
3448 of the stack unwinding mechanism."),
3450 show_riscv_debug_variable
,
3451 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3453 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
3454 &riscv_debug_gdbarch
, _("\
3455 Set riscv gdbarch initialisation debugging."), _("\
3456 Show riscv gdbarch initialisation debugging."), _("\
3457 When non-zero, print debugging information for the riscv gdbarch\n\
3458 initialisation process."),
3460 show_riscv_debug_variable
,
3461 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3463 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3464 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
3465 _("RISC-V specific commands."),
3466 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
3468 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
3469 _("RISC-V specific commands."),
3470 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
3473 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
3474 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
3475 &use_compressed_breakpoints
,
3477 Set debugger's use of compressed breakpoints."), _(" \
3478 Show debugger's use of compressed breakpoints."), _("\
3479 Debugging compressed code requires compressed breakpoints to be used. If\n\
3480 left to 'auto' then gdb will use them if the existing instruction is a\n\
3481 compressed instruction. If that doesn't give the correct behavior, then\n\
3482 this option can be used."),
3484 show_use_compressed_breakpoints
,