1 /* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
3 Copyright (C) 2011-2017 Free Software Foundation, Inc.
5 Contributed by Red Hat, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
24 #include "prologue-value.h"
27 #include "opcode/rl78.h"
31 #include "frame-unwind.h"
32 #include "frame-base.h"
35 #include "dwarf2-frame.h"
36 #include "reggroups.h"
50 RL78_REGS_PER_BANK
= 8
53 /* Register Numbers. */
57 /* All general purpose registers are 8 bits wide. */
58 RL78_RAW_BANK0_R0_REGNUM
= 0,
59 RL78_RAW_BANK0_R1_REGNUM
,
60 RL78_RAW_BANK0_R2_REGNUM
,
61 RL78_RAW_BANK0_R3_REGNUM
,
62 RL78_RAW_BANK0_R4_REGNUM
,
63 RL78_RAW_BANK0_R5_REGNUM
,
64 RL78_RAW_BANK0_R6_REGNUM
,
65 RL78_RAW_BANK0_R7_REGNUM
,
67 RL78_RAW_BANK1_R0_REGNUM
,
68 RL78_RAW_BANK1_R1_REGNUM
,
69 RL78_RAW_BANK1_R2_REGNUM
,
70 RL78_RAW_BANK1_R3_REGNUM
,
71 RL78_RAW_BANK1_R4_REGNUM
,
72 RL78_RAW_BANK1_R5_REGNUM
,
73 RL78_RAW_BANK1_R6_REGNUM
,
74 RL78_RAW_BANK1_R7_REGNUM
,
76 RL78_RAW_BANK2_R0_REGNUM
,
77 RL78_RAW_BANK2_R1_REGNUM
,
78 RL78_RAW_BANK2_R2_REGNUM
,
79 RL78_RAW_BANK2_R3_REGNUM
,
80 RL78_RAW_BANK2_R4_REGNUM
,
81 RL78_RAW_BANK2_R5_REGNUM
,
82 RL78_RAW_BANK2_R6_REGNUM
,
83 RL78_RAW_BANK2_R7_REGNUM
,
85 RL78_RAW_BANK3_R0_REGNUM
,
86 RL78_RAW_BANK3_R1_REGNUM
,
87 RL78_RAW_BANK3_R2_REGNUM
,
88 RL78_RAW_BANK3_R3_REGNUM
,
89 RL78_RAW_BANK3_R4_REGNUM
,
90 RL78_RAW_BANK3_R5_REGNUM
,
91 RL78_RAW_BANK3_R6_REGNUM
,
92 RL78_RAW_BANK3_R7_REGNUM
,
94 RL78_PSW_REGNUM
, /* 8 bits */
95 RL78_ES_REGNUM
, /* 8 bits */
96 RL78_CS_REGNUM
, /* 8 bits */
97 RL78_RAW_PC_REGNUM
, /* 20 bits; we'll use 32 bits for it. */
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM
, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM
, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM
, /* 8 bits */
103 RL78_MEM_REGNUM
, /* 8 bits ?? */
107 /* Pseudo registers. */
108 RL78_PC_REGNUM
= RL78_NUM_REGS
,
125 RL78_BANK0_R0_REGNUM
,
126 RL78_BANK0_R1_REGNUM
,
127 RL78_BANK0_R2_REGNUM
,
128 RL78_BANK0_R3_REGNUM
,
129 RL78_BANK0_R4_REGNUM
,
130 RL78_BANK0_R5_REGNUM
,
131 RL78_BANK0_R6_REGNUM
,
132 RL78_BANK0_R7_REGNUM
,
134 RL78_BANK1_R0_REGNUM
,
135 RL78_BANK1_R1_REGNUM
,
136 RL78_BANK1_R2_REGNUM
,
137 RL78_BANK1_R3_REGNUM
,
138 RL78_BANK1_R4_REGNUM
,
139 RL78_BANK1_R5_REGNUM
,
140 RL78_BANK1_R6_REGNUM
,
141 RL78_BANK1_R7_REGNUM
,
143 RL78_BANK2_R0_REGNUM
,
144 RL78_BANK2_R1_REGNUM
,
145 RL78_BANK2_R2_REGNUM
,
146 RL78_BANK2_R3_REGNUM
,
147 RL78_BANK2_R4_REGNUM
,
148 RL78_BANK2_R5_REGNUM
,
149 RL78_BANK2_R6_REGNUM
,
150 RL78_BANK2_R7_REGNUM
,
152 RL78_BANK3_R0_REGNUM
,
153 RL78_BANK3_R1_REGNUM
,
154 RL78_BANK3_R2_REGNUM
,
155 RL78_BANK3_R3_REGNUM
,
156 RL78_BANK3_R4_REGNUM
,
157 RL78_BANK3_R5_REGNUM
,
158 RL78_BANK3_R6_REGNUM
,
159 RL78_BANK3_R7_REGNUM
,
161 RL78_BANK0_RP0_REGNUM
,
162 RL78_BANK0_RP1_REGNUM
,
163 RL78_BANK0_RP2_REGNUM
,
164 RL78_BANK0_RP3_REGNUM
,
166 RL78_BANK1_RP0_REGNUM
,
167 RL78_BANK1_RP1_REGNUM
,
168 RL78_BANK1_RP2_REGNUM
,
169 RL78_BANK1_RP3_REGNUM
,
171 RL78_BANK2_RP0_REGNUM
,
172 RL78_BANK2_RP1_REGNUM
,
173 RL78_BANK2_RP2_REGNUM
,
174 RL78_BANK2_RP3_REGNUM
,
176 RL78_BANK3_RP0_REGNUM
,
177 RL78_BANK3_RP1_REGNUM
,
178 RL78_BANK3_RP2_REGNUM
,
179 RL78_BANK3_RP3_REGNUM
,
181 /* These are the same as the above 16 registers, but have
182 a pointer type for use as base registers in expression
183 evaluation. These are not user visible registers. */
184 RL78_BANK0_RP0_PTR_REGNUM
,
185 RL78_BANK0_RP1_PTR_REGNUM
,
186 RL78_BANK0_RP2_PTR_REGNUM
,
187 RL78_BANK0_RP3_PTR_REGNUM
,
189 RL78_BANK1_RP0_PTR_REGNUM
,
190 RL78_BANK1_RP1_PTR_REGNUM
,
191 RL78_BANK1_RP2_PTR_REGNUM
,
192 RL78_BANK1_RP3_PTR_REGNUM
,
194 RL78_BANK2_RP0_PTR_REGNUM
,
195 RL78_BANK2_RP1_PTR_REGNUM
,
196 RL78_BANK2_RP2_PTR_REGNUM
,
197 RL78_BANK2_RP3_PTR_REGNUM
,
199 RL78_BANK3_RP0_PTR_REGNUM
,
200 RL78_BANK3_RP1_PTR_REGNUM
,
201 RL78_BANK3_RP2_PTR_REGNUM
,
202 RL78_BANK3_RP3_PTR_REGNUM
,
205 RL78_NUM_PSEUDO_REGS
= RL78_NUM_TOTAL_REGS
- RL78_NUM_REGS
208 #define RL78_SP_ADDR 0xffff8
210 /* Architecture specific data. */
214 /* The ELF header flags specify the multilib used. */
217 struct type
*rl78_void
,
229 /* This structure holds the results of a prologue analysis. */
233 /* The offset from the frame base to the stack pointer --- always
236 Calling this a "size" is a bit misleading, but given that the
237 stack grows downwards, using offsets for everything keeps one
238 from going completely sign-crazy: you never change anything's
239 sign for an ADD instruction; always change the second operand's
240 sign for a SUB instruction; and everything takes care of
244 /* Non-zero if this function has initialized the frame pointer from
245 the stack pointer, zero otherwise. */
248 /* If has_frame_ptr is non-zero, this is the offset from the frame
249 base to where the frame pointer points. This is always zero or
251 int frame_ptr_offset
;
253 /* The address of the first instruction at which the frame has been
254 set up and the arguments are where the debug info says they are
255 --- as best as we can tell. */
256 CORE_ADDR prologue_end
;
258 /* reg_offset[R] is the offset from the CFA at which register R is
259 saved, or 1 if register R has not been saved. (Real values are
260 always zero or negative.) */
261 int reg_offset
[RL78_NUM_TOTAL_REGS
];
264 /* Construct type for PSW register. */
267 rl78_psw_type (struct gdbarch
*gdbarch
)
269 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
271 if (tdep
->rl78_psw_type
== NULL
)
273 tdep
->rl78_psw_type
= arch_flags_type (gdbarch
,
274 "builtin_type_rl78_psw", 8);
275 append_flags_type_flag (tdep
->rl78_psw_type
, 0, "CY");
276 append_flags_type_flag (tdep
->rl78_psw_type
, 1, "ISP0");
277 append_flags_type_flag (tdep
->rl78_psw_type
, 2, "ISP1");
278 append_flags_type_flag (tdep
->rl78_psw_type
, 3, "RBS0");
279 append_flags_type_flag (tdep
->rl78_psw_type
, 4, "AC");
280 append_flags_type_flag (tdep
->rl78_psw_type
, 5, "RBS1");
281 append_flags_type_flag (tdep
->rl78_psw_type
, 6, "Z");
282 append_flags_type_flag (tdep
->rl78_psw_type
, 7, "IE");
285 return tdep
->rl78_psw_type
;
288 /* Implement the "register_type" gdbarch method. */
291 rl78_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
295 if (reg_nr
== RL78_PC_REGNUM
)
296 return tdep
->rl78_code_pointer
;
297 else if (reg_nr
== RL78_RAW_PC_REGNUM
)
298 return tdep
->rl78_uint32
;
299 else if (reg_nr
== RL78_PSW_REGNUM
)
300 return rl78_psw_type (gdbarch
);
301 else if (reg_nr
<= RL78_MEM_REGNUM
302 || (RL78_X_REGNUM
<= reg_nr
&& reg_nr
<= RL78_H_REGNUM
)
303 || (RL78_BANK0_R0_REGNUM
<= reg_nr
304 && reg_nr
<= RL78_BANK3_R7_REGNUM
))
305 return tdep
->rl78_int8
;
306 else if (reg_nr
== RL78_SP_REGNUM
307 || (RL78_BANK0_RP0_PTR_REGNUM
<= reg_nr
308 && reg_nr
<= RL78_BANK3_RP3_PTR_REGNUM
))
309 return tdep
->rl78_data_pointer
;
311 return tdep
->rl78_int16
;
314 /* Implement the "register_name" gdbarch method. */
317 rl78_register_name (struct gdbarch
*gdbarch
, int regnr
)
319 static const char *const reg_names
[] =
440 /* The 16 register slots would be named
441 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
442 want these to be user visible registers. */
443 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
446 return reg_names
[regnr
];
449 /* Implement the "register_name" gdbarch method for the g10 variant. */
452 rl78_g10_register_name (struct gdbarch
*gdbarch
, int regnr
)
454 static const char *const reg_names
[] =
575 /* The 16 register slots would be named
576 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
577 want these to be user visible registers. */
578 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
581 return reg_names
[regnr
];
584 /* Implement the "register_reggroup_p" gdbarch method. */
587 rl78_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
588 struct reggroup
*group
)
590 if (group
== all_reggroup
)
593 /* All other registers are saved and restored. */
594 if (group
== save_reggroup
|| group
== restore_reggroup
)
596 if ((regnum
< RL78_NUM_REGS
597 && regnum
!= RL78_SPL_REGNUM
598 && regnum
!= RL78_SPH_REGNUM
599 && regnum
!= RL78_RAW_PC_REGNUM
)
600 || regnum
== RL78_SP_REGNUM
601 || regnum
== RL78_PC_REGNUM
)
607 if ((RL78_BANK0_R0_REGNUM
<= regnum
&& regnum
<= RL78_BANK3_R7_REGNUM
)
608 || regnum
== RL78_ES_REGNUM
609 || regnum
== RL78_CS_REGNUM
610 || regnum
== RL78_SPL_REGNUM
611 || regnum
== RL78_SPH_REGNUM
612 || regnum
== RL78_PMC_REGNUM
613 || regnum
== RL78_MEM_REGNUM
614 || regnum
== RL78_RAW_PC_REGNUM
615 || (RL78_BANK0_RP0_REGNUM
<= regnum
&& regnum
<= RL78_BANK3_RP3_REGNUM
))
616 return group
== system_reggroup
;
618 return group
== general_reggroup
;
621 /* Strip bits to form an instruction address. (When fetching a
622 32-bit address from the stack, the high eight bits are garbage.
623 This function strips off those unused bits.) */
626 rl78_make_instruction_address (CORE_ADDR addr
)
628 return addr
& 0xffffff;
631 /* Set / clear bits necessary to make a data address. */
634 rl78_make_data_address (CORE_ADDR addr
)
636 return (addr
& 0xffff) | 0xf0000;
639 /* Implement the "pseudo_register_read" gdbarch method. */
641 static enum register_status
642 rl78_pseudo_register_read (struct gdbarch
*gdbarch
,
643 struct regcache
*regcache
,
644 int reg
, gdb_byte
*buffer
)
646 enum register_status status
;
648 if (RL78_BANK0_R0_REGNUM
<= reg
&& reg
<= RL78_BANK3_R7_REGNUM
)
650 int raw_regnum
= RL78_RAW_BANK0_R0_REGNUM
651 + (reg
- RL78_BANK0_R0_REGNUM
);
653 status
= regcache_raw_read (regcache
, raw_regnum
, buffer
);
655 else if (RL78_BANK0_RP0_REGNUM
<= reg
&& reg
<= RL78_BANK3_RP3_REGNUM
)
657 int raw_regnum
= 2 * (reg
- RL78_BANK0_RP0_REGNUM
)
658 + RL78_RAW_BANK0_R0_REGNUM
;
660 status
= regcache_raw_read (regcache
, raw_regnum
, buffer
);
661 if (status
== REG_VALID
)
662 status
= regcache_raw_read (regcache
, raw_regnum
+ 1, buffer
+ 1);
664 else if (RL78_BANK0_RP0_PTR_REGNUM
<= reg
&& reg
<= RL78_BANK3_RP3_PTR_REGNUM
)
666 int raw_regnum
= 2 * (reg
- RL78_BANK0_RP0_PTR_REGNUM
)
667 + RL78_RAW_BANK0_R0_REGNUM
;
669 status
= regcache_raw_read (regcache
, raw_regnum
, buffer
);
670 if (status
== REG_VALID
)
671 status
= regcache_raw_read (regcache
, raw_regnum
+ 1, buffer
+ 1);
673 else if (reg
== RL78_SP_REGNUM
)
675 status
= regcache_raw_read (regcache
, RL78_SPL_REGNUM
, buffer
);
676 if (status
== REG_VALID
)
677 status
= regcache_raw_read (regcache
, RL78_SPH_REGNUM
, buffer
+ 1);
679 else if (reg
== RL78_PC_REGNUM
)
683 status
= regcache_raw_read (regcache
, RL78_RAW_PC_REGNUM
, rawbuf
);
684 memcpy (buffer
, rawbuf
, 3);
686 else if (RL78_X_REGNUM
<= reg
&& reg
<= RL78_H_REGNUM
)
690 status
= regcache_raw_read_unsigned (regcache
, RL78_PSW_REGNUM
, &psw
);
691 if (status
== REG_VALID
)
693 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
694 int bank
= ((psw
>> 3) & 1) | ((psw
>> 4) & 1);
695 int raw_regnum
= RL78_RAW_BANK0_R0_REGNUM
+ bank
* RL78_REGS_PER_BANK
696 + (reg
- RL78_X_REGNUM
);
697 status
= regcache_raw_read (regcache
, raw_regnum
, buffer
);
700 else if (RL78_AX_REGNUM
<= reg
&& reg
<= RL78_HL_REGNUM
)
704 status
= regcache_raw_read_unsigned (regcache
, RL78_PSW_REGNUM
, &psw
);
705 if (status
== REG_VALID
)
707 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
708 int bank
= ((psw
>> 3) & 1) | ((psw
>> 4) & 1);
709 int raw_regnum
= RL78_RAW_BANK0_R0_REGNUM
+ bank
* RL78_REGS_PER_BANK
710 + 2 * (reg
- RL78_AX_REGNUM
);
711 status
= regcache_raw_read (regcache
, raw_regnum
, buffer
);
712 if (status
== REG_VALID
)
713 status
= regcache_raw_read (regcache
, raw_regnum
+ 1,
718 gdb_assert_not_reached ("invalid pseudo register number");
722 /* Implement the "pseudo_register_write" gdbarch method. */
725 rl78_pseudo_register_write (struct gdbarch
*gdbarch
,
726 struct regcache
*regcache
,
727 int reg
, const gdb_byte
*buffer
)
729 if (RL78_BANK0_R0_REGNUM
<= reg
&& reg
<= RL78_BANK3_R7_REGNUM
)
731 int raw_regnum
= RL78_RAW_BANK0_R0_REGNUM
732 + (reg
- RL78_BANK0_R0_REGNUM
);
734 regcache_raw_write (regcache
, raw_regnum
, buffer
);
736 else if (RL78_BANK0_RP0_REGNUM
<= reg
&& reg
<= RL78_BANK3_RP3_REGNUM
)
738 int raw_regnum
= 2 * (reg
- RL78_BANK0_RP0_REGNUM
)
739 + RL78_RAW_BANK0_R0_REGNUM
;
741 regcache_raw_write (regcache
, raw_regnum
, buffer
);
742 regcache_raw_write (regcache
, raw_regnum
+ 1, buffer
+ 1);
744 else if (RL78_BANK0_RP0_PTR_REGNUM
<= reg
&& reg
<= RL78_BANK3_RP3_PTR_REGNUM
)
746 int raw_regnum
= 2 * (reg
- RL78_BANK0_RP0_PTR_REGNUM
)
747 + RL78_RAW_BANK0_R0_REGNUM
;
749 regcache_raw_write (regcache
, raw_regnum
, buffer
);
750 regcache_raw_write (regcache
, raw_regnum
+ 1, buffer
+ 1);
752 else if (reg
== RL78_SP_REGNUM
)
754 regcache_raw_write (regcache
, RL78_SPL_REGNUM
, buffer
);
755 regcache_raw_write (regcache
, RL78_SPH_REGNUM
, buffer
+ 1);
757 else if (reg
== RL78_PC_REGNUM
)
761 memcpy (rawbuf
, buffer
, 3);
763 regcache_raw_write (regcache
, RL78_RAW_PC_REGNUM
, rawbuf
);
765 else if (RL78_X_REGNUM
<= reg
&& reg
<= RL78_H_REGNUM
)
771 regcache_raw_read_unsigned (regcache
, RL78_PSW_REGNUM
, &psw
);
772 bank
= ((psw
>> 3) & 1) | ((psw
>> 4) & 1);
773 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
774 raw_regnum
= RL78_RAW_BANK0_R0_REGNUM
+ bank
* RL78_REGS_PER_BANK
775 + (reg
- RL78_X_REGNUM
);
776 regcache_raw_write (regcache
, raw_regnum
, buffer
);
778 else if (RL78_AX_REGNUM
<= reg
&& reg
<= RL78_HL_REGNUM
)
781 int bank
, raw_regnum
;
783 regcache_raw_read_unsigned (regcache
, RL78_PSW_REGNUM
, &psw
);
784 bank
= ((psw
>> 3) & 1) | ((psw
>> 4) & 1);
785 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
786 raw_regnum
= RL78_RAW_BANK0_R0_REGNUM
+ bank
* RL78_REGS_PER_BANK
787 + 2 * (reg
- RL78_AX_REGNUM
);
788 regcache_raw_write (regcache
, raw_regnum
, buffer
);
789 regcache_raw_write (regcache
, raw_regnum
+ 1, buffer
+ 1);
792 gdb_assert_not_reached ("invalid pseudo register number");
795 /* The documented BRK instruction is actually a two byte sequence,
796 {0x61, 0xcc}, but instructions may be as short as one byte.
797 Correspondence with Renesas revealed that the one byte sequence
798 0xff is used when a one byte breakpoint instruction is required. */
799 constexpr gdb_byte rl78_break_insn
[] = { 0xff };
801 typedef BP_MANIPULATION (rl78_break_insn
) rl78_breakpoint
;
803 /* Define a "handle" struct for fetching the next opcode. */
805 struct rl78_get_opcode_byte_handle
811 opc_reg_to_gdb_regnum (int opcreg
)
816 return RL78_X_REGNUM
;
818 return RL78_A_REGNUM
;
820 return RL78_C_REGNUM
;
822 return RL78_B_REGNUM
;
824 return RL78_E_REGNUM
;
826 return RL78_D_REGNUM
;
828 return RL78_L_REGNUM
;
830 return RL78_H_REGNUM
;
832 return RL78_AX_REGNUM
;
834 return RL78_BC_REGNUM
;
836 return RL78_DE_REGNUM
;
838 return RL78_HL_REGNUM
;
840 return RL78_SP_REGNUM
;
842 return RL78_PSW_REGNUM
;
844 return RL78_CS_REGNUM
;
846 return RL78_ES_REGNUM
;
848 return RL78_PMC_REGNUM
;
850 return RL78_MEM_REGNUM
;
852 internal_error (__FILE__
, __LINE__
,
853 _("Undefined mapping for opc reg %d"),
861 /* Fetch a byte on behalf of the opcode decoder. HANDLE contains
862 the memory address of the next byte to fetch. If successful,
863 the address in the handle is updated and the byte fetched is
864 returned as the value of the function. If not successful, -1
868 rl78_get_opcode_byte (void *handle
)
870 struct rl78_get_opcode_byte_handle
*opcdata
871 = (struct rl78_get_opcode_byte_handle
*) handle
;
875 status
= target_read_memory (opcdata
->pc
, &byte
, 1);
885 /* Function for finding saved registers in a 'struct pv_area'; this
886 function is passed to pv_area::scan.
888 If VALUE is a saved register, ADDR says it was saved at a constant
889 offset from the frame base, and SIZE indicates that the whole
890 register was saved, record its offset. */
893 check_for_saved (void *result_untyped
, pv_t addr
, CORE_ADDR size
,
896 struct rl78_prologue
*result
= (struct rl78_prologue
*) result_untyped
;
898 if (value
.kind
== pvk_register
900 && pv_is_register (addr
, RL78_SP_REGNUM
)
901 && size
== register_size (target_gdbarch (), value
.reg
))
902 result
->reg_offset
[value
.reg
] = addr
.k
;
905 /* Analyze a prologue starting at START_PC, going no further than
906 LIMIT_PC. Fill in RESULT as appropriate. */
909 rl78_analyze_prologue (CORE_ADDR start_pc
,
910 CORE_ADDR limit_pc
, struct rl78_prologue
*result
)
912 CORE_ADDR pc
, next_pc
;
914 pv_t reg
[RL78_NUM_TOTAL_REGS
];
915 CORE_ADDR after_last_frame_setup_insn
= start_pc
;
918 memset (result
, 0, sizeof (*result
));
920 for (rn
= 0; rn
< RL78_NUM_TOTAL_REGS
; rn
++)
922 reg
[rn
] = pv_register (rn
, 0);
923 result
->reg_offset
[rn
] = 1;
926 pv_area
stack (RL78_SP_REGNUM
, gdbarch_addr_bit (target_gdbarch ()));
928 /* The call instruction has saved the return address on the stack. */
929 reg
[RL78_SP_REGNUM
] = pv_add_constant (reg
[RL78_SP_REGNUM
], -4);
930 stack
.store (reg
[RL78_SP_REGNUM
], 4, reg
[RL78_PC_REGNUM
]);
933 while (pc
< limit_pc
)
936 struct rl78_get_opcode_byte_handle opcode_handle
;
937 RL78_Opcode_Decoded opc
;
939 opcode_handle
.pc
= pc
;
940 bytes_read
= rl78_decode_opcode (pc
, &opc
, rl78_get_opcode_byte
,
941 &opcode_handle
, RL78_ISA_DEFAULT
);
942 next_pc
= pc
+ bytes_read
;
944 if (opc
.id
== RLO_sel
)
946 bank
= opc
.op
[1].addend
;
948 else if (opc
.id
== RLO_mov
949 && opc
.op
[0].type
== RL78_Operand_PreDec
950 && opc
.op
[0].reg
== RL78_Reg_SP
951 && opc
.op
[1].type
== RL78_Operand_Register
)
953 int rsrc
= (bank
* RL78_REGS_PER_BANK
)
954 + 2 * (opc
.op
[1].reg
- RL78_Reg_AX
);
956 reg
[RL78_SP_REGNUM
] = pv_add_constant (reg
[RL78_SP_REGNUM
], -1);
957 stack
.store (reg
[RL78_SP_REGNUM
], 1, reg
[rsrc
]);
958 reg
[RL78_SP_REGNUM
] = pv_add_constant (reg
[RL78_SP_REGNUM
], -1);
959 stack
.store (reg
[RL78_SP_REGNUM
], 1, reg
[rsrc
+ 1]);
960 after_last_frame_setup_insn
= next_pc
;
962 else if (opc
.id
== RLO_sub
963 && opc
.op
[0].type
== RL78_Operand_Register
964 && opc
.op
[0].reg
== RL78_Reg_SP
965 && opc
.op
[1].type
== RL78_Operand_Immediate
)
967 int addend
= opc
.op
[1].addend
;
969 reg
[RL78_SP_REGNUM
] = pv_add_constant (reg
[RL78_SP_REGNUM
],
971 after_last_frame_setup_insn
= next_pc
;
973 else if (opc
.id
== RLO_mov
974 && opc
.size
== RL78_Word
975 && opc
.op
[0].type
== RL78_Operand_Register
976 && opc
.op
[1].type
== RL78_Operand_Indirect
977 && opc
.op
[1].addend
== RL78_SP_ADDR
)
979 reg
[opc_reg_to_gdb_regnum (opc
.op
[0].reg
)]
980 = reg
[RL78_SP_REGNUM
];
982 else if (opc
.id
== RLO_sub
983 && opc
.size
== RL78_Word
984 && opc
.op
[0].type
== RL78_Operand_Register
985 && opc
.op
[1].type
== RL78_Operand_Immediate
)
987 int addend
= opc
.op
[1].addend
;
988 int regnum
= opc_reg_to_gdb_regnum (opc
.op
[0].reg
);
990 reg
[regnum
] = pv_add_constant (reg
[regnum
], -addend
);
992 else if (opc
.id
== RLO_mov
993 && opc
.size
== RL78_Word
994 && opc
.op
[0].type
== RL78_Operand_Indirect
995 && opc
.op
[0].addend
== RL78_SP_ADDR
996 && opc
.op
[1].type
== RL78_Operand_Register
)
999 = reg
[opc_reg_to_gdb_regnum (opc
.op
[1].reg
)];
1000 after_last_frame_setup_insn
= next_pc
;
1004 /* Terminate the prologue scan. */
1011 /* Is the frame size (offset, really) a known constant? */
1012 if (pv_is_register (reg
[RL78_SP_REGNUM
], RL78_SP_REGNUM
))
1013 result
->frame_size
= reg
[RL78_SP_REGNUM
].k
;
1015 /* Record where all the registers were saved. */
1016 stack
.scan (check_for_saved
, (void *) result
);
1018 result
->prologue_end
= after_last_frame_setup_insn
;
1021 /* Implement the "addr_bits_remove" gdbarch method. */
1024 rl78_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1026 return addr
& 0xffffff;
1029 /* Implement the "address_to_pointer" gdbarch method. */
1032 rl78_address_to_pointer (struct gdbarch
*gdbarch
,
1033 struct type
*type
, gdb_byte
*buf
, CORE_ADDR addr
)
1035 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1037 store_unsigned_integer (buf
, TYPE_LENGTH (type
), byte_order
,
1041 /* Implement the "pointer_to_address" gdbarch method. */
1044 rl78_pointer_to_address (struct gdbarch
*gdbarch
,
1045 struct type
*type
, const gdb_byte
*buf
)
1047 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1049 = extract_unsigned_integer (buf
, TYPE_LENGTH (type
), byte_order
);
1051 /* Is it a code address? */
1052 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
1053 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
1054 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
))
1055 || TYPE_LENGTH (type
) == 4)
1056 return rl78_make_instruction_address (addr
);
1058 return rl78_make_data_address (addr
);
1061 /* Implement the "skip_prologue" gdbarch method. */
1064 rl78_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1067 CORE_ADDR func_addr
, func_end
;
1068 struct rl78_prologue p
;
1070 /* Try to find the extent of the function that contains PC. */
1071 if (!find_pc_partial_function (pc
, &name
, &func_addr
, &func_end
))
1074 rl78_analyze_prologue (pc
, func_end
, &p
);
1075 return p
.prologue_end
;
1078 /* Implement the "unwind_pc" gdbarch method. */
1081 rl78_unwind_pc (struct gdbarch
*arch
, struct frame_info
*next_frame
)
1083 return rl78_addr_bits_remove
1084 (arch
, frame_unwind_register_unsigned (next_frame
,
1088 /* Implement the "unwind_sp" gdbarch method. */
1091 rl78_unwind_sp (struct gdbarch
*arch
, struct frame_info
*next_frame
)
1093 return frame_unwind_register_unsigned (next_frame
, RL78_SP_REGNUM
);
1096 /* Given a frame described by THIS_FRAME, decode the prologue of its
1097 associated function if there is not cache entry as specified by
1098 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
1099 return that struct as the value of this function. */
1101 static struct rl78_prologue
*
1102 rl78_analyze_frame_prologue (struct frame_info
*this_frame
,
1103 void **this_prologue_cache
)
1105 if (!*this_prologue_cache
)
1107 CORE_ADDR func_start
, stop_addr
;
1109 *this_prologue_cache
= FRAME_OBSTACK_ZALLOC (struct rl78_prologue
);
1111 func_start
= get_frame_func (this_frame
);
1112 stop_addr
= get_frame_pc (this_frame
);
1114 /* If we couldn't find any function containing the PC, then
1115 just initialize the prologue cache, but don't do anything. */
1117 stop_addr
= func_start
;
1119 rl78_analyze_prologue (func_start
, stop_addr
,
1120 (struct rl78_prologue
*) *this_prologue_cache
);
1123 return (struct rl78_prologue
*) *this_prologue_cache
;
1126 /* Given a frame and a prologue cache, return this frame's base. */
1129 rl78_frame_base (struct frame_info
*this_frame
, void **this_prologue_cache
)
1131 struct rl78_prologue
*p
1132 = rl78_analyze_frame_prologue (this_frame
, this_prologue_cache
);
1133 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
, RL78_SP_REGNUM
);
1135 return rl78_make_data_address (sp
- p
->frame_size
);
1138 /* Implement the "frame_this_id" method for unwinding frames. */
1141 rl78_this_id (struct frame_info
*this_frame
,
1142 void **this_prologue_cache
, struct frame_id
*this_id
)
1144 *this_id
= frame_id_build (rl78_frame_base (this_frame
,
1145 this_prologue_cache
),
1146 get_frame_func (this_frame
));
1149 /* Implement the "frame_prev_register" method for unwinding frames. */
1151 static struct value
*
1152 rl78_prev_register (struct frame_info
*this_frame
,
1153 void **this_prologue_cache
, int regnum
)
1155 struct rl78_prologue
*p
1156 = rl78_analyze_frame_prologue (this_frame
, this_prologue_cache
);
1157 CORE_ADDR frame_base
= rl78_frame_base (this_frame
, this_prologue_cache
);
1159 if (regnum
== RL78_SP_REGNUM
)
1160 return frame_unwind_got_constant (this_frame
, regnum
, frame_base
);
1162 else if (regnum
== RL78_SPL_REGNUM
)
1163 return frame_unwind_got_constant (this_frame
, regnum
,
1164 (frame_base
& 0xff));
1166 else if (regnum
== RL78_SPH_REGNUM
)
1167 return frame_unwind_got_constant (this_frame
, regnum
,
1168 ((frame_base
>> 8) & 0xff));
1170 /* If prologue analysis says we saved this register somewhere,
1171 return a description of the stack slot holding it. */
1172 else if (p
->reg_offset
[regnum
] != 1)
1175 frame_unwind_got_memory (this_frame
, regnum
,
1176 frame_base
+ p
->reg_offset
[regnum
]);
1178 if (regnum
== RL78_PC_REGNUM
)
1180 ULONGEST pc
= rl78_make_instruction_address (value_as_long (rv
));
1182 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
1187 /* Otherwise, presume we haven't changed the value of this
1188 register, and get it from the next frame. */
1190 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1193 static const struct frame_unwind rl78_unwind
=
1196 default_frame_unwind_stop_reason
,
1200 default_frame_sniffer
1203 /* Implement the "dwarf_reg_to_regnum" gdbarch method. */
1206 rl78_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1208 if (0 <= reg
&& reg
<= 31)
1211 /* Map even registers to their 16-bit counterparts which have a
1212 pointer type. This is usually what is required from the DWARF
1214 return (reg
>> 1) + RL78_BANK0_RP0_PTR_REGNUM
;
1219 return RL78_SP_REGNUM
;
1223 return RL78_PSW_REGNUM
;
1225 return RL78_ES_REGNUM
;
1227 return RL78_CS_REGNUM
;
1229 return RL78_PC_REGNUM
;
1234 /* Implement the `register_sim_regno' gdbarch method. */
1237 rl78_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
1239 gdb_assert (regnum
< RL78_NUM_REGS
);
1241 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
1242 just want to override the default here which disallows register
1243 numbers which have no names. */
1247 /* Implement the "return_value" gdbarch method. */
1249 static enum return_value_convention
1250 rl78_return_value (struct gdbarch
*gdbarch
,
1251 struct value
*function
,
1252 struct type
*valtype
,
1253 struct regcache
*regcache
,
1254 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1256 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1257 ULONGEST valtype_len
= TYPE_LENGTH (valtype
);
1258 int is_g10
= gdbarch_tdep (gdbarch
)->elf_flags
& E_FLAG_RL78_G10
;
1260 if (valtype_len
> 8)
1261 return RETURN_VALUE_STRUCT_CONVENTION
;
1266 int argreg
= RL78_RAW_BANK1_R0_REGNUM
;
1267 CORE_ADDR g10_raddr
= 0xffec8;
1270 while (valtype_len
> 0)
1273 u
= read_memory_integer (g10_raddr
, 1,
1274 gdbarch_byte_order (gdbarch
));
1276 regcache_cooked_read_unsigned (regcache
, argreg
, &u
);
1277 store_unsigned_integer (readbuf
+ offset
, 1, byte_order
, u
);
1288 int argreg
= RL78_RAW_BANK1_R0_REGNUM
;
1289 CORE_ADDR g10_raddr
= 0xffec8;
1292 while (valtype_len
> 0)
1294 u
= extract_unsigned_integer (writebuf
+ offset
, 1, byte_order
);
1296 gdb_byte b
= u
& 0xff;
1297 write_memory (g10_raddr
, &b
, 1);
1300 regcache_cooked_write_unsigned (regcache
, argreg
, u
);
1308 return RETURN_VALUE_REGISTER_CONVENTION
;
1312 /* Implement the "frame_align" gdbarch method. */
1315 rl78_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1317 return rl78_make_data_address (align_down (sp
, 2));
1321 /* Implement the "dummy_id" gdbarch method. */
1323 static struct frame_id
1324 rl78_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1327 frame_id_build (rl78_make_data_address
1328 (get_frame_register_unsigned
1329 (this_frame
, RL78_SP_REGNUM
)),
1330 get_frame_pc (this_frame
));
1334 /* Implement the "push_dummy_call" gdbarch method. */
1337 rl78_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1338 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1339 int nargs
, struct value
**args
, CORE_ADDR sp
,
1340 int struct_return
, CORE_ADDR struct_addr
)
1342 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1346 /* Push arguments in reverse order. */
1347 for (i
= nargs
- 1; i
>= 0; i
--)
1349 struct type
*value_type
= value_enclosing_type (args
[i
]);
1350 int len
= TYPE_LENGTH (value_type
);
1351 int container_len
= (len
+ 1) & ~1;
1353 sp
-= container_len
;
1354 write_memory (rl78_make_data_address (sp
),
1355 value_contents_all (args
[i
]), len
);
1358 /* Store struct value address. */
1361 store_unsigned_integer (buf
, 2, byte_order
, struct_addr
);
1363 write_memory (rl78_make_data_address (sp
), buf
, 2);
1366 /* Store return address. */
1368 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
1369 write_memory (rl78_make_data_address (sp
), buf
, 4);
1371 /* Finally, update the stack pointer... */
1372 regcache_cooked_write_unsigned (regcache
, RL78_SP_REGNUM
, sp
);
1374 /* DWARF2/GCC uses the stack address *before* the function call as a
1376 return rl78_make_data_address (sp
+ 4);
1379 /* Allocate and initialize a gdbarch object. */
1381 static struct gdbarch
*
1382 rl78_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1384 struct gdbarch
*gdbarch
;
1385 struct gdbarch_tdep
*tdep
;
1388 /* Extract the elf_flags if available. */
1389 if (info
.abfd
!= NULL
1390 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
1391 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
1396 /* Try to find the architecture in the list of already defined
1398 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1400 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
1402 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
1405 return arches
->gdbarch
;
1408 /* None found, create a new architecture from the information
1410 tdep
= XCNEW (struct gdbarch_tdep
);
1411 gdbarch
= gdbarch_alloc (&info
, tdep
);
1412 tdep
->elf_flags
= elf_flags
;
1414 /* Initialize types. */
1415 tdep
->rl78_void
= arch_type (gdbarch
, TYPE_CODE_VOID
, TARGET_CHAR_BIT
,
1417 tdep
->rl78_uint8
= arch_integer_type (gdbarch
, 8, 1, "uint8_t");
1418 tdep
->rl78_int8
= arch_integer_type (gdbarch
, 8, 0, "int8_t");
1419 tdep
->rl78_uint16
= arch_integer_type (gdbarch
, 16, 1, "uint16_t");
1420 tdep
->rl78_int16
= arch_integer_type (gdbarch
, 16, 0, "int16_t");
1421 tdep
->rl78_uint32
= arch_integer_type (gdbarch
, 32, 1, "uint32_t");
1422 tdep
->rl78_int32
= arch_integer_type (gdbarch
, 32, 0, "int32_t");
1424 tdep
->rl78_data_pointer
1425 = arch_pointer_type (gdbarch
, 16, "rl78_data_addr_t", tdep
->rl78_void
);
1426 tdep
->rl78_code_pointer
1427 = arch_pointer_type (gdbarch
, 32, "rl78_code_addr_t", tdep
->rl78_void
);
1430 set_gdbarch_num_regs (gdbarch
, RL78_NUM_REGS
);
1431 set_gdbarch_num_pseudo_regs (gdbarch
, RL78_NUM_PSEUDO_REGS
);
1432 if (tdep
->elf_flags
& E_FLAG_RL78_G10
)
1433 set_gdbarch_register_name (gdbarch
, rl78_g10_register_name
);
1435 set_gdbarch_register_name (gdbarch
, rl78_register_name
);
1436 set_gdbarch_register_type (gdbarch
, rl78_register_type
);
1437 set_gdbarch_pc_regnum (gdbarch
, RL78_PC_REGNUM
);
1438 set_gdbarch_sp_regnum (gdbarch
, RL78_SP_REGNUM
);
1439 set_gdbarch_pseudo_register_read (gdbarch
, rl78_pseudo_register_read
);
1440 set_gdbarch_pseudo_register_write (gdbarch
, rl78_pseudo_register_write
);
1441 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rl78_dwarf_reg_to_regnum
);
1442 set_gdbarch_register_reggroup_p (gdbarch
, rl78_register_reggroup_p
);
1443 set_gdbarch_register_sim_regno (gdbarch
, rl78_register_sim_regno
);
1446 set_gdbarch_char_signed (gdbarch
, 0);
1447 set_gdbarch_short_bit (gdbarch
, 16);
1448 set_gdbarch_int_bit (gdbarch
, 16);
1449 set_gdbarch_long_bit (gdbarch
, 32);
1450 set_gdbarch_long_long_bit (gdbarch
, 64);
1451 set_gdbarch_ptr_bit (gdbarch
, 16);
1452 set_gdbarch_addr_bit (gdbarch
, 32);
1453 set_gdbarch_dwarf2_addr_size (gdbarch
, 4);
1454 set_gdbarch_float_bit (gdbarch
, 32);
1455 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
1456 set_gdbarch_double_bit (gdbarch
, 32);
1457 set_gdbarch_long_double_bit (gdbarch
, 64);
1458 set_gdbarch_double_format (gdbarch
, floatformats_ieee_single
);
1459 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
1460 set_gdbarch_pointer_to_address (gdbarch
, rl78_pointer_to_address
);
1461 set_gdbarch_address_to_pointer (gdbarch
, rl78_address_to_pointer
);
1462 set_gdbarch_addr_bits_remove (gdbarch
, rl78_addr_bits_remove
);
1465 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, rl78_breakpoint::kind_from_pc
);
1466 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, rl78_breakpoint::bp_from_kind
);
1467 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
1469 /* Frames, prologues, etc. */
1470 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1471 set_gdbarch_skip_prologue (gdbarch
, rl78_skip_prologue
);
1472 set_gdbarch_unwind_pc (gdbarch
, rl78_unwind_pc
);
1473 set_gdbarch_unwind_sp (gdbarch
, rl78_unwind_sp
);
1474 set_gdbarch_frame_align (gdbarch
, rl78_frame_align
);
1476 dwarf2_append_unwinders (gdbarch
);
1477 frame_unwind_append_unwinder (gdbarch
, &rl78_unwind
);
1479 /* Dummy frames, return values. */
1480 set_gdbarch_dummy_id (gdbarch
, rl78_dummy_id
);
1481 set_gdbarch_push_dummy_call (gdbarch
, rl78_push_dummy_call
);
1482 set_gdbarch_return_value (gdbarch
, rl78_return_value
);
1484 /* Virtual tables. */
1485 set_gdbarch_vbit_in_delta (gdbarch
, 1);
1490 /* Register the above initialization routine. */
1493 _initialize_rl78_tdep (void)
1495 register_gdbarch_init (bfd_arch_rl78
, rl78_gdbarch_init
);