gdb/rl78-tdep.c

   1 /* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
   2
   3    Copyright (C) 2011-2012 Free Software Foundation, Inc.
   4
   5    Contributed by Red Hat, Inc.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "defs.h"
  23 #include "arch-utils.h"
  24 #include "prologue-value.h"
  25 #include "target.h"
  26 #include "regcache.h"
  27 #include "opcode/rl78.h"
  28 #include "dis-asm.h"
  29 #include "gdbtypes.h"
  30 #include "frame.h"
  31 #include "frame-unwind.h"
  32 #include "frame-base.h"
  33 #include "value.h"
  34 #include "gdbcore.h"
  35 #include "dwarf2-frame.h"
  36
  37 #include "elf/rl78.h"
  38 #include "elf-bfd.h"
  39
  40 /* Register Banks.  */
  41
  42 enum
  43 {
  44   RL78_BANK0 = 0,
  45   RL78_BANK1 = 1,
  46   RL78_BANK2 = 2,
  47   RL78_BANK3 = 3,
  48   RL78_NUMBANKS = 4,
  49   RL78_REGS_PER_BANK = 8
  50 };
  51
  52 /* Register Numbers.  */
  53
  54 enum
  55 {
  56   /* All general purpose registers are 8 bits wide.  */
  57   RL78_BANK0_R0_REGNUM = 0,
  58   RL78_BANK0_R1_REGNUM,
  59   RL78_BANK0_R2_REGNUM,
  60   RL78_BANK0_R3_REGNUM,
  61   RL78_BANK0_R4_REGNUM,
  62   RL78_BANK0_R5_REGNUM,
  63   RL78_BANK0_R6_REGNUM,
  64   RL78_BANK0_R7_REGNUM,
  65
  66   RL78_BANK1_R0_REGNUM,
  67   RL78_BANK1_R1_REGNUM,
  68   RL78_BANK1_R2_REGNUM,
  69   RL78_BANK1_R3_REGNUM,
  70   RL78_BANK1_R4_REGNUM,
  71   RL78_BANK1_R5_REGNUM,
  72   RL78_BANK1_R6_REGNUM,
  73   RL78_BANK1_R7_REGNUM,
  74
  75   RL78_BANK2_R0_REGNUM,
  76   RL78_BANK2_R1_REGNUM,
  77   RL78_BANK2_R2_REGNUM,
  78   RL78_BANK2_R3_REGNUM,
  79   RL78_BANK2_R4_REGNUM,
  80   RL78_BANK2_R5_REGNUM,
  81   RL78_BANK2_R6_REGNUM,
  82   RL78_BANK2_R7_REGNUM,
  83
  84   RL78_BANK3_R0_REGNUM,
  85   RL78_BANK3_R1_REGNUM,
  86   RL78_BANK3_R2_REGNUM,
  87   RL78_BANK3_R3_REGNUM,
  88   RL78_BANK3_R4_REGNUM,
  89   RL78_BANK3_R5_REGNUM,
  90   RL78_BANK3_R6_REGNUM,
  91   RL78_BANK3_R7_REGNUM,
  92
  93   RL78_PSW_REGNUM,      /* 8 bits */
  94   RL78_ES_REGNUM,       /* 8 bits */
  95   RL78_CS_REGNUM,       /* 8 bits */
  96   RL78_PC_REGNUM,       /* 20 bits; we'll use 32 bits for it.  */
  97
  98   /* Fixed address SFRs (some of those above are SFRs too.) */
  99   RL78_SPL_REGNUM,      /* 8 bits; lower half of SP */
 100   RL78_SPH_REGNUM,      /* 8 bits; upper half of SP */
 101   RL78_PMC_REGNUM,      /* 8 bits */
 102   RL78_MEM_REGNUM,      /* 8 bits ?? */
 103
 104   RL78_NUM_REGS,
 105
 106   /* Pseudo registers.  */
 107   RL78_BANK0_RP0_REGNUM = RL78_NUM_REGS,
 108   RL78_BANK0_RP1_REGNUM,
 109   RL78_BANK0_RP2_REGNUM,
 110   RL78_BANK0_RP3_REGNUM,
 111
 112   RL78_BANK1_RP0_REGNUM,
 113   RL78_BANK1_RP1_REGNUM,
 114   RL78_BANK1_RP2_REGNUM,
 115   RL78_BANK1_RP3_REGNUM,
 116
 117   RL78_BANK2_RP0_REGNUM,
 118   RL78_BANK2_RP1_REGNUM,
 119   RL78_BANK2_RP2_REGNUM,
 120   RL78_BANK2_RP3_REGNUM,
 121
 122   RL78_BANK3_RP0_REGNUM,
 123   RL78_BANK3_RP1_REGNUM,
 124   RL78_BANK3_RP2_REGNUM,
 125   RL78_BANK3_RP3_REGNUM,
 126
 127   RL78_SP_REGNUM,
 128
 129   RL78_X_REGNUM,
 130   RL78_A_REGNUM,
 131   RL78_C_REGNUM,
 132   RL78_B_REGNUM,
 133   RL78_E_REGNUM,
 134   RL78_D_REGNUM,
 135   RL78_L_REGNUM,
 136   RL78_H_REGNUM,
 137
 138   RL78_AX_REGNUM,
 139   RL78_BC_REGNUM,
 140   RL78_DE_REGNUM,
 141   RL78_HL_REGNUM,
 142   RL78_NUM_TOTAL_REGS,
 143   RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
 144 };
 145
 146 /* Architecture specific data.  */
 147
 148 struct gdbarch_tdep
 149 {
 150   /* The ELF header flags specify the multilib used.  */
 151   int elf_flags;
 152
 153   struct type *rl78_void,
 154               *rl78_uint8,
 155               *rl78_int8,
 156               *rl78_uint16,
 157               *rl78_int16,
 158               *rl78_uint32,
 159               *rl78_int32,
 160               *rl78_data_pointer,
 161               *rl78_code_pointer;
 162 };
 163
 164 /* This structure holds the results of a prologue analysis.  */
 165
 166 struct rl78_prologue
 167 {
 168   /* The offset from the frame base to the stack pointer --- always
 169      zero or negative.
 170
 171      Calling this a "size" is a bit misleading, but given that the
 172      stack grows downwards, using offsets for everything keeps one
 173      from going completely sign-crazy: you never change anything's
 174      sign for an ADD instruction; always change the second operand's
 175      sign for a SUB instruction; and everything takes care of
 176      itself.  */
 177   int frame_size;
 178
 179   /* Non-zero if this function has initialized the frame pointer from
 180      the stack pointer, zero otherwise.  */
 181   int has_frame_ptr;
 182
 183   /* If has_frame_ptr is non-zero, this is the offset from the frame
 184      base to where the frame pointer points.  This is always zero or
 185      negative.  */
 186   int frame_ptr_offset;
 187
 188   /* The address of the first instruction at which the frame has been
 189      set up and the arguments are where the debug info says they are
 190      --- as best as we can tell.  */
 191   CORE_ADDR prologue_end;
 192
 193   /* reg_offset[R] is the offset from the CFA at which register R is
 194      saved, or 1 if register R has not been saved.  (Real values are
 195      always zero or negative.)  */
 196   int reg_offset[RL78_NUM_TOTAL_REGS];
 197 };
 198
 199 /* Implement the "register_type" gdbarch method.  */
 200
 201 static struct type *
 202 rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
 203 {
 204   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
 205
 206   if (reg_nr == RL78_PC_REGNUM)
 207     return tdep->rl78_code_pointer;
 208   else if (reg_nr <= RL78_MEM_REGNUM
 209            || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM))
 210     return tdep->rl78_int8;
 211   else
 212     return tdep->rl78_data_pointer;
 213 }
 214
 215 /* Implement the "register_name" gdbarch method.  */
 216
 217 static const char *
 218 rl78_register_name (struct gdbarch *gdbarch, int regnr)
 219 {
 220   static const char *const reg_names[] =
 221   {
 222     "bank0_r0",
 223     "bank0_r1",
 224     "bank0_r2",
 225     "bank0_r3",
 226     "bank0_r4",
 227     "bank0_r5",
 228     "bank0_r6",
 229     "bank0_r7",
 230
 231     "bank1_r0",
 232     "bank1_r1",
 233     "bank1_r2",
 234     "bank1_r3",
 235     "bank1_r4",
 236     "bank1_r5",
 237     "bank1_r6",
 238     "bank1_r7",
 239
 240     "bank2_r0",
 241     "bank2_r1",
 242     "bank2_r2",
 243     "bank2_r3",
 244     "bank2_r4",
 245     "bank2_r5",
 246     "bank2_r6",
 247     "bank2_r7",
 248
 249     "bank3_r0",
 250     "bank3_r1",
 251     "bank3_r2",
 252     "bank3_r3",
 253     "bank3_r4",
 254     "bank3_r5",
 255     "bank3_r6",
 256     "bank3_r7",
 257
 258     "psw",
 259     "es",
 260     "cs",
 261     "pc",
 262
 263     "spl",
 264     "sph",
 265     "pmc",
 266     "mem",
 267
 268     "bank0_rp0",
 269     "bank0_rp1",
 270     "bank0_rp2",
 271     "bank0_rp3",
 272
 273     "bank1_rp0",
 274     "bank1_rp1",
 275     "bank1_rp2",
 276     "bank1_rp3",
 277
 278     "bank2_rp0",
 279     "bank2_rp1",
 280     "bank2_rp2",
 281     "bank2_rp3",
 282
 283     "bank3_rp0",
 284     "bank3_rp1",
 285     "bank3_rp2",
 286     "bank3_rp3",
 287
 288     "sp",
 289
 290     "x",
 291     "a",
 292     "c",
 293     "b",
 294     "e",
 295     "d",
 296     "l",
 297     "h",
 298
 299     "ax",
 300     "bc",
 301     "de",
 302     "hl"
 303   };
 304
 305   return reg_names[regnr];
 306 }
 307
 308 /* Strip bits to form an instruction address.  (When fetching a
 309    32-bit address from the stack, the high eight bits are garbage.
 310    This function strips off those unused bits.)  */
 311
 312 static CORE_ADDR
 313 rl78_make_instruction_address (CORE_ADDR addr)
 314 {
 315   return addr & 0xffffff;
 316 }
 317
 318 /* Set / clear bits necessary to make a data address.  */
 319
 320 static CORE_ADDR
 321 rl78_make_data_address (CORE_ADDR addr)
 322 {
 323   return (addr & 0xffff) | 0xf0000;
 324 }
 325
 326 /* Implement the "pseudo_register_read" gdbarch method.  */
 327
 328 static enum register_status
 329 rl78_pseudo_register_read (struct gdbarch *gdbarch,
 330                            struct regcache *regcache,
 331                            int reg, gdb_byte *buffer)
 332 {
 333   enum register_status status;
 334
 335   if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
 336     {
 337       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
 338                        + RL78_BANK0_R0_REGNUM;
 339
 340       status = regcache_raw_read (regcache, raw_regnum, buffer);
 341       if (status == REG_VALID)
 342         status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
 343     }
 344   else if (reg == RL78_SP_REGNUM)
 345     {
 346       status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
 347       if (status == REG_VALID)
 348         status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
 349     }
 350   else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
 351     {
 352       ULONGEST psw;
 353
 354       status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
 355       if (status == REG_VALID)
 356         {
 357           /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
 358           int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
 359           int raw_regnum = RL78_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
 360                            + (reg - RL78_X_REGNUM);
 361           status = regcache_raw_read (regcache, raw_regnum, buffer);
 362         }
 363     }
 364   else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
 365     {
 366       ULONGEST psw;
 367
 368       status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
 369       if (status == REG_VALID)
 370         {
 371           /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
 372           int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
 373           int raw_regnum = RL78_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
 374                            + 2 * (reg - RL78_AX_REGNUM);
 375           status = regcache_raw_read (regcache, raw_regnum, buffer);
 376           if (status == REG_VALID)
 377             status = regcache_raw_read (regcache, raw_regnum + 1,
 378                                         buffer + 1);
 379         }
 380     }
 381   else
 382     gdb_assert_not_reached ("invalid pseudo register number");
 383   return status;
 384 }
 385
 386 /* Implement the "pseudo_register_write" gdbarch method.  */
 387
 388 static void
 389 rl78_pseudo_register_write (struct gdbarch *gdbarch,
 390                             struct regcache *regcache,
 391                             int reg, const gdb_byte *buffer)
 392 {
 393   if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
 394     {
 395       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
 396                        + RL78_BANK0_R0_REGNUM;
 397
 398       regcache_raw_write (regcache, raw_regnum, buffer);
 399       regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
 400     }
 401   else if (reg == RL78_SP_REGNUM)
 402     {
 403       regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
 404       regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
 405     }
 406   else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
 407     {
 408       ULONGEST psw;
 409       int bank;
 410       int raw_regnum;
 411
 412       regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
 413       bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
 414       /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
 415       raw_regnum = RL78_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
 416                    + (reg - RL78_X_REGNUM);
 417       regcache_raw_write (regcache, raw_regnum, buffer);
 418     }
 419   else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
 420     {
 421       ULONGEST psw;
 422       int bank, raw_regnum;
 423
 424       regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
 425       bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
 426       /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
 427       raw_regnum = RL78_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
 428                    + 2 * (reg - RL78_AX_REGNUM);
 429       regcache_raw_write (regcache, raw_regnum, buffer);
 430       regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
 431     }
 432   else
 433     gdb_assert_not_reached ("invalid pseudo register number");
 434 }
 435
 436 /* Implement the "breakpoint_from_pc" gdbarch method.  */
 437
 438 const gdb_byte *
 439 rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
 440                          int *lenptr)
 441 {
 442   /* The documented BRK instruction is actually a two byte sequence,
 443      {0x61, 0xcc}, but instructions may be as short as one byte.
 444      Correspondence with Renesas revealed that the one byte sequence
 445      0xff is used when a one byte breakpoint instruction is required.  */
 446   static gdb_byte breakpoint[] = { 0xff };
 447
 448   *lenptr = sizeof breakpoint;
 449   return breakpoint;
 450 }
 451
 452 /* Define a "handle" struct for fetching the next opcode.  */
 453
 454 struct rl78_get_opcode_byte_handle
 455 {
 456   CORE_ADDR pc;
 457 };
 458
 459 /* Fetch a byte on behalf of the opcode decoder.  HANDLE contains
 460    the memory address of the next byte to fetch.  If successful,
 461    the address in the handle is updated and the byte fetched is
 462    returned as the value of the function.  If not successful, -1
 463    is returned.  */
 464
 465 static int
 466 rl78_get_opcode_byte (void *handle)
 467 {
 468   struct rl78_get_opcode_byte_handle *opcdata = handle;
 469   int status;
 470   gdb_byte byte;
 471
 472   status = target_read_memory (opcdata->pc, &byte, 1);
 473   if (status == 0)
 474     {
 475       opcdata->pc += 1;
 476       return byte;
 477     }
 478   else
 479     return -1;
 480 }
 481
 482 /* Function for finding saved registers in a 'struct pv_area'; this
 483    function is passed to pv_area_scan.
 484
 485    If VALUE is a saved register, ADDR says it was saved at a constant
 486    offset from the frame base, and SIZE indicates that the whole
 487    register was saved, record its offset.  */
 488
 489 static void
 490 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
 491                  pv_t value)
 492 {
 493   struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
 494
 495   if (value.kind == pvk_register
 496       && value.k == 0
 497       && pv_is_register (addr, RL78_SP_REGNUM)
 498       && size == register_size (target_gdbarch, value.reg))
 499     result->reg_offset[value.reg] = addr.k;
 500 }
 501
 502 /* Analyze a prologue starting at START_PC, going no further than
 503    LIMIT_PC.  Fill in RESULT as appropriate.  */
 504
 505 static void
 506 rl78_analyze_prologue (CORE_ADDR start_pc,
 507                        CORE_ADDR limit_pc, struct rl78_prologue *result)
 508 {
 509   CORE_ADDR pc, next_pc;
 510   int rn;
 511   pv_t reg[RL78_NUM_TOTAL_REGS];
 512   struct pv_area *stack;
 513   struct cleanup *back_to;
 514   CORE_ADDR after_last_frame_setup_insn = start_pc;
 515   int bank = 0;
 516
 517   memset (result, 0, sizeof (*result));
 518
 519   for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
 520     {
 521       reg[rn] = pv_register (rn, 0);
 522       result->reg_offset[rn] = 1;
 523     }
 524
 525   stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch));
 526   back_to = make_cleanup_free_pv_area (stack);
 527
 528   /* The call instruction has saved the return address on the stack.  */
 529   reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
 530   pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
 531
 532   pc = start_pc;
 533   while (pc < limit_pc)
 534     {
 535       int bytes_read;
 536       struct rl78_get_opcode_byte_handle opcode_handle;
 537       RL78_Opcode_Decoded opc;
 538
 539       opcode_handle.pc = pc;
 540       bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
 541                                      &opcode_handle);
 542       next_pc = pc + bytes_read;
 543
 544       if (opc.id == RLO_sel)
 545         {
 546           bank = opc.op[1].addend;
 547         }
 548       else if (opc.id == RLO_mov
 549                && opc.op[0].type == RL78_Operand_PreDec
 550                && opc.op[0].reg == RL78_Reg_SP
 551                && opc.op[1].type == RL78_Operand_Register)
 552         {
 553           int rsrc = (bank * RL78_REGS_PER_BANK)
 554                    + 2 * (opc.op[1].reg - RL78_Reg_AX);
 555
 556           reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
 557           pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
 558           reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
 559           pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
 560           after_last_frame_setup_insn = next_pc;
 561         }
 562       else if (opc.id == RLO_sub
 563                && opc.op[0].type == RL78_Operand_Register
 564                && opc.op[0].reg == RL78_Reg_SP
 565                && opc.op[1].type == RL78_Operand_Immediate)
 566         {
 567           int addend = opc.op[1].addend;
 568
 569           reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
 570                                                  -addend);
 571           after_last_frame_setup_insn = next_pc;
 572         }
 573       else
 574         {
 575           /* Terminate the prologue scan.  */
 576           break;
 577         }
 578
 579       pc = next_pc;
 580     }
 581
 582   /* Is the frame size (offset, really) a known constant?  */
 583   if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
 584     result->frame_size = reg[RL78_SP_REGNUM].k;
 585
 586   /* Record where all the registers were saved.  */
 587   pv_area_scan (stack, check_for_saved, (void *) result);
 588
 589   result->prologue_end = after_last_frame_setup_insn;
 590
 591   do_cleanups (back_to);
 592 }
 593
 594 /* Implement the "addr_bits_remove" gdbarch method.  */
 595
 596 static CORE_ADDR
 597 rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
 598 {
 599   return addr & 0xffffff;
 600 }
 601
 602 /* Implement the "address_to_pointer" gdbarch method.  */
 603
 604 static void
 605 rl78_address_to_pointer (struct gdbarch *gdbarch,
 606                          struct type *type, gdb_byte *buf, CORE_ADDR addr)
 607 {
 608   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 609
 610   store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
 611                           addr & 0xffffff);
 612 }
 613
 614 /* Implement the "pointer_to_address" gdbarch method.  */
 615
 616 static CORE_ADDR
 617 rl78_pointer_to_address (struct gdbarch *gdbarch,
 618                          struct type *type, const gdb_byte *buf)
 619 {
 620   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 621   CORE_ADDR addr
 622     = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
 623
 624   /* Is it a code address?  */
 625   if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
 626       || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
 627       || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
 628       || TYPE_LENGTH (type) == 4)
 629     return rl78_make_instruction_address (addr);
 630   else
 631     return rl78_make_data_address (addr);
 632 }
 633
 634 /* Implement the "skip_prologue" gdbarch method.  */
 635
 636 static CORE_ADDR
 637 rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 638 {
 639   const char *name;
 640   CORE_ADDR func_addr, func_end;
 641   struct rl78_prologue p;
 642
 643   /* Try to find the extent of the function that contains PC.  */
 644   if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
 645     return pc;
 646
 647   rl78_analyze_prologue (pc, func_end, &p);
 648   return p.prologue_end;
 649 }
 650
 651 /* Implement the "unwind_pc" gdbarch method.  */
 652
 653 static CORE_ADDR
 654 rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
 655 {
 656   return rl78_addr_bits_remove
 657            (arch, frame_unwind_register_unsigned (next_frame,
 658                                                   RL78_PC_REGNUM));
 659 }
 660
 661 /* Implement the "unwind_sp" gdbarch method.  */
 662
 663 static CORE_ADDR
 664 rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
 665 {
 666   return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
 667 }
 668
 669 /* Given a frame described by THIS_FRAME, decode the prologue of its
 670    associated function if there is not cache entry as specified by
 671    THIS_PROLOGUE_CACHE.  Save the decoded prologue in the cache and
 672    return that struct as the value of this function.  */
 673
 674 static struct rl78_prologue *
 675 rl78_analyze_frame_prologue (struct frame_info *this_frame,
 676                            void **this_prologue_cache)
 677 {
 678   if (!*this_prologue_cache)
 679     {
 680       CORE_ADDR func_start, stop_addr;
 681
 682       *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
 683
 684       func_start = get_frame_func (this_frame);
 685       stop_addr = get_frame_pc (this_frame);
 686
 687       /* If we couldn't find any function containing the PC, then
 688          just initialize the prologue cache, but don't do anything.  */
 689       if (!func_start)
 690         stop_addr = func_start;
 691
 692       rl78_analyze_prologue (func_start, stop_addr, *this_prologue_cache);
 693     }
 694
 695   return *this_prologue_cache;
 696 }
 697
 698 /* Given a frame and a prologue cache, return this frame's base.  */
 699
 700 static CORE_ADDR
 701 rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
 702 {
 703   struct rl78_prologue *p
 704     = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
 705   CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
 706
 707   return rl78_make_data_address (sp - p->frame_size);
 708 }
 709
 710 /* Implement the "frame_this_id" method for unwinding frames.  */
 711
 712 static void
 713 rl78_this_id (struct frame_info *this_frame,
 714               void **this_prologue_cache, struct frame_id *this_id)
 715 {
 716   *this_id = frame_id_build (rl78_frame_base (this_frame,
 717                                               this_prologue_cache),
 718                              get_frame_func (this_frame));
 719 }
 720
 721 /* Implement the "frame_prev_register" method for unwinding frames.  */
 722
 723 static struct value *
 724 rl78_prev_register (struct frame_info *this_frame,
 725                     void **this_prologue_cache, int regnum)
 726 {
 727   struct rl78_prologue *p
 728     = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
 729   CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
 730
 731   if (regnum == RL78_SP_REGNUM)
 732     return frame_unwind_got_constant (this_frame, regnum, frame_base);
 733
 734   else if (regnum == RL78_SPL_REGNUM)
 735     return frame_unwind_got_constant (this_frame, regnum,
 736                                       (frame_base & 0xff));
 737
 738   else if (regnum == RL78_SPH_REGNUM)
 739     return frame_unwind_got_constant (this_frame, regnum,
 740                                       ((frame_base >> 8) & 0xff));
 741
 742   /* If prologue analysis says we saved this register somewhere,
 743      return a description of the stack slot holding it.  */
 744   else if (p->reg_offset[regnum] != 1)
 745     {
 746       struct value *rv =
 747         frame_unwind_got_memory (this_frame, regnum,
 748                                  frame_base + p->reg_offset[regnum]);
 749
 750       if (regnum == RL78_PC_REGNUM)
 751         {
 752           ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
 753
 754           return frame_unwind_got_constant (this_frame, regnum, pc);
 755         }
 756       return rv;
 757     }
 758
 759   /* Otherwise, presume we haven't changed the value of this
 760      register, and get it from the next frame.  */
 761   else
 762     return frame_unwind_got_register (this_frame, regnum, regnum);
 763 }
 764
 765 static const struct frame_unwind rl78_unwind =
 766 {
 767   NORMAL_FRAME,
 768   default_frame_unwind_stop_reason,
 769   rl78_this_id,
 770   rl78_prev_register,
 771   NULL,
 772   default_frame_sniffer
 773 };
 774
 775 /* Implement the "dwarf_reg_to_regnum" gdbarch method.  */
 776
 777 static int
 778 rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
 779 {
 780   if (0 <= reg && reg <= 31)
 781     {
 782       if ((reg & 1) == 0)
 783         /* Map even registers to their 16-bit counterparts.  This
 784            is usually what is required from the DWARF info.  */
 785         return (reg >> 1) + RL78_BANK0_RP0_REGNUM;
 786       else
 787         return reg;
 788     }
 789   else if (reg == 32)
 790     return RL78_SP_REGNUM;
 791   else if (reg == 33)
 792     return RL78_PC_REGNUM;
 793   else
 794     internal_error (__FILE__, __LINE__,
 795                     _("Undefined dwarf2 register mapping of reg %d"),
 796                     reg);
 797 }
 798
 799 /* Implement the "return_value" gdbarch method.  */
 800
 801 static enum return_value_convention
 802 rl78_return_value (struct gdbarch *gdbarch,
 803                    struct type *func_type,
 804                    struct type *valtype,
 805                    struct regcache *regcache,
 806                    gdb_byte *readbuf, const gdb_byte *writebuf)
 807 {
 808   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 809   ULONGEST valtype_len = TYPE_LENGTH (valtype);
 810
 811   if (valtype_len > 8)
 812     return RETURN_VALUE_STRUCT_CONVENTION;
 813
 814   if (readbuf)
 815     {
 816       ULONGEST u;
 817       int argreg = RL78_BANK1_R0_REGNUM;
 818       int offset = 0;
 819
 820       while (valtype_len > 0)
 821         {
 822           regcache_cooked_read_unsigned (regcache, argreg, &u);
 823           store_unsigned_integer (readbuf + offset, 1, byte_order, u);
 824           valtype_len -= 1;
 825           offset += 1;
 826           argreg++;
 827         }
 828     }
 829
 830   if (writebuf)
 831     {
 832       ULONGEST u;
 833       int argreg = RL78_BANK1_R0_REGNUM;
 834       int offset = 0;
 835
 836       while (valtype_len > 0)
 837         {
 838           u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
 839           regcache_cooked_write_unsigned (regcache, argreg, u);
 840           valtype_len -= 1;
 841           offset += 1;
 842           argreg++;
 843         }
 844     }
 845
 846   return RETURN_VALUE_REGISTER_CONVENTION;
 847 }
 848
 849
 850 /* Implement the "frame_align" gdbarch method.  */
 851
 852 static CORE_ADDR
 853 rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 854 {
 855   return rl78_make_data_address (align_down (sp, 2));
 856 }
 857
 858
 859 /* Implement the "dummy_id" gdbarch method.  */
 860
 861 static struct frame_id
 862 rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
 863 {
 864   return
 865     frame_id_build (rl78_make_data_address
 866                       (get_frame_register_unsigned
 867                         (this_frame, RL78_SP_REGNUM)),
 868                     get_frame_pc (this_frame));
 869 }
 870
 871
 872 /* Implement the "push_dummy_call" gdbarch method.  */
 873
 874 static CORE_ADDR
 875 rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 876                       struct regcache *regcache, CORE_ADDR bp_addr,
 877                       int nargs, struct value **args, CORE_ADDR sp,
 878                       int struct_return, CORE_ADDR struct_addr)
 879 {
 880   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 881   gdb_byte buf[4];
 882   int i;
 883
 884   /* Push arguments in reverse order.  */
 885   for (i = nargs - 1; i >= 0; i--)
 886     {
 887       struct type *value_type = value_enclosing_type (args[i]);
 888       int len = TYPE_LENGTH (value_type);
 889       int container_len = (len + 1) & ~1;
 890       int offset;
 891
 892       sp -= container_len;
 893       write_memory (rl78_make_data_address (sp),
 894                     value_contents_all (args[i]), len);
 895     }
 896
 897   /* Store struct value address.  */
 898   if (struct_return)
 899     {
 900       store_unsigned_integer (buf, 2, byte_order, struct_addr);
 901       sp -= 2;
 902       write_memory (rl78_make_data_address (sp), buf, 2);
 903     }
 904
 905   /* Store return address.  */
 906   sp -= 4;
 907   store_unsigned_integer (buf, 4, byte_order, bp_addr);
 908   write_memory (rl78_make_data_address (sp), buf, 4);
 909
 910   /* Finally, update the stack pointer...  */
 911   regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
 912
 913   /* DWARF2/GCC uses the stack address *before* the function call as a
 914      frame's CFA.  */
 915   return rl78_make_data_address (sp + 4);
 916 }
 917
 918 /* Allocate and initialize a gdbarch object.  */
 919
 920 static struct gdbarch *
 921 rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 922 {
 923   struct gdbarch *gdbarch;
 924   struct gdbarch_tdep *tdep;
 925   int elf_flags;
 926
 927   /* Extract the elf_flags if available.  */
 928   if (info.abfd != NULL
 929       && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
 930     elf_flags = elf_elfheader (info.abfd)->e_flags;
 931   else
 932     elf_flags = 0;
 933
 934
 935   /* Try to find the architecture in the list of already defined
 936      architectures.  */
 937   for (arches = gdbarch_list_lookup_by_info (arches, &info);
 938        arches != NULL;
 939        arches = gdbarch_list_lookup_by_info (arches->next, &info))
 940     {
 941       if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
 942         continue;
 943
 944       return arches->gdbarch;
 945     }
 946
 947   /* None found, create a new architecture from the information
 948      provided.  */
 949   tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
 950   gdbarch = gdbarch_alloc (&info, tdep);
 951   tdep->elf_flags = elf_flags;
 952
 953   /* Initialize types.  */
 954   tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
 955   tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
 956   tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
 957   tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
 958   tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
 959   tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
 960   tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
 961
 962   tdep->rl78_data_pointer
 963     = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
 964                  xstrdup ("rl78_data_addr_t"));
 965   TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
 966   TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;
 967
 968   tdep->rl78_code_pointer
 969     = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
 970                  xstrdup ("rl78_code_addr_t"));
 971   TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
 972   TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
 973
 974   /* Registers.  */
 975   set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
 976   set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
 977   set_gdbarch_register_name (gdbarch, rl78_register_name);
 978   set_gdbarch_register_type (gdbarch, rl78_register_type);
 979   set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
 980   set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
 981   set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
 982   set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
 983   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
 984
 985   /* Data types.  */
 986   set_gdbarch_char_signed (gdbarch, 0);
 987   set_gdbarch_short_bit (gdbarch, 16);
 988   set_gdbarch_int_bit (gdbarch, 16);
 989   set_gdbarch_long_bit (gdbarch, 32);
 990   set_gdbarch_long_long_bit (gdbarch, 64);
 991   set_gdbarch_ptr_bit (gdbarch, 16);
 992   set_gdbarch_addr_bit (gdbarch, 32);
 993   set_gdbarch_float_bit (gdbarch, 32);
 994   set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
 995   set_gdbarch_double_bit (gdbarch, 32);
 996   set_gdbarch_long_double_bit (gdbarch, 64);
 997   set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
 998   set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
 999   set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1000   set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1001   set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1002
1003   /* Breakpoints.  */
1004   set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
1005   set_gdbarch_decr_pc_after_break (gdbarch, 1);
1006
1007   /* Disassembly.  */
1008   set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1009
1010   /* Frames, prologues, etc.  */
1011   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1012   set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1013   set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1014   set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1015   set_gdbarch_frame_align (gdbarch, rl78_frame_align);
1016   frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1017
1018   /* Dummy frames, return values.  */
1019   set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1020   set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1021   set_gdbarch_return_value (gdbarch, rl78_return_value);
1022
1023   /* Virtual tables.  */
1024   set_gdbarch_vbit_in_delta (gdbarch, 1);
1025
1026   return gdbarch;
1027 }
1028
1029 /* Register the above initialization routine.  */
1030
1031 void
1032 _initialize_rl78_tdep (void)
1033 {
1034   register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
1035 }