1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* Holds the current set of options to be passed to the disassembler. */
110 static char *powerpc_disassembler_options
;
112 /* The list of available "set powerpc ..." and "show powerpc ..."
114 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
115 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
117 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
119 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
120 static const char *const powerpc_vector_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
131 static const char *powerpc_vector_abi_string
= "auto";
133 /* To be used by skip_prologue. */
135 struct rs6000_framedata
137 int offset
; /* total size of frame --- the distance
138 by which we decrement sp to allocate
140 int saved_gpr
; /* smallest # of saved gpr */
141 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
142 int saved_fpr
; /* smallest # of saved fpr */
143 int saved_vr
; /* smallest # of saved vr */
144 int saved_ev
; /* smallest # of saved ev */
145 int alloca_reg
; /* alloca register number (frame ptr) */
146 char frameless
; /* true if frameless functions. */
147 char nosavedpc
; /* true if pc not saved. */
148 char used_bl
; /* true if link register clobbered */
149 int gpr_offset
; /* offset of saved gprs from prev sp */
150 int fpr_offset
; /* offset of saved fprs from prev sp */
151 int vr_offset
; /* offset of saved vrs from prev sp */
152 int ev_offset
; /* offset of saved evs from prev sp */
153 int lr_offset
; /* offset of saved lr */
154 int lr_register
; /* register of saved lr, if trustworthy */
155 int cr_offset
; /* offset of saved cr */
156 int vrsave_offset
; /* offset of saved vrsave register */
160 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
162 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
165 if (tdep
->ppc_vsr0_regnum
< 0)
168 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
169 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
172 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
174 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
177 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
180 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
184 /* Return true if REGNO is an SPE register, false otherwise. */
186 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
190 /* Is it a reference to EV0 -- EV31, and do we have those? */
191 if (IS_SPE_PSEUDOREG (tdep
, regno
))
194 /* Is it a reference to one of the raw upper GPR halves? */
195 if (tdep
->ppc_ev0_upper_regnum
>= 0
196 && tdep
->ppc_ev0_upper_regnum
<= regno
197 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
200 /* Is it a reference to the 64-bit accumulator, and do we have that? */
201 if (tdep
->ppc_acc_regnum
>= 0
202 && tdep
->ppc_acc_regnum
== regno
)
205 /* Is it a reference to the SPE floating-point status and control register,
206 and do we have that? */
207 if (tdep
->ppc_spefscr_regnum
>= 0
208 && tdep
->ppc_spefscr_regnum
== regno
)
215 /* Return non-zero if the architecture described by GDBARCH has
216 floating-point registers (f0 --- f31 and fpscr). */
218 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 return (tdep
->ppc_fp0_regnum
>= 0
223 && tdep
->ppc_fpscr_regnum
>= 0);
226 /* Return non-zero if the architecture described by GDBARCH has
227 VSX registers (vsr0 --- vsr63). */
229 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
233 return tdep
->ppc_vsr0_regnum
>= 0;
236 /* Return non-zero if the architecture described by GDBARCH has
237 Altivec registers (vr0 --- vr31, vrsave and vscr). */
239 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
243 return (tdep
->ppc_vr0_regnum
>= 0
244 && tdep
->ppc_vrsave_regnum
>= 0);
247 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
250 This is a helper function for init_sim_regno_table, constructing
251 the table mapping GDB register numbers to sim register numbers; we
252 initialize every element in that table to -1 before we start
255 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
257 /* Make sure we don't try to assign any given GDB register a sim
258 register number more than once. */
259 gdb_assert (table
[gdb_regno
] == -1);
260 table
[gdb_regno
] = sim_regno
;
264 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
265 numbers to simulator register numbers, based on the values placed
266 in the ARCH->tdep->ppc_foo_regnum members. */
268 init_sim_regno_table (struct gdbarch
*arch
)
270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
271 int total_regs
= gdbarch_num_regs (arch
);
272 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
274 static const char *const segment_regs
[] = {
275 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
276 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
279 /* Presume that all registers not explicitly mentioned below are
280 unavailable from the sim. */
281 for (i
= 0; i
< total_regs
; i
++)
284 /* General-purpose registers. */
285 for (i
= 0; i
< ppc_num_gprs
; i
++)
286 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
288 /* Floating-point registers. */
289 if (tdep
->ppc_fp0_regnum
>= 0)
290 for (i
= 0; i
< ppc_num_fprs
; i
++)
291 set_sim_regno (sim_regno
,
292 tdep
->ppc_fp0_regnum
+ i
,
293 sim_ppc_f0_regnum
+ i
);
294 if (tdep
->ppc_fpscr_regnum
>= 0)
295 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
297 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
298 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
299 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
301 /* Segment registers. */
302 for (i
= 0; i
< ppc_num_srs
; i
++)
306 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
308 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
311 /* Altivec registers. */
312 if (tdep
->ppc_vr0_regnum
>= 0)
314 for (i
= 0; i
< ppc_num_vrs
; i
++)
315 set_sim_regno (sim_regno
,
316 tdep
->ppc_vr0_regnum
+ i
,
317 sim_ppc_vr0_regnum
+ i
);
319 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
320 we can treat this more like the other cases. */
321 set_sim_regno (sim_regno
,
322 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
323 sim_ppc_vscr_regnum
);
325 /* vsave is a special-purpose register, so the code below handles it. */
327 /* SPE APU (E500) registers. */
328 if (tdep
->ppc_ev0_upper_regnum
>= 0)
329 for (i
= 0; i
< ppc_num_gprs
; i
++)
330 set_sim_regno (sim_regno
,
331 tdep
->ppc_ev0_upper_regnum
+ i
,
332 sim_ppc_rh0_regnum
+ i
);
333 if (tdep
->ppc_acc_regnum
>= 0)
334 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
335 /* spefscr is a special-purpose register, so the code below handles it. */
338 /* Now handle all special-purpose registers. Verify that they
339 haven't mistakenly been assigned numbers by any of the above
341 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
343 const char *spr_name
= sim_spr_register_name (i
);
346 if (spr_name
!= NULL
)
347 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
350 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
354 /* Drop the initialized array into place. */
355 tdep
->sim_regno
= sim_regno
;
359 /* Given a GDB register number REG, return the corresponding SIM
362 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
364 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
367 if (tdep
->sim_regno
== NULL
)
368 init_sim_regno_table (gdbarch
);
371 && reg
<= gdbarch_num_regs (gdbarch
)
372 + gdbarch_num_pseudo_regs (gdbarch
));
373 sim_regno
= tdep
->sim_regno
[reg
];
378 return LEGACY_SIM_REGNO_IGNORE
;
383 /* Register set support functions. */
385 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
386 Write the register to REGCACHE. */
389 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
390 const gdb_byte
*regs
, size_t offset
, int regsize
)
392 if (regnum
!= -1 && offset
!= -1)
396 struct gdbarch
*gdbarch
= regcache
->arch ();
397 int gdb_regsize
= register_size (gdbarch
, regnum
);
398 if (gdb_regsize
< regsize
399 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
400 offset
+= regsize
- gdb_regsize
;
402 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
406 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
407 in a field REGSIZE wide. Zero pad as necessary. */
410 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
411 gdb_byte
*regs
, size_t offset
, int regsize
)
413 if (regnum
!= -1 && offset
!= -1)
417 struct gdbarch
*gdbarch
= regcache
->arch ();
418 int gdb_regsize
= register_size (gdbarch
, regnum
);
419 if (gdb_regsize
< regsize
)
421 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
423 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
424 offset
+= regsize
- gdb_regsize
;
427 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
428 regsize
- gdb_regsize
);
431 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
436 ppc_greg_offset (struct gdbarch
*gdbarch
,
437 struct gdbarch_tdep
*tdep
,
438 const struct ppc_reg_offsets
*offsets
,
442 *regsize
= offsets
->gpr_size
;
443 if (regnum
>= tdep
->ppc_gp0_regnum
444 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
445 return (offsets
->r0_offset
446 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
448 if (regnum
== gdbarch_pc_regnum (gdbarch
))
449 return offsets
->pc_offset
;
451 if (regnum
== tdep
->ppc_ps_regnum
)
452 return offsets
->ps_offset
;
454 if (regnum
== tdep
->ppc_lr_regnum
)
455 return offsets
->lr_offset
;
457 if (regnum
== tdep
->ppc_ctr_regnum
)
458 return offsets
->ctr_offset
;
460 *regsize
= offsets
->xr_size
;
461 if (regnum
== tdep
->ppc_cr_regnum
)
462 return offsets
->cr_offset
;
464 if (regnum
== tdep
->ppc_xer_regnum
)
465 return offsets
->xer_offset
;
467 if (regnum
== tdep
->ppc_mq_regnum
)
468 return offsets
->mq_offset
;
474 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
475 const struct ppc_reg_offsets
*offsets
,
478 if (regnum
>= tdep
->ppc_fp0_regnum
479 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
480 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
482 if (regnum
== tdep
->ppc_fpscr_regnum
)
483 return offsets
->fpscr_offset
;
489 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
490 const struct ppc_reg_offsets
*offsets
,
493 if (regnum
>= tdep
->ppc_vr0_regnum
494 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
495 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
497 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
498 return offsets
->vscr_offset
;
500 if (regnum
== tdep
->ppc_vrsave_regnum
)
501 return offsets
->vrsave_offset
;
506 /* Supply register REGNUM in the general-purpose register set REGSET
507 from the buffer specified by GREGS and LEN to register cache
508 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
511 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
512 int regnum
, const void *gregs
, size_t len
)
514 struct gdbarch
*gdbarch
= regcache
->arch ();
515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
516 const struct ppc_reg_offsets
*offsets
517 = (const struct ppc_reg_offsets
*) regset
->regmap
;
524 int gpr_size
= offsets
->gpr_size
;
526 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
527 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
528 i
++, offset
+= gpr_size
)
529 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
532 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
533 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
535 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
536 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
537 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
538 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
539 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
540 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
541 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
543 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
544 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
546 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
547 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
552 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
553 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
556 /* Supply register REGNUM in the floating-point register set REGSET
557 from the buffer specified by FPREGS and LEN to register cache
558 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
561 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
562 int regnum
, const void *fpregs
, size_t len
)
564 struct gdbarch
*gdbarch
= regcache
->arch ();
565 struct gdbarch_tdep
*tdep
;
566 const struct ppc_reg_offsets
*offsets
;
569 if (!ppc_floating_point_unit_p (gdbarch
))
572 tdep
= gdbarch_tdep (gdbarch
);
573 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
578 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
579 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
581 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
583 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
584 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
585 offsets
->fpscr_size
);
589 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
590 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
591 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
594 /* Supply register REGNUM in the VSX register set REGSET
595 from the buffer specified by VSXREGS and LEN to register cache
596 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
599 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
600 int regnum
, const void *vsxregs
, size_t len
)
602 struct gdbarch
*gdbarch
= regcache
->arch ();
603 struct gdbarch_tdep
*tdep
;
605 if (!ppc_vsx_support_p (gdbarch
))
608 tdep
= gdbarch_tdep (gdbarch
);
614 for (i
= tdep
->ppc_vsr0_upper_regnum
;
615 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
617 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vsxregs
, 0, 8);
622 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vsxregs
, 0, 8);
625 /* Supply register REGNUM in the Altivec register set REGSET
626 from the buffer specified by VRREGS and LEN to register cache
627 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
630 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
631 int regnum
, const void *vrregs
, size_t len
)
633 struct gdbarch
*gdbarch
= regcache
->arch ();
634 struct gdbarch_tdep
*tdep
;
635 const struct ppc_reg_offsets
*offsets
;
638 if (!ppc_altivec_support_p (gdbarch
))
641 tdep
= gdbarch_tdep (gdbarch
);
642 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
647 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
648 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
650 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vrregs
, offset
, 16);
652 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
653 (const gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
655 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
656 (const gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
660 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
661 if (regnum
!= tdep
->ppc_vrsave_regnum
662 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
663 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vrregs
, offset
, 16);
665 ppc_supply_reg (regcache
, regnum
,
666 (const gdb_byte
*) vrregs
, offset
, 4);
669 /* Collect register REGNUM in the general-purpose register set
670 REGSET from register cache REGCACHE into the buffer specified by
671 GREGS and LEN. If REGNUM is -1, do this for all registers in
675 ppc_collect_gregset (const struct regset
*regset
,
676 const struct regcache
*regcache
,
677 int regnum
, void *gregs
, size_t len
)
679 struct gdbarch
*gdbarch
= regcache
->arch ();
680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
681 const struct ppc_reg_offsets
*offsets
682 = (const struct ppc_reg_offsets
*) regset
->regmap
;
689 int gpr_size
= offsets
->gpr_size
;
691 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
692 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
693 i
++, offset
+= gpr_size
)
694 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
696 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
697 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
698 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
699 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
700 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
701 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
702 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
703 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
704 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
705 (gdb_byte
*) gregs
, offsets
->cr_offset
,
707 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
708 (gdb_byte
*) gregs
, offsets
->xer_offset
,
710 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
711 (gdb_byte
*) gregs
, offsets
->mq_offset
,
716 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
717 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
720 /* Collect register REGNUM in the floating-point register set
721 REGSET from register cache REGCACHE into the buffer specified by
722 FPREGS and LEN. If REGNUM is -1, do this for all registers in
726 ppc_collect_fpregset (const struct regset
*regset
,
727 const struct regcache
*regcache
,
728 int regnum
, void *fpregs
, size_t len
)
730 struct gdbarch
*gdbarch
= regcache
->arch ();
731 struct gdbarch_tdep
*tdep
;
732 const struct ppc_reg_offsets
*offsets
;
735 if (!ppc_floating_point_unit_p (gdbarch
))
738 tdep
= gdbarch_tdep (gdbarch
);
739 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
744 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
745 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
747 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
749 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
750 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
751 offsets
->fpscr_size
);
755 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
756 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
757 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
760 /* Collect register REGNUM in the VSX register set
761 REGSET from register cache REGCACHE into the buffer specified by
762 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
766 ppc_collect_vsxregset (const struct regset
*regset
,
767 const struct regcache
*regcache
,
768 int regnum
, void *vsxregs
, size_t len
)
770 struct gdbarch
*gdbarch
= regcache
->arch ();
771 struct gdbarch_tdep
*tdep
;
773 if (!ppc_vsx_support_p (gdbarch
))
776 tdep
= gdbarch_tdep (gdbarch
);
782 for (i
= tdep
->ppc_vsr0_upper_regnum
;
783 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
785 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vsxregs
, 0, 8);
790 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vsxregs
, 0, 8);
794 /* Collect register REGNUM in the Altivec register set
795 REGSET from register cache REGCACHE into the buffer specified by
796 VRREGS and LEN. If REGNUM is -1, do this for all registers in
800 ppc_collect_vrregset (const struct regset
*regset
,
801 const struct regcache
*regcache
,
802 int regnum
, void *vrregs
, size_t len
)
804 struct gdbarch
*gdbarch
= regcache
->arch ();
805 struct gdbarch_tdep
*tdep
;
806 const struct ppc_reg_offsets
*offsets
;
809 if (!ppc_altivec_support_p (gdbarch
))
812 tdep
= gdbarch_tdep (gdbarch
);
813 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
818 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
819 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
821 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vrregs
, offset
, 16);
823 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
824 (gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
826 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
827 (gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
831 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
832 if (regnum
!= tdep
->ppc_vrsave_regnum
833 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
834 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vrregs
, offset
, 16);
836 ppc_collect_reg (regcache
, regnum
,
837 (gdb_byte
*) vrregs
, offset
, 4);
842 insn_changes_sp_or_jumps (unsigned long insn
)
844 int opcode
= (insn
>> 26) & 0x03f;
845 int sd
= (insn
>> 21) & 0x01f;
846 int a
= (insn
>> 16) & 0x01f;
847 int subcode
= (insn
>> 1) & 0x3ff;
849 /* Changes the stack pointer. */
851 /* NOTE: There are many ways to change the value of a given register.
852 The ways below are those used when the register is R1, the SP,
853 in a funtion's epilogue. */
855 if (opcode
== 31 && subcode
== 444 && a
== 1)
856 return 1; /* mr R1,Rn */
857 if (opcode
== 14 && sd
== 1)
858 return 1; /* addi R1,Rn,simm */
859 if (opcode
== 58 && sd
== 1)
860 return 1; /* ld R1,ds(Rn) */
862 /* Transfers control. */
868 if (opcode
== 19 && subcode
== 16)
870 if (opcode
== 19 && subcode
== 528)
871 return 1; /* bcctr */
876 /* Return true if we are in the function's epilogue, i.e. after the
877 instruction that destroyed the function's stack frame.
879 1) scan forward from the point of execution:
880 a) If you find an instruction that modifies the stack pointer
881 or transfers control (except a return), execution is not in
883 b) Stop scanning if you find a return instruction or reach the
884 end of the function or reach the hard limit for the size of
886 2) scan backward from the point of execution:
887 a) If you find an instruction that modifies the stack pointer,
888 execution *is* in an epilogue, return.
889 b) Stop scanning if you reach an instruction that transfers
890 control or the beginning of the function or reach the hard
891 limit for the size of an epilogue. */
894 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
895 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
897 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
898 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
899 bfd_byte insn_buf
[PPC_INSN_SIZE
];
900 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
903 /* Find the search limits based on function boundaries and hard limit. */
905 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
908 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
909 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
911 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
912 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
914 /* Scan forward until next 'blr'. */
916 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
918 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
920 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
921 if (insn
== 0x4e800020)
923 /* Assume a bctr is a tail call unless it points strictly within
925 if (insn
== 0x4e800420)
927 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
928 tdep
->ppc_ctr_regnum
);
929 if (ctr
> func_start
&& ctr
< func_end
)
934 if (insn_changes_sp_or_jumps (insn
))
938 /* Scan backward until adjustment to stack pointer (R1). */
940 for (scan_pc
= pc
- PPC_INSN_SIZE
;
941 scan_pc
>= epilogue_start
;
942 scan_pc
-= PPC_INSN_SIZE
)
944 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
946 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
947 if (insn_changes_sp_or_jumps (insn
))
954 /* Implement the stack_frame_destroyed_p gdbarch method. */
957 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
959 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
963 /* Get the ith function argument for the current function. */
965 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
968 return get_frame_register_unsigned (frame
, 3 + argi
);
971 /* Sequence of bytes for breakpoint instruction. */
973 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
974 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
976 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
979 /* Instruction masks for displaced stepping. */
980 #define BRANCH_MASK 0xfc000000
981 #define BP_MASK 0xFC0007FE
982 #define B_INSN 0x48000000
983 #define BC_INSN 0x40000000
984 #define BXL_INSN 0x4c000000
985 #define BP_INSN 0x7C000008
987 /* Instruction masks used during single-stepping of atomic
989 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
990 #define LWARX_INSTRUCTION 0x7c000028
991 #define LDARX_INSTRUCTION 0x7c0000A8
992 #define LBARX_INSTRUCTION 0x7c000068
993 #define LHARX_INSTRUCTION 0x7c0000e8
994 #define LQARX_INSTRUCTION 0x7c000228
995 #define STORE_CONDITIONAL_MASK 0xfc0007ff
996 #define STWCX_INSTRUCTION 0x7c00012d
997 #define STDCX_INSTRUCTION 0x7c0001ad
998 #define STBCX_INSTRUCTION 0x7c00056d
999 #define STHCX_INSTRUCTION 0x7c0005ad
1000 #define STQCX_INSTRUCTION 0x7c00016d
1002 /* Check if insn is one of the Load And Reserve instructions used for atomic
1004 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
1005 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
1006 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
1007 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
1008 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
1009 /* Check if insn is one of the Store Conditional instructions used for atomic
1011 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
1012 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
1013 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
1014 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
1015 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
1017 typedef buf_displaced_step_closure ppc_displaced_step_closure
;
1019 /* We can't displaced step atomic sequences. */
1021 static struct displaced_step_closure
*
1022 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1023 CORE_ADDR from
, CORE_ADDR to
,
1024 struct regcache
*regs
)
1026 size_t len
= gdbarch_max_insn_length (gdbarch
);
1027 std::unique_ptr
<ppc_displaced_step_closure
> closure
1028 (new ppc_displaced_step_closure (len
));
1029 gdb_byte
*buf
= closure
->buf
.data ();
1030 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1033 read_memory (from
, buf
, len
);
1035 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
1037 /* Assume all atomic sequences start with a Load and Reserve instruction. */
1038 if (IS_LOAD_AND_RESERVE_INSN (insn
))
1040 if (debug_displaced
)
1042 fprintf_unfiltered (gdb_stdlog
,
1043 "displaced: can't displaced step "
1044 "atomic sequence at %s\n",
1045 paddress (gdbarch
, from
));
1051 write_memory (to
, buf
, len
);
1053 if (debug_displaced
)
1055 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1056 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1057 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1060 return closure
.release ();
1063 /* Fix up the state of registers and memory after having single-stepped
1064 a displaced instruction. */
1066 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
1067 struct displaced_step_closure
*closure_
,
1068 CORE_ADDR from
, CORE_ADDR to
,
1069 struct regcache
*regs
)
1071 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1072 /* Our closure is a copy of the instruction. */
1073 ppc_displaced_step_closure
*closure
= (ppc_displaced_step_closure
*) closure_
;
1074 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
1075 PPC_INSN_SIZE
, byte_order
);
1076 ULONGEST opcode
= 0;
1077 /* Offset for non PC-relative instructions. */
1078 LONGEST offset
= PPC_INSN_SIZE
;
1080 opcode
= insn
& BRANCH_MASK
;
1082 if (debug_displaced
)
1083 fprintf_unfiltered (gdb_stdlog
,
1084 "displaced: (ppc) fixup (%s, %s)\n",
1085 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1088 /* Handle PC-relative branch instructions. */
1089 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1091 ULONGEST current_pc
;
1093 /* Read the current PC value after the instruction has been executed
1094 in a displaced location. Calculate the offset to be applied to the
1095 original PC value before the displaced stepping. */
1096 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1098 offset
= current_pc
- to
;
1100 if (opcode
!= BXL_INSN
)
1102 /* Check for AA bit indicating whether this is an absolute
1103 addressing or PC-relative (1: absolute, 0: relative). */
1106 /* PC-relative addressing is being used in the branch. */
1107 if (debug_displaced
)
1110 "displaced: (ppc) branch instruction: %s\n"
1111 "displaced: (ppc) adjusted PC from %s to %s\n",
1112 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1113 paddress (gdbarch
, from
+ offset
));
1115 regcache_cooked_write_unsigned (regs
,
1116 gdbarch_pc_regnum (gdbarch
),
1122 /* If we're here, it means we have a branch to LR or CTR. If the
1123 branch was taken, the offset is probably greater than 4 (the next
1124 instruction), so it's safe to assume that an offset of 4 means we
1125 did not take the branch. */
1126 if (offset
== PPC_INSN_SIZE
)
1127 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1128 from
+ PPC_INSN_SIZE
);
1131 /* Check for LK bit indicating whether we should set the link
1132 register to point to the next instruction
1133 (1: Set, 0: Don't set). */
1136 /* Link register needs to be set to the next instruction's PC. */
1137 regcache_cooked_write_unsigned (regs
,
1138 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1139 from
+ PPC_INSN_SIZE
);
1140 if (debug_displaced
)
1141 fprintf_unfiltered (gdb_stdlog
,
1142 "displaced: (ppc) adjusted LR to %s\n",
1143 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1147 /* Check for breakpoints in the inferior. If we've found one, place the PC
1148 right at the breakpoint instruction. */
1149 else if ((insn
& BP_MASK
) == BP_INSN
)
1150 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1152 /* Handle any other instructions that do not fit in the categories above. */
1153 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1157 /* Always use hardware single-stepping to execute the
1158 displaced instruction. */
1160 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1161 struct displaced_step_closure
*closure
)
1166 /* Checks for an atomic sequence of instructions beginning with a
1167 Load And Reserve instruction and ending with a Store Conditional
1168 instruction. If such a sequence is found, attempt to step through it.
1169 A breakpoint is placed at the end of the sequence. */
1170 std::vector
<CORE_ADDR
>
1171 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1173 struct gdbarch
*gdbarch
= regcache
->arch ();
1174 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1175 CORE_ADDR pc
= regcache_read_pc (regcache
);
1176 CORE_ADDR breaks
[2] = {-1, -1};
1178 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1179 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1182 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1183 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1184 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1186 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1187 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1190 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1192 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1194 loc
+= PPC_INSN_SIZE
;
1195 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1197 /* Assume that there is at most one conditional branch in the atomic
1198 sequence. If a conditional branch is found, put a breakpoint in
1199 its destination address. */
1200 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1202 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1203 int absolute
= insn
& 2;
1205 if (bc_insn_count
>= 1)
1206 return {}; /* More than one conditional branch found, fallback
1207 to the standard single-step code. */
1210 breaks
[1] = immediate
;
1212 breaks
[1] = loc
+ immediate
;
1218 if (IS_STORE_CONDITIONAL_INSN (insn
))
1222 /* Assume that the atomic sequence ends with a Store Conditional
1224 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1228 loc
+= PPC_INSN_SIZE
;
1229 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1231 /* Insert a breakpoint right after the end of the atomic sequence. */
1234 /* Check for duplicated breakpoints. Check also for a breakpoint
1235 placed (branch instruction's destination) anywhere in sequence. */
1237 && (breaks
[1] == breaks
[0]
1238 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1239 last_breakpoint
= 0;
1241 std::vector
<CORE_ADDR
> next_pcs
;
1243 for (index
= 0; index
<= last_breakpoint
; index
++)
1244 next_pcs
.push_back (breaks
[index
]);
1250 #define SIGNED_SHORT(x) \
1251 ((sizeof (short) == 2) \
1252 ? ((int)(short)(x)) \
1253 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1255 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1257 /* Limit the number of skipped non-prologue instructions, as the examining
1258 of the prologue is expensive. */
1259 static int max_skip_non_prologue_insns
= 10;
1261 /* Return nonzero if the given instruction OP can be part of the prologue
1262 of a function and saves a parameter on the stack. FRAMEP should be
1263 set if one of the previous instructions in the function has set the
1267 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1269 /* Move parameters from argument registers to temporary register. */
1270 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1272 /* Rx must be scratch register r0. */
1273 const int rx_regno
= (op
>> 16) & 31;
1274 /* Ry: Only r3 - r10 are used for parameter passing. */
1275 const int ry_regno
= GET_SRC_REG (op
);
1277 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1279 *r0_contains_arg
= 1;
1286 /* Save a General Purpose Register on stack. */
1288 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1289 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1291 /* Rx: Only r3 - r10 are used for parameter passing. */
1292 const int rx_regno
= GET_SRC_REG (op
);
1294 return (rx_regno
>= 3 && rx_regno
<= 10);
1297 /* Save a General Purpose Register on stack via the Frame Pointer. */
1300 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1301 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1302 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1304 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1305 However, the compiler sometimes uses r0 to hold an argument. */
1306 const int rx_regno
= GET_SRC_REG (op
);
1308 return ((rx_regno
>= 3 && rx_regno
<= 10)
1309 || (rx_regno
== 0 && *r0_contains_arg
));
1312 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1314 /* Only f2 - f8 are used for parameter passing. */
1315 const int src_regno
= GET_SRC_REG (op
);
1317 return (src_regno
>= 2 && src_regno
<= 8);
1320 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1322 /* Only f2 - f8 are used for parameter passing. */
1323 const int src_regno
= GET_SRC_REG (op
);
1325 return (src_regno
>= 2 && src_regno
<= 8);
1328 /* Not an insn that saves a parameter on stack. */
1332 /* Assuming that INSN is a "bl" instruction located at PC, return
1333 nonzero if the destination of the branch is a "blrl" instruction.
1335 This sequence is sometimes found in certain function prologues.
1336 It allows the function to load the LR register with a value that
1337 they can use to access PIC data using PC-relative offsets. */
1340 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1347 absolute
= (int) ((insn
>> 1) & 1);
1348 immediate
= ((insn
& ~3) << 6) >> 6;
1352 dest
= pc
+ immediate
;
1354 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1355 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1361 /* Masks for decoding a branch-and-link (bl) instruction.
1363 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1364 The former is anded with the opcode in question; if the result of
1365 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1366 question is a ``bl'' instruction.
1368 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1369 the branch displacement. */
1371 #define BL_MASK 0xfc000001
1372 #define BL_INSTRUCTION 0x48000001
1373 #define BL_DISPLACEMENT_MASK 0x03fffffc
1375 static unsigned long
1376 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1378 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1382 /* Fetch the instruction and convert it to an integer. */
1383 if (target_read_memory (pc
, buf
, 4))
1385 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1390 /* GCC generates several well-known sequences of instructions at the begining
1391 of each function prologue when compiling with -fstack-check. If one of
1392 such sequences starts at START_PC, then return the address of the
1393 instruction immediately past this sequence. Otherwise, return START_PC. */
1396 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1398 CORE_ADDR pc
= start_pc
;
1399 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1401 /* First possible sequence: A small number of probes.
1402 stw 0, -<some immediate>(1)
1403 [repeat this instruction any (small) number of times]. */
1405 if ((op
& 0xffff0000) == 0x90010000)
1407 while ((op
& 0xffff0000) == 0x90010000)
1410 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1415 /* Second sequence: A probing loop.
1416 addi 12,1,-<some immediate>
1417 lis 0,-<some immediate>
1418 [possibly ori 0,0,<some immediate>]
1422 addi 12,12,-<some immediate>
1425 [possibly one last probe: stw 0,<some immediate>(12)]. */
1429 /* addi 12,1,-<some immediate> */
1430 if ((op
& 0xffff0000) != 0x39810000)
1433 /* lis 0,-<some immediate> */
1435 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1436 if ((op
& 0xffff0000) != 0x3c000000)
1440 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1441 /* [possibly ori 0,0,<some immediate>] */
1442 if ((op
& 0xffff0000) == 0x60000000)
1445 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1448 if (op
!= 0x7c0c0214)
1453 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1454 if (op
!= 0x7c0c0000)
1459 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1460 if ((op
& 0xff9f0001) != 0x41820000)
1463 /* addi 12,12,-<some immediate> */
1465 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1466 if ((op
& 0xffff0000) != 0x398c0000)
1471 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1472 if (op
!= 0x900c0000)
1477 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1478 if ((op
& 0xfc000001) != 0x48000000)
1481 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1483 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1484 if ((op
& 0xffff0000) == 0x900c0000)
1487 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1490 /* We found a valid stack-check sequence, return the new PC. */
1494 /* Third sequence: No probe; instead, a comparizon between the stack size
1495 limit (saved in a run-time global variable) and the current stack
1498 addi 0,1,-<some immediate>
1499 lis 12,__gnat_stack_limit@ha
1500 lwz 12,__gnat_stack_limit@l(12)
1503 or, with a small variant in the case of a bigger stack frame:
1504 addis 0,1,<some immediate>
1505 addic 0,0,-<some immediate>
1506 lis 12,__gnat_stack_limit@ha
1507 lwz 12,__gnat_stack_limit@l(12)
1512 /* addi 0,1,-<some immediate> */
1513 if ((op
& 0xffff0000) != 0x38010000)
1515 /* small stack frame variant not recognized; try the
1516 big stack frame variant: */
1518 /* addis 0,1,<some immediate> */
1519 if ((op
& 0xffff0000) != 0x3c010000)
1522 /* addic 0,0,-<some immediate> */
1524 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1525 if ((op
& 0xffff0000) != 0x30000000)
1529 /* lis 12,<some immediate> */
1531 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1532 if ((op
& 0xffff0000) != 0x3d800000)
1535 /* lwz 12,<some immediate>(12) */
1537 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1538 if ((op
& 0xffff0000) != 0x818c0000)
1543 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1544 if ((op
& 0xfffffffe) != 0x7c406008)
1547 /* We found a valid stack-check sequence, return the new PC. */
1551 /* No stack check code in our prologue, return the start_pc. */
1555 /* return pc value after skipping a function prologue and also return
1556 information about a function frame.
1558 in struct rs6000_framedata fdata:
1559 - frameless is TRUE, if function does not have a frame.
1560 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1561 - offset is the initial size of this stack frame --- the amount by
1562 which we decrement the sp to allocate the frame.
1563 - saved_gpr is the number of the first saved gpr.
1564 - saved_fpr is the number of the first saved fpr.
1565 - saved_vr is the number of the first saved vr.
1566 - saved_ev is the number of the first saved ev.
1567 - alloca_reg is the number of the register used for alloca() handling.
1569 - gpr_offset is the offset of the first saved gpr from the previous frame.
1570 - fpr_offset is the offset of the first saved fpr from the previous frame.
1571 - vr_offset is the offset of the first saved vr from the previous frame.
1572 - ev_offset is the offset of the first saved ev from the previous frame.
1573 - lr_offset is the offset of the saved lr
1574 - cr_offset is the offset of the saved cr
1575 - vrsave_offset is the offset of the saved vrsave register. */
1578 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1579 struct rs6000_framedata
*fdata
)
1581 CORE_ADDR orig_pc
= pc
;
1582 CORE_ADDR last_prologue_pc
= pc
;
1583 CORE_ADDR li_found_pc
= 0;
1587 long vr_saved_offset
= 0;
1593 int vrsave_reg
= -1;
1596 int minimal_toc_loaded
= 0;
1597 int prev_insn_was_prologue_insn
= 1;
1598 int num_skip_non_prologue_insns
= 0;
1599 int r0_contains_arg
= 0;
1600 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1601 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1602 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1604 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1605 fdata
->saved_gpr
= -1;
1606 fdata
->saved_fpr
= -1;
1607 fdata
->saved_vr
= -1;
1608 fdata
->saved_ev
= -1;
1609 fdata
->alloca_reg
= -1;
1610 fdata
->frameless
= 1;
1611 fdata
->nosavedpc
= 1;
1612 fdata
->lr_register
= -1;
1614 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1620 /* Sometimes it isn't clear if an instruction is a prologue
1621 instruction or not. When we encounter one of these ambiguous
1622 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1623 Otherwise, we'll assume that it really is a prologue instruction. */
1624 if (prev_insn_was_prologue_insn
)
1625 last_prologue_pc
= pc
;
1627 /* Stop scanning if we've hit the limit. */
1631 prev_insn_was_prologue_insn
= 1;
1633 /* Fetch the instruction and convert it to an integer. */
1634 if (target_read_memory (pc
, buf
, 4))
1636 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1638 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1640 /* Since shared library / PIC code, which needs to get its
1641 address at runtime, can appear to save more than one link
1655 remember just the first one, but skip over additional
1658 lr_reg
= (op
& 0x03e00000) >> 21;
1660 r0_contains_arg
= 0;
1663 else if ((op
& 0xfc1fffff) == 0x7c000026)
1665 cr_reg
= (op
& 0x03e00000);
1667 r0_contains_arg
= 0;
1671 else if ((op
& 0xfc1f0000) == 0xd8010000)
1672 { /* stfd Rx,NUM(r1) */
1673 reg
= GET_SRC_REG (op
);
1674 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1676 fdata
->saved_fpr
= reg
;
1677 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1682 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1683 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1684 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1685 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1688 reg
= GET_SRC_REG (op
);
1689 if ((op
& 0xfc1f0000) == 0xbc010000)
1690 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1692 fdata
->gpr_mask
|= 1U << reg
;
1693 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1695 fdata
->saved_gpr
= reg
;
1696 if ((op
& 0xfc1f0003) == 0xf8010000)
1698 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1703 else if ((op
& 0xffff0000) == 0x3c4c0000
1704 || (op
& 0xffff0000) == 0x3c400000
1705 || (op
& 0xffff0000) == 0x38420000)
1707 /* . 0: addis 2,12,.TOC.-0b@ha
1708 . addi 2,2,.TOC.-0b@l
1712 used by ELFv2 global entry points to set up r2. */
1715 else if (op
== 0x60000000)
1718 /* Allow nops in the prologue, but do not consider them to
1719 be part of the prologue unless followed by other prologue
1721 prev_insn_was_prologue_insn
= 0;
1725 else if ((op
& 0xffff0000) == 0x3c000000)
1726 { /* addis 0,0,NUM, used for >= 32k frames */
1727 fdata
->offset
= (op
& 0x0000ffff) << 16;
1728 fdata
->frameless
= 0;
1729 r0_contains_arg
= 0;
1733 else if ((op
& 0xffff0000) == 0x60000000)
1734 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1735 fdata
->offset
|= (op
& 0x0000ffff);
1736 fdata
->frameless
= 0;
1737 r0_contains_arg
= 0;
1741 else if (lr_reg
>= 0 &&
1742 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1743 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1744 /* stw Rx, NUM(r1) */
1745 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1746 /* stwu Rx, NUM(r1) */
1747 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1748 { /* where Rx == lr */
1749 fdata
->lr_offset
= offset
;
1750 fdata
->nosavedpc
= 0;
1751 /* Invalidate lr_reg, but don't set it to -1.
1752 That would mean that it had never been set. */
1754 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1755 (op
& 0xfc000000) == 0x90000000) /* stw */
1757 /* Does not update r1, so add displacement to lr_offset. */
1758 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1763 else if (cr_reg
>= 0 &&
1764 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1765 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1766 /* stw Rx, NUM(r1) */
1767 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1768 /* stwu Rx, NUM(r1) */
1769 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1770 { /* where Rx == cr */
1771 fdata
->cr_offset
= offset
;
1772 /* Invalidate cr_reg, but don't set it to -1.
1773 That would mean that it had never been set. */
1775 if ((op
& 0xfc000003) == 0xf8000000 ||
1776 (op
& 0xfc000000) == 0x90000000)
1778 /* Does not update r1, so add displacement to cr_offset. */
1779 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1784 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1786 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1787 prediction bits. If the LR has already been saved, we can
1791 else if (op
== 0x48000005)
1798 else if (op
== 0x48000004)
1803 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1804 in V.4 -mminimal-toc */
1805 (op
& 0xffff0000) == 0x3bde0000)
1806 { /* addi 30,30,foo@l */
1810 else if ((op
& 0xfc000001) == 0x48000001)
1814 fdata
->frameless
= 0;
1816 /* If the return address has already been saved, we can skip
1817 calls to blrl (for PIC). */
1818 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1824 /* Don't skip over the subroutine call if it is not within
1825 the first three instructions of the prologue and either
1826 we have no line table information or the line info tells
1827 us that the subroutine call is not part of the line
1828 associated with the prologue. */
1829 if ((pc
- orig_pc
) > 8)
1831 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1832 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1834 if ((prologue_sal
.line
== 0)
1835 || (prologue_sal
.line
!= this_sal
.line
))
1839 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1841 /* At this point, make sure this is not a trampoline
1842 function (a function that simply calls another functions,
1843 and nothing else). If the next is not a nop, this branch
1844 was part of the function prologue. */
1846 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1847 break; /* Don't skip over
1853 /* update stack pointer */
1854 else if ((op
& 0xfc1f0000) == 0x94010000)
1855 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1856 fdata
->frameless
= 0;
1857 fdata
->offset
= SIGNED_SHORT (op
);
1858 offset
= fdata
->offset
;
1861 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1862 { /* stwux rX,r1,rY */
1863 /* No way to figure out what r1 is going to be. */
1864 fdata
->frameless
= 0;
1865 offset
= fdata
->offset
;
1868 else if ((op
& 0xfc1f0003) == 0xf8010001)
1869 { /* stdu rX,NUM(r1) */
1870 fdata
->frameless
= 0;
1871 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1872 offset
= fdata
->offset
;
1875 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1876 { /* stdux rX,r1,rY */
1877 /* No way to figure out what r1 is going to be. */
1878 fdata
->frameless
= 0;
1879 offset
= fdata
->offset
;
1882 else if ((op
& 0xffff0000) == 0x38210000)
1883 { /* addi r1,r1,SIMM */
1884 fdata
->frameless
= 0;
1885 fdata
->offset
+= SIGNED_SHORT (op
);
1886 offset
= fdata
->offset
;
1889 /* Load up minimal toc pointer. Do not treat an epilogue restore
1890 of r31 as a minimal TOC load. */
1891 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1892 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1894 && !minimal_toc_loaded
)
1896 minimal_toc_loaded
= 1;
1899 /* move parameters from argument registers to local variable
1902 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1903 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1904 (((op
>> 21) & 31) <= 10) &&
1905 ((long) ((op
>> 16) & 31)
1906 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1910 /* store parameters in stack */
1912 /* Move parameters from argument registers to temporary register. */
1913 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1917 /* Set up frame pointer */
1919 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1921 fdata
->frameless
= 0;
1923 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1926 /* Another way to set up the frame pointer. */
1928 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1929 || op
== 0x7c3f0b78)
1931 fdata
->frameless
= 0;
1933 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1936 /* Another way to set up the frame pointer. */
1938 else if ((op
& 0xfc1fffff) == 0x38010000)
1939 { /* addi rX, r1, 0x0 */
1940 fdata
->frameless
= 0;
1942 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1943 + ((op
& ~0x38010000) >> 21));
1946 /* AltiVec related instructions. */
1947 /* Store the vrsave register (spr 256) in another register for
1948 later manipulation, or load a register into the vrsave
1949 register. 2 instructions are used: mfvrsave and
1950 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1951 and mtspr SPR256, Rn. */
1952 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1953 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1954 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1956 vrsave_reg
= GET_SRC_REG (op
);
1959 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1963 /* Store the register where vrsave was saved to onto the stack:
1964 rS is the register where vrsave was stored in a previous
1966 /* 100100 sssss 00001 dddddddd dddddddd */
1967 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1969 if (vrsave_reg
== GET_SRC_REG (op
))
1971 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1976 /* Compute the new value of vrsave, by modifying the register
1977 where vrsave was saved to. */
1978 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1979 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1983 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1984 in a pair of insns to save the vector registers on the
1986 /* 001110 00000 00000 iiii iiii iiii iiii */
1987 /* 001110 01110 00000 iiii iiii iiii iiii */
1988 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1989 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1991 if ((op
& 0xffff0000) == 0x38000000)
1992 r0_contains_arg
= 0;
1994 vr_saved_offset
= SIGNED_SHORT (op
);
1996 /* This insn by itself is not part of the prologue, unless
1997 if part of the pair of insns mentioned above. So do not
1998 record this insn as part of the prologue yet. */
1999 prev_insn_was_prologue_insn
= 0;
2001 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
2002 /* 011111 sssss 11111 00000 00111001110 */
2003 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
2005 if (pc
== (li_found_pc
+ 4))
2007 vr_reg
= GET_SRC_REG (op
);
2008 /* If this is the first vector reg to be saved, or if
2009 it has a lower number than others previously seen,
2010 reupdate the frame info. */
2011 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
2013 fdata
->saved_vr
= vr_reg
;
2014 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2016 vr_saved_offset
= -1;
2021 /* End AltiVec related instructions. */
2023 /* Start BookE related instructions. */
2024 /* Store gen register S at (r31+uimm).
2025 Any register less than r13 is volatile, so we don't care. */
2026 /* 000100 sssss 11111 iiiii 01100100001 */
2027 else if (arch_info
->mach
== bfd_mach_ppc_e500
2028 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2030 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2033 ev_reg
= GET_SRC_REG (op
);
2034 imm
= (op
>> 11) & 0x1f;
2035 ev_offset
= imm
* 8;
2036 /* If this is the first vector reg to be saved, or if
2037 it has a lower number than others previously seen,
2038 reupdate the frame info. */
2039 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2041 fdata
->saved_ev
= ev_reg
;
2042 fdata
->ev_offset
= ev_offset
+ offset
;
2047 /* Store gen register rS at (r1+rB). */
2048 /* 000100 sssss 00001 bbbbb 01100100000 */
2049 else if (arch_info
->mach
== bfd_mach_ppc_e500
2050 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2052 if (pc
== (li_found_pc
+ 4))
2054 ev_reg
= GET_SRC_REG (op
);
2055 /* If this is the first vector reg to be saved, or if
2056 it has a lower number than others previously seen,
2057 reupdate the frame info. */
2058 /* We know the contents of rB from the previous instruction. */
2059 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2061 fdata
->saved_ev
= ev_reg
;
2062 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2064 vr_saved_offset
= -1;
2070 /* Store gen register r31 at (rA+uimm). */
2071 /* 000100 11111 aaaaa iiiii 01100100001 */
2072 else if (arch_info
->mach
== bfd_mach_ppc_e500
2073 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2075 /* Wwe know that the source register is 31 already, but
2076 it can't hurt to compute it. */
2077 ev_reg
= GET_SRC_REG (op
);
2078 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2079 /* If this is the first vector reg to be saved, or if
2080 it has a lower number than others previously seen,
2081 reupdate the frame info. */
2082 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2084 fdata
->saved_ev
= ev_reg
;
2085 fdata
->ev_offset
= ev_offset
+ offset
;
2090 /* Store gen register S at (r31+r0).
2091 Store param on stack when offset from SP bigger than 4 bytes. */
2092 /* 000100 sssss 11111 00000 01100100000 */
2093 else if (arch_info
->mach
== bfd_mach_ppc_e500
2094 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2096 if (pc
== (li_found_pc
+ 4))
2098 if ((op
& 0x03e00000) >= 0x01a00000)
2100 ev_reg
= GET_SRC_REG (op
);
2101 /* If this is the first vector reg to be saved, or if
2102 it has a lower number than others previously seen,
2103 reupdate the frame info. */
2104 /* We know the contents of r0 from the previous
2106 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2108 fdata
->saved_ev
= ev_reg
;
2109 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2113 vr_saved_offset
= -1;
2118 /* End BookE related instructions. */
2122 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2124 /* Not a recognized prologue instruction.
2125 Handle optimizer code motions into the prologue by continuing
2126 the search if we have no valid frame yet or if the return
2127 address is not yet saved in the frame. Also skip instructions
2128 if some of the GPRs expected to be saved are not yet saved. */
2129 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2130 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2133 if (op
== 0x4e800020 /* blr */
2134 || op
== 0x4e800420) /* bctr */
2135 /* Do not scan past epilogue in frameless functions or
2138 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2139 /* Never skip branches. */
2142 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2143 /* Do not scan too many insns, scanning insns is expensive with
2147 /* Continue scanning. */
2148 prev_insn_was_prologue_insn
= 0;
2154 /* I have problems with skipping over __main() that I need to address
2155 * sometime. Previously, I used to use misc_function_vector which
2156 * didn't work as well as I wanted to be. -MGO */
2158 /* If the first thing after skipping a prolog is a branch to a function,
2159 this might be a call to an initializer in main(), introduced by gcc2.
2160 We'd like to skip over it as well. Fortunately, xlc does some extra
2161 work before calling a function right after a prologue, thus we can
2162 single out such gcc2 behaviour. */
2165 if ((op
& 0xfc000001) == 0x48000001)
2166 { /* bl foo, an initializer function? */
2167 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2169 if (op
== 0x4def7b82)
2170 { /* cror 0xf, 0xf, 0xf (nop) */
2172 /* Check and see if we are in main. If so, skip over this
2173 initializer function as well. */
2175 tmp
= find_pc_misc_function (pc
);
2177 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2183 if (pc
== lim_pc
&& lr_reg
>= 0)
2184 fdata
->lr_register
= lr_reg
;
2186 fdata
->offset
= -fdata
->offset
;
2187 return last_prologue_pc
;
2191 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2193 struct rs6000_framedata frame
;
2194 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2196 /* See if we can determine the end of the prologue via the symbol table.
2197 If so, then return either PC, or the PC after the prologue, whichever
2199 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2201 CORE_ADDR post_prologue_pc
2202 = skip_prologue_using_sal (gdbarch
, func_addr
);
2203 if (post_prologue_pc
!= 0)
2204 return std::max (pc
, post_prologue_pc
);
2207 /* Can't determine prologue from the symbol table, need to examine
2210 /* Find an upper limit on the function prologue using the debug
2211 information. If the debug information could not be used to provide
2212 that bound, then use an arbitrary large number as the upper bound. */
2213 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2215 limit_pc
= pc
+ 100; /* Magic. */
2217 /* Do not allow limit_pc to be past the function end, if we know
2218 where that end is... */
2219 if (func_end_addr
&& limit_pc
> func_end_addr
)
2220 limit_pc
= func_end_addr
;
2222 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2226 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2227 in the prologue of main().
2229 The function below examines the code pointed at by PC and checks to
2230 see if it corresponds to a call to __eabi. If so, it returns the
2231 address of the instruction following that call. Otherwise, it simply
2235 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2237 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2241 if (target_read_memory (pc
, buf
, 4))
2243 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2245 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2247 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2248 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2249 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2251 /* We check for ___eabi (three leading underscores) in addition
2252 to __eabi in case the GCC option "-fleading-underscore" was
2253 used to compile the program. */
2254 if (s
.minsym
!= NULL
2255 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2256 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2257 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2263 /* All the ABI's require 16 byte alignment. */
2265 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2267 return (addr
& -16);
2270 /* Return whether handle_inferior_event() should proceed through code
2271 starting at PC in function NAME when stepping.
2273 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2274 handle memory references that are too distant to fit in instructions
2275 generated by the compiler. For example, if 'foo' in the following
2280 is greater than 32767, the linker might replace the lwz with a branch to
2281 somewhere in @FIX1 that does the load in 2 instructions and then branches
2282 back to where execution should continue.
2284 GDB should silently step over @FIX code, just like AIX dbx does.
2285 Unfortunately, the linker uses the "b" instruction for the
2286 branches, meaning that the link register doesn't get set.
2287 Therefore, GDB's usual step_over_function () mechanism won't work.
2289 Instead, use the gdbarch_skip_trampoline_code and
2290 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2294 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2295 CORE_ADDR pc
, const char *name
)
2297 return name
&& startswith (name
, "@FIX");
2300 /* Skip code that the user doesn't want to see when stepping:
2302 1. Indirect function calls use a piece of trampoline code to do context
2303 switching, i.e. to set the new TOC table. Skip such code if we are on
2304 its first instruction (as when we have single-stepped to here).
2306 2. Skip shared library trampoline code (which is different from
2307 indirect function call trampolines).
2309 3. Skip bigtoc fixup code.
2311 Result is desired PC to step until, or NULL if we are not in
2312 code that should be skipped. */
2315 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2317 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2318 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2319 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2320 unsigned int ii
, op
;
2322 CORE_ADDR solib_target_pc
;
2323 struct bound_minimal_symbol msymbol
;
2325 static unsigned trampoline_code
[] =
2327 0x800b0000, /* l r0,0x0(r11) */
2328 0x90410014, /* st r2,0x14(r1) */
2329 0x7c0903a6, /* mtctr r0 */
2330 0x804b0004, /* l r2,0x4(r11) */
2331 0x816b0008, /* l r11,0x8(r11) */
2332 0x4e800420, /* bctr */
2333 0x4e800020, /* br */
2337 /* Check for bigtoc fixup code. */
2338 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2340 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2341 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2343 /* Double-check that the third instruction from PC is relative "b". */
2344 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2345 if ((op
& 0xfc000003) == 0x48000000)
2347 /* Extract bits 6-29 as a signed 24-bit relative word address and
2348 add it to the containing PC. */
2349 rel
= ((int)(op
<< 6) >> 6);
2350 return pc
+ 8 + rel
;
2354 /* If pc is in a shared library trampoline, return its target. */
2355 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2356 if (solib_target_pc
)
2357 return solib_target_pc
;
2359 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2361 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2362 if (op
!= trampoline_code
[ii
])
2365 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2367 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2371 /* ISA-specific vector types. */
2373 static struct type
*
2374 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2376 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2378 if (!tdep
->ppc_builtin_type_vec64
)
2380 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2382 /* The type we're building is this: */
2384 union __gdb_builtin_type_vec64
2388 int32_t v2_int32
[2];
2389 int16_t v4_int16
[4];
2396 t
= arch_composite_type (gdbarch
,
2397 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2398 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2399 append_composite_type_field (t
, "v2_float",
2400 init_vector_type (bt
->builtin_float
, 2));
2401 append_composite_type_field (t
, "v2_int32",
2402 init_vector_type (bt
->builtin_int32
, 2));
2403 append_composite_type_field (t
, "v4_int16",
2404 init_vector_type (bt
->builtin_int16
, 4));
2405 append_composite_type_field (t
, "v8_int8",
2406 init_vector_type (bt
->builtin_int8
, 8));
2408 TYPE_VECTOR (t
) = 1;
2409 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2410 tdep
->ppc_builtin_type_vec64
= t
;
2413 return tdep
->ppc_builtin_type_vec64
;
2416 /* Vector 128 type. */
2418 static struct type
*
2419 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2421 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2423 if (!tdep
->ppc_builtin_type_vec128
)
2425 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2427 /* The type we're building is this
2429 type = union __ppc_builtin_type_vec128 {
2431 double v2_double[2];
2433 int32_t v4_int32[4];
2434 int16_t v8_int16[8];
2435 int8_t v16_int8[16];
2441 t
= arch_composite_type (gdbarch
,
2442 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2443 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2444 append_composite_type_field (t
, "v2_double",
2445 init_vector_type (bt
->builtin_double
, 2));
2446 append_composite_type_field (t
, "v4_float",
2447 init_vector_type (bt
->builtin_float
, 4));
2448 append_composite_type_field (t
, "v4_int32",
2449 init_vector_type (bt
->builtin_int32
, 4));
2450 append_composite_type_field (t
, "v8_int16",
2451 init_vector_type (bt
->builtin_int16
, 8));
2452 append_composite_type_field (t
, "v16_int8",
2453 init_vector_type (bt
->builtin_int8
, 16));
2455 TYPE_VECTOR (t
) = 1;
2456 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2457 tdep
->ppc_builtin_type_vec128
= t
;
2460 return tdep
->ppc_builtin_type_vec128
;
2463 /* Return the name of register number REGNO, or the empty string if it
2464 is an anonymous register. */
2467 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2469 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2471 /* The upper half "registers" have names in the XML description,
2472 but we present only the low GPRs and the full 64-bit registers
2474 if (tdep
->ppc_ev0_upper_regnum
>= 0
2475 && tdep
->ppc_ev0_upper_regnum
<= regno
2476 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2479 /* Hide the upper halves of the vs0~vs31 registers. */
2480 if (tdep
->ppc_vsr0_regnum
>= 0
2481 && tdep
->ppc_vsr0_upper_regnum
<= regno
2482 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2485 /* Check if the SPE pseudo registers are available. */
2486 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2488 static const char *const spe_regnames
[] = {
2489 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2490 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2491 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2492 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2494 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2497 /* Check if the decimal128 pseudo-registers are available. */
2498 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2500 static const char *const dfp128_regnames
[] = {
2501 "dl0", "dl1", "dl2", "dl3",
2502 "dl4", "dl5", "dl6", "dl7",
2503 "dl8", "dl9", "dl10", "dl11",
2504 "dl12", "dl13", "dl14", "dl15"
2506 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2509 /* Check if this is a VSX pseudo-register. */
2510 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2512 static const char *const vsx_regnames
[] = {
2513 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2514 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2515 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2516 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2517 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2518 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2519 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2520 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2521 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2523 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2526 /* Check if the this is a Extended FP pseudo-register. */
2527 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2529 static const char *const efpr_regnames
[] = {
2530 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2531 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2532 "f46", "f47", "f48", "f49", "f50", "f51",
2533 "f52", "f53", "f54", "f55", "f56", "f57",
2534 "f58", "f59", "f60", "f61", "f62", "f63"
2536 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2539 return tdesc_register_name (gdbarch
, regno
);
2542 /* Return the GDB type object for the "standard" data type of data in
2545 static struct type
*
2546 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2548 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2550 /* These are the only pseudo-registers we support. */
2551 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2552 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2553 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2554 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2556 /* These are the e500 pseudo-registers. */
2557 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2558 return rs6000_builtin_type_vec64 (gdbarch
);
2559 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2560 /* PPC decimal128 pseudo-registers. */
2561 return builtin_type (gdbarch
)->builtin_declong
;
2562 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2563 /* POWER7 VSX pseudo-registers. */
2564 return rs6000_builtin_type_vec128 (gdbarch
);
2566 /* POWER7 Extended FP pseudo-registers. */
2567 return builtin_type (gdbarch
)->builtin_double
;
2570 /* Is REGNUM a member of REGGROUP? */
2572 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2573 struct reggroup
*group
)
2575 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2577 /* These are the only pseudo-registers we support. */
2578 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2579 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2580 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2581 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2583 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2584 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2585 return group
== all_reggroup
|| group
== vector_reggroup
;
2587 /* PPC decimal128 or Extended FP pseudo-registers. */
2588 return group
== all_reggroup
|| group
== float_reggroup
;
2591 /* The register format for RS/6000 floating point registers is always
2592 double, we need a conversion if the memory format is float. */
2595 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2598 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2600 return (tdep
->ppc_fp0_regnum
>= 0
2601 && regnum
>= tdep
->ppc_fp0_regnum
2602 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2603 && TYPE_CODE (type
) == TYPE_CODE_FLT
2604 && TYPE_LENGTH (type
)
2605 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2609 rs6000_register_to_value (struct frame_info
*frame
,
2613 int *optimizedp
, int *unavailablep
)
2615 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2616 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2618 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2620 if (!get_frame_register_bytes (frame
, regnum
, 0,
2621 register_size (gdbarch
, regnum
),
2622 from
, optimizedp
, unavailablep
))
2625 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2627 *optimizedp
= *unavailablep
= 0;
2632 rs6000_value_to_register (struct frame_info
*frame
,
2635 const gdb_byte
*from
)
2637 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2638 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2640 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2642 convert_typed_floating (from
, type
,
2643 to
, builtin_type (gdbarch
)->builtin_double
);
2644 put_frame_register (frame
, regnum
, to
);
2647 /* The type of a function that moves the value of REG between CACHE
2648 or BUF --- in either direction. */
2649 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2652 /* Move SPE vector register values between a 64-bit buffer and the two
2653 32-bit raw register halves in a regcache. This function handles
2654 both splitting a 64-bit value into two 32-bit halves, and joining
2655 two halves into a whole 64-bit value, depending on the function
2656 passed as the MOVE argument.
2658 EV_REG must be the number of an SPE evN vector register --- a
2659 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2662 Call MOVE once for each 32-bit half of that register, passing
2663 REGCACHE, the number of the raw register corresponding to that
2664 half, and the address of the appropriate half of BUFFER.
2666 For example, passing 'regcache_raw_read' as the MOVE function will
2667 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2668 'regcache_raw_supply' will supply the contents of BUFFER to the
2669 appropriate pair of raw registers in REGCACHE.
2671 You may need to cast away some 'const' qualifiers when passing
2672 MOVE, since this function can't tell at compile-time which of
2673 REGCACHE or BUFFER is acting as the source of the data. If C had
2674 co-variant type qualifiers, ... */
2676 static enum register_status
2677 e500_move_ev_register (move_ev_register_func move
,
2678 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2680 struct gdbarch
*arch
= regcache
->arch ();
2681 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2683 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2684 enum register_status status
;
2686 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2688 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2690 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2692 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2694 if (status
== REG_VALID
)
2695 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2700 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2701 if (status
== REG_VALID
)
2702 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2709 static enum register_status
2710 do_regcache_raw_read (struct regcache
*regcache
, int regnum
, void *buffer
)
2712 return regcache_raw_read (regcache
, regnum
, (gdb_byte
*) buffer
);
2715 static enum register_status
2716 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2718 regcache_raw_write (regcache
, regnum
, (const gdb_byte
*) buffer
);
2723 static enum register_status
2724 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2725 int reg_nr
, gdb_byte
*buffer
)
2727 return e500_move_ev_register (do_regcache_raw_read
, regcache
, reg_nr
, buffer
);
2731 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2732 int reg_nr
, const gdb_byte
*buffer
)
2734 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2735 reg_nr
, (void *) buffer
);
2738 /* Read method for DFP pseudo-registers. */
2739 static enum register_status
2740 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2741 int reg_nr
, gdb_byte
*buffer
)
2743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2744 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2745 enum register_status status
;
2747 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2749 /* Read two FP registers to form a whole dl register. */
2750 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2751 2 * reg_index
, buffer
);
2752 if (status
== REG_VALID
)
2753 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2754 2 * reg_index
+ 1, buffer
+ 8);
2758 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2759 2 * reg_index
+ 1, buffer
);
2760 if (status
== REG_VALID
)
2761 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2762 2 * reg_index
, buffer
+ 8);
2768 /* Write method for DFP pseudo-registers. */
2770 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2771 int reg_nr
, const gdb_byte
*buffer
)
2773 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2774 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2776 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2778 /* Write each half of the dl register into a separate
2780 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2781 2 * reg_index
, buffer
);
2782 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2783 2 * reg_index
+ 1, buffer
+ 8);
2787 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2788 2 * reg_index
+ 1, buffer
);
2789 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2790 2 * reg_index
, buffer
+ 8);
2794 /* Read method for POWER7 VSX pseudo-registers. */
2795 static enum register_status
2796 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2797 int reg_nr
, gdb_byte
*buffer
)
2799 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2800 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2801 enum register_status status
;
2803 /* Read the portion that overlaps the VMX registers. */
2805 status
= regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2806 reg_index
- 32, buffer
);
2808 /* Read the portion that overlaps the FPR registers. */
2809 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2811 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2813 if (status
== REG_VALID
)
2814 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2815 reg_index
, buffer
+ 8);
2819 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2820 reg_index
, buffer
+ 8);
2821 if (status
== REG_VALID
)
2822 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2829 /* Write method for POWER7 VSX pseudo-registers. */
2831 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2832 int reg_nr
, const gdb_byte
*buffer
)
2834 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2835 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2837 /* Write the portion that overlaps the VMX registers. */
2839 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2840 reg_index
- 32, buffer
);
2842 /* Write the portion that overlaps the FPR registers. */
2843 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2845 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2847 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2848 reg_index
, buffer
+ 8);
2852 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2853 reg_index
, buffer
+ 8);
2854 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2859 /* Read method for POWER7 Extended FP pseudo-registers. */
2860 static enum register_status
2861 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2862 int reg_nr
, gdb_byte
*buffer
)
2864 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2865 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2866 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2868 /* Read the portion that overlaps the VMX register. */
2869 return regcache_raw_read_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2870 offset
, register_size (gdbarch
, reg_nr
),
2874 /* Write method for POWER7 Extended FP pseudo-registers. */
2876 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2877 int reg_nr
, const gdb_byte
*buffer
)
2879 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2880 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2881 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2883 /* Write the portion that overlaps the VMX register. */
2884 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2885 offset
, register_size (gdbarch
, reg_nr
),
2889 static enum register_status
2890 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2891 struct regcache
*regcache
,
2892 int reg_nr
, gdb_byte
*buffer
)
2894 struct gdbarch
*regcache_arch
= regcache
->arch ();
2895 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2897 gdb_assert (regcache_arch
== gdbarch
);
2899 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2900 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2901 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2902 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2903 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2904 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2905 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2906 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2908 internal_error (__FILE__
, __LINE__
,
2909 _("rs6000_pseudo_register_read: "
2910 "called on unexpected register '%s' (%d)"),
2911 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2915 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2916 struct regcache
*regcache
,
2917 int reg_nr
, const gdb_byte
*buffer
)
2919 struct gdbarch
*regcache_arch
= regcache
->arch ();
2920 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2922 gdb_assert (regcache_arch
== gdbarch
);
2924 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2925 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2926 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2927 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2928 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2929 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2930 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2931 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2933 internal_error (__FILE__
, __LINE__
,
2934 _("rs6000_pseudo_register_write: "
2935 "called on unexpected register '%s' (%d)"),
2936 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2940 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2941 struct agent_expr
*ax
, int reg_nr
)
2943 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2944 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2946 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
2947 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
2948 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
2950 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2952 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2953 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
2954 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
2956 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2958 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2961 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
2965 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
2966 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
2969 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2971 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2972 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
2975 internal_error (__FILE__
, __LINE__
,
2976 _("rs6000_pseudo_register_collect: "
2977 "called on unexpected register '%s' (%d)"),
2978 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2984 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
2985 struct agent_expr
*ax
, struct axs_value
*value
,
2988 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2989 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
2990 value
->kind
= axs_lvalue_register
;
2991 value
->u
.reg
= tdep
->ppc_lr_regnum
;
2995 /* Convert a DBX STABS register number to a GDB register number. */
2997 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2999 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3001 if (0 <= num
&& num
<= 31)
3002 return tdep
->ppc_gp0_regnum
+ num
;
3003 else if (32 <= num
&& num
<= 63)
3004 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3005 specifies registers the architecture doesn't have? Our
3006 callers don't check the value we return. */
3007 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3008 else if (77 <= num
&& num
<= 108)
3009 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3010 else if (1200 <= num
&& num
< 1200 + 32)
3011 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3016 return tdep
->ppc_mq_regnum
;
3018 return tdep
->ppc_lr_regnum
;
3020 return tdep
->ppc_ctr_regnum
;
3022 return tdep
->ppc_xer_regnum
;
3024 return tdep
->ppc_vrsave_regnum
;
3026 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3028 return tdep
->ppc_acc_regnum
;
3030 return tdep
->ppc_spefscr_regnum
;
3037 /* Convert a Dwarf 2 register number to a GDB register number. */
3039 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3041 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3043 if (0 <= num
&& num
<= 31)
3044 return tdep
->ppc_gp0_regnum
+ num
;
3045 else if (32 <= num
&& num
<= 63)
3046 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3047 specifies registers the architecture doesn't have? Our
3048 callers don't check the value we return. */
3049 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3050 else if (1124 <= num
&& num
< 1124 + 32)
3051 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3052 else if (1200 <= num
&& num
< 1200 + 32)
3053 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3058 return tdep
->ppc_cr_regnum
;
3060 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3062 return tdep
->ppc_acc_regnum
;
3064 return tdep
->ppc_mq_regnum
;
3066 return tdep
->ppc_xer_regnum
;
3068 return tdep
->ppc_lr_regnum
;
3070 return tdep
->ppc_ctr_regnum
;
3072 return tdep
->ppc_vrsave_regnum
;
3074 return tdep
->ppc_spefscr_regnum
;
3080 /* Translate a .eh_frame register to DWARF register, or adjust a
3081 .debug_frame register. */
3084 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3086 /* GCC releases before 3.4 use GCC internal register numbering in
3087 .debug_frame (and .debug_info, et cetera). The numbering is
3088 different from the standard SysV numbering for everything except
3089 for GPRs and FPRs. We can not detect this problem in most cases
3090 - to get accurate debug info for variables living in lr, ctr, v0,
3091 et cetera, use a newer version of GCC. But we must detect
3092 one important case - lr is in column 65 in .debug_frame output,
3095 GCC 3.4, and the "hammer" branch, have a related problem. They
3096 record lr register saves in .debug_frame as 108, but still record
3097 the return column as 65. We fix that up too.
3099 We can do this because 65 is assigned to fpsr, and GCC never
3100 generates debug info referring to it. To add support for
3101 handwritten debug info that restores fpsr, we would need to add a
3102 producer version check to this. */
3111 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3112 internal register numbering; translate that to the standard DWARF2
3113 register numbering. */
3114 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3116 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3117 return num
- 68 + 86;
3118 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3119 return num
- 77 + 1124;
3131 case 109: /* vrsave */
3133 case 110: /* vscr */
3135 case 111: /* spe_acc */
3137 case 112: /* spefscr */
3145 /* Handling the various POWER/PowerPC variants. */
3147 /* Information about a particular processor variant. */
3151 /* Name of this variant. */
3154 /* English description of the variant. */
3155 const char *description
;
3157 /* bfd_arch_info.arch corresponding to variant. */
3158 enum bfd_architecture arch
;
3160 /* bfd_arch_info.mach corresponding to variant. */
3163 /* Target description for this variant. */
3164 struct target_desc
**tdesc
;
3167 static struct variant variants
[] =
3169 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3170 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3171 {"power", "POWER user-level", bfd_arch_rs6000
,
3172 bfd_mach_rs6k
, &tdesc_rs6000
},
3173 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3174 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3175 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3176 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3177 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3178 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3179 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3180 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3181 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3182 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3183 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3184 604, &tdesc_powerpc_604
},
3185 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3186 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3187 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3188 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3189 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3190 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3191 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3192 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3193 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3194 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3195 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3196 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3199 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3200 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3201 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3202 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3203 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3204 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3205 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3206 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3207 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3208 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3209 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3210 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3212 /* FIXME: I haven't checked the register sets of the following. */
3213 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3214 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3215 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3216 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3217 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3218 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3220 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3223 /* Return the variant corresponding to architecture ARCH and machine number
3224 MACH. If no such variant exists, return null. */
3226 static const struct variant
*
3227 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3229 const struct variant
*v
;
3231 for (v
= variants
; v
->name
; v
++)
3232 if (arch
== v
->arch
&& mach
== v
->mach
)
3240 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3242 return frame_unwind_register_unsigned (next_frame
,
3243 gdbarch_pc_regnum (gdbarch
));
3246 static struct frame_id
3247 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3249 return frame_id_build (get_frame_register_unsigned
3250 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3251 get_frame_pc (this_frame
));
3254 struct rs6000_frame_cache
3257 CORE_ADDR initial_sp
;
3258 struct trad_frame_saved_reg
*saved_regs
;
3260 /* Set BASE_P to true if this frame cache is properly initialized.
3261 Otherwise set to false because some registers or memory cannot
3264 /* Cache PC for building unavailable frame. */
3268 static struct rs6000_frame_cache
*
3269 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3271 struct rs6000_frame_cache
*cache
;
3272 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3273 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3274 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3275 struct rs6000_framedata fdata
;
3276 int wordsize
= tdep
->wordsize
;
3277 CORE_ADDR func
= 0, pc
= 0;
3279 if ((*this_cache
) != NULL
)
3280 return (struct rs6000_frame_cache
*) (*this_cache
);
3281 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3282 (*this_cache
) = cache
;
3284 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3288 func
= get_frame_func (this_frame
);
3290 pc
= get_frame_pc (this_frame
);
3291 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3293 /* Figure out the parent's stack pointer. */
3295 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3296 address of the current frame. Things might be easier if the
3297 ->frame pointed to the outer-most address of the frame. In
3298 the mean time, the address of the prev frame is used as the
3299 base address of this frame. */
3300 cache
->base
= get_frame_register_unsigned
3301 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3303 CATCH (ex
, RETURN_MASK_ERROR
)
3305 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3306 throw_exception (ex
);
3307 return (struct rs6000_frame_cache
*) (*this_cache
);
3311 /* If the function appears to be frameless, check a couple of likely
3312 indicators that we have simply failed to find the frame setup.
3313 Two common cases of this are missing symbols (i.e.
3314 get_frame_func returns the wrong address or 0), and assembly
3315 stubs which have a fast exit path but set up a frame on the slow
3318 If the LR appears to return to this function, then presume that
3319 we have an ABI compliant frame that we failed to find. */
3320 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3325 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3326 if (func
== 0 && saved_lr
== pc
)
3330 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3331 if (func
== saved_func
)
3337 fdata
.frameless
= 0;
3338 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3342 if (!fdata
.frameless
)
3344 /* Frameless really means stackless. */
3347 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3348 byte_order
, &backchain
))
3349 cache
->base
= (CORE_ADDR
) backchain
;
3352 trad_frame_set_value (cache
->saved_regs
,
3353 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3355 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3356 All fpr's from saved_fpr to fp31 are saved. */
3358 if (fdata
.saved_fpr
>= 0)
3361 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3363 /* If skip_prologue says floating-point registers were saved,
3364 but the current architecture has no floating-point registers,
3365 then that's strange. But we have no indices to even record
3366 the addresses under, so we just ignore it. */
3367 if (ppc_floating_point_unit_p (gdbarch
))
3368 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3370 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3375 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3376 All gpr's from saved_gpr to gpr31 are saved (except during the
3379 if (fdata
.saved_gpr
>= 0)
3382 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3383 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3385 if (fdata
.gpr_mask
& (1U << i
))
3386 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3387 gpr_addr
+= wordsize
;
3391 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3392 All vr's from saved_vr to vr31 are saved. */
3393 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3395 if (fdata
.saved_vr
>= 0)
3398 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3399 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3401 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3402 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3407 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3408 All vr's from saved_ev to ev31 are saved. ????? */
3409 if (tdep
->ppc_ev0_regnum
!= -1)
3411 if (fdata
.saved_ev
>= 0)
3414 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3415 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3417 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3419 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3420 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3421 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3426 /* If != 0, fdata.cr_offset is the offset from the frame that
3428 if (fdata
.cr_offset
!= 0)
3429 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3430 = cache
->base
+ fdata
.cr_offset
;
3432 /* If != 0, fdata.lr_offset is the offset from the frame that
3434 if (fdata
.lr_offset
!= 0)
3435 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3436 = cache
->base
+ fdata
.lr_offset
;
3437 else if (fdata
.lr_register
!= -1)
3438 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3439 /* The PC is found in the link register. */
3440 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3441 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3443 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3444 holds the VRSAVE. */
3445 if (fdata
.vrsave_offset
!= 0)
3446 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3447 = cache
->base
+ fdata
.vrsave_offset
;
3449 if (fdata
.alloca_reg
< 0)
3450 /* If no alloca register used, then fi->frame is the value of the
3451 %sp for this frame, and it is good enough. */
3453 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3456 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3463 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3464 struct frame_id
*this_id
)
3466 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3471 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3475 /* This marks the outermost frame. */
3476 if (info
->base
== 0)
3479 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3482 static struct value
*
3483 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3484 void **this_cache
, int regnum
)
3486 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3488 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3491 static const struct frame_unwind rs6000_frame_unwind
=
3494 default_frame_unwind_stop_reason
,
3495 rs6000_frame_this_id
,
3496 rs6000_frame_prev_register
,
3498 default_frame_sniffer
3501 /* Allocate and initialize a frame cache for an epilogue frame.
3502 SP is restored and prev-PC is stored in LR. */
3504 static struct rs6000_frame_cache
*
3505 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3507 struct rs6000_frame_cache
*cache
;
3508 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3512 return (struct rs6000_frame_cache
*) *this_cache
;
3514 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3515 (*this_cache
) = cache
;
3516 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3520 /* At this point the stack looks as if we just entered the
3521 function, and the return address is stored in LR. */
3524 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3525 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3528 cache
->initial_sp
= sp
;
3530 trad_frame_set_value (cache
->saved_regs
,
3531 gdbarch_pc_regnum (gdbarch
), lr
);
3533 CATCH (ex
, RETURN_MASK_ERROR
)
3535 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3536 throw_exception (ex
);
3543 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3544 Return the frame ID of an epilogue frame. */
3547 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3548 void **this_cache
, struct frame_id
*this_id
)
3551 struct rs6000_frame_cache
*info
=
3552 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3554 pc
= get_frame_func (this_frame
);
3555 if (info
->base
== 0)
3556 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3558 (*this_id
) = frame_id_build (info
->base
, pc
);
3561 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3562 Return the register value of REGNUM in previous frame. */
3564 static struct value
*
3565 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3566 void **this_cache
, int regnum
)
3568 struct rs6000_frame_cache
*info
=
3569 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3570 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3573 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3574 Check whether this an epilogue frame. */
3577 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3578 struct frame_info
*this_frame
,
3579 void **this_prologue_cache
)
3581 if (frame_relative_level (this_frame
) == 0)
3582 return rs6000_in_function_epilogue_frame_p (this_frame
,
3583 get_frame_arch (this_frame
),
3584 get_frame_pc (this_frame
));
3589 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3590 a function without debug information. */
3592 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3595 default_frame_unwind_stop_reason
,
3596 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3598 rs6000_epilogue_frame_sniffer
3603 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3605 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3607 return info
->initial_sp
;
3610 static const struct frame_base rs6000_frame_base
= {
3611 &rs6000_frame_unwind
,
3612 rs6000_frame_base_address
,
3613 rs6000_frame_base_address
,
3614 rs6000_frame_base_address
3617 static const struct frame_base
*
3618 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3620 return &rs6000_frame_base
;
3623 /* DWARF-2 frame support. Used to handle the detection of
3624 clobbered registers during function calls. */
3627 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3628 struct dwarf2_frame_state_reg
*reg
,
3629 struct frame_info
*this_frame
)
3631 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3633 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3634 non-volatile registers. We will use the same code for both. */
3636 /* Call-saved GP registers. */
3637 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3638 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3639 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3640 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3642 /* Call-clobbered GP registers. */
3643 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3644 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3645 || (regnum
== tdep
->ppc_gp0_regnum
))
3646 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3648 /* Deal with FP registers, if supported. */
3649 if (tdep
->ppc_fp0_regnum
>= 0)
3651 /* Call-saved FP registers. */
3652 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3653 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3654 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3656 /* Call-clobbered FP registers. */
3657 if ((regnum
>= tdep
->ppc_fp0_regnum
3658 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3659 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3662 /* Deal with ALTIVEC registers, if supported. */
3663 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3665 /* Call-saved Altivec registers. */
3666 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3667 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3668 || regnum
== tdep
->ppc_vrsave_regnum
)
3669 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3671 /* Call-clobbered Altivec registers. */
3672 if ((regnum
>= tdep
->ppc_vr0_regnum
3673 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3674 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3677 /* Handle PC register and Stack Pointer correctly. */
3678 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3679 reg
->how
= DWARF2_FRAME_REG_RA
;
3680 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3681 reg
->how
= DWARF2_FRAME_REG_CFA
;
3685 /* Return true if a .gnu_attributes section exists in BFD and it
3686 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3687 section exists in BFD and it indicates that SPE extensions are in
3688 use. Check the .gnu.attributes section first, as the binary might be
3689 compiled for SPE, but not actually using SPE instructions. */
3692 bfd_uses_spe_extensions (bfd
*abfd
)
3695 gdb_byte
*contents
= NULL
;
3705 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3706 could be using the SPE vector abi without actually using any spe
3707 bits whatsoever. But it's close enough for now. */
3708 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3709 Tag_GNU_Power_ABI_Vector
);
3710 if (vector_abi
== 3)
3714 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3718 size
= bfd_get_section_size (sect
);
3719 contents
= (gdb_byte
*) xmalloc (size
);
3720 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3726 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3732 char name[name_len rounded up to 4-byte alignment];
3733 char data[data_len];
3736 Technically, there's only supposed to be one such structure in a
3737 given apuinfo section, but the linker is not always vigilant about
3738 merging apuinfo sections from input files. Just go ahead and parse
3739 them all, exiting early when we discover the binary uses SPE
3742 It's not specified in what endianness the information in this
3743 section is stored. Assume that it's the endianness of the BFD. */
3747 unsigned int name_len
;
3748 unsigned int data_len
;
3751 /* If we can't read the first three fields, we're done. */
3755 name_len
= bfd_get_32 (abfd
, ptr
);
3756 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3757 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3758 type
= bfd_get_32 (abfd
, ptr
+ 8);
3761 /* The name must be "APUinfo\0". */
3763 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3767 /* The type must be 2. */
3771 /* The data is stored as a series of uint32. The upper half of
3772 each uint32 indicates the particular APU used and the lower
3773 half indicates the revision of that APU. We just care about
3776 /* Not 4-byte quantities. */
3782 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3783 unsigned int apu
= apuinfo
>> 16;
3787 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3789 if (apu
== 0x100 || apu
== 0x101)
3804 /* These are macros for parsing instruction fields (I.1.6.28) */
3806 #define PPC_FIELD(value, from, len) \
3807 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3808 #define PPC_SEXT(v, bs) \
3809 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3810 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3811 - ((CORE_ADDR) 1 << ((bs) - 1)))
3812 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3813 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3814 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3815 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3816 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3817 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3818 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3819 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3820 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3821 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3822 | (PPC_FIELD (insn, 16, 5) << 5))
3823 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3824 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3825 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3826 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3827 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3828 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3829 #define PPC_OE(insn) PPC_BIT (insn, 21)
3830 #define PPC_RC(insn) PPC_BIT (insn, 31)
3831 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3832 #define PPC_LK(insn) PPC_BIT (insn, 31)
3833 #define PPC_TX(insn) PPC_BIT (insn, 31)
3834 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3836 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3837 #define PPC_XER_NB(xer) (xer & 0x7f)
3839 /* Record Vector-Scalar Registers.
3840 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3841 Otherwise, it's just a VR register. Record them accordingly. */
3844 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3846 if (vsr
< 0 || vsr
>= 64)
3851 if (tdep
->ppc_vr0_regnum
>= 0)
3852 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3856 if (tdep
->ppc_fp0_regnum
>= 0)
3857 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3858 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3859 record_full_arch_list_add_reg (regcache
,
3860 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3866 /* Parse and record instructions primary opcode-4 at ADDR.
3867 Return 0 if successful. */
3870 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3871 CORE_ADDR addr
, uint32_t insn
)
3873 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3874 int ext
= PPC_FIELD (insn
, 21, 11);
3875 int vra
= PPC_FIELD (insn
, 11, 5);
3879 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3880 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3881 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3882 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3883 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3885 case 42: /* Vector Select */
3886 case 43: /* Vector Permute */
3887 case 59: /* Vector Permute Right-indexed */
3888 case 44: /* Vector Shift Left Double by Octet Immediate */
3889 case 45: /* Vector Permute and Exclusive-OR */
3890 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3891 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3892 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3893 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3894 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3895 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3896 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3897 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3898 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3899 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3900 case 46: /* Vector Multiply-Add Single-Precision */
3901 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3902 record_full_arch_list_add_reg (regcache
,
3903 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3906 case 48: /* Multiply-Add High Doubleword */
3907 case 49: /* Multiply-Add High Doubleword Unsigned */
3908 case 51: /* Multiply-Add Low Doubleword */
3909 record_full_arch_list_add_reg (regcache
,
3910 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3914 switch ((ext
& 0x1ff))
3917 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3918 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3919 && vra
!= 4 /* Decimal Convert To Zoned */
3920 && vra
!= 5 /* Decimal Convert To National */
3921 && vra
!= 6 /* Decimal Convert From Zoned */
3922 && vra
!= 7 /* Decimal Convert From National */
3923 && vra
!= 31) /* Decimal Set Sign */
3925 /* 5.16 Decimal Integer Arithmetic Instructions */
3926 case 1: /* Decimal Add Modulo */
3927 case 65: /* Decimal Subtract Modulo */
3929 case 193: /* Decimal Shift */
3930 case 129: /* Decimal Unsigned Shift */
3931 case 449: /* Decimal Shift and Round */
3933 case 257: /* Decimal Truncate */
3934 case 321: /* Decimal Unsigned Truncate */
3936 /* Bit-21 should be set. */
3937 if (!PPC_BIT (insn
, 21))
3940 record_full_arch_list_add_reg (regcache
,
3941 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3942 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3946 /* Bit-21 is used for RC */
3947 switch (ext
& 0x3ff)
3949 case 6: /* Vector Compare Equal To Unsigned Byte */
3950 case 70: /* Vector Compare Equal To Unsigned Halfword */
3951 case 134: /* Vector Compare Equal To Unsigned Word */
3952 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3953 case 774: /* Vector Compare Greater Than Signed Byte */
3954 case 838: /* Vector Compare Greater Than Signed Halfword */
3955 case 902: /* Vector Compare Greater Than Signed Word */
3956 case 967: /* Vector Compare Greater Than Signed Doubleword */
3957 case 518: /* Vector Compare Greater Than Unsigned Byte */
3958 case 646: /* Vector Compare Greater Than Unsigned Word */
3959 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3960 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3961 case 966: /* Vector Compare Bounds Single-Precision */
3962 case 198: /* Vector Compare Equal To Single-Precision */
3963 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3964 case 710: /* Vector Compare Greater Than Single-Precision */
3965 case 7: /* Vector Compare Not Equal Byte */
3966 case 71: /* Vector Compare Not Equal Halfword */
3967 case 135: /* Vector Compare Not Equal Word */
3968 case 263: /* Vector Compare Not Equal or Zero Byte */
3969 case 327: /* Vector Compare Not Equal or Zero Halfword */
3970 case 391: /* Vector Compare Not Equal or Zero Word */
3972 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3973 record_full_arch_list_add_reg (regcache
,
3974 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3982 case 0: /* Vector Count Leading Zero Least-Significant Bits
3984 case 1: /* Vector Count Trailing Zero Least-Significant Bits
3986 record_full_arch_list_add_reg (regcache
,
3987 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3990 case 6: /* Vector Negate Word */
3991 case 7: /* Vector Negate Doubleword */
3992 case 8: /* Vector Parity Byte Word */
3993 case 9: /* Vector Parity Byte Doubleword */
3994 case 10: /* Vector Parity Byte Quadword */
3995 case 16: /* Vector Extend Sign Byte To Word */
3996 case 17: /* Vector Extend Sign Halfword To Word */
3997 case 24: /* Vector Extend Sign Byte To Doubleword */
3998 case 25: /* Vector Extend Sign Halfword To Doubleword */
3999 case 26: /* Vector Extend Sign Word To Doubleword */
4000 case 28: /* Vector Count Trailing Zeros Byte */
4001 case 29: /* Vector Count Trailing Zeros Halfword */
4002 case 30: /* Vector Count Trailing Zeros Word */
4003 case 31: /* Vector Count Trailing Zeros Doubleword */
4004 record_full_arch_list_add_reg (regcache
,
4005 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4012 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4013 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4014 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4015 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4016 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4017 case 462: /* Vector Pack Signed Word Signed Saturate */
4018 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4019 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4020 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4021 case 512: /* Vector Add Unsigned Byte Saturate */
4022 case 576: /* Vector Add Unsigned Halfword Saturate */
4023 case 640: /* Vector Add Unsigned Word Saturate */
4024 case 768: /* Vector Add Signed Byte Saturate */
4025 case 832: /* Vector Add Signed Halfword Saturate */
4026 case 896: /* Vector Add Signed Word Saturate */
4027 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4028 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4029 case 1664: /* Vector Subtract Unsigned Word Saturate */
4030 case 1792: /* Vector Subtract Signed Byte Saturate */
4031 case 1856: /* Vector Subtract Signed Halfword Saturate */
4032 case 1920: /* Vector Subtract Signed Word Saturate */
4034 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4035 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4036 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4037 case 1672: /* Vector Sum across Half Signed Word Saturate */
4038 case 1928: /* Vector Sum across Signed Word Saturate */
4039 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4040 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4041 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4043 case 12: /* Vector Merge High Byte */
4044 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4045 case 76: /* Vector Merge High Halfword */
4046 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4047 case 140: /* Vector Merge High Word */
4048 case 268: /* Vector Merge Low Byte */
4049 case 332: /* Vector Merge Low Halfword */
4050 case 396: /* Vector Merge Low Word */
4051 case 526: /* Vector Unpack High Signed Byte */
4052 case 590: /* Vector Unpack High Signed Halfword */
4053 case 654: /* Vector Unpack Low Signed Byte */
4054 case 718: /* Vector Unpack Low Signed Halfword */
4055 case 782: /* Vector Pack Pixel */
4056 case 846: /* Vector Unpack High Pixel */
4057 case 974: /* Vector Unpack Low Pixel */
4058 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4059 case 1614: /* Vector Unpack High Signed Word */
4060 case 1676: /* Vector Merge Odd Word */
4061 case 1742: /* Vector Unpack Low Signed Word */
4062 case 1932: /* Vector Merge Even Word */
4063 case 524: /* Vector Splat Byte */
4064 case 588: /* Vector Splat Halfword */
4065 case 652: /* Vector Splat Word */
4066 case 780: /* Vector Splat Immediate Signed Byte */
4067 case 844: /* Vector Splat Immediate Signed Halfword */
4068 case 908: /* Vector Splat Immediate Signed Word */
4069 case 452: /* Vector Shift Left */
4070 case 708: /* Vector Shift Right */
4071 case 1036: /* Vector Shift Left by Octet */
4072 case 1100: /* Vector Shift Right by Octet */
4073 case 0: /* Vector Add Unsigned Byte Modulo */
4074 case 64: /* Vector Add Unsigned Halfword Modulo */
4075 case 128: /* Vector Add Unsigned Word Modulo */
4076 case 192: /* Vector Add Unsigned Doubleword Modulo */
4077 case 256: /* Vector Add Unsigned Quadword Modulo */
4078 case 320: /* Vector Add & write Carry Unsigned Quadword */
4079 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4080 case 8: /* Vector Multiply Odd Unsigned Byte */
4081 case 72: /* Vector Multiply Odd Unsigned Halfword */
4082 case 136: /* Vector Multiply Odd Unsigned Word */
4083 case 264: /* Vector Multiply Odd Signed Byte */
4084 case 328: /* Vector Multiply Odd Signed Halfword */
4085 case 392: /* Vector Multiply Odd Signed Word */
4086 case 520: /* Vector Multiply Even Unsigned Byte */
4087 case 584: /* Vector Multiply Even Unsigned Halfword */
4088 case 648: /* Vector Multiply Even Unsigned Word */
4089 case 776: /* Vector Multiply Even Signed Byte */
4090 case 840: /* Vector Multiply Even Signed Halfword */
4091 case 904: /* Vector Multiply Even Signed Word */
4092 case 137: /* Vector Multiply Unsigned Word Modulo */
4093 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4094 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4095 case 1152: /* Vector Subtract Unsigned Word Modulo */
4096 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4097 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4098 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4099 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4100 case 1282: /* Vector Average Signed Byte */
4101 case 1346: /* Vector Average Signed Halfword */
4102 case 1410: /* Vector Average Signed Word */
4103 case 1026: /* Vector Average Unsigned Byte */
4104 case 1090: /* Vector Average Unsigned Halfword */
4105 case 1154: /* Vector Average Unsigned Word */
4106 case 258: /* Vector Maximum Signed Byte */
4107 case 322: /* Vector Maximum Signed Halfword */
4108 case 386: /* Vector Maximum Signed Word */
4109 case 450: /* Vector Maximum Signed Doubleword */
4110 case 2: /* Vector Maximum Unsigned Byte */
4111 case 66: /* Vector Maximum Unsigned Halfword */
4112 case 130: /* Vector Maximum Unsigned Word */
4113 case 194: /* Vector Maximum Unsigned Doubleword */
4114 case 770: /* Vector Minimum Signed Byte */
4115 case 834: /* Vector Minimum Signed Halfword */
4116 case 898: /* Vector Minimum Signed Word */
4117 case 962: /* Vector Minimum Signed Doubleword */
4118 case 514: /* Vector Minimum Unsigned Byte */
4119 case 578: /* Vector Minimum Unsigned Halfword */
4120 case 642: /* Vector Minimum Unsigned Word */
4121 case 706: /* Vector Minimum Unsigned Doubleword */
4122 case 1028: /* Vector Logical AND */
4123 case 1668: /* Vector Logical Equivalent */
4124 case 1092: /* Vector Logical AND with Complement */
4125 case 1412: /* Vector Logical NAND */
4126 case 1348: /* Vector Logical OR with Complement */
4127 case 1156: /* Vector Logical OR */
4128 case 1284: /* Vector Logical NOR */
4129 case 1220: /* Vector Logical XOR */
4130 case 4: /* Vector Rotate Left Byte */
4131 case 132: /* Vector Rotate Left Word VX-form */
4132 case 68: /* Vector Rotate Left Halfword */
4133 case 196: /* Vector Rotate Left Doubleword */
4134 case 260: /* Vector Shift Left Byte */
4135 case 388: /* Vector Shift Left Word */
4136 case 324: /* Vector Shift Left Halfword */
4137 case 1476: /* Vector Shift Left Doubleword */
4138 case 516: /* Vector Shift Right Byte */
4139 case 644: /* Vector Shift Right Word */
4140 case 580: /* Vector Shift Right Halfword */
4141 case 1732: /* Vector Shift Right Doubleword */
4142 case 772: /* Vector Shift Right Algebraic Byte */
4143 case 900: /* Vector Shift Right Algebraic Word */
4144 case 836: /* Vector Shift Right Algebraic Halfword */
4145 case 964: /* Vector Shift Right Algebraic Doubleword */
4146 case 10: /* Vector Add Single-Precision */
4147 case 74: /* Vector Subtract Single-Precision */
4148 case 1034: /* Vector Maximum Single-Precision */
4149 case 1098: /* Vector Minimum Single-Precision */
4150 case 842: /* Vector Convert From Signed Fixed-Point Word */
4151 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4152 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4153 case 522: /* Vector Round to Single-Precision Integer Nearest */
4154 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4155 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4156 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4157 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4158 case 266: /* Vector Reciprocal Estimate Single-Precision */
4159 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4160 case 1288: /* Vector AES Cipher */
4161 case 1289: /* Vector AES Cipher Last */
4162 case 1352: /* Vector AES Inverse Cipher */
4163 case 1353: /* Vector AES Inverse Cipher Last */
4164 case 1480: /* Vector AES SubBytes */
4165 case 1730: /* Vector SHA-512 Sigma Doubleword */
4166 case 1666: /* Vector SHA-256 Sigma Word */
4167 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4168 case 1160: /* Vector Polynomial Multiply-Sum Word */
4169 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4170 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4171 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4172 case 1794: /* Vector Count Leading Zeros Byte */
4173 case 1858: /* Vector Count Leading Zeros Halfword */
4174 case 1922: /* Vector Count Leading Zeros Word */
4175 case 1986: /* Vector Count Leading Zeros Doubleword */
4176 case 1795: /* Vector Population Count Byte */
4177 case 1859: /* Vector Population Count Halfword */
4178 case 1923: /* Vector Population Count Word */
4179 case 1987: /* Vector Population Count Doubleword */
4180 case 1356: /* Vector Bit Permute Quadword */
4181 case 1484: /* Vector Bit Permute Doubleword */
4182 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4183 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4185 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4186 case 65: /* Vector Multiply-by-10 Extended & write Carry
4187 Unsigned Quadword */
4188 case 1027: /* Vector Absolute Difference Unsigned Byte */
4189 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4190 case 1155: /* Vector Absolute Difference Unsigned Word */
4191 case 1796: /* Vector Shift Right Variable */
4192 case 1860: /* Vector Shift Left Variable */
4193 case 133: /* Vector Rotate Left Word then Mask Insert */
4194 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4195 case 389: /* Vector Rotate Left Word then AND with Mask */
4196 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4197 case 525: /* Vector Extract Unsigned Byte */
4198 case 589: /* Vector Extract Unsigned Halfword */
4199 case 653: /* Vector Extract Unsigned Word */
4200 case 717: /* Vector Extract Doubleword */
4201 case 781: /* Vector Insert Byte */
4202 case 845: /* Vector Insert Halfword */
4203 case 909: /* Vector Insert Word */
4204 case 973: /* Vector Insert Doubleword */
4205 record_full_arch_list_add_reg (regcache
,
4206 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4209 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4210 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4211 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4212 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4213 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4214 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4215 record_full_arch_list_add_reg (regcache
,
4216 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4219 case 1604: /* Move To Vector Status and Control Register */
4220 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4222 case 1540: /* Move From Vector Status and Control Register */
4223 record_full_arch_list_add_reg (regcache
,
4224 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4226 case 833: /* Decimal Copy Sign */
4227 record_full_arch_list_add_reg (regcache
,
4228 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4229 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4233 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4234 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4238 /* Parse and record instructions of primary opcode-19 at ADDR.
4239 Return 0 if successful. */
4242 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4243 CORE_ADDR addr
, uint32_t insn
)
4245 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4246 int ext
= PPC_EXTOP (insn
);
4248 switch (ext
& 0x01f)
4250 case 2: /* Add PC Immediate Shifted */
4251 record_full_arch_list_add_reg (regcache
,
4252 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4258 case 0: /* Move Condition Register Field */
4259 case 33: /* Condition Register NOR */
4260 case 129: /* Condition Register AND with Complement */
4261 case 193: /* Condition Register XOR */
4262 case 225: /* Condition Register NAND */
4263 case 257: /* Condition Register AND */
4264 case 289: /* Condition Register Equivalent */
4265 case 417: /* Condition Register OR with Complement */
4266 case 449: /* Condition Register OR */
4267 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4270 case 16: /* Branch Conditional */
4271 case 560: /* Branch Conditional to Branch Target Address Register */
4272 if ((PPC_BO (insn
) & 0x4) == 0)
4273 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4275 case 528: /* Branch Conditional to Count Register */
4277 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4280 case 150: /* Instruction Synchronize */
4285 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4286 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4290 /* Parse and record instructions of primary opcode-31 at ADDR.
4291 Return 0 if successful. */
4294 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4295 CORE_ADDR addr
, uint32_t insn
)
4297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4298 int ext
= PPC_EXTOP (insn
);
4300 CORE_ADDR at_dcsz
, ea
= 0;
4301 ULONGEST rb
, ra
, xer
;
4304 /* These instructions have OE bit. */
4305 switch (ext
& 0x1ff)
4307 /* These write RT and XER. Update CR if RC is set. */
4308 case 8: /* Subtract from carrying */
4309 case 10: /* Add carrying */
4310 case 136: /* Subtract from extended */
4311 case 138: /* Add extended */
4312 case 200: /* Subtract from zero extended */
4313 case 202: /* Add to zero extended */
4314 case 232: /* Subtract from minus one extended */
4315 case 234: /* Add to minus one extended */
4316 /* CA is always altered, but SO/OV are only altered when OE=1.
4317 In any case, XER is always altered. */
4318 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4320 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4321 record_full_arch_list_add_reg (regcache
,
4322 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4325 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4326 case 40: /* Subtract from */
4327 case 104: /* Negate */
4328 case 233: /* Multiply low doubleword */
4329 case 235: /* Multiply low word */
4331 case 393: /* Divide Doubleword Extended Unsigned */
4332 case 395: /* Divide Word Extended Unsigned */
4333 case 425: /* Divide Doubleword Extended */
4334 case 427: /* Divide Word Extended */
4335 case 457: /* Divide Doubleword Unsigned */
4336 case 459: /* Divide Word Unsigned */
4337 case 489: /* Divide Doubleword */
4338 case 491: /* Divide Word */
4340 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4342 case 9: /* Multiply High Doubleword Unsigned */
4343 case 11: /* Multiply High Word Unsigned */
4344 case 73: /* Multiply High Doubleword */
4345 case 75: /* Multiply High Word */
4347 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4348 record_full_arch_list_add_reg (regcache
,
4349 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4353 if ((ext
& 0x1f) == 15)
4355 /* Integer Select. bit[16:20] is used for BC. */
4356 record_full_arch_list_add_reg (regcache
,
4357 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4361 if ((ext
& 0xff) == 170)
4363 /* Add Extended using alternate carry bits */
4364 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4365 record_full_arch_list_add_reg (regcache
,
4366 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4372 case 78: /* Determine Leftmost Zero Byte */
4374 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4375 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4376 record_full_arch_list_add_reg (regcache
,
4377 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4380 /* These only write RT. */
4381 case 19: /* Move from condition register */
4382 /* Move From One Condition Register Field */
4383 case 74: /* Add and Generate Sixes */
4384 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4385 case 302: /* Move From Branch History Rolling Buffer */
4386 case 339: /* Move From Special Purpose Register */
4387 case 371: /* Move From Time Base [Phased-Out] */
4388 case 309: /* Load Doubleword Monitored Indexed */
4389 case 128: /* Set Boolean */
4390 case 755: /* Deliver A Random Number */
4391 record_full_arch_list_add_reg (regcache
,
4392 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4395 /* These only write to RA. */
4396 case 51: /* Move From VSR Doubleword */
4397 case 115: /* Move From VSR Word and Zero */
4398 case 122: /* Population count bytes */
4399 case 378: /* Population count words */
4400 case 506: /* Population count doublewords */
4401 case 154: /* Parity Word */
4402 case 186: /* Parity Doubleword */
4403 case 252: /* Bit Permute Doubleword */
4404 case 282: /* Convert Declets To Binary Coded Decimal */
4405 case 314: /* Convert Binary Coded Decimal To Declets */
4406 case 508: /* Compare bytes */
4407 case 307: /* Move From VSR Lower Doubleword */
4408 record_full_arch_list_add_reg (regcache
,
4409 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4412 /* These write CR and optional RA. */
4413 case 792: /* Shift Right Algebraic Word */
4414 case 794: /* Shift Right Algebraic Doubleword */
4415 case 824: /* Shift Right Algebraic Word Immediate */
4416 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4417 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4418 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4419 record_full_arch_list_add_reg (regcache
,
4420 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4422 case 0: /* Compare */
4423 case 32: /* Compare logical */
4424 case 144: /* Move To Condition Register Fields */
4425 /* Move To One Condition Register Field */
4426 case 192: /* Compare Ranged Byte */
4427 case 224: /* Compare Equal Byte */
4428 case 576: /* Move XER to CR Extended */
4429 case 902: /* Paste (should always fail due to single-stepping and
4430 the memory location might not be accessible, so
4432 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4435 /* These write to RT. Update RA if 'update indexed.' */
4436 case 53: /* Load Doubleword with Update Indexed */
4437 case 119: /* Load Byte and Zero with Update Indexed */
4438 case 311: /* Load Halfword and Zero with Update Indexed */
4439 case 55: /* Load Word and Zero with Update Indexed */
4440 case 375: /* Load Halfword Algebraic with Update Indexed */
4441 case 373: /* Load Word Algebraic with Update Indexed */
4442 record_full_arch_list_add_reg (regcache
,
4443 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4445 case 21: /* Load Doubleword Indexed */
4446 case 52: /* Load Byte And Reserve Indexed */
4447 case 116: /* Load Halfword And Reserve Indexed */
4448 case 20: /* Load Word And Reserve Indexed */
4449 case 84: /* Load Doubleword And Reserve Indexed */
4450 case 87: /* Load Byte and Zero Indexed */
4451 case 279: /* Load Halfword and Zero Indexed */
4452 case 23: /* Load Word and Zero Indexed */
4453 case 343: /* Load Halfword Algebraic Indexed */
4454 case 341: /* Load Word Algebraic Indexed */
4455 case 790: /* Load Halfword Byte-Reverse Indexed */
4456 case 534: /* Load Word Byte-Reverse Indexed */
4457 case 532: /* Load Doubleword Byte-Reverse Indexed */
4458 case 582: /* Load Word Atomic */
4459 case 614: /* Load Doubleword Atomic */
4460 case 265: /* Modulo Unsigned Doubleword */
4461 case 777: /* Modulo Signed Doubleword */
4462 case 267: /* Modulo Unsigned Word */
4463 case 779: /* Modulo Signed Word */
4464 record_full_arch_list_add_reg (regcache
,
4465 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4468 case 597: /* Load String Word Immediate */
4469 case 533: /* Load String Word Indexed */
4478 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4479 nr
= PPC_XER_NB (xer
);
4484 /* If n=0, the contents of register RT are undefined. */
4488 for (i
= 0; i
< nr
; i
++)
4489 record_full_arch_list_add_reg (regcache
,
4490 tdep
->ppc_gp0_regnum
4491 + ((PPC_RT (insn
) + i
) & 0x1f));
4494 case 276: /* Load Quadword And Reserve Indexed */
4495 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4496 record_full_arch_list_add_reg (regcache
, tmp
);
4497 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4500 /* These write VRT. */
4501 case 6: /* Load Vector for Shift Left Indexed */
4502 case 38: /* Load Vector for Shift Right Indexed */
4503 case 7: /* Load Vector Element Byte Indexed */
4504 case 39: /* Load Vector Element Halfword Indexed */
4505 case 71: /* Load Vector Element Word Indexed */
4506 case 103: /* Load Vector Indexed */
4507 case 359: /* Load Vector Indexed LRU */
4508 record_full_arch_list_add_reg (regcache
,
4509 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4512 /* These write FRT. Update RA if 'update indexed.' */
4513 case 567: /* Load Floating-Point Single with Update Indexed */
4514 case 631: /* Load Floating-Point Double with Update Indexed */
4515 record_full_arch_list_add_reg (regcache
,
4516 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4518 case 535: /* Load Floating-Point Single Indexed */
4519 case 599: /* Load Floating-Point Double Indexed */
4520 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4521 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4522 record_full_arch_list_add_reg (regcache
,
4523 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4526 case 791: /* Load Floating-Point Double Pair Indexed */
4527 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4528 record_full_arch_list_add_reg (regcache
, tmp
);
4529 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4532 case 179: /* Move To VSR Doubleword */
4533 case 211: /* Move To VSR Word Algebraic */
4534 case 243: /* Move To VSR Word and Zero */
4535 case 588: /* Load VSX Scalar Doubleword Indexed */
4536 case 524: /* Load VSX Scalar Single-Precision Indexed */
4537 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4538 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4539 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4540 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4541 case 780: /* Load VSX Vector Word*4 Indexed */
4542 case 268: /* Load VSX Vector Indexed */
4543 case 364: /* Load VSX Vector Word & Splat Indexed */
4544 case 812: /* Load VSX Vector Halfword*8 Indexed */
4545 case 876: /* Load VSX Vector Byte*16 Indexed */
4546 case 269: /* Load VSX Vector with Length */
4547 case 301: /* Load VSX Vector Left-justified with Length */
4548 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4549 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4550 case 403: /* Move To VSR Word & Splat */
4551 case 435: /* Move To VSR Double Doubleword */
4552 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4555 /* These write RA. Update CR if RC is set. */
4556 case 24: /* Shift Left Word */
4557 case 26: /* Count Leading Zeros Word */
4558 case 27: /* Shift Left Doubleword */
4560 case 58: /* Count Leading Zeros Doubleword */
4561 case 60: /* AND with Complement */
4563 case 284: /* Equivalent */
4565 case 476: /* NAND */
4566 case 412: /* OR with Complement */
4568 case 536: /* Shift Right Word */
4569 case 539: /* Shift Right Doubleword */
4570 case 922: /* Extend Sign Halfword */
4571 case 954: /* Extend Sign Byte */
4572 case 986: /* Extend Sign Word */
4573 case 538: /* Count Trailing Zeros Word */
4574 case 570: /* Count Trailing Zeros Doubleword */
4575 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4576 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4578 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4579 record_full_arch_list_add_reg (regcache
,
4580 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4584 case 181: /* Store Doubleword with Update Indexed */
4585 case 183: /* Store Word with Update Indexed */
4586 case 247: /* Store Byte with Update Indexed */
4587 case 439: /* Store Half Word with Update Indexed */
4588 case 695: /* Store Floating-Point Single with Update Indexed */
4589 case 759: /* Store Floating-Point Double with Update Indexed */
4590 record_full_arch_list_add_reg (regcache
,
4591 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4593 case 135: /* Store Vector Element Byte Indexed */
4594 case 167: /* Store Vector Element Halfword Indexed */
4595 case 199: /* Store Vector Element Word Indexed */
4596 case 231: /* Store Vector Indexed */
4597 case 487: /* Store Vector Indexed LRU */
4598 case 716: /* Store VSX Scalar Doubleword Indexed */
4599 case 140: /* Store VSX Scalar as Integer Word Indexed */
4600 case 652: /* Store VSX Scalar Single-Precision Indexed */
4601 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4602 case 908: /* Store VSX Vector Word*4 Indexed */
4603 case 149: /* Store Doubleword Indexed */
4604 case 151: /* Store Word Indexed */
4605 case 215: /* Store Byte Indexed */
4606 case 407: /* Store Half Word Indexed */
4607 case 694: /* Store Byte Conditional Indexed */
4608 case 726: /* Store Halfword Conditional Indexed */
4609 case 150: /* Store Word Conditional Indexed */
4610 case 214: /* Store Doubleword Conditional Indexed */
4611 case 182: /* Store Quadword Conditional Indexed */
4612 case 662: /* Store Word Byte-Reverse Indexed */
4613 case 918: /* Store Halfword Byte-Reverse Indexed */
4614 case 660: /* Store Doubleword Byte-Reverse Indexed */
4615 case 663: /* Store Floating-Point Single Indexed */
4616 case 727: /* Store Floating-Point Double Indexed */
4617 case 919: /* Store Floating-Point Double Pair Indexed */
4618 case 983: /* Store Floating-Point as Integer Word Indexed */
4619 case 396: /* Store VSX Vector Indexed */
4620 case 940: /* Store VSX Vector Halfword*8 Indexed */
4621 case 1004: /* Store VSX Vector Byte*16 Indexed */
4622 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4623 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4624 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4625 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4628 if (PPC_RA (insn
) != 0)
4629 regcache_raw_read_unsigned (regcache
,
4630 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4631 regcache_raw_read_unsigned (regcache
,
4632 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4637 case 183: /* Store Word with Update Indexed */
4638 case 199: /* Store Vector Element Word Indexed */
4639 case 140: /* Store VSX Scalar as Integer Word Indexed */
4640 case 652: /* Store VSX Scalar Single-Precision Indexed */
4641 case 151: /* Store Word Indexed */
4642 case 150: /* Store Word Conditional Indexed */
4643 case 662: /* Store Word Byte-Reverse Indexed */
4644 case 663: /* Store Floating-Point Single Indexed */
4645 case 695: /* Store Floating-Point Single with Update Indexed */
4646 case 983: /* Store Floating-Point as Integer Word Indexed */
4649 case 247: /* Store Byte with Update Indexed */
4650 case 135: /* Store Vector Element Byte Indexed */
4651 case 215: /* Store Byte Indexed */
4652 case 694: /* Store Byte Conditional Indexed */
4653 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4656 case 439: /* Store Halfword with Update Indexed */
4657 case 167: /* Store Vector Element Halfword Indexed */
4658 case 407: /* Store Halfword Indexed */
4659 case 726: /* Store Halfword Conditional Indexed */
4660 case 918: /* Store Halfword Byte-Reverse Indexed */
4661 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4664 case 181: /* Store Doubleword with Update Indexed */
4665 case 716: /* Store VSX Scalar Doubleword Indexed */
4666 case 149: /* Store Doubleword Indexed */
4667 case 214: /* Store Doubleword Conditional Indexed */
4668 case 660: /* Store Doubleword Byte-Reverse Indexed */
4669 case 727: /* Store Floating-Point Double Indexed */
4670 case 759: /* Store Floating-Point Double with Update Indexed */
4673 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4674 case 908: /* Store VSX Vector Word*4 Indexed */
4675 case 182: /* Store Quadword Conditional Indexed */
4676 case 231: /* Store Vector Indexed */
4677 case 487: /* Store Vector Indexed LRU */
4678 case 919: /* Store Floating-Point Double Pair Indexed */
4679 case 396: /* Store VSX Vector Indexed */
4680 case 940: /* Store VSX Vector Halfword*8 Indexed */
4681 case 1004: /* Store VSX Vector Byte*16 Indexed */
4688 /* Align address for Store Vector instructions. */
4691 case 167: /* Store Vector Element Halfword Indexed */
4692 addr
= addr
& ~0x1ULL
;
4695 case 199: /* Store Vector Element Word Indexed */
4696 addr
= addr
& ~0x3ULL
;
4699 case 231: /* Store Vector Indexed */
4700 case 487: /* Store Vector Indexed LRU */
4701 addr
= addr
& ~0xfULL
;
4705 record_full_arch_list_add_mem (addr
, size
);
4708 case 397: /* Store VSX Vector with Length */
4709 case 429: /* Store VSX Vector Left-justified with Length */
4711 if (PPC_RA (insn
) != 0)
4712 regcache_raw_read_unsigned (regcache
,
4713 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4715 regcache_raw_read_unsigned (regcache
,
4716 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4717 /* Store up to 16 bytes. */
4718 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4720 record_full_arch_list_add_mem (ea
, nb
);
4723 case 710: /* Store Word Atomic */
4724 case 742: /* Store Doubleword Atomic */
4726 if (PPC_RA (insn
) != 0)
4727 regcache_raw_read_unsigned (regcache
,
4728 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4732 case 710: /* Store Word Atomic */
4735 case 742: /* Store Doubleword Atomic */
4741 record_full_arch_list_add_mem (ea
, size
);
4744 case 725: /* Store String Word Immediate */
4746 if (PPC_RA (insn
) != 0)
4747 regcache_raw_read_unsigned (regcache
,
4748 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4755 record_full_arch_list_add_mem (ea
, nb
);
4759 case 661: /* Store String Word Indexed */
4761 if (PPC_RA (insn
) != 0)
4762 regcache_raw_read_unsigned (regcache
,
4763 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4766 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4767 nb
= PPC_XER_NB (xer
);
4771 regcache_raw_read_unsigned (regcache
,
4772 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4775 record_full_arch_list_add_mem (ea
, nb
);
4780 case 467: /* Move To Special Purpose Register */
4781 switch (PPC_SPR (insn
))
4784 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4787 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4790 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4792 case 256: /* VRSAVE */
4793 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4799 case 147: /* Move To Split Little Endian */
4800 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4803 case 512: /* Move to Condition Register from XER */
4804 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4805 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4808 case 4: /* Trap Word */
4809 case 68: /* Trap Doubleword */
4810 case 430: /* Clear BHRB */
4811 case 598: /* Synchronize */
4812 case 62: /* Wait for Interrupt */
4814 case 22: /* Instruction Cache Block Touch */
4815 case 854: /* Enforce In-order Execution of I/O */
4816 case 246: /* Data Cache Block Touch for Store */
4817 case 54: /* Data Cache Block Store */
4818 case 86: /* Data Cache Block Flush */
4819 case 278: /* Data Cache Block Touch */
4820 case 758: /* Data Cache Block Allocate */
4821 case 982: /* Instruction Cache Block Invalidate */
4822 case 774: /* Copy */
4823 case 838: /* CP_Abort */
4826 case 654: /* Transaction Begin */
4827 case 686: /* Transaction End */
4828 case 750: /* Transaction Suspend or Resume */
4829 case 782: /* Transaction Abort Word Conditional */
4830 case 814: /* Transaction Abort Doubleword Conditional */
4831 case 846: /* Transaction Abort Word Conditional Immediate */
4832 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4833 case 910: /* Transaction Abort */
4834 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4836 case 718: /* Transaction Check */
4837 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4840 case 1014: /* Data Cache Block set to Zero */
4841 if (target_auxv_search (¤t_target
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4843 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4846 if (PPC_RA (insn
) != 0)
4847 regcache_raw_read_unsigned (regcache
,
4848 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4849 regcache_raw_read_unsigned (regcache
,
4850 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4851 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4852 record_full_arch_list_add_mem (ea
, at_dcsz
);
4857 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4858 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4862 /* Parse and record instructions of primary opcode-59 at ADDR.
4863 Return 0 if successful. */
4866 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4867 CORE_ADDR addr
, uint32_t insn
)
4869 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4870 int ext
= PPC_EXTOP (insn
);
4874 case 18: /* Floating Divide */
4875 case 20: /* Floating Subtract */
4876 case 21: /* Floating Add */
4877 case 22: /* Floating Square Root */
4878 case 24: /* Floating Reciprocal Estimate */
4879 case 25: /* Floating Multiply */
4880 case 26: /* Floating Reciprocal Square Root Estimate */
4881 case 28: /* Floating Multiply-Subtract */
4882 case 29: /* Floating Multiply-Add */
4883 case 30: /* Floating Negative Multiply-Subtract */
4884 case 31: /* Floating Negative Multiply-Add */
4885 record_full_arch_list_add_reg (regcache
,
4886 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4888 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4889 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4896 case 2: /* DFP Add */
4897 case 3: /* DFP Quantize */
4898 case 34: /* DFP Multiply */
4899 case 35: /* DFP Reround */
4900 case 67: /* DFP Quantize Immediate */
4901 case 99: /* DFP Round To FP Integer With Inexact */
4902 case 227: /* DFP Round To FP Integer Without Inexact */
4903 case 258: /* DFP Convert To DFP Long! */
4904 case 290: /* DFP Convert To Fixed */
4905 case 514: /* DFP Subtract */
4906 case 546: /* DFP Divide */
4907 case 770: /* DFP Round To DFP Short! */
4908 case 802: /* DFP Convert From Fixed */
4909 case 834: /* DFP Encode BCD To DPD */
4911 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4912 record_full_arch_list_add_reg (regcache
,
4913 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4914 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4917 case 130: /* DFP Compare Ordered */
4918 case 162: /* DFP Test Exponent */
4919 case 194: /* DFP Test Data Class */
4920 case 226: /* DFP Test Data Group */
4921 case 642: /* DFP Compare Unordered */
4922 case 674: /* DFP Test Significance */
4923 case 675: /* DFP Test Significance Immediate */
4924 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4925 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4928 case 66: /* DFP Shift Significand Left Immediate */
4929 case 98: /* DFP Shift Significand Right Immediate */
4930 case 322: /* DFP Decode DPD To BCD */
4931 case 354: /* DFP Extract Biased Exponent */
4932 case 866: /* DFP Insert Biased Exponent */
4933 record_full_arch_list_add_reg (regcache
,
4934 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4936 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4939 case 846: /* Floating Convert From Integer Doubleword Single */
4940 case 974: /* Floating Convert From Integer Doubleword Unsigned
4942 record_full_arch_list_add_reg (regcache
,
4943 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4945 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4946 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4951 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4952 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4956 /* Parse and record instructions of primary opcode-60 at ADDR.
4957 Return 0 if successful. */
4960 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4961 CORE_ADDR addr
, uint32_t insn
)
4963 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4964 int ext
= PPC_EXTOP (insn
);
4968 case 0: /* VSX Scalar Add Single-Precision */
4969 case 32: /* VSX Scalar Add Double-Precision */
4970 case 24: /* VSX Scalar Divide Single-Precision */
4971 case 56: /* VSX Scalar Divide Double-Precision */
4972 case 176: /* VSX Scalar Copy Sign Double-Precision */
4973 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4974 case 41: /* ditto */
4975 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4977 case 160: /* VSX Scalar Maximum Double-Precision */
4978 case 168: /* VSX Scalar Minimum Double-Precision */
4979 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4980 case 57: /* ditto */
4981 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4982 case 25: /* ditto */
4983 case 48: /* VSX Scalar Multiply Double-Precision */
4984 case 16: /* VSX Scalar Multiply Single-Precision */
4985 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4986 case 169: /* ditto */
4987 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4988 case 137: /* ditto */
4989 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4990 case 185: /* ditto */
4991 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4992 case 153: /* ditto */
4993 case 40: /* VSX Scalar Subtract Double-Precision */
4994 case 8: /* VSX Scalar Subtract Single-Precision */
4995 case 96: /* VSX Vector Add Double-Precision */
4996 case 64: /* VSX Vector Add Single-Precision */
4997 case 120: /* VSX Vector Divide Double-Precision */
4998 case 88: /* VSX Vector Divide Single-Precision */
4999 case 97: /* VSX Vector Multiply-Add Double-Precision */
5000 case 105: /* ditto */
5001 case 65: /* VSX Vector Multiply-Add Single-Precision */
5002 case 73: /* ditto */
5003 case 224: /* VSX Vector Maximum Double-Precision */
5004 case 192: /* VSX Vector Maximum Single-Precision */
5005 case 232: /* VSX Vector Minimum Double-Precision */
5006 case 200: /* VSX Vector Minimum Single-Precision */
5007 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5008 case 121: /* ditto */
5009 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5010 case 89: /* ditto */
5011 case 112: /* VSX Vector Multiply Double-Precision */
5012 case 80: /* VSX Vector Multiply Single-Precision */
5013 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5014 case 233: /* ditto */
5015 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5016 case 201: /* ditto */
5017 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5018 case 249: /* ditto */
5019 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5020 case 217: /* ditto */
5021 case 104: /* VSX Vector Subtract Double-Precision */
5022 case 72: /* VSX Vector Subtract Single-Precision */
5023 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5024 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5025 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5026 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5027 case 3: /* VSX Scalar Compare Equal Double-Precision */
5028 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5029 case 19: /* VSX Scalar Compare Greater Than or Equal
5031 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5033 case 240: /* VSX Vector Copy Sign Double-Precision */
5034 case 208: /* VSX Vector Copy Sign Single-Precision */
5035 case 130: /* VSX Logical AND */
5036 case 138: /* VSX Logical AND with Complement */
5037 case 186: /* VSX Logical Equivalence */
5038 case 178: /* VSX Logical NAND */
5039 case 170: /* VSX Logical OR with Complement */
5040 case 162: /* VSX Logical NOR */
5041 case 146: /* VSX Logical OR */
5042 case 154: /* VSX Logical XOR */
5043 case 18: /* VSX Merge High Word */
5044 case 50: /* VSX Merge Low Word */
5045 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5046 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5047 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5048 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5049 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5050 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5051 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5052 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5053 case 216: /* VSX Vector Insert Exponent Single-Precision */
5054 case 248: /* VSX Vector Insert Exponent Double-Precision */
5055 case 26: /* VSX Vector Permute */
5056 case 58: /* VSX Vector Permute Right-indexed */
5057 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5058 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5059 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5060 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5061 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5064 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5065 case 125: /* VSX Vector Test for software Divide Double-Precision */
5066 case 93: /* VSX Vector Test for software Divide Single-Precision */
5067 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5070 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5071 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5072 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5073 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5074 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5078 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5080 case 99: /* VSX Vector Compare Equal To Double-Precision */
5081 case 67: /* VSX Vector Compare Equal To Single-Precision */
5082 case 115: /* VSX Vector Compare Greater Than or
5083 Equal To Double-Precision */
5084 case 83: /* VSX Vector Compare Greater Than or
5085 Equal To Single-Precision */
5086 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5087 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5089 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5090 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5091 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5097 case 265: /* VSX Scalar round Double-Precision to
5098 Single-Precision and Convert to
5099 Single-Precision format */
5100 case 344: /* VSX Scalar truncate Double-Precision to
5101 Integer and Convert to Signed Integer
5102 Doubleword format with Saturate */
5103 case 88: /* VSX Scalar truncate Double-Precision to
5104 Integer and Convert to Signed Integer Word
5105 Format with Saturate */
5106 case 328: /* VSX Scalar truncate Double-Precision integer
5107 and Convert to Unsigned Integer Doubleword
5108 Format with Saturate */
5109 case 72: /* VSX Scalar truncate Double-Precision to
5110 Integer and Convert to Unsigned Integer Word
5111 Format with Saturate */
5112 case 329: /* VSX Scalar Convert Single-Precision to
5113 Double-Precision format */
5114 case 376: /* VSX Scalar Convert Signed Integer
5115 Doubleword to floating-point format and
5116 Round to Double-Precision format */
5117 case 312: /* VSX Scalar Convert Signed Integer
5118 Doubleword to floating-point format and
5119 round to Single-Precision */
5120 case 360: /* VSX Scalar Convert Unsigned Integer
5121 Doubleword to floating-point format and
5122 Round to Double-Precision format */
5123 case 296: /* VSX Scalar Convert Unsigned Integer
5124 Doubleword to floating-point format and
5125 Round to Single-Precision */
5126 case 73: /* VSX Scalar Round to Double-Precision Integer
5127 Using Round to Nearest Away */
5128 case 107: /* VSX Scalar Round to Double-Precision Integer
5129 Exact using Current rounding mode */
5130 case 121: /* VSX Scalar Round to Double-Precision Integer
5131 Using Round toward -Infinity */
5132 case 105: /* VSX Scalar Round to Double-Precision Integer
5133 Using Round toward +Infinity */
5134 case 89: /* VSX Scalar Round to Double-Precision Integer
5135 Using Round toward Zero */
5136 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5137 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5138 case 281: /* VSX Scalar Round to Single-Precision */
5139 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5141 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5143 case 75: /* VSX Scalar Square Root Double-Precision */
5144 case 11: /* VSX Scalar Square Root Single-Precision */
5145 case 393: /* VSX Vector round Double-Precision to
5146 Single-Precision and Convert to
5147 Single-Precision format */
5148 case 472: /* VSX Vector truncate Double-Precision to
5149 Integer and Convert to Signed Integer
5150 Doubleword format with Saturate */
5151 case 216: /* VSX Vector truncate Double-Precision to
5152 Integer and Convert to Signed Integer Word
5153 Format with Saturate */
5154 case 456: /* VSX Vector truncate Double-Precision to
5155 Integer and Convert to Unsigned Integer
5156 Doubleword format with Saturate */
5157 case 200: /* VSX Vector truncate Double-Precision to
5158 Integer and Convert to Unsigned Integer Word
5159 Format with Saturate */
5160 case 457: /* VSX Vector Convert Single-Precision to
5161 Double-Precision format */
5162 case 408: /* VSX Vector truncate Single-Precision to
5163 Integer and Convert to Signed Integer
5164 Doubleword format with Saturate */
5165 case 152: /* VSX Vector truncate Single-Precision to
5166 Integer and Convert to Signed Integer Word
5167 Format with Saturate */
5168 case 392: /* VSX Vector truncate Single-Precision to
5169 Integer and Convert to Unsigned Integer
5170 Doubleword format with Saturate */
5171 case 136: /* VSX Vector truncate Single-Precision to
5172 Integer and Convert to Unsigned Integer Word
5173 Format with Saturate */
5174 case 504: /* VSX Vector Convert and round Signed Integer
5175 Doubleword to Double-Precision format */
5176 case 440: /* VSX Vector Convert and round Signed Integer
5177 Doubleword to Single-Precision format */
5178 case 248: /* VSX Vector Convert Signed Integer Word to
5179 Double-Precision format */
5180 case 184: /* VSX Vector Convert and round Signed Integer
5181 Word to Single-Precision format */
5182 case 488: /* VSX Vector Convert and round Unsigned
5183 Integer Doubleword to Double-Precision format */
5184 case 424: /* VSX Vector Convert and round Unsigned
5185 Integer Doubleword to Single-Precision format */
5186 case 232: /* VSX Vector Convert and round Unsigned
5187 Integer Word to Double-Precision format */
5188 case 168: /* VSX Vector Convert and round Unsigned
5189 Integer Word to Single-Precision format */
5190 case 201: /* VSX Vector Round to Double-Precision
5191 Integer using round to Nearest Away */
5192 case 235: /* VSX Vector Round to Double-Precision
5193 Integer Exact using Current rounding mode */
5194 case 249: /* VSX Vector Round to Double-Precision
5195 Integer using round toward -Infinity */
5196 case 233: /* VSX Vector Round to Double-Precision
5197 Integer using round toward +Infinity */
5198 case 217: /* VSX Vector Round to Double-Precision
5199 Integer using round toward Zero */
5200 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5201 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5202 case 137: /* VSX Vector Round to Single-Precision Integer
5203 Using Round to Nearest Away */
5204 case 171: /* VSX Vector Round to Single-Precision Integer
5205 Exact Using Current rounding mode */
5206 case 185: /* VSX Vector Round to Single-Precision Integer
5207 Using Round toward -Infinity */
5208 case 169: /* VSX Vector Round to Single-Precision Integer
5209 Using Round toward +Infinity */
5210 case 153: /* VSX Vector Round to Single-Precision Integer
5211 Using round toward Zero */
5212 case 202: /* VSX Vector Reciprocal Square Root Estimate
5214 case 138: /* VSX Vector Reciprocal Square Root Estimate
5216 case 203: /* VSX Vector Square Root Double-Precision */
5217 case 139: /* VSX Vector Square Root Single-Precision */
5218 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5220 case 345: /* VSX Scalar Absolute Value Double-Precision */
5221 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5222 Vector Single-Precision format Non-signalling */
5223 case 331: /* VSX Scalar Convert Single-Precision to
5224 Double-Precision format Non-signalling */
5225 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5226 case 377: /* VSX Scalar Negate Double-Precision */
5227 case 473: /* VSX Vector Absolute Value Double-Precision */
5228 case 409: /* VSX Vector Absolute Value Single-Precision */
5229 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5230 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5231 case 505: /* VSX Vector Negate Double-Precision */
5232 case 441: /* VSX Vector Negate Single-Precision */
5233 case 164: /* VSX Splat Word */
5234 case 165: /* VSX Vector Extract Unsigned Word */
5235 case 181: /* VSX Vector Insert Word */
5236 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5239 case 298: /* VSX Scalar Test Data Class Single-Precision */
5240 case 362: /* VSX Scalar Test Data Class Double-Precision */
5241 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5243 case 106: /* VSX Scalar Test for software Square Root
5245 case 234: /* VSX Vector Test for software Square Root
5247 case 170: /* VSX Vector Test for software Square Root
5249 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5253 switch (PPC_FIELD (insn
, 11, 5))
5255 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5256 case 1: /* VSX Scalar Extract Significand Double-Precision */
5257 record_full_arch_list_add_reg (regcache
,
5258 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5260 case 16: /* VSX Scalar Convert Half-Precision format to
5261 Double-Precision format */
5262 case 17: /* VSX Scalar round & Convert Double-Precision format
5263 to Half-Precision format */
5264 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5265 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5271 switch (PPC_FIELD (insn
, 11, 5))
5273 case 24: /* VSX Vector Convert Half-Precision format to
5274 Single-Precision format */
5275 case 25: /* VSX Vector round and Convert Single-Precision format
5276 to Half-Precision format */
5277 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5279 case 0: /* VSX Vector Extract Exponent Double-Precision */
5280 case 1: /* VSX Vector Extract Significand Double-Precision */
5281 case 7: /* VSX Vector Byte-Reverse Halfword */
5282 case 8: /* VSX Vector Extract Exponent Single-Precision */
5283 case 9: /* VSX Vector Extract Significand Single-Precision */
5284 case 15: /* VSX Vector Byte-Reverse Word */
5285 case 23: /* VSX Vector Byte-Reverse Doubleword */
5286 case 31: /* VSX Vector Byte-Reverse Quadword */
5287 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5295 case 360: /* VSX Vector Splat Immediate Byte */
5296 if (PPC_FIELD (insn
, 11, 2) == 0)
5298 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5302 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5303 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5307 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5309 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5313 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5314 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5318 /* Parse and record instructions of primary opcode-61 at ADDR.
5319 Return 0 if successful. */
5322 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5323 CORE_ADDR addr
, uint32_t insn
)
5325 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5331 case 0: /* Store Floating-Point Double Pair */
5332 case 2: /* Store VSX Scalar Doubleword */
5333 case 3: /* Store VSX Scalar Single */
5334 if (PPC_RA (insn
) != 0)
5335 regcache_raw_read_unsigned (regcache
,
5336 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5338 ea
+= PPC_DS (insn
) << 2;
5341 case 0: /* Store Floating-Point Double Pair */
5344 case 2: /* Store VSX Scalar Doubleword */
5347 case 3: /* Store VSX Scalar Single */
5353 record_full_arch_list_add_mem (ea
, size
);
5359 case 1: /* Load VSX Vector */
5360 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5362 case 5: /* Store VSX Vector */
5363 if (PPC_RA (insn
) != 0)
5364 regcache_raw_read_unsigned (regcache
,
5365 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5367 ea
+= PPC_DQ (insn
) << 4;
5368 record_full_arch_list_add_mem (ea
, 16);
5372 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5373 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5377 /* Parse and record instructions of primary opcode-63 at ADDR.
5378 Return 0 if successful. */
5381 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5382 CORE_ADDR addr
, uint32_t insn
)
5384 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5385 int ext
= PPC_EXTOP (insn
);
5390 case 18: /* Floating Divide */
5391 case 20: /* Floating Subtract */
5392 case 21: /* Floating Add */
5393 case 22: /* Floating Square Root */
5394 case 24: /* Floating Reciprocal Estimate */
5395 case 25: /* Floating Multiply */
5396 case 26: /* Floating Reciprocal Square Root Estimate */
5397 case 28: /* Floating Multiply-Subtract */
5398 case 29: /* Floating Multiply-Add */
5399 case 30: /* Floating Negative Multiply-Subtract */
5400 case 31: /* Floating Negative Multiply-Add */
5401 record_full_arch_list_add_reg (regcache
,
5402 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5404 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5405 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5408 case 23: /* Floating Select */
5409 record_full_arch_list_add_reg (regcache
,
5410 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5412 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5418 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5419 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5421 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5422 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5428 case 2: /* DFP Add Quad */
5429 case 3: /* DFP Quantize Quad */
5430 case 34: /* DFP Multiply Quad */
5431 case 35: /* DFP Reround Quad */
5432 case 67: /* DFP Quantize Immediate Quad */
5433 case 99: /* DFP Round To FP Integer With Inexact Quad */
5434 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5435 case 258: /* DFP Convert To DFP Extended Quad */
5436 case 514: /* DFP Subtract Quad */
5437 case 546: /* DFP Divide Quad */
5438 case 770: /* DFP Round To DFP Long Quad */
5439 case 802: /* DFP Convert From Fixed Quad */
5440 case 834: /* DFP Encode BCD To DPD Quad */
5442 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5443 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5444 record_full_arch_list_add_reg (regcache
, tmp
);
5445 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5446 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5449 case 130: /* DFP Compare Ordered Quad */
5450 case 162: /* DFP Test Exponent Quad */
5451 case 194: /* DFP Test Data Class Quad */
5452 case 226: /* DFP Test Data Group Quad */
5453 case 642: /* DFP Compare Unordered Quad */
5454 case 674: /* DFP Test Significance Quad */
5455 case 675: /* DFP Test Significance Immediate Quad */
5456 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5457 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5460 case 66: /* DFP Shift Significand Left Immediate Quad */
5461 case 98: /* DFP Shift Significand Right Immediate Quad */
5462 case 322: /* DFP Decode DPD To BCD Quad */
5463 case 866: /* DFP Insert Biased Exponent Quad */
5464 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5465 record_full_arch_list_add_reg (regcache
, tmp
);
5466 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5468 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5471 case 290: /* DFP Convert To Fixed Quad */
5472 record_full_arch_list_add_reg (regcache
,
5473 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5475 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5476 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5479 case 354: /* DFP Extract Biased Exponent Quad */
5480 record_full_arch_list_add_reg (regcache
,
5481 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5483 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5486 case 12: /* Floating Round to Single-Precision */
5487 case 14: /* Floating Convert To Integer Word */
5488 case 15: /* Floating Convert To Integer Word
5489 with round toward Zero */
5490 case 142: /* Floating Convert To Integer Word Unsigned */
5491 case 143: /* Floating Convert To Integer Word Unsigned
5492 with round toward Zero */
5493 case 392: /* Floating Round to Integer Nearest */
5494 case 424: /* Floating Round to Integer Toward Zero */
5495 case 456: /* Floating Round to Integer Plus */
5496 case 488: /* Floating Round to Integer Minus */
5497 case 814: /* Floating Convert To Integer Doubleword */
5498 case 815: /* Floating Convert To Integer Doubleword
5499 with round toward Zero */
5500 case 846: /* Floating Convert From Integer Doubleword */
5501 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5502 case 943: /* Floating Convert To Integer Doubleword Unsigned
5503 with round toward Zero */
5504 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5505 record_full_arch_list_add_reg (regcache
,
5506 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5508 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5509 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5513 switch (PPC_FIELD (insn
, 11, 5))
5515 case 1: /* Move From FPSCR & Clear Enables */
5516 case 20: /* Move From FPSCR Control & set DRN */
5517 case 21: /* Move From FPSCR Control & set DRN Immediate */
5518 case 22: /* Move From FPSCR Control & set RN */
5519 case 23: /* Move From FPSCR Control & set RN Immediate */
5520 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5521 case 0: /* Move From FPSCR */
5522 case 24: /* Move From FPSCR Lightweight */
5523 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5524 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5525 record_full_arch_list_add_reg (regcache
,
5526 tdep
->ppc_fp0_regnum
5532 case 8: /* Floating Copy Sign */
5533 case 40: /* Floating Negate */
5534 case 72: /* Floating Move Register */
5535 case 136: /* Floating Negative Absolute Value */
5536 case 264: /* Floating Absolute Value */
5537 record_full_arch_list_add_reg (regcache
,
5538 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5540 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5543 case 838: /* Floating Merge Odd Word */
5544 case 966: /* Floating Merge Even Word */
5545 record_full_arch_list_add_reg (regcache
,
5546 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5549 case 38: /* Move To FPSCR Bit 1 */
5550 case 70: /* Move To FPSCR Bit 0 */
5551 case 134: /* Move To FPSCR Field Immediate */
5552 case 711: /* Move To FPSCR Fields */
5554 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5555 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5558 case 0: /* Floating Compare Unordered */
5559 case 32: /* Floating Compare Ordered */
5560 case 64: /* Move to Condition Register from FPSCR */
5561 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5562 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5563 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5564 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5565 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5567 case 128: /* Floating Test for software Divide */
5568 case 160: /* Floating Test for software Square Root */
5569 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5572 case 4: /* VSX Scalar Add Quad-Precision */
5573 case 36: /* VSX Scalar Multiply Quad-Precision */
5574 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5575 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5576 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5577 case 484: /* VSX Scalar Negative Multiply-Subtract
5579 case 516: /* VSX Scalar Subtract Quad-Precision */
5580 case 548: /* VSX Scalar Divide Quad-Precision */
5581 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5583 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5584 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5585 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5589 switch (PPC_FIELD (insn
, 11, 5))
5591 case 27: /* VSX Scalar Square Root Quad-Precision */
5592 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5594 case 0: /* VSX Scalar Absolute Quad-Precision */
5595 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5596 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5597 case 16: /* VSX Scalar Negate Quad-Precision */
5598 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5599 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5605 switch (PPC_FIELD (insn
, 11, 5))
5607 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5608 to Unsigned Word format */
5609 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5610 Quad-Precision format */
5611 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5612 to Signed Word format */
5613 case 10: /* VSX Scalar Convert Signed Doubleword format to
5614 Quad-Precision format */
5615 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5616 to Unsigned Doubleword format */
5617 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5618 Double-Precision format */
5619 case 22: /* VSX Scalar Convert Double-Precision format to
5620 Quad-Precision format */
5621 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5622 to Signed Doubleword format */
5623 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5624 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5629 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5630 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5634 /* Parse the current instruction and record the values of the registers and
5635 memory that will be changed in current instruction to "record_arch_list".
5636 Return -1 if something wrong. */
5639 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5642 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5643 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5647 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5648 op6
= PPC_OP6 (insn
);
5652 case 2: /* Trap Doubleword Immediate */
5653 case 3: /* Trap Word Immediate */
5658 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5662 case 17: /* System call */
5663 if (PPC_LEV (insn
) != 0)
5666 if (tdep
->ppc_syscall_record
!= NULL
)
5668 if (tdep
->ppc_syscall_record (regcache
) != 0)
5673 printf_unfiltered (_("no syscall record support\n"));
5678 case 7: /* Multiply Low Immediate */
5679 record_full_arch_list_add_reg (regcache
,
5680 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5683 case 8: /* Subtract From Immediate Carrying */
5684 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5685 record_full_arch_list_add_reg (regcache
,
5686 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5689 case 10: /* Compare Logical Immediate */
5690 case 11: /* Compare Immediate */
5691 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5694 case 13: /* Add Immediate Carrying and Record */
5695 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5697 case 12: /* Add Immediate Carrying */
5698 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5700 case 14: /* Add Immediate */
5701 case 15: /* Add Immediate Shifted */
5702 record_full_arch_list_add_reg (regcache
,
5703 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5706 case 16: /* Branch Conditional */
5707 if ((PPC_BO (insn
) & 0x4) == 0)
5708 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5710 case 18: /* Branch */
5712 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5716 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5720 case 20: /* Rotate Left Word Immediate then Mask Insert */
5721 case 21: /* Rotate Left Word Immediate then AND with Mask */
5722 case 23: /* Rotate Left Word then AND with Mask */
5723 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5724 /* Rotate Left Doubleword Immediate then Clear Right */
5725 /* Rotate Left Doubleword Immediate then Clear */
5726 /* Rotate Left Doubleword then Clear Left */
5727 /* Rotate Left Doubleword then Clear Right */
5728 /* Rotate Left Doubleword Immediate then Mask Insert */
5730 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5731 record_full_arch_list_add_reg (regcache
,
5732 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5735 case 28: /* AND Immediate */
5736 case 29: /* AND Immediate Shifted */
5737 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5739 case 24: /* OR Immediate */
5740 case 25: /* OR Immediate Shifted */
5741 case 26: /* XOR Immediate */
5742 case 27: /* XOR Immediate Shifted */
5743 record_full_arch_list_add_reg (regcache
,
5744 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5748 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5752 case 33: /* Load Word and Zero with Update */
5753 case 35: /* Load Byte and Zero with Update */
5754 case 41: /* Load Halfword and Zero with Update */
5755 case 43: /* Load Halfword Algebraic with Update */
5756 record_full_arch_list_add_reg (regcache
,
5757 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5759 case 32: /* Load Word and Zero */
5760 case 34: /* Load Byte and Zero */
5761 case 40: /* Load Halfword and Zero */
5762 case 42: /* Load Halfword Algebraic */
5763 record_full_arch_list_add_reg (regcache
,
5764 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5767 case 46: /* Load Multiple Word */
5768 for (i
= PPC_RT (insn
); i
< 32; i
++)
5769 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5772 case 56: /* Load Quadword */
5773 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5774 record_full_arch_list_add_reg (regcache
, tmp
);
5775 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5778 case 49: /* Load Floating-Point Single with Update */
5779 case 51: /* Load Floating-Point Double with Update */
5780 record_full_arch_list_add_reg (regcache
,
5781 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5783 case 48: /* Load Floating-Point Single */
5784 case 50: /* Load Floating-Point Double */
5785 record_full_arch_list_add_reg (regcache
,
5786 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5789 case 47: /* Store Multiple Word */
5793 if (PPC_RA (insn
) != 0)
5794 regcache_raw_read_unsigned (regcache
,
5795 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5798 addr
+= PPC_D (insn
);
5799 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5803 case 37: /* Store Word with Update */
5804 case 39: /* Store Byte with Update */
5805 case 45: /* Store Halfword with Update */
5806 case 53: /* Store Floating-Point Single with Update */
5807 case 55: /* Store Floating-Point Double with Update */
5808 record_full_arch_list_add_reg (regcache
,
5809 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5811 case 36: /* Store Word */
5812 case 38: /* Store Byte */
5813 case 44: /* Store Halfword */
5814 case 52: /* Store Floating-Point Single */
5815 case 54: /* Store Floating-Point Double */
5820 if (PPC_RA (insn
) != 0)
5821 regcache_raw_read_unsigned (regcache
,
5822 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5824 addr
+= PPC_D (insn
);
5826 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5828 else if (op6
== 54 || op6
== 55)
5830 else if (op6
== 44 || op6
== 45)
5832 else if (op6
== 38 || op6
== 39)
5837 record_full_arch_list_add_mem (addr
, size
);
5844 case 0: /* Load Floating-Point Double Pair */
5845 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5846 record_full_arch_list_add_reg (regcache
, tmp
);
5847 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5849 case 2: /* Load VSX Scalar Doubleword */
5850 case 3: /* Load VSX Scalar Single */
5851 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5858 case 58: /* Load Doubleword */
5859 /* Load Doubleword with Update */
5860 /* Load Word Algebraic */
5861 if (PPC_FIELD (insn
, 30, 2) > 2)
5864 record_full_arch_list_add_reg (regcache
,
5865 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5866 if (PPC_BIT (insn
, 31))
5867 record_full_arch_list_add_reg (regcache
,
5868 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5872 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5877 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5882 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5886 case 62: /* Store Doubleword */
5887 /* Store Doubleword with Update */
5888 /* Store Quadword with Update */
5892 int sub2
= PPC_FIELD (insn
, 30, 2);
5897 if (PPC_RA (insn
) != 0)
5898 regcache_raw_read_unsigned (regcache
,
5899 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5902 size
= (sub2
== 2) ? 16 : 8;
5904 addr
+= PPC_DS (insn
) << 2;
5905 record_full_arch_list_add_mem (addr
, size
);
5907 if (op6
== 62 && sub2
== 1)
5908 record_full_arch_list_add_reg (regcache
,
5909 tdep
->ppc_gp0_regnum
+
5916 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5922 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5923 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5927 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5929 if (record_full_arch_list_add_end ())
5934 /* Initialize the current architecture based on INFO. If possible, re-use an
5935 architecture from ARCHES, which is a list of architectures already created
5936 during this debugging session.
5938 Called e.g. at program startup, when reading a core file, and when reading
5941 static struct gdbarch
*
5942 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5944 struct gdbarch
*gdbarch
;
5945 struct gdbarch_tdep
*tdep
;
5946 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5947 enum bfd_architecture arch
;
5950 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5952 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5953 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5954 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5956 int tdesc_wordsize
= -1;
5957 const struct target_desc
*tdesc
= info
.target_desc
;
5958 struct tdesc_arch_data
*tdesc_data
= NULL
;
5959 int num_pseudoregs
= 0;
5962 /* INFO may refer to a binary that is not of the PowerPC architecture,
5963 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5964 In this case, we must not attempt to infer properties of the (PowerPC
5965 side) of the target system from properties of that executable. Trust
5966 the target description instead. */
5968 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5969 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5972 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5973 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5975 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5976 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5978 /* Check word size. If INFO is from a binary file, infer it from
5979 that, else choose a likely default. */
5980 if (from_xcoff_exec
)
5982 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5987 else if (from_elf_exec
)
5989 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5994 else if (tdesc_has_registers (tdesc
))
5998 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
5999 wordsize
= (info
.bfd_arch_info
->bits_per_word
6000 / info
.bfd_arch_info
->bits_per_byte
);
6005 /* Get the architecture and machine from the BFD. */
6006 arch
= info
.bfd_arch_info
->arch
;
6007 mach
= info
.bfd_arch_info
->mach
;
6009 /* For e500 executables, the apuinfo section is of help here. Such
6010 section contains the identifier and revision number of each
6011 Application-specific Processing Unit that is present on the
6012 chip. The content of the section is determined by the assembler
6013 which looks at each instruction and determines which unit (and
6014 which version of it) can execute it. Grovel through the section
6015 looking for relevant e500 APUs. */
6017 if (bfd_uses_spe_extensions (info
.abfd
))
6019 arch
= info
.bfd_arch_info
->arch
;
6020 mach
= bfd_mach_ppc_e500
;
6021 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6022 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6025 /* Find a default target description which describes our register
6026 layout, if we do not already have one. */
6027 if (! tdesc_has_registers (tdesc
))
6029 const struct variant
*v
;
6031 /* Choose variant. */
6032 v
= find_variant_by_arch (arch
, mach
);
6039 gdb_assert (tdesc_has_registers (tdesc
));
6041 /* Check any target description for validity. */
6042 if (tdesc_has_registers (tdesc
))
6044 static const char *const gprs
[] = {
6045 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6046 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6047 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6048 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6050 const struct tdesc_feature
*feature
;
6052 static const char *const msr_names
[] = { "msr", "ps" };
6053 static const char *const cr_names
[] = { "cr", "cnd" };
6054 static const char *const ctr_names
[] = { "ctr", "cnt" };
6056 feature
= tdesc_find_feature (tdesc
,
6057 "org.gnu.gdb.power.core");
6058 if (feature
== NULL
)
6061 tdesc_data
= tdesc_data_alloc ();
6064 for (i
= 0; i
< ppc_num_gprs
; i
++)
6065 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
6066 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
6068 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
6070 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
6073 /* Allow alternate names for these registers, to accomodate GDB's
6075 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6076 PPC_MSR_REGNUM
, msr_names
);
6077 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6078 PPC_CR_REGNUM
, cr_names
);
6079 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6080 PPC_CTR_REGNUM
, ctr_names
);
6084 tdesc_data_cleanup (tdesc_data
);
6088 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
6091 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
6093 wordsize
= tdesc_wordsize
;
6095 feature
= tdesc_find_feature (tdesc
,
6096 "org.gnu.gdb.power.fpu");
6097 if (feature
!= NULL
)
6099 static const char *const fprs
[] = {
6100 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6101 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6102 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6103 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6106 for (i
= 0; i
< ppc_num_fprs
; i
++)
6107 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6108 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6109 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6110 PPC_FPSCR_REGNUM
, "fpscr");
6114 tdesc_data_cleanup (tdesc_data
);
6122 /* The DFP pseudo-registers will be available when there are floating
6124 have_dfp
= have_fpu
;
6126 feature
= tdesc_find_feature (tdesc
,
6127 "org.gnu.gdb.power.altivec");
6128 if (feature
!= NULL
)
6130 static const char *const vector_regs
[] = {
6131 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6132 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6133 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6134 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6138 for (i
= 0; i
< ppc_num_gprs
; i
++)
6139 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6142 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6143 PPC_VSCR_REGNUM
, "vscr");
6144 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6145 PPC_VRSAVE_REGNUM
, "vrsave");
6147 if (have_spe
|| !valid_p
)
6149 tdesc_data_cleanup (tdesc_data
);
6157 /* Check for POWER7 VSX registers support. */
6158 feature
= tdesc_find_feature (tdesc
,
6159 "org.gnu.gdb.power.vsx");
6161 if (feature
!= NULL
)
6163 static const char *const vsx_regs
[] = {
6164 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6165 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6166 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6167 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6168 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6174 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6175 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6176 PPC_VSR0_UPPER_REGNUM
+ i
,
6180 tdesc_data_cleanup (tdesc_data
);
6189 /* On machines supporting the SPE APU, the general-purpose registers
6190 are 64 bits long. There are SIMD vector instructions to treat them
6191 as pairs of floats, but the rest of the instruction set treats them
6192 as 32-bit registers, and only operates on their lower halves.
6194 In the GDB regcache, we treat their high and low halves as separate
6195 registers. The low halves we present as the general-purpose
6196 registers, and then we have pseudo-registers that stitch together
6197 the upper and lower halves and present them as pseudo-registers.
6199 Thus, the target description is expected to supply the upper
6200 halves separately. */
6202 feature
= tdesc_find_feature (tdesc
,
6203 "org.gnu.gdb.power.spe");
6204 if (feature
!= NULL
)
6206 static const char *const upper_spe
[] = {
6207 "ev0h", "ev1h", "ev2h", "ev3h",
6208 "ev4h", "ev5h", "ev6h", "ev7h",
6209 "ev8h", "ev9h", "ev10h", "ev11h",
6210 "ev12h", "ev13h", "ev14h", "ev15h",
6211 "ev16h", "ev17h", "ev18h", "ev19h",
6212 "ev20h", "ev21h", "ev22h", "ev23h",
6213 "ev24h", "ev25h", "ev26h", "ev27h",
6214 "ev28h", "ev29h", "ev30h", "ev31h"
6218 for (i
= 0; i
< ppc_num_gprs
; i
++)
6219 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6220 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6222 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6223 PPC_SPE_ACC_REGNUM
, "acc");
6224 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6225 PPC_SPE_FSCR_REGNUM
, "spefscr");
6227 if (have_mq
|| have_fpu
|| !valid_p
)
6229 tdesc_data_cleanup (tdesc_data
);
6238 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6239 complain for a 32-bit binary on a 64-bit target; we do not yet
6240 support that. For instance, the 32-bit ABI routines expect
6243 As long as there isn't an explicit target description, we'll
6244 choose one based on the BFD architecture and get a word size
6245 matching the binary (probably powerpc:common or
6246 powerpc:common64). So there is only trouble if a 64-bit target
6247 supplies a 64-bit description while debugging a 32-bit
6249 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6251 tdesc_data_cleanup (tdesc_data
);
6258 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6261 elf_abi
= POWERPC_ELF_V1
;
6264 elf_abi
= POWERPC_ELF_V2
;
6271 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6273 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6274 Tag_GNU_Power_ABI_FP
))
6277 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6280 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6287 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6289 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6290 Tag_GNU_Power_ABI_Vector
))
6293 vector_abi
= POWERPC_VEC_GENERIC
;
6296 vector_abi
= POWERPC_VEC_ALTIVEC
;
6299 vector_abi
= POWERPC_VEC_SPE
;
6307 /* At this point, the only supported ELF-based 64-bit little-endian
6308 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6309 default. All other supported ELF-based operating systems use the
6310 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6311 e.g. because we run a legacy binary, or have attached to a process
6312 and have not found any associated binary file, set the default
6313 according to this heuristic. */
6314 if (elf_abi
== POWERPC_ELF_AUTO
)
6316 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6317 elf_abi
= POWERPC_ELF_V2
;
6319 elf_abi
= POWERPC_ELF_V1
;
6322 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6324 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6327 soft_float
= !have_fpu
;
6329 /* If we have a hard float binary or setting but no floating point
6330 registers, downgrade to soft float anyway. We're still somewhat
6331 useful in this scenario. */
6332 if (!soft_float
&& !have_fpu
)
6335 /* Similarly for vector registers. */
6336 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6337 vector_abi
= POWERPC_VEC_GENERIC
;
6339 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6340 vector_abi
= POWERPC_VEC_GENERIC
;
6342 if (vector_abi
== POWERPC_VEC_AUTO
)
6345 vector_abi
= POWERPC_VEC_ALTIVEC
;
6347 vector_abi
= POWERPC_VEC_SPE
;
6349 vector_abi
= POWERPC_VEC_GENERIC
;
6352 /* Do not limit the vector ABI based on available hardware, since we
6353 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6355 /* Find a candidate among extant architectures. */
6356 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6358 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6360 /* Word size in the various PowerPC bfd_arch_info structs isn't
6361 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6362 separate word size check. */
6363 tdep
= gdbarch_tdep (arches
->gdbarch
);
6364 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6366 if (tdep
&& tdep
->soft_float
!= soft_float
)
6368 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6370 if (tdep
&& tdep
->wordsize
== wordsize
)
6372 if (tdesc_data
!= NULL
)
6373 tdesc_data_cleanup (tdesc_data
);
6374 return arches
->gdbarch
;
6378 /* None found, create a new architecture from INFO, whose bfd_arch_info
6379 validity depends on the source:
6380 - executable useless
6381 - rs6000_host_arch() good
6383 - "set arch" trust blindly
6384 - GDB startup useless but harmless */
6386 tdep
= XCNEW (struct gdbarch_tdep
);
6387 tdep
->wordsize
= wordsize
;
6388 tdep
->elf_abi
= elf_abi
;
6389 tdep
->soft_float
= soft_float
;
6390 tdep
->vector_abi
= vector_abi
;
6392 gdbarch
= gdbarch_alloc (&info
, tdep
);
6394 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6395 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6396 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6397 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6398 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6399 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6400 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6401 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6403 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6404 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6405 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6406 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6407 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6408 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6409 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6410 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6412 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6413 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6414 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6415 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6417 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6418 GDB traditionally called it "ps", though, so let GDB add an
6420 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6423 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6425 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6427 /* Set lr_frame_offset. */
6429 tdep
->lr_frame_offset
= 16;
6431 tdep
->lr_frame_offset
= 4;
6433 if (have_spe
|| have_dfp
|| have_vsx
)
6435 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6436 set_gdbarch_pseudo_register_write (gdbarch
,
6437 rs6000_pseudo_register_write
);
6438 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6439 rs6000_ax_pseudo_register_collect
);
6442 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6444 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6446 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6449 num_pseudoregs
+= 32;
6451 num_pseudoregs
+= 16;
6453 /* Include both VSX and Extended FP registers. */
6454 num_pseudoregs
+= 96;
6456 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6458 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6459 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6460 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6461 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6462 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6463 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6464 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6465 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6466 set_gdbarch_char_signed (gdbarch
, 0);
6468 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6471 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6473 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6474 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6475 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6477 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6478 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6481 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6482 else if (wordsize
== 8)
6483 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6485 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6486 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6487 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6489 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6491 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6492 rs6000_breakpoint::kind_from_pc
);
6493 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6494 rs6000_breakpoint::bp_from_kind
);
6496 /* The value of symbols of type N_SO and N_FUN maybe null when
6498 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6500 /* Handles single stepping of atomic sequences. */
6501 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6503 /* Not sure on this. FIXMEmgo */
6504 set_gdbarch_frame_args_skip (gdbarch
, 8);
6506 /* Helpers for function argument information. */
6507 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6510 set_gdbarch_in_solib_return_trampoline
6511 (gdbarch
, rs6000_in_solib_return_trampoline
);
6512 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6514 /* Hook in the DWARF CFI frame unwinder. */
6515 dwarf2_append_unwinders (gdbarch
);
6516 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6518 /* Frame handling. */
6519 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6521 /* Setup displaced stepping. */
6522 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6523 ppc_displaced_step_copy_insn
);
6524 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6525 ppc_displaced_step_hw_singlestep
);
6526 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6527 set_gdbarch_displaced_step_location (gdbarch
,
6528 displaced_step_at_entry_point
);
6530 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6532 /* Hook in ABI-specific overrides, if they have been registered. */
6533 info
.target_desc
= tdesc
;
6534 info
.tdesc_data
= tdesc_data
;
6535 gdbarch_init_osabi (info
, gdbarch
);
6539 case GDB_OSABI_LINUX
:
6540 case GDB_OSABI_NETBSD
:
6541 case GDB_OSABI_UNKNOWN
:
6542 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6543 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6544 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6545 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6546 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6549 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6551 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6552 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6553 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6554 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6555 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6558 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6559 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6560 rs6000_pseudo_register_reggroup_p
);
6561 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6563 /* Override the normal target description method to make the SPE upper
6564 halves anonymous. */
6565 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6567 /* Choose register numbers for all supported pseudo-registers. */
6568 tdep
->ppc_ev0_regnum
= -1;
6569 tdep
->ppc_dl0_regnum
= -1;
6570 tdep
->ppc_vsr0_regnum
= -1;
6571 tdep
->ppc_efpr0_regnum
= -1;
6573 cur_reg
= gdbarch_num_regs (gdbarch
);
6577 tdep
->ppc_ev0_regnum
= cur_reg
;
6582 tdep
->ppc_dl0_regnum
= cur_reg
;
6587 tdep
->ppc_vsr0_regnum
= cur_reg
;
6589 tdep
->ppc_efpr0_regnum
= cur_reg
;
6593 gdb_assert (gdbarch_num_regs (gdbarch
)
6594 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6596 /* Register the ravenscar_arch_ops. */
6597 if (mach
== bfd_mach_ppc_e500
)
6598 register_e500_ravenscar_ops (gdbarch
);
6600 register_ppc_ravenscar_ops (gdbarch
);
6602 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
6603 set_gdbarch_valid_disassembler_options (gdbarch
,
6604 disassembler_options_powerpc ());
6610 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6617 /* FIXME: Dump gdbarch_tdep. */
6620 /* PowerPC-specific commands. */
6623 set_powerpc_command (const char *args
, int from_tty
)
6625 printf_unfiltered (_("\
6626 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6627 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6631 show_powerpc_command (const char *args
, int from_tty
)
6633 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6637 powerpc_set_soft_float (char *args
, int from_tty
,
6638 struct cmd_list_element
*c
)
6640 struct gdbarch_info info
;
6642 /* Update the architecture. */
6643 gdbarch_info_init (&info
);
6644 if (!gdbarch_update_p (info
))
6645 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6649 powerpc_set_vector_abi (char *args
, int from_tty
,
6650 struct cmd_list_element
*c
)
6652 struct gdbarch_info info
;
6655 for (vector_abi
= POWERPC_VEC_AUTO
;
6656 vector_abi
!= POWERPC_VEC_LAST
;
6658 if (strcmp (powerpc_vector_abi_string
,
6659 powerpc_vector_strings
[vector_abi
]) == 0)
6661 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6665 if (vector_abi
== POWERPC_VEC_LAST
)
6666 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6667 powerpc_vector_abi_string
);
6669 /* Update the architecture. */
6670 gdbarch_info_init (&info
);
6671 if (!gdbarch_update_p (info
))
6672 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6675 /* Show the current setting of the exact watchpoints flag. */
6678 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6679 struct cmd_list_element
*c
,
6682 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6685 /* Read a PPC instruction from memory. */
6688 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6690 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6691 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6693 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6696 /* Return non-zero if the instructions at PC match the series
6697 described in PATTERN, or zero otherwise. PATTERN is an array of
6698 'struct ppc_insn_pattern' objects, terminated by an entry whose
6701 When the match is successful, fill INSN[i] with what PATTERN[i]
6702 matched. If PATTERN[i] is optional, and the instruction wasn't
6703 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6704 INSN should have as many elements as PATTERN. Note that, if
6705 PATTERN contains optional instructions which aren't present in
6706 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6707 i'th instruction in memory. */
6710 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6711 struct ppc_insn_pattern
*pattern
,
6712 unsigned int *insns
)
6717 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6720 insn
= read_insn (frame
, pc
);
6722 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6728 else if (!pattern
[i
].optional
)
6735 /* Return the 'd' field of the d-form instruction INSN, properly
6739 ppc_insn_d_field (unsigned int insn
)
6741 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6744 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6745 zero bits concatenated at the right, and properly
6749 ppc_insn_ds_field (unsigned int insn
)
6751 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6754 /* Initialization code. */
6757 _initialize_rs6000_tdep (void)
6759 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6760 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6762 /* Initialize the standard target descriptions. */
6763 initialize_tdesc_powerpc_32 ();
6764 initialize_tdesc_powerpc_altivec32 ();
6765 initialize_tdesc_powerpc_vsx32 ();
6766 initialize_tdesc_powerpc_403 ();
6767 initialize_tdesc_powerpc_403gc ();
6768 initialize_tdesc_powerpc_405 ();
6769 initialize_tdesc_powerpc_505 ();
6770 initialize_tdesc_powerpc_601 ();
6771 initialize_tdesc_powerpc_602 ();
6772 initialize_tdesc_powerpc_603 ();
6773 initialize_tdesc_powerpc_604 ();
6774 initialize_tdesc_powerpc_64 ();
6775 initialize_tdesc_powerpc_altivec64 ();
6776 initialize_tdesc_powerpc_vsx64 ();
6777 initialize_tdesc_powerpc_7400 ();
6778 initialize_tdesc_powerpc_750 ();
6779 initialize_tdesc_powerpc_860 ();
6780 initialize_tdesc_powerpc_e500 ();
6781 initialize_tdesc_rs6000 ();
6783 /* Add root prefix command for all "set powerpc"/"show powerpc"
6785 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6786 _("Various PowerPC-specific commands."),
6787 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6789 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6790 _("Various PowerPC-specific commands."),
6791 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6793 /* Add a command to allow the user to force the ABI. */
6794 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6795 &powerpc_soft_float_global
,
6796 _("Set whether to use a soft-float ABI."),
6797 _("Show whether to use a soft-float ABI."),
6799 powerpc_set_soft_float
, NULL
,
6800 &setpowerpccmdlist
, &showpowerpccmdlist
);
6802 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6803 &powerpc_vector_abi_string
,
6804 _("Set the vector ABI."),
6805 _("Show the vector ABI."),
6806 NULL
, powerpc_set_vector_abi
, NULL
,
6807 &setpowerpccmdlist
, &showpowerpccmdlist
);
6809 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6810 &target_exact_watchpoints
,
6812 Set whether to use just one debug register for watchpoints on scalars."),
6814 Show whether to use just one debug register for watchpoints on scalars."),
6816 If true, GDB will use only one debug register when watching a variable of\n\
6817 scalar type, thus assuming that the variable is accessed through the address\n\
6818 of its first byte."),
6819 NULL
, show_powerpc_exact_watchpoints
,
6820 &setpowerpccmdlist
, &showpowerpccmdlist
);