1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2/frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* To be used by skip_prologue. */
158 struct rs6000_framedata
160 int offset
; /* total size of frame --- the distance
161 by which we decrement sp to allocate
163 int saved_gpr
; /* smallest # of saved gpr */
164 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
165 int saved_fpr
; /* smallest # of saved fpr */
166 int saved_vr
; /* smallest # of saved vr */
167 int saved_ev
; /* smallest # of saved ev */
168 int alloca_reg
; /* alloca register number (frame ptr) */
169 char frameless
; /* true if frameless functions. */
170 char nosavedpc
; /* true if pc not saved. */
171 char used_bl
; /* true if link register clobbered */
172 int gpr_offset
; /* offset of saved gprs from prev sp */
173 int fpr_offset
; /* offset of saved fprs from prev sp */
174 int vr_offset
; /* offset of saved vrs from prev sp */
175 int ev_offset
; /* offset of saved evs from prev sp */
176 int lr_offset
; /* offset of saved lr */
177 int lr_register
; /* register of saved lr, if trustworthy */
178 int cr_offset
; /* offset of saved cr */
179 int vrsave_offset
; /* offset of saved vrsave register */
183 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
185 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
188 if (tdep
->ppc_vsr0_regnum
< 0)
191 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
192 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
195 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
197 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
199 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
200 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
203 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
207 /* Return true if REGNO is an SPE register, false otherwise. */
209 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
211 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
213 /* Is it a reference to EV0 -- EV31, and do we have those? */
214 if (IS_SPE_PSEUDOREG (tdep
, regno
))
217 /* Is it a reference to one of the raw upper GPR halves? */
218 if (tdep
->ppc_ev0_upper_regnum
>= 0
219 && tdep
->ppc_ev0_upper_regnum
<= regno
220 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
223 /* Is it a reference to the 64-bit accumulator, and do we have that? */
224 if (tdep
->ppc_acc_regnum
>= 0
225 && tdep
->ppc_acc_regnum
== regno
)
228 /* Is it a reference to the SPE floating-point status and control register,
229 and do we have that? */
230 if (tdep
->ppc_spefscr_regnum
>= 0
231 && tdep
->ppc_spefscr_regnum
== regno
)
238 /* Return non-zero if the architecture described by GDBARCH has
239 floating-point registers (f0 --- f31 and fpscr). */
241 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
243 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
245 return (tdep
->ppc_fp0_regnum
>= 0
246 && tdep
->ppc_fpscr_regnum
>= 0);
249 /* Return non-zero if the architecture described by GDBARCH has
250 Altivec registers (vr0 --- vr31, vrsave and vscr). */
252 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
254 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
256 return (tdep
->ppc_vr0_regnum
>= 0
257 && tdep
->ppc_vrsave_regnum
>= 0);
260 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
263 This is a helper function for init_sim_regno_table, constructing
264 the table mapping GDB register numbers to sim register numbers; we
265 initialize every element in that table to -1 before we start
268 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
270 /* Make sure we don't try to assign any given GDB register a sim
271 register number more than once. */
272 gdb_assert (table
[gdb_regno
] == -1);
273 table
[gdb_regno
] = sim_regno
;
277 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
278 numbers to simulator register numbers, based on the values placed
279 in the ARCH->tdep->ppc_foo_regnum members. */
281 init_sim_regno_table (struct gdbarch
*arch
)
283 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
284 int total_regs
= gdbarch_num_regs (arch
);
285 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
287 static const char *const segment_regs
[] = {
288 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
289 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
292 /* Presume that all registers not explicitly mentioned below are
293 unavailable from the sim. */
294 for (i
= 0; i
< total_regs
; i
++)
297 /* General-purpose registers. */
298 for (i
= 0; i
< ppc_num_gprs
; i
++)
299 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
301 /* Floating-point registers. */
302 if (tdep
->ppc_fp0_regnum
>= 0)
303 for (i
= 0; i
< ppc_num_fprs
; i
++)
304 set_sim_regno (sim_regno
,
305 tdep
->ppc_fp0_regnum
+ i
,
306 sim_ppc_f0_regnum
+ i
);
307 if (tdep
->ppc_fpscr_regnum
>= 0)
308 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
310 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
311 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
312 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
314 /* Segment registers. */
315 for (i
= 0; i
< ppc_num_srs
; i
++)
319 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
321 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
324 /* Altivec registers. */
325 if (tdep
->ppc_vr0_regnum
>= 0)
327 for (i
= 0; i
< ppc_num_vrs
; i
++)
328 set_sim_regno (sim_regno
,
329 tdep
->ppc_vr0_regnum
+ i
,
330 sim_ppc_vr0_regnum
+ i
);
332 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
333 we can treat this more like the other cases. */
334 set_sim_regno (sim_regno
,
335 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
336 sim_ppc_vscr_regnum
);
338 /* vsave is a special-purpose register, so the code below handles it. */
340 /* SPE APU (E500) registers. */
341 if (tdep
->ppc_ev0_upper_regnum
>= 0)
342 for (i
= 0; i
< ppc_num_gprs
; i
++)
343 set_sim_regno (sim_regno
,
344 tdep
->ppc_ev0_upper_regnum
+ i
,
345 sim_ppc_rh0_regnum
+ i
);
346 if (tdep
->ppc_acc_regnum
>= 0)
347 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
348 /* spefscr is a special-purpose register, so the code below handles it. */
351 /* Now handle all special-purpose registers. Verify that they
352 haven't mistakenly been assigned numbers by any of the above
354 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
356 const char *spr_name
= sim_spr_register_name (i
);
359 if (spr_name
!= NULL
)
360 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
363 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
367 /* Drop the initialized array into place. */
368 tdep
->sim_regno
= sim_regno
;
372 /* Given a GDB register number REG, return the corresponding SIM
375 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
377 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
380 if (tdep
->sim_regno
== NULL
)
381 init_sim_regno_table (gdbarch
);
383 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
384 sim_regno
= tdep
->sim_regno
[reg
];
389 return LEGACY_SIM_REGNO_IGNORE
;
394 /* Register set support functions. */
396 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
397 Write the register to REGCACHE. */
400 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
401 const gdb_byte
*regs
, size_t offset
, int regsize
)
403 if (regnum
!= -1 && offset
!= -1)
407 struct gdbarch
*gdbarch
= regcache
->arch ();
408 int gdb_regsize
= register_size (gdbarch
, regnum
);
409 if (gdb_regsize
< regsize
410 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
411 offset
+= regsize
- gdb_regsize
;
413 regcache
->raw_supply (regnum
, regs
+ offset
);
417 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
418 in a field REGSIZE wide. Zero pad as necessary. */
421 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
422 gdb_byte
*regs
, size_t offset
, int regsize
)
424 if (regnum
!= -1 && offset
!= -1)
428 struct gdbarch
*gdbarch
= regcache
->arch ();
429 int gdb_regsize
= register_size (gdbarch
, regnum
);
430 if (gdb_regsize
< regsize
)
432 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
434 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
435 offset
+= regsize
- gdb_regsize
;
438 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
439 regsize
- gdb_regsize
);
442 regcache
->raw_collect (regnum
, regs
+ offset
);
447 ppc_greg_offset (struct gdbarch
*gdbarch
,
448 struct gdbarch_tdep
*tdep
,
449 const struct ppc_reg_offsets
*offsets
,
453 *regsize
= offsets
->gpr_size
;
454 if (regnum
>= tdep
->ppc_gp0_regnum
455 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
456 return (offsets
->r0_offset
457 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
459 if (regnum
== gdbarch_pc_regnum (gdbarch
))
460 return offsets
->pc_offset
;
462 if (regnum
== tdep
->ppc_ps_regnum
)
463 return offsets
->ps_offset
;
465 if (regnum
== tdep
->ppc_lr_regnum
)
466 return offsets
->lr_offset
;
468 if (regnum
== tdep
->ppc_ctr_regnum
)
469 return offsets
->ctr_offset
;
471 *regsize
= offsets
->xr_size
;
472 if (regnum
== tdep
->ppc_cr_regnum
)
473 return offsets
->cr_offset
;
475 if (regnum
== tdep
->ppc_xer_regnum
)
476 return offsets
->xer_offset
;
478 if (regnum
== tdep
->ppc_mq_regnum
)
479 return offsets
->mq_offset
;
485 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
486 const struct ppc_reg_offsets
*offsets
,
489 if (regnum
>= tdep
->ppc_fp0_regnum
490 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
491 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
493 if (regnum
== tdep
->ppc_fpscr_regnum
)
494 return offsets
->fpscr_offset
;
499 /* Supply register REGNUM in the general-purpose register set REGSET
500 from the buffer specified by GREGS and LEN to register cache
501 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
504 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
505 int regnum
, const void *gregs
, size_t len
)
507 struct gdbarch
*gdbarch
= regcache
->arch ();
508 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
509 const struct ppc_reg_offsets
*offsets
510 = (const struct ppc_reg_offsets
*) regset
->regmap
;
517 int gpr_size
= offsets
->gpr_size
;
519 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
520 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
521 i
++, offset
+= gpr_size
)
522 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
525 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
526 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
527 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
528 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
529 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
530 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
531 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
532 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
533 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
534 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
536 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
537 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
539 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
540 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
545 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
546 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
549 /* Supply register REGNUM in the floating-point register set REGSET
550 from the buffer specified by FPREGS and LEN to register cache
551 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
554 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
555 int regnum
, const void *fpregs
, size_t len
)
557 struct gdbarch
*gdbarch
= regcache
->arch ();
558 struct gdbarch_tdep
*tdep
;
559 const struct ppc_reg_offsets
*offsets
;
562 if (!ppc_floating_point_unit_p (gdbarch
))
565 tdep
= gdbarch_tdep (gdbarch
);
566 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
571 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
572 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
574 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
576 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
577 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
578 offsets
->fpscr_size
);
582 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
583 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
584 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
587 /* Collect register REGNUM in the general-purpose register set
588 REGSET from register cache REGCACHE into the buffer specified by
589 GREGS and LEN. If REGNUM is -1, do this for all registers in
593 ppc_collect_gregset (const struct regset
*regset
,
594 const struct regcache
*regcache
,
595 int regnum
, void *gregs
, size_t len
)
597 struct gdbarch
*gdbarch
= regcache
->arch ();
598 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
599 const struct ppc_reg_offsets
*offsets
600 = (const struct ppc_reg_offsets
*) regset
->regmap
;
607 int gpr_size
= offsets
->gpr_size
;
609 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
610 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
611 i
++, offset
+= gpr_size
)
612 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
614 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
615 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
616 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
617 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
618 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
619 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
620 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
621 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
622 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
623 (gdb_byte
*) gregs
, offsets
->cr_offset
,
625 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
626 (gdb_byte
*) gregs
, offsets
->xer_offset
,
628 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
629 (gdb_byte
*) gregs
, offsets
->mq_offset
,
634 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
635 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
638 /* Collect register REGNUM in the floating-point register set
639 REGSET from register cache REGCACHE into the buffer specified by
640 FPREGS and LEN. If REGNUM is -1, do this for all registers in
644 ppc_collect_fpregset (const struct regset
*regset
,
645 const struct regcache
*regcache
,
646 int regnum
, void *fpregs
, size_t len
)
648 struct gdbarch
*gdbarch
= regcache
->arch ();
649 struct gdbarch_tdep
*tdep
;
650 const struct ppc_reg_offsets
*offsets
;
653 if (!ppc_floating_point_unit_p (gdbarch
))
656 tdep
= gdbarch_tdep (gdbarch
);
657 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
662 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
663 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
665 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
667 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
668 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
669 offsets
->fpscr_size
);
673 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
674 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
675 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
679 insn_changes_sp_or_jumps (unsigned long insn
)
681 int opcode
= (insn
>> 26) & 0x03f;
682 int sd
= (insn
>> 21) & 0x01f;
683 int a
= (insn
>> 16) & 0x01f;
684 int subcode
= (insn
>> 1) & 0x3ff;
686 /* Changes the stack pointer. */
688 /* NOTE: There are many ways to change the value of a given register.
689 The ways below are those used when the register is R1, the SP,
690 in a funtion's epilogue. */
692 if (opcode
== 31 && subcode
== 444 && a
== 1)
693 return 1; /* mr R1,Rn */
694 if (opcode
== 14 && sd
== 1)
695 return 1; /* addi R1,Rn,simm */
696 if (opcode
== 58 && sd
== 1)
697 return 1; /* ld R1,ds(Rn) */
699 /* Transfers control. */
705 if (opcode
== 19 && subcode
== 16)
707 if (opcode
== 19 && subcode
== 528)
708 return 1; /* bcctr */
713 /* Return true if we are in the function's epilogue, i.e. after the
714 instruction that destroyed the function's stack frame.
716 1) scan forward from the point of execution:
717 a) If you find an instruction that modifies the stack pointer
718 or transfers control (except a return), execution is not in
720 b) Stop scanning if you find a return instruction or reach the
721 end of the function or reach the hard limit for the size of
723 2) scan backward from the point of execution:
724 a) If you find an instruction that modifies the stack pointer,
725 execution *is* in an epilogue, return.
726 b) Stop scanning if you reach an instruction that transfers
727 control or the beginning of the function or reach the hard
728 limit for the size of an epilogue. */
731 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
732 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
735 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
736 bfd_byte insn_buf
[PPC_INSN_SIZE
];
737 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
740 /* Find the search limits based on function boundaries and hard limit. */
742 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
745 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
746 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
748 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
749 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
751 /* Scan forward until next 'blr'. */
753 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
755 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
757 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
758 if (insn
== 0x4e800020)
760 /* Assume a bctr is a tail call unless it points strictly within
762 if (insn
== 0x4e800420)
764 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
765 tdep
->ppc_ctr_regnum
);
766 if (ctr
> func_start
&& ctr
< func_end
)
771 if (insn_changes_sp_or_jumps (insn
))
775 /* Scan backward until adjustment to stack pointer (R1). */
777 for (scan_pc
= pc
- PPC_INSN_SIZE
;
778 scan_pc
>= epilogue_start
;
779 scan_pc
-= PPC_INSN_SIZE
)
781 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
783 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
784 if (insn_changes_sp_or_jumps (insn
))
791 /* Implement the stack_frame_destroyed_p gdbarch method. */
794 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
796 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
800 /* Get the ith function argument for the current function. */
802 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
805 return get_frame_register_unsigned (frame
, 3 + argi
);
808 /* Sequence of bytes for breakpoint instruction. */
810 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
811 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
813 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
816 /* Instruction masks for displaced stepping. */
817 #define BRANCH_MASK 0xfc000000
818 #define BP_MASK 0xFC0007FE
819 #define B_INSN 0x48000000
820 #define BC_INSN 0x40000000
821 #define BXL_INSN 0x4c000000
822 #define BP_INSN 0x7C000008
824 /* Instruction masks used during single-stepping of atomic
826 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
827 #define LWARX_INSTRUCTION 0x7c000028
828 #define LDARX_INSTRUCTION 0x7c0000A8
829 #define LBARX_INSTRUCTION 0x7c000068
830 #define LHARX_INSTRUCTION 0x7c0000e8
831 #define LQARX_INSTRUCTION 0x7c000228
832 #define STORE_CONDITIONAL_MASK 0xfc0007ff
833 #define STWCX_INSTRUCTION 0x7c00012d
834 #define STDCX_INSTRUCTION 0x7c0001ad
835 #define STBCX_INSTRUCTION 0x7c00056d
836 #define STHCX_INSTRUCTION 0x7c0005ad
837 #define STQCX_INSTRUCTION 0x7c00016d
839 /* Check if insn is one of the Load And Reserve instructions used for atomic
841 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
842 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
843 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
844 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
845 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
846 /* Check if insn is one of the Store Conditional instructions used for atomic
848 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
849 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
850 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
851 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
852 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
854 typedef buf_displaced_step_closure ppc_displaced_step_closure
;
856 /* We can't displaced step atomic sequences. */
858 static displaced_step_closure_up
859 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
860 CORE_ADDR from
, CORE_ADDR to
,
861 struct regcache
*regs
)
863 size_t len
= gdbarch_max_insn_length (gdbarch
);
864 std::unique_ptr
<ppc_displaced_step_closure
> closure
865 (new ppc_displaced_step_closure (len
));
866 gdb_byte
*buf
= closure
->buf
.data ();
867 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
870 read_memory (from
, buf
, len
);
872 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
874 /* Assume all atomic sequences start with a Load and Reserve instruction. */
875 if (IS_LOAD_AND_RESERVE_INSN (insn
))
879 fprintf_unfiltered (gdb_stdlog
,
880 "displaced: can't displaced step "
881 "atomic sequence at %s\n",
882 paddress (gdbarch
, from
));
888 write_memory (to
, buf
, len
);
892 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
893 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
894 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
897 /* This is a work around for a problem with g++ 4.8. */
898 return displaced_step_closure_up (closure
.release ());
901 /* Fix up the state of registers and memory after having single-stepped
902 a displaced instruction. */
904 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
905 struct displaced_step_closure
*closure_
,
906 CORE_ADDR from
, CORE_ADDR to
,
907 struct regcache
*regs
)
909 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
910 /* Our closure is a copy of the instruction. */
911 ppc_displaced_step_closure
*closure
= (ppc_displaced_step_closure
*) closure_
;
912 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
913 PPC_INSN_SIZE
, byte_order
);
915 /* Offset for non PC-relative instructions. */
916 LONGEST offset
= PPC_INSN_SIZE
;
918 opcode
= insn
& BRANCH_MASK
;
921 fprintf_unfiltered (gdb_stdlog
,
922 "displaced: (ppc) fixup (%s, %s)\n",
923 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
926 /* Handle PC-relative branch instructions. */
927 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
931 /* Read the current PC value after the instruction has been executed
932 in a displaced location. Calculate the offset to be applied to the
933 original PC value before the displaced stepping. */
934 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
936 offset
= current_pc
- to
;
938 if (opcode
!= BXL_INSN
)
940 /* Check for AA bit indicating whether this is an absolute
941 addressing or PC-relative (1: absolute, 0: relative). */
944 /* PC-relative addressing is being used in the branch. */
948 "displaced: (ppc) branch instruction: %s\n"
949 "displaced: (ppc) adjusted PC from %s to %s\n",
950 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
951 paddress (gdbarch
, from
+ offset
));
953 regcache_cooked_write_unsigned (regs
,
954 gdbarch_pc_regnum (gdbarch
),
960 /* If we're here, it means we have a branch to LR or CTR. If the
961 branch was taken, the offset is probably greater than 4 (the next
962 instruction), so it's safe to assume that an offset of 4 means we
963 did not take the branch. */
964 if (offset
== PPC_INSN_SIZE
)
965 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
966 from
+ PPC_INSN_SIZE
);
969 /* Check for LK bit indicating whether we should set the link
970 register to point to the next instruction
971 (1: Set, 0: Don't set). */
974 /* Link register needs to be set to the next instruction's PC. */
975 regcache_cooked_write_unsigned (regs
,
976 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
977 from
+ PPC_INSN_SIZE
);
979 fprintf_unfiltered (gdb_stdlog
,
980 "displaced: (ppc) adjusted LR to %s\n",
981 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
985 /* Check for breakpoints in the inferior. If we've found one, place the PC
986 right at the breakpoint instruction. */
987 else if ((insn
& BP_MASK
) == BP_INSN
)
988 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
990 /* Handle any other instructions that do not fit in the categories above. */
991 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
995 /* Always use hardware single-stepping to execute the
996 displaced instruction. */
998 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
999 struct displaced_step_closure
*closure
)
1004 /* Checks for an atomic sequence of instructions beginning with a
1005 Load And Reserve instruction and ending with a Store Conditional
1006 instruction. If such a sequence is found, attempt to step through it.
1007 A breakpoint is placed at the end of the sequence. */
1008 std::vector
<CORE_ADDR
>
1009 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1011 struct gdbarch
*gdbarch
= regcache
->arch ();
1012 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1013 CORE_ADDR pc
= regcache_read_pc (regcache
);
1014 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1016 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1017 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1020 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1021 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1022 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1024 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1025 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1028 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1030 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1032 loc
+= PPC_INSN_SIZE
;
1033 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1035 /* Assume that there is at most one conditional branch in the atomic
1036 sequence. If a conditional branch is found, put a breakpoint in
1037 its destination address. */
1038 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1040 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1041 int absolute
= insn
& 2;
1043 if (bc_insn_count
>= 1)
1044 return {}; /* More than one conditional branch found, fallback
1045 to the standard single-step code. */
1048 breaks
[1] = immediate
;
1050 breaks
[1] = loc
+ immediate
;
1056 if (IS_STORE_CONDITIONAL_INSN (insn
))
1060 /* Assume that the atomic sequence ends with a Store Conditional
1062 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1066 loc
+= PPC_INSN_SIZE
;
1068 /* Insert a breakpoint right after the end of the atomic sequence. */
1071 /* Check for duplicated breakpoints. Check also for a breakpoint
1072 placed (branch instruction's destination) anywhere in sequence. */
1074 && (breaks
[1] == breaks
[0]
1075 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1076 last_breakpoint
= 0;
1078 std::vector
<CORE_ADDR
> next_pcs
;
1080 for (index
= 0; index
<= last_breakpoint
; index
++)
1081 next_pcs
.push_back (breaks
[index
]);
1087 #define SIGNED_SHORT(x) \
1088 ((sizeof (short) == 2) \
1089 ? ((int)(short)(x)) \
1090 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1092 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1094 /* Limit the number of skipped non-prologue instructions, as the examining
1095 of the prologue is expensive. */
1096 static int max_skip_non_prologue_insns
= 10;
1098 /* Return nonzero if the given instruction OP can be part of the prologue
1099 of a function and saves a parameter on the stack. FRAMEP should be
1100 set if one of the previous instructions in the function has set the
1104 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1106 /* Move parameters from argument registers to temporary register. */
1107 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1109 /* Rx must be scratch register r0. */
1110 const int rx_regno
= (op
>> 16) & 31;
1111 /* Ry: Only r3 - r10 are used for parameter passing. */
1112 const int ry_regno
= GET_SRC_REG (op
);
1114 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1116 *r0_contains_arg
= 1;
1123 /* Save a General Purpose Register on stack. */
1125 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1126 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1128 /* Rx: Only r3 - r10 are used for parameter passing. */
1129 const int rx_regno
= GET_SRC_REG (op
);
1131 return (rx_regno
>= 3 && rx_regno
<= 10);
1134 /* Save a General Purpose Register on stack via the Frame Pointer. */
1137 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1138 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1139 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1141 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1142 However, the compiler sometimes uses r0 to hold an argument. */
1143 const int rx_regno
= GET_SRC_REG (op
);
1145 return ((rx_regno
>= 3 && rx_regno
<= 10)
1146 || (rx_regno
== 0 && *r0_contains_arg
));
1149 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1151 /* Only f2 - f8 are used for parameter passing. */
1152 const int src_regno
= GET_SRC_REG (op
);
1154 return (src_regno
>= 2 && src_regno
<= 8);
1157 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1159 /* Only f2 - f8 are used for parameter passing. */
1160 const int src_regno
= GET_SRC_REG (op
);
1162 return (src_regno
>= 2 && src_regno
<= 8);
1165 /* Not an insn that saves a parameter on stack. */
1169 /* Assuming that INSN is a "bl" instruction located at PC, return
1170 nonzero if the destination of the branch is a "blrl" instruction.
1172 This sequence is sometimes found in certain function prologues.
1173 It allows the function to load the LR register with a value that
1174 they can use to access PIC data using PC-relative offsets. */
1177 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1184 absolute
= (int) ((insn
>> 1) & 1);
1185 immediate
= ((insn
& ~3) << 6) >> 6;
1189 dest
= pc
+ immediate
;
1191 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1192 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1198 /* Return true if OP is a stw or std instruction with
1199 register operands RS and RA and any immediate offset.
1201 If WITH_UPDATE is true, also return true if OP is
1202 a stwu or stdu instruction with the same operands.
1204 Return false otherwise.
1207 store_insn_p (unsigned long op
, unsigned long rs
,
1208 unsigned long ra
, bool with_update
)
1213 if (/* std RS, SIMM(RA) */
1214 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1215 /* stw RS, SIMM(RA) */
1216 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1221 if (/* stdu RS, SIMM(RA) */
1222 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1223 /* stwu RS, SIMM(RA) */
1224 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1231 /* Masks for decoding a branch-and-link (bl) instruction.
1233 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1234 The former is anded with the opcode in question; if the result of
1235 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1236 question is a ``bl'' instruction.
1238 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
1239 the branch displacement. */
1241 #define BL_MASK 0xfc000001
1242 #define BL_INSTRUCTION 0x48000001
1243 #define BL_DISPLACEMENT_MASK 0x03fffffc
1245 static unsigned long
1246 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1248 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1252 /* Fetch the instruction and convert it to an integer. */
1253 if (target_read_memory (pc
, buf
, 4))
1255 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1260 /* GCC generates several well-known sequences of instructions at the begining
1261 of each function prologue when compiling with -fstack-check. If one of
1262 such sequences starts at START_PC, then return the address of the
1263 instruction immediately past this sequence. Otherwise, return START_PC. */
1266 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1268 CORE_ADDR pc
= start_pc
;
1269 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1271 /* First possible sequence: A small number of probes.
1272 stw 0, -<some immediate>(1)
1273 [repeat this instruction any (small) number of times]. */
1275 if ((op
& 0xffff0000) == 0x90010000)
1277 while ((op
& 0xffff0000) == 0x90010000)
1280 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1285 /* Second sequence: A probing loop.
1286 addi 12,1,-<some immediate>
1287 lis 0,-<some immediate>
1288 [possibly ori 0,0,<some immediate>]
1292 addi 12,12,-<some immediate>
1295 [possibly one last probe: stw 0,<some immediate>(12)]. */
1299 /* addi 12,1,-<some immediate> */
1300 if ((op
& 0xffff0000) != 0x39810000)
1303 /* lis 0,-<some immediate> */
1305 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1306 if ((op
& 0xffff0000) != 0x3c000000)
1310 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1311 /* [possibly ori 0,0,<some immediate>] */
1312 if ((op
& 0xffff0000) == 0x60000000)
1315 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1318 if (op
!= 0x7c0c0214)
1323 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1324 if (op
!= 0x7c0c0000)
1329 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1330 if ((op
& 0xff9f0001) != 0x41820000)
1333 /* addi 12,12,-<some immediate> */
1335 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1336 if ((op
& 0xffff0000) != 0x398c0000)
1341 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1342 if (op
!= 0x900c0000)
1347 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1348 if ((op
& 0xfc000001) != 0x48000000)
1351 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1353 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1354 if ((op
& 0xffff0000) == 0x900c0000)
1357 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1360 /* We found a valid stack-check sequence, return the new PC. */
1364 /* Third sequence: No probe; instead, a comparison between the stack size
1365 limit (saved in a run-time global variable) and the current stack
1368 addi 0,1,-<some immediate>
1369 lis 12,__gnat_stack_limit@ha
1370 lwz 12,__gnat_stack_limit@l(12)
1373 or, with a small variant in the case of a bigger stack frame:
1374 addis 0,1,<some immediate>
1375 addic 0,0,-<some immediate>
1376 lis 12,__gnat_stack_limit@ha
1377 lwz 12,__gnat_stack_limit@l(12)
1382 /* addi 0,1,-<some immediate> */
1383 if ((op
& 0xffff0000) != 0x38010000)
1385 /* small stack frame variant not recognized; try the
1386 big stack frame variant: */
1388 /* addis 0,1,<some immediate> */
1389 if ((op
& 0xffff0000) != 0x3c010000)
1392 /* addic 0,0,-<some immediate> */
1394 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1395 if ((op
& 0xffff0000) != 0x30000000)
1399 /* lis 12,<some immediate> */
1401 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1402 if ((op
& 0xffff0000) != 0x3d800000)
1405 /* lwz 12,<some immediate>(12) */
1407 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1408 if ((op
& 0xffff0000) != 0x818c0000)
1413 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1414 if ((op
& 0xfffffffe) != 0x7c406008)
1417 /* We found a valid stack-check sequence, return the new PC. */
1421 /* No stack check code in our prologue, return the start_pc. */
1425 /* return pc value after skipping a function prologue and also return
1426 information about a function frame.
1428 in struct rs6000_framedata fdata:
1429 - frameless is TRUE, if function does not have a frame.
1430 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1431 - offset is the initial size of this stack frame --- the amount by
1432 which we decrement the sp to allocate the frame.
1433 - saved_gpr is the number of the first saved gpr.
1434 - saved_fpr is the number of the first saved fpr.
1435 - saved_vr is the number of the first saved vr.
1436 - saved_ev is the number of the first saved ev.
1437 - alloca_reg is the number of the register used for alloca() handling.
1439 - gpr_offset is the offset of the first saved gpr from the previous frame.
1440 - fpr_offset is the offset of the first saved fpr from the previous frame.
1441 - vr_offset is the offset of the first saved vr from the previous frame.
1442 - ev_offset is the offset of the first saved ev from the previous frame.
1443 - lr_offset is the offset of the saved lr
1444 - cr_offset is the offset of the saved cr
1445 - vrsave_offset is the offset of the saved vrsave register. */
1448 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1449 struct rs6000_framedata
*fdata
)
1451 CORE_ADDR orig_pc
= pc
;
1452 CORE_ADDR last_prologue_pc
= pc
;
1453 CORE_ADDR li_found_pc
= 0;
1457 long alloca_reg_offset
= 0;
1458 long vr_saved_offset
= 0;
1464 int vrsave_reg
= -1;
1467 int minimal_toc_loaded
= 0;
1468 int prev_insn_was_prologue_insn
= 1;
1469 int num_skip_non_prologue_insns
= 0;
1470 int r0_contains_arg
= 0;
1471 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1472 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1473 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1475 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1476 fdata
->saved_gpr
= -1;
1477 fdata
->saved_fpr
= -1;
1478 fdata
->saved_vr
= -1;
1479 fdata
->saved_ev
= -1;
1480 fdata
->alloca_reg
= -1;
1481 fdata
->frameless
= 1;
1482 fdata
->nosavedpc
= 1;
1483 fdata
->lr_register
= -1;
1485 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1491 /* Sometimes it isn't clear if an instruction is a prologue
1492 instruction or not. When we encounter one of these ambiguous
1493 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1494 Otherwise, we'll assume that it really is a prologue instruction. */
1495 if (prev_insn_was_prologue_insn
)
1496 last_prologue_pc
= pc
;
1498 /* Stop scanning if we've hit the limit. */
1502 prev_insn_was_prologue_insn
= 1;
1504 /* Fetch the instruction and convert it to an integer. */
1505 if (target_read_memory (pc
, buf
, 4))
1507 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1509 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1511 /* Since shared library / PIC code, which needs to get its
1512 address at runtime, can appear to save more than one link
1526 remember just the first one, but skip over additional
1529 lr_reg
= (op
& 0x03e00000) >> 21;
1531 r0_contains_arg
= 0;
1534 else if ((op
& 0xfc1fffff) == 0x7c000026)
1536 cr_reg
= (op
& 0x03e00000) >> 21;
1538 r0_contains_arg
= 0;
1542 else if ((op
& 0xfc1f0000) == 0xd8010000)
1543 { /* stfd Rx,NUM(r1) */
1544 reg
= GET_SRC_REG (op
);
1545 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1547 fdata
->saved_fpr
= reg
;
1548 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1553 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1554 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1555 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1556 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1559 reg
= GET_SRC_REG (op
);
1560 if ((op
& 0xfc1f0000) == 0xbc010000)
1561 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1563 fdata
->gpr_mask
|= 1U << reg
;
1564 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1566 fdata
->saved_gpr
= reg
;
1567 if ((op
& 0xfc1f0003) == 0xf8010000)
1569 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1574 else if ((op
& 0xffff0000) == 0x3c4c0000
1575 || (op
& 0xffff0000) == 0x3c400000
1576 || (op
& 0xffff0000) == 0x38420000)
1578 /* . 0: addis 2,12,.TOC.-0b@ha
1579 . addi 2,2,.TOC.-0b@l
1583 used by ELFv2 global entry points to set up r2. */
1586 else if (op
== 0x60000000)
1589 /* Allow nops in the prologue, but do not consider them to
1590 be part of the prologue unless followed by other prologue
1592 prev_insn_was_prologue_insn
= 0;
1596 else if ((op
& 0xffff0000) == 0x3c000000)
1597 { /* addis 0,0,NUM, used for >= 32k frames */
1598 fdata
->offset
= (op
& 0x0000ffff) << 16;
1599 fdata
->frameless
= 0;
1600 r0_contains_arg
= 0;
1604 else if ((op
& 0xffff0000) == 0x60000000)
1605 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1606 fdata
->offset
|= (op
& 0x0000ffff);
1607 fdata
->frameless
= 0;
1608 r0_contains_arg
= 0;
1612 else if (lr_reg
>= 0 &&
1613 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1615 (store_insn_p (op
, lr_reg
,
1616 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1619 if (store_insn_p (op
, lr_reg
, 1, true))
1620 fdata
->lr_offset
= offset
;
1621 else /* LR save through frame pointer. */
1622 fdata
->lr_offset
= alloca_reg_offset
;
1624 fdata
->nosavedpc
= 0;
1625 /* Invalidate lr_reg, but don't set it to -1.
1626 That would mean that it had never been set. */
1628 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1629 (op
& 0xfc000000) == 0x90000000) /* stw */
1631 /* Does not update r1, so add displacement to lr_offset. */
1632 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1637 else if (cr_reg
>= 0 &&
1638 (store_insn_p (op
, cr_reg
, 1, true)))
1640 fdata
->cr_offset
= offset
;
1641 /* Invalidate cr_reg, but don't set it to -1.
1642 That would mean that it had never been set. */
1644 if ((op
& 0xfc000003) == 0xf8000000 ||
1645 (op
& 0xfc000000) == 0x90000000)
1647 /* Does not update r1, so add displacement to cr_offset. */
1648 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1653 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1655 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1656 prediction bits. If the LR has already been saved, we can
1660 else if (op
== 0x48000005)
1667 else if (op
== 0x48000004)
1672 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1673 in V.4 -mminimal-toc */
1674 (op
& 0xffff0000) == 0x3bde0000)
1675 { /* addi 30,30,foo@l */
1679 else if ((op
& 0xfc000001) == 0x48000001)
1683 fdata
->frameless
= 0;
1685 /* If the return address has already been saved, we can skip
1686 calls to blrl (for PIC). */
1687 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1693 /* Don't skip over the subroutine call if it is not within
1694 the first three instructions of the prologue and either
1695 we have no line table information or the line info tells
1696 us that the subroutine call is not part of the line
1697 associated with the prologue. */
1698 if ((pc
- orig_pc
) > 8)
1700 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1701 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1703 if ((prologue_sal
.line
== 0)
1704 || (prologue_sal
.line
!= this_sal
.line
))
1708 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1710 /* At this point, make sure this is not a trampoline
1711 function (a function that simply calls another functions,
1712 and nothing else). If the next is not a nop, this branch
1713 was part of the function prologue. */
1715 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1716 break; /* Don't skip over
1722 /* update stack pointer */
1723 else if ((op
& 0xfc1f0000) == 0x94010000)
1724 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1725 fdata
->frameless
= 0;
1726 fdata
->offset
= SIGNED_SHORT (op
);
1727 offset
= fdata
->offset
;
1730 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1731 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1732 /* No way to figure out what r1 is going to be. */
1733 fdata
->frameless
= 0;
1734 offset
= fdata
->offset
;
1737 else if ((op
& 0xfc1f0003) == 0xf8010001)
1738 { /* stdu rX,NUM(r1) */
1739 fdata
->frameless
= 0;
1740 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1741 offset
= fdata
->offset
;
1744 else if ((op
& 0xffff0000) == 0x38210000)
1745 { /* addi r1,r1,SIMM */
1746 fdata
->frameless
= 0;
1747 fdata
->offset
+= SIGNED_SHORT (op
);
1748 offset
= fdata
->offset
;
1751 /* Load up minimal toc pointer. Do not treat an epilogue restore
1752 of r31 as a minimal TOC load. */
1753 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1754 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1756 && !minimal_toc_loaded
)
1758 minimal_toc_loaded
= 1;
1761 /* move parameters from argument registers to local variable
1764 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1765 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1766 (((op
>> 21) & 31) <= 10) &&
1767 ((long) ((op
>> 16) & 31)
1768 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1772 /* store parameters in stack */
1774 /* Move parameters from argument registers to temporary register. */
1775 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1779 /* Set up frame pointer */
1781 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1783 fdata
->frameless
= 0;
1785 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1786 alloca_reg_offset
= offset
;
1789 /* Another way to set up the frame pointer. */
1791 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1792 || op
== 0x7c3f0b78)
1794 fdata
->frameless
= 0;
1796 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1797 alloca_reg_offset
= offset
;
1800 /* Another way to set up the frame pointer. */
1802 else if ((op
& 0xfc1fffff) == 0x38010000)
1803 { /* addi rX, r1, 0x0 */
1804 fdata
->frameless
= 0;
1806 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1807 + ((op
& ~0x38010000) >> 21));
1808 alloca_reg_offset
= offset
;
1811 /* AltiVec related instructions. */
1812 /* Store the vrsave register (spr 256) in another register for
1813 later manipulation, or load a register into the vrsave
1814 register. 2 instructions are used: mfvrsave and
1815 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1816 and mtspr SPR256, Rn. */
1817 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1818 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1819 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1821 vrsave_reg
= GET_SRC_REG (op
);
1824 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1828 /* Store the register where vrsave was saved to onto the stack:
1829 rS is the register where vrsave was stored in a previous
1831 /* 100100 sssss 00001 dddddddd dddddddd */
1832 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1834 if (vrsave_reg
== GET_SRC_REG (op
))
1836 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1841 /* Compute the new value of vrsave, by modifying the register
1842 where vrsave was saved to. */
1843 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1844 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1848 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1849 in a pair of insns to save the vector registers on the
1851 /* 001110 00000 00000 iiii iiii iiii iiii */
1852 /* 001110 01110 00000 iiii iiii iiii iiii */
1853 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1854 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1856 if ((op
& 0xffff0000) == 0x38000000)
1857 r0_contains_arg
= 0;
1859 vr_saved_offset
= SIGNED_SHORT (op
);
1861 /* This insn by itself is not part of the prologue, unless
1862 if part of the pair of insns mentioned above. So do not
1863 record this insn as part of the prologue yet. */
1864 prev_insn_was_prologue_insn
= 0;
1866 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1867 /* 011111 sssss 11111 00000 00111001110 */
1868 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1870 if (pc
== (li_found_pc
+ 4))
1872 vr_reg
= GET_SRC_REG (op
);
1873 /* If this is the first vector reg to be saved, or if
1874 it has a lower number than others previously seen,
1875 reupdate the frame info. */
1876 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1878 fdata
->saved_vr
= vr_reg
;
1879 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1881 vr_saved_offset
= -1;
1886 /* End AltiVec related instructions. */
1888 /* Start BookE related instructions. */
1889 /* Store gen register S at (r31+uimm).
1890 Any register less than r13 is volatile, so we don't care. */
1891 /* 000100 sssss 11111 iiiii 01100100001 */
1892 else if (arch_info
->mach
== bfd_mach_ppc_e500
1893 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1895 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1898 ev_reg
= GET_SRC_REG (op
);
1899 imm
= (op
>> 11) & 0x1f;
1900 ev_offset
= imm
* 8;
1901 /* If this is the first vector reg to be saved, or if
1902 it has a lower number than others previously seen,
1903 reupdate the frame info. */
1904 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1906 fdata
->saved_ev
= ev_reg
;
1907 fdata
->ev_offset
= ev_offset
+ offset
;
1912 /* Store gen register rS at (r1+rB). */
1913 /* 000100 sssss 00001 bbbbb 01100100000 */
1914 else if (arch_info
->mach
== bfd_mach_ppc_e500
1915 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1917 if (pc
== (li_found_pc
+ 4))
1919 ev_reg
= GET_SRC_REG (op
);
1920 /* If this is the first vector reg to be saved, or if
1921 it has a lower number than others previously seen,
1922 reupdate the frame info. */
1923 /* We know the contents of rB from the previous instruction. */
1924 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1926 fdata
->saved_ev
= ev_reg
;
1927 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1929 vr_saved_offset
= -1;
1935 /* Store gen register r31 at (rA+uimm). */
1936 /* 000100 11111 aaaaa iiiii 01100100001 */
1937 else if (arch_info
->mach
== bfd_mach_ppc_e500
1938 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1940 /* Wwe know that the source register is 31 already, but
1941 it can't hurt to compute it. */
1942 ev_reg
= GET_SRC_REG (op
);
1943 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1944 /* If this is the first vector reg to be saved, or if
1945 it has a lower number than others previously seen,
1946 reupdate the frame info. */
1947 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1949 fdata
->saved_ev
= ev_reg
;
1950 fdata
->ev_offset
= ev_offset
+ offset
;
1955 /* Store gen register S at (r31+r0).
1956 Store param on stack when offset from SP bigger than 4 bytes. */
1957 /* 000100 sssss 11111 00000 01100100000 */
1958 else if (arch_info
->mach
== bfd_mach_ppc_e500
1959 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1961 if (pc
== (li_found_pc
+ 4))
1963 if ((op
& 0x03e00000) >= 0x01a00000)
1965 ev_reg
= GET_SRC_REG (op
);
1966 /* If this is the first vector reg to be saved, or if
1967 it has a lower number than others previously seen,
1968 reupdate the frame info. */
1969 /* We know the contents of r0 from the previous
1971 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1973 fdata
->saved_ev
= ev_reg
;
1974 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1978 vr_saved_offset
= -1;
1983 /* End BookE related instructions. */
1987 /* Not a recognized prologue instruction.
1988 Handle optimizer code motions into the prologue by continuing
1989 the search if we have no valid frame yet or if the return
1990 address is not yet saved in the frame. Also skip instructions
1991 if some of the GPRs expected to be saved are not yet saved. */
1992 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
1993 && fdata
->saved_gpr
!= -1)
1995 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
1997 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
2001 if (op
== 0x4e800020 /* blr */
2002 || op
== 0x4e800420) /* bctr */
2003 /* Do not scan past epilogue in frameless functions or
2006 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2007 /* Never skip branches. */
2010 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2011 /* Do not scan too many insns, scanning insns is expensive with
2015 /* Continue scanning. */
2016 prev_insn_was_prologue_insn
= 0;
2022 /* I have problems with skipping over __main() that I need to address
2023 * sometime. Previously, I used to use misc_function_vector which
2024 * didn't work as well as I wanted to be. -MGO */
2026 /* If the first thing after skipping a prolog is a branch to a function,
2027 this might be a call to an initializer in main(), introduced by gcc2.
2028 We'd like to skip over it as well. Fortunately, xlc does some extra
2029 work before calling a function right after a prologue, thus we can
2030 single out such gcc2 behaviour. */
2033 if ((op
& 0xfc000001) == 0x48000001)
2034 { /* bl foo, an initializer function? */
2035 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2037 if (op
== 0x4def7b82)
2038 { /* cror 0xf, 0xf, 0xf (nop) */
2040 /* Check and see if we are in main. If so, skip over this
2041 initializer function as well. */
2043 tmp
= find_pc_misc_function (pc
);
2045 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2051 if (pc
== lim_pc
&& lr_reg
>= 0)
2052 fdata
->lr_register
= lr_reg
;
2054 fdata
->offset
= -fdata
->offset
;
2055 return last_prologue_pc
;
2059 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2061 struct rs6000_framedata frame
;
2062 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2064 /* See if we can determine the end of the prologue via the symbol table.
2065 If so, then return either PC, or the PC after the prologue, whichever
2067 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2069 CORE_ADDR post_prologue_pc
2070 = skip_prologue_using_sal (gdbarch
, func_addr
);
2071 if (post_prologue_pc
!= 0)
2072 return std::max (pc
, post_prologue_pc
);
2075 /* Can't determine prologue from the symbol table, need to examine
2078 /* Find an upper limit on the function prologue using the debug
2079 information. If the debug information could not be used to provide
2080 that bound, then use an arbitrary large number as the upper bound. */
2081 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2083 limit_pc
= pc
+ 100; /* Magic. */
2085 /* Do not allow limit_pc to be past the function end, if we know
2086 where that end is... */
2087 if (func_end_addr
&& limit_pc
> func_end_addr
)
2088 limit_pc
= func_end_addr
;
2090 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2094 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2095 in the prologue of main().
2097 The function below examines the code pointed at by PC and checks to
2098 see if it corresponds to a call to __eabi. If so, it returns the
2099 address of the instruction following that call. Otherwise, it simply
2103 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2105 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2109 if (target_read_memory (pc
, buf
, 4))
2111 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2113 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2115 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2116 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2117 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2119 /* We check for ___eabi (three leading underscores) in addition
2120 to __eabi in case the GCC option "-fleading-underscore" was
2121 used to compile the program. */
2122 if (s
.minsym
!= NULL
2123 && s
.minsym
->linkage_name () != NULL
2124 && (strcmp (s
.minsym
->linkage_name (), "__eabi") == 0
2125 || strcmp (s
.minsym
->linkage_name (), "___eabi") == 0))
2131 /* All the ABI's require 16 byte alignment. */
2133 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2135 return (addr
& -16);
2138 /* Return whether handle_inferior_event() should proceed through code
2139 starting at PC in function NAME when stepping.
2141 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2142 handle memory references that are too distant to fit in instructions
2143 generated by the compiler. For example, if 'foo' in the following
2148 is greater than 32767, the linker might replace the lwz with a branch to
2149 somewhere in @FIX1 that does the load in 2 instructions and then branches
2150 back to where execution should continue.
2152 GDB should silently step over @FIX code, just like AIX dbx does.
2153 Unfortunately, the linker uses the "b" instruction for the
2154 branches, meaning that the link register doesn't get set.
2155 Therefore, GDB's usual step_over_function () mechanism won't work.
2157 Instead, use the gdbarch_skip_trampoline_code and
2158 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2162 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2163 CORE_ADDR pc
, const char *name
)
2165 return name
&& startswith (name
, "@FIX");
2168 /* Skip code that the user doesn't want to see when stepping:
2170 1. Indirect function calls use a piece of trampoline code to do context
2171 switching, i.e. to set the new TOC table. Skip such code if we are on
2172 its first instruction (as when we have single-stepped to here).
2174 2. Skip shared library trampoline code (which is different from
2175 indirect function call trampolines).
2177 3. Skip bigtoc fixup code.
2179 Result is desired PC to step until, or NULL if we are not in
2180 code that should be skipped. */
2183 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2185 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2187 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2188 unsigned int ii
, op
;
2190 CORE_ADDR solib_target_pc
;
2191 struct bound_minimal_symbol msymbol
;
2193 static unsigned trampoline_code
[] =
2195 0x800b0000, /* l r0,0x0(r11) */
2196 0x90410014, /* st r2,0x14(r1) */
2197 0x7c0903a6, /* mtctr r0 */
2198 0x804b0004, /* l r2,0x4(r11) */
2199 0x816b0008, /* l r11,0x8(r11) */
2200 0x4e800420, /* bctr */
2201 0x4e800020, /* br */
2205 /* Check for bigtoc fixup code. */
2206 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2208 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2209 msymbol
.minsym
->linkage_name ()))
2211 /* Double-check that the third instruction from PC is relative "b". */
2212 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2213 if ((op
& 0xfc000003) == 0x48000000)
2215 /* Extract bits 6-29 as a signed 24-bit relative word address and
2216 add it to the containing PC. */
2217 rel
= ((int)(op
<< 6) >> 6);
2218 return pc
+ 8 + rel
;
2222 /* If pc is in a shared library trampoline, return its target. */
2223 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2224 if (solib_target_pc
)
2225 return solib_target_pc
;
2227 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2229 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2230 if (op
!= trampoline_code
[ii
])
2233 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2235 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2239 /* ISA-specific vector types. */
2241 static struct type
*
2242 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2244 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2246 if (!tdep
->ppc_builtin_type_vec64
)
2248 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2250 /* The type we're building is this: */
2252 union __gdb_builtin_type_vec64
2256 int32_t v2_int32
[2];
2257 int16_t v4_int16
[4];
2264 t
= arch_composite_type (gdbarch
,
2265 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2266 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2267 append_composite_type_field (t
, "v2_float",
2268 init_vector_type (bt
->builtin_float
, 2));
2269 append_composite_type_field (t
, "v2_int32",
2270 init_vector_type (bt
->builtin_int32
, 2));
2271 append_composite_type_field (t
, "v4_int16",
2272 init_vector_type (bt
->builtin_int16
, 4));
2273 append_composite_type_field (t
, "v8_int8",
2274 init_vector_type (bt
->builtin_int8
, 8));
2276 TYPE_VECTOR (t
) = 1;
2277 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2278 tdep
->ppc_builtin_type_vec64
= t
;
2281 return tdep
->ppc_builtin_type_vec64
;
2284 /* Vector 128 type. */
2286 static struct type
*
2287 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2289 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2291 if (!tdep
->ppc_builtin_type_vec128
)
2293 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2295 /* The type we're building is this
2297 type = union __ppc_builtin_type_vec128 {
2299 double v2_double[2];
2301 int32_t v4_int32[4];
2302 int16_t v8_int16[8];
2303 int8_t v16_int8[16];
2309 t
= arch_composite_type (gdbarch
,
2310 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2311 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2312 append_composite_type_field (t
, "v2_double",
2313 init_vector_type (bt
->builtin_double
, 2));
2314 append_composite_type_field (t
, "v4_float",
2315 init_vector_type (bt
->builtin_float
, 4));
2316 append_composite_type_field (t
, "v4_int32",
2317 init_vector_type (bt
->builtin_int32
, 4));
2318 append_composite_type_field (t
, "v8_int16",
2319 init_vector_type (bt
->builtin_int16
, 8));
2320 append_composite_type_field (t
, "v16_int8",
2321 init_vector_type (bt
->builtin_int8
, 16));
2323 TYPE_VECTOR (t
) = 1;
2324 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2325 tdep
->ppc_builtin_type_vec128
= t
;
2328 return tdep
->ppc_builtin_type_vec128
;
2331 /* Return the name of register number REGNO, or the empty string if it
2332 is an anonymous register. */
2335 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2337 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2339 /* The upper half "registers" have names in the XML description,
2340 but we present only the low GPRs and the full 64-bit registers
2342 if (tdep
->ppc_ev0_upper_regnum
>= 0
2343 && tdep
->ppc_ev0_upper_regnum
<= regno
2344 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2347 /* Hide the upper halves of the vs0~vs31 registers. */
2348 if (tdep
->ppc_vsr0_regnum
>= 0
2349 && tdep
->ppc_vsr0_upper_regnum
<= regno
2350 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2353 /* Hide the upper halves of the cvs0~cvs31 registers. */
2354 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2355 && regno
< PPC_CVSR0_UPPER_REGNUM
+ ppc_num_gprs
)
2358 /* Check if the SPE pseudo registers are available. */
2359 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2361 static const char *const spe_regnames
[] = {
2362 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2363 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2364 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2365 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2367 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2370 /* Check if the decimal128 pseudo-registers are available. */
2371 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2373 static const char *const dfp128_regnames
[] = {
2374 "dl0", "dl1", "dl2", "dl3",
2375 "dl4", "dl5", "dl6", "dl7",
2376 "dl8", "dl9", "dl10", "dl11",
2377 "dl12", "dl13", "dl14", "dl15"
2379 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2382 /* Check if this is a vX alias for a raw vrX vector register. */
2383 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2385 static const char *const vector_alias_regnames
[] = {
2386 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2387 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2388 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2389 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2391 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2394 /* Check if this is a VSX pseudo-register. */
2395 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2397 static const char *const vsx_regnames
[] = {
2398 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2399 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2400 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2401 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2402 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2403 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2404 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2405 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2406 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2408 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2411 /* Check if the this is a Extended FP pseudo-register. */
2412 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2414 static const char *const efpr_regnames
[] = {
2415 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2416 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2417 "f46", "f47", "f48", "f49", "f50", "f51",
2418 "f52", "f53", "f54", "f55", "f56", "f57",
2419 "f58", "f59", "f60", "f61", "f62", "f63"
2421 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2424 /* Check if this is a Checkpointed DFP pseudo-register. */
2425 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2427 static const char *const cdfp128_regnames
[] = {
2428 "cdl0", "cdl1", "cdl2", "cdl3",
2429 "cdl4", "cdl5", "cdl6", "cdl7",
2430 "cdl8", "cdl9", "cdl10", "cdl11",
2431 "cdl12", "cdl13", "cdl14", "cdl15"
2433 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2436 /* Check if this is a Checkpointed VSX pseudo-register. */
2437 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2439 static const char *const cvsx_regnames
[] = {
2440 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2441 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2442 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2443 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2444 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2445 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2446 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2447 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2448 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2450 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2453 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2454 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2456 static const char *const cefpr_regnames
[] = {
2457 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2458 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2459 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2460 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2461 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2463 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2466 return tdesc_register_name (gdbarch
, regno
);
2469 /* Return the GDB type object for the "standard" data type of data in
2472 static struct type
*
2473 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2475 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2477 /* These are the e500 pseudo-registers. */
2478 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2479 return rs6000_builtin_type_vec64 (gdbarch
);
2480 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2481 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2482 /* PPC decimal128 pseudo-registers. */
2483 return builtin_type (gdbarch
)->builtin_declong
;
2484 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2485 return gdbarch_register_type (gdbarch
,
2486 tdep
->ppc_vr0_regnum
2488 - tdep
->ppc_v0_alias_regnum
));
2489 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2490 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2491 /* POWER7 VSX pseudo-registers. */
2492 return rs6000_builtin_type_vec128 (gdbarch
);
2493 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2494 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2495 /* POWER7 Extended FP pseudo-registers. */
2496 return builtin_type (gdbarch
)->builtin_double
;
2498 internal_error (__FILE__
, __LINE__
,
2499 _("rs6000_pseudo_register_type: "
2500 "called on unexpected register '%s' (%d)"),
2501 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2504 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2505 the vX aliases for the vector registers by always returning false
2506 to avoid duplicated information in "info register vector/all",
2507 since the raw vrX registers will already show in these cases. For
2508 other pseudo-registers we use the default membership function. */
2511 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2512 struct reggroup
*group
)
2514 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2516 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2519 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2522 /* The register format for RS/6000 floating point registers is always
2523 double, we need a conversion if the memory format is float. */
2526 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2529 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2531 return (tdep
->ppc_fp0_regnum
>= 0
2532 && regnum
>= tdep
->ppc_fp0_regnum
2533 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2534 && TYPE_CODE (type
) == TYPE_CODE_FLT
2535 && TYPE_LENGTH (type
)
2536 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2540 rs6000_register_to_value (struct frame_info
*frame
,
2544 int *optimizedp
, int *unavailablep
)
2546 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2547 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2549 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2551 if (!get_frame_register_bytes (frame
, regnum
, 0,
2552 register_size (gdbarch
, regnum
),
2553 from
, optimizedp
, unavailablep
))
2556 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2558 *optimizedp
= *unavailablep
= 0;
2563 rs6000_value_to_register (struct frame_info
*frame
,
2566 const gdb_byte
*from
)
2568 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2569 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2571 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2573 target_float_convert (from
, type
,
2574 to
, builtin_type (gdbarch
)->builtin_double
);
2575 put_frame_register (frame
, regnum
, to
);
2578 /* The type of a function that moves the value of REG between CACHE
2579 or BUF --- in either direction. */
2580 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2583 /* Move SPE vector register values between a 64-bit buffer and the two
2584 32-bit raw register halves in a regcache. This function handles
2585 both splitting a 64-bit value into two 32-bit halves, and joining
2586 two halves into a whole 64-bit value, depending on the function
2587 passed as the MOVE argument.
2589 EV_REG must be the number of an SPE evN vector register --- a
2590 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2593 Call MOVE once for each 32-bit half of that register, passing
2594 REGCACHE, the number of the raw register corresponding to that
2595 half, and the address of the appropriate half of BUFFER.
2597 For example, passing 'regcache_raw_read' as the MOVE function will
2598 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2599 'regcache_raw_supply' will supply the contents of BUFFER to the
2600 appropriate pair of raw registers in REGCACHE.
2602 You may need to cast away some 'const' qualifiers when passing
2603 MOVE, since this function can't tell at compile-time which of
2604 REGCACHE or BUFFER is acting as the source of the data. If C had
2605 co-variant type qualifiers, ... */
2607 static enum register_status
2608 e500_move_ev_register (move_ev_register_func move
,
2609 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2611 struct gdbarch
*arch
= regcache
->arch ();
2612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2614 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2615 enum register_status status
;
2617 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2619 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2621 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2623 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2625 if (status
== REG_VALID
)
2626 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2631 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2632 if (status
== REG_VALID
)
2633 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2640 static enum register_status
2641 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2643 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2648 static enum register_status
2649 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2650 int ev_reg
, gdb_byte
*buffer
)
2652 struct gdbarch
*arch
= regcache
->arch ();
2653 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2655 enum register_status status
;
2657 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2659 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2661 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2663 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2665 if (status
== REG_VALID
)
2666 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2671 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2672 if (status
== REG_VALID
)
2673 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2682 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2683 int reg_nr
, const gdb_byte
*buffer
)
2685 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2686 reg_nr
, (void *) buffer
);
2689 /* Read method for DFP pseudo-registers. */
2690 static enum register_status
2691 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2692 int reg_nr
, gdb_byte
*buffer
)
2694 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2696 enum register_status status
;
2698 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2700 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2701 fp0
= PPC_F0_REGNUM
;
2705 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2707 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2708 fp0
= PPC_CF0_REGNUM
;
2711 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2713 /* Read two FP registers to form a whole dl register. */
2714 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2715 if (status
== REG_VALID
)
2716 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2721 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2722 if (status
== REG_VALID
)
2723 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2729 /* Write method for DFP pseudo-registers. */
2731 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2732 int reg_nr
, const gdb_byte
*buffer
)
2734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2737 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2739 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2740 fp0
= PPC_F0_REGNUM
;
2744 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2746 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2747 fp0
= PPC_CF0_REGNUM
;
2750 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2752 /* Write each half of the dl register into a separate
2754 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2755 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2759 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2760 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2764 /* Read method for the vX aliases for the raw vrX registers. */
2766 static enum register_status
2767 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2768 readable_regcache
*regcache
, int reg_nr
,
2771 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2772 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2774 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2775 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2779 /* Write method for the vX aliases for the raw vrX registers. */
2782 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2783 struct regcache
*regcache
,
2784 int reg_nr
, const gdb_byte
*buffer
)
2786 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2787 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2789 regcache
->raw_write (tdep
->ppc_vr0_regnum
2790 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
2793 /* Read method for POWER7 VSX pseudo-registers. */
2794 static enum register_status
2795 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2796 int reg_nr
, gdb_byte
*buffer
)
2798 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2799 int reg_index
, vr0
, fp0
, vsr0_upper
;
2800 enum register_status status
;
2802 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2804 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2805 vr0
= PPC_VR0_REGNUM
;
2806 fp0
= PPC_F0_REGNUM
;
2807 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2811 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2813 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2814 vr0
= PPC_CVR0_REGNUM
;
2815 fp0
= PPC_CF0_REGNUM
;
2816 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2819 /* Read the portion that overlaps the VMX registers. */
2821 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
2823 /* Read the portion that overlaps the FPR registers. */
2824 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2826 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
2827 if (status
== REG_VALID
)
2828 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
2833 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
2834 if (status
== REG_VALID
)
2835 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
2841 /* Write method for POWER7 VSX pseudo-registers. */
2843 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2844 int reg_nr
, const gdb_byte
*buffer
)
2846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2847 int reg_index
, vr0
, fp0
, vsr0_upper
;
2849 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2851 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2852 vr0
= PPC_VR0_REGNUM
;
2853 fp0
= PPC_F0_REGNUM
;
2854 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2858 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2860 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2861 vr0
= PPC_CVR0_REGNUM
;
2862 fp0
= PPC_CF0_REGNUM
;
2863 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2866 /* Write the portion that overlaps the VMX registers. */
2868 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
2870 /* Write the portion that overlaps the FPR registers. */
2871 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2873 regcache
->raw_write (fp0
+ reg_index
, buffer
);
2874 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
2878 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
2879 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
2883 /* Read method for POWER7 Extended FP pseudo-registers. */
2884 static enum register_status
2885 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2886 int reg_nr
, gdb_byte
*buffer
)
2888 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2891 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2893 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2894 vr0
= PPC_VR0_REGNUM
;
2898 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2900 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2901 vr0
= PPC_CVR0_REGNUM
;
2904 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2906 /* Read the portion that overlaps the VMX register. */
2907 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
2908 register_size (gdbarch
, reg_nr
),
2912 /* Write method for POWER7 Extended FP pseudo-registers. */
2914 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2915 int reg_nr
, const gdb_byte
*buffer
)
2917 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2919 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2921 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2923 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2924 vr0
= PPC_VR0_REGNUM
;
2928 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2930 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2931 vr0
= PPC_CVR0_REGNUM
;
2933 /* The call to raw_write_part fails silently if the initial read
2934 of the read-update-write sequence returns an invalid status,
2935 so we check this manually and throw an error if needed. */
2936 regcache
->raw_update (vr0
+ reg_index
);
2937 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
2938 error (_("Cannot write to the checkpointed EFP register, "
2939 "the corresponding vector register is unavailable."));
2942 /* Write the portion that overlaps the VMX register. */
2943 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
2944 register_size (gdbarch
, reg_nr
), buffer
);
2947 static enum register_status
2948 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2949 readable_regcache
*regcache
,
2950 int reg_nr
, gdb_byte
*buffer
)
2952 struct gdbarch
*regcache_arch
= regcache
->arch ();
2953 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2955 gdb_assert (regcache_arch
== gdbarch
);
2957 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2958 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2959 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
2960 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
2961 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2962 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
2963 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
2965 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
2966 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
2967 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2968 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
2969 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
2970 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2972 internal_error (__FILE__
, __LINE__
,
2973 _("rs6000_pseudo_register_read: "
2974 "called on unexpected register '%s' (%d)"),
2975 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2979 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2980 struct regcache
*regcache
,
2981 int reg_nr
, const gdb_byte
*buffer
)
2983 struct gdbarch
*regcache_arch
= regcache
->arch ();
2984 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2986 gdb_assert (regcache_arch
== gdbarch
);
2988 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2989 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2990 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
2991 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
2992 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2993 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
2994 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2995 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
2996 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
2997 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2998 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
2999 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3000 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3002 internal_error (__FILE__
, __LINE__
,
3003 _("rs6000_pseudo_register_write: "
3004 "called on unexpected register '%s' (%d)"),
3005 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3008 /* Set the register mask in AX with the registers that form the DFP or
3009 checkpointed DFP pseudo-register REG_NR. */
3012 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3013 struct agent_expr
*ax
, int reg_nr
)
3015 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3018 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3020 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3021 fp0
= PPC_F0_REGNUM
;
3025 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3027 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3028 fp0
= PPC_CF0_REGNUM
;
3031 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3032 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3035 /* Set the register mask in AX with the raw vector register that
3036 corresponds to its REG_NR alias. */
3039 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3040 struct agent_expr
*ax
, int reg_nr
)
3042 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3043 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3045 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3046 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3049 /* Set the register mask in AX with the registers that form the VSX or
3050 checkpointed VSX pseudo-register REG_NR. */
3053 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3054 struct agent_expr
*ax
, int reg_nr
)
3056 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3057 int reg_index
, vr0
, fp0
, vsr0_upper
;
3059 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3061 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3062 vr0
= PPC_VR0_REGNUM
;
3063 fp0
= PPC_F0_REGNUM
;
3064 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3068 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3070 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3071 vr0
= PPC_CVR0_REGNUM
;
3072 fp0
= PPC_CF0_REGNUM
;
3073 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3078 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3082 ax_reg_mask (ax
, fp0
+ reg_index
);
3083 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3087 /* Set the register mask in AX with the register that corresponds to
3088 the EFP or checkpointed EFP pseudo-register REG_NR. */
3091 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3092 struct agent_expr
*ax
, int reg_nr
)
3094 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3097 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3099 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3100 vr0
= PPC_VR0_REGNUM
;
3104 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3106 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3107 vr0
= PPC_CVR0_REGNUM
;
3110 ax_reg_mask (ax
, vr0
+ reg_index
);
3114 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3115 struct agent_expr
*ax
, int reg_nr
)
3117 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3118 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3120 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3121 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3122 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3124 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3125 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3127 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3129 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3131 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3133 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3134 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3136 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3138 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3139 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3141 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3144 internal_error (__FILE__
, __LINE__
,
3145 _("rs6000_pseudo_register_collect: "
3146 "called on unexpected register '%s' (%d)"),
3147 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3153 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3154 struct agent_expr
*ax
, struct axs_value
*value
,
3157 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3158 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3159 value
->kind
= axs_lvalue_register
;
3160 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3164 /* Convert a DBX STABS register number to a GDB register number. */
3166 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3170 if (0 <= num
&& num
<= 31)
3171 return tdep
->ppc_gp0_regnum
+ num
;
3172 else if (32 <= num
&& num
<= 63)
3173 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3174 specifies registers the architecture doesn't have? Our
3175 callers don't check the value we return. */
3176 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3177 else if (77 <= num
&& num
<= 108)
3178 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3179 else if (1200 <= num
&& num
< 1200 + 32)
3180 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3185 return tdep
->ppc_mq_regnum
;
3187 return tdep
->ppc_lr_regnum
;
3189 return tdep
->ppc_ctr_regnum
;
3191 return tdep
->ppc_xer_regnum
;
3193 return tdep
->ppc_vrsave_regnum
;
3195 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3197 return tdep
->ppc_acc_regnum
;
3199 return tdep
->ppc_spefscr_regnum
;
3206 /* Convert a Dwarf 2 register number to a GDB register number. */
3208 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3210 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3212 if (0 <= num
&& num
<= 31)
3213 return tdep
->ppc_gp0_regnum
+ num
;
3214 else if (32 <= num
&& num
<= 63)
3215 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3216 specifies registers the architecture doesn't have? Our
3217 callers don't check the value we return. */
3218 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3219 else if (1124 <= num
&& num
< 1124 + 32)
3220 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3221 else if (1200 <= num
&& num
< 1200 + 32)
3222 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3227 return tdep
->ppc_cr_regnum
;
3229 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3231 return tdep
->ppc_acc_regnum
;
3233 return tdep
->ppc_mq_regnum
;
3235 return tdep
->ppc_xer_regnum
;
3237 return tdep
->ppc_lr_regnum
;
3239 return tdep
->ppc_ctr_regnum
;
3241 return tdep
->ppc_vrsave_regnum
;
3243 return tdep
->ppc_spefscr_regnum
;
3249 /* Translate a .eh_frame register to DWARF register, or adjust a
3250 .debug_frame register. */
3253 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3255 /* GCC releases before 3.4 use GCC internal register numbering in
3256 .debug_frame (and .debug_info, et cetera). The numbering is
3257 different from the standard SysV numbering for everything except
3258 for GPRs and FPRs. We can not detect this problem in most cases
3259 - to get accurate debug info for variables living in lr, ctr, v0,
3260 et cetera, use a newer version of GCC. But we must detect
3261 one important case - lr is in column 65 in .debug_frame output,
3264 GCC 3.4, and the "hammer" branch, have a related problem. They
3265 record lr register saves in .debug_frame as 108, but still record
3266 the return column as 65. We fix that up too.
3268 We can do this because 65 is assigned to fpsr, and GCC never
3269 generates debug info referring to it. To add support for
3270 handwritten debug info that restores fpsr, we would need to add a
3271 producer version check to this. */
3280 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3281 internal register numbering; translate that to the standard DWARF2
3282 register numbering. */
3283 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3285 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3286 return num
- 68 + 86;
3287 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3288 return num
- 77 + 1124;
3300 case 109: /* vrsave */
3302 case 110: /* vscr */
3304 case 111: /* spe_acc */
3306 case 112: /* spefscr */
3314 /* Handling the various POWER/PowerPC variants. */
3316 /* Information about a particular processor variant. */
3320 /* Name of this variant. */
3323 /* English description of the variant. */
3324 const char *description
;
3326 /* bfd_arch_info.arch corresponding to variant. */
3327 enum bfd_architecture arch
;
3329 /* bfd_arch_info.mach corresponding to variant. */
3332 /* Target description for this variant. */
3333 struct target_desc
**tdesc
;
3336 static struct variant variants
[] =
3338 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3339 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3340 {"power", "POWER user-level", bfd_arch_rs6000
,
3341 bfd_mach_rs6k
, &tdesc_rs6000
},
3342 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3343 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3344 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3345 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3346 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3347 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3348 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3349 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3350 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3351 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3352 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3353 604, &tdesc_powerpc_604
},
3354 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3355 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3356 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3357 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3358 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3359 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3360 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3361 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3362 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3363 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3364 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3365 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3368 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3369 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3370 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3371 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3372 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3373 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3374 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3375 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3376 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3377 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3378 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3379 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3381 /* FIXME: I haven't checked the register sets of the following. */
3382 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3383 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3384 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3385 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3386 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3387 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3389 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3392 /* Return the variant corresponding to architecture ARCH and machine number
3393 MACH. If no such variant exists, return null. */
3395 static const struct variant
*
3396 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3398 const struct variant
*v
;
3400 for (v
= variants
; v
->name
; v
++)
3401 if (arch
== v
->arch
&& mach
== v
->mach
)
3409 struct rs6000_frame_cache
3412 CORE_ADDR initial_sp
;
3413 struct trad_frame_saved_reg
*saved_regs
;
3415 /* Set BASE_P to true if this frame cache is properly initialized.
3416 Otherwise set to false because some registers or memory cannot
3419 /* Cache PC for building unavailable frame. */
3423 static struct rs6000_frame_cache
*
3424 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3426 struct rs6000_frame_cache
*cache
;
3427 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3428 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3429 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3430 struct rs6000_framedata fdata
;
3431 int wordsize
= tdep
->wordsize
;
3432 CORE_ADDR func
= 0, pc
= 0;
3434 if ((*this_cache
) != NULL
)
3435 return (struct rs6000_frame_cache
*) (*this_cache
);
3436 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3437 (*this_cache
) = cache
;
3439 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3443 func
= get_frame_func (this_frame
);
3445 pc
= get_frame_pc (this_frame
);
3446 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3448 /* Figure out the parent's stack pointer. */
3450 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3451 address of the current frame. Things might be easier if the
3452 ->frame pointed to the outer-most address of the frame. In
3453 the mean time, the address of the prev frame is used as the
3454 base address of this frame. */
3455 cache
->base
= get_frame_register_unsigned
3456 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3458 catch (const gdb_exception_error
&ex
)
3460 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3462 return (struct rs6000_frame_cache
*) (*this_cache
);
3465 /* If the function appears to be frameless, check a couple of likely
3466 indicators that we have simply failed to find the frame setup.
3467 Two common cases of this are missing symbols (i.e.
3468 get_frame_func returns the wrong address or 0), and assembly
3469 stubs which have a fast exit path but set up a frame on the slow
3472 If the LR appears to return to this function, then presume that
3473 we have an ABI compliant frame that we failed to find. */
3474 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3479 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3480 if (func
== 0 && saved_lr
== pc
)
3484 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3485 if (func
== saved_func
)
3491 fdata
.frameless
= 0;
3492 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3496 if (!fdata
.frameless
)
3498 /* Frameless really means stackless. */
3501 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3502 byte_order
, &backchain
))
3503 cache
->base
= (CORE_ADDR
) backchain
;
3506 trad_frame_set_value (cache
->saved_regs
,
3507 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3509 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3510 All fpr's from saved_fpr to fp31 are saved. */
3512 if (fdata
.saved_fpr
>= 0)
3515 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3517 /* If skip_prologue says floating-point registers were saved,
3518 but the current architecture has no floating-point registers,
3519 then that's strange. But we have no indices to even record
3520 the addresses under, so we just ignore it. */
3521 if (ppc_floating_point_unit_p (gdbarch
))
3522 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3524 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3529 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3530 All gpr's from saved_gpr to gpr31 are saved (except during the
3533 if (fdata
.saved_gpr
>= 0)
3536 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3537 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3539 if (fdata
.gpr_mask
& (1U << i
))
3540 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3541 gpr_addr
+= wordsize
;
3545 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3546 All vr's from saved_vr to vr31 are saved. */
3547 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3549 if (fdata
.saved_vr
>= 0)
3552 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3553 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3555 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3556 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3561 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3562 All vr's from saved_ev to ev31 are saved. ????? */
3563 if (tdep
->ppc_ev0_regnum
!= -1)
3565 if (fdata
.saved_ev
>= 0)
3568 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3569 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3571 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3573 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3574 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3575 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3580 /* If != 0, fdata.cr_offset is the offset from the frame that
3582 if (fdata
.cr_offset
!= 0)
3583 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3584 = cache
->base
+ fdata
.cr_offset
;
3586 /* If != 0, fdata.lr_offset is the offset from the frame that
3588 if (fdata
.lr_offset
!= 0)
3589 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3590 = cache
->base
+ fdata
.lr_offset
;
3591 else if (fdata
.lr_register
!= -1)
3592 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3593 /* The PC is found in the link register. */
3594 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3595 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3597 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3598 holds the VRSAVE. */
3599 if (fdata
.vrsave_offset
!= 0)
3600 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3601 = cache
->base
+ fdata
.vrsave_offset
;
3603 if (fdata
.alloca_reg
< 0)
3604 /* If no alloca register used, then fi->frame is the value of the
3605 %sp for this frame, and it is good enough. */
3607 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3610 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3617 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3618 struct frame_id
*this_id
)
3620 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3625 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3629 /* This marks the outermost frame. */
3630 if (info
->base
== 0)
3633 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3636 static struct value
*
3637 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3638 void **this_cache
, int regnum
)
3640 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3642 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3645 static const struct frame_unwind rs6000_frame_unwind
=
3648 default_frame_unwind_stop_reason
,
3649 rs6000_frame_this_id
,
3650 rs6000_frame_prev_register
,
3652 default_frame_sniffer
3655 /* Allocate and initialize a frame cache for an epilogue frame.
3656 SP is restored and prev-PC is stored in LR. */
3658 static struct rs6000_frame_cache
*
3659 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3661 struct rs6000_frame_cache
*cache
;
3662 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3663 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3666 return (struct rs6000_frame_cache
*) *this_cache
;
3668 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3669 (*this_cache
) = cache
;
3670 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3674 /* At this point the stack looks as if we just entered the
3675 function, and the return address is stored in LR. */
3678 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3679 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3682 cache
->initial_sp
= sp
;
3684 trad_frame_set_value (cache
->saved_regs
,
3685 gdbarch_pc_regnum (gdbarch
), lr
);
3687 catch (const gdb_exception_error
&ex
)
3689 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3696 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3697 Return the frame ID of an epilogue frame. */
3700 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3701 void **this_cache
, struct frame_id
*this_id
)
3704 struct rs6000_frame_cache
*info
=
3705 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3707 pc
= get_frame_func (this_frame
);
3708 if (info
->base
== 0)
3709 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3711 (*this_id
) = frame_id_build (info
->base
, pc
);
3714 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3715 Return the register value of REGNUM in previous frame. */
3717 static struct value
*
3718 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3719 void **this_cache
, int regnum
)
3721 struct rs6000_frame_cache
*info
=
3722 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3723 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3726 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3727 Check whether this an epilogue frame. */
3730 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3731 struct frame_info
*this_frame
,
3732 void **this_prologue_cache
)
3734 if (frame_relative_level (this_frame
) == 0)
3735 return rs6000_in_function_epilogue_frame_p (this_frame
,
3736 get_frame_arch (this_frame
),
3737 get_frame_pc (this_frame
));
3742 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3743 a function without debug information. */
3745 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3748 default_frame_unwind_stop_reason
,
3749 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3751 rs6000_epilogue_frame_sniffer
3756 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3758 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3760 return info
->initial_sp
;
3763 static const struct frame_base rs6000_frame_base
= {
3764 &rs6000_frame_unwind
,
3765 rs6000_frame_base_address
,
3766 rs6000_frame_base_address
,
3767 rs6000_frame_base_address
3770 static const struct frame_base
*
3771 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3773 return &rs6000_frame_base
;
3776 /* DWARF-2 frame support. Used to handle the detection of
3777 clobbered registers during function calls. */
3780 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3781 struct dwarf2_frame_state_reg
*reg
,
3782 struct frame_info
*this_frame
)
3784 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3786 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3787 non-volatile registers. We will use the same code for both. */
3789 /* Call-saved GP registers. */
3790 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3791 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3792 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3793 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3795 /* Call-clobbered GP registers. */
3796 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3797 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3798 || (regnum
== tdep
->ppc_gp0_regnum
))
3799 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3801 /* Deal with FP registers, if supported. */
3802 if (tdep
->ppc_fp0_regnum
>= 0)
3804 /* Call-saved FP registers. */
3805 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3806 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3807 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3809 /* Call-clobbered FP registers. */
3810 if ((regnum
>= tdep
->ppc_fp0_regnum
3811 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3812 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3815 /* Deal with ALTIVEC registers, if supported. */
3816 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3818 /* Call-saved Altivec registers. */
3819 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3820 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3821 || regnum
== tdep
->ppc_vrsave_regnum
)
3822 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3824 /* Call-clobbered Altivec registers. */
3825 if ((regnum
>= tdep
->ppc_vr0_regnum
3826 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3827 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3830 /* Handle PC register and Stack Pointer correctly. */
3831 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3832 reg
->how
= DWARF2_FRAME_REG_RA
;
3833 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3834 reg
->how
= DWARF2_FRAME_REG_CFA
;
3838 /* Return true if a .gnu_attributes section exists in BFD and it
3839 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3840 section exists in BFD and it indicates that SPE extensions are in
3841 use. Check the .gnu.attributes section first, as the binary might be
3842 compiled for SPE, but not actually using SPE instructions. */
3845 bfd_uses_spe_extensions (bfd
*abfd
)
3848 gdb_byte
*contents
= NULL
;
3857 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3858 could be using the SPE vector abi without actually using any spe
3859 bits whatsoever. But it's close enough for now. */
3860 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3861 Tag_GNU_Power_ABI_Vector
);
3862 if (vector_abi
== 3)
3866 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3870 size
= bfd_section_size (sect
);
3871 contents
= (gdb_byte
*) xmalloc (size
);
3872 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3878 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3884 char name[name_len rounded up to 4-byte alignment];
3885 char data[data_len];
3888 Technically, there's only supposed to be one such structure in a
3889 given apuinfo section, but the linker is not always vigilant about
3890 merging apuinfo sections from input files. Just go ahead and parse
3891 them all, exiting early when we discover the binary uses SPE
3894 It's not specified in what endianness the information in this
3895 section is stored. Assume that it's the endianness of the BFD. */
3899 unsigned int name_len
;
3900 unsigned int data_len
;
3903 /* If we can't read the first three fields, we're done. */
3907 name_len
= bfd_get_32 (abfd
, ptr
);
3908 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3909 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3910 type
= bfd_get_32 (abfd
, ptr
+ 8);
3913 /* The name must be "APUinfo\0". */
3915 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3919 /* The type must be 2. */
3923 /* The data is stored as a series of uint32. The upper half of
3924 each uint32 indicates the particular APU used and the lower
3925 half indicates the revision of that APU. We just care about
3928 /* Not 4-byte quantities. */
3934 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3935 unsigned int apu
= apuinfo
>> 16;
3939 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3941 if (apu
== 0x100 || apu
== 0x101)
3956 /* These are macros for parsing instruction fields (I.1.6.28) */
3958 #define PPC_FIELD(value, from, len) \
3959 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3960 #define PPC_SEXT(v, bs) \
3961 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3962 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3963 - ((CORE_ADDR) 1 << ((bs) - 1)))
3964 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3965 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3966 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3967 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3968 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3969 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3970 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3971 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3972 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3973 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3974 | (PPC_FIELD (insn, 16, 5) << 5))
3975 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3976 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3977 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3978 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3979 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3980 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3981 #define PPC_OE(insn) PPC_BIT (insn, 21)
3982 #define PPC_RC(insn) PPC_BIT (insn, 31)
3983 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3984 #define PPC_LK(insn) PPC_BIT (insn, 31)
3985 #define PPC_TX(insn) PPC_BIT (insn, 31)
3986 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3988 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3989 #define PPC_XER_NB(xer) (xer & 0x7f)
3991 /* Record Vector-Scalar Registers.
3992 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3993 Otherwise, it's just a VR register. Record them accordingly. */
3996 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3998 if (vsr
< 0 || vsr
>= 64)
4003 if (tdep
->ppc_vr0_regnum
>= 0)
4004 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
4008 if (tdep
->ppc_fp0_regnum
>= 0)
4009 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
4010 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
4011 record_full_arch_list_add_reg (regcache
,
4012 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4018 /* Parse and record instructions primary opcode-4 at ADDR.
4019 Return 0 if successful. */
4022 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4023 CORE_ADDR addr
, uint32_t insn
)
4025 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4026 int ext
= PPC_FIELD (insn
, 21, 11);
4027 int vra
= PPC_FIELD (insn
, 11, 5);
4031 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4032 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4033 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4034 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4035 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4037 case 42: /* Vector Select */
4038 case 43: /* Vector Permute */
4039 case 59: /* Vector Permute Right-indexed */
4040 case 44: /* Vector Shift Left Double by Octet Immediate */
4041 case 45: /* Vector Permute and Exclusive-OR */
4042 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4043 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4044 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4045 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4046 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4047 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4048 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4049 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4050 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4051 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4052 case 46: /* Vector Multiply-Add Single-Precision */
4053 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4054 record_full_arch_list_add_reg (regcache
,
4055 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4058 case 48: /* Multiply-Add High Doubleword */
4059 case 49: /* Multiply-Add High Doubleword Unsigned */
4060 case 51: /* Multiply-Add Low Doubleword */
4061 record_full_arch_list_add_reg (regcache
,
4062 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4066 switch ((ext
& 0x1ff))
4069 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4070 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4071 && vra
!= 4 /* Decimal Convert To Zoned */
4072 && vra
!= 5 /* Decimal Convert To National */
4073 && vra
!= 6 /* Decimal Convert From Zoned */
4074 && vra
!= 7 /* Decimal Convert From National */
4075 && vra
!= 31) /* Decimal Set Sign */
4078 /* 5.16 Decimal Integer Arithmetic Instructions */
4079 case 1: /* Decimal Add Modulo */
4080 case 65: /* Decimal Subtract Modulo */
4082 case 193: /* Decimal Shift */
4083 case 129: /* Decimal Unsigned Shift */
4084 case 449: /* Decimal Shift and Round */
4086 case 257: /* Decimal Truncate */
4087 case 321: /* Decimal Unsigned Truncate */
4089 /* Bit-21 should be set. */
4090 if (!PPC_BIT (insn
, 21))
4093 record_full_arch_list_add_reg (regcache
,
4094 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4095 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4099 /* Bit-21 is used for RC */
4100 switch (ext
& 0x3ff)
4102 case 6: /* Vector Compare Equal To Unsigned Byte */
4103 case 70: /* Vector Compare Equal To Unsigned Halfword */
4104 case 134: /* Vector Compare Equal To Unsigned Word */
4105 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4106 case 774: /* Vector Compare Greater Than Signed Byte */
4107 case 838: /* Vector Compare Greater Than Signed Halfword */
4108 case 902: /* Vector Compare Greater Than Signed Word */
4109 case 967: /* Vector Compare Greater Than Signed Doubleword */
4110 case 518: /* Vector Compare Greater Than Unsigned Byte */
4111 case 646: /* Vector Compare Greater Than Unsigned Word */
4112 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4113 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4114 case 966: /* Vector Compare Bounds Single-Precision */
4115 case 198: /* Vector Compare Equal To Single-Precision */
4116 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4117 case 710: /* Vector Compare Greater Than Single-Precision */
4118 case 7: /* Vector Compare Not Equal Byte */
4119 case 71: /* Vector Compare Not Equal Halfword */
4120 case 135: /* Vector Compare Not Equal Word */
4121 case 263: /* Vector Compare Not Equal or Zero Byte */
4122 case 327: /* Vector Compare Not Equal or Zero Halfword */
4123 case 391: /* Vector Compare Not Equal or Zero Word */
4125 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4126 record_full_arch_list_add_reg (regcache
,
4127 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4135 case 0: /* Vector Count Leading Zero Least-Significant Bits
4137 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4139 record_full_arch_list_add_reg (regcache
,
4140 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4143 case 6: /* Vector Negate Word */
4144 case 7: /* Vector Negate Doubleword */
4145 case 8: /* Vector Parity Byte Word */
4146 case 9: /* Vector Parity Byte Doubleword */
4147 case 10: /* Vector Parity Byte Quadword */
4148 case 16: /* Vector Extend Sign Byte To Word */
4149 case 17: /* Vector Extend Sign Halfword To Word */
4150 case 24: /* Vector Extend Sign Byte To Doubleword */
4151 case 25: /* Vector Extend Sign Halfword To Doubleword */
4152 case 26: /* Vector Extend Sign Word To Doubleword */
4153 case 28: /* Vector Count Trailing Zeros Byte */
4154 case 29: /* Vector Count Trailing Zeros Halfword */
4155 case 30: /* Vector Count Trailing Zeros Word */
4156 case 31: /* Vector Count Trailing Zeros Doubleword */
4157 record_full_arch_list_add_reg (regcache
,
4158 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4165 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4166 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4167 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4168 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4169 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4170 case 462: /* Vector Pack Signed Word Signed Saturate */
4171 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4172 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4173 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4174 case 512: /* Vector Add Unsigned Byte Saturate */
4175 case 576: /* Vector Add Unsigned Halfword Saturate */
4176 case 640: /* Vector Add Unsigned Word Saturate */
4177 case 768: /* Vector Add Signed Byte Saturate */
4178 case 832: /* Vector Add Signed Halfword Saturate */
4179 case 896: /* Vector Add Signed Word Saturate */
4180 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4181 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4182 case 1664: /* Vector Subtract Unsigned Word Saturate */
4183 case 1792: /* Vector Subtract Signed Byte Saturate */
4184 case 1856: /* Vector Subtract Signed Halfword Saturate */
4185 case 1920: /* Vector Subtract Signed Word Saturate */
4187 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4188 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4189 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4190 case 1672: /* Vector Sum across Half Signed Word Saturate */
4191 case 1928: /* Vector Sum across Signed Word Saturate */
4192 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4193 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4194 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4196 case 12: /* Vector Merge High Byte */
4197 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4198 case 76: /* Vector Merge High Halfword */
4199 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4200 case 140: /* Vector Merge High Word */
4201 case 268: /* Vector Merge Low Byte */
4202 case 332: /* Vector Merge Low Halfword */
4203 case 396: /* Vector Merge Low Word */
4204 case 526: /* Vector Unpack High Signed Byte */
4205 case 590: /* Vector Unpack High Signed Halfword */
4206 case 654: /* Vector Unpack Low Signed Byte */
4207 case 718: /* Vector Unpack Low Signed Halfword */
4208 case 782: /* Vector Pack Pixel */
4209 case 846: /* Vector Unpack High Pixel */
4210 case 974: /* Vector Unpack Low Pixel */
4211 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4212 case 1614: /* Vector Unpack High Signed Word */
4213 case 1676: /* Vector Merge Odd Word */
4214 case 1742: /* Vector Unpack Low Signed Word */
4215 case 1932: /* Vector Merge Even Word */
4216 case 524: /* Vector Splat Byte */
4217 case 588: /* Vector Splat Halfword */
4218 case 652: /* Vector Splat Word */
4219 case 780: /* Vector Splat Immediate Signed Byte */
4220 case 844: /* Vector Splat Immediate Signed Halfword */
4221 case 908: /* Vector Splat Immediate Signed Word */
4222 case 452: /* Vector Shift Left */
4223 case 708: /* Vector Shift Right */
4224 case 1036: /* Vector Shift Left by Octet */
4225 case 1100: /* Vector Shift Right by Octet */
4226 case 0: /* Vector Add Unsigned Byte Modulo */
4227 case 64: /* Vector Add Unsigned Halfword Modulo */
4228 case 128: /* Vector Add Unsigned Word Modulo */
4229 case 192: /* Vector Add Unsigned Doubleword Modulo */
4230 case 256: /* Vector Add Unsigned Quadword Modulo */
4231 case 320: /* Vector Add & write Carry Unsigned Quadword */
4232 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4233 case 8: /* Vector Multiply Odd Unsigned Byte */
4234 case 72: /* Vector Multiply Odd Unsigned Halfword */
4235 case 136: /* Vector Multiply Odd Unsigned Word */
4236 case 264: /* Vector Multiply Odd Signed Byte */
4237 case 328: /* Vector Multiply Odd Signed Halfword */
4238 case 392: /* Vector Multiply Odd Signed Word */
4239 case 520: /* Vector Multiply Even Unsigned Byte */
4240 case 584: /* Vector Multiply Even Unsigned Halfword */
4241 case 648: /* Vector Multiply Even Unsigned Word */
4242 case 776: /* Vector Multiply Even Signed Byte */
4243 case 840: /* Vector Multiply Even Signed Halfword */
4244 case 904: /* Vector Multiply Even Signed Word */
4245 case 137: /* Vector Multiply Unsigned Word Modulo */
4246 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4247 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4248 case 1152: /* Vector Subtract Unsigned Word Modulo */
4249 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4250 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4251 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4252 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4253 case 1282: /* Vector Average Signed Byte */
4254 case 1346: /* Vector Average Signed Halfword */
4255 case 1410: /* Vector Average Signed Word */
4256 case 1026: /* Vector Average Unsigned Byte */
4257 case 1090: /* Vector Average Unsigned Halfword */
4258 case 1154: /* Vector Average Unsigned Word */
4259 case 258: /* Vector Maximum Signed Byte */
4260 case 322: /* Vector Maximum Signed Halfword */
4261 case 386: /* Vector Maximum Signed Word */
4262 case 450: /* Vector Maximum Signed Doubleword */
4263 case 2: /* Vector Maximum Unsigned Byte */
4264 case 66: /* Vector Maximum Unsigned Halfword */
4265 case 130: /* Vector Maximum Unsigned Word */
4266 case 194: /* Vector Maximum Unsigned Doubleword */
4267 case 770: /* Vector Minimum Signed Byte */
4268 case 834: /* Vector Minimum Signed Halfword */
4269 case 898: /* Vector Minimum Signed Word */
4270 case 962: /* Vector Minimum Signed Doubleword */
4271 case 514: /* Vector Minimum Unsigned Byte */
4272 case 578: /* Vector Minimum Unsigned Halfword */
4273 case 642: /* Vector Minimum Unsigned Word */
4274 case 706: /* Vector Minimum Unsigned Doubleword */
4275 case 1028: /* Vector Logical AND */
4276 case 1668: /* Vector Logical Equivalent */
4277 case 1092: /* Vector Logical AND with Complement */
4278 case 1412: /* Vector Logical NAND */
4279 case 1348: /* Vector Logical OR with Complement */
4280 case 1156: /* Vector Logical OR */
4281 case 1284: /* Vector Logical NOR */
4282 case 1220: /* Vector Logical XOR */
4283 case 4: /* Vector Rotate Left Byte */
4284 case 132: /* Vector Rotate Left Word VX-form */
4285 case 68: /* Vector Rotate Left Halfword */
4286 case 196: /* Vector Rotate Left Doubleword */
4287 case 260: /* Vector Shift Left Byte */
4288 case 388: /* Vector Shift Left Word */
4289 case 324: /* Vector Shift Left Halfword */
4290 case 1476: /* Vector Shift Left Doubleword */
4291 case 516: /* Vector Shift Right Byte */
4292 case 644: /* Vector Shift Right Word */
4293 case 580: /* Vector Shift Right Halfword */
4294 case 1732: /* Vector Shift Right Doubleword */
4295 case 772: /* Vector Shift Right Algebraic Byte */
4296 case 900: /* Vector Shift Right Algebraic Word */
4297 case 836: /* Vector Shift Right Algebraic Halfword */
4298 case 964: /* Vector Shift Right Algebraic Doubleword */
4299 case 10: /* Vector Add Single-Precision */
4300 case 74: /* Vector Subtract Single-Precision */
4301 case 1034: /* Vector Maximum Single-Precision */
4302 case 1098: /* Vector Minimum Single-Precision */
4303 case 842: /* Vector Convert From Signed Fixed-Point Word */
4304 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4305 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4306 case 522: /* Vector Round to Single-Precision Integer Nearest */
4307 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4308 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4309 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4310 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4311 case 266: /* Vector Reciprocal Estimate Single-Precision */
4312 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4313 case 1288: /* Vector AES Cipher */
4314 case 1289: /* Vector AES Cipher Last */
4315 case 1352: /* Vector AES Inverse Cipher */
4316 case 1353: /* Vector AES Inverse Cipher Last */
4317 case 1480: /* Vector AES SubBytes */
4318 case 1730: /* Vector SHA-512 Sigma Doubleword */
4319 case 1666: /* Vector SHA-256 Sigma Word */
4320 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4321 case 1160: /* Vector Polynomial Multiply-Sum Word */
4322 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4323 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4324 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4325 case 1794: /* Vector Count Leading Zeros Byte */
4326 case 1858: /* Vector Count Leading Zeros Halfword */
4327 case 1922: /* Vector Count Leading Zeros Word */
4328 case 1986: /* Vector Count Leading Zeros Doubleword */
4329 case 1795: /* Vector Population Count Byte */
4330 case 1859: /* Vector Population Count Halfword */
4331 case 1923: /* Vector Population Count Word */
4332 case 1987: /* Vector Population Count Doubleword */
4333 case 1356: /* Vector Bit Permute Quadword */
4334 case 1484: /* Vector Bit Permute Doubleword */
4335 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4336 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4338 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4339 case 65: /* Vector Multiply-by-10 Extended & write Carry
4340 Unsigned Quadword */
4341 case 1027: /* Vector Absolute Difference Unsigned Byte */
4342 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4343 case 1155: /* Vector Absolute Difference Unsigned Word */
4344 case 1796: /* Vector Shift Right Variable */
4345 case 1860: /* Vector Shift Left Variable */
4346 case 133: /* Vector Rotate Left Word then Mask Insert */
4347 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4348 case 389: /* Vector Rotate Left Word then AND with Mask */
4349 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4350 case 525: /* Vector Extract Unsigned Byte */
4351 case 589: /* Vector Extract Unsigned Halfword */
4352 case 653: /* Vector Extract Unsigned Word */
4353 case 717: /* Vector Extract Doubleword */
4354 case 781: /* Vector Insert Byte */
4355 case 845: /* Vector Insert Halfword */
4356 case 909: /* Vector Insert Word */
4357 case 973: /* Vector Insert Doubleword */
4358 record_full_arch_list_add_reg (regcache
,
4359 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4362 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4363 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4364 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4365 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4366 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4367 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4368 record_full_arch_list_add_reg (regcache
,
4369 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4372 case 1604: /* Move To Vector Status and Control Register */
4373 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4375 case 1540: /* Move From Vector Status and Control Register */
4376 record_full_arch_list_add_reg (regcache
,
4377 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4379 case 833: /* Decimal Copy Sign */
4380 record_full_arch_list_add_reg (regcache
,
4381 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4382 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4386 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4387 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4391 /* Parse and record instructions of primary opcode-19 at ADDR.
4392 Return 0 if successful. */
4395 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4396 CORE_ADDR addr
, uint32_t insn
)
4398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4399 int ext
= PPC_EXTOP (insn
);
4401 switch (ext
& 0x01f)
4403 case 2: /* Add PC Immediate Shifted */
4404 record_full_arch_list_add_reg (regcache
,
4405 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4411 case 0: /* Move Condition Register Field */
4412 case 33: /* Condition Register NOR */
4413 case 129: /* Condition Register AND with Complement */
4414 case 193: /* Condition Register XOR */
4415 case 225: /* Condition Register NAND */
4416 case 257: /* Condition Register AND */
4417 case 289: /* Condition Register Equivalent */
4418 case 417: /* Condition Register OR with Complement */
4419 case 449: /* Condition Register OR */
4420 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4423 case 16: /* Branch Conditional */
4424 case 560: /* Branch Conditional to Branch Target Address Register */
4425 if ((PPC_BO (insn
) & 0x4) == 0)
4426 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4428 case 528: /* Branch Conditional to Count Register */
4430 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4433 case 150: /* Instruction Synchronize */
4438 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4439 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4443 /* Parse and record instructions of primary opcode-31 at ADDR.
4444 Return 0 if successful. */
4447 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4448 CORE_ADDR addr
, uint32_t insn
)
4450 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4451 int ext
= PPC_EXTOP (insn
);
4453 CORE_ADDR at_dcsz
, ea
= 0;
4454 ULONGEST rb
, ra
, xer
;
4457 /* These instructions have OE bit. */
4458 switch (ext
& 0x1ff)
4460 /* These write RT and XER. Update CR if RC is set. */
4461 case 8: /* Subtract from carrying */
4462 case 10: /* Add carrying */
4463 case 136: /* Subtract from extended */
4464 case 138: /* Add extended */
4465 case 200: /* Subtract from zero extended */
4466 case 202: /* Add to zero extended */
4467 case 232: /* Subtract from minus one extended */
4468 case 234: /* Add to minus one extended */
4469 /* CA is always altered, but SO/OV are only altered when OE=1.
4470 In any case, XER is always altered. */
4471 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4473 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4474 record_full_arch_list_add_reg (regcache
,
4475 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4478 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4479 case 40: /* Subtract from */
4480 case 104: /* Negate */
4481 case 233: /* Multiply low doubleword */
4482 case 235: /* Multiply low word */
4484 case 393: /* Divide Doubleword Extended Unsigned */
4485 case 395: /* Divide Word Extended Unsigned */
4486 case 425: /* Divide Doubleword Extended */
4487 case 427: /* Divide Word Extended */
4488 case 457: /* Divide Doubleword Unsigned */
4489 case 459: /* Divide Word Unsigned */
4490 case 489: /* Divide Doubleword */
4491 case 491: /* Divide Word */
4493 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4495 case 9: /* Multiply High Doubleword Unsigned */
4496 case 11: /* Multiply High Word Unsigned */
4497 case 73: /* Multiply High Doubleword */
4498 case 75: /* Multiply High Word */
4500 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4501 record_full_arch_list_add_reg (regcache
,
4502 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4506 if ((ext
& 0x1f) == 15)
4508 /* Integer Select. bit[16:20] is used for BC. */
4509 record_full_arch_list_add_reg (regcache
,
4510 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4514 if ((ext
& 0xff) == 170)
4516 /* Add Extended using alternate carry bits */
4517 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4518 record_full_arch_list_add_reg (regcache
,
4519 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4525 case 78: /* Determine Leftmost Zero Byte */
4527 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4528 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4529 record_full_arch_list_add_reg (regcache
,
4530 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4533 /* These only write RT. */
4534 case 19: /* Move from condition register */
4535 /* Move From One Condition Register Field */
4536 case 74: /* Add and Generate Sixes */
4537 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4538 case 302: /* Move From Branch History Rolling Buffer */
4539 case 339: /* Move From Special Purpose Register */
4540 case 371: /* Move From Time Base [Phased-Out] */
4541 case 309: /* Load Doubleword Monitored Indexed */
4542 case 128: /* Set Boolean */
4543 case 755: /* Deliver A Random Number */
4544 record_full_arch_list_add_reg (regcache
,
4545 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4548 /* These only write to RA. */
4549 case 51: /* Move From VSR Doubleword */
4550 case 115: /* Move From VSR Word and Zero */
4551 case 122: /* Population count bytes */
4552 case 378: /* Population count words */
4553 case 506: /* Population count doublewords */
4554 case 154: /* Parity Word */
4555 case 186: /* Parity Doubleword */
4556 case 252: /* Bit Permute Doubleword */
4557 case 282: /* Convert Declets To Binary Coded Decimal */
4558 case 314: /* Convert Binary Coded Decimal To Declets */
4559 case 508: /* Compare bytes */
4560 case 307: /* Move From VSR Lower Doubleword */
4561 record_full_arch_list_add_reg (regcache
,
4562 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4565 /* These write CR and optional RA. */
4566 case 792: /* Shift Right Algebraic Word */
4567 case 794: /* Shift Right Algebraic Doubleword */
4568 case 824: /* Shift Right Algebraic Word Immediate */
4569 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4570 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4571 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4572 record_full_arch_list_add_reg (regcache
,
4573 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4575 case 0: /* Compare */
4576 case 32: /* Compare logical */
4577 case 144: /* Move To Condition Register Fields */
4578 /* Move To One Condition Register Field */
4579 case 192: /* Compare Ranged Byte */
4580 case 224: /* Compare Equal Byte */
4581 case 576: /* Move XER to CR Extended */
4582 case 902: /* Paste (should always fail due to single-stepping and
4583 the memory location might not be accessible, so
4585 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4588 /* These write to RT. Update RA if 'update indexed.' */
4589 case 53: /* Load Doubleword with Update Indexed */
4590 case 119: /* Load Byte and Zero with Update Indexed */
4591 case 311: /* Load Halfword and Zero with Update Indexed */
4592 case 55: /* Load Word and Zero with Update Indexed */
4593 case 375: /* Load Halfword Algebraic with Update Indexed */
4594 case 373: /* Load Word Algebraic with Update Indexed */
4595 record_full_arch_list_add_reg (regcache
,
4596 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4598 case 21: /* Load Doubleword Indexed */
4599 case 52: /* Load Byte And Reserve Indexed */
4600 case 116: /* Load Halfword And Reserve Indexed */
4601 case 20: /* Load Word And Reserve Indexed */
4602 case 84: /* Load Doubleword And Reserve Indexed */
4603 case 87: /* Load Byte and Zero Indexed */
4604 case 279: /* Load Halfword and Zero Indexed */
4605 case 23: /* Load Word and Zero Indexed */
4606 case 343: /* Load Halfword Algebraic Indexed */
4607 case 341: /* Load Word Algebraic Indexed */
4608 case 790: /* Load Halfword Byte-Reverse Indexed */
4609 case 534: /* Load Word Byte-Reverse Indexed */
4610 case 532: /* Load Doubleword Byte-Reverse Indexed */
4611 case 582: /* Load Word Atomic */
4612 case 614: /* Load Doubleword Atomic */
4613 case 265: /* Modulo Unsigned Doubleword */
4614 case 777: /* Modulo Signed Doubleword */
4615 case 267: /* Modulo Unsigned Word */
4616 case 779: /* Modulo Signed Word */
4617 record_full_arch_list_add_reg (regcache
,
4618 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4621 case 597: /* Load String Word Immediate */
4622 case 533: /* Load String Word Indexed */
4631 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4632 nr
= PPC_XER_NB (xer
);
4637 /* If n=0, the contents of register RT are undefined. */
4641 for (i
= 0; i
< nr
; i
++)
4642 record_full_arch_list_add_reg (regcache
,
4643 tdep
->ppc_gp0_regnum
4644 + ((PPC_RT (insn
) + i
) & 0x1f));
4647 case 276: /* Load Quadword And Reserve Indexed */
4648 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4649 record_full_arch_list_add_reg (regcache
, tmp
);
4650 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4653 /* These write VRT. */
4654 case 6: /* Load Vector for Shift Left Indexed */
4655 case 38: /* Load Vector for Shift Right Indexed */
4656 case 7: /* Load Vector Element Byte Indexed */
4657 case 39: /* Load Vector Element Halfword Indexed */
4658 case 71: /* Load Vector Element Word Indexed */
4659 case 103: /* Load Vector Indexed */
4660 case 359: /* Load Vector Indexed LRU */
4661 record_full_arch_list_add_reg (regcache
,
4662 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4665 /* These write FRT. Update RA if 'update indexed.' */
4666 case 567: /* Load Floating-Point Single with Update Indexed */
4667 case 631: /* Load Floating-Point Double with Update Indexed */
4668 record_full_arch_list_add_reg (regcache
,
4669 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4671 case 535: /* Load Floating-Point Single Indexed */
4672 case 599: /* Load Floating-Point Double Indexed */
4673 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4674 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4675 record_full_arch_list_add_reg (regcache
,
4676 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4679 case 791: /* Load Floating-Point Double Pair Indexed */
4680 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4681 record_full_arch_list_add_reg (regcache
, tmp
);
4682 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4685 case 179: /* Move To VSR Doubleword */
4686 case 211: /* Move To VSR Word Algebraic */
4687 case 243: /* Move To VSR Word and Zero */
4688 case 588: /* Load VSX Scalar Doubleword Indexed */
4689 case 524: /* Load VSX Scalar Single-Precision Indexed */
4690 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4691 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4692 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4693 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4694 case 780: /* Load VSX Vector Word*4 Indexed */
4695 case 268: /* Load VSX Vector Indexed */
4696 case 364: /* Load VSX Vector Word & Splat Indexed */
4697 case 812: /* Load VSX Vector Halfword*8 Indexed */
4698 case 876: /* Load VSX Vector Byte*16 Indexed */
4699 case 269: /* Load VSX Vector with Length */
4700 case 301: /* Load VSX Vector Left-justified with Length */
4701 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4702 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4703 case 403: /* Move To VSR Word & Splat */
4704 case 435: /* Move To VSR Double Doubleword */
4705 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4708 /* These write RA. Update CR if RC is set. */
4709 case 24: /* Shift Left Word */
4710 case 26: /* Count Leading Zeros Word */
4711 case 27: /* Shift Left Doubleword */
4713 case 58: /* Count Leading Zeros Doubleword */
4714 case 60: /* AND with Complement */
4716 case 284: /* Equivalent */
4718 case 476: /* NAND */
4719 case 412: /* OR with Complement */
4721 case 536: /* Shift Right Word */
4722 case 539: /* Shift Right Doubleword */
4723 case 922: /* Extend Sign Halfword */
4724 case 954: /* Extend Sign Byte */
4725 case 986: /* Extend Sign Word */
4726 case 538: /* Count Trailing Zeros Word */
4727 case 570: /* Count Trailing Zeros Doubleword */
4728 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4729 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4731 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
4732 && (PPC_RS (insn
) == PPC_RA (insn
))
4733 && (PPC_RA (insn
) == PPC_RB (insn
))
4736 /* or Rx,Rx,Rx alters PRI in PPR. */
4737 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4742 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4743 record_full_arch_list_add_reg (regcache
,
4744 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4748 case 181: /* Store Doubleword with Update Indexed */
4749 case 183: /* Store Word with Update Indexed */
4750 case 247: /* Store Byte with Update Indexed */
4751 case 439: /* Store Half Word with Update Indexed */
4752 case 695: /* Store Floating-Point Single with Update Indexed */
4753 case 759: /* Store Floating-Point Double with Update Indexed */
4754 record_full_arch_list_add_reg (regcache
,
4755 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4757 case 135: /* Store Vector Element Byte Indexed */
4758 case 167: /* Store Vector Element Halfword Indexed */
4759 case 199: /* Store Vector Element Word Indexed */
4760 case 231: /* Store Vector Indexed */
4761 case 487: /* Store Vector Indexed LRU */
4762 case 716: /* Store VSX Scalar Doubleword Indexed */
4763 case 140: /* Store VSX Scalar as Integer Word Indexed */
4764 case 652: /* Store VSX Scalar Single-Precision Indexed */
4765 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4766 case 908: /* Store VSX Vector Word*4 Indexed */
4767 case 149: /* Store Doubleword Indexed */
4768 case 151: /* Store Word Indexed */
4769 case 215: /* Store Byte Indexed */
4770 case 407: /* Store Half Word Indexed */
4771 case 694: /* Store Byte Conditional Indexed */
4772 case 726: /* Store Halfword Conditional Indexed */
4773 case 150: /* Store Word Conditional Indexed */
4774 case 214: /* Store Doubleword Conditional Indexed */
4775 case 182: /* Store Quadword Conditional Indexed */
4776 case 662: /* Store Word Byte-Reverse Indexed */
4777 case 918: /* Store Halfword Byte-Reverse Indexed */
4778 case 660: /* Store Doubleword Byte-Reverse Indexed */
4779 case 663: /* Store Floating-Point Single Indexed */
4780 case 727: /* Store Floating-Point Double Indexed */
4781 case 919: /* Store Floating-Point Double Pair Indexed */
4782 case 983: /* Store Floating-Point as Integer Word Indexed */
4783 case 396: /* Store VSX Vector Indexed */
4784 case 940: /* Store VSX Vector Halfword*8 Indexed */
4785 case 1004: /* Store VSX Vector Byte*16 Indexed */
4786 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4787 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4788 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4789 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4792 if (PPC_RA (insn
) != 0)
4793 regcache_raw_read_unsigned (regcache
,
4794 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4795 regcache_raw_read_unsigned (regcache
,
4796 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4801 case 183: /* Store Word with Update Indexed */
4802 case 199: /* Store Vector Element Word Indexed */
4803 case 140: /* Store VSX Scalar as Integer Word Indexed */
4804 case 652: /* Store VSX Scalar Single-Precision Indexed */
4805 case 151: /* Store Word Indexed */
4806 case 150: /* Store Word Conditional Indexed */
4807 case 662: /* Store Word Byte-Reverse Indexed */
4808 case 663: /* Store Floating-Point Single Indexed */
4809 case 695: /* Store Floating-Point Single with Update Indexed */
4810 case 983: /* Store Floating-Point as Integer Word Indexed */
4813 case 247: /* Store Byte with Update Indexed */
4814 case 135: /* Store Vector Element Byte Indexed */
4815 case 215: /* Store Byte Indexed */
4816 case 694: /* Store Byte Conditional Indexed */
4817 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4820 case 439: /* Store Halfword with Update Indexed */
4821 case 167: /* Store Vector Element Halfword Indexed */
4822 case 407: /* Store Halfword Indexed */
4823 case 726: /* Store Halfword Conditional Indexed */
4824 case 918: /* Store Halfword Byte-Reverse Indexed */
4825 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4828 case 181: /* Store Doubleword with Update Indexed */
4829 case 716: /* Store VSX Scalar Doubleword Indexed */
4830 case 149: /* Store Doubleword Indexed */
4831 case 214: /* Store Doubleword Conditional Indexed */
4832 case 660: /* Store Doubleword Byte-Reverse Indexed */
4833 case 727: /* Store Floating-Point Double Indexed */
4834 case 759: /* Store Floating-Point Double with Update Indexed */
4837 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4838 case 908: /* Store VSX Vector Word*4 Indexed */
4839 case 182: /* Store Quadword Conditional Indexed */
4840 case 231: /* Store Vector Indexed */
4841 case 487: /* Store Vector Indexed LRU */
4842 case 919: /* Store Floating-Point Double Pair Indexed */
4843 case 396: /* Store VSX Vector Indexed */
4844 case 940: /* Store VSX Vector Halfword*8 Indexed */
4845 case 1004: /* Store VSX Vector Byte*16 Indexed */
4852 /* Align address for Store Vector instructions. */
4855 case 167: /* Store Vector Element Halfword Indexed */
4856 addr
= addr
& ~0x1ULL
;
4859 case 199: /* Store Vector Element Word Indexed */
4860 addr
= addr
& ~0x3ULL
;
4863 case 231: /* Store Vector Indexed */
4864 case 487: /* Store Vector Indexed LRU */
4865 addr
= addr
& ~0xfULL
;
4869 record_full_arch_list_add_mem (addr
, size
);
4872 case 397: /* Store VSX Vector with Length */
4873 case 429: /* Store VSX Vector Left-justified with Length */
4875 if (PPC_RA (insn
) != 0)
4876 regcache_raw_read_unsigned (regcache
,
4877 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4879 regcache_raw_read_unsigned (regcache
,
4880 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4881 /* Store up to 16 bytes. */
4882 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4884 record_full_arch_list_add_mem (ea
, nb
);
4887 case 710: /* Store Word Atomic */
4888 case 742: /* Store Doubleword Atomic */
4890 if (PPC_RA (insn
) != 0)
4891 regcache_raw_read_unsigned (regcache
,
4892 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4896 case 710: /* Store Word Atomic */
4899 case 742: /* Store Doubleword Atomic */
4905 record_full_arch_list_add_mem (ea
, size
);
4908 case 725: /* Store String Word Immediate */
4910 if (PPC_RA (insn
) != 0)
4911 regcache_raw_read_unsigned (regcache
,
4912 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4919 record_full_arch_list_add_mem (ea
, nb
);
4923 case 661: /* Store String Word Indexed */
4925 if (PPC_RA (insn
) != 0)
4926 regcache_raw_read_unsigned (regcache
,
4927 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4930 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4931 nb
= PPC_XER_NB (xer
);
4935 regcache_raw_read_unsigned (regcache
,
4936 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4939 record_full_arch_list_add_mem (ea
, nb
);
4944 case 467: /* Move To Special Purpose Register */
4945 switch (PPC_SPR (insn
))
4948 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4951 if (tdep
->ppc_dscr_regnum
>= 0)
4952 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
4955 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4958 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4960 case 256: /* VRSAVE */
4961 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4964 if (tdep
->ppc_tar_regnum
>= 0)
4965 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
4969 if (tdep
->ppc_ppr_regnum
>= 0)
4970 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4976 case 147: /* Move To Split Little Endian */
4977 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4980 case 512: /* Move to Condition Register from XER */
4981 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4982 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4985 case 4: /* Trap Word */
4986 case 68: /* Trap Doubleword */
4987 case 430: /* Clear BHRB */
4988 case 598: /* Synchronize */
4989 case 62: /* Wait for Interrupt */
4991 case 22: /* Instruction Cache Block Touch */
4992 case 854: /* Enforce In-order Execution of I/O */
4993 case 246: /* Data Cache Block Touch for Store */
4994 case 54: /* Data Cache Block Store */
4995 case 86: /* Data Cache Block Flush */
4996 case 278: /* Data Cache Block Touch */
4997 case 758: /* Data Cache Block Allocate */
4998 case 982: /* Instruction Cache Block Invalidate */
4999 case 774: /* Copy */
5000 case 838: /* CP_Abort */
5003 case 654: /* Transaction Begin */
5004 case 686: /* Transaction End */
5005 case 750: /* Transaction Suspend or Resume */
5006 case 782: /* Transaction Abort Word Conditional */
5007 case 814: /* Transaction Abort Doubleword Conditional */
5008 case 846: /* Transaction Abort Word Conditional Immediate */
5009 case 878: /* Transaction Abort Doubleword Conditional Immediate */
5010 case 910: /* Transaction Abort */
5011 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5013 case 718: /* Transaction Check */
5014 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5017 case 1014: /* Data Cache Block set to Zero */
5018 if (target_auxv_search (current_top_target (), AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5020 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5023 if (PPC_RA (insn
) != 0)
5024 regcache_raw_read_unsigned (regcache
,
5025 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5026 regcache_raw_read_unsigned (regcache
,
5027 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5028 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5029 record_full_arch_list_add_mem (ea
, at_dcsz
);
5034 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5035 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5039 /* Parse and record instructions of primary opcode-59 at ADDR.
5040 Return 0 if successful. */
5043 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5044 CORE_ADDR addr
, uint32_t insn
)
5046 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5047 int ext
= PPC_EXTOP (insn
);
5051 case 18: /* Floating Divide */
5052 case 20: /* Floating Subtract */
5053 case 21: /* Floating Add */
5054 case 22: /* Floating Square Root */
5055 case 24: /* Floating Reciprocal Estimate */
5056 case 25: /* Floating Multiply */
5057 case 26: /* Floating Reciprocal Square Root Estimate */
5058 case 28: /* Floating Multiply-Subtract */
5059 case 29: /* Floating Multiply-Add */
5060 case 30: /* Floating Negative Multiply-Subtract */
5061 case 31: /* Floating Negative Multiply-Add */
5062 record_full_arch_list_add_reg (regcache
,
5063 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5065 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5066 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5073 case 2: /* DFP Add */
5074 case 3: /* DFP Quantize */
5075 case 34: /* DFP Multiply */
5076 case 35: /* DFP Reround */
5077 case 67: /* DFP Quantize Immediate */
5078 case 99: /* DFP Round To FP Integer With Inexact */
5079 case 227: /* DFP Round To FP Integer Without Inexact */
5080 case 258: /* DFP Convert To DFP Long! */
5081 case 290: /* DFP Convert To Fixed */
5082 case 514: /* DFP Subtract */
5083 case 546: /* DFP Divide */
5084 case 770: /* DFP Round To DFP Short! */
5085 case 802: /* DFP Convert From Fixed */
5086 case 834: /* DFP Encode BCD To DPD */
5088 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5089 record_full_arch_list_add_reg (regcache
,
5090 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5091 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5094 case 130: /* DFP Compare Ordered */
5095 case 162: /* DFP Test Exponent */
5096 case 194: /* DFP Test Data Class */
5097 case 226: /* DFP Test Data Group */
5098 case 642: /* DFP Compare Unordered */
5099 case 674: /* DFP Test Significance */
5100 case 675: /* DFP Test Significance Immediate */
5101 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5102 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5105 case 66: /* DFP Shift Significand Left Immediate */
5106 case 98: /* DFP Shift Significand Right Immediate */
5107 case 322: /* DFP Decode DPD To BCD */
5108 case 354: /* DFP Extract Biased Exponent */
5109 case 866: /* DFP Insert Biased Exponent */
5110 record_full_arch_list_add_reg (regcache
,
5111 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5113 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5116 case 846: /* Floating Convert From Integer Doubleword Single */
5117 case 974: /* Floating Convert From Integer Doubleword Unsigned
5119 record_full_arch_list_add_reg (regcache
,
5120 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5122 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5123 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5128 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5129 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5133 /* Parse and record instructions of primary opcode-60 at ADDR.
5134 Return 0 if successful. */
5137 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5138 CORE_ADDR addr
, uint32_t insn
)
5140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5141 int ext
= PPC_EXTOP (insn
);
5145 case 0: /* VSX Scalar Add Single-Precision */
5146 case 32: /* VSX Scalar Add Double-Precision */
5147 case 24: /* VSX Scalar Divide Single-Precision */
5148 case 56: /* VSX Scalar Divide Double-Precision */
5149 case 176: /* VSX Scalar Copy Sign Double-Precision */
5150 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5151 case 41: /* ditto */
5152 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5154 case 160: /* VSX Scalar Maximum Double-Precision */
5155 case 168: /* VSX Scalar Minimum Double-Precision */
5156 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5157 case 57: /* ditto */
5158 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5159 case 25: /* ditto */
5160 case 48: /* VSX Scalar Multiply Double-Precision */
5161 case 16: /* VSX Scalar Multiply Single-Precision */
5162 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5163 case 169: /* ditto */
5164 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5165 case 137: /* ditto */
5166 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5167 case 185: /* ditto */
5168 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5169 case 153: /* ditto */
5170 case 40: /* VSX Scalar Subtract Double-Precision */
5171 case 8: /* VSX Scalar Subtract Single-Precision */
5172 case 96: /* VSX Vector Add Double-Precision */
5173 case 64: /* VSX Vector Add Single-Precision */
5174 case 120: /* VSX Vector Divide Double-Precision */
5175 case 88: /* VSX Vector Divide Single-Precision */
5176 case 97: /* VSX Vector Multiply-Add Double-Precision */
5177 case 105: /* ditto */
5178 case 65: /* VSX Vector Multiply-Add Single-Precision */
5179 case 73: /* ditto */
5180 case 224: /* VSX Vector Maximum Double-Precision */
5181 case 192: /* VSX Vector Maximum Single-Precision */
5182 case 232: /* VSX Vector Minimum Double-Precision */
5183 case 200: /* VSX Vector Minimum Single-Precision */
5184 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5185 case 121: /* ditto */
5186 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5187 case 89: /* ditto */
5188 case 112: /* VSX Vector Multiply Double-Precision */
5189 case 80: /* VSX Vector Multiply Single-Precision */
5190 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5191 case 233: /* ditto */
5192 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5193 case 201: /* ditto */
5194 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5195 case 249: /* ditto */
5196 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5197 case 217: /* ditto */
5198 case 104: /* VSX Vector Subtract Double-Precision */
5199 case 72: /* VSX Vector Subtract Single-Precision */
5200 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5201 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5202 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5203 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5204 case 3: /* VSX Scalar Compare Equal Double-Precision */
5205 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5206 case 19: /* VSX Scalar Compare Greater Than or Equal
5208 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5210 case 240: /* VSX Vector Copy Sign Double-Precision */
5211 case 208: /* VSX Vector Copy Sign Single-Precision */
5212 case 130: /* VSX Logical AND */
5213 case 138: /* VSX Logical AND with Complement */
5214 case 186: /* VSX Logical Equivalence */
5215 case 178: /* VSX Logical NAND */
5216 case 170: /* VSX Logical OR with Complement */
5217 case 162: /* VSX Logical NOR */
5218 case 146: /* VSX Logical OR */
5219 case 154: /* VSX Logical XOR */
5220 case 18: /* VSX Merge High Word */
5221 case 50: /* VSX Merge Low Word */
5222 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5223 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5224 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5225 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5226 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5227 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5228 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5229 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5230 case 216: /* VSX Vector Insert Exponent Single-Precision */
5231 case 248: /* VSX Vector Insert Exponent Double-Precision */
5232 case 26: /* VSX Vector Permute */
5233 case 58: /* VSX Vector Permute Right-indexed */
5234 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5235 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5236 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5237 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5238 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5241 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5242 case 125: /* VSX Vector Test for software Divide Double-Precision */
5243 case 93: /* VSX Vector Test for software Divide Single-Precision */
5244 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5247 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5248 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5249 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5250 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5251 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5255 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5257 case 99: /* VSX Vector Compare Equal To Double-Precision */
5258 case 67: /* VSX Vector Compare Equal To Single-Precision */
5259 case 115: /* VSX Vector Compare Greater Than or
5260 Equal To Double-Precision */
5261 case 83: /* VSX Vector Compare Greater Than or
5262 Equal To Single-Precision */
5263 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5264 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5266 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5267 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5268 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5274 case 265: /* VSX Scalar round Double-Precision to
5275 Single-Precision and Convert to
5276 Single-Precision format */
5277 case 344: /* VSX Scalar truncate Double-Precision to
5278 Integer and Convert to Signed Integer
5279 Doubleword format with Saturate */
5280 case 88: /* VSX Scalar truncate Double-Precision to
5281 Integer and Convert to Signed Integer Word
5282 Format with Saturate */
5283 case 328: /* VSX Scalar truncate Double-Precision integer
5284 and Convert to Unsigned Integer Doubleword
5285 Format with Saturate */
5286 case 72: /* VSX Scalar truncate Double-Precision to
5287 Integer and Convert to Unsigned Integer Word
5288 Format with Saturate */
5289 case 329: /* VSX Scalar Convert Single-Precision to
5290 Double-Precision format */
5291 case 376: /* VSX Scalar Convert Signed Integer
5292 Doubleword to floating-point format and
5293 Round to Double-Precision format */
5294 case 312: /* VSX Scalar Convert Signed Integer
5295 Doubleword to floating-point format and
5296 round to Single-Precision */
5297 case 360: /* VSX Scalar Convert Unsigned Integer
5298 Doubleword to floating-point format and
5299 Round to Double-Precision format */
5300 case 296: /* VSX Scalar Convert Unsigned Integer
5301 Doubleword to floating-point format and
5302 Round to Single-Precision */
5303 case 73: /* VSX Scalar Round to Double-Precision Integer
5304 Using Round to Nearest Away */
5305 case 107: /* VSX Scalar Round to Double-Precision Integer
5306 Exact using Current rounding mode */
5307 case 121: /* VSX Scalar Round to Double-Precision Integer
5308 Using Round toward -Infinity */
5309 case 105: /* VSX Scalar Round to Double-Precision Integer
5310 Using Round toward +Infinity */
5311 case 89: /* VSX Scalar Round to Double-Precision Integer
5312 Using Round toward Zero */
5313 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5314 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5315 case 281: /* VSX Scalar Round to Single-Precision */
5316 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5318 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5320 case 75: /* VSX Scalar Square Root Double-Precision */
5321 case 11: /* VSX Scalar Square Root Single-Precision */
5322 case 393: /* VSX Vector round Double-Precision to
5323 Single-Precision and Convert to
5324 Single-Precision format */
5325 case 472: /* VSX Vector truncate Double-Precision to
5326 Integer and Convert to Signed Integer
5327 Doubleword format with Saturate */
5328 case 216: /* VSX Vector truncate Double-Precision to
5329 Integer and Convert to Signed Integer Word
5330 Format with Saturate */
5331 case 456: /* VSX Vector truncate Double-Precision to
5332 Integer and Convert to Unsigned Integer
5333 Doubleword format with Saturate */
5334 case 200: /* VSX Vector truncate Double-Precision to
5335 Integer and Convert to Unsigned Integer Word
5336 Format with Saturate */
5337 case 457: /* VSX Vector Convert Single-Precision to
5338 Double-Precision format */
5339 case 408: /* VSX Vector truncate Single-Precision to
5340 Integer and Convert to Signed Integer
5341 Doubleword format with Saturate */
5342 case 152: /* VSX Vector truncate Single-Precision to
5343 Integer and Convert to Signed Integer Word
5344 Format with Saturate */
5345 case 392: /* VSX Vector truncate Single-Precision to
5346 Integer and Convert to Unsigned Integer
5347 Doubleword format with Saturate */
5348 case 136: /* VSX Vector truncate Single-Precision to
5349 Integer and Convert to Unsigned Integer Word
5350 Format with Saturate */
5351 case 504: /* VSX Vector Convert and round Signed Integer
5352 Doubleword to Double-Precision format */
5353 case 440: /* VSX Vector Convert and round Signed Integer
5354 Doubleword to Single-Precision format */
5355 case 248: /* VSX Vector Convert Signed Integer Word to
5356 Double-Precision format */
5357 case 184: /* VSX Vector Convert and round Signed Integer
5358 Word to Single-Precision format */
5359 case 488: /* VSX Vector Convert and round Unsigned
5360 Integer Doubleword to Double-Precision format */
5361 case 424: /* VSX Vector Convert and round Unsigned
5362 Integer Doubleword to Single-Precision format */
5363 case 232: /* VSX Vector Convert and round Unsigned
5364 Integer Word to Double-Precision format */
5365 case 168: /* VSX Vector Convert and round Unsigned
5366 Integer Word to Single-Precision format */
5367 case 201: /* VSX Vector Round to Double-Precision
5368 Integer using round to Nearest Away */
5369 case 235: /* VSX Vector Round to Double-Precision
5370 Integer Exact using Current rounding mode */
5371 case 249: /* VSX Vector Round to Double-Precision
5372 Integer using round toward -Infinity */
5373 case 233: /* VSX Vector Round to Double-Precision
5374 Integer using round toward +Infinity */
5375 case 217: /* VSX Vector Round to Double-Precision
5376 Integer using round toward Zero */
5377 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5378 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5379 case 137: /* VSX Vector Round to Single-Precision Integer
5380 Using Round to Nearest Away */
5381 case 171: /* VSX Vector Round to Single-Precision Integer
5382 Exact Using Current rounding mode */
5383 case 185: /* VSX Vector Round to Single-Precision Integer
5384 Using Round toward -Infinity */
5385 case 169: /* VSX Vector Round to Single-Precision Integer
5386 Using Round toward +Infinity */
5387 case 153: /* VSX Vector Round to Single-Precision Integer
5388 Using round toward Zero */
5389 case 202: /* VSX Vector Reciprocal Square Root Estimate
5391 case 138: /* VSX Vector Reciprocal Square Root Estimate
5393 case 203: /* VSX Vector Square Root Double-Precision */
5394 case 139: /* VSX Vector Square Root Single-Precision */
5395 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5397 case 345: /* VSX Scalar Absolute Value Double-Precision */
5398 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5399 Vector Single-Precision format Non-signalling */
5400 case 331: /* VSX Scalar Convert Single-Precision to
5401 Double-Precision format Non-signalling */
5402 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5403 case 377: /* VSX Scalar Negate Double-Precision */
5404 case 473: /* VSX Vector Absolute Value Double-Precision */
5405 case 409: /* VSX Vector Absolute Value Single-Precision */
5406 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5407 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5408 case 505: /* VSX Vector Negate Double-Precision */
5409 case 441: /* VSX Vector Negate Single-Precision */
5410 case 164: /* VSX Splat Word */
5411 case 165: /* VSX Vector Extract Unsigned Word */
5412 case 181: /* VSX Vector Insert Word */
5413 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5416 case 298: /* VSX Scalar Test Data Class Single-Precision */
5417 case 362: /* VSX Scalar Test Data Class Double-Precision */
5418 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5420 case 106: /* VSX Scalar Test for software Square Root
5422 case 234: /* VSX Vector Test for software Square Root
5424 case 170: /* VSX Vector Test for software Square Root
5426 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5430 switch (PPC_FIELD (insn
, 11, 5))
5432 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5433 case 1: /* VSX Scalar Extract Significand Double-Precision */
5434 record_full_arch_list_add_reg (regcache
,
5435 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5437 case 16: /* VSX Scalar Convert Half-Precision format to
5438 Double-Precision format */
5439 case 17: /* VSX Scalar round & Convert Double-Precision format
5440 to Half-Precision format */
5441 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5442 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5448 switch (PPC_FIELD (insn
, 11, 5))
5450 case 24: /* VSX Vector Convert Half-Precision format to
5451 Single-Precision format */
5452 case 25: /* VSX Vector round and Convert Single-Precision format
5453 to Half-Precision format */
5454 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5456 case 0: /* VSX Vector Extract Exponent Double-Precision */
5457 case 1: /* VSX Vector Extract Significand Double-Precision */
5458 case 7: /* VSX Vector Byte-Reverse Halfword */
5459 case 8: /* VSX Vector Extract Exponent Single-Precision */
5460 case 9: /* VSX Vector Extract Significand Single-Precision */
5461 case 15: /* VSX Vector Byte-Reverse Word */
5462 case 23: /* VSX Vector Byte-Reverse Doubleword */
5463 case 31: /* VSX Vector Byte-Reverse Quadword */
5464 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5472 case 360: /* VSX Vector Splat Immediate Byte */
5473 if (PPC_FIELD (insn
, 11, 2) == 0)
5475 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5479 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5480 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5484 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5486 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5490 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5491 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5495 /* Parse and record instructions of primary opcode-61 at ADDR.
5496 Return 0 if successful. */
5499 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5500 CORE_ADDR addr
, uint32_t insn
)
5502 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5508 case 0: /* Store Floating-Point Double Pair */
5509 case 2: /* Store VSX Scalar Doubleword */
5510 case 3: /* Store VSX Scalar Single */
5511 if (PPC_RA (insn
) != 0)
5512 regcache_raw_read_unsigned (regcache
,
5513 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5515 ea
+= PPC_DS (insn
) << 2;
5518 case 0: /* Store Floating-Point Double Pair */
5521 case 2: /* Store VSX Scalar Doubleword */
5524 case 3: /* Store VSX Scalar Single */
5530 record_full_arch_list_add_mem (ea
, size
);
5536 case 1: /* Load VSX Vector */
5537 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5539 case 5: /* Store VSX Vector */
5540 if (PPC_RA (insn
) != 0)
5541 regcache_raw_read_unsigned (regcache
,
5542 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5544 ea
+= PPC_DQ (insn
) << 4;
5545 record_full_arch_list_add_mem (ea
, 16);
5549 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5550 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5554 /* Parse and record instructions of primary opcode-63 at ADDR.
5555 Return 0 if successful. */
5558 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5559 CORE_ADDR addr
, uint32_t insn
)
5561 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5562 int ext
= PPC_EXTOP (insn
);
5567 case 18: /* Floating Divide */
5568 case 20: /* Floating Subtract */
5569 case 21: /* Floating Add */
5570 case 22: /* Floating Square Root */
5571 case 24: /* Floating Reciprocal Estimate */
5572 case 25: /* Floating Multiply */
5573 case 26: /* Floating Reciprocal Square Root Estimate */
5574 case 28: /* Floating Multiply-Subtract */
5575 case 29: /* Floating Multiply-Add */
5576 case 30: /* Floating Negative Multiply-Subtract */
5577 case 31: /* Floating Negative Multiply-Add */
5578 record_full_arch_list_add_reg (regcache
,
5579 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5581 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5582 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5585 case 23: /* Floating Select */
5586 record_full_arch_list_add_reg (regcache
,
5587 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5589 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5595 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5596 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5598 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5599 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5605 case 2: /* DFP Add Quad */
5606 case 3: /* DFP Quantize Quad */
5607 case 34: /* DFP Multiply Quad */
5608 case 35: /* DFP Reround Quad */
5609 case 67: /* DFP Quantize Immediate Quad */
5610 case 99: /* DFP Round To FP Integer With Inexact Quad */
5611 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5612 case 258: /* DFP Convert To DFP Extended Quad */
5613 case 514: /* DFP Subtract Quad */
5614 case 546: /* DFP Divide Quad */
5615 case 770: /* DFP Round To DFP Long Quad */
5616 case 802: /* DFP Convert From Fixed Quad */
5617 case 834: /* DFP Encode BCD To DPD Quad */
5619 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5620 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5621 record_full_arch_list_add_reg (regcache
, tmp
);
5622 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5623 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5626 case 130: /* DFP Compare Ordered Quad */
5627 case 162: /* DFP Test Exponent Quad */
5628 case 194: /* DFP Test Data Class Quad */
5629 case 226: /* DFP Test Data Group Quad */
5630 case 642: /* DFP Compare Unordered Quad */
5631 case 674: /* DFP Test Significance Quad */
5632 case 675: /* DFP Test Significance Immediate Quad */
5633 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5634 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5637 case 66: /* DFP Shift Significand Left Immediate Quad */
5638 case 98: /* DFP Shift Significand Right Immediate Quad */
5639 case 322: /* DFP Decode DPD To BCD Quad */
5640 case 866: /* DFP Insert Biased Exponent Quad */
5641 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5642 record_full_arch_list_add_reg (regcache
, tmp
);
5643 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5645 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5648 case 290: /* DFP Convert To Fixed Quad */
5649 record_full_arch_list_add_reg (regcache
,
5650 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5652 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5653 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5656 case 354: /* DFP Extract Biased Exponent Quad */
5657 record_full_arch_list_add_reg (regcache
,
5658 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5660 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5663 case 12: /* Floating Round to Single-Precision */
5664 case 14: /* Floating Convert To Integer Word */
5665 case 15: /* Floating Convert To Integer Word
5666 with round toward Zero */
5667 case 142: /* Floating Convert To Integer Word Unsigned */
5668 case 143: /* Floating Convert To Integer Word Unsigned
5669 with round toward Zero */
5670 case 392: /* Floating Round to Integer Nearest */
5671 case 424: /* Floating Round to Integer Toward Zero */
5672 case 456: /* Floating Round to Integer Plus */
5673 case 488: /* Floating Round to Integer Minus */
5674 case 814: /* Floating Convert To Integer Doubleword */
5675 case 815: /* Floating Convert To Integer Doubleword
5676 with round toward Zero */
5677 case 846: /* Floating Convert From Integer Doubleword */
5678 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5679 case 943: /* Floating Convert To Integer Doubleword Unsigned
5680 with round toward Zero */
5681 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5682 record_full_arch_list_add_reg (regcache
,
5683 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5685 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5686 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5690 switch (PPC_FIELD (insn
, 11, 5))
5692 case 1: /* Move From FPSCR & Clear Enables */
5693 case 20: /* Move From FPSCR Control & set DRN */
5694 case 21: /* Move From FPSCR Control & set DRN Immediate */
5695 case 22: /* Move From FPSCR Control & set RN */
5696 case 23: /* Move From FPSCR Control & set RN Immediate */
5697 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5699 case 0: /* Move From FPSCR */
5700 case 24: /* Move From FPSCR Lightweight */
5701 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5702 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5703 record_full_arch_list_add_reg (regcache
,
5704 tdep
->ppc_fp0_regnum
5710 case 8: /* Floating Copy Sign */
5711 case 40: /* Floating Negate */
5712 case 72: /* Floating Move Register */
5713 case 136: /* Floating Negative Absolute Value */
5714 case 264: /* Floating Absolute Value */
5715 record_full_arch_list_add_reg (regcache
,
5716 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5718 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5721 case 838: /* Floating Merge Odd Word */
5722 case 966: /* Floating Merge Even Word */
5723 record_full_arch_list_add_reg (regcache
,
5724 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5727 case 38: /* Move To FPSCR Bit 1 */
5728 case 70: /* Move To FPSCR Bit 0 */
5729 case 134: /* Move To FPSCR Field Immediate */
5730 case 711: /* Move To FPSCR Fields */
5732 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5733 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5736 case 0: /* Floating Compare Unordered */
5737 case 32: /* Floating Compare Ordered */
5738 case 64: /* Move to Condition Register from FPSCR */
5739 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5740 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5741 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5742 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5743 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5745 case 128: /* Floating Test for software Divide */
5746 case 160: /* Floating Test for software Square Root */
5747 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5750 case 4: /* VSX Scalar Add Quad-Precision */
5751 case 36: /* VSX Scalar Multiply Quad-Precision */
5752 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5753 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5754 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5755 case 484: /* VSX Scalar Negative Multiply-Subtract
5757 case 516: /* VSX Scalar Subtract Quad-Precision */
5758 case 548: /* VSX Scalar Divide Quad-Precision */
5759 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5761 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5762 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5763 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5767 switch (PPC_FIELD (insn
, 11, 5))
5769 case 27: /* VSX Scalar Square Root Quad-Precision */
5770 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5772 case 0: /* VSX Scalar Absolute Quad-Precision */
5773 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5774 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5775 case 16: /* VSX Scalar Negate Quad-Precision */
5776 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5777 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5783 switch (PPC_FIELD (insn
, 11, 5))
5785 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5786 to Unsigned Word format */
5787 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5788 Quad-Precision format */
5789 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5790 to Signed Word format */
5791 case 10: /* VSX Scalar Convert Signed Doubleword format to
5792 Quad-Precision format */
5793 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5794 to Unsigned Doubleword format */
5795 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5796 Double-Precision format */
5797 case 22: /* VSX Scalar Convert Double-Precision format to
5798 Quad-Precision format */
5799 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5800 to Signed Doubleword format */
5801 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5802 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5807 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5808 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5812 /* Parse the current instruction and record the values of the registers and
5813 memory that will be changed in current instruction to "record_arch_list".
5814 Return -1 if something wrong. */
5817 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5820 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5821 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5825 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5826 op6
= PPC_OP6 (insn
);
5830 case 2: /* Trap Doubleword Immediate */
5831 case 3: /* Trap Word Immediate */
5836 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5840 case 17: /* System call */
5841 if (PPC_LEV (insn
) != 0)
5844 if (tdep
->ppc_syscall_record
!= NULL
)
5846 if (tdep
->ppc_syscall_record (regcache
) != 0)
5851 printf_unfiltered (_("no syscall record support\n"));
5856 case 7: /* Multiply Low Immediate */
5857 record_full_arch_list_add_reg (regcache
,
5858 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5861 case 8: /* Subtract From Immediate Carrying */
5862 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5863 record_full_arch_list_add_reg (regcache
,
5864 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5867 case 10: /* Compare Logical Immediate */
5868 case 11: /* Compare Immediate */
5869 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5872 case 13: /* Add Immediate Carrying and Record */
5873 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5875 case 12: /* Add Immediate Carrying */
5876 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5878 case 14: /* Add Immediate */
5879 case 15: /* Add Immediate Shifted */
5880 record_full_arch_list_add_reg (regcache
,
5881 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5884 case 16: /* Branch Conditional */
5885 if ((PPC_BO (insn
) & 0x4) == 0)
5886 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5888 case 18: /* Branch */
5890 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5894 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5898 case 20: /* Rotate Left Word Immediate then Mask Insert */
5899 case 21: /* Rotate Left Word Immediate then AND with Mask */
5900 case 23: /* Rotate Left Word then AND with Mask */
5901 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5902 /* Rotate Left Doubleword Immediate then Clear Right */
5903 /* Rotate Left Doubleword Immediate then Clear */
5904 /* Rotate Left Doubleword then Clear Left */
5905 /* Rotate Left Doubleword then Clear Right */
5906 /* Rotate Left Doubleword Immediate then Mask Insert */
5908 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5909 record_full_arch_list_add_reg (regcache
,
5910 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5913 case 28: /* AND Immediate */
5914 case 29: /* AND Immediate Shifted */
5915 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5917 case 24: /* OR Immediate */
5918 case 25: /* OR Immediate Shifted */
5919 case 26: /* XOR Immediate */
5920 case 27: /* XOR Immediate Shifted */
5921 record_full_arch_list_add_reg (regcache
,
5922 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5926 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5930 case 33: /* Load Word and Zero with Update */
5931 case 35: /* Load Byte and Zero with Update */
5932 case 41: /* Load Halfword and Zero with Update */
5933 case 43: /* Load Halfword Algebraic with Update */
5934 record_full_arch_list_add_reg (regcache
,
5935 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5937 case 32: /* Load Word and Zero */
5938 case 34: /* Load Byte and Zero */
5939 case 40: /* Load Halfword and Zero */
5940 case 42: /* Load Halfword Algebraic */
5941 record_full_arch_list_add_reg (regcache
,
5942 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5945 case 46: /* Load Multiple Word */
5946 for (i
= PPC_RT (insn
); i
< 32; i
++)
5947 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5950 case 56: /* Load Quadword */
5951 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5952 record_full_arch_list_add_reg (regcache
, tmp
);
5953 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5956 case 49: /* Load Floating-Point Single with Update */
5957 case 51: /* Load Floating-Point Double with Update */
5958 record_full_arch_list_add_reg (regcache
,
5959 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5961 case 48: /* Load Floating-Point Single */
5962 case 50: /* Load Floating-Point Double */
5963 record_full_arch_list_add_reg (regcache
,
5964 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5967 case 47: /* Store Multiple Word */
5971 if (PPC_RA (insn
) != 0)
5972 regcache_raw_read_unsigned (regcache
,
5973 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5976 iaddr
+= PPC_D (insn
);
5977 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
5981 case 37: /* Store Word with Update */
5982 case 39: /* Store Byte with Update */
5983 case 45: /* Store Halfword with Update */
5984 case 53: /* Store Floating-Point Single with Update */
5985 case 55: /* Store Floating-Point Double with Update */
5986 record_full_arch_list_add_reg (regcache
,
5987 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5989 case 36: /* Store Word */
5990 case 38: /* Store Byte */
5991 case 44: /* Store Halfword */
5992 case 52: /* Store Floating-Point Single */
5993 case 54: /* Store Floating-Point Double */
5998 if (PPC_RA (insn
) != 0)
5999 regcache_raw_read_unsigned (regcache
,
6000 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6002 iaddr
+= PPC_D (insn
);
6004 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
6006 else if (op6
== 54 || op6
== 55)
6008 else if (op6
== 44 || op6
== 45)
6010 else if (op6
== 38 || op6
== 39)
6015 record_full_arch_list_add_mem (iaddr
, size
);
6022 case 0: /* Load Floating-Point Double Pair */
6023 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
6024 record_full_arch_list_add_reg (regcache
, tmp
);
6025 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6027 case 2: /* Load VSX Scalar Doubleword */
6028 case 3: /* Load VSX Scalar Single */
6029 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6036 case 58: /* Load Doubleword */
6037 /* Load Doubleword with Update */
6038 /* Load Word Algebraic */
6039 if (PPC_FIELD (insn
, 30, 2) > 2)
6042 record_full_arch_list_add_reg (regcache
,
6043 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6044 if (PPC_BIT (insn
, 31))
6045 record_full_arch_list_add_reg (regcache
,
6046 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6050 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
6055 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
6060 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
6064 case 62: /* Store Doubleword */
6065 /* Store Doubleword with Update */
6066 /* Store Quadword with Update */
6070 int sub2
= PPC_FIELD (insn
, 30, 2);
6075 if (PPC_RA (insn
) != 0)
6076 regcache_raw_read_unsigned (regcache
,
6077 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6080 size
= (sub2
== 2) ? 16 : 8;
6082 iaddr
+= PPC_DS (insn
) << 2;
6083 record_full_arch_list_add_mem (iaddr
, size
);
6085 if (op6
== 62 && sub2
== 1)
6086 record_full_arch_list_add_reg (regcache
,
6087 tdep
->ppc_gp0_regnum
+
6094 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
6100 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
6101 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
6105 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
6107 if (record_full_arch_list_add_end ())
6112 /* Initialize the current architecture based on INFO. If possible, re-use an
6113 architecture from ARCHES, which is a list of architectures already created
6114 during this debugging session.
6116 Called e.g. at program startup, when reading a core file, and when reading
6119 static struct gdbarch
*
6120 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6122 struct gdbarch
*gdbarch
;
6123 struct gdbarch_tdep
*tdep
;
6124 int wordsize
, from_xcoff_exec
, from_elf_exec
;
6125 enum bfd_architecture arch
;
6128 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
6130 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
6131 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
6132 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
6133 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
6134 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
6135 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
6136 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
6137 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
6138 int have_htm_tar
= 0;
6139 int tdesc_wordsize
= -1;
6140 const struct target_desc
*tdesc
= info
.target_desc
;
6141 struct tdesc_arch_data
*tdesc_data
= NULL
;
6142 int num_pseudoregs
= 0;
6145 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6146 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
6148 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6149 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
6151 /* Check word size. If INFO is from a binary file, infer it from
6152 that, else choose a likely default. */
6153 if (from_xcoff_exec
)
6155 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
6160 else if (from_elf_exec
)
6162 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6167 else if (tdesc_has_registers (tdesc
))
6171 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6172 wordsize
= (info
.bfd_arch_info
->bits_per_word
6173 / info
.bfd_arch_info
->bits_per_byte
);
6178 /* Get the architecture and machine from the BFD. */
6179 arch
= info
.bfd_arch_info
->arch
;
6180 mach
= info
.bfd_arch_info
->mach
;
6182 /* For e500 executables, the apuinfo section is of help here. Such
6183 section contains the identifier and revision number of each
6184 Application-specific Processing Unit that is present on the
6185 chip. The content of the section is determined by the assembler
6186 which looks at each instruction and determines which unit (and
6187 which version of it) can execute it. Grovel through the section
6188 looking for relevant e500 APUs. */
6190 if (bfd_uses_spe_extensions (info
.abfd
))
6192 arch
= info
.bfd_arch_info
->arch
;
6193 mach
= bfd_mach_ppc_e500
;
6194 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6195 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6198 /* Find a default target description which describes our register
6199 layout, if we do not already have one. */
6200 if (! tdesc_has_registers (tdesc
))
6202 const struct variant
*v
;
6204 /* Choose variant. */
6205 v
= find_variant_by_arch (arch
, mach
);
6212 gdb_assert (tdesc_has_registers (tdesc
));
6214 /* Check any target description for validity. */
6215 if (tdesc_has_registers (tdesc
))
6217 static const char *const gprs
[] = {
6218 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6219 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6220 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6221 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6223 const struct tdesc_feature
*feature
;
6225 static const char *const msr_names
[] = { "msr", "ps" };
6226 static const char *const cr_names
[] = { "cr", "cnd" };
6227 static const char *const ctr_names
[] = { "ctr", "cnt" };
6229 feature
= tdesc_find_feature (tdesc
,
6230 "org.gnu.gdb.power.core");
6231 if (feature
== NULL
)
6234 tdesc_data
= tdesc_data_alloc ();
6237 for (i
= 0; i
< ppc_num_gprs
; i
++)
6238 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
6239 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
6241 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
6243 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
6246 /* Allow alternate names for these registers, to accomodate GDB's
6248 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6249 PPC_MSR_REGNUM
, msr_names
);
6250 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6251 PPC_CR_REGNUM
, cr_names
);
6252 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6253 PPC_CTR_REGNUM
, ctr_names
);
6257 tdesc_data_cleanup (tdesc_data
);
6261 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
6264 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
6266 wordsize
= tdesc_wordsize
;
6268 feature
= tdesc_find_feature (tdesc
,
6269 "org.gnu.gdb.power.fpu");
6270 if (feature
!= NULL
)
6272 static const char *const fprs
[] = {
6273 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6274 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6275 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6276 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6279 for (i
= 0; i
< ppc_num_fprs
; i
++)
6280 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6281 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6282 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6283 PPC_FPSCR_REGNUM
, "fpscr");
6287 tdesc_data_cleanup (tdesc_data
);
6292 /* The fpscr register was expanded in isa 2.05 to 64 bits
6293 along with the addition of the decimal floating point
6295 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
6301 feature
= tdesc_find_feature (tdesc
,
6302 "org.gnu.gdb.power.altivec");
6303 if (feature
!= NULL
)
6305 static const char *const vector_regs
[] = {
6306 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6307 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6308 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6309 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6313 for (i
= 0; i
< ppc_num_gprs
; i
++)
6314 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6317 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6318 PPC_VSCR_REGNUM
, "vscr");
6319 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6320 PPC_VRSAVE_REGNUM
, "vrsave");
6322 if (have_spe
|| !valid_p
)
6324 tdesc_data_cleanup (tdesc_data
);
6332 /* Check for POWER7 VSX registers support. */
6333 feature
= tdesc_find_feature (tdesc
,
6334 "org.gnu.gdb.power.vsx");
6336 if (feature
!= NULL
)
6338 static const char *const vsx_regs
[] = {
6339 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6340 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6341 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6342 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6343 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6349 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6350 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6351 PPC_VSR0_UPPER_REGNUM
+ i
,
6354 if (!valid_p
|| !have_fpu
|| !have_altivec
)
6356 tdesc_data_cleanup (tdesc_data
);
6365 /* On machines supporting the SPE APU, the general-purpose registers
6366 are 64 bits long. There are SIMD vector instructions to treat them
6367 as pairs of floats, but the rest of the instruction set treats them
6368 as 32-bit registers, and only operates on their lower halves.
6370 In the GDB regcache, we treat their high and low halves as separate
6371 registers. The low halves we present as the general-purpose
6372 registers, and then we have pseudo-registers that stitch together
6373 the upper and lower halves and present them as pseudo-registers.
6375 Thus, the target description is expected to supply the upper
6376 halves separately. */
6378 feature
= tdesc_find_feature (tdesc
,
6379 "org.gnu.gdb.power.spe");
6380 if (feature
!= NULL
)
6382 static const char *const upper_spe
[] = {
6383 "ev0h", "ev1h", "ev2h", "ev3h",
6384 "ev4h", "ev5h", "ev6h", "ev7h",
6385 "ev8h", "ev9h", "ev10h", "ev11h",
6386 "ev12h", "ev13h", "ev14h", "ev15h",
6387 "ev16h", "ev17h", "ev18h", "ev19h",
6388 "ev20h", "ev21h", "ev22h", "ev23h",
6389 "ev24h", "ev25h", "ev26h", "ev27h",
6390 "ev28h", "ev29h", "ev30h", "ev31h"
6394 for (i
= 0; i
< ppc_num_gprs
; i
++)
6395 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6396 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6398 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6399 PPC_SPE_ACC_REGNUM
, "acc");
6400 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6401 PPC_SPE_FSCR_REGNUM
, "spefscr");
6403 if (have_mq
|| have_fpu
|| !valid_p
)
6405 tdesc_data_cleanup (tdesc_data
);
6413 /* Program Priority Register. */
6414 feature
= tdesc_find_feature (tdesc
,
6415 "org.gnu.gdb.power.ppr");
6416 if (feature
!= NULL
)
6419 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6420 PPC_PPR_REGNUM
, "ppr");
6424 tdesc_data_cleanup (tdesc_data
);
6432 /* Data Stream Control Register. */
6433 feature
= tdesc_find_feature (tdesc
,
6434 "org.gnu.gdb.power.dscr");
6435 if (feature
!= NULL
)
6438 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6439 PPC_DSCR_REGNUM
, "dscr");
6443 tdesc_data_cleanup (tdesc_data
);
6451 /* Target Address Register. */
6452 feature
= tdesc_find_feature (tdesc
,
6453 "org.gnu.gdb.power.tar");
6454 if (feature
!= NULL
)
6457 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6458 PPC_TAR_REGNUM
, "tar");
6462 tdesc_data_cleanup (tdesc_data
);
6470 /* Event-based Branching Registers. */
6471 feature
= tdesc_find_feature (tdesc
,
6472 "org.gnu.gdb.power.ebb");
6473 if (feature
!= NULL
)
6475 static const char *const ebb_regs
[] = {
6476 "bescr", "ebbhr", "ebbrr"
6480 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
6481 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6482 PPC_BESCR_REGNUM
+ i
,
6486 tdesc_data_cleanup (tdesc_data
);
6494 /* Subset of the ISA 2.07 Performance Monitor Registers provided
6496 feature
= tdesc_find_feature (tdesc
,
6497 "org.gnu.gdb.power.linux.pmu");
6498 if (feature
!= NULL
)
6502 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6505 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6508 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6511 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6514 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6520 tdesc_data_cleanup (tdesc_data
);
6528 /* Hardware Transactional Memory Registers. */
6529 feature
= tdesc_find_feature (tdesc
,
6530 "org.gnu.gdb.power.htm.spr");
6531 if (feature
!= NULL
)
6533 static const char *const tm_spr_regs
[] = {
6534 "tfhar", "texasr", "tfiar"
6538 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
6539 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6540 PPC_TFHAR_REGNUM
+ i
,
6544 tdesc_data_cleanup (tdesc_data
);
6553 feature
= tdesc_find_feature (tdesc
,
6554 "org.gnu.gdb.power.htm.core");
6555 if (feature
!= NULL
)
6557 static const char *const cgprs
[] = {
6558 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
6559 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
6560 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
6561 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
6562 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
6567 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
6568 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6573 tdesc_data_cleanup (tdesc_data
);
6582 feature
= tdesc_find_feature (tdesc
,
6583 "org.gnu.gdb.power.htm.fpu");
6584 if (feature
!= NULL
)
6588 static const char *const cfprs
[] = {
6589 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
6590 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
6591 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
6592 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
6593 "cf30", "cf31", "cfpscr"
6596 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
6597 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6603 tdesc_data_cleanup (tdesc_data
);
6611 feature
= tdesc_find_feature (tdesc
,
6612 "org.gnu.gdb.power.htm.altivec");
6613 if (feature
!= NULL
)
6617 static const char *const cvmx
[] = {
6618 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
6619 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
6620 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
6621 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
6622 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
6626 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
6627 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6628 PPC_CVR0_REGNUM
+ i
,
6633 tdesc_data_cleanup (tdesc_data
);
6636 have_htm_altivec
= 1;
6639 have_htm_altivec
= 0;
6641 feature
= tdesc_find_feature (tdesc
,
6642 "org.gnu.gdb.power.htm.vsx");
6643 if (feature
!= NULL
)
6647 static const char *const cvsx
[] = {
6648 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
6649 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
6650 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
6651 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
6652 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
6656 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
6657 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6658 (PPC_CVSR0_UPPER_REGNUM
6662 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
6664 tdesc_data_cleanup (tdesc_data
);
6672 feature
= tdesc_find_feature (tdesc
,
6673 "org.gnu.gdb.power.htm.ppr");
6674 if (feature
!= NULL
)
6676 valid_p
= tdesc_numbered_register (feature
, tdesc_data
,
6677 PPC_CPPR_REGNUM
, "cppr");
6681 tdesc_data_cleanup (tdesc_data
);
6689 feature
= tdesc_find_feature (tdesc
,
6690 "org.gnu.gdb.power.htm.dscr");
6691 if (feature
!= NULL
)
6693 valid_p
= tdesc_numbered_register (feature
, tdesc_data
,
6694 PPC_CDSCR_REGNUM
, "cdscr");
6698 tdesc_data_cleanup (tdesc_data
);
6706 feature
= tdesc_find_feature (tdesc
,
6707 "org.gnu.gdb.power.htm.tar");
6708 if (feature
!= NULL
)
6710 valid_p
= tdesc_numbered_register (feature
, tdesc_data
,
6711 PPC_CTAR_REGNUM
, "ctar");
6715 tdesc_data_cleanup (tdesc_data
);
6724 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6725 complain for a 32-bit binary on a 64-bit target; we do not yet
6726 support that. For instance, the 32-bit ABI routines expect
6729 As long as there isn't an explicit target description, we'll
6730 choose one based on the BFD architecture and get a word size
6731 matching the binary (probably powerpc:common or
6732 powerpc:common64). So there is only trouble if a 64-bit target
6733 supplies a 64-bit description while debugging a 32-bit
6735 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6737 tdesc_data_cleanup (tdesc_data
);
6744 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6747 elf_abi
= POWERPC_ELF_V1
;
6750 elf_abi
= POWERPC_ELF_V2
;
6757 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6759 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6760 Tag_GNU_Power_ABI_FP
) & 3)
6763 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6766 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6773 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6775 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6776 Tag_GNU_Power_ABI_FP
) >> 2)
6779 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6782 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6789 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6791 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6792 Tag_GNU_Power_ABI_Vector
))
6795 vector_abi
= POWERPC_VEC_GENERIC
;
6798 vector_abi
= POWERPC_VEC_ALTIVEC
;
6801 vector_abi
= POWERPC_VEC_SPE
;
6809 /* At this point, the only supported ELF-based 64-bit little-endian
6810 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6811 default. All other supported ELF-based operating systems use the
6812 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6813 e.g. because we run a legacy binary, or have attached to a process
6814 and have not found any associated binary file, set the default
6815 according to this heuristic. */
6816 if (elf_abi
== POWERPC_ELF_AUTO
)
6818 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6819 elf_abi
= POWERPC_ELF_V2
;
6821 elf_abi
= POWERPC_ELF_V1
;
6824 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6826 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6829 soft_float
= !have_fpu
;
6831 /* If we have a hard float binary or setting but no floating point
6832 registers, downgrade to soft float anyway. We're still somewhat
6833 useful in this scenario. */
6834 if (!soft_float
&& !have_fpu
)
6837 /* Similarly for vector registers. */
6838 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6839 vector_abi
= POWERPC_VEC_GENERIC
;
6841 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6842 vector_abi
= POWERPC_VEC_GENERIC
;
6844 if (vector_abi
== POWERPC_VEC_AUTO
)
6847 vector_abi
= POWERPC_VEC_ALTIVEC
;
6849 vector_abi
= POWERPC_VEC_SPE
;
6851 vector_abi
= POWERPC_VEC_GENERIC
;
6854 /* Do not limit the vector ABI based on available hardware, since we
6855 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6857 /* Find a candidate among extant architectures. */
6858 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6860 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6862 /* Word size in the various PowerPC bfd_arch_info structs isn't
6863 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6864 separate word size check. */
6865 tdep
= gdbarch_tdep (arches
->gdbarch
);
6866 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6868 if (tdep
&& tdep
->soft_float
!= soft_float
)
6870 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6872 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6874 if (tdep
&& tdep
->wordsize
== wordsize
)
6876 if (tdesc_data
!= NULL
)
6877 tdesc_data_cleanup (tdesc_data
);
6878 return arches
->gdbarch
;
6882 /* None found, create a new architecture from INFO, whose bfd_arch_info
6883 validity depends on the source:
6884 - executable useless
6885 - rs6000_host_arch() good
6887 - "set arch" trust blindly
6888 - GDB startup useless but harmless */
6890 tdep
= XCNEW (struct gdbarch_tdep
);
6891 tdep
->wordsize
= wordsize
;
6892 tdep
->elf_abi
= elf_abi
;
6893 tdep
->soft_float
= soft_float
;
6894 tdep
->long_double_abi
= long_double_abi
;
6895 tdep
->vector_abi
= vector_abi
;
6897 gdbarch
= gdbarch_alloc (&info
, tdep
);
6899 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6900 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6901 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6902 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6903 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6904 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6905 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6906 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6908 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6909 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6910 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6911 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6912 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6913 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6914 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6915 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6916 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
6917 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
6918 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
6919 tdep
->have_ebb
= have_ebb
;
6921 /* If additional pmu registers are added, care must be taken when
6922 setting new fields in the tdep below, to maintain compatibility
6923 with features that only provide some of the registers. Currently
6924 gdb access to the pmu registers is only supported in linux, and
6925 linux only provides a subset of the pmu registers defined in the
6928 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
6929 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
6930 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
6931 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
6932 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
6934 tdep
->have_htm_spr
= have_htm_spr
;
6935 tdep
->have_htm_core
= have_htm_core
;
6936 tdep
->have_htm_fpu
= have_htm_fpu
;
6937 tdep
->have_htm_altivec
= have_htm_altivec
;
6938 tdep
->have_htm_vsx
= have_htm_vsx
;
6939 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
6940 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
6941 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
6943 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6944 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6945 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6946 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6948 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6949 GDB traditionally called it "ps", though, so let GDB add an
6951 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6954 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6956 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6958 /* Set lr_frame_offset. */
6960 tdep
->lr_frame_offset
= 16;
6962 tdep
->lr_frame_offset
= 4;
6964 if (have_spe
|| have_dfp
|| have_altivec
6965 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
6967 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6968 set_gdbarch_pseudo_register_write (gdbarch
,
6969 rs6000_pseudo_register_write
);
6970 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6971 rs6000_ax_pseudo_register_collect
);
6974 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6976 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6978 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6981 num_pseudoregs
+= 32;
6983 num_pseudoregs
+= 16;
6985 num_pseudoregs
+= 32;
6987 /* Include both VSX and Extended FP registers. */
6988 num_pseudoregs
+= 96;
6990 num_pseudoregs
+= 16;
6991 /* Include both checkpointed VSX and EFP registers. */
6993 num_pseudoregs
+= 64 + 32;
6995 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6997 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6998 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6999 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7000 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7001 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7002 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7003 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7004 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
7005 set_gdbarch_char_signed (gdbarch
, 0);
7007 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
7010 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
7012 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
7013 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
7014 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
7016 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
7017 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
7020 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
7021 else if (wordsize
== 8)
7022 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
7024 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
7025 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
7026 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
7028 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7030 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
7031 rs6000_breakpoint::kind_from_pc
);
7032 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
7033 rs6000_breakpoint::bp_from_kind
);
7035 /* The value of symbols of type N_SO and N_FUN maybe null when
7037 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
7039 /* Handles single stepping of atomic sequences. */
7040 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
7042 /* Not sure on this. FIXMEmgo */
7043 set_gdbarch_frame_args_skip (gdbarch
, 8);
7045 /* Helpers for function argument information. */
7046 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
7049 set_gdbarch_in_solib_return_trampoline
7050 (gdbarch
, rs6000_in_solib_return_trampoline
);
7051 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
7053 /* Hook in the DWARF CFI frame unwinder. */
7054 dwarf2_append_unwinders (gdbarch
);
7055 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
7057 /* Frame handling. */
7058 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
7060 /* Setup displaced stepping. */
7061 set_gdbarch_displaced_step_copy_insn (gdbarch
,
7062 ppc_displaced_step_copy_insn
);
7063 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
7064 ppc_displaced_step_hw_singlestep
);
7065 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
7066 set_gdbarch_displaced_step_location (gdbarch
,
7067 displaced_step_at_entry_point
);
7069 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
7071 /* Hook in ABI-specific overrides, if they have been registered. */
7072 info
.target_desc
= tdesc
;
7073 info
.tdesc_data
= tdesc_data
;
7074 gdbarch_init_osabi (info
, gdbarch
);
7078 case GDB_OSABI_LINUX
:
7079 case GDB_OSABI_NETBSD
:
7080 case GDB_OSABI_UNKNOWN
:
7081 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7082 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7083 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7086 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
7088 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7089 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7090 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7093 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
7094 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
7095 rs6000_pseudo_register_reggroup_p
);
7096 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7098 /* Override the normal target description method to make the SPE upper
7099 halves anonymous. */
7100 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
7102 /* Choose register numbers for all supported pseudo-registers. */
7103 tdep
->ppc_ev0_regnum
= -1;
7104 tdep
->ppc_dl0_regnum
= -1;
7105 tdep
->ppc_v0_alias_regnum
= -1;
7106 tdep
->ppc_vsr0_regnum
= -1;
7107 tdep
->ppc_efpr0_regnum
= -1;
7108 tdep
->ppc_cdl0_regnum
= -1;
7109 tdep
->ppc_cvsr0_regnum
= -1;
7110 tdep
->ppc_cefpr0_regnum
= -1;
7112 cur_reg
= gdbarch_num_regs (gdbarch
);
7116 tdep
->ppc_ev0_regnum
= cur_reg
;
7121 tdep
->ppc_dl0_regnum
= cur_reg
;
7126 tdep
->ppc_v0_alias_regnum
= cur_reg
;
7131 tdep
->ppc_vsr0_regnum
= cur_reg
;
7133 tdep
->ppc_efpr0_regnum
= cur_reg
;
7138 tdep
->ppc_cdl0_regnum
= cur_reg
;
7143 tdep
->ppc_cvsr0_regnum
= cur_reg
;
7145 tdep
->ppc_cefpr0_regnum
= cur_reg
;
7149 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
7151 /* Register the ravenscar_arch_ops. */
7152 if (mach
== bfd_mach_ppc_e500
)
7153 register_e500_ravenscar_ops (gdbarch
);
7155 register_ppc_ravenscar_ops (gdbarch
);
7157 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
7158 set_gdbarch_valid_disassembler_options (gdbarch
,
7159 disassembler_options_powerpc ());
7165 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7172 /* FIXME: Dump gdbarch_tdep. */
7175 /* PowerPC-specific commands. */
7178 set_powerpc_command (const char *args
, int from_tty
)
7180 printf_unfiltered (_("\
7181 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
7182 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
7186 show_powerpc_command (const char *args
, int from_tty
)
7188 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
7192 powerpc_set_soft_float (const char *args
, int from_tty
,
7193 struct cmd_list_element
*c
)
7195 struct gdbarch_info info
;
7197 /* Update the architecture. */
7198 gdbarch_info_init (&info
);
7199 if (!gdbarch_update_p (info
))
7200 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7204 powerpc_set_vector_abi (const char *args
, int from_tty
,
7205 struct cmd_list_element
*c
)
7207 struct gdbarch_info info
;
7210 for (vector_abi
= POWERPC_VEC_AUTO
;
7211 vector_abi
!= POWERPC_VEC_LAST
;
7213 if (strcmp (powerpc_vector_abi_string
,
7214 powerpc_vector_strings
[vector_abi
]) == 0)
7216 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
7220 if (vector_abi
== POWERPC_VEC_LAST
)
7221 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
7222 powerpc_vector_abi_string
);
7224 /* Update the architecture. */
7225 gdbarch_info_init (&info
);
7226 if (!gdbarch_update_p (info
))
7227 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7230 /* Show the current setting of the exact watchpoints flag. */
7233 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
7234 struct cmd_list_element
*c
,
7237 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
7240 /* Read a PPC instruction from memory. */
7243 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
7245 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7246 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7248 return read_memory_unsigned_integer (pc
, 4, byte_order
);
7251 /* Return non-zero if the instructions at PC match the series
7252 described in PATTERN, or zero otherwise. PATTERN is an array of
7253 'struct ppc_insn_pattern' objects, terminated by an entry whose
7256 When the match is successful, fill INSNS[i] with what PATTERN[i]
7257 matched. If PATTERN[i] is optional, and the instruction wasn't
7258 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
7259 INSNS should have as many elements as PATTERN, minus the terminator.
7260 Note that, if PATTERN contains optional instructions which aren't
7261 present in memory, then INSNS will have holes, so INSNS[i] isn't
7262 necessarily the i'th instruction in memory. */
7265 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
7266 const struct ppc_insn_pattern
*pattern
,
7267 unsigned int *insns
)
7272 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
7275 insn
= read_insn (frame
, pc
);
7277 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
7283 else if (!pattern
[i
].optional
)
7290 /* Return the 'd' field of the d-form instruction INSN, properly
7294 ppc_insn_d_field (unsigned int insn
)
7296 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
7299 /* Return the 'ds' field of the ds-form instruction INSN, with the two
7300 zero bits concatenated at the right, and properly
7304 ppc_insn_ds_field (unsigned int insn
)
7306 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
7309 /* Initialization code. */
7311 void _initialize_rs6000_tdep ();
7313 _initialize_rs6000_tdep ()
7315 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7316 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7318 /* Initialize the standard target descriptions. */
7319 initialize_tdesc_powerpc_32 ();
7320 initialize_tdesc_powerpc_altivec32 ();
7321 initialize_tdesc_powerpc_vsx32 ();
7322 initialize_tdesc_powerpc_403 ();
7323 initialize_tdesc_powerpc_403gc ();
7324 initialize_tdesc_powerpc_405 ();
7325 initialize_tdesc_powerpc_505 ();
7326 initialize_tdesc_powerpc_601 ();
7327 initialize_tdesc_powerpc_602 ();
7328 initialize_tdesc_powerpc_603 ();
7329 initialize_tdesc_powerpc_604 ();
7330 initialize_tdesc_powerpc_64 ();
7331 initialize_tdesc_powerpc_altivec64 ();
7332 initialize_tdesc_powerpc_vsx64 ();
7333 initialize_tdesc_powerpc_7400 ();
7334 initialize_tdesc_powerpc_750 ();
7335 initialize_tdesc_powerpc_860 ();
7336 initialize_tdesc_powerpc_e500 ();
7337 initialize_tdesc_rs6000 ();
7339 /* Add root prefix command for all "set powerpc"/"show powerpc"
7341 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
7342 _("Various PowerPC-specific commands."),
7343 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
7345 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
7346 _("Various PowerPC-specific commands."),
7347 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
7349 /* Add a command to allow the user to force the ABI. */
7350 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
7351 &powerpc_soft_float_global
,
7352 _("Set whether to use a soft-float ABI."),
7353 _("Show whether to use a soft-float ABI."),
7355 powerpc_set_soft_float
, NULL
,
7356 &setpowerpccmdlist
, &showpowerpccmdlist
);
7358 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
7359 &powerpc_vector_abi_string
,
7360 _("Set the vector ABI."),
7361 _("Show the vector ABI."),
7362 NULL
, powerpc_set_vector_abi
, NULL
,
7363 &setpowerpccmdlist
, &showpowerpccmdlist
);
7365 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
7366 &target_exact_watchpoints
,
7368 Set whether to use just one debug register for watchpoints on scalars."),
7370 Show whether to use just one debug register for watchpoints on scalars."),
7372 If true, GDB will use only one debug register when watching a variable of\n\
7373 scalar type, thus assuming that the variable is accessed through the address\n\
7374 of its first byte."),
7375 NULL
, show_powerpc_exact_watchpoints
,
7376 &setpowerpccmdlist
, &showpowerpccmdlist
);