1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* To be used by skip_prologue. */
158 struct rs6000_framedata
160 int offset
; /* total size of frame --- the distance
161 by which we decrement sp to allocate
163 int saved_gpr
; /* smallest # of saved gpr */
164 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
165 int saved_fpr
; /* smallest # of saved fpr */
166 int saved_vr
; /* smallest # of saved vr */
167 int saved_ev
; /* smallest # of saved ev */
168 int alloca_reg
; /* alloca register number (frame ptr) */
169 char frameless
; /* true if frameless functions. */
170 char nosavedpc
; /* true if pc not saved. */
171 char used_bl
; /* true if link register clobbered */
172 int gpr_offset
; /* offset of saved gprs from prev sp */
173 int fpr_offset
; /* offset of saved fprs from prev sp */
174 int vr_offset
; /* offset of saved vrs from prev sp */
175 int ev_offset
; /* offset of saved evs from prev sp */
176 int lr_offset
; /* offset of saved lr */
177 int lr_register
; /* register of saved lr, if trustworthy */
178 int cr_offset
; /* offset of saved cr */
179 int vrsave_offset
; /* offset of saved vrsave register */
183 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
185 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
188 if (tdep
->ppc_vsr0_regnum
< 0)
191 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
192 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
195 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
197 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
199 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
200 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
203 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
207 /* Return true if REGNO is an SPE register, false otherwise. */
209 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
211 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
213 /* Is it a reference to EV0 -- EV31, and do we have those? */
214 if (IS_SPE_PSEUDOREG (tdep
, regno
))
217 /* Is it a reference to one of the raw upper GPR halves? */
218 if (tdep
->ppc_ev0_upper_regnum
>= 0
219 && tdep
->ppc_ev0_upper_regnum
<= regno
220 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
223 /* Is it a reference to the 64-bit accumulator, and do we have that? */
224 if (tdep
->ppc_acc_regnum
>= 0
225 && tdep
->ppc_acc_regnum
== regno
)
228 /* Is it a reference to the SPE floating-point status and control register,
229 and do we have that? */
230 if (tdep
->ppc_spefscr_regnum
>= 0
231 && tdep
->ppc_spefscr_regnum
== regno
)
238 /* Return non-zero if the architecture described by GDBARCH has
239 floating-point registers (f0 --- f31 and fpscr). */
241 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
243 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
245 return (tdep
->ppc_fp0_regnum
>= 0
246 && tdep
->ppc_fpscr_regnum
>= 0);
249 /* Return non-zero if the architecture described by GDBARCH has
250 Altivec registers (vr0 --- vr31, vrsave and vscr). */
252 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
254 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
256 return (tdep
->ppc_vr0_regnum
>= 0
257 && tdep
->ppc_vrsave_regnum
>= 0);
260 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
263 This is a helper function for init_sim_regno_table, constructing
264 the table mapping GDB register numbers to sim register numbers; we
265 initialize every element in that table to -1 before we start
268 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
270 /* Make sure we don't try to assign any given GDB register a sim
271 register number more than once. */
272 gdb_assert (table
[gdb_regno
] == -1);
273 table
[gdb_regno
] = sim_regno
;
277 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
278 numbers to simulator register numbers, based on the values placed
279 in the ARCH->tdep->ppc_foo_regnum members. */
281 init_sim_regno_table (struct gdbarch
*arch
)
283 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
284 int total_regs
= gdbarch_num_regs (arch
);
285 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
287 static const char *const segment_regs
[] = {
288 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
289 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
292 /* Presume that all registers not explicitly mentioned below are
293 unavailable from the sim. */
294 for (i
= 0; i
< total_regs
; i
++)
297 /* General-purpose registers. */
298 for (i
= 0; i
< ppc_num_gprs
; i
++)
299 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
301 /* Floating-point registers. */
302 if (tdep
->ppc_fp0_regnum
>= 0)
303 for (i
= 0; i
< ppc_num_fprs
; i
++)
304 set_sim_regno (sim_regno
,
305 tdep
->ppc_fp0_regnum
+ i
,
306 sim_ppc_f0_regnum
+ i
);
307 if (tdep
->ppc_fpscr_regnum
>= 0)
308 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
310 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
311 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
312 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
314 /* Segment registers. */
315 for (i
= 0; i
< ppc_num_srs
; i
++)
319 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
321 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
324 /* Altivec registers. */
325 if (tdep
->ppc_vr0_regnum
>= 0)
327 for (i
= 0; i
< ppc_num_vrs
; i
++)
328 set_sim_regno (sim_regno
,
329 tdep
->ppc_vr0_regnum
+ i
,
330 sim_ppc_vr0_regnum
+ i
);
332 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
333 we can treat this more like the other cases. */
334 set_sim_regno (sim_regno
,
335 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
336 sim_ppc_vscr_regnum
);
338 /* vsave is a special-purpose register, so the code below handles it. */
340 /* SPE APU (E500) registers. */
341 if (tdep
->ppc_ev0_upper_regnum
>= 0)
342 for (i
= 0; i
< ppc_num_gprs
; i
++)
343 set_sim_regno (sim_regno
,
344 tdep
->ppc_ev0_upper_regnum
+ i
,
345 sim_ppc_rh0_regnum
+ i
);
346 if (tdep
->ppc_acc_regnum
>= 0)
347 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
348 /* spefscr is a special-purpose register, so the code below handles it. */
351 /* Now handle all special-purpose registers. Verify that they
352 haven't mistakenly been assigned numbers by any of the above
354 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
356 const char *spr_name
= sim_spr_register_name (i
);
359 if (spr_name
!= NULL
)
360 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
363 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
367 /* Drop the initialized array into place. */
368 tdep
->sim_regno
= sim_regno
;
372 /* Given a GDB register number REG, return the corresponding SIM
375 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
377 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
380 if (tdep
->sim_regno
== NULL
)
381 init_sim_regno_table (gdbarch
);
383 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
384 sim_regno
= tdep
->sim_regno
[reg
];
389 return LEGACY_SIM_REGNO_IGNORE
;
394 /* Register set support functions. */
396 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
397 Write the register to REGCACHE. */
400 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
401 const gdb_byte
*regs
, size_t offset
, int regsize
)
403 if (regnum
!= -1 && offset
!= -1)
407 struct gdbarch
*gdbarch
= regcache
->arch ();
408 int gdb_regsize
= register_size (gdbarch
, regnum
);
409 if (gdb_regsize
< regsize
410 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
411 offset
+= regsize
- gdb_regsize
;
413 regcache
->raw_supply (regnum
, regs
+ offset
);
417 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
418 in a field REGSIZE wide. Zero pad as necessary. */
421 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
422 gdb_byte
*regs
, size_t offset
, int regsize
)
424 if (regnum
!= -1 && offset
!= -1)
428 struct gdbarch
*gdbarch
= regcache
->arch ();
429 int gdb_regsize
= register_size (gdbarch
, regnum
);
430 if (gdb_regsize
< regsize
)
432 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
434 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
435 offset
+= regsize
- gdb_regsize
;
438 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
439 regsize
- gdb_regsize
);
442 regcache
->raw_collect (regnum
, regs
+ offset
);
447 ppc_greg_offset (struct gdbarch
*gdbarch
,
448 struct gdbarch_tdep
*tdep
,
449 const struct ppc_reg_offsets
*offsets
,
453 *regsize
= offsets
->gpr_size
;
454 if (regnum
>= tdep
->ppc_gp0_regnum
455 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
456 return (offsets
->r0_offset
457 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
459 if (regnum
== gdbarch_pc_regnum (gdbarch
))
460 return offsets
->pc_offset
;
462 if (regnum
== tdep
->ppc_ps_regnum
)
463 return offsets
->ps_offset
;
465 if (regnum
== tdep
->ppc_lr_regnum
)
466 return offsets
->lr_offset
;
468 if (regnum
== tdep
->ppc_ctr_regnum
)
469 return offsets
->ctr_offset
;
471 *regsize
= offsets
->xr_size
;
472 if (regnum
== tdep
->ppc_cr_regnum
)
473 return offsets
->cr_offset
;
475 if (regnum
== tdep
->ppc_xer_regnum
)
476 return offsets
->xer_offset
;
478 if (regnum
== tdep
->ppc_mq_regnum
)
479 return offsets
->mq_offset
;
485 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
486 const struct ppc_reg_offsets
*offsets
,
489 if (regnum
>= tdep
->ppc_fp0_regnum
490 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
491 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
493 if (regnum
== tdep
->ppc_fpscr_regnum
)
494 return offsets
->fpscr_offset
;
499 /* Supply register REGNUM in the general-purpose register set REGSET
500 from the buffer specified by GREGS and LEN to register cache
501 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
504 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
505 int regnum
, const void *gregs
, size_t len
)
507 struct gdbarch
*gdbarch
= regcache
->arch ();
508 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
509 const struct ppc_reg_offsets
*offsets
510 = (const struct ppc_reg_offsets
*) regset
->regmap
;
517 int gpr_size
= offsets
->gpr_size
;
519 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
520 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
521 i
++, offset
+= gpr_size
)
522 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
525 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
526 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
527 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
528 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
529 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
530 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
531 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
532 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
533 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
534 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
536 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
537 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
539 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
540 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
545 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
546 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
549 /* Supply register REGNUM in the floating-point register set REGSET
550 from the buffer specified by FPREGS and LEN to register cache
551 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
554 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
555 int regnum
, const void *fpregs
, size_t len
)
557 struct gdbarch
*gdbarch
= regcache
->arch ();
558 struct gdbarch_tdep
*tdep
;
559 const struct ppc_reg_offsets
*offsets
;
562 if (!ppc_floating_point_unit_p (gdbarch
))
565 tdep
= gdbarch_tdep (gdbarch
);
566 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
571 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
572 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
574 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
576 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
577 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
578 offsets
->fpscr_size
);
582 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
583 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
584 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
587 /* Collect register REGNUM in the general-purpose register set
588 REGSET from register cache REGCACHE into the buffer specified by
589 GREGS and LEN. If REGNUM is -1, do this for all registers in
593 ppc_collect_gregset (const struct regset
*regset
,
594 const struct regcache
*regcache
,
595 int regnum
, void *gregs
, size_t len
)
597 struct gdbarch
*gdbarch
= regcache
->arch ();
598 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
599 const struct ppc_reg_offsets
*offsets
600 = (const struct ppc_reg_offsets
*) regset
->regmap
;
607 int gpr_size
= offsets
->gpr_size
;
609 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
610 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
611 i
++, offset
+= gpr_size
)
612 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
614 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
615 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
616 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
617 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
618 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
619 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
620 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
621 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
622 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
623 (gdb_byte
*) gregs
, offsets
->cr_offset
,
625 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
626 (gdb_byte
*) gregs
, offsets
->xer_offset
,
628 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
629 (gdb_byte
*) gregs
, offsets
->mq_offset
,
634 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
635 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
638 /* Collect register REGNUM in the floating-point register set
639 REGSET from register cache REGCACHE into the buffer specified by
640 FPREGS and LEN. If REGNUM is -1, do this for all registers in
644 ppc_collect_fpregset (const struct regset
*regset
,
645 const struct regcache
*regcache
,
646 int regnum
, void *fpregs
, size_t len
)
648 struct gdbarch
*gdbarch
= regcache
->arch ();
649 struct gdbarch_tdep
*tdep
;
650 const struct ppc_reg_offsets
*offsets
;
653 if (!ppc_floating_point_unit_p (gdbarch
))
656 tdep
= gdbarch_tdep (gdbarch
);
657 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
662 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
663 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
665 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
667 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
668 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
669 offsets
->fpscr_size
);
673 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
674 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
675 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
679 insn_changes_sp_or_jumps (unsigned long insn
)
681 int opcode
= (insn
>> 26) & 0x03f;
682 int sd
= (insn
>> 21) & 0x01f;
683 int a
= (insn
>> 16) & 0x01f;
684 int subcode
= (insn
>> 1) & 0x3ff;
686 /* Changes the stack pointer. */
688 /* NOTE: There are many ways to change the value of a given register.
689 The ways below are those used when the register is R1, the SP,
690 in a funtion's epilogue. */
692 if (opcode
== 31 && subcode
== 444 && a
== 1)
693 return 1; /* mr R1,Rn */
694 if (opcode
== 14 && sd
== 1)
695 return 1; /* addi R1,Rn,simm */
696 if (opcode
== 58 && sd
== 1)
697 return 1; /* ld R1,ds(Rn) */
699 /* Transfers control. */
705 if (opcode
== 19 && subcode
== 16)
707 if (opcode
== 19 && subcode
== 528)
708 return 1; /* bcctr */
713 /* Return true if we are in the function's epilogue, i.e. after the
714 instruction that destroyed the function's stack frame.
716 1) scan forward from the point of execution:
717 a) If you find an instruction that modifies the stack pointer
718 or transfers control (except a return), execution is not in
720 b) Stop scanning if you find a return instruction or reach the
721 end of the function or reach the hard limit for the size of
723 2) scan backward from the point of execution:
724 a) If you find an instruction that modifies the stack pointer,
725 execution *is* in an epilogue, return.
726 b) Stop scanning if you reach an instruction that transfers
727 control or the beginning of the function or reach the hard
728 limit for the size of an epilogue. */
731 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
732 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
735 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
736 bfd_byte insn_buf
[PPC_INSN_SIZE
];
737 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
740 /* Find the search limits based on function boundaries and hard limit. */
742 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
745 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
746 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
748 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
749 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
751 /* Scan forward until next 'blr'. */
753 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
755 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
757 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
758 if (insn
== 0x4e800020)
760 /* Assume a bctr is a tail call unless it points strictly within
762 if (insn
== 0x4e800420)
764 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
765 tdep
->ppc_ctr_regnum
);
766 if (ctr
> func_start
&& ctr
< func_end
)
771 if (insn_changes_sp_or_jumps (insn
))
775 /* Scan backward until adjustment to stack pointer (R1). */
777 for (scan_pc
= pc
- PPC_INSN_SIZE
;
778 scan_pc
>= epilogue_start
;
779 scan_pc
-= PPC_INSN_SIZE
)
781 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
783 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
784 if (insn_changes_sp_or_jumps (insn
))
791 /* Implement the stack_frame_destroyed_p gdbarch method. */
794 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
796 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
800 /* Get the ith function argument for the current function. */
802 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
805 return get_frame_register_unsigned (frame
, 3 + argi
);
808 /* Sequence of bytes for breakpoint instruction. */
810 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
811 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
813 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
816 /* Instruction masks for displaced stepping. */
817 #define BRANCH_MASK 0xfc000000
818 #define BP_MASK 0xFC0007FE
819 #define B_INSN 0x48000000
820 #define BC_INSN 0x40000000
821 #define BXL_INSN 0x4c000000
822 #define BP_INSN 0x7C000008
824 /* Instruction masks used during single-stepping of atomic
826 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
827 #define LWARX_INSTRUCTION 0x7c000028
828 #define LDARX_INSTRUCTION 0x7c0000A8
829 #define LBARX_INSTRUCTION 0x7c000068
830 #define LHARX_INSTRUCTION 0x7c0000e8
831 #define LQARX_INSTRUCTION 0x7c000228
832 #define STORE_CONDITIONAL_MASK 0xfc0007ff
833 #define STWCX_INSTRUCTION 0x7c00012d
834 #define STDCX_INSTRUCTION 0x7c0001ad
835 #define STBCX_INSTRUCTION 0x7c00056d
836 #define STHCX_INSTRUCTION 0x7c0005ad
837 #define STQCX_INSTRUCTION 0x7c00016d
839 /* Check if insn is one of the Load And Reserve instructions used for atomic
841 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
842 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
843 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
844 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
845 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
846 /* Check if insn is one of the Store Conditional instructions used for atomic
848 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
849 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
850 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
851 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
852 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
854 typedef buf_displaced_step_closure ppc_displaced_step_closure
;
856 /* We can't displaced step atomic sequences. */
858 static struct displaced_step_closure
*
859 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
860 CORE_ADDR from
, CORE_ADDR to
,
861 struct regcache
*regs
)
863 size_t len
= gdbarch_max_insn_length (gdbarch
);
864 std::unique_ptr
<ppc_displaced_step_closure
> closure
865 (new ppc_displaced_step_closure (len
));
866 gdb_byte
*buf
= closure
->buf
.data ();
867 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
870 read_memory (from
, buf
, len
);
872 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
874 /* Assume all atomic sequences start with a Load and Reserve instruction. */
875 if (IS_LOAD_AND_RESERVE_INSN (insn
))
879 fprintf_unfiltered (gdb_stdlog
,
880 "displaced: can't displaced step "
881 "atomic sequence at %s\n",
882 paddress (gdbarch
, from
));
888 write_memory (to
, buf
, len
);
892 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
893 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
894 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
897 return closure
.release ();
900 /* Fix up the state of registers and memory after having single-stepped
901 a displaced instruction. */
903 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
904 struct displaced_step_closure
*closure_
,
905 CORE_ADDR from
, CORE_ADDR to
,
906 struct regcache
*regs
)
908 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
909 /* Our closure is a copy of the instruction. */
910 ppc_displaced_step_closure
*closure
= (ppc_displaced_step_closure
*) closure_
;
911 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
912 PPC_INSN_SIZE
, byte_order
);
914 /* Offset for non PC-relative instructions. */
915 LONGEST offset
= PPC_INSN_SIZE
;
917 opcode
= insn
& BRANCH_MASK
;
920 fprintf_unfiltered (gdb_stdlog
,
921 "displaced: (ppc) fixup (%s, %s)\n",
922 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
925 /* Handle PC-relative branch instructions. */
926 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
930 /* Read the current PC value after the instruction has been executed
931 in a displaced location. Calculate the offset to be applied to the
932 original PC value before the displaced stepping. */
933 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
935 offset
= current_pc
- to
;
937 if (opcode
!= BXL_INSN
)
939 /* Check for AA bit indicating whether this is an absolute
940 addressing or PC-relative (1: absolute, 0: relative). */
943 /* PC-relative addressing is being used in the branch. */
947 "displaced: (ppc) branch instruction: %s\n"
948 "displaced: (ppc) adjusted PC from %s to %s\n",
949 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
950 paddress (gdbarch
, from
+ offset
));
952 regcache_cooked_write_unsigned (regs
,
953 gdbarch_pc_regnum (gdbarch
),
959 /* If we're here, it means we have a branch to LR or CTR. If the
960 branch was taken, the offset is probably greater than 4 (the next
961 instruction), so it's safe to assume that an offset of 4 means we
962 did not take the branch. */
963 if (offset
== PPC_INSN_SIZE
)
964 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
965 from
+ PPC_INSN_SIZE
);
968 /* Check for LK bit indicating whether we should set the link
969 register to point to the next instruction
970 (1: Set, 0: Don't set). */
973 /* Link register needs to be set to the next instruction's PC. */
974 regcache_cooked_write_unsigned (regs
,
975 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
976 from
+ PPC_INSN_SIZE
);
978 fprintf_unfiltered (gdb_stdlog
,
979 "displaced: (ppc) adjusted LR to %s\n",
980 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
984 /* Check for breakpoints in the inferior. If we've found one, place the PC
985 right at the breakpoint instruction. */
986 else if ((insn
& BP_MASK
) == BP_INSN
)
987 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
989 /* Handle any other instructions that do not fit in the categories above. */
990 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
994 /* Always use hardware single-stepping to execute the
995 displaced instruction. */
997 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
998 struct displaced_step_closure
*closure
)
1003 /* Checks for an atomic sequence of instructions beginning with a
1004 Load And Reserve instruction and ending with a Store Conditional
1005 instruction. If such a sequence is found, attempt to step through it.
1006 A breakpoint is placed at the end of the sequence. */
1007 std::vector
<CORE_ADDR
>
1008 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1010 struct gdbarch
*gdbarch
= regcache
->arch ();
1011 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1012 CORE_ADDR pc
= regcache_read_pc (regcache
);
1013 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1015 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1016 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1019 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1020 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1021 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1023 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1024 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1027 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1029 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1031 loc
+= PPC_INSN_SIZE
;
1032 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1034 /* Assume that there is at most one conditional branch in the atomic
1035 sequence. If a conditional branch is found, put a breakpoint in
1036 its destination address. */
1037 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1039 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1040 int absolute
= insn
& 2;
1042 if (bc_insn_count
>= 1)
1043 return {}; /* More than one conditional branch found, fallback
1044 to the standard single-step code. */
1047 breaks
[1] = immediate
;
1049 breaks
[1] = loc
+ immediate
;
1055 if (IS_STORE_CONDITIONAL_INSN (insn
))
1059 /* Assume that the atomic sequence ends with a Store Conditional
1061 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1065 loc
+= PPC_INSN_SIZE
;
1067 /* Insert a breakpoint right after the end of the atomic sequence. */
1070 /* Check for duplicated breakpoints. Check also for a breakpoint
1071 placed (branch instruction's destination) anywhere in sequence. */
1073 && (breaks
[1] == breaks
[0]
1074 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1075 last_breakpoint
= 0;
1077 std::vector
<CORE_ADDR
> next_pcs
;
1079 for (index
= 0; index
<= last_breakpoint
; index
++)
1080 next_pcs
.push_back (breaks
[index
]);
1086 #define SIGNED_SHORT(x) \
1087 ((sizeof (short) == 2) \
1088 ? ((int)(short)(x)) \
1089 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1091 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1093 /* Limit the number of skipped non-prologue instructions, as the examining
1094 of the prologue is expensive. */
1095 static int max_skip_non_prologue_insns
= 10;
1097 /* Return nonzero if the given instruction OP can be part of the prologue
1098 of a function and saves a parameter on the stack. FRAMEP should be
1099 set if one of the previous instructions in the function has set the
1103 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1105 /* Move parameters from argument registers to temporary register. */
1106 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1108 /* Rx must be scratch register r0. */
1109 const int rx_regno
= (op
>> 16) & 31;
1110 /* Ry: Only r3 - r10 are used for parameter passing. */
1111 const int ry_regno
= GET_SRC_REG (op
);
1113 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1115 *r0_contains_arg
= 1;
1122 /* Save a General Purpose Register on stack. */
1124 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1125 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1127 /* Rx: Only r3 - r10 are used for parameter passing. */
1128 const int rx_regno
= GET_SRC_REG (op
);
1130 return (rx_regno
>= 3 && rx_regno
<= 10);
1133 /* Save a General Purpose Register on stack via the Frame Pointer. */
1136 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1137 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1138 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1140 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1141 However, the compiler sometimes uses r0 to hold an argument. */
1142 const int rx_regno
= GET_SRC_REG (op
);
1144 return ((rx_regno
>= 3 && rx_regno
<= 10)
1145 || (rx_regno
== 0 && *r0_contains_arg
));
1148 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1150 /* Only f2 - f8 are used for parameter passing. */
1151 const int src_regno
= GET_SRC_REG (op
);
1153 return (src_regno
>= 2 && src_regno
<= 8);
1156 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1158 /* Only f2 - f8 are used for parameter passing. */
1159 const int src_regno
= GET_SRC_REG (op
);
1161 return (src_regno
>= 2 && src_regno
<= 8);
1164 /* Not an insn that saves a parameter on stack. */
1168 /* Assuming that INSN is a "bl" instruction located at PC, return
1169 nonzero if the destination of the branch is a "blrl" instruction.
1171 This sequence is sometimes found in certain function prologues.
1172 It allows the function to load the LR register with a value that
1173 they can use to access PIC data using PC-relative offsets. */
1176 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1183 absolute
= (int) ((insn
>> 1) & 1);
1184 immediate
= ((insn
& ~3) << 6) >> 6;
1188 dest
= pc
+ immediate
;
1190 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1191 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1197 /* Return true if OP is a stw or std instruction with
1198 register operands RS and RA and any immediate offset.
1200 If WITH_UPDATE is true, also return true if OP is
1201 a stwu or stdu instruction with the same operands.
1203 Return false otherwise.
1206 store_insn_p (unsigned long op
, unsigned long rs
,
1207 unsigned long ra
, bool with_update
)
1212 if (/* std RS, SIMM(RA) */
1213 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1214 /* stw RS, SIMM(RA) */
1215 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1220 if (/* stdu RS, SIMM(RA) */
1221 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1222 /* stwu RS, SIMM(RA) */
1223 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1230 /* Masks for decoding a branch-and-link (bl) instruction.
1232 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1233 The former is anded with the opcode in question; if the result of
1234 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1235 question is a ``bl'' instruction.
1237 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1238 the branch displacement. */
1240 #define BL_MASK 0xfc000001
1241 #define BL_INSTRUCTION 0x48000001
1242 #define BL_DISPLACEMENT_MASK 0x03fffffc
1244 static unsigned long
1245 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1247 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1251 /* Fetch the instruction and convert it to an integer. */
1252 if (target_read_memory (pc
, buf
, 4))
1254 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1259 /* GCC generates several well-known sequences of instructions at the begining
1260 of each function prologue when compiling with -fstack-check. If one of
1261 such sequences starts at START_PC, then return the address of the
1262 instruction immediately past this sequence. Otherwise, return START_PC. */
1265 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1267 CORE_ADDR pc
= start_pc
;
1268 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1270 /* First possible sequence: A small number of probes.
1271 stw 0, -<some immediate>(1)
1272 [repeat this instruction any (small) number of times]. */
1274 if ((op
& 0xffff0000) == 0x90010000)
1276 while ((op
& 0xffff0000) == 0x90010000)
1279 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1284 /* Second sequence: A probing loop.
1285 addi 12,1,-<some immediate>
1286 lis 0,-<some immediate>
1287 [possibly ori 0,0,<some immediate>]
1291 addi 12,12,-<some immediate>
1294 [possibly one last probe: stw 0,<some immediate>(12)]. */
1298 /* addi 12,1,-<some immediate> */
1299 if ((op
& 0xffff0000) != 0x39810000)
1302 /* lis 0,-<some immediate> */
1304 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1305 if ((op
& 0xffff0000) != 0x3c000000)
1309 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1310 /* [possibly ori 0,0,<some immediate>] */
1311 if ((op
& 0xffff0000) == 0x60000000)
1314 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1317 if (op
!= 0x7c0c0214)
1322 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1323 if (op
!= 0x7c0c0000)
1328 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1329 if ((op
& 0xff9f0001) != 0x41820000)
1332 /* addi 12,12,-<some immediate> */
1334 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1335 if ((op
& 0xffff0000) != 0x398c0000)
1340 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1341 if (op
!= 0x900c0000)
1346 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1347 if ((op
& 0xfc000001) != 0x48000000)
1350 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1352 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1353 if ((op
& 0xffff0000) == 0x900c0000)
1356 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1359 /* We found a valid stack-check sequence, return the new PC. */
1363 /* Third sequence: No probe; instead, a comparizon between the stack size
1364 limit (saved in a run-time global variable) and the current stack
1367 addi 0,1,-<some immediate>
1368 lis 12,__gnat_stack_limit@ha
1369 lwz 12,__gnat_stack_limit@l(12)
1372 or, with a small variant in the case of a bigger stack frame:
1373 addis 0,1,<some immediate>
1374 addic 0,0,-<some immediate>
1375 lis 12,__gnat_stack_limit@ha
1376 lwz 12,__gnat_stack_limit@l(12)
1381 /* addi 0,1,-<some immediate> */
1382 if ((op
& 0xffff0000) != 0x38010000)
1384 /* small stack frame variant not recognized; try the
1385 big stack frame variant: */
1387 /* addis 0,1,<some immediate> */
1388 if ((op
& 0xffff0000) != 0x3c010000)
1391 /* addic 0,0,-<some immediate> */
1393 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1394 if ((op
& 0xffff0000) != 0x30000000)
1398 /* lis 12,<some immediate> */
1400 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1401 if ((op
& 0xffff0000) != 0x3d800000)
1404 /* lwz 12,<some immediate>(12) */
1406 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1407 if ((op
& 0xffff0000) != 0x818c0000)
1412 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1413 if ((op
& 0xfffffffe) != 0x7c406008)
1416 /* We found a valid stack-check sequence, return the new PC. */
1420 /* No stack check code in our prologue, return the start_pc. */
1424 /* return pc value after skipping a function prologue and also return
1425 information about a function frame.
1427 in struct rs6000_framedata fdata:
1428 - frameless is TRUE, if function does not have a frame.
1429 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1430 - offset is the initial size of this stack frame --- the amount by
1431 which we decrement the sp to allocate the frame.
1432 - saved_gpr is the number of the first saved gpr.
1433 - saved_fpr is the number of the first saved fpr.
1434 - saved_vr is the number of the first saved vr.
1435 - saved_ev is the number of the first saved ev.
1436 - alloca_reg is the number of the register used for alloca() handling.
1438 - gpr_offset is the offset of the first saved gpr from the previous frame.
1439 - fpr_offset is the offset of the first saved fpr from the previous frame.
1440 - vr_offset is the offset of the first saved vr from the previous frame.
1441 - ev_offset is the offset of the first saved ev from the previous frame.
1442 - lr_offset is the offset of the saved lr
1443 - cr_offset is the offset of the saved cr
1444 - vrsave_offset is the offset of the saved vrsave register. */
1447 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1448 struct rs6000_framedata
*fdata
)
1450 CORE_ADDR orig_pc
= pc
;
1451 CORE_ADDR last_prologue_pc
= pc
;
1452 CORE_ADDR li_found_pc
= 0;
1456 long alloca_reg_offset
= 0;
1457 long vr_saved_offset
= 0;
1463 int vrsave_reg
= -1;
1466 int minimal_toc_loaded
= 0;
1467 int prev_insn_was_prologue_insn
= 1;
1468 int num_skip_non_prologue_insns
= 0;
1469 int r0_contains_arg
= 0;
1470 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1471 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1472 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1474 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1475 fdata
->saved_gpr
= -1;
1476 fdata
->saved_fpr
= -1;
1477 fdata
->saved_vr
= -1;
1478 fdata
->saved_ev
= -1;
1479 fdata
->alloca_reg
= -1;
1480 fdata
->frameless
= 1;
1481 fdata
->nosavedpc
= 1;
1482 fdata
->lr_register
= -1;
1484 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1490 /* Sometimes it isn't clear if an instruction is a prologue
1491 instruction or not. When we encounter one of these ambiguous
1492 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1493 Otherwise, we'll assume that it really is a prologue instruction. */
1494 if (prev_insn_was_prologue_insn
)
1495 last_prologue_pc
= pc
;
1497 /* Stop scanning if we've hit the limit. */
1501 prev_insn_was_prologue_insn
= 1;
1503 /* Fetch the instruction and convert it to an integer. */
1504 if (target_read_memory (pc
, buf
, 4))
1506 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1508 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1510 /* Since shared library / PIC code, which needs to get its
1511 address at runtime, can appear to save more than one link
1525 remember just the first one, but skip over additional
1528 lr_reg
= (op
& 0x03e00000) >> 21;
1530 r0_contains_arg
= 0;
1533 else if ((op
& 0xfc1fffff) == 0x7c000026)
1535 cr_reg
= (op
& 0x03e00000) >> 21;
1537 r0_contains_arg
= 0;
1541 else if ((op
& 0xfc1f0000) == 0xd8010000)
1542 { /* stfd Rx,NUM(r1) */
1543 reg
= GET_SRC_REG (op
);
1544 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1546 fdata
->saved_fpr
= reg
;
1547 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1552 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1553 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1554 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1555 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1558 reg
= GET_SRC_REG (op
);
1559 if ((op
& 0xfc1f0000) == 0xbc010000)
1560 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1562 fdata
->gpr_mask
|= 1U << reg
;
1563 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1565 fdata
->saved_gpr
= reg
;
1566 if ((op
& 0xfc1f0003) == 0xf8010000)
1568 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1573 else if ((op
& 0xffff0000) == 0x3c4c0000
1574 || (op
& 0xffff0000) == 0x3c400000
1575 || (op
& 0xffff0000) == 0x38420000)
1577 /* . 0: addis 2,12,.TOC.-0b@ha
1578 . addi 2,2,.TOC.-0b@l
1582 used by ELFv2 global entry points to set up r2. */
1585 else if (op
== 0x60000000)
1588 /* Allow nops in the prologue, but do not consider them to
1589 be part of the prologue unless followed by other prologue
1591 prev_insn_was_prologue_insn
= 0;
1595 else if ((op
& 0xffff0000) == 0x3c000000)
1596 { /* addis 0,0,NUM, used for >= 32k frames */
1597 fdata
->offset
= (op
& 0x0000ffff) << 16;
1598 fdata
->frameless
= 0;
1599 r0_contains_arg
= 0;
1603 else if ((op
& 0xffff0000) == 0x60000000)
1604 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1605 fdata
->offset
|= (op
& 0x0000ffff);
1606 fdata
->frameless
= 0;
1607 r0_contains_arg
= 0;
1611 else if (lr_reg
>= 0 &&
1612 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1614 (store_insn_p (op
, lr_reg
,
1615 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1618 if (store_insn_p (op
, lr_reg
, 1, true))
1619 fdata
->lr_offset
= offset
;
1620 else /* LR save through frame pointer. */
1621 fdata
->lr_offset
= alloca_reg_offset
;
1623 fdata
->nosavedpc
= 0;
1624 /* Invalidate lr_reg, but don't set it to -1.
1625 That would mean that it had never been set. */
1627 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1628 (op
& 0xfc000000) == 0x90000000) /* stw */
1630 /* Does not update r1, so add displacement to lr_offset. */
1631 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1636 else if (cr_reg
>= 0 &&
1637 (store_insn_p (op
, cr_reg
, 1, true)))
1639 fdata
->cr_offset
= offset
;
1640 /* Invalidate cr_reg, but don't set it to -1.
1641 That would mean that it had never been set. */
1643 if ((op
& 0xfc000003) == 0xf8000000 ||
1644 (op
& 0xfc000000) == 0x90000000)
1646 /* Does not update r1, so add displacement to cr_offset. */
1647 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1652 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1654 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1655 prediction bits. If the LR has already been saved, we can
1659 else if (op
== 0x48000005)
1666 else if (op
== 0x48000004)
1671 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1672 in V.4 -mminimal-toc */
1673 (op
& 0xffff0000) == 0x3bde0000)
1674 { /* addi 30,30,foo@l */
1678 else if ((op
& 0xfc000001) == 0x48000001)
1682 fdata
->frameless
= 0;
1684 /* If the return address has already been saved, we can skip
1685 calls to blrl (for PIC). */
1686 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1692 /* Don't skip over the subroutine call if it is not within
1693 the first three instructions of the prologue and either
1694 we have no line table information or the line info tells
1695 us that the subroutine call is not part of the line
1696 associated with the prologue. */
1697 if ((pc
- orig_pc
) > 8)
1699 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1700 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1702 if ((prologue_sal
.line
== 0)
1703 || (prologue_sal
.line
!= this_sal
.line
))
1707 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1709 /* At this point, make sure this is not a trampoline
1710 function (a function that simply calls another functions,
1711 and nothing else). If the next is not a nop, this branch
1712 was part of the function prologue. */
1714 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1715 break; /* Don't skip over
1721 /* update stack pointer */
1722 else if ((op
& 0xfc1f0000) == 0x94010000)
1723 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1724 fdata
->frameless
= 0;
1725 fdata
->offset
= SIGNED_SHORT (op
);
1726 offset
= fdata
->offset
;
1729 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1730 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1731 /* No way to figure out what r1 is going to be. */
1732 fdata
->frameless
= 0;
1733 offset
= fdata
->offset
;
1736 else if ((op
& 0xfc1f0003) == 0xf8010001)
1737 { /* stdu rX,NUM(r1) */
1738 fdata
->frameless
= 0;
1739 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1740 offset
= fdata
->offset
;
1743 else if ((op
& 0xffff0000) == 0x38210000)
1744 { /* addi r1,r1,SIMM */
1745 fdata
->frameless
= 0;
1746 fdata
->offset
+= SIGNED_SHORT (op
);
1747 offset
= fdata
->offset
;
1750 /* Load up minimal toc pointer. Do not treat an epilogue restore
1751 of r31 as a minimal TOC load. */
1752 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1753 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1755 && !minimal_toc_loaded
)
1757 minimal_toc_loaded
= 1;
1760 /* move parameters from argument registers to local variable
1763 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1764 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1765 (((op
>> 21) & 31) <= 10) &&
1766 ((long) ((op
>> 16) & 31)
1767 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1771 /* store parameters in stack */
1773 /* Move parameters from argument registers to temporary register. */
1774 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1778 /* Set up frame pointer */
1780 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1782 fdata
->frameless
= 0;
1784 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1785 alloca_reg_offset
= offset
;
1788 /* Another way to set up the frame pointer. */
1790 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1791 || op
== 0x7c3f0b78)
1793 fdata
->frameless
= 0;
1795 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1796 alloca_reg_offset
= offset
;
1799 /* Another way to set up the frame pointer. */
1801 else if ((op
& 0xfc1fffff) == 0x38010000)
1802 { /* addi rX, r1, 0x0 */
1803 fdata
->frameless
= 0;
1805 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1806 + ((op
& ~0x38010000) >> 21));
1807 alloca_reg_offset
= offset
;
1810 /* AltiVec related instructions. */
1811 /* Store the vrsave register (spr 256) in another register for
1812 later manipulation, or load a register into the vrsave
1813 register. 2 instructions are used: mfvrsave and
1814 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1815 and mtspr SPR256, Rn. */
1816 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1817 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1818 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1820 vrsave_reg
= GET_SRC_REG (op
);
1823 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1827 /* Store the register where vrsave was saved to onto the stack:
1828 rS is the register where vrsave was stored in a previous
1830 /* 100100 sssss 00001 dddddddd dddddddd */
1831 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1833 if (vrsave_reg
== GET_SRC_REG (op
))
1835 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1840 /* Compute the new value of vrsave, by modifying the register
1841 where vrsave was saved to. */
1842 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1843 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1847 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1848 in a pair of insns to save the vector registers on the
1850 /* 001110 00000 00000 iiii iiii iiii iiii */
1851 /* 001110 01110 00000 iiii iiii iiii iiii */
1852 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1853 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1855 if ((op
& 0xffff0000) == 0x38000000)
1856 r0_contains_arg
= 0;
1858 vr_saved_offset
= SIGNED_SHORT (op
);
1860 /* This insn by itself is not part of the prologue, unless
1861 if part of the pair of insns mentioned above. So do not
1862 record this insn as part of the prologue yet. */
1863 prev_insn_was_prologue_insn
= 0;
1865 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1866 /* 011111 sssss 11111 00000 00111001110 */
1867 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1869 if (pc
== (li_found_pc
+ 4))
1871 vr_reg
= GET_SRC_REG (op
);
1872 /* If this is the first vector reg to be saved, or if
1873 it has a lower number than others previously seen,
1874 reupdate the frame info. */
1875 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1877 fdata
->saved_vr
= vr_reg
;
1878 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1880 vr_saved_offset
= -1;
1885 /* End AltiVec related instructions. */
1887 /* Start BookE related instructions. */
1888 /* Store gen register S at (r31+uimm).
1889 Any register less than r13 is volatile, so we don't care. */
1890 /* 000100 sssss 11111 iiiii 01100100001 */
1891 else if (arch_info
->mach
== bfd_mach_ppc_e500
1892 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1894 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1897 ev_reg
= GET_SRC_REG (op
);
1898 imm
= (op
>> 11) & 0x1f;
1899 ev_offset
= imm
* 8;
1900 /* If this is the first vector reg to be saved, or if
1901 it has a lower number than others previously seen,
1902 reupdate the frame info. */
1903 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1905 fdata
->saved_ev
= ev_reg
;
1906 fdata
->ev_offset
= ev_offset
+ offset
;
1911 /* Store gen register rS at (r1+rB). */
1912 /* 000100 sssss 00001 bbbbb 01100100000 */
1913 else if (arch_info
->mach
== bfd_mach_ppc_e500
1914 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1916 if (pc
== (li_found_pc
+ 4))
1918 ev_reg
= GET_SRC_REG (op
);
1919 /* If this is the first vector reg to be saved, or if
1920 it has a lower number than others previously seen,
1921 reupdate the frame info. */
1922 /* We know the contents of rB from the previous instruction. */
1923 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1925 fdata
->saved_ev
= ev_reg
;
1926 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1928 vr_saved_offset
= -1;
1934 /* Store gen register r31 at (rA+uimm). */
1935 /* 000100 11111 aaaaa iiiii 01100100001 */
1936 else if (arch_info
->mach
== bfd_mach_ppc_e500
1937 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1939 /* Wwe know that the source register is 31 already, but
1940 it can't hurt to compute it. */
1941 ev_reg
= GET_SRC_REG (op
);
1942 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1943 /* If this is the first vector reg to be saved, or if
1944 it has a lower number than others previously seen,
1945 reupdate the frame info. */
1946 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1948 fdata
->saved_ev
= ev_reg
;
1949 fdata
->ev_offset
= ev_offset
+ offset
;
1954 /* Store gen register S at (r31+r0).
1955 Store param on stack when offset from SP bigger than 4 bytes. */
1956 /* 000100 sssss 11111 00000 01100100000 */
1957 else if (arch_info
->mach
== bfd_mach_ppc_e500
1958 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1960 if (pc
== (li_found_pc
+ 4))
1962 if ((op
& 0x03e00000) >= 0x01a00000)
1964 ev_reg
= GET_SRC_REG (op
);
1965 /* If this is the first vector reg to be saved, or if
1966 it has a lower number than others previously seen,
1967 reupdate the frame info. */
1968 /* We know the contents of r0 from the previous
1970 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1972 fdata
->saved_ev
= ev_reg
;
1973 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1977 vr_saved_offset
= -1;
1982 /* End BookE related instructions. */
1986 /* Not a recognized prologue instruction.
1987 Handle optimizer code motions into the prologue by continuing
1988 the search if we have no valid frame yet or if the return
1989 address is not yet saved in the frame. Also skip instructions
1990 if some of the GPRs expected to be saved are not yet saved. */
1991 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
1992 && fdata
->saved_gpr
!= -1)
1994 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
1996 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
2000 if (op
== 0x4e800020 /* blr */
2001 || op
== 0x4e800420) /* bctr */
2002 /* Do not scan past epilogue in frameless functions or
2005 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2006 /* Never skip branches. */
2009 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2010 /* Do not scan too many insns, scanning insns is expensive with
2014 /* Continue scanning. */
2015 prev_insn_was_prologue_insn
= 0;
2021 /* I have problems with skipping over __main() that I need to address
2022 * sometime. Previously, I used to use misc_function_vector which
2023 * didn't work as well as I wanted to be. -MGO */
2025 /* If the first thing after skipping a prolog is a branch to a function,
2026 this might be a call to an initializer in main(), introduced by gcc2.
2027 We'd like to skip over it as well. Fortunately, xlc does some extra
2028 work before calling a function right after a prologue, thus we can
2029 single out such gcc2 behaviour. */
2032 if ((op
& 0xfc000001) == 0x48000001)
2033 { /* bl foo, an initializer function? */
2034 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2036 if (op
== 0x4def7b82)
2037 { /* cror 0xf, 0xf, 0xf (nop) */
2039 /* Check and see if we are in main. If so, skip over this
2040 initializer function as well. */
2042 tmp
= find_pc_misc_function (pc
);
2044 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2050 if (pc
== lim_pc
&& lr_reg
>= 0)
2051 fdata
->lr_register
= lr_reg
;
2053 fdata
->offset
= -fdata
->offset
;
2054 return last_prologue_pc
;
2058 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2060 struct rs6000_framedata frame
;
2061 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2063 /* See if we can determine the end of the prologue via the symbol table.
2064 If so, then return either PC, or the PC after the prologue, whichever
2066 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2068 CORE_ADDR post_prologue_pc
2069 = skip_prologue_using_sal (gdbarch
, func_addr
);
2070 if (post_prologue_pc
!= 0)
2071 return std::max (pc
, post_prologue_pc
);
2074 /* Can't determine prologue from the symbol table, need to examine
2077 /* Find an upper limit on the function prologue using the debug
2078 information. If the debug information could not be used to provide
2079 that bound, then use an arbitrary large number as the upper bound. */
2080 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2082 limit_pc
= pc
+ 100; /* Magic. */
2084 /* Do not allow limit_pc to be past the function end, if we know
2085 where that end is... */
2086 if (func_end_addr
&& limit_pc
> func_end_addr
)
2087 limit_pc
= func_end_addr
;
2089 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2093 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2094 in the prologue of main().
2096 The function below examines the code pointed at by PC and checks to
2097 see if it corresponds to a call to __eabi. If so, it returns the
2098 address of the instruction following that call. Otherwise, it simply
2102 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2104 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2108 if (target_read_memory (pc
, buf
, 4))
2110 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2112 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2114 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2115 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2116 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2118 /* We check for ___eabi (three leading underscores) in addition
2119 to __eabi in case the GCC option "-fleading-underscore" was
2120 used to compile the program. */
2121 if (s
.minsym
!= NULL
2122 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2123 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2124 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2130 /* All the ABI's require 16 byte alignment. */
2132 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2134 return (addr
& -16);
2137 /* Return whether handle_inferior_event() should proceed through code
2138 starting at PC in function NAME when stepping.
2140 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2141 handle memory references that are too distant to fit in instructions
2142 generated by the compiler. For example, if 'foo' in the following
2147 is greater than 32767, the linker might replace the lwz with a branch to
2148 somewhere in @FIX1 that does the load in 2 instructions and then branches
2149 back to where execution should continue.
2151 GDB should silently step over @FIX code, just like AIX dbx does.
2152 Unfortunately, the linker uses the "b" instruction for the
2153 branches, meaning that the link register doesn't get set.
2154 Therefore, GDB's usual step_over_function () mechanism won't work.
2156 Instead, use the gdbarch_skip_trampoline_code and
2157 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2161 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2162 CORE_ADDR pc
, const char *name
)
2164 return name
&& startswith (name
, "@FIX");
2167 /* Skip code that the user doesn't want to see when stepping:
2169 1. Indirect function calls use a piece of trampoline code to do context
2170 switching, i.e. to set the new TOC table. Skip such code if we are on
2171 its first instruction (as when we have single-stepped to here).
2173 2. Skip shared library trampoline code (which is different from
2174 indirect function call trampolines).
2176 3. Skip bigtoc fixup code.
2178 Result is desired PC to step until, or NULL if we are not in
2179 code that should be skipped. */
2182 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2184 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2186 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2187 unsigned int ii
, op
;
2189 CORE_ADDR solib_target_pc
;
2190 struct bound_minimal_symbol msymbol
;
2192 static unsigned trampoline_code
[] =
2194 0x800b0000, /* l r0,0x0(r11) */
2195 0x90410014, /* st r2,0x14(r1) */
2196 0x7c0903a6, /* mtctr r0 */
2197 0x804b0004, /* l r2,0x4(r11) */
2198 0x816b0008, /* l r11,0x8(r11) */
2199 0x4e800420, /* bctr */
2200 0x4e800020, /* br */
2204 /* Check for bigtoc fixup code. */
2205 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2207 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2208 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2210 /* Double-check that the third instruction from PC is relative "b". */
2211 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2212 if ((op
& 0xfc000003) == 0x48000000)
2214 /* Extract bits 6-29 as a signed 24-bit relative word address and
2215 add it to the containing PC. */
2216 rel
= ((int)(op
<< 6) >> 6);
2217 return pc
+ 8 + rel
;
2221 /* If pc is in a shared library trampoline, return its target. */
2222 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2223 if (solib_target_pc
)
2224 return solib_target_pc
;
2226 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2228 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2229 if (op
!= trampoline_code
[ii
])
2232 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2234 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2238 /* ISA-specific vector types. */
2240 static struct type
*
2241 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2243 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2245 if (!tdep
->ppc_builtin_type_vec64
)
2247 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2249 /* The type we're building is this: */
2251 union __gdb_builtin_type_vec64
2255 int32_t v2_int32
[2];
2256 int16_t v4_int16
[4];
2263 t
= arch_composite_type (gdbarch
,
2264 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2265 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2266 append_composite_type_field (t
, "v2_float",
2267 init_vector_type (bt
->builtin_float
, 2));
2268 append_composite_type_field (t
, "v2_int32",
2269 init_vector_type (bt
->builtin_int32
, 2));
2270 append_composite_type_field (t
, "v4_int16",
2271 init_vector_type (bt
->builtin_int16
, 4));
2272 append_composite_type_field (t
, "v8_int8",
2273 init_vector_type (bt
->builtin_int8
, 8));
2275 TYPE_VECTOR (t
) = 1;
2276 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2277 tdep
->ppc_builtin_type_vec64
= t
;
2280 return tdep
->ppc_builtin_type_vec64
;
2283 /* Vector 128 type. */
2285 static struct type
*
2286 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2288 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2290 if (!tdep
->ppc_builtin_type_vec128
)
2292 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2294 /* The type we're building is this
2296 type = union __ppc_builtin_type_vec128 {
2298 double v2_double[2];
2300 int32_t v4_int32[4];
2301 int16_t v8_int16[8];
2302 int8_t v16_int8[16];
2308 t
= arch_composite_type (gdbarch
,
2309 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2310 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2311 append_composite_type_field (t
, "v2_double",
2312 init_vector_type (bt
->builtin_double
, 2));
2313 append_composite_type_field (t
, "v4_float",
2314 init_vector_type (bt
->builtin_float
, 4));
2315 append_composite_type_field (t
, "v4_int32",
2316 init_vector_type (bt
->builtin_int32
, 4));
2317 append_composite_type_field (t
, "v8_int16",
2318 init_vector_type (bt
->builtin_int16
, 8));
2319 append_composite_type_field (t
, "v16_int8",
2320 init_vector_type (bt
->builtin_int8
, 16));
2322 TYPE_VECTOR (t
) = 1;
2323 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2324 tdep
->ppc_builtin_type_vec128
= t
;
2327 return tdep
->ppc_builtin_type_vec128
;
2330 /* Return the name of register number REGNO, or the empty string if it
2331 is an anonymous register. */
2334 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2336 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2338 /* The upper half "registers" have names in the XML description,
2339 but we present only the low GPRs and the full 64-bit registers
2341 if (tdep
->ppc_ev0_upper_regnum
>= 0
2342 && tdep
->ppc_ev0_upper_regnum
<= regno
2343 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2346 /* Hide the upper halves of the vs0~vs31 registers. */
2347 if (tdep
->ppc_vsr0_regnum
>= 0
2348 && tdep
->ppc_vsr0_upper_regnum
<= regno
2349 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2352 /* Hide the upper halves of the cvs0~cvs31 registers. */
2353 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2354 && regno
< PPC_CVSR0_UPPER_REGNUM
+ ppc_num_gprs
)
2357 /* Check if the SPE pseudo registers are available. */
2358 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2360 static const char *const spe_regnames
[] = {
2361 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2362 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2363 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2364 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2366 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2369 /* Check if the decimal128 pseudo-registers are available. */
2370 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2372 static const char *const dfp128_regnames
[] = {
2373 "dl0", "dl1", "dl2", "dl3",
2374 "dl4", "dl5", "dl6", "dl7",
2375 "dl8", "dl9", "dl10", "dl11",
2376 "dl12", "dl13", "dl14", "dl15"
2378 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2381 /* Check if this is a vX alias for a raw vrX vector register. */
2382 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2384 static const char *const vector_alias_regnames
[] = {
2385 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2386 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2387 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2388 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2390 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2393 /* Check if this is a VSX pseudo-register. */
2394 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2396 static const char *const vsx_regnames
[] = {
2397 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2398 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2399 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2400 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2401 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2402 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2403 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2404 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2405 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2407 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2410 /* Check if the this is a Extended FP pseudo-register. */
2411 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2413 static const char *const efpr_regnames
[] = {
2414 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2415 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2416 "f46", "f47", "f48", "f49", "f50", "f51",
2417 "f52", "f53", "f54", "f55", "f56", "f57",
2418 "f58", "f59", "f60", "f61", "f62", "f63"
2420 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2423 /* Check if this is a Checkpointed DFP pseudo-register. */
2424 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2426 static const char *const cdfp128_regnames
[] = {
2427 "cdl0", "cdl1", "cdl2", "cdl3",
2428 "cdl4", "cdl5", "cdl6", "cdl7",
2429 "cdl8", "cdl9", "cdl10", "cdl11",
2430 "cdl12", "cdl13", "cdl14", "cdl15"
2432 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2435 /* Check if this is a Checkpointed VSX pseudo-register. */
2436 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2438 static const char *const cvsx_regnames
[] = {
2439 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2440 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2441 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2442 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2443 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2444 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2445 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2446 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2447 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2449 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2452 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2453 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2455 static const char *const cefpr_regnames
[] = {
2456 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2457 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2458 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2459 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2460 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2462 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2465 return tdesc_register_name (gdbarch
, regno
);
2468 /* Return the GDB type object for the "standard" data type of data in
2471 static struct type
*
2472 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2474 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2476 /* These are the e500 pseudo-registers. */
2477 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2478 return rs6000_builtin_type_vec64 (gdbarch
);
2479 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2480 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2481 /* PPC decimal128 pseudo-registers. */
2482 return builtin_type (gdbarch
)->builtin_declong
;
2483 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2484 return gdbarch_register_type (gdbarch
,
2485 tdep
->ppc_vr0_regnum
2487 - tdep
->ppc_v0_alias_regnum
));
2488 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2489 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2490 /* POWER7 VSX pseudo-registers. */
2491 return rs6000_builtin_type_vec128 (gdbarch
);
2492 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2493 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2494 /* POWER7 Extended FP pseudo-registers. */
2495 return builtin_type (gdbarch
)->builtin_double
;
2497 internal_error (__FILE__
, __LINE__
,
2498 _("rs6000_pseudo_register_type: "
2499 "called on unexpected register '%s' (%d)"),
2500 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2503 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2504 the vX aliases for the vector registers by always returning false
2505 to avoid duplicated information in "info register vector/all",
2506 since the raw vrX registers will already show in these cases. For
2507 other pseudo-registers we use the default membership function. */
2510 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2511 struct reggroup
*group
)
2513 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2515 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2518 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2521 /* The register format for RS/6000 floating point registers is always
2522 double, we need a conversion if the memory format is float. */
2525 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2528 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2530 return (tdep
->ppc_fp0_regnum
>= 0
2531 && regnum
>= tdep
->ppc_fp0_regnum
2532 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2533 && TYPE_CODE (type
) == TYPE_CODE_FLT
2534 && TYPE_LENGTH (type
)
2535 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2539 rs6000_register_to_value (struct frame_info
*frame
,
2543 int *optimizedp
, int *unavailablep
)
2545 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2546 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2548 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2550 if (!get_frame_register_bytes (frame
, regnum
, 0,
2551 register_size (gdbarch
, regnum
),
2552 from
, optimizedp
, unavailablep
))
2555 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2557 *optimizedp
= *unavailablep
= 0;
2562 rs6000_value_to_register (struct frame_info
*frame
,
2565 const gdb_byte
*from
)
2567 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2568 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2570 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2572 target_float_convert (from
, type
,
2573 to
, builtin_type (gdbarch
)->builtin_double
);
2574 put_frame_register (frame
, regnum
, to
);
2577 /* The type of a function that moves the value of REG between CACHE
2578 or BUF --- in either direction. */
2579 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2582 /* Move SPE vector register values between a 64-bit buffer and the two
2583 32-bit raw register halves in a regcache. This function handles
2584 both splitting a 64-bit value into two 32-bit halves, and joining
2585 two halves into a whole 64-bit value, depending on the function
2586 passed as the MOVE argument.
2588 EV_REG must be the number of an SPE evN vector register --- a
2589 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2592 Call MOVE once for each 32-bit half of that register, passing
2593 REGCACHE, the number of the raw register corresponding to that
2594 half, and the address of the appropriate half of BUFFER.
2596 For example, passing 'regcache_raw_read' as the MOVE function will
2597 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2598 'regcache_raw_supply' will supply the contents of BUFFER to the
2599 appropriate pair of raw registers in REGCACHE.
2601 You may need to cast away some 'const' qualifiers when passing
2602 MOVE, since this function can't tell at compile-time which of
2603 REGCACHE or BUFFER is acting as the source of the data. If C had
2604 co-variant type qualifiers, ... */
2606 static enum register_status
2607 e500_move_ev_register (move_ev_register_func move
,
2608 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2610 struct gdbarch
*arch
= regcache
->arch ();
2611 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2613 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2614 enum register_status status
;
2616 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2618 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2620 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2622 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2624 if (status
== REG_VALID
)
2625 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2630 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2631 if (status
== REG_VALID
)
2632 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2639 static enum register_status
2640 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2642 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2647 static enum register_status
2648 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2649 int ev_reg
, gdb_byte
*buffer
)
2651 struct gdbarch
*arch
= regcache
->arch ();
2652 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2654 enum register_status status
;
2656 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2658 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2660 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2662 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2664 if (status
== REG_VALID
)
2665 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2670 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2671 if (status
== REG_VALID
)
2672 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2681 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2682 int reg_nr
, const gdb_byte
*buffer
)
2684 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2685 reg_nr
, (void *) buffer
);
2688 /* Read method for DFP pseudo-registers. */
2689 static enum register_status
2690 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2691 int reg_nr
, gdb_byte
*buffer
)
2693 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2695 enum register_status status
;
2697 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2699 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2700 fp0
= PPC_F0_REGNUM
;
2704 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2706 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2707 fp0
= PPC_CF0_REGNUM
;
2710 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2712 /* Read two FP registers to form a whole dl register. */
2713 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2714 if (status
== REG_VALID
)
2715 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2720 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2721 if (status
== REG_VALID
)
2722 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2728 /* Write method for DFP pseudo-registers. */
2730 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2731 int reg_nr
, const gdb_byte
*buffer
)
2733 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2736 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2738 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2739 fp0
= PPC_F0_REGNUM
;
2743 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2745 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2746 fp0
= PPC_CF0_REGNUM
;
2749 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2751 /* Write each half of the dl register into a separate
2753 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2754 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2758 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2759 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2763 /* Read method for the vX aliases for the raw vrX registers. */
2765 static enum register_status
2766 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2767 readable_regcache
*regcache
, int reg_nr
,
2770 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2771 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2773 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2774 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2778 /* Write method for the vX aliases for the raw vrX registers. */
2781 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2782 struct regcache
*regcache
,
2783 int reg_nr
, const gdb_byte
*buffer
)
2785 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2786 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2788 regcache
->raw_write (tdep
->ppc_vr0_regnum
2789 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
2792 /* Read method for POWER7 VSX pseudo-registers. */
2793 static enum register_status
2794 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2795 int reg_nr
, gdb_byte
*buffer
)
2797 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2798 int reg_index
, vr0
, fp0
, vsr0_upper
;
2799 enum register_status status
;
2801 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2803 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2804 vr0
= PPC_VR0_REGNUM
;
2805 fp0
= PPC_F0_REGNUM
;
2806 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2810 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2812 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2813 vr0
= PPC_CVR0_REGNUM
;
2814 fp0
= PPC_CF0_REGNUM
;
2815 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2818 /* Read the portion that overlaps the VMX registers. */
2820 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
2822 /* Read the portion that overlaps the FPR registers. */
2823 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2825 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
2826 if (status
== REG_VALID
)
2827 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
2832 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
2833 if (status
== REG_VALID
)
2834 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
2840 /* Write method for POWER7 VSX pseudo-registers. */
2842 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2843 int reg_nr
, const gdb_byte
*buffer
)
2845 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2846 int reg_index
, vr0
, fp0
, vsr0_upper
;
2848 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2850 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2851 vr0
= PPC_VR0_REGNUM
;
2852 fp0
= PPC_F0_REGNUM
;
2853 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2857 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2859 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2860 vr0
= PPC_CVR0_REGNUM
;
2861 fp0
= PPC_CF0_REGNUM
;
2862 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2865 /* Write the portion that overlaps the VMX registers. */
2867 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
2869 /* Write the portion that overlaps the FPR registers. */
2870 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2872 regcache
->raw_write (fp0
+ reg_index
, buffer
);
2873 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
2877 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
2878 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
2882 /* Read method for POWER7 Extended FP pseudo-registers. */
2883 static enum register_status
2884 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2885 int reg_nr
, gdb_byte
*buffer
)
2887 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2890 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2892 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2893 vr0
= PPC_VR0_REGNUM
;
2897 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2899 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2900 vr0
= PPC_CVR0_REGNUM
;
2903 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2905 /* Read the portion that overlaps the VMX register. */
2906 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
2907 register_size (gdbarch
, reg_nr
),
2911 /* Write method for POWER7 Extended FP pseudo-registers. */
2913 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2914 int reg_nr
, const gdb_byte
*buffer
)
2916 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2918 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2920 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2922 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2923 vr0
= PPC_VR0_REGNUM
;
2927 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2929 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2930 vr0
= PPC_CVR0_REGNUM
;
2932 /* The call to raw_write_part fails silently if the initial read
2933 of the read-update-write sequence returns an invalid status,
2934 so we check this manually and throw an error if needed. */
2935 regcache
->raw_update (vr0
+ reg_index
);
2936 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
2937 error (_("Cannot write to the checkpointed EFP register, "
2938 "the corresponding vector register is unavailable."));
2941 /* Write the portion that overlaps the VMX register. */
2942 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
2943 register_size (gdbarch
, reg_nr
), buffer
);
2946 static enum register_status
2947 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2948 readable_regcache
*regcache
,
2949 int reg_nr
, gdb_byte
*buffer
)
2951 struct gdbarch
*regcache_arch
= regcache
->arch ();
2952 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2954 gdb_assert (regcache_arch
== gdbarch
);
2956 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2957 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2958 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
2959 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
2960 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2961 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
2962 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
2964 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
2965 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
2966 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2967 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
2968 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
2969 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2971 internal_error (__FILE__
, __LINE__
,
2972 _("rs6000_pseudo_register_read: "
2973 "called on unexpected register '%s' (%d)"),
2974 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2978 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2979 struct regcache
*regcache
,
2980 int reg_nr
, const gdb_byte
*buffer
)
2982 struct gdbarch
*regcache_arch
= regcache
->arch ();
2983 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2985 gdb_assert (regcache_arch
== gdbarch
);
2987 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2988 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2989 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
2990 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
2991 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2992 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
2993 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2994 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
2995 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
2996 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2997 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
2998 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
2999 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3001 internal_error (__FILE__
, __LINE__
,
3002 _("rs6000_pseudo_register_write: "
3003 "called on unexpected register '%s' (%d)"),
3004 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3007 /* Set the register mask in AX with the registers that form the DFP or
3008 checkpointed DFP pseudo-register REG_NR. */
3011 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3012 struct agent_expr
*ax
, int reg_nr
)
3014 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3017 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3019 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3020 fp0
= PPC_F0_REGNUM
;
3024 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3026 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3027 fp0
= PPC_CF0_REGNUM
;
3030 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3031 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3034 /* Set the register mask in AX with the raw vector register that
3035 corresponds to its REG_NR alias. */
3038 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3039 struct agent_expr
*ax
, int reg_nr
)
3041 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3042 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3044 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3045 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3048 /* Set the register mask in AX with the registers that form the VSX or
3049 checkpointed VSX pseudo-register REG_NR. */
3052 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3053 struct agent_expr
*ax
, int reg_nr
)
3055 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3056 int reg_index
, vr0
, fp0
, vsr0_upper
;
3058 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3060 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3061 vr0
= PPC_VR0_REGNUM
;
3062 fp0
= PPC_F0_REGNUM
;
3063 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3067 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3069 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3070 vr0
= PPC_CVR0_REGNUM
;
3071 fp0
= PPC_CF0_REGNUM
;
3072 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3077 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3081 ax_reg_mask (ax
, fp0
+ reg_index
);
3082 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3086 /* Set the register mask in AX with the register that corresponds to
3087 the EFP or checkpointed EFP pseudo-register REG_NR. */
3090 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3091 struct agent_expr
*ax
, int reg_nr
)
3093 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3096 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3098 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3099 vr0
= PPC_VR0_REGNUM
;
3103 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3105 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3106 vr0
= PPC_CVR0_REGNUM
;
3109 ax_reg_mask (ax
, vr0
+ reg_index
);
3113 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3114 struct agent_expr
*ax
, int reg_nr
)
3116 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3117 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3119 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3120 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3121 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3123 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3124 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3126 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3128 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3130 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3132 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3133 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3135 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3137 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3138 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3140 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3143 internal_error (__FILE__
, __LINE__
,
3144 _("rs6000_pseudo_register_collect: "
3145 "called on unexpected register '%s' (%d)"),
3146 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3152 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3153 struct agent_expr
*ax
, struct axs_value
*value
,
3156 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3157 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3158 value
->kind
= axs_lvalue_register
;
3159 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3163 /* Convert a DBX STABS register number to a GDB register number. */
3165 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3169 if (0 <= num
&& num
<= 31)
3170 return tdep
->ppc_gp0_regnum
+ num
;
3171 else if (32 <= num
&& num
<= 63)
3172 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3173 specifies registers the architecture doesn't have? Our
3174 callers don't check the value we return. */
3175 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3176 else if (77 <= num
&& num
<= 108)
3177 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3178 else if (1200 <= num
&& num
< 1200 + 32)
3179 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3184 return tdep
->ppc_mq_regnum
;
3186 return tdep
->ppc_lr_regnum
;
3188 return tdep
->ppc_ctr_regnum
;
3190 return tdep
->ppc_xer_regnum
;
3192 return tdep
->ppc_vrsave_regnum
;
3194 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3196 return tdep
->ppc_acc_regnum
;
3198 return tdep
->ppc_spefscr_regnum
;
3205 /* Convert a Dwarf 2 register number to a GDB register number. */
3207 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3211 if (0 <= num
&& num
<= 31)
3212 return tdep
->ppc_gp0_regnum
+ num
;
3213 else if (32 <= num
&& num
<= 63)
3214 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3215 specifies registers the architecture doesn't have? Our
3216 callers don't check the value we return. */
3217 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3218 else if (1124 <= num
&& num
< 1124 + 32)
3219 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3220 else if (1200 <= num
&& num
< 1200 + 32)
3221 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3226 return tdep
->ppc_cr_regnum
;
3228 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3230 return tdep
->ppc_acc_regnum
;
3232 return tdep
->ppc_mq_regnum
;
3234 return tdep
->ppc_xer_regnum
;
3236 return tdep
->ppc_lr_regnum
;
3238 return tdep
->ppc_ctr_regnum
;
3240 return tdep
->ppc_vrsave_regnum
;
3242 return tdep
->ppc_spefscr_regnum
;
3248 /* Translate a .eh_frame register to DWARF register, or adjust a
3249 .debug_frame register. */
3252 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3254 /* GCC releases before 3.4 use GCC internal register numbering in
3255 .debug_frame (and .debug_info, et cetera). The numbering is
3256 different from the standard SysV numbering for everything except
3257 for GPRs and FPRs. We can not detect this problem in most cases
3258 - to get accurate debug info for variables living in lr, ctr, v0,
3259 et cetera, use a newer version of GCC. But we must detect
3260 one important case - lr is in column 65 in .debug_frame output,
3263 GCC 3.4, and the "hammer" branch, have a related problem. They
3264 record lr register saves in .debug_frame as 108, but still record
3265 the return column as 65. We fix that up too.
3267 We can do this because 65 is assigned to fpsr, and GCC never
3268 generates debug info referring to it. To add support for
3269 handwritten debug info that restores fpsr, we would need to add a
3270 producer version check to this. */
3279 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3280 internal register numbering; translate that to the standard DWARF2
3281 register numbering. */
3282 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3284 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3285 return num
- 68 + 86;
3286 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3287 return num
- 77 + 1124;
3299 case 109: /* vrsave */
3301 case 110: /* vscr */
3303 case 111: /* spe_acc */
3305 case 112: /* spefscr */
3313 /* Handling the various POWER/PowerPC variants. */
3315 /* Information about a particular processor variant. */
3319 /* Name of this variant. */
3322 /* English description of the variant. */
3323 const char *description
;
3325 /* bfd_arch_info.arch corresponding to variant. */
3326 enum bfd_architecture arch
;
3328 /* bfd_arch_info.mach corresponding to variant. */
3331 /* Target description for this variant. */
3332 struct target_desc
**tdesc
;
3335 static struct variant variants
[] =
3337 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3338 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3339 {"power", "POWER user-level", bfd_arch_rs6000
,
3340 bfd_mach_rs6k
, &tdesc_rs6000
},
3341 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3342 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3343 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3344 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3345 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3346 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3347 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3348 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3349 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3350 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3351 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3352 604, &tdesc_powerpc_604
},
3353 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3354 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3355 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3356 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3357 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3358 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3359 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3360 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3361 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3362 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3363 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3364 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3367 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3368 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3369 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3370 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3371 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3372 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3373 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3374 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3375 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3376 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3377 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3378 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3380 /* FIXME: I haven't checked the register sets of the following. */
3381 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3382 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3383 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3384 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3385 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3386 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3388 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3391 /* Return the variant corresponding to architecture ARCH and machine number
3392 MACH. If no such variant exists, return null. */
3394 static const struct variant
*
3395 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3397 const struct variant
*v
;
3399 for (v
= variants
; v
->name
; v
++)
3400 if (arch
== v
->arch
&& mach
== v
->mach
)
3408 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3410 return frame_unwind_register_unsigned (next_frame
,
3411 gdbarch_pc_regnum (gdbarch
));
3414 static struct frame_id
3415 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3417 return frame_id_build (get_frame_register_unsigned
3418 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3419 get_frame_pc (this_frame
));
3422 struct rs6000_frame_cache
3425 CORE_ADDR initial_sp
;
3426 struct trad_frame_saved_reg
*saved_regs
;
3428 /* Set BASE_P to true if this frame cache is properly initialized.
3429 Otherwise set to false because some registers or memory cannot
3432 /* Cache PC for building unavailable frame. */
3436 static struct rs6000_frame_cache
*
3437 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3439 struct rs6000_frame_cache
*cache
;
3440 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3441 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3442 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3443 struct rs6000_framedata fdata
;
3444 int wordsize
= tdep
->wordsize
;
3445 CORE_ADDR func
= 0, pc
= 0;
3447 if ((*this_cache
) != NULL
)
3448 return (struct rs6000_frame_cache
*) (*this_cache
);
3449 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3450 (*this_cache
) = cache
;
3452 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3456 func
= get_frame_func (this_frame
);
3458 pc
= get_frame_pc (this_frame
);
3459 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3461 /* Figure out the parent's stack pointer. */
3463 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3464 address of the current frame. Things might be easier if the
3465 ->frame pointed to the outer-most address of the frame. In
3466 the mean time, the address of the prev frame is used as the
3467 base address of this frame. */
3468 cache
->base
= get_frame_register_unsigned
3469 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3471 catch (const gdb_exception_error
&ex
)
3473 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3475 return (struct rs6000_frame_cache
*) (*this_cache
);
3478 /* If the function appears to be frameless, check a couple of likely
3479 indicators that we have simply failed to find the frame setup.
3480 Two common cases of this are missing symbols (i.e.
3481 get_frame_func returns the wrong address or 0), and assembly
3482 stubs which have a fast exit path but set up a frame on the slow
3485 If the LR appears to return to this function, then presume that
3486 we have an ABI compliant frame that we failed to find. */
3487 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3492 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3493 if (func
== 0 && saved_lr
== pc
)
3497 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3498 if (func
== saved_func
)
3504 fdata
.frameless
= 0;
3505 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3509 if (!fdata
.frameless
)
3511 /* Frameless really means stackless. */
3514 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3515 byte_order
, &backchain
))
3516 cache
->base
= (CORE_ADDR
) backchain
;
3519 trad_frame_set_value (cache
->saved_regs
,
3520 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3522 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3523 All fpr's from saved_fpr to fp31 are saved. */
3525 if (fdata
.saved_fpr
>= 0)
3528 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3530 /* If skip_prologue says floating-point registers were saved,
3531 but the current architecture has no floating-point registers,
3532 then that's strange. But we have no indices to even record
3533 the addresses under, so we just ignore it. */
3534 if (ppc_floating_point_unit_p (gdbarch
))
3535 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3537 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3542 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3543 All gpr's from saved_gpr to gpr31 are saved (except during the
3546 if (fdata
.saved_gpr
>= 0)
3549 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3550 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3552 if (fdata
.gpr_mask
& (1U << i
))
3553 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3554 gpr_addr
+= wordsize
;
3558 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3559 All vr's from saved_vr to vr31 are saved. */
3560 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3562 if (fdata
.saved_vr
>= 0)
3565 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3566 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3568 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3569 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3574 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3575 All vr's from saved_ev to ev31 are saved. ????? */
3576 if (tdep
->ppc_ev0_regnum
!= -1)
3578 if (fdata
.saved_ev
>= 0)
3581 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3582 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3584 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3586 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3587 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3588 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3593 /* If != 0, fdata.cr_offset is the offset from the frame that
3595 if (fdata
.cr_offset
!= 0)
3596 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3597 = cache
->base
+ fdata
.cr_offset
;
3599 /* If != 0, fdata.lr_offset is the offset from the frame that
3601 if (fdata
.lr_offset
!= 0)
3602 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3603 = cache
->base
+ fdata
.lr_offset
;
3604 else if (fdata
.lr_register
!= -1)
3605 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3606 /* The PC is found in the link register. */
3607 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3608 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3610 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3611 holds the VRSAVE. */
3612 if (fdata
.vrsave_offset
!= 0)
3613 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3614 = cache
->base
+ fdata
.vrsave_offset
;
3616 if (fdata
.alloca_reg
< 0)
3617 /* If no alloca register used, then fi->frame is the value of the
3618 %sp for this frame, and it is good enough. */
3620 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3623 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3630 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3631 struct frame_id
*this_id
)
3633 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3638 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3642 /* This marks the outermost frame. */
3643 if (info
->base
== 0)
3646 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3649 static struct value
*
3650 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3651 void **this_cache
, int regnum
)
3653 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3655 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3658 static const struct frame_unwind rs6000_frame_unwind
=
3661 default_frame_unwind_stop_reason
,
3662 rs6000_frame_this_id
,
3663 rs6000_frame_prev_register
,
3665 default_frame_sniffer
3668 /* Allocate and initialize a frame cache for an epilogue frame.
3669 SP is restored and prev-PC is stored in LR. */
3671 static struct rs6000_frame_cache
*
3672 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3674 struct rs6000_frame_cache
*cache
;
3675 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3676 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3679 return (struct rs6000_frame_cache
*) *this_cache
;
3681 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3682 (*this_cache
) = cache
;
3683 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3687 /* At this point the stack looks as if we just entered the
3688 function, and the return address is stored in LR. */
3691 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3692 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3695 cache
->initial_sp
= sp
;
3697 trad_frame_set_value (cache
->saved_regs
,
3698 gdbarch_pc_regnum (gdbarch
), lr
);
3700 catch (const gdb_exception_error
&ex
)
3702 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3709 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3710 Return the frame ID of an epilogue frame. */
3713 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3714 void **this_cache
, struct frame_id
*this_id
)
3717 struct rs6000_frame_cache
*info
=
3718 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3720 pc
= get_frame_func (this_frame
);
3721 if (info
->base
== 0)
3722 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3724 (*this_id
) = frame_id_build (info
->base
, pc
);
3727 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3728 Return the register value of REGNUM in previous frame. */
3730 static struct value
*
3731 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3732 void **this_cache
, int regnum
)
3734 struct rs6000_frame_cache
*info
=
3735 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3736 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3739 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3740 Check whether this an epilogue frame. */
3743 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3744 struct frame_info
*this_frame
,
3745 void **this_prologue_cache
)
3747 if (frame_relative_level (this_frame
) == 0)
3748 return rs6000_in_function_epilogue_frame_p (this_frame
,
3749 get_frame_arch (this_frame
),
3750 get_frame_pc (this_frame
));
3755 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3756 a function without debug information. */
3758 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3761 default_frame_unwind_stop_reason
,
3762 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3764 rs6000_epilogue_frame_sniffer
3769 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3771 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3773 return info
->initial_sp
;
3776 static const struct frame_base rs6000_frame_base
= {
3777 &rs6000_frame_unwind
,
3778 rs6000_frame_base_address
,
3779 rs6000_frame_base_address
,
3780 rs6000_frame_base_address
3783 static const struct frame_base
*
3784 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3786 return &rs6000_frame_base
;
3789 /* DWARF-2 frame support. Used to handle the detection of
3790 clobbered registers during function calls. */
3793 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3794 struct dwarf2_frame_state_reg
*reg
,
3795 struct frame_info
*this_frame
)
3797 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3799 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3800 non-volatile registers. We will use the same code for both. */
3802 /* Call-saved GP registers. */
3803 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3804 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3805 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3806 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3808 /* Call-clobbered GP registers. */
3809 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3810 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3811 || (regnum
== tdep
->ppc_gp0_regnum
))
3812 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3814 /* Deal with FP registers, if supported. */
3815 if (tdep
->ppc_fp0_regnum
>= 0)
3817 /* Call-saved FP registers. */
3818 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3819 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3820 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3822 /* Call-clobbered FP registers. */
3823 if ((regnum
>= tdep
->ppc_fp0_regnum
3824 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3825 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3828 /* Deal with ALTIVEC registers, if supported. */
3829 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3831 /* Call-saved Altivec registers. */
3832 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3833 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3834 || regnum
== tdep
->ppc_vrsave_regnum
)
3835 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3837 /* Call-clobbered Altivec registers. */
3838 if ((regnum
>= tdep
->ppc_vr0_regnum
3839 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3840 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3843 /* Handle PC register and Stack Pointer correctly. */
3844 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3845 reg
->how
= DWARF2_FRAME_REG_RA
;
3846 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3847 reg
->how
= DWARF2_FRAME_REG_CFA
;
3851 /* Return true if a .gnu_attributes section exists in BFD and it
3852 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3853 section exists in BFD and it indicates that SPE extensions are in
3854 use. Check the .gnu.attributes section first, as the binary might be
3855 compiled for SPE, but not actually using SPE instructions. */
3858 bfd_uses_spe_extensions (bfd
*abfd
)
3861 gdb_byte
*contents
= NULL
;
3870 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3871 could be using the SPE vector abi without actually using any spe
3872 bits whatsoever. But it's close enough for now. */
3873 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3874 Tag_GNU_Power_ABI_Vector
);
3875 if (vector_abi
== 3)
3879 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3883 size
= bfd_get_section_size (sect
);
3884 contents
= (gdb_byte
*) xmalloc (size
);
3885 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3891 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3897 char name[name_len rounded up to 4-byte alignment];
3898 char data[data_len];
3901 Technically, there's only supposed to be one such structure in a
3902 given apuinfo section, but the linker is not always vigilant about
3903 merging apuinfo sections from input files. Just go ahead and parse
3904 them all, exiting early when we discover the binary uses SPE
3907 It's not specified in what endianness the information in this
3908 section is stored. Assume that it's the endianness of the BFD. */
3912 unsigned int name_len
;
3913 unsigned int data_len
;
3916 /* If we can't read the first three fields, we're done. */
3920 name_len
= bfd_get_32 (abfd
, ptr
);
3921 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3922 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3923 type
= bfd_get_32 (abfd
, ptr
+ 8);
3926 /* The name must be "APUinfo\0". */
3928 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3932 /* The type must be 2. */
3936 /* The data is stored as a series of uint32. The upper half of
3937 each uint32 indicates the particular APU used and the lower
3938 half indicates the revision of that APU. We just care about
3941 /* Not 4-byte quantities. */
3947 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3948 unsigned int apu
= apuinfo
>> 16;
3952 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3954 if (apu
== 0x100 || apu
== 0x101)
3969 /* These are macros for parsing instruction fields (I.1.6.28) */
3971 #define PPC_FIELD(value, from, len) \
3972 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3973 #define PPC_SEXT(v, bs) \
3974 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3975 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3976 - ((CORE_ADDR) 1 << ((bs) - 1)))
3977 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3978 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3979 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3980 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3981 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3982 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3983 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3984 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3985 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3986 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3987 | (PPC_FIELD (insn, 16, 5) << 5))
3988 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3989 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3990 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3991 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3992 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3993 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3994 #define PPC_OE(insn) PPC_BIT (insn, 21)
3995 #define PPC_RC(insn) PPC_BIT (insn, 31)
3996 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3997 #define PPC_LK(insn) PPC_BIT (insn, 31)
3998 #define PPC_TX(insn) PPC_BIT (insn, 31)
3999 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
4001 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
4002 #define PPC_XER_NB(xer) (xer & 0x7f)
4004 /* Record Vector-Scalar Registers.
4005 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
4006 Otherwise, it's just a VR register. Record them accordingly. */
4009 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
4011 if (vsr
< 0 || vsr
>= 64)
4016 if (tdep
->ppc_vr0_regnum
>= 0)
4017 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
4021 if (tdep
->ppc_fp0_regnum
>= 0)
4022 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
4023 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
4024 record_full_arch_list_add_reg (regcache
,
4025 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4031 /* Parse and record instructions primary opcode-4 at ADDR.
4032 Return 0 if successful. */
4035 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4036 CORE_ADDR addr
, uint32_t insn
)
4038 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4039 int ext
= PPC_FIELD (insn
, 21, 11);
4040 int vra
= PPC_FIELD (insn
, 11, 5);
4044 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4045 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4046 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4047 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4048 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4050 case 42: /* Vector Select */
4051 case 43: /* Vector Permute */
4052 case 59: /* Vector Permute Right-indexed */
4053 case 44: /* Vector Shift Left Double by Octet Immediate */
4054 case 45: /* Vector Permute and Exclusive-OR */
4055 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4056 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4057 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4058 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4059 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4060 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4061 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4062 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4063 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4064 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4065 case 46: /* Vector Multiply-Add Single-Precision */
4066 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4067 record_full_arch_list_add_reg (regcache
,
4068 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4071 case 48: /* Multiply-Add High Doubleword */
4072 case 49: /* Multiply-Add High Doubleword Unsigned */
4073 case 51: /* Multiply-Add Low Doubleword */
4074 record_full_arch_list_add_reg (regcache
,
4075 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4079 switch ((ext
& 0x1ff))
4082 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4083 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4084 && vra
!= 4 /* Decimal Convert To Zoned */
4085 && vra
!= 5 /* Decimal Convert To National */
4086 && vra
!= 6 /* Decimal Convert From Zoned */
4087 && vra
!= 7 /* Decimal Convert From National */
4088 && vra
!= 31) /* Decimal Set Sign */
4091 /* 5.16 Decimal Integer Arithmetic Instructions */
4092 case 1: /* Decimal Add Modulo */
4093 case 65: /* Decimal Subtract Modulo */
4095 case 193: /* Decimal Shift */
4096 case 129: /* Decimal Unsigned Shift */
4097 case 449: /* Decimal Shift and Round */
4099 case 257: /* Decimal Truncate */
4100 case 321: /* Decimal Unsigned Truncate */
4102 /* Bit-21 should be set. */
4103 if (!PPC_BIT (insn
, 21))
4106 record_full_arch_list_add_reg (regcache
,
4107 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4108 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4112 /* Bit-21 is used for RC */
4113 switch (ext
& 0x3ff)
4115 case 6: /* Vector Compare Equal To Unsigned Byte */
4116 case 70: /* Vector Compare Equal To Unsigned Halfword */
4117 case 134: /* Vector Compare Equal To Unsigned Word */
4118 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4119 case 774: /* Vector Compare Greater Than Signed Byte */
4120 case 838: /* Vector Compare Greater Than Signed Halfword */
4121 case 902: /* Vector Compare Greater Than Signed Word */
4122 case 967: /* Vector Compare Greater Than Signed Doubleword */
4123 case 518: /* Vector Compare Greater Than Unsigned Byte */
4124 case 646: /* Vector Compare Greater Than Unsigned Word */
4125 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4126 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4127 case 966: /* Vector Compare Bounds Single-Precision */
4128 case 198: /* Vector Compare Equal To Single-Precision */
4129 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4130 case 710: /* Vector Compare Greater Than Single-Precision */
4131 case 7: /* Vector Compare Not Equal Byte */
4132 case 71: /* Vector Compare Not Equal Halfword */
4133 case 135: /* Vector Compare Not Equal Word */
4134 case 263: /* Vector Compare Not Equal or Zero Byte */
4135 case 327: /* Vector Compare Not Equal or Zero Halfword */
4136 case 391: /* Vector Compare Not Equal or Zero Word */
4138 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4139 record_full_arch_list_add_reg (regcache
,
4140 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4148 case 0: /* Vector Count Leading Zero Least-Significant Bits
4150 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4152 record_full_arch_list_add_reg (regcache
,
4153 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4156 case 6: /* Vector Negate Word */
4157 case 7: /* Vector Negate Doubleword */
4158 case 8: /* Vector Parity Byte Word */
4159 case 9: /* Vector Parity Byte Doubleword */
4160 case 10: /* Vector Parity Byte Quadword */
4161 case 16: /* Vector Extend Sign Byte To Word */
4162 case 17: /* Vector Extend Sign Halfword To Word */
4163 case 24: /* Vector Extend Sign Byte To Doubleword */
4164 case 25: /* Vector Extend Sign Halfword To Doubleword */
4165 case 26: /* Vector Extend Sign Word To Doubleword */
4166 case 28: /* Vector Count Trailing Zeros Byte */
4167 case 29: /* Vector Count Trailing Zeros Halfword */
4168 case 30: /* Vector Count Trailing Zeros Word */
4169 case 31: /* Vector Count Trailing Zeros Doubleword */
4170 record_full_arch_list_add_reg (regcache
,
4171 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4178 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4179 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4180 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4181 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4182 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4183 case 462: /* Vector Pack Signed Word Signed Saturate */
4184 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4185 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4186 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4187 case 512: /* Vector Add Unsigned Byte Saturate */
4188 case 576: /* Vector Add Unsigned Halfword Saturate */
4189 case 640: /* Vector Add Unsigned Word Saturate */
4190 case 768: /* Vector Add Signed Byte Saturate */
4191 case 832: /* Vector Add Signed Halfword Saturate */
4192 case 896: /* Vector Add Signed Word Saturate */
4193 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4194 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4195 case 1664: /* Vector Subtract Unsigned Word Saturate */
4196 case 1792: /* Vector Subtract Signed Byte Saturate */
4197 case 1856: /* Vector Subtract Signed Halfword Saturate */
4198 case 1920: /* Vector Subtract Signed Word Saturate */
4200 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4201 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4202 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4203 case 1672: /* Vector Sum across Half Signed Word Saturate */
4204 case 1928: /* Vector Sum across Signed Word Saturate */
4205 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4206 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4207 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4209 case 12: /* Vector Merge High Byte */
4210 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4211 case 76: /* Vector Merge High Halfword */
4212 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4213 case 140: /* Vector Merge High Word */
4214 case 268: /* Vector Merge Low Byte */
4215 case 332: /* Vector Merge Low Halfword */
4216 case 396: /* Vector Merge Low Word */
4217 case 526: /* Vector Unpack High Signed Byte */
4218 case 590: /* Vector Unpack High Signed Halfword */
4219 case 654: /* Vector Unpack Low Signed Byte */
4220 case 718: /* Vector Unpack Low Signed Halfword */
4221 case 782: /* Vector Pack Pixel */
4222 case 846: /* Vector Unpack High Pixel */
4223 case 974: /* Vector Unpack Low Pixel */
4224 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4225 case 1614: /* Vector Unpack High Signed Word */
4226 case 1676: /* Vector Merge Odd Word */
4227 case 1742: /* Vector Unpack Low Signed Word */
4228 case 1932: /* Vector Merge Even Word */
4229 case 524: /* Vector Splat Byte */
4230 case 588: /* Vector Splat Halfword */
4231 case 652: /* Vector Splat Word */
4232 case 780: /* Vector Splat Immediate Signed Byte */
4233 case 844: /* Vector Splat Immediate Signed Halfword */
4234 case 908: /* Vector Splat Immediate Signed Word */
4235 case 452: /* Vector Shift Left */
4236 case 708: /* Vector Shift Right */
4237 case 1036: /* Vector Shift Left by Octet */
4238 case 1100: /* Vector Shift Right by Octet */
4239 case 0: /* Vector Add Unsigned Byte Modulo */
4240 case 64: /* Vector Add Unsigned Halfword Modulo */
4241 case 128: /* Vector Add Unsigned Word Modulo */
4242 case 192: /* Vector Add Unsigned Doubleword Modulo */
4243 case 256: /* Vector Add Unsigned Quadword Modulo */
4244 case 320: /* Vector Add & write Carry Unsigned Quadword */
4245 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4246 case 8: /* Vector Multiply Odd Unsigned Byte */
4247 case 72: /* Vector Multiply Odd Unsigned Halfword */
4248 case 136: /* Vector Multiply Odd Unsigned Word */
4249 case 264: /* Vector Multiply Odd Signed Byte */
4250 case 328: /* Vector Multiply Odd Signed Halfword */
4251 case 392: /* Vector Multiply Odd Signed Word */
4252 case 520: /* Vector Multiply Even Unsigned Byte */
4253 case 584: /* Vector Multiply Even Unsigned Halfword */
4254 case 648: /* Vector Multiply Even Unsigned Word */
4255 case 776: /* Vector Multiply Even Signed Byte */
4256 case 840: /* Vector Multiply Even Signed Halfword */
4257 case 904: /* Vector Multiply Even Signed Word */
4258 case 137: /* Vector Multiply Unsigned Word Modulo */
4259 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4260 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4261 case 1152: /* Vector Subtract Unsigned Word Modulo */
4262 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4263 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4264 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4265 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4266 case 1282: /* Vector Average Signed Byte */
4267 case 1346: /* Vector Average Signed Halfword */
4268 case 1410: /* Vector Average Signed Word */
4269 case 1026: /* Vector Average Unsigned Byte */
4270 case 1090: /* Vector Average Unsigned Halfword */
4271 case 1154: /* Vector Average Unsigned Word */
4272 case 258: /* Vector Maximum Signed Byte */
4273 case 322: /* Vector Maximum Signed Halfword */
4274 case 386: /* Vector Maximum Signed Word */
4275 case 450: /* Vector Maximum Signed Doubleword */
4276 case 2: /* Vector Maximum Unsigned Byte */
4277 case 66: /* Vector Maximum Unsigned Halfword */
4278 case 130: /* Vector Maximum Unsigned Word */
4279 case 194: /* Vector Maximum Unsigned Doubleword */
4280 case 770: /* Vector Minimum Signed Byte */
4281 case 834: /* Vector Minimum Signed Halfword */
4282 case 898: /* Vector Minimum Signed Word */
4283 case 962: /* Vector Minimum Signed Doubleword */
4284 case 514: /* Vector Minimum Unsigned Byte */
4285 case 578: /* Vector Minimum Unsigned Halfword */
4286 case 642: /* Vector Minimum Unsigned Word */
4287 case 706: /* Vector Minimum Unsigned Doubleword */
4288 case 1028: /* Vector Logical AND */
4289 case 1668: /* Vector Logical Equivalent */
4290 case 1092: /* Vector Logical AND with Complement */
4291 case 1412: /* Vector Logical NAND */
4292 case 1348: /* Vector Logical OR with Complement */
4293 case 1156: /* Vector Logical OR */
4294 case 1284: /* Vector Logical NOR */
4295 case 1220: /* Vector Logical XOR */
4296 case 4: /* Vector Rotate Left Byte */
4297 case 132: /* Vector Rotate Left Word VX-form */
4298 case 68: /* Vector Rotate Left Halfword */
4299 case 196: /* Vector Rotate Left Doubleword */
4300 case 260: /* Vector Shift Left Byte */
4301 case 388: /* Vector Shift Left Word */
4302 case 324: /* Vector Shift Left Halfword */
4303 case 1476: /* Vector Shift Left Doubleword */
4304 case 516: /* Vector Shift Right Byte */
4305 case 644: /* Vector Shift Right Word */
4306 case 580: /* Vector Shift Right Halfword */
4307 case 1732: /* Vector Shift Right Doubleword */
4308 case 772: /* Vector Shift Right Algebraic Byte */
4309 case 900: /* Vector Shift Right Algebraic Word */
4310 case 836: /* Vector Shift Right Algebraic Halfword */
4311 case 964: /* Vector Shift Right Algebraic Doubleword */
4312 case 10: /* Vector Add Single-Precision */
4313 case 74: /* Vector Subtract Single-Precision */
4314 case 1034: /* Vector Maximum Single-Precision */
4315 case 1098: /* Vector Minimum Single-Precision */
4316 case 842: /* Vector Convert From Signed Fixed-Point Word */
4317 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4318 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4319 case 522: /* Vector Round to Single-Precision Integer Nearest */
4320 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4321 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4322 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4323 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4324 case 266: /* Vector Reciprocal Estimate Single-Precision */
4325 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4326 case 1288: /* Vector AES Cipher */
4327 case 1289: /* Vector AES Cipher Last */
4328 case 1352: /* Vector AES Inverse Cipher */
4329 case 1353: /* Vector AES Inverse Cipher Last */
4330 case 1480: /* Vector AES SubBytes */
4331 case 1730: /* Vector SHA-512 Sigma Doubleword */
4332 case 1666: /* Vector SHA-256 Sigma Word */
4333 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4334 case 1160: /* Vector Polynomial Multiply-Sum Word */
4335 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4336 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4337 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4338 case 1794: /* Vector Count Leading Zeros Byte */
4339 case 1858: /* Vector Count Leading Zeros Halfword */
4340 case 1922: /* Vector Count Leading Zeros Word */
4341 case 1986: /* Vector Count Leading Zeros Doubleword */
4342 case 1795: /* Vector Population Count Byte */
4343 case 1859: /* Vector Population Count Halfword */
4344 case 1923: /* Vector Population Count Word */
4345 case 1987: /* Vector Population Count Doubleword */
4346 case 1356: /* Vector Bit Permute Quadword */
4347 case 1484: /* Vector Bit Permute Doubleword */
4348 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4349 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4351 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4352 case 65: /* Vector Multiply-by-10 Extended & write Carry
4353 Unsigned Quadword */
4354 case 1027: /* Vector Absolute Difference Unsigned Byte */
4355 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4356 case 1155: /* Vector Absolute Difference Unsigned Word */
4357 case 1796: /* Vector Shift Right Variable */
4358 case 1860: /* Vector Shift Left Variable */
4359 case 133: /* Vector Rotate Left Word then Mask Insert */
4360 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4361 case 389: /* Vector Rotate Left Word then AND with Mask */
4362 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4363 case 525: /* Vector Extract Unsigned Byte */
4364 case 589: /* Vector Extract Unsigned Halfword */
4365 case 653: /* Vector Extract Unsigned Word */
4366 case 717: /* Vector Extract Doubleword */
4367 case 781: /* Vector Insert Byte */
4368 case 845: /* Vector Insert Halfword */
4369 case 909: /* Vector Insert Word */
4370 case 973: /* Vector Insert Doubleword */
4371 record_full_arch_list_add_reg (regcache
,
4372 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4375 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4376 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4377 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4378 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4379 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4380 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4381 record_full_arch_list_add_reg (regcache
,
4382 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4385 case 1604: /* Move To Vector Status and Control Register */
4386 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4388 case 1540: /* Move From Vector Status and Control Register */
4389 record_full_arch_list_add_reg (regcache
,
4390 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4392 case 833: /* Decimal Copy Sign */
4393 record_full_arch_list_add_reg (regcache
,
4394 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4395 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4399 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4400 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4404 /* Parse and record instructions of primary opcode-19 at ADDR.
4405 Return 0 if successful. */
4408 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4409 CORE_ADDR addr
, uint32_t insn
)
4411 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4412 int ext
= PPC_EXTOP (insn
);
4414 switch (ext
& 0x01f)
4416 case 2: /* Add PC Immediate Shifted */
4417 record_full_arch_list_add_reg (regcache
,
4418 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4424 case 0: /* Move Condition Register Field */
4425 case 33: /* Condition Register NOR */
4426 case 129: /* Condition Register AND with Complement */
4427 case 193: /* Condition Register XOR */
4428 case 225: /* Condition Register NAND */
4429 case 257: /* Condition Register AND */
4430 case 289: /* Condition Register Equivalent */
4431 case 417: /* Condition Register OR with Complement */
4432 case 449: /* Condition Register OR */
4433 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4436 case 16: /* Branch Conditional */
4437 case 560: /* Branch Conditional to Branch Target Address Register */
4438 if ((PPC_BO (insn
) & 0x4) == 0)
4439 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4441 case 528: /* Branch Conditional to Count Register */
4443 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4446 case 150: /* Instruction Synchronize */
4451 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4452 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4456 /* Parse and record instructions of primary opcode-31 at ADDR.
4457 Return 0 if successful. */
4460 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4461 CORE_ADDR addr
, uint32_t insn
)
4463 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4464 int ext
= PPC_EXTOP (insn
);
4466 CORE_ADDR at_dcsz
, ea
= 0;
4467 ULONGEST rb
, ra
, xer
;
4470 /* These instructions have OE bit. */
4471 switch (ext
& 0x1ff)
4473 /* These write RT and XER. Update CR if RC is set. */
4474 case 8: /* Subtract from carrying */
4475 case 10: /* Add carrying */
4476 case 136: /* Subtract from extended */
4477 case 138: /* Add extended */
4478 case 200: /* Subtract from zero extended */
4479 case 202: /* Add to zero extended */
4480 case 232: /* Subtract from minus one extended */
4481 case 234: /* Add to minus one extended */
4482 /* CA is always altered, but SO/OV are only altered when OE=1.
4483 In any case, XER is always altered. */
4484 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4486 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4487 record_full_arch_list_add_reg (regcache
,
4488 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4491 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4492 case 40: /* Subtract from */
4493 case 104: /* Negate */
4494 case 233: /* Multiply low doubleword */
4495 case 235: /* Multiply low word */
4497 case 393: /* Divide Doubleword Extended Unsigned */
4498 case 395: /* Divide Word Extended Unsigned */
4499 case 425: /* Divide Doubleword Extended */
4500 case 427: /* Divide Word Extended */
4501 case 457: /* Divide Doubleword Unsigned */
4502 case 459: /* Divide Word Unsigned */
4503 case 489: /* Divide Doubleword */
4504 case 491: /* Divide Word */
4506 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4508 case 9: /* Multiply High Doubleword Unsigned */
4509 case 11: /* Multiply High Word Unsigned */
4510 case 73: /* Multiply High Doubleword */
4511 case 75: /* Multiply High Word */
4513 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4514 record_full_arch_list_add_reg (regcache
,
4515 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4519 if ((ext
& 0x1f) == 15)
4521 /* Integer Select. bit[16:20] is used for BC. */
4522 record_full_arch_list_add_reg (regcache
,
4523 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4527 if ((ext
& 0xff) == 170)
4529 /* Add Extended using alternate carry bits */
4530 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4531 record_full_arch_list_add_reg (regcache
,
4532 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4538 case 78: /* Determine Leftmost Zero Byte */
4540 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4541 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4542 record_full_arch_list_add_reg (regcache
,
4543 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4546 /* These only write RT. */
4547 case 19: /* Move from condition register */
4548 /* Move From One Condition Register Field */
4549 case 74: /* Add and Generate Sixes */
4550 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4551 case 302: /* Move From Branch History Rolling Buffer */
4552 case 339: /* Move From Special Purpose Register */
4553 case 371: /* Move From Time Base [Phased-Out] */
4554 case 309: /* Load Doubleword Monitored Indexed */
4555 case 128: /* Set Boolean */
4556 case 755: /* Deliver A Random Number */
4557 record_full_arch_list_add_reg (regcache
,
4558 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4561 /* These only write to RA. */
4562 case 51: /* Move From VSR Doubleword */
4563 case 115: /* Move From VSR Word and Zero */
4564 case 122: /* Population count bytes */
4565 case 378: /* Population count words */
4566 case 506: /* Population count doublewords */
4567 case 154: /* Parity Word */
4568 case 186: /* Parity Doubleword */
4569 case 252: /* Bit Permute Doubleword */
4570 case 282: /* Convert Declets To Binary Coded Decimal */
4571 case 314: /* Convert Binary Coded Decimal To Declets */
4572 case 508: /* Compare bytes */
4573 case 307: /* Move From VSR Lower Doubleword */
4574 record_full_arch_list_add_reg (regcache
,
4575 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4578 /* These write CR and optional RA. */
4579 case 792: /* Shift Right Algebraic Word */
4580 case 794: /* Shift Right Algebraic Doubleword */
4581 case 824: /* Shift Right Algebraic Word Immediate */
4582 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4583 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4584 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4585 record_full_arch_list_add_reg (regcache
,
4586 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4588 case 0: /* Compare */
4589 case 32: /* Compare logical */
4590 case 144: /* Move To Condition Register Fields */
4591 /* Move To One Condition Register Field */
4592 case 192: /* Compare Ranged Byte */
4593 case 224: /* Compare Equal Byte */
4594 case 576: /* Move XER to CR Extended */
4595 case 902: /* Paste (should always fail due to single-stepping and
4596 the memory location might not be accessible, so
4598 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4601 /* These write to RT. Update RA if 'update indexed.' */
4602 case 53: /* Load Doubleword with Update Indexed */
4603 case 119: /* Load Byte and Zero with Update Indexed */
4604 case 311: /* Load Halfword and Zero with Update Indexed */
4605 case 55: /* Load Word and Zero with Update Indexed */
4606 case 375: /* Load Halfword Algebraic with Update Indexed */
4607 case 373: /* Load Word Algebraic with Update Indexed */
4608 record_full_arch_list_add_reg (regcache
,
4609 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4611 case 21: /* Load Doubleword Indexed */
4612 case 52: /* Load Byte And Reserve Indexed */
4613 case 116: /* Load Halfword And Reserve Indexed */
4614 case 20: /* Load Word And Reserve Indexed */
4615 case 84: /* Load Doubleword And Reserve Indexed */
4616 case 87: /* Load Byte and Zero Indexed */
4617 case 279: /* Load Halfword and Zero Indexed */
4618 case 23: /* Load Word and Zero Indexed */
4619 case 343: /* Load Halfword Algebraic Indexed */
4620 case 341: /* Load Word Algebraic Indexed */
4621 case 790: /* Load Halfword Byte-Reverse Indexed */
4622 case 534: /* Load Word Byte-Reverse Indexed */
4623 case 532: /* Load Doubleword Byte-Reverse Indexed */
4624 case 582: /* Load Word Atomic */
4625 case 614: /* Load Doubleword Atomic */
4626 case 265: /* Modulo Unsigned Doubleword */
4627 case 777: /* Modulo Signed Doubleword */
4628 case 267: /* Modulo Unsigned Word */
4629 case 779: /* Modulo Signed Word */
4630 record_full_arch_list_add_reg (regcache
,
4631 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4634 case 597: /* Load String Word Immediate */
4635 case 533: /* Load String Word Indexed */
4644 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4645 nr
= PPC_XER_NB (xer
);
4650 /* If n=0, the contents of register RT are undefined. */
4654 for (i
= 0; i
< nr
; i
++)
4655 record_full_arch_list_add_reg (regcache
,
4656 tdep
->ppc_gp0_regnum
4657 + ((PPC_RT (insn
) + i
) & 0x1f));
4660 case 276: /* Load Quadword And Reserve Indexed */
4661 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4662 record_full_arch_list_add_reg (regcache
, tmp
);
4663 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4666 /* These write VRT. */
4667 case 6: /* Load Vector for Shift Left Indexed */
4668 case 38: /* Load Vector for Shift Right Indexed */
4669 case 7: /* Load Vector Element Byte Indexed */
4670 case 39: /* Load Vector Element Halfword Indexed */
4671 case 71: /* Load Vector Element Word Indexed */
4672 case 103: /* Load Vector Indexed */
4673 case 359: /* Load Vector Indexed LRU */
4674 record_full_arch_list_add_reg (regcache
,
4675 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4678 /* These write FRT. Update RA if 'update indexed.' */
4679 case 567: /* Load Floating-Point Single with Update Indexed */
4680 case 631: /* Load Floating-Point Double with Update Indexed */
4681 record_full_arch_list_add_reg (regcache
,
4682 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4684 case 535: /* Load Floating-Point Single Indexed */
4685 case 599: /* Load Floating-Point Double Indexed */
4686 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4687 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4688 record_full_arch_list_add_reg (regcache
,
4689 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4692 case 791: /* Load Floating-Point Double Pair Indexed */
4693 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4694 record_full_arch_list_add_reg (regcache
, tmp
);
4695 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4698 case 179: /* Move To VSR Doubleword */
4699 case 211: /* Move To VSR Word Algebraic */
4700 case 243: /* Move To VSR Word and Zero */
4701 case 588: /* Load VSX Scalar Doubleword Indexed */
4702 case 524: /* Load VSX Scalar Single-Precision Indexed */
4703 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4704 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4705 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4706 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4707 case 780: /* Load VSX Vector Word*4 Indexed */
4708 case 268: /* Load VSX Vector Indexed */
4709 case 364: /* Load VSX Vector Word & Splat Indexed */
4710 case 812: /* Load VSX Vector Halfword*8 Indexed */
4711 case 876: /* Load VSX Vector Byte*16 Indexed */
4712 case 269: /* Load VSX Vector with Length */
4713 case 301: /* Load VSX Vector Left-justified with Length */
4714 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4715 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4716 case 403: /* Move To VSR Word & Splat */
4717 case 435: /* Move To VSR Double Doubleword */
4718 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4721 /* These write RA. Update CR if RC is set. */
4722 case 24: /* Shift Left Word */
4723 case 26: /* Count Leading Zeros Word */
4724 case 27: /* Shift Left Doubleword */
4726 case 58: /* Count Leading Zeros Doubleword */
4727 case 60: /* AND with Complement */
4729 case 284: /* Equivalent */
4731 case 476: /* NAND */
4732 case 412: /* OR with Complement */
4734 case 536: /* Shift Right Word */
4735 case 539: /* Shift Right Doubleword */
4736 case 922: /* Extend Sign Halfword */
4737 case 954: /* Extend Sign Byte */
4738 case 986: /* Extend Sign Word */
4739 case 538: /* Count Trailing Zeros Word */
4740 case 570: /* Count Trailing Zeros Doubleword */
4741 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4742 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4744 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
4745 && (PPC_RS (insn
) == PPC_RA (insn
))
4746 && (PPC_RA (insn
) == PPC_RB (insn
))
4749 /* or Rx,Rx,Rx alters PRI in PPR. */
4750 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4755 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4756 record_full_arch_list_add_reg (regcache
,
4757 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4761 case 181: /* Store Doubleword with Update Indexed */
4762 case 183: /* Store Word with Update Indexed */
4763 case 247: /* Store Byte with Update Indexed */
4764 case 439: /* Store Half Word with Update Indexed */
4765 case 695: /* Store Floating-Point Single with Update Indexed */
4766 case 759: /* Store Floating-Point Double with Update Indexed */
4767 record_full_arch_list_add_reg (regcache
,
4768 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4770 case 135: /* Store Vector Element Byte Indexed */
4771 case 167: /* Store Vector Element Halfword Indexed */
4772 case 199: /* Store Vector Element Word Indexed */
4773 case 231: /* Store Vector Indexed */
4774 case 487: /* Store Vector Indexed LRU */
4775 case 716: /* Store VSX Scalar Doubleword Indexed */
4776 case 140: /* Store VSX Scalar as Integer Word Indexed */
4777 case 652: /* Store VSX Scalar Single-Precision Indexed */
4778 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4779 case 908: /* Store VSX Vector Word*4 Indexed */
4780 case 149: /* Store Doubleword Indexed */
4781 case 151: /* Store Word Indexed */
4782 case 215: /* Store Byte Indexed */
4783 case 407: /* Store Half Word Indexed */
4784 case 694: /* Store Byte Conditional Indexed */
4785 case 726: /* Store Halfword Conditional Indexed */
4786 case 150: /* Store Word Conditional Indexed */
4787 case 214: /* Store Doubleword Conditional Indexed */
4788 case 182: /* Store Quadword Conditional Indexed */
4789 case 662: /* Store Word Byte-Reverse Indexed */
4790 case 918: /* Store Halfword Byte-Reverse Indexed */
4791 case 660: /* Store Doubleword Byte-Reverse Indexed */
4792 case 663: /* Store Floating-Point Single Indexed */
4793 case 727: /* Store Floating-Point Double Indexed */
4794 case 919: /* Store Floating-Point Double Pair Indexed */
4795 case 983: /* Store Floating-Point as Integer Word Indexed */
4796 case 396: /* Store VSX Vector Indexed */
4797 case 940: /* Store VSX Vector Halfword*8 Indexed */
4798 case 1004: /* Store VSX Vector Byte*16 Indexed */
4799 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4800 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4801 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4802 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4805 if (PPC_RA (insn
) != 0)
4806 regcache_raw_read_unsigned (regcache
,
4807 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4808 regcache_raw_read_unsigned (regcache
,
4809 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4814 case 183: /* Store Word with Update Indexed */
4815 case 199: /* Store Vector Element Word Indexed */
4816 case 140: /* Store VSX Scalar as Integer Word Indexed */
4817 case 652: /* Store VSX Scalar Single-Precision Indexed */
4818 case 151: /* Store Word Indexed */
4819 case 150: /* Store Word Conditional Indexed */
4820 case 662: /* Store Word Byte-Reverse Indexed */
4821 case 663: /* Store Floating-Point Single Indexed */
4822 case 695: /* Store Floating-Point Single with Update Indexed */
4823 case 983: /* Store Floating-Point as Integer Word Indexed */
4826 case 247: /* Store Byte with Update Indexed */
4827 case 135: /* Store Vector Element Byte Indexed */
4828 case 215: /* Store Byte Indexed */
4829 case 694: /* Store Byte Conditional Indexed */
4830 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4833 case 439: /* Store Halfword with Update Indexed */
4834 case 167: /* Store Vector Element Halfword Indexed */
4835 case 407: /* Store Halfword Indexed */
4836 case 726: /* Store Halfword Conditional Indexed */
4837 case 918: /* Store Halfword Byte-Reverse Indexed */
4838 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4841 case 181: /* Store Doubleword with Update Indexed */
4842 case 716: /* Store VSX Scalar Doubleword Indexed */
4843 case 149: /* Store Doubleword Indexed */
4844 case 214: /* Store Doubleword Conditional Indexed */
4845 case 660: /* Store Doubleword Byte-Reverse Indexed */
4846 case 727: /* Store Floating-Point Double Indexed */
4847 case 759: /* Store Floating-Point Double with Update Indexed */
4850 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4851 case 908: /* Store VSX Vector Word*4 Indexed */
4852 case 182: /* Store Quadword Conditional Indexed */
4853 case 231: /* Store Vector Indexed */
4854 case 487: /* Store Vector Indexed LRU */
4855 case 919: /* Store Floating-Point Double Pair Indexed */
4856 case 396: /* Store VSX Vector Indexed */
4857 case 940: /* Store VSX Vector Halfword*8 Indexed */
4858 case 1004: /* Store VSX Vector Byte*16 Indexed */
4865 /* Align address for Store Vector instructions. */
4868 case 167: /* Store Vector Element Halfword Indexed */
4869 addr
= addr
& ~0x1ULL
;
4872 case 199: /* Store Vector Element Word Indexed */
4873 addr
= addr
& ~0x3ULL
;
4876 case 231: /* Store Vector Indexed */
4877 case 487: /* Store Vector Indexed LRU */
4878 addr
= addr
& ~0xfULL
;
4882 record_full_arch_list_add_mem (addr
, size
);
4885 case 397: /* Store VSX Vector with Length */
4886 case 429: /* Store VSX Vector Left-justified with Length */
4888 if (PPC_RA (insn
) != 0)
4889 regcache_raw_read_unsigned (regcache
,
4890 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4892 regcache_raw_read_unsigned (regcache
,
4893 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4894 /* Store up to 16 bytes. */
4895 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4897 record_full_arch_list_add_mem (ea
, nb
);
4900 case 710: /* Store Word Atomic */
4901 case 742: /* Store Doubleword Atomic */
4903 if (PPC_RA (insn
) != 0)
4904 regcache_raw_read_unsigned (regcache
,
4905 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4909 case 710: /* Store Word Atomic */
4912 case 742: /* Store Doubleword Atomic */
4918 record_full_arch_list_add_mem (ea
, size
);
4921 case 725: /* Store String Word Immediate */
4923 if (PPC_RA (insn
) != 0)
4924 regcache_raw_read_unsigned (regcache
,
4925 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4932 record_full_arch_list_add_mem (ea
, nb
);
4936 case 661: /* Store String Word Indexed */
4938 if (PPC_RA (insn
) != 0)
4939 regcache_raw_read_unsigned (regcache
,
4940 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4943 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4944 nb
= PPC_XER_NB (xer
);
4948 regcache_raw_read_unsigned (regcache
,
4949 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4952 record_full_arch_list_add_mem (ea
, nb
);
4957 case 467: /* Move To Special Purpose Register */
4958 switch (PPC_SPR (insn
))
4961 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4964 if (tdep
->ppc_dscr_regnum
>= 0)
4965 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
4968 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4971 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4973 case 256: /* VRSAVE */
4974 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4977 if (tdep
->ppc_tar_regnum
>= 0)
4978 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
4982 if (tdep
->ppc_ppr_regnum
>= 0)
4983 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4989 case 147: /* Move To Split Little Endian */
4990 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4993 case 512: /* Move to Condition Register from XER */
4994 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4995 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4998 case 4: /* Trap Word */
4999 case 68: /* Trap Doubleword */
5000 case 430: /* Clear BHRB */
5001 case 598: /* Synchronize */
5002 case 62: /* Wait for Interrupt */
5004 case 22: /* Instruction Cache Block Touch */
5005 case 854: /* Enforce In-order Execution of I/O */
5006 case 246: /* Data Cache Block Touch for Store */
5007 case 54: /* Data Cache Block Store */
5008 case 86: /* Data Cache Block Flush */
5009 case 278: /* Data Cache Block Touch */
5010 case 758: /* Data Cache Block Allocate */
5011 case 982: /* Instruction Cache Block Invalidate */
5012 case 774: /* Copy */
5013 case 838: /* CP_Abort */
5016 case 654: /* Transaction Begin */
5017 case 686: /* Transaction End */
5018 case 750: /* Transaction Suspend or Resume */
5019 case 782: /* Transaction Abort Word Conditional */
5020 case 814: /* Transaction Abort Doubleword Conditional */
5021 case 846: /* Transaction Abort Word Conditional Immediate */
5022 case 878: /* Transaction Abort Doubleword Conditional Immediate */
5023 case 910: /* Transaction Abort */
5024 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5026 case 718: /* Transaction Check */
5027 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5030 case 1014: /* Data Cache Block set to Zero */
5031 if (target_auxv_search (current_top_target (), AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5033 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5036 if (PPC_RA (insn
) != 0)
5037 regcache_raw_read_unsigned (regcache
,
5038 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5039 regcache_raw_read_unsigned (regcache
,
5040 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5041 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5042 record_full_arch_list_add_mem (ea
, at_dcsz
);
5047 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5048 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5052 /* Parse and record instructions of primary opcode-59 at ADDR.
5053 Return 0 if successful. */
5056 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5057 CORE_ADDR addr
, uint32_t insn
)
5059 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5060 int ext
= PPC_EXTOP (insn
);
5064 case 18: /* Floating Divide */
5065 case 20: /* Floating Subtract */
5066 case 21: /* Floating Add */
5067 case 22: /* Floating Square Root */
5068 case 24: /* Floating Reciprocal Estimate */
5069 case 25: /* Floating Multiply */
5070 case 26: /* Floating Reciprocal Square Root Estimate */
5071 case 28: /* Floating Multiply-Subtract */
5072 case 29: /* Floating Multiply-Add */
5073 case 30: /* Floating Negative Multiply-Subtract */
5074 case 31: /* Floating Negative Multiply-Add */
5075 record_full_arch_list_add_reg (regcache
,
5076 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5078 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5079 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5086 case 2: /* DFP Add */
5087 case 3: /* DFP Quantize */
5088 case 34: /* DFP Multiply */
5089 case 35: /* DFP Reround */
5090 case 67: /* DFP Quantize Immediate */
5091 case 99: /* DFP Round To FP Integer With Inexact */
5092 case 227: /* DFP Round To FP Integer Without Inexact */
5093 case 258: /* DFP Convert To DFP Long! */
5094 case 290: /* DFP Convert To Fixed */
5095 case 514: /* DFP Subtract */
5096 case 546: /* DFP Divide */
5097 case 770: /* DFP Round To DFP Short! */
5098 case 802: /* DFP Convert From Fixed */
5099 case 834: /* DFP Encode BCD To DPD */
5101 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5102 record_full_arch_list_add_reg (regcache
,
5103 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5104 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5107 case 130: /* DFP Compare Ordered */
5108 case 162: /* DFP Test Exponent */
5109 case 194: /* DFP Test Data Class */
5110 case 226: /* DFP Test Data Group */
5111 case 642: /* DFP Compare Unordered */
5112 case 674: /* DFP Test Significance */
5113 case 675: /* DFP Test Significance Immediate */
5114 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5115 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5118 case 66: /* DFP Shift Significand Left Immediate */
5119 case 98: /* DFP Shift Significand Right Immediate */
5120 case 322: /* DFP Decode DPD To BCD */
5121 case 354: /* DFP Extract Biased Exponent */
5122 case 866: /* DFP Insert Biased Exponent */
5123 record_full_arch_list_add_reg (regcache
,
5124 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5126 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5129 case 846: /* Floating Convert From Integer Doubleword Single */
5130 case 974: /* Floating Convert From Integer Doubleword Unsigned
5132 record_full_arch_list_add_reg (regcache
,
5133 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5135 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5136 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5141 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5142 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5146 /* Parse and record instructions of primary opcode-60 at ADDR.
5147 Return 0 if successful. */
5150 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5151 CORE_ADDR addr
, uint32_t insn
)
5153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5154 int ext
= PPC_EXTOP (insn
);
5158 case 0: /* VSX Scalar Add Single-Precision */
5159 case 32: /* VSX Scalar Add Double-Precision */
5160 case 24: /* VSX Scalar Divide Single-Precision */
5161 case 56: /* VSX Scalar Divide Double-Precision */
5162 case 176: /* VSX Scalar Copy Sign Double-Precision */
5163 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5164 case 41: /* ditto */
5165 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5167 case 160: /* VSX Scalar Maximum Double-Precision */
5168 case 168: /* VSX Scalar Minimum Double-Precision */
5169 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5170 case 57: /* ditto */
5171 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5172 case 25: /* ditto */
5173 case 48: /* VSX Scalar Multiply Double-Precision */
5174 case 16: /* VSX Scalar Multiply Single-Precision */
5175 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5176 case 169: /* ditto */
5177 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5178 case 137: /* ditto */
5179 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5180 case 185: /* ditto */
5181 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5182 case 153: /* ditto */
5183 case 40: /* VSX Scalar Subtract Double-Precision */
5184 case 8: /* VSX Scalar Subtract Single-Precision */
5185 case 96: /* VSX Vector Add Double-Precision */
5186 case 64: /* VSX Vector Add Single-Precision */
5187 case 120: /* VSX Vector Divide Double-Precision */
5188 case 88: /* VSX Vector Divide Single-Precision */
5189 case 97: /* VSX Vector Multiply-Add Double-Precision */
5190 case 105: /* ditto */
5191 case 65: /* VSX Vector Multiply-Add Single-Precision */
5192 case 73: /* ditto */
5193 case 224: /* VSX Vector Maximum Double-Precision */
5194 case 192: /* VSX Vector Maximum Single-Precision */
5195 case 232: /* VSX Vector Minimum Double-Precision */
5196 case 200: /* VSX Vector Minimum Single-Precision */
5197 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5198 case 121: /* ditto */
5199 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5200 case 89: /* ditto */
5201 case 112: /* VSX Vector Multiply Double-Precision */
5202 case 80: /* VSX Vector Multiply Single-Precision */
5203 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5204 case 233: /* ditto */
5205 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5206 case 201: /* ditto */
5207 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5208 case 249: /* ditto */
5209 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5210 case 217: /* ditto */
5211 case 104: /* VSX Vector Subtract Double-Precision */
5212 case 72: /* VSX Vector Subtract Single-Precision */
5213 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5214 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5215 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5216 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5217 case 3: /* VSX Scalar Compare Equal Double-Precision */
5218 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5219 case 19: /* VSX Scalar Compare Greater Than or Equal
5221 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5223 case 240: /* VSX Vector Copy Sign Double-Precision */
5224 case 208: /* VSX Vector Copy Sign Single-Precision */
5225 case 130: /* VSX Logical AND */
5226 case 138: /* VSX Logical AND with Complement */
5227 case 186: /* VSX Logical Equivalence */
5228 case 178: /* VSX Logical NAND */
5229 case 170: /* VSX Logical OR with Complement */
5230 case 162: /* VSX Logical NOR */
5231 case 146: /* VSX Logical OR */
5232 case 154: /* VSX Logical XOR */
5233 case 18: /* VSX Merge High Word */
5234 case 50: /* VSX Merge Low Word */
5235 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5236 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5237 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5238 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5239 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5240 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5241 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5242 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5243 case 216: /* VSX Vector Insert Exponent Single-Precision */
5244 case 248: /* VSX Vector Insert Exponent Double-Precision */
5245 case 26: /* VSX Vector Permute */
5246 case 58: /* VSX Vector Permute Right-indexed */
5247 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5248 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5249 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5250 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5251 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5254 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5255 case 125: /* VSX Vector Test for software Divide Double-Precision */
5256 case 93: /* VSX Vector Test for software Divide Single-Precision */
5257 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5260 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5261 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5262 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5263 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5264 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5268 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5270 case 99: /* VSX Vector Compare Equal To Double-Precision */
5271 case 67: /* VSX Vector Compare Equal To Single-Precision */
5272 case 115: /* VSX Vector Compare Greater Than or
5273 Equal To Double-Precision */
5274 case 83: /* VSX Vector Compare Greater Than or
5275 Equal To Single-Precision */
5276 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5277 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5279 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5280 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5281 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5287 case 265: /* VSX Scalar round Double-Precision to
5288 Single-Precision and Convert to
5289 Single-Precision format */
5290 case 344: /* VSX Scalar truncate Double-Precision to
5291 Integer and Convert to Signed Integer
5292 Doubleword format with Saturate */
5293 case 88: /* VSX Scalar truncate Double-Precision to
5294 Integer and Convert to Signed Integer Word
5295 Format with Saturate */
5296 case 328: /* VSX Scalar truncate Double-Precision integer
5297 and Convert to Unsigned Integer Doubleword
5298 Format with Saturate */
5299 case 72: /* VSX Scalar truncate Double-Precision to
5300 Integer and Convert to Unsigned Integer Word
5301 Format with Saturate */
5302 case 329: /* VSX Scalar Convert Single-Precision to
5303 Double-Precision format */
5304 case 376: /* VSX Scalar Convert Signed Integer
5305 Doubleword to floating-point format and
5306 Round to Double-Precision format */
5307 case 312: /* VSX Scalar Convert Signed Integer
5308 Doubleword to floating-point format and
5309 round to Single-Precision */
5310 case 360: /* VSX Scalar Convert Unsigned Integer
5311 Doubleword to floating-point format and
5312 Round to Double-Precision format */
5313 case 296: /* VSX Scalar Convert Unsigned Integer
5314 Doubleword to floating-point format and
5315 Round to Single-Precision */
5316 case 73: /* VSX Scalar Round to Double-Precision Integer
5317 Using Round to Nearest Away */
5318 case 107: /* VSX Scalar Round to Double-Precision Integer
5319 Exact using Current rounding mode */
5320 case 121: /* VSX Scalar Round to Double-Precision Integer
5321 Using Round toward -Infinity */
5322 case 105: /* VSX Scalar Round to Double-Precision Integer
5323 Using Round toward +Infinity */
5324 case 89: /* VSX Scalar Round to Double-Precision Integer
5325 Using Round toward Zero */
5326 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5327 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5328 case 281: /* VSX Scalar Round to Single-Precision */
5329 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5331 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5333 case 75: /* VSX Scalar Square Root Double-Precision */
5334 case 11: /* VSX Scalar Square Root Single-Precision */
5335 case 393: /* VSX Vector round Double-Precision to
5336 Single-Precision and Convert to
5337 Single-Precision format */
5338 case 472: /* VSX Vector truncate Double-Precision to
5339 Integer and Convert to Signed Integer
5340 Doubleword format with Saturate */
5341 case 216: /* VSX Vector truncate Double-Precision to
5342 Integer and Convert to Signed Integer Word
5343 Format with Saturate */
5344 case 456: /* VSX Vector truncate Double-Precision to
5345 Integer and Convert to Unsigned Integer
5346 Doubleword format with Saturate */
5347 case 200: /* VSX Vector truncate Double-Precision to
5348 Integer and Convert to Unsigned Integer Word
5349 Format with Saturate */
5350 case 457: /* VSX Vector Convert Single-Precision to
5351 Double-Precision format */
5352 case 408: /* VSX Vector truncate Single-Precision to
5353 Integer and Convert to Signed Integer
5354 Doubleword format with Saturate */
5355 case 152: /* VSX Vector truncate Single-Precision to
5356 Integer and Convert to Signed Integer Word
5357 Format with Saturate */
5358 case 392: /* VSX Vector truncate Single-Precision to
5359 Integer and Convert to Unsigned Integer
5360 Doubleword format with Saturate */
5361 case 136: /* VSX Vector truncate Single-Precision to
5362 Integer and Convert to Unsigned Integer Word
5363 Format with Saturate */
5364 case 504: /* VSX Vector Convert and round Signed Integer
5365 Doubleword to Double-Precision format */
5366 case 440: /* VSX Vector Convert and round Signed Integer
5367 Doubleword to Single-Precision format */
5368 case 248: /* VSX Vector Convert Signed Integer Word to
5369 Double-Precision format */
5370 case 184: /* VSX Vector Convert and round Signed Integer
5371 Word to Single-Precision format */
5372 case 488: /* VSX Vector Convert and round Unsigned
5373 Integer Doubleword to Double-Precision format */
5374 case 424: /* VSX Vector Convert and round Unsigned
5375 Integer Doubleword to Single-Precision format */
5376 case 232: /* VSX Vector Convert and round Unsigned
5377 Integer Word to Double-Precision format */
5378 case 168: /* VSX Vector Convert and round Unsigned
5379 Integer Word to Single-Precision format */
5380 case 201: /* VSX Vector Round to Double-Precision
5381 Integer using round to Nearest Away */
5382 case 235: /* VSX Vector Round to Double-Precision
5383 Integer Exact using Current rounding mode */
5384 case 249: /* VSX Vector Round to Double-Precision
5385 Integer using round toward -Infinity */
5386 case 233: /* VSX Vector Round to Double-Precision
5387 Integer using round toward +Infinity */
5388 case 217: /* VSX Vector Round to Double-Precision
5389 Integer using round toward Zero */
5390 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5391 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5392 case 137: /* VSX Vector Round to Single-Precision Integer
5393 Using Round to Nearest Away */
5394 case 171: /* VSX Vector Round to Single-Precision Integer
5395 Exact Using Current rounding mode */
5396 case 185: /* VSX Vector Round to Single-Precision Integer
5397 Using Round toward -Infinity */
5398 case 169: /* VSX Vector Round to Single-Precision Integer
5399 Using Round toward +Infinity */
5400 case 153: /* VSX Vector Round to Single-Precision Integer
5401 Using round toward Zero */
5402 case 202: /* VSX Vector Reciprocal Square Root Estimate
5404 case 138: /* VSX Vector Reciprocal Square Root Estimate
5406 case 203: /* VSX Vector Square Root Double-Precision */
5407 case 139: /* VSX Vector Square Root Single-Precision */
5408 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5410 case 345: /* VSX Scalar Absolute Value Double-Precision */
5411 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5412 Vector Single-Precision format Non-signalling */
5413 case 331: /* VSX Scalar Convert Single-Precision to
5414 Double-Precision format Non-signalling */
5415 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5416 case 377: /* VSX Scalar Negate Double-Precision */
5417 case 473: /* VSX Vector Absolute Value Double-Precision */
5418 case 409: /* VSX Vector Absolute Value Single-Precision */
5419 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5420 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5421 case 505: /* VSX Vector Negate Double-Precision */
5422 case 441: /* VSX Vector Negate Single-Precision */
5423 case 164: /* VSX Splat Word */
5424 case 165: /* VSX Vector Extract Unsigned Word */
5425 case 181: /* VSX Vector Insert Word */
5426 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5429 case 298: /* VSX Scalar Test Data Class Single-Precision */
5430 case 362: /* VSX Scalar Test Data Class Double-Precision */
5431 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5433 case 106: /* VSX Scalar Test for software Square Root
5435 case 234: /* VSX Vector Test for software Square Root
5437 case 170: /* VSX Vector Test for software Square Root
5439 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5443 switch (PPC_FIELD (insn
, 11, 5))
5445 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5446 case 1: /* VSX Scalar Extract Significand Double-Precision */
5447 record_full_arch_list_add_reg (regcache
,
5448 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5450 case 16: /* VSX Scalar Convert Half-Precision format to
5451 Double-Precision format */
5452 case 17: /* VSX Scalar round & Convert Double-Precision format
5453 to Half-Precision format */
5454 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5455 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5461 switch (PPC_FIELD (insn
, 11, 5))
5463 case 24: /* VSX Vector Convert Half-Precision format to
5464 Single-Precision format */
5465 case 25: /* VSX Vector round and Convert Single-Precision format
5466 to Half-Precision format */
5467 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5469 case 0: /* VSX Vector Extract Exponent Double-Precision */
5470 case 1: /* VSX Vector Extract Significand Double-Precision */
5471 case 7: /* VSX Vector Byte-Reverse Halfword */
5472 case 8: /* VSX Vector Extract Exponent Single-Precision */
5473 case 9: /* VSX Vector Extract Significand Single-Precision */
5474 case 15: /* VSX Vector Byte-Reverse Word */
5475 case 23: /* VSX Vector Byte-Reverse Doubleword */
5476 case 31: /* VSX Vector Byte-Reverse Quadword */
5477 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5485 case 360: /* VSX Vector Splat Immediate Byte */
5486 if (PPC_FIELD (insn
, 11, 2) == 0)
5488 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5492 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5493 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5497 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5499 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5503 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5504 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5508 /* Parse and record instructions of primary opcode-61 at ADDR.
5509 Return 0 if successful. */
5512 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5513 CORE_ADDR addr
, uint32_t insn
)
5515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5521 case 0: /* Store Floating-Point Double Pair */
5522 case 2: /* Store VSX Scalar Doubleword */
5523 case 3: /* Store VSX Scalar Single */
5524 if (PPC_RA (insn
) != 0)
5525 regcache_raw_read_unsigned (regcache
,
5526 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5528 ea
+= PPC_DS (insn
) << 2;
5531 case 0: /* Store Floating-Point Double Pair */
5534 case 2: /* Store VSX Scalar Doubleword */
5537 case 3: /* Store VSX Scalar Single */
5543 record_full_arch_list_add_mem (ea
, size
);
5549 case 1: /* Load VSX Vector */
5550 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5552 case 5: /* Store VSX Vector */
5553 if (PPC_RA (insn
) != 0)
5554 regcache_raw_read_unsigned (regcache
,
5555 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5557 ea
+= PPC_DQ (insn
) << 4;
5558 record_full_arch_list_add_mem (ea
, 16);
5562 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5563 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5567 /* Parse and record instructions of primary opcode-63 at ADDR.
5568 Return 0 if successful. */
5571 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5572 CORE_ADDR addr
, uint32_t insn
)
5574 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5575 int ext
= PPC_EXTOP (insn
);
5580 case 18: /* Floating Divide */
5581 case 20: /* Floating Subtract */
5582 case 21: /* Floating Add */
5583 case 22: /* Floating Square Root */
5584 case 24: /* Floating Reciprocal Estimate */
5585 case 25: /* Floating Multiply */
5586 case 26: /* Floating Reciprocal Square Root Estimate */
5587 case 28: /* Floating Multiply-Subtract */
5588 case 29: /* Floating Multiply-Add */
5589 case 30: /* Floating Negative Multiply-Subtract */
5590 case 31: /* Floating Negative Multiply-Add */
5591 record_full_arch_list_add_reg (regcache
,
5592 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5594 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5595 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5598 case 23: /* Floating Select */
5599 record_full_arch_list_add_reg (regcache
,
5600 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5602 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5608 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5609 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5611 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5612 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5618 case 2: /* DFP Add Quad */
5619 case 3: /* DFP Quantize Quad */
5620 case 34: /* DFP Multiply Quad */
5621 case 35: /* DFP Reround Quad */
5622 case 67: /* DFP Quantize Immediate Quad */
5623 case 99: /* DFP Round To FP Integer With Inexact Quad */
5624 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5625 case 258: /* DFP Convert To DFP Extended Quad */
5626 case 514: /* DFP Subtract Quad */
5627 case 546: /* DFP Divide Quad */
5628 case 770: /* DFP Round To DFP Long Quad */
5629 case 802: /* DFP Convert From Fixed Quad */
5630 case 834: /* DFP Encode BCD To DPD Quad */
5632 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5633 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5634 record_full_arch_list_add_reg (regcache
, tmp
);
5635 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5636 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5639 case 130: /* DFP Compare Ordered Quad */
5640 case 162: /* DFP Test Exponent Quad */
5641 case 194: /* DFP Test Data Class Quad */
5642 case 226: /* DFP Test Data Group Quad */
5643 case 642: /* DFP Compare Unordered Quad */
5644 case 674: /* DFP Test Significance Quad */
5645 case 675: /* DFP Test Significance Immediate Quad */
5646 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5647 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5650 case 66: /* DFP Shift Significand Left Immediate Quad */
5651 case 98: /* DFP Shift Significand Right Immediate Quad */
5652 case 322: /* DFP Decode DPD To BCD Quad */
5653 case 866: /* DFP Insert Biased Exponent Quad */
5654 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5655 record_full_arch_list_add_reg (regcache
, tmp
);
5656 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5658 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5661 case 290: /* DFP Convert To Fixed Quad */
5662 record_full_arch_list_add_reg (regcache
,
5663 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5665 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5666 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5669 case 354: /* DFP Extract Biased Exponent Quad */
5670 record_full_arch_list_add_reg (regcache
,
5671 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5673 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5676 case 12: /* Floating Round to Single-Precision */
5677 case 14: /* Floating Convert To Integer Word */
5678 case 15: /* Floating Convert To Integer Word
5679 with round toward Zero */
5680 case 142: /* Floating Convert To Integer Word Unsigned */
5681 case 143: /* Floating Convert To Integer Word Unsigned
5682 with round toward Zero */
5683 case 392: /* Floating Round to Integer Nearest */
5684 case 424: /* Floating Round to Integer Toward Zero */
5685 case 456: /* Floating Round to Integer Plus */
5686 case 488: /* Floating Round to Integer Minus */
5687 case 814: /* Floating Convert To Integer Doubleword */
5688 case 815: /* Floating Convert To Integer Doubleword
5689 with round toward Zero */
5690 case 846: /* Floating Convert From Integer Doubleword */
5691 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5692 case 943: /* Floating Convert To Integer Doubleword Unsigned
5693 with round toward Zero */
5694 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5695 record_full_arch_list_add_reg (regcache
,
5696 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5698 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5699 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5703 switch (PPC_FIELD (insn
, 11, 5))
5705 case 1: /* Move From FPSCR & Clear Enables */
5706 case 20: /* Move From FPSCR Control & set DRN */
5707 case 21: /* Move From FPSCR Control & set DRN Immediate */
5708 case 22: /* Move From FPSCR Control & set RN */
5709 case 23: /* Move From FPSCR Control & set RN Immediate */
5710 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5712 case 0: /* Move From FPSCR */
5713 case 24: /* Move From FPSCR Lightweight */
5714 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5715 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5716 record_full_arch_list_add_reg (regcache
,
5717 tdep
->ppc_fp0_regnum
5723 case 8: /* Floating Copy Sign */
5724 case 40: /* Floating Negate */
5725 case 72: /* Floating Move Register */
5726 case 136: /* Floating Negative Absolute Value */
5727 case 264: /* Floating Absolute Value */
5728 record_full_arch_list_add_reg (regcache
,
5729 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5731 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5734 case 838: /* Floating Merge Odd Word */
5735 case 966: /* Floating Merge Even Word */
5736 record_full_arch_list_add_reg (regcache
,
5737 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5740 case 38: /* Move To FPSCR Bit 1 */
5741 case 70: /* Move To FPSCR Bit 0 */
5742 case 134: /* Move To FPSCR Field Immediate */
5743 case 711: /* Move To FPSCR Fields */
5745 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5746 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5749 case 0: /* Floating Compare Unordered */
5750 case 32: /* Floating Compare Ordered */
5751 case 64: /* Move to Condition Register from FPSCR */
5752 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5753 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5754 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5755 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5756 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5758 case 128: /* Floating Test for software Divide */
5759 case 160: /* Floating Test for software Square Root */
5760 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5763 case 4: /* VSX Scalar Add Quad-Precision */
5764 case 36: /* VSX Scalar Multiply Quad-Precision */
5765 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5766 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5767 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5768 case 484: /* VSX Scalar Negative Multiply-Subtract
5770 case 516: /* VSX Scalar Subtract Quad-Precision */
5771 case 548: /* VSX Scalar Divide Quad-Precision */
5772 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5774 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5775 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5776 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5780 switch (PPC_FIELD (insn
, 11, 5))
5782 case 27: /* VSX Scalar Square Root Quad-Precision */
5783 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5785 case 0: /* VSX Scalar Absolute Quad-Precision */
5786 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5787 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5788 case 16: /* VSX Scalar Negate Quad-Precision */
5789 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5790 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5796 switch (PPC_FIELD (insn
, 11, 5))
5798 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5799 to Unsigned Word format */
5800 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5801 Quad-Precision format */
5802 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5803 to Signed Word format */
5804 case 10: /* VSX Scalar Convert Signed Doubleword format to
5805 Quad-Precision format */
5806 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5807 to Unsigned Doubleword format */
5808 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5809 Double-Precision format */
5810 case 22: /* VSX Scalar Convert Double-Precision format to
5811 Quad-Precision format */
5812 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5813 to Signed Doubleword format */
5814 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5815 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5820 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5821 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5825 /* Parse the current instruction and record the values of the registers and
5826 memory that will be changed in current instruction to "record_arch_list".
5827 Return -1 if something wrong. */
5830 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5833 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5834 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5838 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5839 op6
= PPC_OP6 (insn
);
5843 case 2: /* Trap Doubleword Immediate */
5844 case 3: /* Trap Word Immediate */
5849 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5853 case 17: /* System call */
5854 if (PPC_LEV (insn
) != 0)
5857 if (tdep
->ppc_syscall_record
!= NULL
)
5859 if (tdep
->ppc_syscall_record (regcache
) != 0)
5864 printf_unfiltered (_("no syscall record support\n"));
5869 case 7: /* Multiply Low Immediate */
5870 record_full_arch_list_add_reg (regcache
,
5871 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5874 case 8: /* Subtract From Immediate Carrying */
5875 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5876 record_full_arch_list_add_reg (regcache
,
5877 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5880 case 10: /* Compare Logical Immediate */
5881 case 11: /* Compare Immediate */
5882 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5885 case 13: /* Add Immediate Carrying and Record */
5886 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5888 case 12: /* Add Immediate Carrying */
5889 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5891 case 14: /* Add Immediate */
5892 case 15: /* Add Immediate Shifted */
5893 record_full_arch_list_add_reg (regcache
,
5894 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5897 case 16: /* Branch Conditional */
5898 if ((PPC_BO (insn
) & 0x4) == 0)
5899 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5901 case 18: /* Branch */
5903 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5907 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5911 case 20: /* Rotate Left Word Immediate then Mask Insert */
5912 case 21: /* Rotate Left Word Immediate then AND with Mask */
5913 case 23: /* Rotate Left Word then AND with Mask */
5914 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5915 /* Rotate Left Doubleword Immediate then Clear Right */
5916 /* Rotate Left Doubleword Immediate then Clear */
5917 /* Rotate Left Doubleword then Clear Left */
5918 /* Rotate Left Doubleword then Clear Right */
5919 /* Rotate Left Doubleword Immediate then Mask Insert */
5921 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5922 record_full_arch_list_add_reg (regcache
,
5923 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5926 case 28: /* AND Immediate */
5927 case 29: /* AND Immediate Shifted */
5928 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5930 case 24: /* OR Immediate */
5931 case 25: /* OR Immediate Shifted */
5932 case 26: /* XOR Immediate */
5933 case 27: /* XOR Immediate Shifted */
5934 record_full_arch_list_add_reg (regcache
,
5935 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5939 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5943 case 33: /* Load Word and Zero with Update */
5944 case 35: /* Load Byte and Zero with Update */
5945 case 41: /* Load Halfword and Zero with Update */
5946 case 43: /* Load Halfword Algebraic with Update */
5947 record_full_arch_list_add_reg (regcache
,
5948 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5950 case 32: /* Load Word and Zero */
5951 case 34: /* Load Byte and Zero */
5952 case 40: /* Load Halfword and Zero */
5953 case 42: /* Load Halfword Algebraic */
5954 record_full_arch_list_add_reg (regcache
,
5955 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5958 case 46: /* Load Multiple Word */
5959 for (i
= PPC_RT (insn
); i
< 32; i
++)
5960 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5963 case 56: /* Load Quadword */
5964 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5965 record_full_arch_list_add_reg (regcache
, tmp
);
5966 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5969 case 49: /* Load Floating-Point Single with Update */
5970 case 51: /* Load Floating-Point Double with Update */
5971 record_full_arch_list_add_reg (regcache
,
5972 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5974 case 48: /* Load Floating-Point Single */
5975 case 50: /* Load Floating-Point Double */
5976 record_full_arch_list_add_reg (regcache
,
5977 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5980 case 47: /* Store Multiple Word */
5984 if (PPC_RA (insn
) != 0)
5985 regcache_raw_read_unsigned (regcache
,
5986 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5989 iaddr
+= PPC_D (insn
);
5990 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
5994 case 37: /* Store Word with Update */
5995 case 39: /* Store Byte with Update */
5996 case 45: /* Store Halfword with Update */
5997 case 53: /* Store Floating-Point Single with Update */
5998 case 55: /* Store Floating-Point Double with Update */
5999 record_full_arch_list_add_reg (regcache
,
6000 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6002 case 36: /* Store Word */
6003 case 38: /* Store Byte */
6004 case 44: /* Store Halfword */
6005 case 52: /* Store Floating-Point Single */
6006 case 54: /* Store Floating-Point Double */
6011 if (PPC_RA (insn
) != 0)
6012 regcache_raw_read_unsigned (regcache
,
6013 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6015 iaddr
+= PPC_D (insn
);
6017 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
6019 else if (op6
== 54 || op6
== 55)
6021 else if (op6
== 44 || op6
== 45)
6023 else if (op6
== 38 || op6
== 39)
6028 record_full_arch_list_add_mem (iaddr
, size
);
6035 case 0: /* Load Floating-Point Double Pair */
6036 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
6037 record_full_arch_list_add_reg (regcache
, tmp
);
6038 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6040 case 2: /* Load VSX Scalar Doubleword */
6041 case 3: /* Load VSX Scalar Single */
6042 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6049 case 58: /* Load Doubleword */
6050 /* Load Doubleword with Update */
6051 /* Load Word Algebraic */
6052 if (PPC_FIELD (insn
, 30, 2) > 2)
6055 record_full_arch_list_add_reg (regcache
,
6056 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6057 if (PPC_BIT (insn
, 31))
6058 record_full_arch_list_add_reg (regcache
,
6059 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6063 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
6068 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
6073 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
6077 case 62: /* Store Doubleword */
6078 /* Store Doubleword with Update */
6079 /* Store Quadword with Update */
6083 int sub2
= PPC_FIELD (insn
, 30, 2);
6088 if (PPC_RA (insn
) != 0)
6089 regcache_raw_read_unsigned (regcache
,
6090 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6093 size
= (sub2
== 2) ? 16 : 8;
6095 iaddr
+= PPC_DS (insn
) << 2;
6096 record_full_arch_list_add_mem (iaddr
, size
);
6098 if (op6
== 62 && sub2
== 1)
6099 record_full_arch_list_add_reg (regcache
,
6100 tdep
->ppc_gp0_regnum
+
6107 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
6113 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
6114 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
6118 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
6120 if (record_full_arch_list_add_end ())
6125 /* Initialize the current architecture based on INFO. If possible, re-use an
6126 architecture from ARCHES, which is a list of architectures already created
6127 during this debugging session.
6129 Called e.g. at program startup, when reading a core file, and when reading
6132 static struct gdbarch
*
6133 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6135 struct gdbarch
*gdbarch
;
6136 struct gdbarch_tdep
*tdep
;
6137 int wordsize
, from_xcoff_exec
, from_elf_exec
;
6138 enum bfd_architecture arch
;
6141 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
6143 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
6144 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
6145 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
6146 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
6147 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
6148 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
6149 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
6150 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
6151 int have_htm_tar
= 0;
6152 int tdesc_wordsize
= -1;
6153 const struct target_desc
*tdesc
= info
.target_desc
;
6154 struct tdesc_arch_data
*tdesc_data
= NULL
;
6155 int num_pseudoregs
= 0;
6158 /* INFO may refer to a binary that is not of the PowerPC architecture,
6159 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
6160 In this case, we must not attempt to infer properties of the (PowerPC
6161 side) of the target system from properties of that executable. Trust
6162 the target description instead. */
6164 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
6165 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
6168 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6169 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
6171 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6172 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
6174 /* Check word size. If INFO is from a binary file, infer it from
6175 that, else choose a likely default. */
6176 if (from_xcoff_exec
)
6178 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
6183 else if (from_elf_exec
)
6185 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6190 else if (tdesc_has_registers (tdesc
))
6194 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6195 wordsize
= (info
.bfd_arch_info
->bits_per_word
6196 / info
.bfd_arch_info
->bits_per_byte
);
6201 /* Get the architecture and machine from the BFD. */
6202 arch
= info
.bfd_arch_info
->arch
;
6203 mach
= info
.bfd_arch_info
->mach
;
6205 /* For e500 executables, the apuinfo section is of help here. Such
6206 section contains the identifier and revision number of each
6207 Application-specific Processing Unit that is present on the
6208 chip. The content of the section is determined by the assembler
6209 which looks at each instruction and determines which unit (and
6210 which version of it) can execute it. Grovel through the section
6211 looking for relevant e500 APUs. */
6213 if (bfd_uses_spe_extensions (info
.abfd
))
6215 arch
= info
.bfd_arch_info
->arch
;
6216 mach
= bfd_mach_ppc_e500
;
6217 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6218 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6221 /* Find a default target description which describes our register
6222 layout, if we do not already have one. */
6223 if (! tdesc_has_registers (tdesc
))
6225 const struct variant
*v
;
6227 /* Choose variant. */
6228 v
= find_variant_by_arch (arch
, mach
);
6235 gdb_assert (tdesc_has_registers (tdesc
));
6237 /* Check any target description for validity. */
6238 if (tdesc_has_registers (tdesc
))
6240 static const char *const gprs
[] = {
6241 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6242 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6243 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6244 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6246 const struct tdesc_feature
*feature
;
6248 static const char *const msr_names
[] = { "msr", "ps" };
6249 static const char *const cr_names
[] = { "cr", "cnd" };
6250 static const char *const ctr_names
[] = { "ctr", "cnt" };
6252 feature
= tdesc_find_feature (tdesc
,
6253 "org.gnu.gdb.power.core");
6254 if (feature
== NULL
)
6257 tdesc_data
= tdesc_data_alloc ();
6260 for (i
= 0; i
< ppc_num_gprs
; i
++)
6261 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
6262 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
6264 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
6266 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
6269 /* Allow alternate names for these registers, to accomodate GDB's
6271 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6272 PPC_MSR_REGNUM
, msr_names
);
6273 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6274 PPC_CR_REGNUM
, cr_names
);
6275 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6276 PPC_CTR_REGNUM
, ctr_names
);
6280 tdesc_data_cleanup (tdesc_data
);
6284 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
6287 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
6289 wordsize
= tdesc_wordsize
;
6291 feature
= tdesc_find_feature (tdesc
,
6292 "org.gnu.gdb.power.fpu");
6293 if (feature
!= NULL
)
6295 static const char *const fprs
[] = {
6296 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6297 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6298 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6299 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6302 for (i
= 0; i
< ppc_num_fprs
; i
++)
6303 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6304 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6305 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6306 PPC_FPSCR_REGNUM
, "fpscr");
6310 tdesc_data_cleanup (tdesc_data
);
6315 /* The fpscr register was expanded in isa 2.05 to 64 bits
6316 along with the addition of the decimal floating point
6318 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
6324 feature
= tdesc_find_feature (tdesc
,
6325 "org.gnu.gdb.power.altivec");
6326 if (feature
!= NULL
)
6328 static const char *const vector_regs
[] = {
6329 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6330 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6331 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6332 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6336 for (i
= 0; i
< ppc_num_gprs
; i
++)
6337 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6340 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6341 PPC_VSCR_REGNUM
, "vscr");
6342 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6343 PPC_VRSAVE_REGNUM
, "vrsave");
6345 if (have_spe
|| !valid_p
)
6347 tdesc_data_cleanup (tdesc_data
);
6355 /* Check for POWER7 VSX registers support. */
6356 feature
= tdesc_find_feature (tdesc
,
6357 "org.gnu.gdb.power.vsx");
6359 if (feature
!= NULL
)
6361 static const char *const vsx_regs
[] = {
6362 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6363 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6364 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6365 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6366 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6372 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6373 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6374 PPC_VSR0_UPPER_REGNUM
+ i
,
6377 if (!valid_p
|| !have_fpu
|| !have_altivec
)
6379 tdesc_data_cleanup (tdesc_data
);
6388 /* On machines supporting the SPE APU, the general-purpose registers
6389 are 64 bits long. There are SIMD vector instructions to treat them
6390 as pairs of floats, but the rest of the instruction set treats them
6391 as 32-bit registers, and only operates on their lower halves.
6393 In the GDB regcache, we treat their high and low halves as separate
6394 registers. The low halves we present as the general-purpose
6395 registers, and then we have pseudo-registers that stitch together
6396 the upper and lower halves and present them as pseudo-registers.
6398 Thus, the target description is expected to supply the upper
6399 halves separately. */
6401 feature
= tdesc_find_feature (tdesc
,
6402 "org.gnu.gdb.power.spe");
6403 if (feature
!= NULL
)
6405 static const char *const upper_spe
[] = {
6406 "ev0h", "ev1h", "ev2h", "ev3h",
6407 "ev4h", "ev5h", "ev6h", "ev7h",
6408 "ev8h", "ev9h", "ev10h", "ev11h",
6409 "ev12h", "ev13h", "ev14h", "ev15h",
6410 "ev16h", "ev17h", "ev18h", "ev19h",
6411 "ev20h", "ev21h", "ev22h", "ev23h",
6412 "ev24h", "ev25h", "ev26h", "ev27h",
6413 "ev28h", "ev29h", "ev30h", "ev31h"
6417 for (i
= 0; i
< ppc_num_gprs
; i
++)
6418 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6419 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6421 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6422 PPC_SPE_ACC_REGNUM
, "acc");
6423 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6424 PPC_SPE_FSCR_REGNUM
, "spefscr");
6426 if (have_mq
|| have_fpu
|| !valid_p
)
6428 tdesc_data_cleanup (tdesc_data
);
6436 /* Program Priority Register. */
6437 feature
= tdesc_find_feature (tdesc
,
6438 "org.gnu.gdb.power.ppr");
6439 if (feature
!= NULL
)
6442 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6443 PPC_PPR_REGNUM
, "ppr");
6447 tdesc_data_cleanup (tdesc_data
);
6455 /* Data Stream Control Register. */
6456 feature
= tdesc_find_feature (tdesc
,
6457 "org.gnu.gdb.power.dscr");
6458 if (feature
!= NULL
)
6461 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6462 PPC_DSCR_REGNUM
, "dscr");
6466 tdesc_data_cleanup (tdesc_data
);
6474 /* Target Address Register. */
6475 feature
= tdesc_find_feature (tdesc
,
6476 "org.gnu.gdb.power.tar");
6477 if (feature
!= NULL
)
6480 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6481 PPC_TAR_REGNUM
, "tar");
6485 tdesc_data_cleanup (tdesc_data
);
6493 /* Event-based Branching Registers. */
6494 feature
= tdesc_find_feature (tdesc
,
6495 "org.gnu.gdb.power.ebb");
6496 if (feature
!= NULL
)
6498 static const char *const ebb_regs
[] = {
6499 "bescr", "ebbhr", "ebbrr"
6503 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
6504 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6505 PPC_BESCR_REGNUM
+ i
,
6509 tdesc_data_cleanup (tdesc_data
);
6517 /* Subset of the ISA 2.07 Performance Monitor Registers provided
6519 feature
= tdesc_find_feature (tdesc
,
6520 "org.gnu.gdb.power.linux.pmu");
6521 if (feature
!= NULL
)
6525 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6528 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6531 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6534 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6537 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6543 tdesc_data_cleanup (tdesc_data
);
6551 /* Hardware Transactional Memory Registers. */
6552 feature
= tdesc_find_feature (tdesc
,
6553 "org.gnu.gdb.power.htm.spr");
6554 if (feature
!= NULL
)
6556 static const char *const tm_spr_regs
[] = {
6557 "tfhar", "texasr", "tfiar"
6561 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
6562 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6563 PPC_TFHAR_REGNUM
+ i
,
6567 tdesc_data_cleanup (tdesc_data
);
6576 feature
= tdesc_find_feature (tdesc
,
6577 "org.gnu.gdb.power.htm.core");
6578 if (feature
!= NULL
)
6580 static const char *const cgprs
[] = {
6581 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
6582 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
6583 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
6584 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
6585 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
6590 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
6591 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6596 tdesc_data_cleanup (tdesc_data
);
6605 feature
= tdesc_find_feature (tdesc
,
6606 "org.gnu.gdb.power.htm.fpu");
6607 if (feature
!= NULL
)
6611 static const char *const cfprs
[] = {
6612 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
6613 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
6614 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
6615 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
6616 "cf30", "cf31", "cfpscr"
6619 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
6620 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6626 tdesc_data_cleanup (tdesc_data
);
6634 feature
= tdesc_find_feature (tdesc
,
6635 "org.gnu.gdb.power.htm.altivec");
6636 if (feature
!= NULL
)
6640 static const char *const cvmx
[] = {
6641 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
6642 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
6643 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
6644 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
6645 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
6649 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
6650 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6651 PPC_CVR0_REGNUM
+ i
,
6656 tdesc_data_cleanup (tdesc_data
);
6659 have_htm_altivec
= 1;
6662 have_htm_altivec
= 0;
6664 feature
= tdesc_find_feature (tdesc
,
6665 "org.gnu.gdb.power.htm.vsx");
6666 if (feature
!= NULL
)
6670 static const char *const cvsx
[] = {
6671 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
6672 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
6673 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
6674 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
6675 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
6679 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
6680 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6681 (PPC_CVSR0_UPPER_REGNUM
6685 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
6687 tdesc_data_cleanup (tdesc_data
);
6695 feature
= tdesc_find_feature (tdesc
,
6696 "org.gnu.gdb.power.htm.ppr");
6697 if (feature
!= NULL
)
6699 valid_p
= tdesc_numbered_register (feature
, tdesc_data
,
6700 PPC_CPPR_REGNUM
, "cppr");
6704 tdesc_data_cleanup (tdesc_data
);
6712 feature
= tdesc_find_feature (tdesc
,
6713 "org.gnu.gdb.power.htm.dscr");
6714 if (feature
!= NULL
)
6716 valid_p
= tdesc_numbered_register (feature
, tdesc_data
,
6717 PPC_CDSCR_REGNUM
, "cdscr");
6721 tdesc_data_cleanup (tdesc_data
);
6729 feature
= tdesc_find_feature (tdesc
,
6730 "org.gnu.gdb.power.htm.tar");
6731 if (feature
!= NULL
)
6733 valid_p
= tdesc_numbered_register (feature
, tdesc_data
,
6734 PPC_CTAR_REGNUM
, "ctar");
6738 tdesc_data_cleanup (tdesc_data
);
6747 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6748 complain for a 32-bit binary on a 64-bit target; we do not yet
6749 support that. For instance, the 32-bit ABI routines expect
6752 As long as there isn't an explicit target description, we'll
6753 choose one based on the BFD architecture and get a word size
6754 matching the binary (probably powerpc:common or
6755 powerpc:common64). So there is only trouble if a 64-bit target
6756 supplies a 64-bit description while debugging a 32-bit
6758 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6760 tdesc_data_cleanup (tdesc_data
);
6767 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6770 elf_abi
= POWERPC_ELF_V1
;
6773 elf_abi
= POWERPC_ELF_V2
;
6780 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6782 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6783 Tag_GNU_Power_ABI_FP
) & 3)
6786 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6789 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6796 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6798 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6799 Tag_GNU_Power_ABI_FP
) >> 2)
6802 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6805 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6812 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6814 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6815 Tag_GNU_Power_ABI_Vector
))
6818 vector_abi
= POWERPC_VEC_GENERIC
;
6821 vector_abi
= POWERPC_VEC_ALTIVEC
;
6824 vector_abi
= POWERPC_VEC_SPE
;
6832 /* At this point, the only supported ELF-based 64-bit little-endian
6833 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6834 default. All other supported ELF-based operating systems use the
6835 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6836 e.g. because we run a legacy binary, or have attached to a process
6837 and have not found any associated binary file, set the default
6838 according to this heuristic. */
6839 if (elf_abi
== POWERPC_ELF_AUTO
)
6841 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6842 elf_abi
= POWERPC_ELF_V2
;
6844 elf_abi
= POWERPC_ELF_V1
;
6847 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6849 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6852 soft_float
= !have_fpu
;
6854 /* If we have a hard float binary or setting but no floating point
6855 registers, downgrade to soft float anyway. We're still somewhat
6856 useful in this scenario. */
6857 if (!soft_float
&& !have_fpu
)
6860 /* Similarly for vector registers. */
6861 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6862 vector_abi
= POWERPC_VEC_GENERIC
;
6864 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6865 vector_abi
= POWERPC_VEC_GENERIC
;
6867 if (vector_abi
== POWERPC_VEC_AUTO
)
6870 vector_abi
= POWERPC_VEC_ALTIVEC
;
6872 vector_abi
= POWERPC_VEC_SPE
;
6874 vector_abi
= POWERPC_VEC_GENERIC
;
6877 /* Do not limit the vector ABI based on available hardware, since we
6878 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6880 /* Find a candidate among extant architectures. */
6881 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6883 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6885 /* Word size in the various PowerPC bfd_arch_info structs isn't
6886 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6887 separate word size check. */
6888 tdep
= gdbarch_tdep (arches
->gdbarch
);
6889 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6891 if (tdep
&& tdep
->soft_float
!= soft_float
)
6893 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6895 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6897 if (tdep
&& tdep
->wordsize
== wordsize
)
6899 if (tdesc_data
!= NULL
)
6900 tdesc_data_cleanup (tdesc_data
);
6901 return arches
->gdbarch
;
6905 /* None found, create a new architecture from INFO, whose bfd_arch_info
6906 validity depends on the source:
6907 - executable useless
6908 - rs6000_host_arch() good
6910 - "set arch" trust blindly
6911 - GDB startup useless but harmless */
6913 tdep
= XCNEW (struct gdbarch_tdep
);
6914 tdep
->wordsize
= wordsize
;
6915 tdep
->elf_abi
= elf_abi
;
6916 tdep
->soft_float
= soft_float
;
6917 tdep
->long_double_abi
= long_double_abi
;
6918 tdep
->vector_abi
= vector_abi
;
6920 gdbarch
= gdbarch_alloc (&info
, tdep
);
6922 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6923 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6924 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6925 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6926 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6927 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6928 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6929 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6931 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6932 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6933 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6934 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6935 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6936 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6937 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6938 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6939 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
6940 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
6941 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
6942 tdep
->have_ebb
= have_ebb
;
6944 /* If additional pmu registers are added, care must be taken when
6945 setting new fields in the tdep below, to maintain compatibility
6946 with features that only provide some of the registers. Currently
6947 gdb access to the pmu registers is only supported in linux, and
6948 linux only provides a subset of the pmu registers defined in the
6951 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
6952 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
6953 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
6954 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
6955 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
6957 tdep
->have_htm_spr
= have_htm_spr
;
6958 tdep
->have_htm_core
= have_htm_core
;
6959 tdep
->have_htm_fpu
= have_htm_fpu
;
6960 tdep
->have_htm_altivec
= have_htm_altivec
;
6961 tdep
->have_htm_vsx
= have_htm_vsx
;
6962 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
6963 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
6964 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
6966 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6967 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6968 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6969 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6971 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6972 GDB traditionally called it "ps", though, so let GDB add an
6974 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6977 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6979 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6981 /* Set lr_frame_offset. */
6983 tdep
->lr_frame_offset
= 16;
6985 tdep
->lr_frame_offset
= 4;
6987 if (have_spe
|| have_dfp
|| have_altivec
6988 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
6990 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6991 set_gdbarch_pseudo_register_write (gdbarch
,
6992 rs6000_pseudo_register_write
);
6993 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6994 rs6000_ax_pseudo_register_collect
);
6997 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6999 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
7001 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
7004 num_pseudoregs
+= 32;
7006 num_pseudoregs
+= 16;
7008 num_pseudoregs
+= 32;
7010 /* Include both VSX and Extended FP registers. */
7011 num_pseudoregs
+= 96;
7013 num_pseudoregs
+= 16;
7014 /* Include both checkpointed VSX and EFP registers. */
7016 num_pseudoregs
+= 64 + 32;
7018 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
7020 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7021 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
7022 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7023 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7024 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7025 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7026 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7027 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
7028 set_gdbarch_char_signed (gdbarch
, 0);
7030 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
7033 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
7035 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
7036 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
7037 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
7039 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
7040 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
7043 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
7044 else if (wordsize
== 8)
7045 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
7047 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
7048 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
7049 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
7051 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7053 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
7054 rs6000_breakpoint::kind_from_pc
);
7055 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
7056 rs6000_breakpoint::bp_from_kind
);
7058 /* The value of symbols of type N_SO and N_FUN maybe null when
7060 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
7062 /* Handles single stepping of atomic sequences. */
7063 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
7065 /* Not sure on this. FIXMEmgo */
7066 set_gdbarch_frame_args_skip (gdbarch
, 8);
7068 /* Helpers for function argument information. */
7069 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
7072 set_gdbarch_in_solib_return_trampoline
7073 (gdbarch
, rs6000_in_solib_return_trampoline
);
7074 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
7076 /* Hook in the DWARF CFI frame unwinder. */
7077 dwarf2_append_unwinders (gdbarch
);
7078 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
7080 /* Frame handling. */
7081 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
7083 /* Setup displaced stepping. */
7084 set_gdbarch_displaced_step_copy_insn (gdbarch
,
7085 ppc_displaced_step_copy_insn
);
7086 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
7087 ppc_displaced_step_hw_singlestep
);
7088 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
7089 set_gdbarch_displaced_step_location (gdbarch
,
7090 displaced_step_at_entry_point
);
7092 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
7094 /* Hook in ABI-specific overrides, if they have been registered. */
7095 info
.target_desc
= tdesc
;
7096 info
.tdesc_data
= tdesc_data
;
7097 gdbarch_init_osabi (info
, gdbarch
);
7101 case GDB_OSABI_LINUX
:
7102 case GDB_OSABI_NETBSD
:
7103 case GDB_OSABI_UNKNOWN
:
7104 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
7105 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7106 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7107 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
7108 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7111 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
7113 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
7114 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7115 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7116 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
7117 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7120 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
7121 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
7122 rs6000_pseudo_register_reggroup_p
);
7123 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7125 /* Override the normal target description method to make the SPE upper
7126 halves anonymous. */
7127 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
7129 /* Choose register numbers for all supported pseudo-registers. */
7130 tdep
->ppc_ev0_regnum
= -1;
7131 tdep
->ppc_dl0_regnum
= -1;
7132 tdep
->ppc_v0_alias_regnum
= -1;
7133 tdep
->ppc_vsr0_regnum
= -1;
7134 tdep
->ppc_efpr0_regnum
= -1;
7135 tdep
->ppc_cdl0_regnum
= -1;
7136 tdep
->ppc_cvsr0_regnum
= -1;
7137 tdep
->ppc_cefpr0_regnum
= -1;
7139 cur_reg
= gdbarch_num_regs (gdbarch
);
7143 tdep
->ppc_ev0_regnum
= cur_reg
;
7148 tdep
->ppc_dl0_regnum
= cur_reg
;
7153 tdep
->ppc_v0_alias_regnum
= cur_reg
;
7158 tdep
->ppc_vsr0_regnum
= cur_reg
;
7160 tdep
->ppc_efpr0_regnum
= cur_reg
;
7165 tdep
->ppc_cdl0_regnum
= cur_reg
;
7170 tdep
->ppc_cvsr0_regnum
= cur_reg
;
7172 tdep
->ppc_cefpr0_regnum
= cur_reg
;
7176 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
7178 /* Register the ravenscar_arch_ops. */
7179 if (mach
== bfd_mach_ppc_e500
)
7180 register_e500_ravenscar_ops (gdbarch
);
7182 register_ppc_ravenscar_ops (gdbarch
);
7184 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
7185 set_gdbarch_valid_disassembler_options (gdbarch
,
7186 disassembler_options_powerpc ());
7192 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7199 /* FIXME: Dump gdbarch_tdep. */
7202 /* PowerPC-specific commands. */
7205 set_powerpc_command (const char *args
, int from_tty
)
7207 printf_unfiltered (_("\
7208 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
7209 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
7213 show_powerpc_command (const char *args
, int from_tty
)
7215 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
7219 powerpc_set_soft_float (const char *args
, int from_tty
,
7220 struct cmd_list_element
*c
)
7222 struct gdbarch_info info
;
7224 /* Update the architecture. */
7225 gdbarch_info_init (&info
);
7226 if (!gdbarch_update_p (info
))
7227 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7231 powerpc_set_vector_abi (const char *args
, int from_tty
,
7232 struct cmd_list_element
*c
)
7234 struct gdbarch_info info
;
7237 for (vector_abi
= POWERPC_VEC_AUTO
;
7238 vector_abi
!= POWERPC_VEC_LAST
;
7240 if (strcmp (powerpc_vector_abi_string
,
7241 powerpc_vector_strings
[vector_abi
]) == 0)
7243 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
7247 if (vector_abi
== POWERPC_VEC_LAST
)
7248 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
7249 powerpc_vector_abi_string
);
7251 /* Update the architecture. */
7252 gdbarch_info_init (&info
);
7253 if (!gdbarch_update_p (info
))
7254 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7257 /* Show the current setting of the exact watchpoints flag. */
7260 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
7261 struct cmd_list_element
*c
,
7264 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
7267 /* Read a PPC instruction from memory. */
7270 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
7272 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7273 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7275 return read_memory_unsigned_integer (pc
, 4, byte_order
);
7278 /* Return non-zero if the instructions at PC match the series
7279 described in PATTERN, or zero otherwise. PATTERN is an array of
7280 'struct ppc_insn_pattern' objects, terminated by an entry whose
7283 When the match is successful, fill INSNS[i] with what PATTERN[i]
7284 matched. If PATTERN[i] is optional, and the instruction wasn't
7285 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
7286 INSNS should have as many elements as PATTERN, minus the terminator.
7287 Note that, if PATTERN contains optional instructions which aren't
7288 present in memory, then INSNS will have holes, so INSNS[i] isn't
7289 necessarily the i'th instruction in memory. */
7292 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
7293 const struct ppc_insn_pattern
*pattern
,
7294 unsigned int *insns
)
7299 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
7302 insn
= read_insn (frame
, pc
);
7304 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
7310 else if (!pattern
[i
].optional
)
7317 /* Return the 'd' field of the d-form instruction INSN, properly
7321 ppc_insn_d_field (unsigned int insn
)
7323 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
7326 /* Return the 'ds' field of the ds-form instruction INSN, with the two
7327 zero bits concatenated at the right, and properly
7331 ppc_insn_ds_field (unsigned int insn
)
7333 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
7336 /* Initialization code. */
7339 _initialize_rs6000_tdep (void)
7341 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7342 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7344 /* Initialize the standard target descriptions. */
7345 initialize_tdesc_powerpc_32 ();
7346 initialize_tdesc_powerpc_altivec32 ();
7347 initialize_tdesc_powerpc_vsx32 ();
7348 initialize_tdesc_powerpc_403 ();
7349 initialize_tdesc_powerpc_403gc ();
7350 initialize_tdesc_powerpc_405 ();
7351 initialize_tdesc_powerpc_505 ();
7352 initialize_tdesc_powerpc_601 ();
7353 initialize_tdesc_powerpc_602 ();
7354 initialize_tdesc_powerpc_603 ();
7355 initialize_tdesc_powerpc_604 ();
7356 initialize_tdesc_powerpc_64 ();
7357 initialize_tdesc_powerpc_altivec64 ();
7358 initialize_tdesc_powerpc_vsx64 ();
7359 initialize_tdesc_powerpc_7400 ();
7360 initialize_tdesc_powerpc_750 ();
7361 initialize_tdesc_powerpc_860 ();
7362 initialize_tdesc_powerpc_e500 ();
7363 initialize_tdesc_rs6000 ();
7365 /* Add root prefix command for all "set powerpc"/"show powerpc"
7367 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
7368 _("Various PowerPC-specific commands."),
7369 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
7371 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
7372 _("Various PowerPC-specific commands."),
7373 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
7375 /* Add a command to allow the user to force the ABI. */
7376 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
7377 &powerpc_soft_float_global
,
7378 _("Set whether to use a soft-float ABI."),
7379 _("Show whether to use a soft-float ABI."),
7381 powerpc_set_soft_float
, NULL
,
7382 &setpowerpccmdlist
, &showpowerpccmdlist
);
7384 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
7385 &powerpc_vector_abi_string
,
7386 _("Set the vector ABI."),
7387 _("Show the vector ABI."),
7388 NULL
, powerpc_set_vector_abi
, NULL
,
7389 &setpowerpccmdlist
, &showpowerpccmdlist
);
7391 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
7392 &target_exact_watchpoints
,
7394 Set whether to use just one debug register for watchpoints on scalars."),
7396 Show whether to use just one debug register for watchpoints on scalars."),
7398 If true, GDB will use only one debug register when watching a variable of\n\
7399 scalar type, thus assuming that the variable is accessed through the address\n\
7400 of its first byte."),
7401 NULL
, show_powerpc_exact_watchpoints
,
7402 &setpowerpccmdlist
, &showpowerpccmdlist
);