1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* Holds the current set of options to be passed to the disassembler. */
110 static char *powerpc_disassembler_options
;
112 /* The list of available "set powerpc ..." and "show powerpc ..."
114 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
115 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
117 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
119 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
120 static const char *const powerpc_vector_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
131 static const char *powerpc_vector_abi_string
= "auto";
133 /* To be used by skip_prologue. */
135 struct rs6000_framedata
137 int offset
; /* total size of frame --- the distance
138 by which we decrement sp to allocate
140 int saved_gpr
; /* smallest # of saved gpr */
141 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
142 int saved_fpr
; /* smallest # of saved fpr */
143 int saved_vr
; /* smallest # of saved vr */
144 int saved_ev
; /* smallest # of saved ev */
145 int alloca_reg
; /* alloca register number (frame ptr) */
146 char frameless
; /* true if frameless functions. */
147 char nosavedpc
; /* true if pc not saved. */
148 char used_bl
; /* true if link register clobbered */
149 int gpr_offset
; /* offset of saved gprs from prev sp */
150 int fpr_offset
; /* offset of saved fprs from prev sp */
151 int vr_offset
; /* offset of saved vrs from prev sp */
152 int ev_offset
; /* offset of saved evs from prev sp */
153 int lr_offset
; /* offset of saved lr */
154 int lr_register
; /* register of saved lr, if trustworthy */
155 int cr_offset
; /* offset of saved cr */
156 int vrsave_offset
; /* offset of saved vrsave register */
160 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
162 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
165 if (tdep
->ppc_vsr0_regnum
< 0)
168 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
169 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
172 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
174 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
177 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
180 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
184 /* Return true if REGNO is an SPE register, false otherwise. */
186 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
190 /* Is it a reference to EV0 -- EV31, and do we have those? */
191 if (IS_SPE_PSEUDOREG (tdep
, regno
))
194 /* Is it a reference to one of the raw upper GPR halves? */
195 if (tdep
->ppc_ev0_upper_regnum
>= 0
196 && tdep
->ppc_ev0_upper_regnum
<= regno
197 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
200 /* Is it a reference to the 64-bit accumulator, and do we have that? */
201 if (tdep
->ppc_acc_regnum
>= 0
202 && tdep
->ppc_acc_regnum
== regno
)
205 /* Is it a reference to the SPE floating-point status and control register,
206 and do we have that? */
207 if (tdep
->ppc_spefscr_regnum
>= 0
208 && tdep
->ppc_spefscr_regnum
== regno
)
215 /* Return non-zero if the architecture described by GDBARCH has
216 floating-point registers (f0 --- f31 and fpscr). */
218 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 return (tdep
->ppc_fp0_regnum
>= 0
223 && tdep
->ppc_fpscr_regnum
>= 0);
226 /* Return non-zero if the architecture described by GDBARCH has
227 VSX registers (vsr0 --- vsr63). */
229 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
233 return tdep
->ppc_vsr0_regnum
>= 0;
236 /* Return non-zero if the architecture described by GDBARCH has
237 Altivec registers (vr0 --- vr31, vrsave and vscr). */
239 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
243 return (tdep
->ppc_vr0_regnum
>= 0
244 && tdep
->ppc_vrsave_regnum
>= 0);
247 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
250 This is a helper function for init_sim_regno_table, constructing
251 the table mapping GDB register numbers to sim register numbers; we
252 initialize every element in that table to -1 before we start
255 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
257 /* Make sure we don't try to assign any given GDB register a sim
258 register number more than once. */
259 gdb_assert (table
[gdb_regno
] == -1);
260 table
[gdb_regno
] = sim_regno
;
264 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
265 numbers to simulator register numbers, based on the values placed
266 in the ARCH->tdep->ppc_foo_regnum members. */
268 init_sim_regno_table (struct gdbarch
*arch
)
270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
271 int total_regs
= gdbarch_num_regs (arch
);
272 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
274 static const char *const segment_regs
[] = {
275 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
276 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
279 /* Presume that all registers not explicitly mentioned below are
280 unavailable from the sim. */
281 for (i
= 0; i
< total_regs
; i
++)
284 /* General-purpose registers. */
285 for (i
= 0; i
< ppc_num_gprs
; i
++)
286 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
288 /* Floating-point registers. */
289 if (tdep
->ppc_fp0_regnum
>= 0)
290 for (i
= 0; i
< ppc_num_fprs
; i
++)
291 set_sim_regno (sim_regno
,
292 tdep
->ppc_fp0_regnum
+ i
,
293 sim_ppc_f0_regnum
+ i
);
294 if (tdep
->ppc_fpscr_regnum
>= 0)
295 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
297 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
298 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
299 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
301 /* Segment registers. */
302 for (i
= 0; i
< ppc_num_srs
; i
++)
306 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
308 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
311 /* Altivec registers. */
312 if (tdep
->ppc_vr0_regnum
>= 0)
314 for (i
= 0; i
< ppc_num_vrs
; i
++)
315 set_sim_regno (sim_regno
,
316 tdep
->ppc_vr0_regnum
+ i
,
317 sim_ppc_vr0_regnum
+ i
);
319 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
320 we can treat this more like the other cases. */
321 set_sim_regno (sim_regno
,
322 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
323 sim_ppc_vscr_regnum
);
325 /* vsave is a special-purpose register, so the code below handles it. */
327 /* SPE APU (E500) registers. */
328 if (tdep
->ppc_ev0_upper_regnum
>= 0)
329 for (i
= 0; i
< ppc_num_gprs
; i
++)
330 set_sim_regno (sim_regno
,
331 tdep
->ppc_ev0_upper_regnum
+ i
,
332 sim_ppc_rh0_regnum
+ i
);
333 if (tdep
->ppc_acc_regnum
>= 0)
334 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
335 /* spefscr is a special-purpose register, so the code below handles it. */
338 /* Now handle all special-purpose registers. Verify that they
339 haven't mistakenly been assigned numbers by any of the above
341 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
343 const char *spr_name
= sim_spr_register_name (i
);
346 if (spr_name
!= NULL
)
347 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
350 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
354 /* Drop the initialized array into place. */
355 tdep
->sim_regno
= sim_regno
;
359 /* Given a GDB register number REG, return the corresponding SIM
362 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
364 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
367 if (tdep
->sim_regno
== NULL
)
368 init_sim_regno_table (gdbarch
);
371 && reg
<= gdbarch_num_regs (gdbarch
)
372 + gdbarch_num_pseudo_regs (gdbarch
));
373 sim_regno
= tdep
->sim_regno
[reg
];
378 return LEGACY_SIM_REGNO_IGNORE
;
383 /* Register set support functions. */
385 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
386 Write the register to REGCACHE. */
389 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
390 const gdb_byte
*regs
, size_t offset
, int regsize
)
392 if (regnum
!= -1 && offset
!= -1)
396 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
397 int gdb_regsize
= register_size (gdbarch
, regnum
);
398 if (gdb_regsize
< regsize
399 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
400 offset
+= regsize
- gdb_regsize
;
402 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
406 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
407 in a field REGSIZE wide. Zero pad as necessary. */
410 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
411 gdb_byte
*regs
, size_t offset
, int regsize
)
413 if (regnum
!= -1 && offset
!= -1)
417 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
418 int gdb_regsize
= register_size (gdbarch
, regnum
);
419 if (gdb_regsize
< regsize
)
421 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
423 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
424 offset
+= regsize
- gdb_regsize
;
427 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
428 regsize
- gdb_regsize
);
431 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
436 ppc_greg_offset (struct gdbarch
*gdbarch
,
437 struct gdbarch_tdep
*tdep
,
438 const struct ppc_reg_offsets
*offsets
,
442 *regsize
= offsets
->gpr_size
;
443 if (regnum
>= tdep
->ppc_gp0_regnum
444 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
445 return (offsets
->r0_offset
446 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
448 if (regnum
== gdbarch_pc_regnum (gdbarch
))
449 return offsets
->pc_offset
;
451 if (regnum
== tdep
->ppc_ps_regnum
)
452 return offsets
->ps_offset
;
454 if (regnum
== tdep
->ppc_lr_regnum
)
455 return offsets
->lr_offset
;
457 if (regnum
== tdep
->ppc_ctr_regnum
)
458 return offsets
->ctr_offset
;
460 *regsize
= offsets
->xr_size
;
461 if (regnum
== tdep
->ppc_cr_regnum
)
462 return offsets
->cr_offset
;
464 if (regnum
== tdep
->ppc_xer_regnum
)
465 return offsets
->xer_offset
;
467 if (regnum
== tdep
->ppc_mq_regnum
)
468 return offsets
->mq_offset
;
474 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
475 const struct ppc_reg_offsets
*offsets
,
478 if (regnum
>= tdep
->ppc_fp0_regnum
479 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
480 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
482 if (regnum
== tdep
->ppc_fpscr_regnum
)
483 return offsets
->fpscr_offset
;
489 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
490 const struct ppc_reg_offsets
*offsets
,
493 if (regnum
>= tdep
->ppc_vr0_regnum
494 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
495 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
497 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
498 return offsets
->vscr_offset
;
500 if (regnum
== tdep
->ppc_vrsave_regnum
)
501 return offsets
->vrsave_offset
;
506 /* Supply register REGNUM in the general-purpose register set REGSET
507 from the buffer specified by GREGS and LEN to register cache
508 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
511 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
512 int regnum
, const void *gregs
, size_t len
)
514 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
516 const struct ppc_reg_offsets
*offsets
517 = (const struct ppc_reg_offsets
*) regset
->regmap
;
524 int gpr_size
= offsets
->gpr_size
;
526 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
527 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
528 i
++, offset
+= gpr_size
)
529 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
532 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
533 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
535 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
536 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
537 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
538 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
539 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
540 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
541 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
543 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
544 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
546 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
547 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
552 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
553 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
556 /* Supply register REGNUM in the floating-point register set REGSET
557 from the buffer specified by FPREGS and LEN to register cache
558 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
561 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
562 int regnum
, const void *fpregs
, size_t len
)
564 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
565 struct gdbarch_tdep
*tdep
;
566 const struct ppc_reg_offsets
*offsets
;
569 if (!ppc_floating_point_unit_p (gdbarch
))
572 tdep
= gdbarch_tdep (gdbarch
);
573 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
578 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
579 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
581 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
583 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
584 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
585 offsets
->fpscr_size
);
589 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
590 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
591 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
594 /* Supply register REGNUM in the VSX register set REGSET
595 from the buffer specified by VSXREGS and LEN to register cache
596 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
599 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
600 int regnum
, const void *vsxregs
, size_t len
)
602 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
603 struct gdbarch_tdep
*tdep
;
605 if (!ppc_vsx_support_p (gdbarch
))
608 tdep
= gdbarch_tdep (gdbarch
);
614 for (i
= tdep
->ppc_vsr0_upper_regnum
;
615 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
617 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vsxregs
, 0, 8);
622 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vsxregs
, 0, 8);
625 /* Supply register REGNUM in the Altivec register set REGSET
626 from the buffer specified by VRREGS and LEN to register cache
627 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
630 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
631 int regnum
, const void *vrregs
, size_t len
)
633 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
634 struct gdbarch_tdep
*tdep
;
635 const struct ppc_reg_offsets
*offsets
;
638 if (!ppc_altivec_support_p (gdbarch
))
641 tdep
= gdbarch_tdep (gdbarch
);
642 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
647 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
648 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
650 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vrregs
, offset
, 16);
652 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
653 (const gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
655 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
656 (const gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
660 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
661 if (regnum
!= tdep
->ppc_vrsave_regnum
662 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
663 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vrregs
, offset
, 16);
665 ppc_supply_reg (regcache
, regnum
,
666 (const gdb_byte
*) vrregs
, offset
, 4);
669 /* Collect register REGNUM in the general-purpose register set
670 REGSET from register cache REGCACHE into the buffer specified by
671 GREGS and LEN. If REGNUM is -1, do this for all registers in
675 ppc_collect_gregset (const struct regset
*regset
,
676 const struct regcache
*regcache
,
677 int regnum
, void *gregs
, size_t len
)
679 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
681 const struct ppc_reg_offsets
*offsets
682 = (const struct ppc_reg_offsets
*) regset
->regmap
;
689 int gpr_size
= offsets
->gpr_size
;
691 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
692 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
693 i
++, offset
+= gpr_size
)
694 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
696 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
697 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
698 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
699 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
700 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
701 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
702 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
703 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
704 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
705 (gdb_byte
*) gregs
, offsets
->cr_offset
,
707 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
708 (gdb_byte
*) gregs
, offsets
->xer_offset
,
710 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
711 (gdb_byte
*) gregs
, offsets
->mq_offset
,
716 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
717 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
720 /* Collect register REGNUM in the floating-point register set
721 REGSET from register cache REGCACHE into the buffer specified by
722 FPREGS and LEN. If REGNUM is -1, do this for all registers in
726 ppc_collect_fpregset (const struct regset
*regset
,
727 const struct regcache
*regcache
,
728 int regnum
, void *fpregs
, size_t len
)
730 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
731 struct gdbarch_tdep
*tdep
;
732 const struct ppc_reg_offsets
*offsets
;
735 if (!ppc_floating_point_unit_p (gdbarch
))
738 tdep
= gdbarch_tdep (gdbarch
);
739 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
744 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
745 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
747 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
749 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
750 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
751 offsets
->fpscr_size
);
755 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
756 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
757 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
760 /* Collect register REGNUM in the VSX register set
761 REGSET from register cache REGCACHE into the buffer specified by
762 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
766 ppc_collect_vsxregset (const struct regset
*regset
,
767 const struct regcache
*regcache
,
768 int regnum
, void *vsxregs
, size_t len
)
770 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
771 struct gdbarch_tdep
*tdep
;
773 if (!ppc_vsx_support_p (gdbarch
))
776 tdep
= gdbarch_tdep (gdbarch
);
782 for (i
= tdep
->ppc_vsr0_upper_regnum
;
783 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
785 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vsxregs
, 0, 8);
790 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vsxregs
, 0, 8);
794 /* Collect register REGNUM in the Altivec register set
795 REGSET from register cache REGCACHE into the buffer specified by
796 VRREGS and LEN. If REGNUM is -1, do this for all registers in
800 ppc_collect_vrregset (const struct regset
*regset
,
801 const struct regcache
*regcache
,
802 int regnum
, void *vrregs
, size_t len
)
804 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
805 struct gdbarch_tdep
*tdep
;
806 const struct ppc_reg_offsets
*offsets
;
809 if (!ppc_altivec_support_p (gdbarch
))
812 tdep
= gdbarch_tdep (gdbarch
);
813 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
818 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
819 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
821 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vrregs
, offset
, 16);
823 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
824 (gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
826 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
827 (gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
831 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
832 if (regnum
!= tdep
->ppc_vrsave_regnum
833 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
834 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vrregs
, offset
, 16);
836 ppc_collect_reg (regcache
, regnum
,
837 (gdb_byte
*) vrregs
, offset
, 4);
842 insn_changes_sp_or_jumps (unsigned long insn
)
844 int opcode
= (insn
>> 26) & 0x03f;
845 int sd
= (insn
>> 21) & 0x01f;
846 int a
= (insn
>> 16) & 0x01f;
847 int subcode
= (insn
>> 1) & 0x3ff;
849 /* Changes the stack pointer. */
851 /* NOTE: There are many ways to change the value of a given register.
852 The ways below are those used when the register is R1, the SP,
853 in a funtion's epilogue. */
855 if (opcode
== 31 && subcode
== 444 && a
== 1)
856 return 1; /* mr R1,Rn */
857 if (opcode
== 14 && sd
== 1)
858 return 1; /* addi R1,Rn,simm */
859 if (opcode
== 58 && sd
== 1)
860 return 1; /* ld R1,ds(Rn) */
862 /* Transfers control. */
868 if (opcode
== 19 && subcode
== 16)
870 if (opcode
== 19 && subcode
== 528)
871 return 1; /* bcctr */
876 /* Return true if we are in the function's epilogue, i.e. after the
877 instruction that destroyed the function's stack frame.
879 1) scan forward from the point of execution:
880 a) If you find an instruction that modifies the stack pointer
881 or transfers control (except a return), execution is not in
883 b) Stop scanning if you find a return instruction or reach the
884 end of the function or reach the hard limit for the size of
886 2) scan backward from the point of execution:
887 a) If you find an instruction that modifies the stack pointer,
888 execution *is* in an epilogue, return.
889 b) Stop scanning if you reach an instruction that transfers
890 control or the beginning of the function or reach the hard
891 limit for the size of an epilogue. */
894 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
895 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
897 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
898 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
899 bfd_byte insn_buf
[PPC_INSN_SIZE
];
900 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
903 /* Find the search limits based on function boundaries and hard limit. */
905 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
908 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
909 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
911 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
912 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
914 /* Scan forward until next 'blr'. */
916 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
918 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
920 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
921 if (insn
== 0x4e800020)
923 /* Assume a bctr is a tail call unless it points strictly within
925 if (insn
== 0x4e800420)
927 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
928 tdep
->ppc_ctr_regnum
);
929 if (ctr
> func_start
&& ctr
< func_end
)
934 if (insn_changes_sp_or_jumps (insn
))
938 /* Scan backward until adjustment to stack pointer (R1). */
940 for (scan_pc
= pc
- PPC_INSN_SIZE
;
941 scan_pc
>= epilogue_start
;
942 scan_pc
-= PPC_INSN_SIZE
)
944 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
946 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
947 if (insn_changes_sp_or_jumps (insn
))
954 /* Implement the stack_frame_destroyed_p gdbarch method. */
957 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
959 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
963 /* Get the ith function argument for the current function. */
965 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
968 return get_frame_register_unsigned (frame
, 3 + argi
);
971 /* Sequence of bytes for breakpoint instruction. */
973 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
974 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
976 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
979 /* Instruction masks for displaced stepping. */
980 #define BRANCH_MASK 0xfc000000
981 #define BP_MASK 0xFC0007FE
982 #define B_INSN 0x48000000
983 #define BC_INSN 0x40000000
984 #define BXL_INSN 0x4c000000
985 #define BP_INSN 0x7C000008
987 /* Instruction masks used during single-stepping of atomic
989 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
990 #define LWARX_INSTRUCTION 0x7c000028
991 #define LDARX_INSTRUCTION 0x7c0000A8
992 #define LBARX_INSTRUCTION 0x7c000068
993 #define LHARX_INSTRUCTION 0x7c0000e8
994 #define LQARX_INSTRUCTION 0x7c000228
995 #define STORE_CONDITIONAL_MASK 0xfc0007ff
996 #define STWCX_INSTRUCTION 0x7c00012d
997 #define STDCX_INSTRUCTION 0x7c0001ad
998 #define STBCX_INSTRUCTION 0x7c00056d
999 #define STHCX_INSTRUCTION 0x7c0005ad
1000 #define STQCX_INSTRUCTION 0x7c00016d
1002 /* Check if insn is one of the Load And Reserve instructions used for atomic
1004 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
1005 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
1006 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
1007 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
1008 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
1009 /* Check if insn is one of the Store Conditional instructions used for atomic
1011 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
1012 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
1013 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
1014 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
1015 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
1017 /* We can't displaced step atomic sequences. Otherwise this is just
1018 like simple_displaced_step_copy_insn. */
1020 static struct displaced_step_closure
*
1021 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1022 CORE_ADDR from
, CORE_ADDR to
,
1023 struct regcache
*regs
)
1025 size_t len
= gdbarch_max_insn_length (gdbarch
);
1026 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
);
1027 struct cleanup
*old_chain
= make_cleanup (xfree
, buf
);
1028 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1031 read_memory (from
, buf
, len
);
1033 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
1035 /* Assume all atomic sequences start with a Load and Reserve instruction. */
1036 if (IS_LOAD_AND_RESERVE_INSN (insn
))
1038 if (debug_displaced
)
1040 fprintf_unfiltered (gdb_stdlog
,
1041 "displaced: can't displaced step "
1042 "atomic sequence at %s\n",
1043 paddress (gdbarch
, from
));
1045 do_cleanups (old_chain
);
1049 write_memory (to
, buf
, len
);
1051 if (debug_displaced
)
1053 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1054 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1055 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1058 discard_cleanups (old_chain
);
1059 return (struct displaced_step_closure
*) buf
;
1062 /* Fix up the state of registers and memory after having single-stepped
1063 a displaced instruction. */
1065 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
1066 struct displaced_step_closure
*closure
,
1067 CORE_ADDR from
, CORE_ADDR to
,
1068 struct regcache
*regs
)
1070 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1071 /* Our closure is a copy of the instruction. */
1072 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
1073 PPC_INSN_SIZE
, byte_order
);
1074 ULONGEST opcode
= 0;
1075 /* Offset for non PC-relative instructions. */
1076 LONGEST offset
= PPC_INSN_SIZE
;
1078 opcode
= insn
& BRANCH_MASK
;
1080 if (debug_displaced
)
1081 fprintf_unfiltered (gdb_stdlog
,
1082 "displaced: (ppc) fixup (%s, %s)\n",
1083 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1086 /* Handle PC-relative branch instructions. */
1087 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1089 ULONGEST current_pc
;
1091 /* Read the current PC value after the instruction has been executed
1092 in a displaced location. Calculate the offset to be applied to the
1093 original PC value before the displaced stepping. */
1094 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1096 offset
= current_pc
- to
;
1098 if (opcode
!= BXL_INSN
)
1100 /* Check for AA bit indicating whether this is an absolute
1101 addressing or PC-relative (1: absolute, 0: relative). */
1104 /* PC-relative addressing is being used in the branch. */
1105 if (debug_displaced
)
1108 "displaced: (ppc) branch instruction: %s\n"
1109 "displaced: (ppc) adjusted PC from %s to %s\n",
1110 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1111 paddress (gdbarch
, from
+ offset
));
1113 regcache_cooked_write_unsigned (regs
,
1114 gdbarch_pc_regnum (gdbarch
),
1120 /* If we're here, it means we have a branch to LR or CTR. If the
1121 branch was taken, the offset is probably greater than 4 (the next
1122 instruction), so it's safe to assume that an offset of 4 means we
1123 did not take the branch. */
1124 if (offset
== PPC_INSN_SIZE
)
1125 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1126 from
+ PPC_INSN_SIZE
);
1129 /* Check for LK bit indicating whether we should set the link
1130 register to point to the next instruction
1131 (1: Set, 0: Don't set). */
1134 /* Link register needs to be set to the next instruction's PC. */
1135 regcache_cooked_write_unsigned (regs
,
1136 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1137 from
+ PPC_INSN_SIZE
);
1138 if (debug_displaced
)
1139 fprintf_unfiltered (gdb_stdlog
,
1140 "displaced: (ppc) adjusted LR to %s\n",
1141 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1145 /* Check for breakpoints in the inferior. If we've found one, place the PC
1146 right at the breakpoint instruction. */
1147 else if ((insn
& BP_MASK
) == BP_INSN
)
1148 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1150 /* Handle any other instructions that do not fit in the categories above. */
1151 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1155 /* Always use hardware single-stepping to execute the
1156 displaced instruction. */
1158 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1159 struct displaced_step_closure
*closure
)
1164 /* Checks for an atomic sequence of instructions beginning with a
1165 Load And Reserve instruction and ending with a Store Conditional
1166 instruction. If such a sequence is found, attempt to step through it.
1167 A breakpoint is placed at the end of the sequence. */
1168 std::vector
<CORE_ADDR
>
1169 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1171 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1172 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1173 CORE_ADDR pc
= regcache_read_pc (regcache
);
1174 CORE_ADDR breaks
[2] = {-1, -1};
1176 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1177 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1180 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1181 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1182 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1184 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1185 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1188 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1190 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1192 loc
+= PPC_INSN_SIZE
;
1193 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1195 /* Assume that there is at most one conditional branch in the atomic
1196 sequence. If a conditional branch is found, put a breakpoint in
1197 its destination address. */
1198 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1200 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1201 int absolute
= insn
& 2;
1203 if (bc_insn_count
>= 1)
1204 return {}; /* More than one conditional branch found, fallback
1205 to the standard single-step code. */
1208 breaks
[1] = immediate
;
1210 breaks
[1] = loc
+ immediate
;
1216 if (IS_STORE_CONDITIONAL_INSN (insn
))
1220 /* Assume that the atomic sequence ends with a Store Conditional
1222 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1226 loc
+= PPC_INSN_SIZE
;
1227 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1229 /* Insert a breakpoint right after the end of the atomic sequence. */
1232 /* Check for duplicated breakpoints. Check also for a breakpoint
1233 placed (branch instruction's destination) anywhere in sequence. */
1235 && (breaks
[1] == breaks
[0]
1236 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1237 last_breakpoint
= 0;
1239 std::vector
<CORE_ADDR
> next_pcs
;
1241 for (index
= 0; index
<= last_breakpoint
; index
++)
1242 next_pcs
.push_back (breaks
[index
]);
1248 #define SIGNED_SHORT(x) \
1249 ((sizeof (short) == 2) \
1250 ? ((int)(short)(x)) \
1251 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1253 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1255 /* Limit the number of skipped non-prologue instructions, as the examining
1256 of the prologue is expensive. */
1257 static int max_skip_non_prologue_insns
= 10;
1259 /* Return nonzero if the given instruction OP can be part of the prologue
1260 of a function and saves a parameter on the stack. FRAMEP should be
1261 set if one of the previous instructions in the function has set the
1265 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1267 /* Move parameters from argument registers to temporary register. */
1268 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1270 /* Rx must be scratch register r0. */
1271 const int rx_regno
= (op
>> 16) & 31;
1272 /* Ry: Only r3 - r10 are used for parameter passing. */
1273 const int ry_regno
= GET_SRC_REG (op
);
1275 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1277 *r0_contains_arg
= 1;
1284 /* Save a General Purpose Register on stack. */
1286 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1287 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1289 /* Rx: Only r3 - r10 are used for parameter passing. */
1290 const int rx_regno
= GET_SRC_REG (op
);
1292 return (rx_regno
>= 3 && rx_regno
<= 10);
1295 /* Save a General Purpose Register on stack via the Frame Pointer. */
1298 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1299 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1300 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1302 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1303 However, the compiler sometimes uses r0 to hold an argument. */
1304 const int rx_regno
= GET_SRC_REG (op
);
1306 return ((rx_regno
>= 3 && rx_regno
<= 10)
1307 || (rx_regno
== 0 && *r0_contains_arg
));
1310 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1312 /* Only f2 - f8 are used for parameter passing. */
1313 const int src_regno
= GET_SRC_REG (op
);
1315 return (src_regno
>= 2 && src_regno
<= 8);
1318 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1320 /* Only f2 - f8 are used for parameter passing. */
1321 const int src_regno
= GET_SRC_REG (op
);
1323 return (src_regno
>= 2 && src_regno
<= 8);
1326 /* Not an insn that saves a parameter on stack. */
1330 /* Assuming that INSN is a "bl" instruction located at PC, return
1331 nonzero if the destination of the branch is a "blrl" instruction.
1333 This sequence is sometimes found in certain function prologues.
1334 It allows the function to load the LR register with a value that
1335 they can use to access PIC data using PC-relative offsets. */
1338 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1345 absolute
= (int) ((insn
>> 1) & 1);
1346 immediate
= ((insn
& ~3) << 6) >> 6;
1350 dest
= pc
+ immediate
;
1352 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1353 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1359 /* Masks for decoding a branch-and-link (bl) instruction.
1361 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1362 The former is anded with the opcode in question; if the result of
1363 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1364 question is a ``bl'' instruction.
1366 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1367 the branch displacement. */
1369 #define BL_MASK 0xfc000001
1370 #define BL_INSTRUCTION 0x48000001
1371 #define BL_DISPLACEMENT_MASK 0x03fffffc
1373 static unsigned long
1374 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1376 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1380 /* Fetch the instruction and convert it to an integer. */
1381 if (target_read_memory (pc
, buf
, 4))
1383 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1388 /* GCC generates several well-known sequences of instructions at the begining
1389 of each function prologue when compiling with -fstack-check. If one of
1390 such sequences starts at START_PC, then return the address of the
1391 instruction immediately past this sequence. Otherwise, return START_PC. */
1394 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1396 CORE_ADDR pc
= start_pc
;
1397 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1399 /* First possible sequence: A small number of probes.
1400 stw 0, -<some immediate>(1)
1401 [repeat this instruction any (small) number of times]. */
1403 if ((op
& 0xffff0000) == 0x90010000)
1405 while ((op
& 0xffff0000) == 0x90010000)
1408 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1413 /* Second sequence: A probing loop.
1414 addi 12,1,-<some immediate>
1415 lis 0,-<some immediate>
1416 [possibly ori 0,0,<some immediate>]
1420 addi 12,12,-<some immediate>
1423 [possibly one last probe: stw 0,<some immediate>(12)]. */
1427 /* addi 12,1,-<some immediate> */
1428 if ((op
& 0xffff0000) != 0x39810000)
1431 /* lis 0,-<some immediate> */
1433 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1434 if ((op
& 0xffff0000) != 0x3c000000)
1438 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1439 /* [possibly ori 0,0,<some immediate>] */
1440 if ((op
& 0xffff0000) == 0x60000000)
1443 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1446 if (op
!= 0x7c0c0214)
1451 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1452 if (op
!= 0x7c0c0000)
1457 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1458 if ((op
& 0xff9f0001) != 0x41820000)
1461 /* addi 12,12,-<some immediate> */
1463 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1464 if ((op
& 0xffff0000) != 0x398c0000)
1469 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1470 if (op
!= 0x900c0000)
1475 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1476 if ((op
& 0xfc000001) != 0x48000000)
1479 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1481 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1482 if ((op
& 0xffff0000) == 0x900c0000)
1485 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1488 /* We found a valid stack-check sequence, return the new PC. */
1492 /* Third sequence: No probe; instead, a comparizon between the stack size
1493 limit (saved in a run-time global variable) and the current stack
1496 addi 0,1,-<some immediate>
1497 lis 12,__gnat_stack_limit@ha
1498 lwz 12,__gnat_stack_limit@l(12)
1501 or, with a small variant in the case of a bigger stack frame:
1502 addis 0,1,<some immediate>
1503 addic 0,0,-<some immediate>
1504 lis 12,__gnat_stack_limit@ha
1505 lwz 12,__gnat_stack_limit@l(12)
1510 /* addi 0,1,-<some immediate> */
1511 if ((op
& 0xffff0000) != 0x38010000)
1513 /* small stack frame variant not recognized; try the
1514 big stack frame variant: */
1516 /* addis 0,1,<some immediate> */
1517 if ((op
& 0xffff0000) != 0x3c010000)
1520 /* addic 0,0,-<some immediate> */
1522 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1523 if ((op
& 0xffff0000) != 0x30000000)
1527 /* lis 12,<some immediate> */
1529 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1530 if ((op
& 0xffff0000) != 0x3d800000)
1533 /* lwz 12,<some immediate>(12) */
1535 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1536 if ((op
& 0xffff0000) != 0x818c0000)
1541 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1542 if ((op
& 0xfffffffe) != 0x7c406008)
1545 /* We found a valid stack-check sequence, return the new PC. */
1549 /* No stack check code in our prologue, return the start_pc. */
1553 /* return pc value after skipping a function prologue and also return
1554 information about a function frame.
1556 in struct rs6000_framedata fdata:
1557 - frameless is TRUE, if function does not have a frame.
1558 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1559 - offset is the initial size of this stack frame --- the amount by
1560 which we decrement the sp to allocate the frame.
1561 - saved_gpr is the number of the first saved gpr.
1562 - saved_fpr is the number of the first saved fpr.
1563 - saved_vr is the number of the first saved vr.
1564 - saved_ev is the number of the first saved ev.
1565 - alloca_reg is the number of the register used for alloca() handling.
1567 - gpr_offset is the offset of the first saved gpr from the previous frame.
1568 - fpr_offset is the offset of the first saved fpr from the previous frame.
1569 - vr_offset is the offset of the first saved vr from the previous frame.
1570 - ev_offset is the offset of the first saved ev from the previous frame.
1571 - lr_offset is the offset of the saved lr
1572 - cr_offset is the offset of the saved cr
1573 - vrsave_offset is the offset of the saved vrsave register. */
1576 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1577 struct rs6000_framedata
*fdata
)
1579 CORE_ADDR orig_pc
= pc
;
1580 CORE_ADDR last_prologue_pc
= pc
;
1581 CORE_ADDR li_found_pc
= 0;
1585 long vr_saved_offset
= 0;
1591 int vrsave_reg
= -1;
1594 int minimal_toc_loaded
= 0;
1595 int prev_insn_was_prologue_insn
= 1;
1596 int num_skip_non_prologue_insns
= 0;
1597 int r0_contains_arg
= 0;
1598 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1599 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1600 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1602 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1603 fdata
->saved_gpr
= -1;
1604 fdata
->saved_fpr
= -1;
1605 fdata
->saved_vr
= -1;
1606 fdata
->saved_ev
= -1;
1607 fdata
->alloca_reg
= -1;
1608 fdata
->frameless
= 1;
1609 fdata
->nosavedpc
= 1;
1610 fdata
->lr_register
= -1;
1612 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1618 /* Sometimes it isn't clear if an instruction is a prologue
1619 instruction or not. When we encounter one of these ambiguous
1620 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1621 Otherwise, we'll assume that it really is a prologue instruction. */
1622 if (prev_insn_was_prologue_insn
)
1623 last_prologue_pc
= pc
;
1625 /* Stop scanning if we've hit the limit. */
1629 prev_insn_was_prologue_insn
= 1;
1631 /* Fetch the instruction and convert it to an integer. */
1632 if (target_read_memory (pc
, buf
, 4))
1634 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1636 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1638 /* Since shared library / PIC code, which needs to get its
1639 address at runtime, can appear to save more than one link
1653 remember just the first one, but skip over additional
1656 lr_reg
= (op
& 0x03e00000) >> 21;
1658 r0_contains_arg
= 0;
1661 else if ((op
& 0xfc1fffff) == 0x7c000026)
1663 cr_reg
= (op
& 0x03e00000);
1665 r0_contains_arg
= 0;
1669 else if ((op
& 0xfc1f0000) == 0xd8010000)
1670 { /* stfd Rx,NUM(r1) */
1671 reg
= GET_SRC_REG (op
);
1672 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1674 fdata
->saved_fpr
= reg
;
1675 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1680 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1681 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1682 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1683 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1686 reg
= GET_SRC_REG (op
);
1687 if ((op
& 0xfc1f0000) == 0xbc010000)
1688 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1690 fdata
->gpr_mask
|= 1U << reg
;
1691 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1693 fdata
->saved_gpr
= reg
;
1694 if ((op
& 0xfc1f0003) == 0xf8010000)
1696 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1701 else if ((op
& 0xffff0000) == 0x3c4c0000
1702 || (op
& 0xffff0000) == 0x3c400000
1703 || (op
& 0xffff0000) == 0x38420000)
1705 /* . 0: addis 2,12,.TOC.-0b@ha
1706 . addi 2,2,.TOC.-0b@l
1710 used by ELFv2 global entry points to set up r2. */
1713 else if (op
== 0x60000000)
1716 /* Allow nops in the prologue, but do not consider them to
1717 be part of the prologue unless followed by other prologue
1719 prev_insn_was_prologue_insn
= 0;
1723 else if ((op
& 0xffff0000) == 0x3c000000)
1724 { /* addis 0,0,NUM, used for >= 32k frames */
1725 fdata
->offset
= (op
& 0x0000ffff) << 16;
1726 fdata
->frameless
= 0;
1727 r0_contains_arg
= 0;
1731 else if ((op
& 0xffff0000) == 0x60000000)
1732 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1733 fdata
->offset
|= (op
& 0x0000ffff);
1734 fdata
->frameless
= 0;
1735 r0_contains_arg
= 0;
1739 else if (lr_reg
>= 0 &&
1740 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1741 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1742 /* stw Rx, NUM(r1) */
1743 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1744 /* stwu Rx, NUM(r1) */
1745 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1746 { /* where Rx == lr */
1747 fdata
->lr_offset
= offset
;
1748 fdata
->nosavedpc
= 0;
1749 /* Invalidate lr_reg, but don't set it to -1.
1750 That would mean that it had never been set. */
1752 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1753 (op
& 0xfc000000) == 0x90000000) /* stw */
1755 /* Does not update r1, so add displacement to lr_offset. */
1756 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1761 else if (cr_reg
>= 0 &&
1762 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1763 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1764 /* stw Rx, NUM(r1) */
1765 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1766 /* stwu Rx, NUM(r1) */
1767 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1768 { /* where Rx == cr */
1769 fdata
->cr_offset
= offset
;
1770 /* Invalidate cr_reg, but don't set it to -1.
1771 That would mean that it had never been set. */
1773 if ((op
& 0xfc000003) == 0xf8000000 ||
1774 (op
& 0xfc000000) == 0x90000000)
1776 /* Does not update r1, so add displacement to cr_offset. */
1777 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1782 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1784 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1785 prediction bits. If the LR has already been saved, we can
1789 else if (op
== 0x48000005)
1796 else if (op
== 0x48000004)
1801 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1802 in V.4 -mminimal-toc */
1803 (op
& 0xffff0000) == 0x3bde0000)
1804 { /* addi 30,30,foo@l */
1808 else if ((op
& 0xfc000001) == 0x48000001)
1812 fdata
->frameless
= 0;
1814 /* If the return address has already been saved, we can skip
1815 calls to blrl (for PIC). */
1816 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1822 /* Don't skip over the subroutine call if it is not within
1823 the first three instructions of the prologue and either
1824 we have no line table information or the line info tells
1825 us that the subroutine call is not part of the line
1826 associated with the prologue. */
1827 if ((pc
- orig_pc
) > 8)
1829 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1830 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1832 if ((prologue_sal
.line
== 0)
1833 || (prologue_sal
.line
!= this_sal
.line
))
1837 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1839 /* At this point, make sure this is not a trampoline
1840 function (a function that simply calls another functions,
1841 and nothing else). If the next is not a nop, this branch
1842 was part of the function prologue. */
1844 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1845 break; /* Don't skip over
1851 /* update stack pointer */
1852 else if ((op
& 0xfc1f0000) == 0x94010000)
1853 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1854 fdata
->frameless
= 0;
1855 fdata
->offset
= SIGNED_SHORT (op
);
1856 offset
= fdata
->offset
;
1859 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1860 { /* stwux rX,r1,rY */
1861 /* No way to figure out what r1 is going to be. */
1862 fdata
->frameless
= 0;
1863 offset
= fdata
->offset
;
1866 else if ((op
& 0xfc1f0003) == 0xf8010001)
1867 { /* stdu rX,NUM(r1) */
1868 fdata
->frameless
= 0;
1869 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1870 offset
= fdata
->offset
;
1873 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1874 { /* stdux rX,r1,rY */
1875 /* No way to figure out what r1 is going to be. */
1876 fdata
->frameless
= 0;
1877 offset
= fdata
->offset
;
1880 else if ((op
& 0xffff0000) == 0x38210000)
1881 { /* addi r1,r1,SIMM */
1882 fdata
->frameless
= 0;
1883 fdata
->offset
+= SIGNED_SHORT (op
);
1884 offset
= fdata
->offset
;
1887 /* Load up minimal toc pointer. Do not treat an epilogue restore
1888 of r31 as a minimal TOC load. */
1889 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1890 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1892 && !minimal_toc_loaded
)
1894 minimal_toc_loaded
= 1;
1897 /* move parameters from argument registers to local variable
1900 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1901 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1902 (((op
>> 21) & 31) <= 10) &&
1903 ((long) ((op
>> 16) & 31)
1904 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1908 /* store parameters in stack */
1910 /* Move parameters from argument registers to temporary register. */
1911 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1915 /* Set up frame pointer */
1917 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1919 fdata
->frameless
= 0;
1921 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1924 /* Another way to set up the frame pointer. */
1926 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1927 || op
== 0x7c3f0b78)
1929 fdata
->frameless
= 0;
1931 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1934 /* Another way to set up the frame pointer. */
1936 else if ((op
& 0xfc1fffff) == 0x38010000)
1937 { /* addi rX, r1, 0x0 */
1938 fdata
->frameless
= 0;
1940 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1941 + ((op
& ~0x38010000) >> 21));
1944 /* AltiVec related instructions. */
1945 /* Store the vrsave register (spr 256) in another register for
1946 later manipulation, or load a register into the vrsave
1947 register. 2 instructions are used: mfvrsave and
1948 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1949 and mtspr SPR256, Rn. */
1950 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1951 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1952 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1954 vrsave_reg
= GET_SRC_REG (op
);
1957 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1961 /* Store the register where vrsave was saved to onto the stack:
1962 rS is the register where vrsave was stored in a previous
1964 /* 100100 sssss 00001 dddddddd dddddddd */
1965 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1967 if (vrsave_reg
== GET_SRC_REG (op
))
1969 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1974 /* Compute the new value of vrsave, by modifying the register
1975 where vrsave was saved to. */
1976 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1977 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1981 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1982 in a pair of insns to save the vector registers on the
1984 /* 001110 00000 00000 iiii iiii iiii iiii */
1985 /* 001110 01110 00000 iiii iiii iiii iiii */
1986 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1987 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1989 if ((op
& 0xffff0000) == 0x38000000)
1990 r0_contains_arg
= 0;
1992 vr_saved_offset
= SIGNED_SHORT (op
);
1994 /* This insn by itself is not part of the prologue, unless
1995 if part of the pair of insns mentioned above. So do not
1996 record this insn as part of the prologue yet. */
1997 prev_insn_was_prologue_insn
= 0;
1999 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
2000 /* 011111 sssss 11111 00000 00111001110 */
2001 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
2003 if (pc
== (li_found_pc
+ 4))
2005 vr_reg
= GET_SRC_REG (op
);
2006 /* If this is the first vector reg to be saved, or if
2007 it has a lower number than others previously seen,
2008 reupdate the frame info. */
2009 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
2011 fdata
->saved_vr
= vr_reg
;
2012 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2014 vr_saved_offset
= -1;
2019 /* End AltiVec related instructions. */
2021 /* Start BookE related instructions. */
2022 /* Store gen register S at (r31+uimm).
2023 Any register less than r13 is volatile, so we don't care. */
2024 /* 000100 sssss 11111 iiiii 01100100001 */
2025 else if (arch_info
->mach
== bfd_mach_ppc_e500
2026 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2028 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2031 ev_reg
= GET_SRC_REG (op
);
2032 imm
= (op
>> 11) & 0x1f;
2033 ev_offset
= imm
* 8;
2034 /* If this is the first vector reg to be saved, or if
2035 it has a lower number than others previously seen,
2036 reupdate the frame info. */
2037 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2039 fdata
->saved_ev
= ev_reg
;
2040 fdata
->ev_offset
= ev_offset
+ offset
;
2045 /* Store gen register rS at (r1+rB). */
2046 /* 000100 sssss 00001 bbbbb 01100100000 */
2047 else if (arch_info
->mach
== bfd_mach_ppc_e500
2048 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2050 if (pc
== (li_found_pc
+ 4))
2052 ev_reg
= GET_SRC_REG (op
);
2053 /* If this is the first vector reg to be saved, or if
2054 it has a lower number than others previously seen,
2055 reupdate the frame info. */
2056 /* We know the contents of rB from the previous instruction. */
2057 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2059 fdata
->saved_ev
= ev_reg
;
2060 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2062 vr_saved_offset
= -1;
2068 /* Store gen register r31 at (rA+uimm). */
2069 /* 000100 11111 aaaaa iiiii 01100100001 */
2070 else if (arch_info
->mach
== bfd_mach_ppc_e500
2071 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2073 /* Wwe know that the source register is 31 already, but
2074 it can't hurt to compute it. */
2075 ev_reg
= GET_SRC_REG (op
);
2076 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2077 /* If this is the first vector reg to be saved, or if
2078 it has a lower number than others previously seen,
2079 reupdate the frame info. */
2080 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2082 fdata
->saved_ev
= ev_reg
;
2083 fdata
->ev_offset
= ev_offset
+ offset
;
2088 /* Store gen register S at (r31+r0).
2089 Store param on stack when offset from SP bigger than 4 bytes. */
2090 /* 000100 sssss 11111 00000 01100100000 */
2091 else if (arch_info
->mach
== bfd_mach_ppc_e500
2092 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2094 if (pc
== (li_found_pc
+ 4))
2096 if ((op
& 0x03e00000) >= 0x01a00000)
2098 ev_reg
= GET_SRC_REG (op
);
2099 /* If this is the first vector reg to be saved, or if
2100 it has a lower number than others previously seen,
2101 reupdate the frame info. */
2102 /* We know the contents of r0 from the previous
2104 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2106 fdata
->saved_ev
= ev_reg
;
2107 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2111 vr_saved_offset
= -1;
2116 /* End BookE related instructions. */
2120 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2122 /* Not a recognized prologue instruction.
2123 Handle optimizer code motions into the prologue by continuing
2124 the search if we have no valid frame yet or if the return
2125 address is not yet saved in the frame. Also skip instructions
2126 if some of the GPRs expected to be saved are not yet saved. */
2127 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2128 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2131 if (op
== 0x4e800020 /* blr */
2132 || op
== 0x4e800420) /* bctr */
2133 /* Do not scan past epilogue in frameless functions or
2136 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2137 /* Never skip branches. */
2140 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2141 /* Do not scan too many insns, scanning insns is expensive with
2145 /* Continue scanning. */
2146 prev_insn_was_prologue_insn
= 0;
2152 /* I have problems with skipping over __main() that I need to address
2153 * sometime. Previously, I used to use misc_function_vector which
2154 * didn't work as well as I wanted to be. -MGO */
2156 /* If the first thing after skipping a prolog is a branch to a function,
2157 this might be a call to an initializer in main(), introduced by gcc2.
2158 We'd like to skip over it as well. Fortunately, xlc does some extra
2159 work before calling a function right after a prologue, thus we can
2160 single out such gcc2 behaviour. */
2163 if ((op
& 0xfc000001) == 0x48000001)
2164 { /* bl foo, an initializer function? */
2165 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2167 if (op
== 0x4def7b82)
2168 { /* cror 0xf, 0xf, 0xf (nop) */
2170 /* Check and see if we are in main. If so, skip over this
2171 initializer function as well. */
2173 tmp
= find_pc_misc_function (pc
);
2175 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2181 if (pc
== lim_pc
&& lr_reg
>= 0)
2182 fdata
->lr_register
= lr_reg
;
2184 fdata
->offset
= -fdata
->offset
;
2185 return last_prologue_pc
;
2189 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2191 struct rs6000_framedata frame
;
2192 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2194 /* See if we can determine the end of the prologue via the symbol table.
2195 If so, then return either PC, or the PC after the prologue, whichever
2197 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2199 CORE_ADDR post_prologue_pc
2200 = skip_prologue_using_sal (gdbarch
, func_addr
);
2201 if (post_prologue_pc
!= 0)
2202 return std::max (pc
, post_prologue_pc
);
2205 /* Can't determine prologue from the symbol table, need to examine
2208 /* Find an upper limit on the function prologue using the debug
2209 information. If the debug information could not be used to provide
2210 that bound, then use an arbitrary large number as the upper bound. */
2211 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2213 limit_pc
= pc
+ 100; /* Magic. */
2215 /* Do not allow limit_pc to be past the function end, if we know
2216 where that end is... */
2217 if (func_end_addr
&& limit_pc
> func_end_addr
)
2218 limit_pc
= func_end_addr
;
2220 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2224 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2225 in the prologue of main().
2227 The function below examines the code pointed at by PC and checks to
2228 see if it corresponds to a call to __eabi. If so, it returns the
2229 address of the instruction following that call. Otherwise, it simply
2233 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2235 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2239 if (target_read_memory (pc
, buf
, 4))
2241 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2243 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2245 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2246 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2247 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2249 /* We check for ___eabi (three leading underscores) in addition
2250 to __eabi in case the GCC option "-fleading-underscore" was
2251 used to compile the program. */
2252 if (s
.minsym
!= NULL
2253 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2254 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2255 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2261 /* All the ABI's require 16 byte alignment. */
2263 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2265 return (addr
& -16);
2268 /* Return whether handle_inferior_event() should proceed through code
2269 starting at PC in function NAME when stepping.
2271 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2272 handle memory references that are too distant to fit in instructions
2273 generated by the compiler. For example, if 'foo' in the following
2278 is greater than 32767, the linker might replace the lwz with a branch to
2279 somewhere in @FIX1 that does the load in 2 instructions and then branches
2280 back to where execution should continue.
2282 GDB should silently step over @FIX code, just like AIX dbx does.
2283 Unfortunately, the linker uses the "b" instruction for the
2284 branches, meaning that the link register doesn't get set.
2285 Therefore, GDB's usual step_over_function () mechanism won't work.
2287 Instead, use the gdbarch_skip_trampoline_code and
2288 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2292 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2293 CORE_ADDR pc
, const char *name
)
2295 return name
&& startswith (name
, "@FIX");
2298 /* Skip code that the user doesn't want to see when stepping:
2300 1. Indirect function calls use a piece of trampoline code to do context
2301 switching, i.e. to set the new TOC table. Skip such code if we are on
2302 its first instruction (as when we have single-stepped to here).
2304 2. Skip shared library trampoline code (which is different from
2305 indirect function call trampolines).
2307 3. Skip bigtoc fixup code.
2309 Result is desired PC to step until, or NULL if we are not in
2310 code that should be skipped. */
2313 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2315 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2317 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2318 unsigned int ii
, op
;
2320 CORE_ADDR solib_target_pc
;
2321 struct bound_minimal_symbol msymbol
;
2323 static unsigned trampoline_code
[] =
2325 0x800b0000, /* l r0,0x0(r11) */
2326 0x90410014, /* st r2,0x14(r1) */
2327 0x7c0903a6, /* mtctr r0 */
2328 0x804b0004, /* l r2,0x4(r11) */
2329 0x816b0008, /* l r11,0x8(r11) */
2330 0x4e800420, /* bctr */
2331 0x4e800020, /* br */
2335 /* Check for bigtoc fixup code. */
2336 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2338 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2339 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2341 /* Double-check that the third instruction from PC is relative "b". */
2342 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2343 if ((op
& 0xfc000003) == 0x48000000)
2345 /* Extract bits 6-29 as a signed 24-bit relative word address and
2346 add it to the containing PC. */
2347 rel
= ((int)(op
<< 6) >> 6);
2348 return pc
+ 8 + rel
;
2352 /* If pc is in a shared library trampoline, return its target. */
2353 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2354 if (solib_target_pc
)
2355 return solib_target_pc
;
2357 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2359 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2360 if (op
!= trampoline_code
[ii
])
2363 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2365 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2369 /* ISA-specific vector types. */
2371 static struct type
*
2372 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2374 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2376 if (!tdep
->ppc_builtin_type_vec64
)
2378 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2380 /* The type we're building is this: */
2382 union __gdb_builtin_type_vec64
2386 int32_t v2_int32
[2];
2387 int16_t v4_int16
[4];
2394 t
= arch_composite_type (gdbarch
,
2395 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2396 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2397 append_composite_type_field (t
, "v2_float",
2398 init_vector_type (bt
->builtin_float
, 2));
2399 append_composite_type_field (t
, "v2_int32",
2400 init_vector_type (bt
->builtin_int32
, 2));
2401 append_composite_type_field (t
, "v4_int16",
2402 init_vector_type (bt
->builtin_int16
, 4));
2403 append_composite_type_field (t
, "v8_int8",
2404 init_vector_type (bt
->builtin_int8
, 8));
2406 TYPE_VECTOR (t
) = 1;
2407 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2408 tdep
->ppc_builtin_type_vec64
= t
;
2411 return tdep
->ppc_builtin_type_vec64
;
2414 /* Vector 128 type. */
2416 static struct type
*
2417 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2421 if (!tdep
->ppc_builtin_type_vec128
)
2423 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2425 /* The type we're building is this
2427 type = union __ppc_builtin_type_vec128 {
2429 double v2_double[2];
2431 int32_t v4_int32[4];
2432 int16_t v8_int16[8];
2433 int8_t v16_int8[16];
2439 t
= arch_composite_type (gdbarch
,
2440 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2441 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2442 append_composite_type_field (t
, "v2_double",
2443 init_vector_type (bt
->builtin_double
, 2));
2444 append_composite_type_field (t
, "v4_float",
2445 init_vector_type (bt
->builtin_float
, 4));
2446 append_composite_type_field (t
, "v4_int32",
2447 init_vector_type (bt
->builtin_int32
, 4));
2448 append_composite_type_field (t
, "v8_int16",
2449 init_vector_type (bt
->builtin_int16
, 8));
2450 append_composite_type_field (t
, "v16_int8",
2451 init_vector_type (bt
->builtin_int8
, 16));
2453 TYPE_VECTOR (t
) = 1;
2454 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2455 tdep
->ppc_builtin_type_vec128
= t
;
2458 return tdep
->ppc_builtin_type_vec128
;
2461 /* Return the name of register number REGNO, or the empty string if it
2462 is an anonymous register. */
2465 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2469 /* The upper half "registers" have names in the XML description,
2470 but we present only the low GPRs and the full 64-bit registers
2472 if (tdep
->ppc_ev0_upper_regnum
>= 0
2473 && tdep
->ppc_ev0_upper_regnum
<= regno
2474 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2477 /* Hide the upper halves of the vs0~vs31 registers. */
2478 if (tdep
->ppc_vsr0_regnum
>= 0
2479 && tdep
->ppc_vsr0_upper_regnum
<= regno
2480 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2483 /* Check if the SPE pseudo registers are available. */
2484 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2486 static const char *const spe_regnames
[] = {
2487 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2488 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2489 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2490 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2492 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2495 /* Check if the decimal128 pseudo-registers are available. */
2496 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2498 static const char *const dfp128_regnames
[] = {
2499 "dl0", "dl1", "dl2", "dl3",
2500 "dl4", "dl5", "dl6", "dl7",
2501 "dl8", "dl9", "dl10", "dl11",
2502 "dl12", "dl13", "dl14", "dl15"
2504 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2507 /* Check if this is a VSX pseudo-register. */
2508 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2510 static const char *const vsx_regnames
[] = {
2511 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2512 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2513 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2514 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2515 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2516 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2517 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2518 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2519 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2521 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2524 /* Check if the this is a Extended FP pseudo-register. */
2525 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2527 static const char *const efpr_regnames
[] = {
2528 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2529 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2530 "f46", "f47", "f48", "f49", "f50", "f51",
2531 "f52", "f53", "f54", "f55", "f56", "f57",
2532 "f58", "f59", "f60", "f61", "f62", "f63"
2534 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2537 return tdesc_register_name (gdbarch
, regno
);
2540 /* Return the GDB type object for the "standard" data type of data in
2543 static struct type
*
2544 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2546 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2548 /* These are the only pseudo-registers we support. */
2549 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2550 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2551 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2552 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2554 /* These are the e500 pseudo-registers. */
2555 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2556 return rs6000_builtin_type_vec64 (gdbarch
);
2557 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2558 /* PPC decimal128 pseudo-registers. */
2559 return builtin_type (gdbarch
)->builtin_declong
;
2560 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2561 /* POWER7 VSX pseudo-registers. */
2562 return rs6000_builtin_type_vec128 (gdbarch
);
2564 /* POWER7 Extended FP pseudo-registers. */
2565 return builtin_type (gdbarch
)->builtin_double
;
2568 /* Is REGNUM a member of REGGROUP? */
2570 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2571 struct reggroup
*group
)
2573 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2575 /* These are the only pseudo-registers we support. */
2576 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2577 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2578 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2579 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2581 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2582 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2583 return group
== all_reggroup
|| group
== vector_reggroup
;
2585 /* PPC decimal128 or Extended FP pseudo-registers. */
2586 return group
== all_reggroup
|| group
== float_reggroup
;
2589 /* The register format for RS/6000 floating point registers is always
2590 double, we need a conversion if the memory format is float. */
2593 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2596 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2598 return (tdep
->ppc_fp0_regnum
>= 0
2599 && regnum
>= tdep
->ppc_fp0_regnum
2600 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2601 && TYPE_CODE (type
) == TYPE_CODE_FLT
2602 && TYPE_LENGTH (type
)
2603 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2607 rs6000_register_to_value (struct frame_info
*frame
,
2611 int *optimizedp
, int *unavailablep
)
2613 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2614 gdb_byte from
[MAX_REGISTER_SIZE
];
2616 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2618 if (!get_frame_register_bytes (frame
, regnum
, 0,
2619 register_size (gdbarch
, regnum
),
2620 from
, optimizedp
, unavailablep
))
2623 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2625 *optimizedp
= *unavailablep
= 0;
2630 rs6000_value_to_register (struct frame_info
*frame
,
2633 const gdb_byte
*from
)
2635 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2636 gdb_byte to
[MAX_REGISTER_SIZE
];
2638 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2640 convert_typed_floating (from
, type
,
2641 to
, builtin_type (gdbarch
)->builtin_double
);
2642 put_frame_register (frame
, regnum
, to
);
2645 /* The type of a function that moves the value of REG between CACHE
2646 or BUF --- in either direction. */
2647 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2650 /* Move SPE vector register values between a 64-bit buffer and the two
2651 32-bit raw register halves in a regcache. This function handles
2652 both splitting a 64-bit value into two 32-bit halves, and joining
2653 two halves into a whole 64-bit value, depending on the function
2654 passed as the MOVE argument.
2656 EV_REG must be the number of an SPE evN vector register --- a
2657 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2660 Call MOVE once for each 32-bit half of that register, passing
2661 REGCACHE, the number of the raw register corresponding to that
2662 half, and the address of the appropriate half of BUFFER.
2664 For example, passing 'regcache_raw_read' as the MOVE function will
2665 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2666 'regcache_raw_supply' will supply the contents of BUFFER to the
2667 appropriate pair of raw registers in REGCACHE.
2669 You may need to cast away some 'const' qualifiers when passing
2670 MOVE, since this function can't tell at compile-time which of
2671 REGCACHE or BUFFER is acting as the source of the data. If C had
2672 co-variant type qualifiers, ... */
2674 static enum register_status
2675 e500_move_ev_register (move_ev_register_func move
,
2676 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2678 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2679 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2681 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2682 enum register_status status
;
2684 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2686 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2688 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2690 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2692 if (status
== REG_VALID
)
2693 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2698 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2699 if (status
== REG_VALID
)
2700 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2707 static enum register_status
2708 do_regcache_raw_read (struct regcache
*regcache
, int regnum
, void *buffer
)
2710 return regcache_raw_read (regcache
, regnum
, (gdb_byte
*) buffer
);
2713 static enum register_status
2714 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2716 regcache_raw_write (regcache
, regnum
, (const gdb_byte
*) buffer
);
2721 static enum register_status
2722 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2723 int reg_nr
, gdb_byte
*buffer
)
2725 return e500_move_ev_register (do_regcache_raw_read
, regcache
, reg_nr
, buffer
);
2729 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2730 int reg_nr
, const gdb_byte
*buffer
)
2732 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2733 reg_nr
, (void *) buffer
);
2736 /* Read method for DFP pseudo-registers. */
2737 static enum register_status
2738 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2739 int reg_nr
, gdb_byte
*buffer
)
2741 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2742 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2743 enum register_status status
;
2745 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2747 /* Read two FP registers to form a whole dl register. */
2748 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2749 2 * reg_index
, buffer
);
2750 if (status
== REG_VALID
)
2751 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2752 2 * reg_index
+ 1, buffer
+ 8);
2756 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2757 2 * reg_index
+ 1, buffer
);
2758 if (status
== REG_VALID
)
2759 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2760 2 * reg_index
, buffer
+ 8);
2766 /* Write method for DFP pseudo-registers. */
2768 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2769 int reg_nr
, const gdb_byte
*buffer
)
2771 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2772 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2774 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2776 /* Write each half of the dl register into a separate
2778 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2779 2 * reg_index
, buffer
);
2780 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2781 2 * reg_index
+ 1, buffer
+ 8);
2785 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2786 2 * reg_index
+ 1, buffer
);
2787 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2788 2 * reg_index
, buffer
+ 8);
2792 /* Read method for POWER7 VSX pseudo-registers. */
2793 static enum register_status
2794 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2795 int reg_nr
, gdb_byte
*buffer
)
2797 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2798 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2799 enum register_status status
;
2801 /* Read the portion that overlaps the VMX registers. */
2803 status
= regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2804 reg_index
- 32, buffer
);
2806 /* Read the portion that overlaps the FPR registers. */
2807 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2809 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2811 if (status
== REG_VALID
)
2812 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2813 reg_index
, buffer
+ 8);
2817 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2818 reg_index
, buffer
+ 8);
2819 if (status
== REG_VALID
)
2820 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2827 /* Write method for POWER7 VSX pseudo-registers. */
2829 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2830 int reg_nr
, const gdb_byte
*buffer
)
2832 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2833 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2835 /* Write the portion that overlaps the VMX registers. */
2837 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2838 reg_index
- 32, buffer
);
2840 /* Write the portion that overlaps the FPR registers. */
2841 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2843 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2845 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2846 reg_index
, buffer
+ 8);
2850 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2851 reg_index
, buffer
+ 8);
2852 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2857 /* Read method for POWER7 Extended FP pseudo-registers. */
2858 static enum register_status
2859 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2860 int reg_nr
, gdb_byte
*buffer
)
2862 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2863 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2864 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2866 /* Read the portion that overlaps the VMX register. */
2867 return regcache_raw_read_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2868 offset
, register_size (gdbarch
, reg_nr
),
2872 /* Write method for POWER7 Extended FP pseudo-registers. */
2874 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2875 int reg_nr
, const gdb_byte
*buffer
)
2877 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2878 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2879 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2881 /* Write the portion that overlaps the VMX register. */
2882 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2883 offset
, register_size (gdbarch
, reg_nr
),
2887 static enum register_status
2888 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2889 struct regcache
*regcache
,
2890 int reg_nr
, gdb_byte
*buffer
)
2892 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2893 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2895 gdb_assert (regcache_arch
== gdbarch
);
2897 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2898 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2899 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2900 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2901 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2902 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2903 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2904 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2906 internal_error (__FILE__
, __LINE__
,
2907 _("rs6000_pseudo_register_read: "
2908 "called on unexpected register '%s' (%d)"),
2909 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2913 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2914 struct regcache
*regcache
,
2915 int reg_nr
, const gdb_byte
*buffer
)
2917 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2918 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2920 gdb_assert (regcache_arch
== gdbarch
);
2922 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2923 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2924 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2925 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2926 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2927 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2928 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2929 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2931 internal_error (__FILE__
, __LINE__
,
2932 _("rs6000_pseudo_register_write: "
2933 "called on unexpected register '%s' (%d)"),
2934 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2938 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2939 struct agent_expr
*ax
, int reg_nr
)
2941 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2942 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2944 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
2945 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
2946 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
2948 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2950 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2951 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
2952 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
2954 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2956 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2959 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
2963 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
2964 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
2967 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2969 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2970 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
2973 internal_error (__FILE__
, __LINE__
,
2974 _("rs6000_pseudo_register_collect: "
2975 "called on unexpected register '%s' (%d)"),
2976 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2982 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
2983 struct agent_expr
*ax
, struct axs_value
*value
,
2986 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2987 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
2988 value
->kind
= axs_lvalue_register
;
2989 value
->u
.reg
= tdep
->ppc_lr_regnum
;
2993 /* Convert a DBX STABS register number to a GDB register number. */
2995 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2997 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2999 if (0 <= num
&& num
<= 31)
3000 return tdep
->ppc_gp0_regnum
+ num
;
3001 else if (32 <= num
&& num
<= 63)
3002 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3003 specifies registers the architecture doesn't have? Our
3004 callers don't check the value we return. */
3005 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3006 else if (77 <= num
&& num
<= 108)
3007 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3008 else if (1200 <= num
&& num
< 1200 + 32)
3009 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3014 return tdep
->ppc_mq_regnum
;
3016 return tdep
->ppc_lr_regnum
;
3018 return tdep
->ppc_ctr_regnum
;
3020 return tdep
->ppc_xer_regnum
;
3022 return tdep
->ppc_vrsave_regnum
;
3024 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3026 return tdep
->ppc_acc_regnum
;
3028 return tdep
->ppc_spefscr_regnum
;
3035 /* Convert a Dwarf 2 register number to a GDB register number. */
3037 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3039 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3041 if (0 <= num
&& num
<= 31)
3042 return tdep
->ppc_gp0_regnum
+ num
;
3043 else if (32 <= num
&& num
<= 63)
3044 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3045 specifies registers the architecture doesn't have? Our
3046 callers don't check the value we return. */
3047 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3048 else if (1124 <= num
&& num
< 1124 + 32)
3049 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3050 else if (1200 <= num
&& num
< 1200 + 32)
3051 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3056 return tdep
->ppc_cr_regnum
;
3058 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3060 return tdep
->ppc_acc_regnum
;
3062 return tdep
->ppc_mq_regnum
;
3064 return tdep
->ppc_xer_regnum
;
3066 return tdep
->ppc_lr_regnum
;
3068 return tdep
->ppc_ctr_regnum
;
3070 return tdep
->ppc_vrsave_regnum
;
3072 return tdep
->ppc_spefscr_regnum
;
3078 /* Translate a .eh_frame register to DWARF register, or adjust a
3079 .debug_frame register. */
3082 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3084 /* GCC releases before 3.4 use GCC internal register numbering in
3085 .debug_frame (and .debug_info, et cetera). The numbering is
3086 different from the standard SysV numbering for everything except
3087 for GPRs and FPRs. We can not detect this problem in most cases
3088 - to get accurate debug info for variables living in lr, ctr, v0,
3089 et cetera, use a newer version of GCC. But we must detect
3090 one important case - lr is in column 65 in .debug_frame output,
3093 GCC 3.4, and the "hammer" branch, have a related problem. They
3094 record lr register saves in .debug_frame as 108, but still record
3095 the return column as 65. We fix that up too.
3097 We can do this because 65 is assigned to fpsr, and GCC never
3098 generates debug info referring to it. To add support for
3099 handwritten debug info that restores fpsr, we would need to add a
3100 producer version check to this. */
3109 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3110 internal register numbering; translate that to the standard DWARF2
3111 register numbering. */
3112 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3114 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3115 return num
- 68 + 86;
3116 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3117 return num
- 77 + 1124;
3129 case 109: /* vrsave */
3131 case 110: /* vscr */
3133 case 111: /* spe_acc */
3135 case 112: /* spefscr */
3143 /* Handling the various POWER/PowerPC variants. */
3145 /* Information about a particular processor variant. */
3149 /* Name of this variant. */
3152 /* English description of the variant. */
3153 const char *description
;
3155 /* bfd_arch_info.arch corresponding to variant. */
3156 enum bfd_architecture arch
;
3158 /* bfd_arch_info.mach corresponding to variant. */
3161 /* Target description for this variant. */
3162 struct target_desc
**tdesc
;
3165 static struct variant variants
[] =
3167 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3168 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3169 {"power", "POWER user-level", bfd_arch_rs6000
,
3170 bfd_mach_rs6k
, &tdesc_rs6000
},
3171 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3172 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3173 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3174 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3175 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3176 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3177 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3178 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3179 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3180 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3181 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3182 604, &tdesc_powerpc_604
},
3183 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3184 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3185 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3186 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3187 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3188 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3189 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3190 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3191 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3192 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3193 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3194 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3197 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3198 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3199 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3200 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3201 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3202 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3203 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3204 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3205 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3206 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3207 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3208 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3210 /* FIXME: I haven't checked the register sets of the following. */
3211 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3212 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3213 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3214 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3215 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3216 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3218 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3221 /* Return the variant corresponding to architecture ARCH and machine number
3222 MACH. If no such variant exists, return null. */
3224 static const struct variant
*
3225 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3227 const struct variant
*v
;
3229 for (v
= variants
; v
->name
; v
++)
3230 if (arch
== v
->arch
&& mach
== v
->mach
)
3237 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3239 if (info
->endian
== BFD_ENDIAN_BIG
)
3240 return print_insn_big_powerpc (memaddr
, info
);
3242 return print_insn_little_powerpc (memaddr
, info
);
3246 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3248 return frame_unwind_register_unsigned (next_frame
,
3249 gdbarch_pc_regnum (gdbarch
));
3252 static struct frame_id
3253 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3255 return frame_id_build (get_frame_register_unsigned
3256 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3257 get_frame_pc (this_frame
));
3260 struct rs6000_frame_cache
3263 CORE_ADDR initial_sp
;
3264 struct trad_frame_saved_reg
*saved_regs
;
3266 /* Set BASE_P to true if this frame cache is properly initialized.
3267 Otherwise set to false because some registers or memory cannot
3270 /* Cache PC for building unavailable frame. */
3274 static struct rs6000_frame_cache
*
3275 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3277 struct rs6000_frame_cache
*cache
;
3278 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3280 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3281 struct rs6000_framedata fdata
;
3282 int wordsize
= tdep
->wordsize
;
3283 CORE_ADDR func
= 0, pc
= 0;
3285 if ((*this_cache
) != NULL
)
3286 return (struct rs6000_frame_cache
*) (*this_cache
);
3287 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3288 (*this_cache
) = cache
;
3290 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3294 func
= get_frame_func (this_frame
);
3296 pc
= get_frame_pc (this_frame
);
3297 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3299 /* Figure out the parent's stack pointer. */
3301 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3302 address of the current frame. Things might be easier if the
3303 ->frame pointed to the outer-most address of the frame. In
3304 the mean time, the address of the prev frame is used as the
3305 base address of this frame. */
3306 cache
->base
= get_frame_register_unsigned
3307 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3309 CATCH (ex
, RETURN_MASK_ERROR
)
3311 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3312 throw_exception (ex
);
3313 return (struct rs6000_frame_cache
*) (*this_cache
);
3317 /* If the function appears to be frameless, check a couple of likely
3318 indicators that we have simply failed to find the frame setup.
3319 Two common cases of this are missing symbols (i.e.
3320 get_frame_func returns the wrong address or 0), and assembly
3321 stubs which have a fast exit path but set up a frame on the slow
3324 If the LR appears to return to this function, then presume that
3325 we have an ABI compliant frame that we failed to find. */
3326 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3331 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3332 if (func
== 0 && saved_lr
== pc
)
3336 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3337 if (func
== saved_func
)
3343 fdata
.frameless
= 0;
3344 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3348 if (!fdata
.frameless
)
3350 /* Frameless really means stackless. */
3353 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3354 byte_order
, &backchain
))
3355 cache
->base
= (CORE_ADDR
) backchain
;
3358 trad_frame_set_value (cache
->saved_regs
,
3359 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3361 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3362 All fpr's from saved_fpr to fp31 are saved. */
3364 if (fdata
.saved_fpr
>= 0)
3367 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3369 /* If skip_prologue says floating-point registers were saved,
3370 but the current architecture has no floating-point registers,
3371 then that's strange. But we have no indices to even record
3372 the addresses under, so we just ignore it. */
3373 if (ppc_floating_point_unit_p (gdbarch
))
3374 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3376 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3381 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3382 All gpr's from saved_gpr to gpr31 are saved (except during the
3385 if (fdata
.saved_gpr
>= 0)
3388 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3389 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3391 if (fdata
.gpr_mask
& (1U << i
))
3392 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3393 gpr_addr
+= wordsize
;
3397 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3398 All vr's from saved_vr to vr31 are saved. */
3399 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3401 if (fdata
.saved_vr
>= 0)
3404 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3405 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3407 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3408 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3413 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3414 All vr's from saved_ev to ev31 are saved. ????? */
3415 if (tdep
->ppc_ev0_regnum
!= -1)
3417 if (fdata
.saved_ev
>= 0)
3420 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3421 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3423 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3425 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3426 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3427 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3432 /* If != 0, fdata.cr_offset is the offset from the frame that
3434 if (fdata
.cr_offset
!= 0)
3435 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3436 = cache
->base
+ fdata
.cr_offset
;
3438 /* If != 0, fdata.lr_offset is the offset from the frame that
3440 if (fdata
.lr_offset
!= 0)
3441 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3442 = cache
->base
+ fdata
.lr_offset
;
3443 else if (fdata
.lr_register
!= -1)
3444 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3445 /* The PC is found in the link register. */
3446 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3447 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3449 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3450 holds the VRSAVE. */
3451 if (fdata
.vrsave_offset
!= 0)
3452 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3453 = cache
->base
+ fdata
.vrsave_offset
;
3455 if (fdata
.alloca_reg
< 0)
3456 /* If no alloca register used, then fi->frame is the value of the
3457 %sp for this frame, and it is good enough. */
3459 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3462 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3469 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3470 struct frame_id
*this_id
)
3472 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3477 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3481 /* This marks the outermost frame. */
3482 if (info
->base
== 0)
3485 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3488 static struct value
*
3489 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3490 void **this_cache
, int regnum
)
3492 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3494 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3497 static const struct frame_unwind rs6000_frame_unwind
=
3500 default_frame_unwind_stop_reason
,
3501 rs6000_frame_this_id
,
3502 rs6000_frame_prev_register
,
3504 default_frame_sniffer
3507 /* Allocate and initialize a frame cache for an epilogue frame.
3508 SP is restored and prev-PC is stored in LR. */
3510 static struct rs6000_frame_cache
*
3511 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3513 struct rs6000_frame_cache
*cache
;
3514 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3518 return (struct rs6000_frame_cache
*) *this_cache
;
3520 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3521 (*this_cache
) = cache
;
3522 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3526 /* At this point the stack looks as if we just entered the
3527 function, and the return address is stored in LR. */
3530 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3531 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3534 cache
->initial_sp
= sp
;
3536 trad_frame_set_value (cache
->saved_regs
,
3537 gdbarch_pc_regnum (gdbarch
), lr
);
3539 CATCH (ex
, RETURN_MASK_ERROR
)
3541 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3542 throw_exception (ex
);
3549 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3550 Return the frame ID of an epilogue frame. */
3553 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3554 void **this_cache
, struct frame_id
*this_id
)
3557 struct rs6000_frame_cache
*info
=
3558 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3560 pc
= get_frame_func (this_frame
);
3561 if (info
->base
== 0)
3562 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3564 (*this_id
) = frame_id_build (info
->base
, pc
);
3567 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3568 Return the register value of REGNUM in previous frame. */
3570 static struct value
*
3571 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3572 void **this_cache
, int regnum
)
3574 struct rs6000_frame_cache
*info
=
3575 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3576 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3579 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3580 Check whether this an epilogue frame. */
3583 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3584 struct frame_info
*this_frame
,
3585 void **this_prologue_cache
)
3587 if (frame_relative_level (this_frame
) == 0)
3588 return rs6000_in_function_epilogue_frame_p (this_frame
,
3589 get_frame_arch (this_frame
),
3590 get_frame_pc (this_frame
));
3595 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3596 a function without debug information. */
3598 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3601 default_frame_unwind_stop_reason
,
3602 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3604 rs6000_epilogue_frame_sniffer
3609 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3611 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3613 return info
->initial_sp
;
3616 static const struct frame_base rs6000_frame_base
= {
3617 &rs6000_frame_unwind
,
3618 rs6000_frame_base_address
,
3619 rs6000_frame_base_address
,
3620 rs6000_frame_base_address
3623 static const struct frame_base
*
3624 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3626 return &rs6000_frame_base
;
3629 /* DWARF-2 frame support. Used to handle the detection of
3630 clobbered registers during function calls. */
3633 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3634 struct dwarf2_frame_state_reg
*reg
,
3635 struct frame_info
*this_frame
)
3637 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3639 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3640 non-volatile registers. We will use the same code for both. */
3642 /* Call-saved GP registers. */
3643 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3644 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3645 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3646 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3648 /* Call-clobbered GP registers. */
3649 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3650 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3651 || (regnum
== tdep
->ppc_gp0_regnum
))
3652 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3654 /* Deal with FP registers, if supported. */
3655 if (tdep
->ppc_fp0_regnum
>= 0)
3657 /* Call-saved FP registers. */
3658 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3659 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3660 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3662 /* Call-clobbered FP registers. */
3663 if ((regnum
>= tdep
->ppc_fp0_regnum
3664 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3665 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3668 /* Deal with ALTIVEC registers, if supported. */
3669 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3671 /* Call-saved Altivec registers. */
3672 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3673 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3674 || regnum
== tdep
->ppc_vrsave_regnum
)
3675 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3677 /* Call-clobbered Altivec registers. */
3678 if ((regnum
>= tdep
->ppc_vr0_regnum
3679 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3680 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3683 /* Handle PC register and Stack Pointer correctly. */
3684 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3685 reg
->how
= DWARF2_FRAME_REG_RA
;
3686 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3687 reg
->how
= DWARF2_FRAME_REG_CFA
;
3691 /* Return true if a .gnu_attributes section exists in BFD and it
3692 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3693 section exists in BFD and it indicates that SPE extensions are in
3694 use. Check the .gnu.attributes section first, as the binary might be
3695 compiled for SPE, but not actually using SPE instructions. */
3698 bfd_uses_spe_extensions (bfd
*abfd
)
3701 gdb_byte
*contents
= NULL
;
3711 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3712 could be using the SPE vector abi without actually using any spe
3713 bits whatsoever. But it's close enough for now. */
3714 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3715 Tag_GNU_Power_ABI_Vector
);
3716 if (vector_abi
== 3)
3720 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3724 size
= bfd_get_section_size (sect
);
3725 contents
= (gdb_byte
*) xmalloc (size
);
3726 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3732 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3738 char name[name_len rounded up to 4-byte alignment];
3739 char data[data_len];
3742 Technically, there's only supposed to be one such structure in a
3743 given apuinfo section, but the linker is not always vigilant about
3744 merging apuinfo sections from input files. Just go ahead and parse
3745 them all, exiting early when we discover the binary uses SPE
3748 It's not specified in what endianness the information in this
3749 section is stored. Assume that it's the endianness of the BFD. */
3753 unsigned int name_len
;
3754 unsigned int data_len
;
3757 /* If we can't read the first three fields, we're done. */
3761 name_len
= bfd_get_32 (abfd
, ptr
);
3762 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3763 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3764 type
= bfd_get_32 (abfd
, ptr
+ 8);
3767 /* The name must be "APUinfo\0". */
3769 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3773 /* The type must be 2. */
3777 /* The data is stored as a series of uint32. The upper half of
3778 each uint32 indicates the particular APU used and the lower
3779 half indicates the revision of that APU. We just care about
3782 /* Not 4-byte quantities. */
3788 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3789 unsigned int apu
= apuinfo
>> 16;
3793 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3795 if (apu
== 0x100 || apu
== 0x101)
3810 /* These are macros for parsing instruction fields (I.1.6.28) */
3812 #define PPC_FIELD(value, from, len) \
3813 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3814 #define PPC_SEXT(v, bs) \
3815 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3816 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3817 - ((CORE_ADDR) 1 << ((bs) - 1)))
3818 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3819 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3820 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3821 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3822 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3823 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3824 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3825 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3826 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3827 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3828 | (PPC_FIELD (insn, 16, 5) << 5))
3829 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3830 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3831 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3832 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3833 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3834 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3835 #define PPC_OE(insn) PPC_BIT (insn, 21)
3836 #define PPC_RC(insn) PPC_BIT (insn, 31)
3837 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3838 #define PPC_LK(insn) PPC_BIT (insn, 31)
3839 #define PPC_TX(insn) PPC_BIT (insn, 31)
3840 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3842 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3843 #define PPC_XER_NB(xer) (xer & 0x7f)
3845 /* Record Vector-Scalar Registers.
3846 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3847 Otherwise, it's just a VR register. Record them accordingly. */
3850 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3852 if (vsr
< 0 || vsr
>= 64)
3857 if (tdep
->ppc_vr0_regnum
>= 0)
3858 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3862 if (tdep
->ppc_fp0_regnum
>= 0)
3863 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3864 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3865 record_full_arch_list_add_reg (regcache
,
3866 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3872 /* Parse and record instructions primary opcode-4 at ADDR.
3873 Return 0 if successful. */
3876 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3877 CORE_ADDR addr
, uint32_t insn
)
3879 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3880 int ext
= PPC_FIELD (insn
, 21, 11);
3881 int vra
= PPC_FIELD (insn
, 11, 5);
3885 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3886 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3887 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3888 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3889 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3891 case 42: /* Vector Select */
3892 case 43: /* Vector Permute */
3893 case 59: /* Vector Permute Right-indexed */
3894 case 44: /* Vector Shift Left Double by Octet Immediate */
3895 case 45: /* Vector Permute and Exclusive-OR */
3896 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3897 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3898 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3899 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3900 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3901 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3902 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3903 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3904 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3905 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3906 case 46: /* Vector Multiply-Add Single-Precision */
3907 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3908 record_full_arch_list_add_reg (regcache
,
3909 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3912 case 48: /* Multiply-Add High Doubleword */
3913 case 49: /* Multiply-Add High Doubleword Unsigned */
3914 case 51: /* Multiply-Add Low Doubleword */
3915 record_full_arch_list_add_reg (regcache
,
3916 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3920 switch ((ext
& 0x1ff))
3923 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3924 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3925 && vra
!= 4 /* Decimal Convert To Zoned */
3926 && vra
!= 5 /* Decimal Convert To National */
3927 && vra
!= 6 /* Decimal Convert From Zoned */
3928 && vra
!= 7 /* Decimal Convert From National */
3929 && vra
!= 31) /* Decimal Set Sign */
3931 /* 5.16 Decimal Integer Arithmetic Instructions */
3932 case 1: /* Decimal Add Modulo */
3933 case 65: /* Decimal Subtract Modulo */
3935 case 193: /* Decimal Shift */
3936 case 129: /* Decimal Unsigned Shift */
3937 case 449: /* Decimal Shift and Round */
3939 case 257: /* Decimal Truncate */
3940 case 321: /* Decimal Unsigned Truncate */
3942 /* Bit-21 should be set. */
3943 if (!PPC_BIT (insn
, 21))
3946 record_full_arch_list_add_reg (regcache
,
3947 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3948 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3952 /* Bit-21 is used for RC */
3953 switch (ext
& 0x3ff)
3955 case 6: /* Vector Compare Equal To Unsigned Byte */
3956 case 70: /* Vector Compare Equal To Unsigned Halfword */
3957 case 134: /* Vector Compare Equal To Unsigned Word */
3958 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3959 case 774: /* Vector Compare Greater Than Signed Byte */
3960 case 838: /* Vector Compare Greater Than Signed Halfword */
3961 case 902: /* Vector Compare Greater Than Signed Word */
3962 case 967: /* Vector Compare Greater Than Signed Doubleword */
3963 case 518: /* Vector Compare Greater Than Unsigned Byte */
3964 case 646: /* Vector Compare Greater Than Unsigned Word */
3965 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3966 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3967 case 966: /* Vector Compare Bounds Single-Precision */
3968 case 198: /* Vector Compare Equal To Single-Precision */
3969 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3970 case 710: /* Vector Compare Greater Than Single-Precision */
3971 case 7: /* Vector Compare Not Equal Byte */
3972 case 71: /* Vector Compare Not Equal Halfword */
3973 case 135: /* Vector Compare Not Equal Word */
3974 case 263: /* Vector Compare Not Equal or Zero Byte */
3975 case 327: /* Vector Compare Not Equal or Zero Halfword */
3976 case 391: /* Vector Compare Not Equal or Zero Word */
3978 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3979 record_full_arch_list_add_reg (regcache
,
3980 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3988 case 0: /* Vector Count Leading Zero Least-Significant Bits
3990 case 1: /* Vector Count Trailing Zero Least-Significant Bits
3992 record_full_arch_list_add_reg (regcache
,
3993 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3996 case 6: /* Vector Negate Word */
3997 case 7: /* Vector Negate Doubleword */
3998 case 8: /* Vector Parity Byte Word */
3999 case 9: /* Vector Parity Byte Doubleword */
4000 case 10: /* Vector Parity Byte Quadword */
4001 case 16: /* Vector Extend Sign Byte To Word */
4002 case 17: /* Vector Extend Sign Halfword To Word */
4003 case 24: /* Vector Extend Sign Byte To Doubleword */
4004 case 25: /* Vector Extend Sign Halfword To Doubleword */
4005 case 26: /* Vector Extend Sign Word To Doubleword */
4006 case 28: /* Vector Count Trailing Zeros Byte */
4007 case 29: /* Vector Count Trailing Zeros Halfword */
4008 case 30: /* Vector Count Trailing Zeros Word */
4009 case 31: /* Vector Count Trailing Zeros Doubleword */
4010 record_full_arch_list_add_reg (regcache
,
4011 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4018 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4019 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4020 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4021 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4022 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4023 case 462: /* Vector Pack Signed Word Signed Saturate */
4024 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4025 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4026 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4027 case 512: /* Vector Add Unsigned Byte Saturate */
4028 case 576: /* Vector Add Unsigned Halfword Saturate */
4029 case 640: /* Vector Add Unsigned Word Saturate */
4030 case 768: /* Vector Add Signed Byte Saturate */
4031 case 832: /* Vector Add Signed Halfword Saturate */
4032 case 896: /* Vector Add Signed Word Saturate */
4033 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4034 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4035 case 1664: /* Vector Subtract Unsigned Word Saturate */
4036 case 1792: /* Vector Subtract Signed Byte Saturate */
4037 case 1856: /* Vector Subtract Signed Halfword Saturate */
4038 case 1920: /* Vector Subtract Signed Word Saturate */
4040 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4041 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4042 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4043 case 1672: /* Vector Sum across Half Signed Word Saturate */
4044 case 1928: /* Vector Sum across Signed Word Saturate */
4045 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4046 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4047 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4049 case 12: /* Vector Merge High Byte */
4050 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4051 case 76: /* Vector Merge High Halfword */
4052 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4053 case 140: /* Vector Merge High Word */
4054 case 268: /* Vector Merge Low Byte */
4055 case 332: /* Vector Merge Low Halfword */
4056 case 396: /* Vector Merge Low Word */
4057 case 526: /* Vector Unpack High Signed Byte */
4058 case 590: /* Vector Unpack High Signed Halfword */
4059 case 654: /* Vector Unpack Low Signed Byte */
4060 case 718: /* Vector Unpack Low Signed Halfword */
4061 case 782: /* Vector Pack Pixel */
4062 case 846: /* Vector Unpack High Pixel */
4063 case 974: /* Vector Unpack Low Pixel */
4064 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4065 case 1614: /* Vector Unpack High Signed Word */
4066 case 1676: /* Vector Merge Odd Word */
4067 case 1742: /* Vector Unpack Low Signed Word */
4068 case 1932: /* Vector Merge Even Word */
4069 case 524: /* Vector Splat Byte */
4070 case 588: /* Vector Splat Halfword */
4071 case 652: /* Vector Splat Word */
4072 case 780: /* Vector Splat Immediate Signed Byte */
4073 case 844: /* Vector Splat Immediate Signed Halfword */
4074 case 908: /* Vector Splat Immediate Signed Word */
4075 case 452: /* Vector Shift Left */
4076 case 708: /* Vector Shift Right */
4077 case 1036: /* Vector Shift Left by Octet */
4078 case 1100: /* Vector Shift Right by Octet */
4079 case 0: /* Vector Add Unsigned Byte Modulo */
4080 case 64: /* Vector Add Unsigned Halfword Modulo */
4081 case 128: /* Vector Add Unsigned Word Modulo */
4082 case 192: /* Vector Add Unsigned Doubleword Modulo */
4083 case 256: /* Vector Add Unsigned Quadword Modulo */
4084 case 320: /* Vector Add & write Carry Unsigned Quadword */
4085 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4086 case 8: /* Vector Multiply Odd Unsigned Byte */
4087 case 72: /* Vector Multiply Odd Unsigned Halfword */
4088 case 136: /* Vector Multiply Odd Unsigned Word */
4089 case 264: /* Vector Multiply Odd Signed Byte */
4090 case 328: /* Vector Multiply Odd Signed Halfword */
4091 case 392: /* Vector Multiply Odd Signed Word */
4092 case 520: /* Vector Multiply Even Unsigned Byte */
4093 case 584: /* Vector Multiply Even Unsigned Halfword */
4094 case 648: /* Vector Multiply Even Unsigned Word */
4095 case 776: /* Vector Multiply Even Signed Byte */
4096 case 840: /* Vector Multiply Even Signed Halfword */
4097 case 904: /* Vector Multiply Even Signed Word */
4098 case 137: /* Vector Multiply Unsigned Word Modulo */
4099 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4100 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4101 case 1152: /* Vector Subtract Unsigned Word Modulo */
4102 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4103 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4104 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4105 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4106 case 1282: /* Vector Average Signed Byte */
4107 case 1346: /* Vector Average Signed Halfword */
4108 case 1410: /* Vector Average Signed Word */
4109 case 1026: /* Vector Average Unsigned Byte */
4110 case 1090: /* Vector Average Unsigned Halfword */
4111 case 1154: /* Vector Average Unsigned Word */
4112 case 258: /* Vector Maximum Signed Byte */
4113 case 322: /* Vector Maximum Signed Halfword */
4114 case 386: /* Vector Maximum Signed Word */
4115 case 450: /* Vector Maximum Signed Doubleword */
4116 case 2: /* Vector Maximum Unsigned Byte */
4117 case 66: /* Vector Maximum Unsigned Halfword */
4118 case 130: /* Vector Maximum Unsigned Word */
4119 case 194: /* Vector Maximum Unsigned Doubleword */
4120 case 770: /* Vector Minimum Signed Byte */
4121 case 834: /* Vector Minimum Signed Halfword */
4122 case 898: /* Vector Minimum Signed Word */
4123 case 962: /* Vector Minimum Signed Doubleword */
4124 case 514: /* Vector Minimum Unsigned Byte */
4125 case 578: /* Vector Minimum Unsigned Halfword */
4126 case 642: /* Vector Minimum Unsigned Word */
4127 case 706: /* Vector Minimum Unsigned Doubleword */
4128 case 1028: /* Vector Logical AND */
4129 case 1668: /* Vector Logical Equivalent */
4130 case 1092: /* Vector Logical AND with Complement */
4131 case 1412: /* Vector Logical NAND */
4132 case 1348: /* Vector Logical OR with Complement */
4133 case 1156: /* Vector Logical OR */
4134 case 1284: /* Vector Logical NOR */
4135 case 1220: /* Vector Logical XOR */
4136 case 4: /* Vector Rotate Left Byte */
4137 case 132: /* Vector Rotate Left Word VX-form */
4138 case 68: /* Vector Rotate Left Halfword */
4139 case 196: /* Vector Rotate Left Doubleword */
4140 case 260: /* Vector Shift Left Byte */
4141 case 388: /* Vector Shift Left Word */
4142 case 324: /* Vector Shift Left Halfword */
4143 case 1476: /* Vector Shift Left Doubleword */
4144 case 516: /* Vector Shift Right Byte */
4145 case 644: /* Vector Shift Right Word */
4146 case 580: /* Vector Shift Right Halfword */
4147 case 1732: /* Vector Shift Right Doubleword */
4148 case 772: /* Vector Shift Right Algebraic Byte */
4149 case 900: /* Vector Shift Right Algebraic Word */
4150 case 836: /* Vector Shift Right Algebraic Halfword */
4151 case 964: /* Vector Shift Right Algebraic Doubleword */
4152 case 10: /* Vector Add Single-Precision */
4153 case 74: /* Vector Subtract Single-Precision */
4154 case 1034: /* Vector Maximum Single-Precision */
4155 case 1098: /* Vector Minimum Single-Precision */
4156 case 842: /* Vector Convert From Signed Fixed-Point Word */
4157 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4158 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4159 case 522: /* Vector Round to Single-Precision Integer Nearest */
4160 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4161 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4162 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4163 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4164 case 266: /* Vector Reciprocal Estimate Single-Precision */
4165 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4166 case 1288: /* Vector AES Cipher */
4167 case 1289: /* Vector AES Cipher Last */
4168 case 1352: /* Vector AES Inverse Cipher */
4169 case 1353: /* Vector AES Inverse Cipher Last */
4170 case 1480: /* Vector AES SubBytes */
4171 case 1730: /* Vector SHA-512 Sigma Doubleword */
4172 case 1666: /* Vector SHA-256 Sigma Word */
4173 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4174 case 1160: /* Vector Polynomial Multiply-Sum Word */
4175 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4176 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4177 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4178 case 1794: /* Vector Count Leading Zeros Byte */
4179 case 1858: /* Vector Count Leading Zeros Halfword */
4180 case 1922: /* Vector Count Leading Zeros Word */
4181 case 1986: /* Vector Count Leading Zeros Doubleword */
4182 case 1795: /* Vector Population Count Byte */
4183 case 1859: /* Vector Population Count Halfword */
4184 case 1923: /* Vector Population Count Word */
4185 case 1987: /* Vector Population Count Doubleword */
4186 case 1356: /* Vector Bit Permute Quadword */
4187 case 1484: /* Vector Bit Permute Doubleword */
4188 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4189 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4191 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4192 case 65: /* Vector Multiply-by-10 Extended & write Carry
4193 Unsigned Quadword */
4194 case 1027: /* Vector Absolute Difference Unsigned Byte */
4195 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4196 case 1155: /* Vector Absolute Difference Unsigned Word */
4197 case 1796: /* Vector Shift Right Variable */
4198 case 1860: /* Vector Shift Left Variable */
4199 case 133: /* Vector Rotate Left Word then Mask Insert */
4200 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4201 case 389: /* Vector Rotate Left Word then AND with Mask */
4202 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4203 case 525: /* Vector Extract Unsigned Byte */
4204 case 589: /* Vector Extract Unsigned Halfword */
4205 case 653: /* Vector Extract Unsigned Word */
4206 case 717: /* Vector Extract Doubleword */
4207 case 781: /* Vector Insert Byte */
4208 case 845: /* Vector Insert Halfword */
4209 case 909: /* Vector Insert Word */
4210 case 973: /* Vector Insert Doubleword */
4211 record_full_arch_list_add_reg (regcache
,
4212 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4215 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4216 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4217 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4218 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4219 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4220 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4221 record_full_arch_list_add_reg (regcache
,
4222 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4225 case 1604: /* Move To Vector Status and Control Register */
4226 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4228 case 1540: /* Move From Vector Status and Control Register */
4229 record_full_arch_list_add_reg (regcache
,
4230 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4232 case 833: /* Decimal Copy Sign */
4233 record_full_arch_list_add_reg (regcache
,
4234 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4235 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4239 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4240 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4244 /* Parse and record instructions of primary opcode-19 at ADDR.
4245 Return 0 if successful. */
4248 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4249 CORE_ADDR addr
, uint32_t insn
)
4251 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4252 int ext
= PPC_EXTOP (insn
);
4254 switch (ext
& 0x01f)
4256 case 2: /* Add PC Immediate Shifted */
4257 record_full_arch_list_add_reg (regcache
,
4258 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4264 case 0: /* Move Condition Register Field */
4265 case 33: /* Condition Register NOR */
4266 case 129: /* Condition Register AND with Complement */
4267 case 193: /* Condition Register XOR */
4268 case 225: /* Condition Register NAND */
4269 case 257: /* Condition Register AND */
4270 case 289: /* Condition Register Equivalent */
4271 case 417: /* Condition Register OR with Complement */
4272 case 449: /* Condition Register OR */
4273 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4276 case 16: /* Branch Conditional */
4277 case 560: /* Branch Conditional to Branch Target Address Register */
4278 if ((PPC_BO (insn
) & 0x4) == 0)
4279 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4281 case 528: /* Branch Conditional to Count Register */
4283 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4286 case 150: /* Instruction Synchronize */
4291 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4292 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4296 /* Parse and record instructions of primary opcode-31 at ADDR.
4297 Return 0 if successful. */
4300 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4301 CORE_ADDR addr
, uint32_t insn
)
4303 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4304 int ext
= PPC_EXTOP (insn
);
4306 CORE_ADDR at_dcsz
, ea
= 0;
4307 ULONGEST rb
, ra
, xer
;
4310 /* These instructions have OE bit. */
4311 switch (ext
& 0x1ff)
4313 /* These write RT and XER. Update CR if RC is set. */
4314 case 8: /* Subtract from carrying */
4315 case 10: /* Add carrying */
4316 case 136: /* Subtract from extended */
4317 case 138: /* Add extended */
4318 case 200: /* Subtract from zero extended */
4319 case 202: /* Add to zero extended */
4320 case 232: /* Subtract from minus one extended */
4321 case 234: /* Add to minus one extended */
4322 /* CA is always altered, but SO/OV are only altered when OE=1.
4323 In any case, XER is always altered. */
4324 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4326 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4327 record_full_arch_list_add_reg (regcache
,
4328 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4331 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4332 case 40: /* Subtract from */
4333 case 104: /* Negate */
4334 case 233: /* Multiply low doubleword */
4335 case 235: /* Multiply low word */
4337 case 393: /* Divide Doubleword Extended Unsigned */
4338 case 395: /* Divide Word Extended Unsigned */
4339 case 425: /* Divide Doubleword Extended */
4340 case 427: /* Divide Word Extended */
4341 case 457: /* Divide Doubleword Unsigned */
4342 case 459: /* Divide Word Unsigned */
4343 case 489: /* Divide Doubleword */
4344 case 491: /* Divide Word */
4346 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4348 case 9: /* Multiply High Doubleword Unsigned */
4349 case 11: /* Multiply High Word Unsigned */
4350 case 73: /* Multiply High Doubleword */
4351 case 75: /* Multiply High Word */
4353 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4354 record_full_arch_list_add_reg (regcache
,
4355 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4359 if ((ext
& 0x1f) == 15)
4361 /* Integer Select. bit[16:20] is used for BC. */
4362 record_full_arch_list_add_reg (regcache
,
4363 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4367 if ((ext
& 0xff) == 170)
4369 /* Add Extended using alternate carry bits */
4370 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4371 record_full_arch_list_add_reg (regcache
,
4372 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4378 case 78: /* Determine Leftmost Zero Byte */
4380 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4381 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4382 record_full_arch_list_add_reg (regcache
,
4383 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4386 /* These only write RT. */
4387 case 19: /* Move from condition register */
4388 /* Move From One Condition Register Field */
4389 case 74: /* Add and Generate Sixes */
4390 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4391 case 302: /* Move From Branch History Rolling Buffer */
4392 case 339: /* Move From Special Purpose Register */
4393 case 371: /* Move From Time Base [Phased-Out] */
4394 case 309: /* Load Doubleword Monitored Indexed */
4395 case 128: /* Set Boolean */
4396 case 755: /* Deliver A Random Number */
4397 record_full_arch_list_add_reg (regcache
,
4398 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4401 /* These only write to RA. */
4402 case 51: /* Move From VSR Doubleword */
4403 case 115: /* Move From VSR Word and Zero */
4404 case 122: /* Population count bytes */
4405 case 378: /* Population count words */
4406 case 506: /* Population count doublewords */
4407 case 154: /* Parity Word */
4408 case 186: /* Parity Doubleword */
4409 case 252: /* Bit Permute Doubleword */
4410 case 282: /* Convert Declets To Binary Coded Decimal */
4411 case 314: /* Convert Binary Coded Decimal To Declets */
4412 case 508: /* Compare bytes */
4413 case 307: /* Move From VSR Lower Doubleword */
4414 record_full_arch_list_add_reg (regcache
,
4415 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4418 /* These write CR and optional RA. */
4419 case 792: /* Shift Right Algebraic Word */
4420 case 794: /* Shift Right Algebraic Doubleword */
4421 case 824: /* Shift Right Algebraic Word Immediate */
4422 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4423 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4424 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4425 record_full_arch_list_add_reg (regcache
,
4426 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4428 case 0: /* Compare */
4429 case 32: /* Compare logical */
4430 case 144: /* Move To Condition Register Fields */
4431 /* Move To One Condition Register Field */
4432 case 192: /* Compare Ranged Byte */
4433 case 224: /* Compare Equal Byte */
4434 case 576: /* Move XER to CR Extended */
4435 case 902: /* Paste (should always fail due to single-stepping and
4436 the memory location might not be accessible, so
4438 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4441 /* These write to RT. Update RA if 'update indexed.' */
4442 case 53: /* Load Doubleword with Update Indexed */
4443 case 119: /* Load Byte and Zero with Update Indexed */
4444 case 311: /* Load Halfword and Zero with Update Indexed */
4445 case 55: /* Load Word and Zero with Update Indexed */
4446 case 375: /* Load Halfword Algebraic with Update Indexed */
4447 case 373: /* Load Word Algebraic with Update Indexed */
4448 record_full_arch_list_add_reg (regcache
,
4449 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4451 case 21: /* Load Doubleword Indexed */
4452 case 52: /* Load Byte And Reserve Indexed */
4453 case 116: /* Load Halfword And Reserve Indexed */
4454 case 20: /* Load Word And Reserve Indexed */
4455 case 84: /* Load Doubleword And Reserve Indexed */
4456 case 87: /* Load Byte and Zero Indexed */
4457 case 279: /* Load Halfword and Zero Indexed */
4458 case 23: /* Load Word and Zero Indexed */
4459 case 343: /* Load Halfword Algebraic Indexed */
4460 case 341: /* Load Word Algebraic Indexed */
4461 case 790: /* Load Halfword Byte-Reverse Indexed */
4462 case 534: /* Load Word Byte-Reverse Indexed */
4463 case 532: /* Load Doubleword Byte-Reverse Indexed */
4464 case 582: /* Load Word Atomic */
4465 case 614: /* Load Doubleword Atomic */
4466 case 265: /* Modulo Unsigned Doubleword */
4467 case 777: /* Modulo Signed Doubleword */
4468 case 267: /* Modulo Unsigned Word */
4469 case 779: /* Modulo Signed Word */
4470 record_full_arch_list_add_reg (regcache
,
4471 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4474 case 597: /* Load String Word Immediate */
4475 case 533: /* Load String Word Indexed */
4484 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4485 nr
= PPC_XER_NB (xer
);
4490 /* If n=0, the contents of register RT are undefined. */
4494 for (i
= 0; i
< nr
; i
++)
4495 record_full_arch_list_add_reg (regcache
,
4496 tdep
->ppc_gp0_regnum
4497 + ((PPC_RT (insn
) + i
) & 0x1f));
4500 case 276: /* Load Quadword And Reserve Indexed */
4501 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4502 record_full_arch_list_add_reg (regcache
, tmp
);
4503 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4506 /* These write VRT. */
4507 case 6: /* Load Vector for Shift Left Indexed */
4508 case 38: /* Load Vector for Shift Right Indexed */
4509 case 7: /* Load Vector Element Byte Indexed */
4510 case 39: /* Load Vector Element Halfword Indexed */
4511 case 71: /* Load Vector Element Word Indexed */
4512 case 103: /* Load Vector Indexed */
4513 case 359: /* Load Vector Indexed LRU */
4514 record_full_arch_list_add_reg (regcache
,
4515 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4518 /* These write FRT. Update RA if 'update indexed.' */
4519 case 567: /* Load Floating-Point Single with Update Indexed */
4520 case 631: /* Load Floating-Point Double with Update Indexed */
4521 record_full_arch_list_add_reg (regcache
,
4522 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4524 case 535: /* Load Floating-Point Single Indexed */
4525 case 599: /* Load Floating-Point Double Indexed */
4526 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4527 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4528 record_full_arch_list_add_reg (regcache
,
4529 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4532 case 791: /* Load Floating-Point Double Pair Indexed */
4533 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4534 record_full_arch_list_add_reg (regcache
, tmp
);
4535 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4538 case 179: /* Move To VSR Doubleword */
4539 case 211: /* Move To VSR Word Algebraic */
4540 case 243: /* Move To VSR Word and Zero */
4541 case 588: /* Load VSX Scalar Doubleword Indexed */
4542 case 524: /* Load VSX Scalar Single-Precision Indexed */
4543 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4544 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4545 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4546 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4547 case 780: /* Load VSX Vector Word*4 Indexed */
4548 case 268: /* Load VSX Vector Indexed */
4549 case 364: /* Load VSX Vector Word & Splat Indexed */
4550 case 812: /* Load VSX Vector Halfword*8 Indexed */
4551 case 876: /* Load VSX Vector Byte*16 Indexed */
4552 case 269: /* Load VSX Vector with Length */
4553 case 301: /* Load VSX Vector Left-justified with Length */
4554 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4555 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4556 case 403: /* Move To VSR Word & Splat */
4557 case 435: /* Move To VSR Double Doubleword */
4558 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4561 /* These write RA. Update CR if RC is set. */
4562 case 24: /* Shift Left Word */
4563 case 26: /* Count Leading Zeros Word */
4564 case 27: /* Shift Left Doubleword */
4566 case 58: /* Count Leading Zeros Doubleword */
4567 case 60: /* AND with Complement */
4569 case 284: /* Equivalent */
4571 case 476: /* NAND */
4572 case 412: /* OR with Complement */
4574 case 536: /* Shift Right Word */
4575 case 539: /* Shift Right Doubleword */
4576 case 922: /* Extend Sign Halfword */
4577 case 954: /* Extend Sign Byte */
4578 case 986: /* Extend Sign Word */
4579 case 538: /* Count Trailing Zeros Word */
4580 case 570: /* Count Trailing Zeros Doubleword */
4581 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4582 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4584 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4585 record_full_arch_list_add_reg (regcache
,
4586 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4590 case 181: /* Store Doubleword with Update Indexed */
4591 case 183: /* Store Word with Update Indexed */
4592 case 247: /* Store Byte with Update Indexed */
4593 case 439: /* Store Half Word with Update Indexed */
4594 case 695: /* Store Floating-Point Single with Update Indexed */
4595 case 759: /* Store Floating-Point Double with Update Indexed */
4596 record_full_arch_list_add_reg (regcache
,
4597 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4599 case 135: /* Store Vector Element Byte Indexed */
4600 case 167: /* Store Vector Element Halfword Indexed */
4601 case 199: /* Store Vector Element Word Indexed */
4602 case 231: /* Store Vector Indexed */
4603 case 487: /* Store Vector Indexed LRU */
4604 case 716: /* Store VSX Scalar Doubleword Indexed */
4605 case 140: /* Store VSX Scalar as Integer Word Indexed */
4606 case 652: /* Store VSX Scalar Single-Precision Indexed */
4607 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4608 case 908: /* Store VSX Vector Word*4 Indexed */
4609 case 149: /* Store Doubleword Indexed */
4610 case 151: /* Store Word Indexed */
4611 case 215: /* Store Byte Indexed */
4612 case 407: /* Store Half Word Indexed */
4613 case 694: /* Store Byte Conditional Indexed */
4614 case 726: /* Store Halfword Conditional Indexed */
4615 case 150: /* Store Word Conditional Indexed */
4616 case 214: /* Store Doubleword Conditional Indexed */
4617 case 182: /* Store Quadword Conditional Indexed */
4618 case 662: /* Store Word Byte-Reverse Indexed */
4619 case 918: /* Store Halfword Byte-Reverse Indexed */
4620 case 660: /* Store Doubleword Byte-Reverse Indexed */
4621 case 663: /* Store Floating-Point Single Indexed */
4622 case 727: /* Store Floating-Point Double Indexed */
4623 case 919: /* Store Floating-Point Double Pair Indexed */
4624 case 983: /* Store Floating-Point as Integer Word Indexed */
4625 case 396: /* Store VSX Vector Indexed */
4626 case 940: /* Store VSX Vector Halfword*8 Indexed */
4627 case 1004: /* Store VSX Vector Byte*16 Indexed */
4628 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4629 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4630 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4631 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4634 if (PPC_RA (insn
) != 0)
4635 regcache_raw_read_unsigned (regcache
,
4636 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4637 regcache_raw_read_unsigned (regcache
,
4638 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4643 case 183: /* Store Word with Update Indexed */
4644 case 199: /* Store Vector Element Word Indexed */
4645 case 140: /* Store VSX Scalar as Integer Word Indexed */
4646 case 652: /* Store VSX Scalar Single-Precision Indexed */
4647 case 151: /* Store Word Indexed */
4648 case 150: /* Store Word Conditional Indexed */
4649 case 662: /* Store Word Byte-Reverse Indexed */
4650 case 663: /* Store Floating-Point Single Indexed */
4651 case 695: /* Store Floating-Point Single with Update Indexed */
4652 case 983: /* Store Floating-Point as Integer Word Indexed */
4655 case 247: /* Store Byte with Update Indexed */
4656 case 135: /* Store Vector Element Byte Indexed */
4657 case 215: /* Store Byte Indexed */
4658 case 694: /* Store Byte Conditional Indexed */
4659 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4662 case 439: /* Store Halfword with Update Indexed */
4663 case 167: /* Store Vector Element Halfword Indexed */
4664 case 407: /* Store Halfword Indexed */
4665 case 726: /* Store Halfword Conditional Indexed */
4666 case 918: /* Store Halfword Byte-Reverse Indexed */
4667 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4670 case 181: /* Store Doubleword with Update Indexed */
4671 case 716: /* Store VSX Scalar Doubleword Indexed */
4672 case 149: /* Store Doubleword Indexed */
4673 case 214: /* Store Doubleword Conditional Indexed */
4674 case 660: /* Store Doubleword Byte-Reverse Indexed */
4675 case 727: /* Store Floating-Point Double Indexed */
4676 case 759: /* Store Floating-Point Double with Update Indexed */
4679 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4680 case 908: /* Store VSX Vector Word*4 Indexed */
4681 case 182: /* Store Quadword Conditional Indexed */
4682 case 231: /* Store Vector Indexed */
4683 case 487: /* Store Vector Indexed LRU */
4684 case 919: /* Store Floating-Point Double Pair Indexed */
4685 case 396: /* Store VSX Vector Indexed */
4686 case 940: /* Store VSX Vector Halfword*8 Indexed */
4687 case 1004: /* Store VSX Vector Byte*16 Indexed */
4694 /* Align address for Store Vector instructions. */
4697 case 167: /* Store Vector Element Halfword Indexed */
4698 addr
= addr
& ~0x1ULL
;
4701 case 199: /* Store Vector Element Word Indexed */
4702 addr
= addr
& ~0x3ULL
;
4705 case 231: /* Store Vector Indexed */
4706 case 487: /* Store Vector Indexed LRU */
4707 addr
= addr
& ~0xfULL
;
4711 record_full_arch_list_add_mem (addr
, size
);
4714 case 397: /* Store VSX Vector with Length */
4715 case 429: /* Store VSX Vector Left-justified with Length */
4717 if (PPC_RA (insn
) != 0)
4718 regcache_raw_read_unsigned (regcache
,
4719 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4721 regcache_raw_read_unsigned (regcache
,
4722 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4723 /* Store up to 16 bytes. */
4724 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4726 record_full_arch_list_add_mem (ea
, nb
);
4729 case 710: /* Store Word Atomic */
4730 case 742: /* Store Doubleword Atomic */
4732 if (PPC_RA (insn
) != 0)
4733 regcache_raw_read_unsigned (regcache
,
4734 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4738 case 710: /* Store Word Atomic */
4741 case 742: /* Store Doubleword Atomic */
4747 record_full_arch_list_add_mem (ea
, size
);
4750 case 725: /* Store String Word Immediate */
4752 if (PPC_RA (insn
) != 0)
4753 regcache_raw_read_unsigned (regcache
,
4754 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4761 record_full_arch_list_add_mem (ea
, nb
);
4765 case 661: /* Store String Word Indexed */
4767 if (PPC_RA (insn
) != 0)
4768 regcache_raw_read_unsigned (regcache
,
4769 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4772 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4773 nb
= PPC_XER_NB (xer
);
4777 regcache_raw_read_unsigned (regcache
,
4778 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4781 record_full_arch_list_add_mem (ea
, nb
);
4786 case 467: /* Move To Special Purpose Register */
4787 switch (PPC_SPR (insn
))
4790 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4793 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4796 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4798 case 256: /* VRSAVE */
4799 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4805 case 147: /* Move To Split Little Endian */
4806 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4809 case 512: /* Move to Condition Register from XER */
4810 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4811 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4814 case 4: /* Trap Word */
4815 case 68: /* Trap Doubleword */
4816 case 430: /* Clear BHRB */
4817 case 598: /* Synchronize */
4818 case 62: /* Wait for Interrupt */
4820 case 22: /* Instruction Cache Block Touch */
4821 case 854: /* Enforce In-order Execution of I/O */
4822 case 246: /* Data Cache Block Touch for Store */
4823 case 54: /* Data Cache Block Store */
4824 case 86: /* Data Cache Block Flush */
4825 case 278: /* Data Cache Block Touch */
4826 case 758: /* Data Cache Block Allocate */
4827 case 982: /* Instruction Cache Block Invalidate */
4828 case 774: /* Copy */
4829 case 838: /* CP_Abort */
4832 case 654: /* Transaction Begin */
4833 case 686: /* Transaction End */
4834 case 750: /* Transaction Suspend or Resume */
4835 case 782: /* Transaction Abort Word Conditional */
4836 case 814: /* Transaction Abort Doubleword Conditional */
4837 case 846: /* Transaction Abort Word Conditional Immediate */
4838 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4839 case 910: /* Transaction Abort */
4840 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4842 case 718: /* Transaction Check */
4843 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4846 case 1014: /* Data Cache Block set to Zero */
4847 if (target_auxv_search (¤t_target
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4849 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4852 if (PPC_RA (insn
) != 0)
4853 regcache_raw_read_unsigned (regcache
,
4854 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4855 regcache_raw_read_unsigned (regcache
,
4856 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4857 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4858 record_full_arch_list_add_mem (ea
, at_dcsz
);
4863 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4864 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4868 /* Parse and record instructions of primary opcode-59 at ADDR.
4869 Return 0 if successful. */
4872 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4873 CORE_ADDR addr
, uint32_t insn
)
4875 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4876 int ext
= PPC_EXTOP (insn
);
4880 case 18: /* Floating Divide */
4881 case 20: /* Floating Subtract */
4882 case 21: /* Floating Add */
4883 case 22: /* Floating Square Root */
4884 case 24: /* Floating Reciprocal Estimate */
4885 case 25: /* Floating Multiply */
4886 case 26: /* Floating Reciprocal Square Root Estimate */
4887 case 28: /* Floating Multiply-Subtract */
4888 case 29: /* Floating Multiply-Add */
4889 case 30: /* Floating Negative Multiply-Subtract */
4890 case 31: /* Floating Negative Multiply-Add */
4891 record_full_arch_list_add_reg (regcache
,
4892 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4894 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4895 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4902 case 2: /* DFP Add */
4903 case 3: /* DFP Quantize */
4904 case 34: /* DFP Multiply */
4905 case 35: /* DFP Reround */
4906 case 67: /* DFP Quantize Immediate */
4907 case 99: /* DFP Round To FP Integer With Inexact */
4908 case 227: /* DFP Round To FP Integer Without Inexact */
4909 case 258: /* DFP Convert To DFP Long! */
4910 case 290: /* DFP Convert To Fixed */
4911 case 514: /* DFP Subtract */
4912 case 546: /* DFP Divide */
4913 case 770: /* DFP Round To DFP Short! */
4914 case 802: /* DFP Convert From Fixed */
4915 case 834: /* DFP Encode BCD To DPD */
4917 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4918 record_full_arch_list_add_reg (regcache
,
4919 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4920 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4923 case 130: /* DFP Compare Ordered */
4924 case 162: /* DFP Test Exponent */
4925 case 194: /* DFP Test Data Class */
4926 case 226: /* DFP Test Data Group */
4927 case 642: /* DFP Compare Unordered */
4928 case 674: /* DFP Test Significance */
4929 case 675: /* DFP Test Significance Immediate */
4930 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4931 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4934 case 66: /* DFP Shift Significand Left Immediate */
4935 case 98: /* DFP Shift Significand Right Immediate */
4936 case 322: /* DFP Decode DPD To BCD */
4937 case 354: /* DFP Extract Biased Exponent */
4938 case 866: /* DFP Insert Biased Exponent */
4939 record_full_arch_list_add_reg (regcache
,
4940 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4942 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4945 case 846: /* Floating Convert From Integer Doubleword Single */
4946 case 974: /* Floating Convert From Integer Doubleword Unsigned
4948 record_full_arch_list_add_reg (regcache
,
4949 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4951 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4952 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4957 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4958 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4962 /* Parse and record instructions of primary opcode-60 at ADDR.
4963 Return 0 if successful. */
4966 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4967 CORE_ADDR addr
, uint32_t insn
)
4969 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4970 int ext
= PPC_EXTOP (insn
);
4974 case 0: /* VSX Scalar Add Single-Precision */
4975 case 32: /* VSX Scalar Add Double-Precision */
4976 case 24: /* VSX Scalar Divide Single-Precision */
4977 case 56: /* VSX Scalar Divide Double-Precision */
4978 case 176: /* VSX Scalar Copy Sign Double-Precision */
4979 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4980 case 41: /* ditto */
4981 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4983 case 160: /* VSX Scalar Maximum Double-Precision */
4984 case 168: /* VSX Scalar Minimum Double-Precision */
4985 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4986 case 57: /* ditto */
4987 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4988 case 25: /* ditto */
4989 case 48: /* VSX Scalar Multiply Double-Precision */
4990 case 16: /* VSX Scalar Multiply Single-Precision */
4991 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4992 case 169: /* ditto */
4993 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4994 case 137: /* ditto */
4995 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4996 case 185: /* ditto */
4997 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4998 case 153: /* ditto */
4999 case 40: /* VSX Scalar Subtract Double-Precision */
5000 case 8: /* VSX Scalar Subtract Single-Precision */
5001 case 96: /* VSX Vector Add Double-Precision */
5002 case 64: /* VSX Vector Add Single-Precision */
5003 case 120: /* VSX Vector Divide Double-Precision */
5004 case 88: /* VSX Vector Divide Single-Precision */
5005 case 97: /* VSX Vector Multiply-Add Double-Precision */
5006 case 105: /* ditto */
5007 case 65: /* VSX Vector Multiply-Add Single-Precision */
5008 case 73: /* ditto */
5009 case 224: /* VSX Vector Maximum Double-Precision */
5010 case 192: /* VSX Vector Maximum Single-Precision */
5011 case 232: /* VSX Vector Minimum Double-Precision */
5012 case 200: /* VSX Vector Minimum Single-Precision */
5013 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5014 case 121: /* ditto */
5015 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5016 case 89: /* ditto */
5017 case 112: /* VSX Vector Multiply Double-Precision */
5018 case 80: /* VSX Vector Multiply Single-Precision */
5019 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5020 case 233: /* ditto */
5021 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5022 case 201: /* ditto */
5023 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5024 case 249: /* ditto */
5025 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5026 case 217: /* ditto */
5027 case 104: /* VSX Vector Subtract Double-Precision */
5028 case 72: /* VSX Vector Subtract Single-Precision */
5029 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5030 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5031 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5032 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5033 case 3: /* VSX Scalar Compare Equal Double-Precision */
5034 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5035 case 19: /* VSX Scalar Compare Greater Than or Equal
5037 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5039 case 240: /* VSX Vector Copy Sign Double-Precision */
5040 case 208: /* VSX Vector Copy Sign Single-Precision */
5041 case 130: /* VSX Logical AND */
5042 case 138: /* VSX Logical AND with Complement */
5043 case 186: /* VSX Logical Equivalence */
5044 case 178: /* VSX Logical NAND */
5045 case 170: /* VSX Logical OR with Complement */
5046 case 162: /* VSX Logical NOR */
5047 case 146: /* VSX Logical OR */
5048 case 154: /* VSX Logical XOR */
5049 case 18: /* VSX Merge High Word */
5050 case 50: /* VSX Merge Low Word */
5051 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5052 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5053 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5054 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5055 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5056 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5057 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5058 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5059 case 216: /* VSX Vector Insert Exponent Single-Precision */
5060 case 248: /* VSX Vector Insert Exponent Double-Precision */
5061 case 26: /* VSX Vector Permute */
5062 case 58: /* VSX Vector Permute Right-indexed */
5063 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5064 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5065 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5066 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5067 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5070 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5071 case 125: /* VSX Vector Test for software Divide Double-Precision */
5072 case 93: /* VSX Vector Test for software Divide Single-Precision */
5073 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5076 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5077 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5078 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5079 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5080 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5084 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5086 case 99: /* VSX Vector Compare Equal To Double-Precision */
5087 case 67: /* VSX Vector Compare Equal To Single-Precision */
5088 case 115: /* VSX Vector Compare Greater Than or
5089 Equal To Double-Precision */
5090 case 83: /* VSX Vector Compare Greater Than or
5091 Equal To Single-Precision */
5092 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5093 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5095 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5096 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5097 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5103 case 265: /* VSX Scalar round Double-Precision to
5104 Single-Precision and Convert to
5105 Single-Precision format */
5106 case 344: /* VSX Scalar truncate Double-Precision to
5107 Integer and Convert to Signed Integer
5108 Doubleword format with Saturate */
5109 case 88: /* VSX Scalar truncate Double-Precision to
5110 Integer and Convert to Signed Integer Word
5111 Format with Saturate */
5112 case 328: /* VSX Scalar truncate Double-Precision integer
5113 and Convert to Unsigned Integer Doubleword
5114 Format with Saturate */
5115 case 72: /* VSX Scalar truncate Double-Precision to
5116 Integer and Convert to Unsigned Integer Word
5117 Format with Saturate */
5118 case 329: /* VSX Scalar Convert Single-Precision to
5119 Double-Precision format */
5120 case 376: /* VSX Scalar Convert Signed Integer
5121 Doubleword to floating-point format and
5122 Round to Double-Precision format */
5123 case 312: /* VSX Scalar Convert Signed Integer
5124 Doubleword to floating-point format and
5125 round to Single-Precision */
5126 case 360: /* VSX Scalar Convert Unsigned Integer
5127 Doubleword to floating-point format and
5128 Round to Double-Precision format */
5129 case 296: /* VSX Scalar Convert Unsigned Integer
5130 Doubleword to floating-point format and
5131 Round to Single-Precision */
5132 case 73: /* VSX Scalar Round to Double-Precision Integer
5133 Using Round to Nearest Away */
5134 case 107: /* VSX Scalar Round to Double-Precision Integer
5135 Exact using Current rounding mode */
5136 case 121: /* VSX Scalar Round to Double-Precision Integer
5137 Using Round toward -Infinity */
5138 case 105: /* VSX Scalar Round to Double-Precision Integer
5139 Using Round toward +Infinity */
5140 case 89: /* VSX Scalar Round to Double-Precision Integer
5141 Using Round toward Zero */
5142 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5143 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5144 case 281: /* VSX Scalar Round to Single-Precision */
5145 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5147 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5149 case 75: /* VSX Scalar Square Root Double-Precision */
5150 case 11: /* VSX Scalar Square Root Single-Precision */
5151 case 393: /* VSX Vector round Double-Precision to
5152 Single-Precision and Convert to
5153 Single-Precision format */
5154 case 472: /* VSX Vector truncate Double-Precision to
5155 Integer and Convert to Signed Integer
5156 Doubleword format with Saturate */
5157 case 216: /* VSX Vector truncate Double-Precision to
5158 Integer and Convert to Signed Integer Word
5159 Format with Saturate */
5160 case 456: /* VSX Vector truncate Double-Precision to
5161 Integer and Convert to Unsigned Integer
5162 Doubleword format with Saturate */
5163 case 200: /* VSX Vector truncate Double-Precision to
5164 Integer and Convert to Unsigned Integer Word
5165 Format with Saturate */
5166 case 457: /* VSX Vector Convert Single-Precision to
5167 Double-Precision format */
5168 case 408: /* VSX Vector truncate Single-Precision to
5169 Integer and Convert to Signed Integer
5170 Doubleword format with Saturate */
5171 case 152: /* VSX Vector truncate Single-Precision to
5172 Integer and Convert to Signed Integer Word
5173 Format with Saturate */
5174 case 392: /* VSX Vector truncate Single-Precision to
5175 Integer and Convert to Unsigned Integer
5176 Doubleword format with Saturate */
5177 case 136: /* VSX Vector truncate Single-Precision to
5178 Integer and Convert to Unsigned Integer Word
5179 Format with Saturate */
5180 case 504: /* VSX Vector Convert and round Signed Integer
5181 Doubleword to Double-Precision format */
5182 case 440: /* VSX Vector Convert and round Signed Integer
5183 Doubleword to Single-Precision format */
5184 case 248: /* VSX Vector Convert Signed Integer Word to
5185 Double-Precision format */
5186 case 184: /* VSX Vector Convert and round Signed Integer
5187 Word to Single-Precision format */
5188 case 488: /* VSX Vector Convert and round Unsigned
5189 Integer Doubleword to Double-Precision format */
5190 case 424: /* VSX Vector Convert and round Unsigned
5191 Integer Doubleword to Single-Precision format */
5192 case 232: /* VSX Vector Convert and round Unsigned
5193 Integer Word to Double-Precision format */
5194 case 168: /* VSX Vector Convert and round Unsigned
5195 Integer Word to Single-Precision format */
5196 case 201: /* VSX Vector Round to Double-Precision
5197 Integer using round to Nearest Away */
5198 case 235: /* VSX Vector Round to Double-Precision
5199 Integer Exact using Current rounding mode */
5200 case 249: /* VSX Vector Round to Double-Precision
5201 Integer using round toward -Infinity */
5202 case 233: /* VSX Vector Round to Double-Precision
5203 Integer using round toward +Infinity */
5204 case 217: /* VSX Vector Round to Double-Precision
5205 Integer using round toward Zero */
5206 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5207 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5208 case 137: /* VSX Vector Round to Single-Precision Integer
5209 Using Round to Nearest Away */
5210 case 171: /* VSX Vector Round to Single-Precision Integer
5211 Exact Using Current rounding mode */
5212 case 185: /* VSX Vector Round to Single-Precision Integer
5213 Using Round toward -Infinity */
5214 case 169: /* VSX Vector Round to Single-Precision Integer
5215 Using Round toward +Infinity */
5216 case 153: /* VSX Vector Round to Single-Precision Integer
5217 Using round toward Zero */
5218 case 202: /* VSX Vector Reciprocal Square Root Estimate
5220 case 138: /* VSX Vector Reciprocal Square Root Estimate
5222 case 203: /* VSX Vector Square Root Double-Precision */
5223 case 139: /* VSX Vector Square Root Single-Precision */
5224 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5226 case 345: /* VSX Scalar Absolute Value Double-Precision */
5227 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5228 Vector Single-Precision format Non-signalling */
5229 case 331: /* VSX Scalar Convert Single-Precision to
5230 Double-Precision format Non-signalling */
5231 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5232 case 377: /* VSX Scalar Negate Double-Precision */
5233 case 473: /* VSX Vector Absolute Value Double-Precision */
5234 case 409: /* VSX Vector Absolute Value Single-Precision */
5235 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5236 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5237 case 505: /* VSX Vector Negate Double-Precision */
5238 case 441: /* VSX Vector Negate Single-Precision */
5239 case 164: /* VSX Splat Word */
5240 case 165: /* VSX Vector Extract Unsigned Word */
5241 case 181: /* VSX Vector Insert Word */
5242 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5245 case 298: /* VSX Scalar Test Data Class Single-Precision */
5246 case 362: /* VSX Scalar Test Data Class Double-Precision */
5247 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5249 case 106: /* VSX Scalar Test for software Square Root
5251 case 234: /* VSX Vector Test for software Square Root
5253 case 170: /* VSX Vector Test for software Square Root
5255 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5259 switch (PPC_FIELD (insn
, 11, 5))
5261 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5262 case 1: /* VSX Scalar Extract Significand Double-Precision */
5263 record_full_arch_list_add_reg (regcache
,
5264 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5266 case 16: /* VSX Scalar Convert Half-Precision format to
5267 Double-Precision format */
5268 case 17: /* VSX Scalar round & Convert Double-Precision format
5269 to Half-Precision format */
5270 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5271 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5277 switch (PPC_FIELD (insn
, 11, 5))
5279 case 24: /* VSX Vector Convert Half-Precision format to
5280 Single-Precision format */
5281 case 25: /* VSX Vector round and Convert Single-Precision format
5282 to Half-Precision format */
5283 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5285 case 0: /* VSX Vector Extract Exponent Double-Precision */
5286 case 1: /* VSX Vector Extract Significand Double-Precision */
5287 case 7: /* VSX Vector Byte-Reverse Halfword */
5288 case 8: /* VSX Vector Extract Exponent Single-Precision */
5289 case 9: /* VSX Vector Extract Significand Single-Precision */
5290 case 15: /* VSX Vector Byte-Reverse Word */
5291 case 23: /* VSX Vector Byte-Reverse Doubleword */
5292 case 31: /* VSX Vector Byte-Reverse Quadword */
5293 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5301 case 360: /* VSX Vector Splat Immediate Byte */
5302 if (PPC_FIELD (insn
, 11, 2) == 0)
5304 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5308 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5309 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5313 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5315 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5319 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5320 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5324 /* Parse and record instructions of primary opcode-61 at ADDR.
5325 Return 0 if successful. */
5328 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5329 CORE_ADDR addr
, uint32_t insn
)
5331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5337 case 0: /* Store Floating-Point Double Pair */
5338 case 2: /* Store VSX Scalar Doubleword */
5339 case 3: /* Store VSX Scalar Single */
5340 if (PPC_RA (insn
) != 0)
5341 regcache_raw_read_unsigned (regcache
,
5342 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5344 ea
+= PPC_DS (insn
) << 2;
5347 case 0: /* Store Floating-Point Double Pair */
5350 case 2: /* Store VSX Scalar Doubleword */
5353 case 3: /* Store VSX Scalar Single */
5359 record_full_arch_list_add_mem (ea
, size
);
5365 case 1: /* Load VSX Vector */
5366 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5368 case 5: /* Store VSX Vector */
5369 if (PPC_RA (insn
) != 0)
5370 regcache_raw_read_unsigned (regcache
,
5371 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5373 ea
+= PPC_DQ (insn
) << 4;
5374 record_full_arch_list_add_mem (ea
, 16);
5378 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5379 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5383 /* Parse and record instructions of primary opcode-63 at ADDR.
5384 Return 0 if successful. */
5387 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5388 CORE_ADDR addr
, uint32_t insn
)
5390 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5391 int ext
= PPC_EXTOP (insn
);
5396 case 18: /* Floating Divide */
5397 case 20: /* Floating Subtract */
5398 case 21: /* Floating Add */
5399 case 22: /* Floating Square Root */
5400 case 24: /* Floating Reciprocal Estimate */
5401 case 25: /* Floating Multiply */
5402 case 26: /* Floating Reciprocal Square Root Estimate */
5403 case 28: /* Floating Multiply-Subtract */
5404 case 29: /* Floating Multiply-Add */
5405 case 30: /* Floating Negative Multiply-Subtract */
5406 case 31: /* Floating Negative Multiply-Add */
5407 record_full_arch_list_add_reg (regcache
,
5408 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5410 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5411 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5414 case 23: /* Floating Select */
5415 record_full_arch_list_add_reg (regcache
,
5416 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5418 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5424 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5425 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5427 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5428 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5434 case 2: /* DFP Add Quad */
5435 case 3: /* DFP Quantize Quad */
5436 case 34: /* DFP Multiply Quad */
5437 case 35: /* DFP Reround Quad */
5438 case 67: /* DFP Quantize Immediate Quad */
5439 case 99: /* DFP Round To FP Integer With Inexact Quad */
5440 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5441 case 258: /* DFP Convert To DFP Extended Quad */
5442 case 514: /* DFP Subtract Quad */
5443 case 546: /* DFP Divide Quad */
5444 case 770: /* DFP Round To DFP Long Quad */
5445 case 802: /* DFP Convert From Fixed Quad */
5446 case 834: /* DFP Encode BCD To DPD Quad */
5448 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5449 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5450 record_full_arch_list_add_reg (regcache
, tmp
);
5451 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5452 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5455 case 130: /* DFP Compare Ordered Quad */
5456 case 162: /* DFP Test Exponent Quad */
5457 case 194: /* DFP Test Data Class Quad */
5458 case 226: /* DFP Test Data Group Quad */
5459 case 642: /* DFP Compare Unordered Quad */
5460 case 674: /* DFP Test Significance Quad */
5461 case 675: /* DFP Test Significance Immediate Quad */
5462 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5463 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5466 case 66: /* DFP Shift Significand Left Immediate Quad */
5467 case 98: /* DFP Shift Significand Right Immediate Quad */
5468 case 322: /* DFP Decode DPD To BCD Quad */
5469 case 866: /* DFP Insert Biased Exponent Quad */
5470 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5471 record_full_arch_list_add_reg (regcache
, tmp
);
5472 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5474 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5477 case 290: /* DFP Convert To Fixed Quad */
5478 record_full_arch_list_add_reg (regcache
,
5479 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5481 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5482 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5485 case 354: /* DFP Extract Biased Exponent Quad */
5486 record_full_arch_list_add_reg (regcache
,
5487 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5489 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5492 case 12: /* Floating Round to Single-Precision */
5493 case 14: /* Floating Convert To Integer Word */
5494 case 15: /* Floating Convert To Integer Word
5495 with round toward Zero */
5496 case 142: /* Floating Convert To Integer Word Unsigned */
5497 case 143: /* Floating Convert To Integer Word Unsigned
5498 with round toward Zero */
5499 case 392: /* Floating Round to Integer Nearest */
5500 case 424: /* Floating Round to Integer Toward Zero */
5501 case 456: /* Floating Round to Integer Plus */
5502 case 488: /* Floating Round to Integer Minus */
5503 case 814: /* Floating Convert To Integer Doubleword */
5504 case 815: /* Floating Convert To Integer Doubleword
5505 with round toward Zero */
5506 case 846: /* Floating Convert From Integer Doubleword */
5507 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5508 case 943: /* Floating Convert To Integer Doubleword Unsigned
5509 with round toward Zero */
5510 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5511 record_full_arch_list_add_reg (regcache
,
5512 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5514 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5515 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5519 switch (PPC_FIELD (insn
, 11, 5))
5521 case 1: /* Move From FPSCR & Clear Enables */
5522 case 20: /* Move From FPSCR Control & set DRN */
5523 case 21: /* Move From FPSCR Control & set DRN Immediate */
5524 case 22: /* Move From FPSCR Control & set RN */
5525 case 23: /* Move From FPSCR Control & set RN Immediate */
5526 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5527 case 0: /* Move From FPSCR */
5528 case 24: /* Move From FPSCR Lightweight */
5529 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5530 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5531 record_full_arch_list_add_reg (regcache
,
5532 tdep
->ppc_fp0_regnum
5538 case 8: /* Floating Copy Sign */
5539 case 40: /* Floating Negate */
5540 case 72: /* Floating Move Register */
5541 case 136: /* Floating Negative Absolute Value */
5542 case 264: /* Floating Absolute Value */
5543 record_full_arch_list_add_reg (regcache
,
5544 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5546 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5549 case 838: /* Floating Merge Odd Word */
5550 case 966: /* Floating Merge Even Word */
5551 record_full_arch_list_add_reg (regcache
,
5552 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5555 case 38: /* Move To FPSCR Bit 1 */
5556 case 70: /* Move To FPSCR Bit 0 */
5557 case 134: /* Move To FPSCR Field Immediate */
5558 case 711: /* Move To FPSCR Fields */
5560 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5561 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5564 case 0: /* Floating Compare Unordered */
5565 case 32: /* Floating Compare Ordered */
5566 case 64: /* Move to Condition Register from FPSCR */
5567 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5568 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5569 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5570 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5571 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5573 case 128: /* Floating Test for software Divide */
5574 case 160: /* Floating Test for software Square Root */
5575 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5578 case 4: /* VSX Scalar Add Quad-Precision */
5579 case 36: /* VSX Scalar Multiply Quad-Precision */
5580 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5581 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5582 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5583 case 484: /* VSX Scalar Negative Multiply-Subtract
5585 case 516: /* VSX Scalar Subtract Quad-Precision */
5586 case 548: /* VSX Scalar Divide Quad-Precision */
5587 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5589 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5590 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5591 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5595 switch (PPC_FIELD (insn
, 11, 5))
5597 case 27: /* VSX Scalar Square Root Quad-Precision */
5598 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5600 case 0: /* VSX Scalar Absolute Quad-Precision */
5601 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5602 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5603 case 16: /* VSX Scalar Negate Quad-Precision */
5604 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5605 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5611 switch (PPC_FIELD (insn
, 11, 5))
5613 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5614 to Unsigned Word format */
5615 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5616 Quad-Precision format */
5617 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5618 to Signed Word format */
5619 case 10: /* VSX Scalar Convert Signed Doubleword format to
5620 Quad-Precision format */
5621 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5622 to Unsigned Doubleword format */
5623 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5624 Double-Precision format */
5625 case 22: /* VSX Scalar Convert Double-Precision format to
5626 Quad-Precision format */
5627 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5628 to Signed Doubleword format */
5629 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5630 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5635 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5636 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5640 /* Parse the current instruction and record the values of the registers and
5641 memory that will be changed in current instruction to "record_arch_list".
5642 Return -1 if something wrong. */
5645 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5648 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5649 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5653 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5654 op6
= PPC_OP6 (insn
);
5658 case 2: /* Trap Doubleword Immediate */
5659 case 3: /* Trap Word Immediate */
5664 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5668 case 17: /* System call */
5669 if (PPC_LEV (insn
) != 0)
5672 if (tdep
->ppc_syscall_record
!= NULL
)
5674 if (tdep
->ppc_syscall_record (regcache
) != 0)
5679 printf_unfiltered (_("no syscall record support\n"));
5684 case 7: /* Multiply Low Immediate */
5685 record_full_arch_list_add_reg (regcache
,
5686 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5689 case 8: /* Subtract From Immediate Carrying */
5690 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5691 record_full_arch_list_add_reg (regcache
,
5692 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5695 case 10: /* Compare Logical Immediate */
5696 case 11: /* Compare Immediate */
5697 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5700 case 13: /* Add Immediate Carrying and Record */
5701 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5703 case 12: /* Add Immediate Carrying */
5704 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5706 case 14: /* Add Immediate */
5707 case 15: /* Add Immediate Shifted */
5708 record_full_arch_list_add_reg (regcache
,
5709 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5712 case 16: /* Branch Conditional */
5713 if ((PPC_BO (insn
) & 0x4) == 0)
5714 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5716 case 18: /* Branch */
5718 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5722 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5726 case 20: /* Rotate Left Word Immediate then Mask Insert */
5727 case 21: /* Rotate Left Word Immediate then AND with Mask */
5728 case 23: /* Rotate Left Word then AND with Mask */
5729 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5730 /* Rotate Left Doubleword Immediate then Clear Right */
5731 /* Rotate Left Doubleword Immediate then Clear */
5732 /* Rotate Left Doubleword then Clear Left */
5733 /* Rotate Left Doubleword then Clear Right */
5734 /* Rotate Left Doubleword Immediate then Mask Insert */
5736 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5737 record_full_arch_list_add_reg (regcache
,
5738 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5741 case 28: /* AND Immediate */
5742 case 29: /* AND Immediate Shifted */
5743 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5745 case 24: /* OR Immediate */
5746 case 25: /* OR Immediate Shifted */
5747 case 26: /* XOR Immediate */
5748 case 27: /* XOR Immediate Shifted */
5749 record_full_arch_list_add_reg (regcache
,
5750 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5754 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5758 case 33: /* Load Word and Zero with Update */
5759 case 35: /* Load Byte and Zero with Update */
5760 case 41: /* Load Halfword and Zero with Update */
5761 case 43: /* Load Halfword Algebraic with Update */
5762 record_full_arch_list_add_reg (regcache
,
5763 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5765 case 32: /* Load Word and Zero */
5766 case 34: /* Load Byte and Zero */
5767 case 40: /* Load Halfword and Zero */
5768 case 42: /* Load Halfword Algebraic */
5769 record_full_arch_list_add_reg (regcache
,
5770 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5773 case 46: /* Load Multiple Word */
5774 for (i
= PPC_RT (insn
); i
< 32; i
++)
5775 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5778 case 56: /* Load Quadword */
5779 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5780 record_full_arch_list_add_reg (regcache
, tmp
);
5781 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5784 case 49: /* Load Floating-Point Single with Update */
5785 case 51: /* Load Floating-Point Double with Update */
5786 record_full_arch_list_add_reg (regcache
,
5787 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5789 case 48: /* Load Floating-Point Single */
5790 case 50: /* Load Floating-Point Double */
5791 record_full_arch_list_add_reg (regcache
,
5792 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5795 case 47: /* Store Multiple Word */
5799 if (PPC_RA (insn
) != 0)
5800 regcache_raw_read_unsigned (regcache
,
5801 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5804 addr
+= PPC_D (insn
);
5805 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5809 case 37: /* Store Word with Update */
5810 case 39: /* Store Byte with Update */
5811 case 45: /* Store Halfword with Update */
5812 case 53: /* Store Floating-Point Single with Update */
5813 case 55: /* Store Floating-Point Double with Update */
5814 record_full_arch_list_add_reg (regcache
,
5815 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5817 case 36: /* Store Word */
5818 case 38: /* Store Byte */
5819 case 44: /* Store Halfword */
5820 case 52: /* Store Floating-Point Single */
5821 case 54: /* Store Floating-Point Double */
5826 if (PPC_RA (insn
) != 0)
5827 regcache_raw_read_unsigned (regcache
,
5828 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5830 addr
+= PPC_D (insn
);
5832 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5834 else if (op6
== 54 || op6
== 55)
5836 else if (op6
== 44 || op6
== 45)
5838 else if (op6
== 38 || op6
== 39)
5843 record_full_arch_list_add_mem (addr
, size
);
5850 case 0: /* Load Floating-Point Double Pair */
5851 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5852 record_full_arch_list_add_reg (regcache
, tmp
);
5853 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5855 case 2: /* Load VSX Scalar Doubleword */
5856 case 3: /* Load VSX Scalar Single */
5857 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5864 case 58: /* Load Doubleword */
5865 /* Load Doubleword with Update */
5866 /* Load Word Algebraic */
5867 if (PPC_FIELD (insn
, 30, 2) > 2)
5870 record_full_arch_list_add_reg (regcache
,
5871 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5872 if (PPC_BIT (insn
, 31))
5873 record_full_arch_list_add_reg (regcache
,
5874 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5878 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5883 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5888 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5892 case 62: /* Store Doubleword */
5893 /* Store Doubleword with Update */
5894 /* Store Quadword with Update */
5898 int sub2
= PPC_FIELD (insn
, 30, 2);
5903 if (PPC_RA (insn
) != 0)
5904 regcache_raw_read_unsigned (regcache
,
5905 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5908 size
= (sub2
== 2) ? 16 : 8;
5910 addr
+= PPC_DS (insn
) << 2;
5911 record_full_arch_list_add_mem (addr
, size
);
5913 if (op6
== 62 && sub2
== 1)
5914 record_full_arch_list_add_reg (regcache
,
5915 tdep
->ppc_gp0_regnum
+
5922 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5928 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5929 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5933 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5935 if (record_full_arch_list_add_end ())
5940 /* Initialize the current architecture based on INFO. If possible, re-use an
5941 architecture from ARCHES, which is a list of architectures already created
5942 during this debugging session.
5944 Called e.g. at program startup, when reading a core file, and when reading
5947 static struct gdbarch
*
5948 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5950 struct gdbarch
*gdbarch
;
5951 struct gdbarch_tdep
*tdep
;
5952 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5953 enum bfd_architecture arch
;
5956 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5958 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5959 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5960 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5962 int tdesc_wordsize
= -1;
5963 const struct target_desc
*tdesc
= info
.target_desc
;
5964 struct tdesc_arch_data
*tdesc_data
= NULL
;
5965 int num_pseudoregs
= 0;
5968 /* INFO may refer to a binary that is not of the PowerPC architecture,
5969 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5970 In this case, we must not attempt to infer properties of the (PowerPC
5971 side) of the target system from properties of that executable. Trust
5972 the target description instead. */
5974 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5975 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5978 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5979 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5981 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5982 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5984 /* Check word size. If INFO is from a binary file, infer it from
5985 that, else choose a likely default. */
5986 if (from_xcoff_exec
)
5988 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5993 else if (from_elf_exec
)
5995 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6000 else if (tdesc_has_registers (tdesc
))
6004 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6005 wordsize
= (info
.bfd_arch_info
->bits_per_word
6006 / info
.bfd_arch_info
->bits_per_byte
);
6011 /* Get the architecture and machine from the BFD. */
6012 arch
= info
.bfd_arch_info
->arch
;
6013 mach
= info
.bfd_arch_info
->mach
;
6015 /* For e500 executables, the apuinfo section is of help here. Such
6016 section contains the identifier and revision number of each
6017 Application-specific Processing Unit that is present on the
6018 chip. The content of the section is determined by the assembler
6019 which looks at each instruction and determines which unit (and
6020 which version of it) can execute it. Grovel through the section
6021 looking for relevant e500 APUs. */
6023 if (bfd_uses_spe_extensions (info
.abfd
))
6025 arch
= info
.bfd_arch_info
->arch
;
6026 mach
= bfd_mach_ppc_e500
;
6027 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6028 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6031 /* Find a default target description which describes our register
6032 layout, if we do not already have one. */
6033 if (! tdesc_has_registers (tdesc
))
6035 const struct variant
*v
;
6037 /* Choose variant. */
6038 v
= find_variant_by_arch (arch
, mach
);
6045 gdb_assert (tdesc_has_registers (tdesc
));
6047 /* Check any target description for validity. */
6048 if (tdesc_has_registers (tdesc
))
6050 static const char *const gprs
[] = {
6051 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6052 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6053 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6054 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6056 const struct tdesc_feature
*feature
;
6058 static const char *const msr_names
[] = { "msr", "ps" };
6059 static const char *const cr_names
[] = { "cr", "cnd" };
6060 static const char *const ctr_names
[] = { "ctr", "cnt" };
6062 feature
= tdesc_find_feature (tdesc
,
6063 "org.gnu.gdb.power.core");
6064 if (feature
== NULL
)
6067 tdesc_data
= tdesc_data_alloc ();
6070 for (i
= 0; i
< ppc_num_gprs
; i
++)
6071 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
6072 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
6074 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
6076 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
6079 /* Allow alternate names for these registers, to accomodate GDB's
6081 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6082 PPC_MSR_REGNUM
, msr_names
);
6083 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6084 PPC_CR_REGNUM
, cr_names
);
6085 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6086 PPC_CTR_REGNUM
, ctr_names
);
6090 tdesc_data_cleanup (tdesc_data
);
6094 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
6097 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
6099 wordsize
= tdesc_wordsize
;
6101 feature
= tdesc_find_feature (tdesc
,
6102 "org.gnu.gdb.power.fpu");
6103 if (feature
!= NULL
)
6105 static const char *const fprs
[] = {
6106 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6107 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6108 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6109 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6112 for (i
= 0; i
< ppc_num_fprs
; i
++)
6113 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6114 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6115 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6116 PPC_FPSCR_REGNUM
, "fpscr");
6120 tdesc_data_cleanup (tdesc_data
);
6128 /* The DFP pseudo-registers will be available when there are floating
6130 have_dfp
= have_fpu
;
6132 feature
= tdesc_find_feature (tdesc
,
6133 "org.gnu.gdb.power.altivec");
6134 if (feature
!= NULL
)
6136 static const char *const vector_regs
[] = {
6137 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6138 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6139 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6140 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6144 for (i
= 0; i
< ppc_num_gprs
; i
++)
6145 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6148 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6149 PPC_VSCR_REGNUM
, "vscr");
6150 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6151 PPC_VRSAVE_REGNUM
, "vrsave");
6153 if (have_spe
|| !valid_p
)
6155 tdesc_data_cleanup (tdesc_data
);
6163 /* Check for POWER7 VSX registers support. */
6164 feature
= tdesc_find_feature (tdesc
,
6165 "org.gnu.gdb.power.vsx");
6167 if (feature
!= NULL
)
6169 static const char *const vsx_regs
[] = {
6170 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6171 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6172 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6173 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6174 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6180 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6181 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6182 PPC_VSR0_UPPER_REGNUM
+ i
,
6186 tdesc_data_cleanup (tdesc_data
);
6195 /* On machines supporting the SPE APU, the general-purpose registers
6196 are 64 bits long. There are SIMD vector instructions to treat them
6197 as pairs of floats, but the rest of the instruction set treats them
6198 as 32-bit registers, and only operates on their lower halves.
6200 In the GDB regcache, we treat their high and low halves as separate
6201 registers. The low halves we present as the general-purpose
6202 registers, and then we have pseudo-registers that stitch together
6203 the upper and lower halves and present them as pseudo-registers.
6205 Thus, the target description is expected to supply the upper
6206 halves separately. */
6208 feature
= tdesc_find_feature (tdesc
,
6209 "org.gnu.gdb.power.spe");
6210 if (feature
!= NULL
)
6212 static const char *const upper_spe
[] = {
6213 "ev0h", "ev1h", "ev2h", "ev3h",
6214 "ev4h", "ev5h", "ev6h", "ev7h",
6215 "ev8h", "ev9h", "ev10h", "ev11h",
6216 "ev12h", "ev13h", "ev14h", "ev15h",
6217 "ev16h", "ev17h", "ev18h", "ev19h",
6218 "ev20h", "ev21h", "ev22h", "ev23h",
6219 "ev24h", "ev25h", "ev26h", "ev27h",
6220 "ev28h", "ev29h", "ev30h", "ev31h"
6224 for (i
= 0; i
< ppc_num_gprs
; i
++)
6225 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6226 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6228 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6229 PPC_SPE_ACC_REGNUM
, "acc");
6230 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6231 PPC_SPE_FSCR_REGNUM
, "spefscr");
6233 if (have_mq
|| have_fpu
|| !valid_p
)
6235 tdesc_data_cleanup (tdesc_data
);
6244 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6245 complain for a 32-bit binary on a 64-bit target; we do not yet
6246 support that. For instance, the 32-bit ABI routines expect
6249 As long as there isn't an explicit target description, we'll
6250 choose one based on the BFD architecture and get a word size
6251 matching the binary (probably powerpc:common or
6252 powerpc:common64). So there is only trouble if a 64-bit target
6253 supplies a 64-bit description while debugging a 32-bit
6255 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6257 tdesc_data_cleanup (tdesc_data
);
6264 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6267 elf_abi
= POWERPC_ELF_V1
;
6270 elf_abi
= POWERPC_ELF_V2
;
6277 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6279 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6280 Tag_GNU_Power_ABI_FP
))
6283 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6286 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6293 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6295 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6296 Tag_GNU_Power_ABI_Vector
))
6299 vector_abi
= POWERPC_VEC_GENERIC
;
6302 vector_abi
= POWERPC_VEC_ALTIVEC
;
6305 vector_abi
= POWERPC_VEC_SPE
;
6313 /* At this point, the only supported ELF-based 64-bit little-endian
6314 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6315 default. All other supported ELF-based operating systems use the
6316 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6317 e.g. because we run a legacy binary, or have attached to a process
6318 and have not found any associated binary file, set the default
6319 according to this heuristic. */
6320 if (elf_abi
== POWERPC_ELF_AUTO
)
6322 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6323 elf_abi
= POWERPC_ELF_V2
;
6325 elf_abi
= POWERPC_ELF_V1
;
6328 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6330 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6333 soft_float
= !have_fpu
;
6335 /* If we have a hard float binary or setting but no floating point
6336 registers, downgrade to soft float anyway. We're still somewhat
6337 useful in this scenario. */
6338 if (!soft_float
&& !have_fpu
)
6341 /* Similarly for vector registers. */
6342 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6343 vector_abi
= POWERPC_VEC_GENERIC
;
6345 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6346 vector_abi
= POWERPC_VEC_GENERIC
;
6348 if (vector_abi
== POWERPC_VEC_AUTO
)
6351 vector_abi
= POWERPC_VEC_ALTIVEC
;
6353 vector_abi
= POWERPC_VEC_SPE
;
6355 vector_abi
= POWERPC_VEC_GENERIC
;
6358 /* Do not limit the vector ABI based on available hardware, since we
6359 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6361 /* Find a candidate among extant architectures. */
6362 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6364 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6366 /* Word size in the various PowerPC bfd_arch_info structs isn't
6367 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6368 separate word size check. */
6369 tdep
= gdbarch_tdep (arches
->gdbarch
);
6370 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6372 if (tdep
&& tdep
->soft_float
!= soft_float
)
6374 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6376 if (tdep
&& tdep
->wordsize
== wordsize
)
6378 if (tdesc_data
!= NULL
)
6379 tdesc_data_cleanup (tdesc_data
);
6380 return arches
->gdbarch
;
6384 /* None found, create a new architecture from INFO, whose bfd_arch_info
6385 validity depends on the source:
6386 - executable useless
6387 - rs6000_host_arch() good
6389 - "set arch" trust blindly
6390 - GDB startup useless but harmless */
6392 tdep
= XCNEW (struct gdbarch_tdep
);
6393 tdep
->wordsize
= wordsize
;
6394 tdep
->elf_abi
= elf_abi
;
6395 tdep
->soft_float
= soft_float
;
6396 tdep
->vector_abi
= vector_abi
;
6398 gdbarch
= gdbarch_alloc (&info
, tdep
);
6400 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6401 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6402 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6403 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6404 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6405 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6406 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6407 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6409 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6410 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6411 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6412 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6413 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6414 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6415 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6416 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6418 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6419 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6420 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6421 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6423 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6424 GDB traditionally called it "ps", though, so let GDB add an
6426 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6429 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6431 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6433 /* Set lr_frame_offset. */
6435 tdep
->lr_frame_offset
= 16;
6437 tdep
->lr_frame_offset
= 4;
6439 if (have_spe
|| have_dfp
|| have_vsx
)
6441 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6442 set_gdbarch_pseudo_register_write (gdbarch
,
6443 rs6000_pseudo_register_write
);
6444 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6445 rs6000_ax_pseudo_register_collect
);
6448 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6450 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6452 /* Select instruction printer. */
6453 if (arch
== bfd_arch_rs6000
)
6454 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
6456 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
6458 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6461 num_pseudoregs
+= 32;
6463 num_pseudoregs
+= 16;
6465 /* Include both VSX and Extended FP registers. */
6466 num_pseudoregs
+= 96;
6468 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6470 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6471 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6472 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6473 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6474 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6475 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6476 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6477 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6478 set_gdbarch_char_signed (gdbarch
, 0);
6480 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6483 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6485 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6486 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6487 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6489 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6490 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6493 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6494 else if (wordsize
== 8)
6495 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6497 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6498 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6499 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6501 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6503 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6504 rs6000_breakpoint::kind_from_pc
);
6505 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6506 rs6000_breakpoint::bp_from_kind
);
6508 /* The value of symbols of type N_SO and N_FUN maybe null when
6510 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6512 /* Handles single stepping of atomic sequences. */
6513 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6515 /* Not sure on this. FIXMEmgo */
6516 set_gdbarch_frame_args_skip (gdbarch
, 8);
6518 /* Helpers for function argument information. */
6519 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6522 set_gdbarch_in_solib_return_trampoline
6523 (gdbarch
, rs6000_in_solib_return_trampoline
);
6524 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6526 /* Hook in the DWARF CFI frame unwinder. */
6527 dwarf2_append_unwinders (gdbarch
);
6528 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6530 /* Frame handling. */
6531 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6533 /* Setup displaced stepping. */
6534 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6535 ppc_displaced_step_copy_insn
);
6536 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6537 ppc_displaced_step_hw_singlestep
);
6538 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6539 set_gdbarch_displaced_step_free_closure (gdbarch
,
6540 simple_displaced_step_free_closure
);
6541 set_gdbarch_displaced_step_location (gdbarch
,
6542 displaced_step_at_entry_point
);
6544 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6546 /* Hook in ABI-specific overrides, if they have been registered. */
6547 info
.target_desc
= tdesc
;
6548 info
.tdep_info
= tdesc_data
;
6549 gdbarch_init_osabi (info
, gdbarch
);
6553 case GDB_OSABI_LINUX
:
6554 case GDB_OSABI_NETBSD
:
6555 case GDB_OSABI_UNKNOWN
:
6556 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6557 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6558 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6559 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6560 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6563 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6565 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6566 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6567 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6568 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6569 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6572 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6573 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6574 rs6000_pseudo_register_reggroup_p
);
6575 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6577 /* Override the normal target description method to make the SPE upper
6578 halves anonymous. */
6579 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6581 /* Choose register numbers for all supported pseudo-registers. */
6582 tdep
->ppc_ev0_regnum
= -1;
6583 tdep
->ppc_dl0_regnum
= -1;
6584 tdep
->ppc_vsr0_regnum
= -1;
6585 tdep
->ppc_efpr0_regnum
= -1;
6587 cur_reg
= gdbarch_num_regs (gdbarch
);
6591 tdep
->ppc_ev0_regnum
= cur_reg
;
6596 tdep
->ppc_dl0_regnum
= cur_reg
;
6601 tdep
->ppc_vsr0_regnum
= cur_reg
;
6603 tdep
->ppc_efpr0_regnum
= cur_reg
;
6607 gdb_assert (gdbarch_num_regs (gdbarch
)
6608 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6610 /* Register the ravenscar_arch_ops. */
6611 if (mach
== bfd_mach_ppc_e500
)
6612 register_e500_ravenscar_ops (gdbarch
);
6614 register_ppc_ravenscar_ops (gdbarch
);
6616 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
6617 set_gdbarch_valid_disassembler_options (gdbarch
,
6618 disassembler_options_powerpc ());
6624 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6626 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6631 /* FIXME: Dump gdbarch_tdep. */
6634 /* PowerPC-specific commands. */
6637 set_powerpc_command (char *args
, int from_tty
)
6639 printf_unfiltered (_("\
6640 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6641 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6645 show_powerpc_command (char *args
, int from_tty
)
6647 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6651 powerpc_set_soft_float (char *args
, int from_tty
,
6652 struct cmd_list_element
*c
)
6654 struct gdbarch_info info
;
6656 /* Update the architecture. */
6657 gdbarch_info_init (&info
);
6658 if (!gdbarch_update_p (info
))
6659 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6663 powerpc_set_vector_abi (char *args
, int from_tty
,
6664 struct cmd_list_element
*c
)
6666 struct gdbarch_info info
;
6669 for (vector_abi
= POWERPC_VEC_AUTO
;
6670 vector_abi
!= POWERPC_VEC_LAST
;
6672 if (strcmp (powerpc_vector_abi_string
,
6673 powerpc_vector_strings
[vector_abi
]) == 0)
6675 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6679 if (vector_abi
== POWERPC_VEC_LAST
)
6680 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6681 powerpc_vector_abi_string
);
6683 /* Update the architecture. */
6684 gdbarch_info_init (&info
);
6685 if (!gdbarch_update_p (info
))
6686 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6689 /* Show the current setting of the exact watchpoints flag. */
6692 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6693 struct cmd_list_element
*c
,
6696 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6699 /* Read a PPC instruction from memory. */
6702 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6704 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6705 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6707 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6710 /* Return non-zero if the instructions at PC match the series
6711 described in PATTERN, or zero otherwise. PATTERN is an array of
6712 'struct ppc_insn_pattern' objects, terminated by an entry whose
6715 When the match is successful, fill INSN[i] with what PATTERN[i]
6716 matched. If PATTERN[i] is optional, and the instruction wasn't
6717 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6718 INSN should have as many elements as PATTERN. Note that, if
6719 PATTERN contains optional instructions which aren't present in
6720 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6721 i'th instruction in memory. */
6724 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6725 struct ppc_insn_pattern
*pattern
,
6726 unsigned int *insns
)
6731 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6734 insn
= read_insn (frame
, pc
);
6736 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6742 else if (!pattern
[i
].optional
)
6749 /* Return the 'd' field of the d-form instruction INSN, properly
6753 ppc_insn_d_field (unsigned int insn
)
6755 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6758 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6759 zero bits concatenated at the right, and properly
6763 ppc_insn_ds_field (unsigned int insn
)
6765 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6768 /* Initialization code. */
6770 /* -Wmissing-prototypes */
6771 extern initialize_file_ftype _initialize_rs6000_tdep
;
6774 _initialize_rs6000_tdep (void)
6776 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6777 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6779 /* Initialize the standard target descriptions. */
6780 initialize_tdesc_powerpc_32 ();
6781 initialize_tdesc_powerpc_altivec32 ();
6782 initialize_tdesc_powerpc_vsx32 ();
6783 initialize_tdesc_powerpc_403 ();
6784 initialize_tdesc_powerpc_403gc ();
6785 initialize_tdesc_powerpc_405 ();
6786 initialize_tdesc_powerpc_505 ();
6787 initialize_tdesc_powerpc_601 ();
6788 initialize_tdesc_powerpc_602 ();
6789 initialize_tdesc_powerpc_603 ();
6790 initialize_tdesc_powerpc_604 ();
6791 initialize_tdesc_powerpc_64 ();
6792 initialize_tdesc_powerpc_altivec64 ();
6793 initialize_tdesc_powerpc_vsx64 ();
6794 initialize_tdesc_powerpc_7400 ();
6795 initialize_tdesc_powerpc_750 ();
6796 initialize_tdesc_powerpc_860 ();
6797 initialize_tdesc_powerpc_e500 ();
6798 initialize_tdesc_rs6000 ();
6800 /* Add root prefix command for all "set powerpc"/"show powerpc"
6802 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6803 _("Various PowerPC-specific commands."),
6804 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6806 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6807 _("Various PowerPC-specific commands."),
6808 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6810 /* Add a command to allow the user to force the ABI. */
6811 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6812 &powerpc_soft_float_global
,
6813 _("Set whether to use a soft-float ABI."),
6814 _("Show whether to use a soft-float ABI."),
6816 powerpc_set_soft_float
, NULL
,
6817 &setpowerpccmdlist
, &showpowerpccmdlist
);
6819 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6820 &powerpc_vector_abi_string
,
6821 _("Set the vector ABI."),
6822 _("Show the vector ABI."),
6823 NULL
, powerpc_set_vector_abi
, NULL
,
6824 &setpowerpccmdlist
, &showpowerpccmdlist
);
6826 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6827 &target_exact_watchpoints
,
6829 Set whether to use just one debug register for watchpoints on scalars."),
6831 Show whether to use just one debug register for watchpoints on scalars."),
6833 If true, GDB will use only one debug register when watching a variable of\n\
6834 scalar type, thus assuming that the variable is accessed through the address\n\
6835 of its first byte."),
6836 NULL
, show_powerpc_exact_watchpoints
,
6837 &setpowerpccmdlist
, &showpowerpccmdlist
);