1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* Holds the current set of options to be passed to the disassembler. */
110 static char *powerpc_disassembler_options
;
112 /* The list of available "set powerpc ..." and "show powerpc ..."
114 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
115 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
117 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
119 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
120 static const char *const powerpc_vector_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
131 static const char *powerpc_vector_abi_string
= "auto";
133 /* To be used by skip_prologue. */
135 struct rs6000_framedata
137 int offset
; /* total size of frame --- the distance
138 by which we decrement sp to allocate
140 int saved_gpr
; /* smallest # of saved gpr */
141 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
142 int saved_fpr
; /* smallest # of saved fpr */
143 int saved_vr
; /* smallest # of saved vr */
144 int saved_ev
; /* smallest # of saved ev */
145 int alloca_reg
; /* alloca register number (frame ptr) */
146 char frameless
; /* true if frameless functions. */
147 char nosavedpc
; /* true if pc not saved. */
148 char used_bl
; /* true if link register clobbered */
149 int gpr_offset
; /* offset of saved gprs from prev sp */
150 int fpr_offset
; /* offset of saved fprs from prev sp */
151 int vr_offset
; /* offset of saved vrs from prev sp */
152 int ev_offset
; /* offset of saved evs from prev sp */
153 int lr_offset
; /* offset of saved lr */
154 int lr_register
; /* register of saved lr, if trustworthy */
155 int cr_offset
; /* offset of saved cr */
156 int vrsave_offset
; /* offset of saved vrsave register */
160 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
162 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
165 if (tdep
->ppc_vsr0_regnum
< 0)
168 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
169 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
172 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
174 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
177 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
180 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
184 /* Return true if REGNO is an SPE register, false otherwise. */
186 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
190 /* Is it a reference to EV0 -- EV31, and do we have those? */
191 if (IS_SPE_PSEUDOREG (tdep
, regno
))
194 /* Is it a reference to one of the raw upper GPR halves? */
195 if (tdep
->ppc_ev0_upper_regnum
>= 0
196 && tdep
->ppc_ev0_upper_regnum
<= regno
197 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
200 /* Is it a reference to the 64-bit accumulator, and do we have that? */
201 if (tdep
->ppc_acc_regnum
>= 0
202 && tdep
->ppc_acc_regnum
== regno
)
205 /* Is it a reference to the SPE floating-point status and control register,
206 and do we have that? */
207 if (tdep
->ppc_spefscr_regnum
>= 0
208 && tdep
->ppc_spefscr_regnum
== regno
)
215 /* Return non-zero if the architecture described by GDBARCH has
216 floating-point registers (f0 --- f31 and fpscr). */
218 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 return (tdep
->ppc_fp0_regnum
>= 0
223 && tdep
->ppc_fpscr_regnum
>= 0);
226 /* Return non-zero if the architecture described by GDBARCH has
227 VSX registers (vsr0 --- vsr63). */
229 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
233 return tdep
->ppc_vsr0_regnum
>= 0;
236 /* Return non-zero if the architecture described by GDBARCH has
237 Altivec registers (vr0 --- vr31, vrsave and vscr). */
239 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
243 return (tdep
->ppc_vr0_regnum
>= 0
244 && tdep
->ppc_vrsave_regnum
>= 0);
247 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
250 This is a helper function for init_sim_regno_table, constructing
251 the table mapping GDB register numbers to sim register numbers; we
252 initialize every element in that table to -1 before we start
255 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
257 /* Make sure we don't try to assign any given GDB register a sim
258 register number more than once. */
259 gdb_assert (table
[gdb_regno
] == -1);
260 table
[gdb_regno
] = sim_regno
;
264 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
265 numbers to simulator register numbers, based on the values placed
266 in the ARCH->tdep->ppc_foo_regnum members. */
268 init_sim_regno_table (struct gdbarch
*arch
)
270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
271 int total_regs
= gdbarch_num_regs (arch
);
272 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
274 static const char *const segment_regs
[] = {
275 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
276 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
279 /* Presume that all registers not explicitly mentioned below are
280 unavailable from the sim. */
281 for (i
= 0; i
< total_regs
; i
++)
284 /* General-purpose registers. */
285 for (i
= 0; i
< ppc_num_gprs
; i
++)
286 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
288 /* Floating-point registers. */
289 if (tdep
->ppc_fp0_regnum
>= 0)
290 for (i
= 0; i
< ppc_num_fprs
; i
++)
291 set_sim_regno (sim_regno
,
292 tdep
->ppc_fp0_regnum
+ i
,
293 sim_ppc_f0_regnum
+ i
);
294 if (tdep
->ppc_fpscr_regnum
>= 0)
295 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
297 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
298 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
299 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
301 /* Segment registers. */
302 for (i
= 0; i
< ppc_num_srs
; i
++)
306 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
308 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
311 /* Altivec registers. */
312 if (tdep
->ppc_vr0_regnum
>= 0)
314 for (i
= 0; i
< ppc_num_vrs
; i
++)
315 set_sim_regno (sim_regno
,
316 tdep
->ppc_vr0_regnum
+ i
,
317 sim_ppc_vr0_regnum
+ i
);
319 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
320 we can treat this more like the other cases. */
321 set_sim_regno (sim_regno
,
322 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
323 sim_ppc_vscr_regnum
);
325 /* vsave is a special-purpose register, so the code below handles it. */
327 /* SPE APU (E500) registers. */
328 if (tdep
->ppc_ev0_upper_regnum
>= 0)
329 for (i
= 0; i
< ppc_num_gprs
; i
++)
330 set_sim_regno (sim_regno
,
331 tdep
->ppc_ev0_upper_regnum
+ i
,
332 sim_ppc_rh0_regnum
+ i
);
333 if (tdep
->ppc_acc_regnum
>= 0)
334 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
335 /* spefscr is a special-purpose register, so the code below handles it. */
338 /* Now handle all special-purpose registers. Verify that they
339 haven't mistakenly been assigned numbers by any of the above
341 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
343 const char *spr_name
= sim_spr_register_name (i
);
346 if (spr_name
!= NULL
)
347 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
350 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
354 /* Drop the initialized array into place. */
355 tdep
->sim_regno
= sim_regno
;
359 /* Given a GDB register number REG, return the corresponding SIM
362 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
364 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
367 if (tdep
->sim_regno
== NULL
)
368 init_sim_regno_table (gdbarch
);
371 && reg
<= gdbarch_num_regs (gdbarch
)
372 + gdbarch_num_pseudo_regs (gdbarch
));
373 sim_regno
= tdep
->sim_regno
[reg
];
378 return LEGACY_SIM_REGNO_IGNORE
;
383 /* Register set support functions. */
385 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
386 Write the register to REGCACHE. */
389 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
390 const gdb_byte
*regs
, size_t offset
, int regsize
)
392 if (regnum
!= -1 && offset
!= -1)
396 struct gdbarch
*gdbarch
= regcache
->arch ();
397 int gdb_regsize
= register_size (gdbarch
, regnum
);
398 if (gdb_regsize
< regsize
399 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
400 offset
+= regsize
- gdb_regsize
;
402 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
406 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
407 in a field REGSIZE wide. Zero pad as necessary. */
410 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
411 gdb_byte
*regs
, size_t offset
, int regsize
)
413 if (regnum
!= -1 && offset
!= -1)
417 struct gdbarch
*gdbarch
= regcache
->arch ();
418 int gdb_regsize
= register_size (gdbarch
, regnum
);
419 if (gdb_regsize
< regsize
)
421 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
423 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
424 offset
+= regsize
- gdb_regsize
;
427 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
428 regsize
- gdb_regsize
);
431 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
436 ppc_greg_offset (struct gdbarch
*gdbarch
,
437 struct gdbarch_tdep
*tdep
,
438 const struct ppc_reg_offsets
*offsets
,
442 *regsize
= offsets
->gpr_size
;
443 if (regnum
>= tdep
->ppc_gp0_regnum
444 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
445 return (offsets
->r0_offset
446 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
448 if (regnum
== gdbarch_pc_regnum (gdbarch
))
449 return offsets
->pc_offset
;
451 if (regnum
== tdep
->ppc_ps_regnum
)
452 return offsets
->ps_offset
;
454 if (regnum
== tdep
->ppc_lr_regnum
)
455 return offsets
->lr_offset
;
457 if (regnum
== tdep
->ppc_ctr_regnum
)
458 return offsets
->ctr_offset
;
460 *regsize
= offsets
->xr_size
;
461 if (regnum
== tdep
->ppc_cr_regnum
)
462 return offsets
->cr_offset
;
464 if (regnum
== tdep
->ppc_xer_regnum
)
465 return offsets
->xer_offset
;
467 if (regnum
== tdep
->ppc_mq_regnum
)
468 return offsets
->mq_offset
;
474 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
475 const struct ppc_reg_offsets
*offsets
,
478 if (regnum
>= tdep
->ppc_fp0_regnum
479 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
480 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
482 if (regnum
== tdep
->ppc_fpscr_regnum
)
483 return offsets
->fpscr_offset
;
489 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
490 const struct ppc_reg_offsets
*offsets
,
493 if (regnum
>= tdep
->ppc_vr0_regnum
494 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
495 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
497 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
498 return offsets
->vscr_offset
;
500 if (regnum
== tdep
->ppc_vrsave_regnum
)
501 return offsets
->vrsave_offset
;
506 /* Supply register REGNUM in the general-purpose register set REGSET
507 from the buffer specified by GREGS and LEN to register cache
508 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
511 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
512 int regnum
, const void *gregs
, size_t len
)
514 struct gdbarch
*gdbarch
= regcache
->arch ();
515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
516 const struct ppc_reg_offsets
*offsets
517 = (const struct ppc_reg_offsets
*) regset
->regmap
;
524 int gpr_size
= offsets
->gpr_size
;
526 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
527 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
528 i
++, offset
+= gpr_size
)
529 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
532 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
533 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
535 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
536 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
537 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
538 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
539 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
540 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
541 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
543 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
544 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
546 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
547 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
552 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
553 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
556 /* Supply register REGNUM in the floating-point register set REGSET
557 from the buffer specified by FPREGS and LEN to register cache
558 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
561 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
562 int regnum
, const void *fpregs
, size_t len
)
564 struct gdbarch
*gdbarch
= regcache
->arch ();
565 struct gdbarch_tdep
*tdep
;
566 const struct ppc_reg_offsets
*offsets
;
569 if (!ppc_floating_point_unit_p (gdbarch
))
572 tdep
= gdbarch_tdep (gdbarch
);
573 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
578 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
579 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
581 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
583 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
584 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
585 offsets
->fpscr_size
);
589 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
590 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
591 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
594 /* Supply register REGNUM in the VSX register set REGSET
595 from the buffer specified by VSXREGS and LEN to register cache
596 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
599 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
600 int regnum
, const void *vsxregs
, size_t len
)
602 struct gdbarch
*gdbarch
= regcache
->arch ();
603 struct gdbarch_tdep
*tdep
;
605 if (!ppc_vsx_support_p (gdbarch
))
608 tdep
= gdbarch_tdep (gdbarch
);
614 for (i
= tdep
->ppc_vsr0_upper_regnum
;
615 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
617 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vsxregs
, 0, 8);
622 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vsxregs
, 0, 8);
625 /* Supply register REGNUM in the Altivec register set REGSET
626 from the buffer specified by VRREGS and LEN to register cache
627 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
630 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
631 int regnum
, const void *vrregs
, size_t len
)
633 struct gdbarch
*gdbarch
= regcache
->arch ();
634 struct gdbarch_tdep
*tdep
;
635 const struct ppc_reg_offsets
*offsets
;
638 if (!ppc_altivec_support_p (gdbarch
))
641 tdep
= gdbarch_tdep (gdbarch
);
642 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
647 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
648 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
650 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vrregs
, offset
, 16);
652 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
653 (const gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
655 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
656 (const gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
660 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
661 if (regnum
!= tdep
->ppc_vrsave_regnum
662 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
663 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vrregs
, offset
, 16);
665 ppc_supply_reg (regcache
, regnum
,
666 (const gdb_byte
*) vrregs
, offset
, 4);
669 /* Collect register REGNUM in the general-purpose register set
670 REGSET from register cache REGCACHE into the buffer specified by
671 GREGS and LEN. If REGNUM is -1, do this for all registers in
675 ppc_collect_gregset (const struct regset
*regset
,
676 const struct regcache
*regcache
,
677 int regnum
, void *gregs
, size_t len
)
679 struct gdbarch
*gdbarch
= regcache
->arch ();
680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
681 const struct ppc_reg_offsets
*offsets
682 = (const struct ppc_reg_offsets
*) regset
->regmap
;
689 int gpr_size
= offsets
->gpr_size
;
691 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
692 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
693 i
++, offset
+= gpr_size
)
694 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
696 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
697 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
698 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
699 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
700 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
701 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
702 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
703 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
704 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
705 (gdb_byte
*) gregs
, offsets
->cr_offset
,
707 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
708 (gdb_byte
*) gregs
, offsets
->xer_offset
,
710 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
711 (gdb_byte
*) gregs
, offsets
->mq_offset
,
716 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
717 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
720 /* Collect register REGNUM in the floating-point register set
721 REGSET from register cache REGCACHE into the buffer specified by
722 FPREGS and LEN. If REGNUM is -1, do this for all registers in
726 ppc_collect_fpregset (const struct regset
*regset
,
727 const struct regcache
*regcache
,
728 int regnum
, void *fpregs
, size_t len
)
730 struct gdbarch
*gdbarch
= regcache
->arch ();
731 struct gdbarch_tdep
*tdep
;
732 const struct ppc_reg_offsets
*offsets
;
735 if (!ppc_floating_point_unit_p (gdbarch
))
738 tdep
= gdbarch_tdep (gdbarch
);
739 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
744 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
745 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
747 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
749 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
750 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
751 offsets
->fpscr_size
);
755 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
756 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
757 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
760 /* Collect register REGNUM in the VSX register set
761 REGSET from register cache REGCACHE into the buffer specified by
762 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
766 ppc_collect_vsxregset (const struct regset
*regset
,
767 const struct regcache
*regcache
,
768 int regnum
, void *vsxregs
, size_t len
)
770 struct gdbarch
*gdbarch
= regcache
->arch ();
771 struct gdbarch_tdep
*tdep
;
773 if (!ppc_vsx_support_p (gdbarch
))
776 tdep
= gdbarch_tdep (gdbarch
);
782 for (i
= tdep
->ppc_vsr0_upper_regnum
;
783 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
785 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vsxregs
, 0, 8);
790 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vsxregs
, 0, 8);
794 /* Collect register REGNUM in the Altivec register set
795 REGSET from register cache REGCACHE into the buffer specified by
796 VRREGS and LEN. If REGNUM is -1, do this for all registers in
800 ppc_collect_vrregset (const struct regset
*regset
,
801 const struct regcache
*regcache
,
802 int regnum
, void *vrregs
, size_t len
)
804 struct gdbarch
*gdbarch
= regcache
->arch ();
805 struct gdbarch_tdep
*tdep
;
806 const struct ppc_reg_offsets
*offsets
;
809 if (!ppc_altivec_support_p (gdbarch
))
812 tdep
= gdbarch_tdep (gdbarch
);
813 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
818 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
819 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
821 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vrregs
, offset
, 16);
823 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
824 (gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
826 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
827 (gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
831 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
832 if (regnum
!= tdep
->ppc_vrsave_regnum
833 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
834 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vrregs
, offset
, 16);
836 ppc_collect_reg (regcache
, regnum
,
837 (gdb_byte
*) vrregs
, offset
, 4);
842 insn_changes_sp_or_jumps (unsigned long insn
)
844 int opcode
= (insn
>> 26) & 0x03f;
845 int sd
= (insn
>> 21) & 0x01f;
846 int a
= (insn
>> 16) & 0x01f;
847 int subcode
= (insn
>> 1) & 0x3ff;
849 /* Changes the stack pointer. */
851 /* NOTE: There are many ways to change the value of a given register.
852 The ways below are those used when the register is R1, the SP,
853 in a funtion's epilogue. */
855 if (opcode
== 31 && subcode
== 444 && a
== 1)
856 return 1; /* mr R1,Rn */
857 if (opcode
== 14 && sd
== 1)
858 return 1; /* addi R1,Rn,simm */
859 if (opcode
== 58 && sd
== 1)
860 return 1; /* ld R1,ds(Rn) */
862 /* Transfers control. */
868 if (opcode
== 19 && subcode
== 16)
870 if (opcode
== 19 && subcode
== 528)
871 return 1; /* bcctr */
876 /* Return true if we are in the function's epilogue, i.e. after the
877 instruction that destroyed the function's stack frame.
879 1) scan forward from the point of execution:
880 a) If you find an instruction that modifies the stack pointer
881 or transfers control (except a return), execution is not in
883 b) Stop scanning if you find a return instruction or reach the
884 end of the function or reach the hard limit for the size of
886 2) scan backward from the point of execution:
887 a) If you find an instruction that modifies the stack pointer,
888 execution *is* in an epilogue, return.
889 b) Stop scanning if you reach an instruction that transfers
890 control or the beginning of the function or reach the hard
891 limit for the size of an epilogue. */
894 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
895 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
897 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
898 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
899 bfd_byte insn_buf
[PPC_INSN_SIZE
];
900 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
903 /* Find the search limits based on function boundaries and hard limit. */
905 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
908 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
909 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
911 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
912 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
914 /* Scan forward until next 'blr'. */
916 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
918 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
920 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
921 if (insn
== 0x4e800020)
923 /* Assume a bctr is a tail call unless it points strictly within
925 if (insn
== 0x4e800420)
927 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
928 tdep
->ppc_ctr_regnum
);
929 if (ctr
> func_start
&& ctr
< func_end
)
934 if (insn_changes_sp_or_jumps (insn
))
938 /* Scan backward until adjustment to stack pointer (R1). */
940 for (scan_pc
= pc
- PPC_INSN_SIZE
;
941 scan_pc
>= epilogue_start
;
942 scan_pc
-= PPC_INSN_SIZE
)
944 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
946 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
947 if (insn_changes_sp_or_jumps (insn
))
954 /* Implement the stack_frame_destroyed_p gdbarch method. */
957 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
959 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
963 /* Get the ith function argument for the current function. */
965 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
968 return get_frame_register_unsigned (frame
, 3 + argi
);
971 /* Sequence of bytes for breakpoint instruction. */
973 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
974 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
976 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
979 /* Instruction masks for displaced stepping. */
980 #define BRANCH_MASK 0xfc000000
981 #define BP_MASK 0xFC0007FE
982 #define B_INSN 0x48000000
983 #define BC_INSN 0x40000000
984 #define BXL_INSN 0x4c000000
985 #define BP_INSN 0x7C000008
987 /* Instruction masks used during single-stepping of atomic
989 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
990 #define LWARX_INSTRUCTION 0x7c000028
991 #define LDARX_INSTRUCTION 0x7c0000A8
992 #define LBARX_INSTRUCTION 0x7c000068
993 #define LHARX_INSTRUCTION 0x7c0000e8
994 #define LQARX_INSTRUCTION 0x7c000228
995 #define STORE_CONDITIONAL_MASK 0xfc0007ff
996 #define STWCX_INSTRUCTION 0x7c00012d
997 #define STDCX_INSTRUCTION 0x7c0001ad
998 #define STBCX_INSTRUCTION 0x7c00056d
999 #define STHCX_INSTRUCTION 0x7c0005ad
1000 #define STQCX_INSTRUCTION 0x7c00016d
1002 /* Check if insn is one of the Load And Reserve instructions used for atomic
1004 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
1005 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
1006 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
1007 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
1008 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
1009 /* Check if insn is one of the Store Conditional instructions used for atomic
1011 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
1012 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
1013 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
1014 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
1015 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
1017 typedef buf_displaced_step_closure ppc_displaced_step_closure
;
1019 /* We can't displaced step atomic sequences. */
1021 static struct displaced_step_closure
*
1022 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1023 CORE_ADDR from
, CORE_ADDR to
,
1024 struct regcache
*regs
)
1026 size_t len
= gdbarch_max_insn_length (gdbarch
);
1027 std::unique_ptr
<ppc_displaced_step_closure
> closure
1028 (new ppc_displaced_step_closure (len
));
1029 gdb_byte
*buf
= closure
->buf
.data ();
1030 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1033 read_memory (from
, buf
, len
);
1035 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
1037 /* Assume all atomic sequences start with a Load and Reserve instruction. */
1038 if (IS_LOAD_AND_RESERVE_INSN (insn
))
1040 if (debug_displaced
)
1042 fprintf_unfiltered (gdb_stdlog
,
1043 "displaced: can't displaced step "
1044 "atomic sequence at %s\n",
1045 paddress (gdbarch
, from
));
1051 write_memory (to
, buf
, len
);
1053 if (debug_displaced
)
1055 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1056 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1057 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1060 return closure
.release ();
1063 /* Fix up the state of registers and memory after having single-stepped
1064 a displaced instruction. */
1066 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
1067 struct displaced_step_closure
*closure_
,
1068 CORE_ADDR from
, CORE_ADDR to
,
1069 struct regcache
*regs
)
1071 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1072 /* Our closure is a copy of the instruction. */
1073 ppc_displaced_step_closure
*closure
= (ppc_displaced_step_closure
*) closure_
;
1074 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
1075 PPC_INSN_SIZE
, byte_order
);
1076 ULONGEST opcode
= 0;
1077 /* Offset for non PC-relative instructions. */
1078 LONGEST offset
= PPC_INSN_SIZE
;
1080 opcode
= insn
& BRANCH_MASK
;
1082 if (debug_displaced
)
1083 fprintf_unfiltered (gdb_stdlog
,
1084 "displaced: (ppc) fixup (%s, %s)\n",
1085 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1088 /* Handle PC-relative branch instructions. */
1089 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1091 ULONGEST current_pc
;
1093 /* Read the current PC value after the instruction has been executed
1094 in a displaced location. Calculate the offset to be applied to the
1095 original PC value before the displaced stepping. */
1096 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1098 offset
= current_pc
- to
;
1100 if (opcode
!= BXL_INSN
)
1102 /* Check for AA bit indicating whether this is an absolute
1103 addressing or PC-relative (1: absolute, 0: relative). */
1106 /* PC-relative addressing is being used in the branch. */
1107 if (debug_displaced
)
1110 "displaced: (ppc) branch instruction: %s\n"
1111 "displaced: (ppc) adjusted PC from %s to %s\n",
1112 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1113 paddress (gdbarch
, from
+ offset
));
1115 regcache_cooked_write_unsigned (regs
,
1116 gdbarch_pc_regnum (gdbarch
),
1122 /* If we're here, it means we have a branch to LR or CTR. If the
1123 branch was taken, the offset is probably greater than 4 (the next
1124 instruction), so it's safe to assume that an offset of 4 means we
1125 did not take the branch. */
1126 if (offset
== PPC_INSN_SIZE
)
1127 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1128 from
+ PPC_INSN_SIZE
);
1131 /* Check for LK bit indicating whether we should set the link
1132 register to point to the next instruction
1133 (1: Set, 0: Don't set). */
1136 /* Link register needs to be set to the next instruction's PC. */
1137 regcache_cooked_write_unsigned (regs
,
1138 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1139 from
+ PPC_INSN_SIZE
);
1140 if (debug_displaced
)
1141 fprintf_unfiltered (gdb_stdlog
,
1142 "displaced: (ppc) adjusted LR to %s\n",
1143 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1147 /* Check for breakpoints in the inferior. If we've found one, place the PC
1148 right at the breakpoint instruction. */
1149 else if ((insn
& BP_MASK
) == BP_INSN
)
1150 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1152 /* Handle any other instructions that do not fit in the categories above. */
1153 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1157 /* Always use hardware single-stepping to execute the
1158 displaced instruction. */
1160 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1161 struct displaced_step_closure
*closure
)
1166 /* Checks for an atomic sequence of instructions beginning with a
1167 Load And Reserve instruction and ending with a Store Conditional
1168 instruction. If such a sequence is found, attempt to step through it.
1169 A breakpoint is placed at the end of the sequence. */
1170 std::vector
<CORE_ADDR
>
1171 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1173 struct gdbarch
*gdbarch
= regcache
->arch ();
1174 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1175 CORE_ADDR pc
= regcache_read_pc (regcache
);
1176 CORE_ADDR breaks
[2] = {-1, -1};
1178 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1179 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1182 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1183 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1184 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1186 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1187 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1190 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1192 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1194 loc
+= PPC_INSN_SIZE
;
1195 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1197 /* Assume that there is at most one conditional branch in the atomic
1198 sequence. If a conditional branch is found, put a breakpoint in
1199 its destination address. */
1200 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1202 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1203 int absolute
= insn
& 2;
1205 if (bc_insn_count
>= 1)
1206 return {}; /* More than one conditional branch found, fallback
1207 to the standard single-step code. */
1210 breaks
[1] = immediate
;
1212 breaks
[1] = loc
+ immediate
;
1218 if (IS_STORE_CONDITIONAL_INSN (insn
))
1222 /* Assume that the atomic sequence ends with a Store Conditional
1224 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1228 loc
+= PPC_INSN_SIZE
;
1230 /* Insert a breakpoint right after the end of the atomic sequence. */
1233 /* Check for duplicated breakpoints. Check also for a breakpoint
1234 placed (branch instruction's destination) anywhere in sequence. */
1236 && (breaks
[1] == breaks
[0]
1237 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1238 last_breakpoint
= 0;
1240 std::vector
<CORE_ADDR
> next_pcs
;
1242 for (index
= 0; index
<= last_breakpoint
; index
++)
1243 next_pcs
.push_back (breaks
[index
]);
1249 #define SIGNED_SHORT(x) \
1250 ((sizeof (short) == 2) \
1251 ? ((int)(short)(x)) \
1252 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1254 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1256 /* Limit the number of skipped non-prologue instructions, as the examining
1257 of the prologue is expensive. */
1258 static int max_skip_non_prologue_insns
= 10;
1260 /* Return nonzero if the given instruction OP can be part of the prologue
1261 of a function and saves a parameter on the stack. FRAMEP should be
1262 set if one of the previous instructions in the function has set the
1266 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1268 /* Move parameters from argument registers to temporary register. */
1269 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1271 /* Rx must be scratch register r0. */
1272 const int rx_regno
= (op
>> 16) & 31;
1273 /* Ry: Only r3 - r10 are used for parameter passing. */
1274 const int ry_regno
= GET_SRC_REG (op
);
1276 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1278 *r0_contains_arg
= 1;
1285 /* Save a General Purpose Register on stack. */
1287 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1288 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1290 /* Rx: Only r3 - r10 are used for parameter passing. */
1291 const int rx_regno
= GET_SRC_REG (op
);
1293 return (rx_regno
>= 3 && rx_regno
<= 10);
1296 /* Save a General Purpose Register on stack via the Frame Pointer. */
1299 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1300 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1301 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1303 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1304 However, the compiler sometimes uses r0 to hold an argument. */
1305 const int rx_regno
= GET_SRC_REG (op
);
1307 return ((rx_regno
>= 3 && rx_regno
<= 10)
1308 || (rx_regno
== 0 && *r0_contains_arg
));
1311 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1313 /* Only f2 - f8 are used for parameter passing. */
1314 const int src_regno
= GET_SRC_REG (op
);
1316 return (src_regno
>= 2 && src_regno
<= 8);
1319 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1321 /* Only f2 - f8 are used for parameter passing. */
1322 const int src_regno
= GET_SRC_REG (op
);
1324 return (src_regno
>= 2 && src_regno
<= 8);
1327 /* Not an insn that saves a parameter on stack. */
1331 /* Assuming that INSN is a "bl" instruction located at PC, return
1332 nonzero if the destination of the branch is a "blrl" instruction.
1334 This sequence is sometimes found in certain function prologues.
1335 It allows the function to load the LR register with a value that
1336 they can use to access PIC data using PC-relative offsets. */
1339 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1346 absolute
= (int) ((insn
>> 1) & 1);
1347 immediate
= ((insn
& ~3) << 6) >> 6;
1351 dest
= pc
+ immediate
;
1353 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1354 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1360 /* Return true if OP is a stw or std instruction with
1361 register operands RS and RA and any immediate offset.
1363 If WITH_UPDATE is true, also return true if OP is
1364 a stwu or stdu instruction with the same operands.
1366 Return false otherwise.
1369 store_insn_p (unsigned long op
, unsigned long rs
,
1370 unsigned long ra
, bool with_update
)
1375 if (/* std RS, SIMM(RA) */
1376 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1377 /* stw RS, SIMM(RA) */
1378 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1383 if (/* stdu RS, SIMM(RA) */
1384 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1385 /* stwu RS, SIMM(RA) */
1386 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1393 /* Masks for decoding a branch-and-link (bl) instruction.
1395 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1396 The former is anded with the opcode in question; if the result of
1397 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1398 question is a ``bl'' instruction.
1400 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1401 the branch displacement. */
1403 #define BL_MASK 0xfc000001
1404 #define BL_INSTRUCTION 0x48000001
1405 #define BL_DISPLACEMENT_MASK 0x03fffffc
1407 static unsigned long
1408 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1410 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1414 /* Fetch the instruction and convert it to an integer. */
1415 if (target_read_memory (pc
, buf
, 4))
1417 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1422 /* GCC generates several well-known sequences of instructions at the begining
1423 of each function prologue when compiling with -fstack-check. If one of
1424 such sequences starts at START_PC, then return the address of the
1425 instruction immediately past this sequence. Otherwise, return START_PC. */
1428 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1430 CORE_ADDR pc
= start_pc
;
1431 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1433 /* First possible sequence: A small number of probes.
1434 stw 0, -<some immediate>(1)
1435 [repeat this instruction any (small) number of times]. */
1437 if ((op
& 0xffff0000) == 0x90010000)
1439 while ((op
& 0xffff0000) == 0x90010000)
1442 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1447 /* Second sequence: A probing loop.
1448 addi 12,1,-<some immediate>
1449 lis 0,-<some immediate>
1450 [possibly ori 0,0,<some immediate>]
1454 addi 12,12,-<some immediate>
1457 [possibly one last probe: stw 0,<some immediate>(12)]. */
1461 /* addi 12,1,-<some immediate> */
1462 if ((op
& 0xffff0000) != 0x39810000)
1465 /* lis 0,-<some immediate> */
1467 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1468 if ((op
& 0xffff0000) != 0x3c000000)
1472 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1473 /* [possibly ori 0,0,<some immediate>] */
1474 if ((op
& 0xffff0000) == 0x60000000)
1477 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1480 if (op
!= 0x7c0c0214)
1485 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1486 if (op
!= 0x7c0c0000)
1491 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1492 if ((op
& 0xff9f0001) != 0x41820000)
1495 /* addi 12,12,-<some immediate> */
1497 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1498 if ((op
& 0xffff0000) != 0x398c0000)
1503 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1504 if (op
!= 0x900c0000)
1509 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1510 if ((op
& 0xfc000001) != 0x48000000)
1513 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1515 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1516 if ((op
& 0xffff0000) == 0x900c0000)
1519 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1522 /* We found a valid stack-check sequence, return the new PC. */
1526 /* Third sequence: No probe; instead, a comparizon between the stack size
1527 limit (saved in a run-time global variable) and the current stack
1530 addi 0,1,-<some immediate>
1531 lis 12,__gnat_stack_limit@ha
1532 lwz 12,__gnat_stack_limit@l(12)
1535 or, with a small variant in the case of a bigger stack frame:
1536 addis 0,1,<some immediate>
1537 addic 0,0,-<some immediate>
1538 lis 12,__gnat_stack_limit@ha
1539 lwz 12,__gnat_stack_limit@l(12)
1544 /* addi 0,1,-<some immediate> */
1545 if ((op
& 0xffff0000) != 0x38010000)
1547 /* small stack frame variant not recognized; try the
1548 big stack frame variant: */
1550 /* addis 0,1,<some immediate> */
1551 if ((op
& 0xffff0000) != 0x3c010000)
1554 /* addic 0,0,-<some immediate> */
1556 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1557 if ((op
& 0xffff0000) != 0x30000000)
1561 /* lis 12,<some immediate> */
1563 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1564 if ((op
& 0xffff0000) != 0x3d800000)
1567 /* lwz 12,<some immediate>(12) */
1569 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1570 if ((op
& 0xffff0000) != 0x818c0000)
1575 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1576 if ((op
& 0xfffffffe) != 0x7c406008)
1579 /* We found a valid stack-check sequence, return the new PC. */
1583 /* No stack check code in our prologue, return the start_pc. */
1587 /* return pc value after skipping a function prologue and also return
1588 information about a function frame.
1590 in struct rs6000_framedata fdata:
1591 - frameless is TRUE, if function does not have a frame.
1592 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1593 - offset is the initial size of this stack frame --- the amount by
1594 which we decrement the sp to allocate the frame.
1595 - saved_gpr is the number of the first saved gpr.
1596 - saved_fpr is the number of the first saved fpr.
1597 - saved_vr is the number of the first saved vr.
1598 - saved_ev is the number of the first saved ev.
1599 - alloca_reg is the number of the register used for alloca() handling.
1601 - gpr_offset is the offset of the first saved gpr from the previous frame.
1602 - fpr_offset is the offset of the first saved fpr from the previous frame.
1603 - vr_offset is the offset of the first saved vr from the previous frame.
1604 - ev_offset is the offset of the first saved ev from the previous frame.
1605 - lr_offset is the offset of the saved lr
1606 - cr_offset is the offset of the saved cr
1607 - vrsave_offset is the offset of the saved vrsave register. */
1610 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1611 struct rs6000_framedata
*fdata
)
1613 CORE_ADDR orig_pc
= pc
;
1614 CORE_ADDR last_prologue_pc
= pc
;
1615 CORE_ADDR li_found_pc
= 0;
1619 long alloca_reg_offset
= 0;
1620 long vr_saved_offset
= 0;
1626 int vrsave_reg
= -1;
1629 int minimal_toc_loaded
= 0;
1630 int prev_insn_was_prologue_insn
= 1;
1631 int num_skip_non_prologue_insns
= 0;
1632 int r0_contains_arg
= 0;
1633 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1634 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1635 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1637 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1638 fdata
->saved_gpr
= -1;
1639 fdata
->saved_fpr
= -1;
1640 fdata
->saved_vr
= -1;
1641 fdata
->saved_ev
= -1;
1642 fdata
->alloca_reg
= -1;
1643 fdata
->frameless
= 1;
1644 fdata
->nosavedpc
= 1;
1645 fdata
->lr_register
= -1;
1647 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1653 /* Sometimes it isn't clear if an instruction is a prologue
1654 instruction or not. When we encounter one of these ambiguous
1655 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1656 Otherwise, we'll assume that it really is a prologue instruction. */
1657 if (prev_insn_was_prologue_insn
)
1658 last_prologue_pc
= pc
;
1660 /* Stop scanning if we've hit the limit. */
1664 prev_insn_was_prologue_insn
= 1;
1666 /* Fetch the instruction and convert it to an integer. */
1667 if (target_read_memory (pc
, buf
, 4))
1669 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1671 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1673 /* Since shared library / PIC code, which needs to get its
1674 address at runtime, can appear to save more than one link
1688 remember just the first one, but skip over additional
1691 lr_reg
= (op
& 0x03e00000) >> 21;
1693 r0_contains_arg
= 0;
1696 else if ((op
& 0xfc1fffff) == 0x7c000026)
1698 cr_reg
= (op
& 0x03e00000) >> 21;
1700 r0_contains_arg
= 0;
1704 else if ((op
& 0xfc1f0000) == 0xd8010000)
1705 { /* stfd Rx,NUM(r1) */
1706 reg
= GET_SRC_REG (op
);
1707 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1709 fdata
->saved_fpr
= reg
;
1710 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1715 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1716 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1717 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1718 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1721 reg
= GET_SRC_REG (op
);
1722 if ((op
& 0xfc1f0000) == 0xbc010000)
1723 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1725 fdata
->gpr_mask
|= 1U << reg
;
1726 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1728 fdata
->saved_gpr
= reg
;
1729 if ((op
& 0xfc1f0003) == 0xf8010000)
1731 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1736 else if ((op
& 0xffff0000) == 0x3c4c0000
1737 || (op
& 0xffff0000) == 0x3c400000
1738 || (op
& 0xffff0000) == 0x38420000)
1740 /* . 0: addis 2,12,.TOC.-0b@ha
1741 . addi 2,2,.TOC.-0b@l
1745 used by ELFv2 global entry points to set up r2. */
1748 else if (op
== 0x60000000)
1751 /* Allow nops in the prologue, but do not consider them to
1752 be part of the prologue unless followed by other prologue
1754 prev_insn_was_prologue_insn
= 0;
1758 else if ((op
& 0xffff0000) == 0x3c000000)
1759 { /* addis 0,0,NUM, used for >= 32k frames */
1760 fdata
->offset
= (op
& 0x0000ffff) << 16;
1761 fdata
->frameless
= 0;
1762 r0_contains_arg
= 0;
1766 else if ((op
& 0xffff0000) == 0x60000000)
1767 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1768 fdata
->offset
|= (op
& 0x0000ffff);
1769 fdata
->frameless
= 0;
1770 r0_contains_arg
= 0;
1774 else if (lr_reg
>= 0 &&
1775 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1777 (store_insn_p (op
, lr_reg
,
1778 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1781 if (store_insn_p (op
, lr_reg
, 1, true))
1782 fdata
->lr_offset
= offset
;
1783 else /* LR save through frame pointer. */
1784 fdata
->lr_offset
= alloca_reg_offset
;
1786 fdata
->nosavedpc
= 0;
1787 /* Invalidate lr_reg, but don't set it to -1.
1788 That would mean that it had never been set. */
1790 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1791 (op
& 0xfc000000) == 0x90000000) /* stw */
1793 /* Does not update r1, so add displacement to lr_offset. */
1794 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1799 else if (cr_reg
>= 0 &&
1800 (store_insn_p (op
, cr_reg
, 1, true)))
1802 fdata
->cr_offset
= offset
;
1803 /* Invalidate cr_reg, but don't set it to -1.
1804 That would mean that it had never been set. */
1806 if ((op
& 0xfc000003) == 0xf8000000 ||
1807 (op
& 0xfc000000) == 0x90000000)
1809 /* Does not update r1, so add displacement to cr_offset. */
1810 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1815 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1817 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1818 prediction bits. If the LR has already been saved, we can
1822 else if (op
== 0x48000005)
1829 else if (op
== 0x48000004)
1834 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1835 in V.4 -mminimal-toc */
1836 (op
& 0xffff0000) == 0x3bde0000)
1837 { /* addi 30,30,foo@l */
1841 else if ((op
& 0xfc000001) == 0x48000001)
1845 fdata
->frameless
= 0;
1847 /* If the return address has already been saved, we can skip
1848 calls to blrl (for PIC). */
1849 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1855 /* Don't skip over the subroutine call if it is not within
1856 the first three instructions of the prologue and either
1857 we have no line table information or the line info tells
1858 us that the subroutine call is not part of the line
1859 associated with the prologue. */
1860 if ((pc
- orig_pc
) > 8)
1862 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1863 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1865 if ((prologue_sal
.line
== 0)
1866 || (prologue_sal
.line
!= this_sal
.line
))
1870 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1872 /* At this point, make sure this is not a trampoline
1873 function (a function that simply calls another functions,
1874 and nothing else). If the next is not a nop, this branch
1875 was part of the function prologue. */
1877 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1878 break; /* Don't skip over
1884 /* update stack pointer */
1885 else if ((op
& 0xfc1f0000) == 0x94010000)
1886 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1887 fdata
->frameless
= 0;
1888 fdata
->offset
= SIGNED_SHORT (op
);
1889 offset
= fdata
->offset
;
1892 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1893 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1894 /* No way to figure out what r1 is going to be. */
1895 fdata
->frameless
= 0;
1896 offset
= fdata
->offset
;
1899 else if ((op
& 0xfc1f0003) == 0xf8010001)
1900 { /* stdu rX,NUM(r1) */
1901 fdata
->frameless
= 0;
1902 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1903 offset
= fdata
->offset
;
1906 else if ((op
& 0xffff0000) == 0x38210000)
1907 { /* addi r1,r1,SIMM */
1908 fdata
->frameless
= 0;
1909 fdata
->offset
+= SIGNED_SHORT (op
);
1910 offset
= fdata
->offset
;
1913 /* Load up minimal toc pointer. Do not treat an epilogue restore
1914 of r31 as a minimal TOC load. */
1915 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1916 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1918 && !minimal_toc_loaded
)
1920 minimal_toc_loaded
= 1;
1923 /* move parameters from argument registers to local variable
1926 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1927 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1928 (((op
>> 21) & 31) <= 10) &&
1929 ((long) ((op
>> 16) & 31)
1930 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1934 /* store parameters in stack */
1936 /* Move parameters from argument registers to temporary register. */
1937 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1941 /* Set up frame pointer */
1943 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1945 fdata
->frameless
= 0;
1947 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1948 alloca_reg_offset
= offset
;
1951 /* Another way to set up the frame pointer. */
1953 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1954 || op
== 0x7c3f0b78)
1956 fdata
->frameless
= 0;
1958 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1959 alloca_reg_offset
= offset
;
1962 /* Another way to set up the frame pointer. */
1964 else if ((op
& 0xfc1fffff) == 0x38010000)
1965 { /* addi rX, r1, 0x0 */
1966 fdata
->frameless
= 0;
1968 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1969 + ((op
& ~0x38010000) >> 21));
1970 alloca_reg_offset
= offset
;
1973 /* AltiVec related instructions. */
1974 /* Store the vrsave register (spr 256) in another register for
1975 later manipulation, or load a register into the vrsave
1976 register. 2 instructions are used: mfvrsave and
1977 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1978 and mtspr SPR256, Rn. */
1979 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1980 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1981 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1983 vrsave_reg
= GET_SRC_REG (op
);
1986 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1990 /* Store the register where vrsave was saved to onto the stack:
1991 rS is the register where vrsave was stored in a previous
1993 /* 100100 sssss 00001 dddddddd dddddddd */
1994 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1996 if (vrsave_reg
== GET_SRC_REG (op
))
1998 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
2003 /* Compute the new value of vrsave, by modifying the register
2004 where vrsave was saved to. */
2005 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
2006 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
2010 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
2011 in a pair of insns to save the vector registers on the
2013 /* 001110 00000 00000 iiii iiii iiii iiii */
2014 /* 001110 01110 00000 iiii iiii iiii iiii */
2015 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
2016 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
2018 if ((op
& 0xffff0000) == 0x38000000)
2019 r0_contains_arg
= 0;
2021 vr_saved_offset
= SIGNED_SHORT (op
);
2023 /* This insn by itself is not part of the prologue, unless
2024 if part of the pair of insns mentioned above. So do not
2025 record this insn as part of the prologue yet. */
2026 prev_insn_was_prologue_insn
= 0;
2028 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
2029 /* 011111 sssss 11111 00000 00111001110 */
2030 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
2032 if (pc
== (li_found_pc
+ 4))
2034 vr_reg
= GET_SRC_REG (op
);
2035 /* If this is the first vector reg to be saved, or if
2036 it has a lower number than others previously seen,
2037 reupdate the frame info. */
2038 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
2040 fdata
->saved_vr
= vr_reg
;
2041 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2043 vr_saved_offset
= -1;
2048 /* End AltiVec related instructions. */
2050 /* Start BookE related instructions. */
2051 /* Store gen register S at (r31+uimm).
2052 Any register less than r13 is volatile, so we don't care. */
2053 /* 000100 sssss 11111 iiiii 01100100001 */
2054 else if (arch_info
->mach
== bfd_mach_ppc_e500
2055 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2057 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2060 ev_reg
= GET_SRC_REG (op
);
2061 imm
= (op
>> 11) & 0x1f;
2062 ev_offset
= imm
* 8;
2063 /* If this is the first vector reg to be saved, or if
2064 it has a lower number than others previously seen,
2065 reupdate the frame info. */
2066 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2068 fdata
->saved_ev
= ev_reg
;
2069 fdata
->ev_offset
= ev_offset
+ offset
;
2074 /* Store gen register rS at (r1+rB). */
2075 /* 000100 sssss 00001 bbbbb 01100100000 */
2076 else if (arch_info
->mach
== bfd_mach_ppc_e500
2077 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2079 if (pc
== (li_found_pc
+ 4))
2081 ev_reg
= GET_SRC_REG (op
);
2082 /* If this is the first vector reg to be saved, or if
2083 it has a lower number than others previously seen,
2084 reupdate the frame info. */
2085 /* We know the contents of rB from the previous instruction. */
2086 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2088 fdata
->saved_ev
= ev_reg
;
2089 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2091 vr_saved_offset
= -1;
2097 /* Store gen register r31 at (rA+uimm). */
2098 /* 000100 11111 aaaaa iiiii 01100100001 */
2099 else if (arch_info
->mach
== bfd_mach_ppc_e500
2100 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2102 /* Wwe know that the source register is 31 already, but
2103 it can't hurt to compute it. */
2104 ev_reg
= GET_SRC_REG (op
);
2105 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2106 /* If this is the first vector reg to be saved, or if
2107 it has a lower number than others previously seen,
2108 reupdate the frame info. */
2109 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2111 fdata
->saved_ev
= ev_reg
;
2112 fdata
->ev_offset
= ev_offset
+ offset
;
2117 /* Store gen register S at (r31+r0).
2118 Store param on stack when offset from SP bigger than 4 bytes. */
2119 /* 000100 sssss 11111 00000 01100100000 */
2120 else if (arch_info
->mach
== bfd_mach_ppc_e500
2121 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2123 if (pc
== (li_found_pc
+ 4))
2125 if ((op
& 0x03e00000) >= 0x01a00000)
2127 ev_reg
= GET_SRC_REG (op
);
2128 /* If this is the first vector reg to be saved, or if
2129 it has a lower number than others previously seen,
2130 reupdate the frame info. */
2131 /* We know the contents of r0 from the previous
2133 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2135 fdata
->saved_ev
= ev_reg
;
2136 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2140 vr_saved_offset
= -1;
2145 /* End BookE related instructions. */
2149 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2151 /* Not a recognized prologue instruction.
2152 Handle optimizer code motions into the prologue by continuing
2153 the search if we have no valid frame yet or if the return
2154 address is not yet saved in the frame. Also skip instructions
2155 if some of the GPRs expected to be saved are not yet saved. */
2156 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2157 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2160 if (op
== 0x4e800020 /* blr */
2161 || op
== 0x4e800420) /* bctr */
2162 /* Do not scan past epilogue in frameless functions or
2165 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2166 /* Never skip branches. */
2169 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2170 /* Do not scan too many insns, scanning insns is expensive with
2174 /* Continue scanning. */
2175 prev_insn_was_prologue_insn
= 0;
2181 /* I have problems with skipping over __main() that I need to address
2182 * sometime. Previously, I used to use misc_function_vector which
2183 * didn't work as well as I wanted to be. -MGO */
2185 /* If the first thing after skipping a prolog is a branch to a function,
2186 this might be a call to an initializer in main(), introduced by gcc2.
2187 We'd like to skip over it as well. Fortunately, xlc does some extra
2188 work before calling a function right after a prologue, thus we can
2189 single out such gcc2 behaviour. */
2192 if ((op
& 0xfc000001) == 0x48000001)
2193 { /* bl foo, an initializer function? */
2194 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2196 if (op
== 0x4def7b82)
2197 { /* cror 0xf, 0xf, 0xf (nop) */
2199 /* Check and see if we are in main. If so, skip over this
2200 initializer function as well. */
2202 tmp
= find_pc_misc_function (pc
);
2204 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2210 if (pc
== lim_pc
&& lr_reg
>= 0)
2211 fdata
->lr_register
= lr_reg
;
2213 fdata
->offset
= -fdata
->offset
;
2214 return last_prologue_pc
;
2218 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2220 struct rs6000_framedata frame
;
2221 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2223 /* See if we can determine the end of the prologue via the symbol table.
2224 If so, then return either PC, or the PC after the prologue, whichever
2226 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2228 CORE_ADDR post_prologue_pc
2229 = skip_prologue_using_sal (gdbarch
, func_addr
);
2230 if (post_prologue_pc
!= 0)
2231 return std::max (pc
, post_prologue_pc
);
2234 /* Can't determine prologue from the symbol table, need to examine
2237 /* Find an upper limit on the function prologue using the debug
2238 information. If the debug information could not be used to provide
2239 that bound, then use an arbitrary large number as the upper bound. */
2240 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2242 limit_pc
= pc
+ 100; /* Magic. */
2244 /* Do not allow limit_pc to be past the function end, if we know
2245 where that end is... */
2246 if (func_end_addr
&& limit_pc
> func_end_addr
)
2247 limit_pc
= func_end_addr
;
2249 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2253 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2254 in the prologue of main().
2256 The function below examines the code pointed at by PC and checks to
2257 see if it corresponds to a call to __eabi. If so, it returns the
2258 address of the instruction following that call. Otherwise, it simply
2262 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2264 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2268 if (target_read_memory (pc
, buf
, 4))
2270 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2272 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2274 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2275 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2276 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2278 /* We check for ___eabi (three leading underscores) in addition
2279 to __eabi in case the GCC option "-fleading-underscore" was
2280 used to compile the program. */
2281 if (s
.minsym
!= NULL
2282 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2283 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2284 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2290 /* All the ABI's require 16 byte alignment. */
2292 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2294 return (addr
& -16);
2297 /* Return whether handle_inferior_event() should proceed through code
2298 starting at PC in function NAME when stepping.
2300 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2301 handle memory references that are too distant to fit in instructions
2302 generated by the compiler. For example, if 'foo' in the following
2307 is greater than 32767, the linker might replace the lwz with a branch to
2308 somewhere in @FIX1 that does the load in 2 instructions and then branches
2309 back to where execution should continue.
2311 GDB should silently step over @FIX code, just like AIX dbx does.
2312 Unfortunately, the linker uses the "b" instruction for the
2313 branches, meaning that the link register doesn't get set.
2314 Therefore, GDB's usual step_over_function () mechanism won't work.
2316 Instead, use the gdbarch_skip_trampoline_code and
2317 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2321 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2322 CORE_ADDR pc
, const char *name
)
2324 return name
&& startswith (name
, "@FIX");
2327 /* Skip code that the user doesn't want to see when stepping:
2329 1. Indirect function calls use a piece of trampoline code to do context
2330 switching, i.e. to set the new TOC table. Skip such code if we are on
2331 its first instruction (as when we have single-stepped to here).
2333 2. Skip shared library trampoline code (which is different from
2334 indirect function call trampolines).
2336 3. Skip bigtoc fixup code.
2338 Result is desired PC to step until, or NULL if we are not in
2339 code that should be skipped. */
2342 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2344 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2345 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2346 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2347 unsigned int ii
, op
;
2349 CORE_ADDR solib_target_pc
;
2350 struct bound_minimal_symbol msymbol
;
2352 static unsigned trampoline_code
[] =
2354 0x800b0000, /* l r0,0x0(r11) */
2355 0x90410014, /* st r2,0x14(r1) */
2356 0x7c0903a6, /* mtctr r0 */
2357 0x804b0004, /* l r2,0x4(r11) */
2358 0x816b0008, /* l r11,0x8(r11) */
2359 0x4e800420, /* bctr */
2360 0x4e800020, /* br */
2364 /* Check for bigtoc fixup code. */
2365 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2367 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2368 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2370 /* Double-check that the third instruction from PC is relative "b". */
2371 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2372 if ((op
& 0xfc000003) == 0x48000000)
2374 /* Extract bits 6-29 as a signed 24-bit relative word address and
2375 add it to the containing PC. */
2376 rel
= ((int)(op
<< 6) >> 6);
2377 return pc
+ 8 + rel
;
2381 /* If pc is in a shared library trampoline, return its target. */
2382 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2383 if (solib_target_pc
)
2384 return solib_target_pc
;
2386 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2388 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2389 if (op
!= trampoline_code
[ii
])
2392 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2394 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2398 /* ISA-specific vector types. */
2400 static struct type
*
2401 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2403 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2405 if (!tdep
->ppc_builtin_type_vec64
)
2407 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2409 /* The type we're building is this: */
2411 union __gdb_builtin_type_vec64
2415 int32_t v2_int32
[2];
2416 int16_t v4_int16
[4];
2423 t
= arch_composite_type (gdbarch
,
2424 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2425 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2426 append_composite_type_field (t
, "v2_float",
2427 init_vector_type (bt
->builtin_float
, 2));
2428 append_composite_type_field (t
, "v2_int32",
2429 init_vector_type (bt
->builtin_int32
, 2));
2430 append_composite_type_field (t
, "v4_int16",
2431 init_vector_type (bt
->builtin_int16
, 4));
2432 append_composite_type_field (t
, "v8_int8",
2433 init_vector_type (bt
->builtin_int8
, 8));
2435 TYPE_VECTOR (t
) = 1;
2436 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2437 tdep
->ppc_builtin_type_vec64
= t
;
2440 return tdep
->ppc_builtin_type_vec64
;
2443 /* Vector 128 type. */
2445 static struct type
*
2446 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2448 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2450 if (!tdep
->ppc_builtin_type_vec128
)
2452 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2454 /* The type we're building is this
2456 type = union __ppc_builtin_type_vec128 {
2458 double v2_double[2];
2460 int32_t v4_int32[4];
2461 int16_t v8_int16[8];
2462 int8_t v16_int8[16];
2468 t
= arch_composite_type (gdbarch
,
2469 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2470 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2471 append_composite_type_field (t
, "v2_double",
2472 init_vector_type (bt
->builtin_double
, 2));
2473 append_composite_type_field (t
, "v4_float",
2474 init_vector_type (bt
->builtin_float
, 4));
2475 append_composite_type_field (t
, "v4_int32",
2476 init_vector_type (bt
->builtin_int32
, 4));
2477 append_composite_type_field (t
, "v8_int16",
2478 init_vector_type (bt
->builtin_int16
, 8));
2479 append_composite_type_field (t
, "v16_int8",
2480 init_vector_type (bt
->builtin_int8
, 16));
2482 TYPE_VECTOR (t
) = 1;
2483 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2484 tdep
->ppc_builtin_type_vec128
= t
;
2487 return tdep
->ppc_builtin_type_vec128
;
2490 /* Return the name of register number REGNO, or the empty string if it
2491 is an anonymous register. */
2494 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2496 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2498 /* The upper half "registers" have names in the XML description,
2499 but we present only the low GPRs and the full 64-bit registers
2501 if (tdep
->ppc_ev0_upper_regnum
>= 0
2502 && tdep
->ppc_ev0_upper_regnum
<= regno
2503 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2506 /* Hide the upper halves of the vs0~vs31 registers. */
2507 if (tdep
->ppc_vsr0_regnum
>= 0
2508 && tdep
->ppc_vsr0_upper_regnum
<= regno
2509 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2512 /* Check if the SPE pseudo registers are available. */
2513 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2515 static const char *const spe_regnames
[] = {
2516 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2517 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2518 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2519 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2521 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2524 /* Check if the decimal128 pseudo-registers are available. */
2525 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2527 static const char *const dfp128_regnames
[] = {
2528 "dl0", "dl1", "dl2", "dl3",
2529 "dl4", "dl5", "dl6", "dl7",
2530 "dl8", "dl9", "dl10", "dl11",
2531 "dl12", "dl13", "dl14", "dl15"
2533 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2536 /* Check if this is a VSX pseudo-register. */
2537 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2539 static const char *const vsx_regnames
[] = {
2540 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2541 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2542 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2543 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2544 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2545 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2546 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2547 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2548 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2550 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2553 /* Check if the this is a Extended FP pseudo-register. */
2554 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2556 static const char *const efpr_regnames
[] = {
2557 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2558 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2559 "f46", "f47", "f48", "f49", "f50", "f51",
2560 "f52", "f53", "f54", "f55", "f56", "f57",
2561 "f58", "f59", "f60", "f61", "f62", "f63"
2563 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2566 return tdesc_register_name (gdbarch
, regno
);
2569 /* Return the GDB type object for the "standard" data type of data in
2572 static struct type
*
2573 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2575 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2577 /* These are the only pseudo-registers we support. */
2578 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2579 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2580 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2581 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2583 /* These are the e500 pseudo-registers. */
2584 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2585 return rs6000_builtin_type_vec64 (gdbarch
);
2586 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2587 /* PPC decimal128 pseudo-registers. */
2588 return builtin_type (gdbarch
)->builtin_declong
;
2589 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2590 /* POWER7 VSX pseudo-registers. */
2591 return rs6000_builtin_type_vec128 (gdbarch
);
2593 /* POWER7 Extended FP pseudo-registers. */
2594 return builtin_type (gdbarch
)->builtin_double
;
2597 /* Is REGNUM a member of REGGROUP? */
2599 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2600 struct reggroup
*group
)
2602 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2604 /* These are the only pseudo-registers we support. */
2605 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2606 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2607 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2608 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2610 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2611 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2612 return group
== all_reggroup
|| group
== vector_reggroup
;
2614 /* PPC decimal128 or Extended FP pseudo-registers. */
2615 return group
== all_reggroup
|| group
== float_reggroup
;
2618 /* The register format for RS/6000 floating point registers is always
2619 double, we need a conversion if the memory format is float. */
2622 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2625 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2627 return (tdep
->ppc_fp0_regnum
>= 0
2628 && regnum
>= tdep
->ppc_fp0_regnum
2629 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2630 && TYPE_CODE (type
) == TYPE_CODE_FLT
2631 && TYPE_LENGTH (type
)
2632 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2636 rs6000_register_to_value (struct frame_info
*frame
,
2640 int *optimizedp
, int *unavailablep
)
2642 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2643 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2645 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2647 if (!get_frame_register_bytes (frame
, regnum
, 0,
2648 register_size (gdbarch
, regnum
),
2649 from
, optimizedp
, unavailablep
))
2652 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2654 *optimizedp
= *unavailablep
= 0;
2659 rs6000_value_to_register (struct frame_info
*frame
,
2662 const gdb_byte
*from
)
2664 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2665 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2667 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2669 target_float_convert (from
, type
,
2670 to
, builtin_type (gdbarch
)->builtin_double
);
2671 put_frame_register (frame
, regnum
, to
);
2674 /* The type of a function that moves the value of REG between CACHE
2675 or BUF --- in either direction. */
2676 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2679 /* Move SPE vector register values between a 64-bit buffer and the two
2680 32-bit raw register halves in a regcache. This function handles
2681 both splitting a 64-bit value into two 32-bit halves, and joining
2682 two halves into a whole 64-bit value, depending on the function
2683 passed as the MOVE argument.
2685 EV_REG must be the number of an SPE evN vector register --- a
2686 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2689 Call MOVE once for each 32-bit half of that register, passing
2690 REGCACHE, the number of the raw register corresponding to that
2691 half, and the address of the appropriate half of BUFFER.
2693 For example, passing 'regcache_raw_read' as the MOVE function will
2694 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2695 'regcache_raw_supply' will supply the contents of BUFFER to the
2696 appropriate pair of raw registers in REGCACHE.
2698 You may need to cast away some 'const' qualifiers when passing
2699 MOVE, since this function can't tell at compile-time which of
2700 REGCACHE or BUFFER is acting as the source of the data. If C had
2701 co-variant type qualifiers, ... */
2703 static enum register_status
2704 e500_move_ev_register (move_ev_register_func move
,
2705 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2707 struct gdbarch
*arch
= regcache
->arch ();
2708 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2710 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2711 enum register_status status
;
2713 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2715 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2717 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2719 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2721 if (status
== REG_VALID
)
2722 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2727 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2728 if (status
== REG_VALID
)
2729 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2736 static enum register_status
2737 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2739 regcache_raw_write (regcache
, regnum
, (const gdb_byte
*) buffer
);
2744 static enum register_status
2745 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2746 int ev_reg
, gdb_byte
*buffer
)
2748 struct gdbarch
*arch
= regcache
->arch ();
2749 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2751 enum register_status status
;
2753 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2755 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2757 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2759 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2761 if (status
== REG_VALID
)
2762 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2767 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2768 if (status
== REG_VALID
)
2769 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2778 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2779 int reg_nr
, const gdb_byte
*buffer
)
2781 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2782 reg_nr
, (void *) buffer
);
2785 /* Read method for DFP pseudo-registers. */
2786 static enum register_status
2787 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2788 int reg_nr
, gdb_byte
*buffer
)
2790 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2791 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2792 enum register_status status
;
2794 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2796 /* Read two FP registers to form a whole dl register. */
2797 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2798 2 * reg_index
, buffer
);
2799 if (status
== REG_VALID
)
2800 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2801 2 * reg_index
+ 1, buffer
+ 8);
2805 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2806 2 * reg_index
+ 1, buffer
);
2807 if (status
== REG_VALID
)
2808 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2809 2 * reg_index
, buffer
+ 8);
2815 /* Write method for DFP pseudo-registers. */
2817 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2818 int reg_nr
, const gdb_byte
*buffer
)
2820 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2821 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2823 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2825 /* Write each half of the dl register into a separate
2827 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2828 2 * reg_index
, buffer
);
2829 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2830 2 * reg_index
+ 1, buffer
+ 8);
2834 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2835 2 * reg_index
+ 1, buffer
);
2836 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2837 2 * reg_index
, buffer
+ 8);
2841 /* Read method for POWER7 VSX pseudo-registers. */
2842 static enum register_status
2843 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2844 int reg_nr
, gdb_byte
*buffer
)
2846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2847 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2848 enum register_status status
;
2850 /* Read the portion that overlaps the VMX registers. */
2852 status
= regcache
->raw_read (tdep
->ppc_vr0_regnum
+
2853 reg_index
- 32, buffer
);
2855 /* Read the portion that overlaps the FPR registers. */
2856 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2858 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2860 if (status
== REG_VALID
)
2861 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2862 reg_index
, buffer
+ 8);
2866 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2867 reg_index
, buffer
+ 8);
2868 if (status
== REG_VALID
)
2869 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2876 /* Write method for POWER7 VSX pseudo-registers. */
2878 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2879 int reg_nr
, const gdb_byte
*buffer
)
2881 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2882 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2884 /* Write the portion that overlaps the VMX registers. */
2886 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2887 reg_index
- 32, buffer
);
2889 /* Write the portion that overlaps the FPR registers. */
2890 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2892 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2894 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2895 reg_index
, buffer
+ 8);
2899 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2900 reg_index
, buffer
+ 8);
2901 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2906 /* Read method for POWER7 Extended FP pseudo-registers. */
2907 static enum register_status
2908 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2909 int reg_nr
, gdb_byte
*buffer
)
2911 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2912 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2913 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2915 /* Read the portion that overlaps the VMX register. */
2916 return regcache
->raw_read_part (tdep
->ppc_vr0_regnum
+ reg_index
,
2917 offset
, register_size (gdbarch
, reg_nr
),
2921 /* Write method for POWER7 Extended FP pseudo-registers. */
2923 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2924 int reg_nr
, const gdb_byte
*buffer
)
2926 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2927 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2928 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2930 /* Write the portion that overlaps the VMX register. */
2931 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2932 offset
, register_size (gdbarch
, reg_nr
),
2936 static enum register_status
2937 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2938 readable_regcache
*regcache
,
2939 int reg_nr
, gdb_byte
*buffer
)
2941 struct gdbarch
*regcache_arch
= regcache
->arch ();
2942 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2944 gdb_assert (regcache_arch
== gdbarch
);
2946 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2947 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2948 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2949 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2950 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2951 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2952 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2953 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2955 internal_error (__FILE__
, __LINE__
,
2956 _("rs6000_pseudo_register_read: "
2957 "called on unexpected register '%s' (%d)"),
2958 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2962 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2963 struct regcache
*regcache
,
2964 int reg_nr
, const gdb_byte
*buffer
)
2966 struct gdbarch
*regcache_arch
= regcache
->arch ();
2967 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2969 gdb_assert (regcache_arch
== gdbarch
);
2971 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2972 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2973 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2974 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2975 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2976 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2977 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2978 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2980 internal_error (__FILE__
, __LINE__
,
2981 _("rs6000_pseudo_register_write: "
2982 "called on unexpected register '%s' (%d)"),
2983 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2987 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2988 struct agent_expr
*ax
, int reg_nr
)
2990 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2991 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2993 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
2994 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
2995 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
2997 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2999 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3000 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
3001 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
3003 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3005 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3008 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
3012 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
3013 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
3016 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3018 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3019 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
3022 internal_error (__FILE__
, __LINE__
,
3023 _("rs6000_pseudo_register_collect: "
3024 "called on unexpected register '%s' (%d)"),
3025 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3031 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3032 struct agent_expr
*ax
, struct axs_value
*value
,
3035 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3036 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3037 value
->kind
= axs_lvalue_register
;
3038 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3042 /* Convert a DBX STABS register number to a GDB register number. */
3044 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3046 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3048 if (0 <= num
&& num
<= 31)
3049 return tdep
->ppc_gp0_regnum
+ num
;
3050 else if (32 <= num
&& num
<= 63)
3051 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3052 specifies registers the architecture doesn't have? Our
3053 callers don't check the value we return. */
3054 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3055 else if (77 <= num
&& num
<= 108)
3056 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3057 else if (1200 <= num
&& num
< 1200 + 32)
3058 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3063 return tdep
->ppc_mq_regnum
;
3065 return tdep
->ppc_lr_regnum
;
3067 return tdep
->ppc_ctr_regnum
;
3069 return tdep
->ppc_xer_regnum
;
3071 return tdep
->ppc_vrsave_regnum
;
3073 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3075 return tdep
->ppc_acc_regnum
;
3077 return tdep
->ppc_spefscr_regnum
;
3084 /* Convert a Dwarf 2 register number to a GDB register number. */
3086 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3088 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3090 if (0 <= num
&& num
<= 31)
3091 return tdep
->ppc_gp0_regnum
+ num
;
3092 else if (32 <= num
&& num
<= 63)
3093 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3094 specifies registers the architecture doesn't have? Our
3095 callers don't check the value we return. */
3096 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3097 else if (1124 <= num
&& num
< 1124 + 32)
3098 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3099 else if (1200 <= num
&& num
< 1200 + 32)
3100 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3105 return tdep
->ppc_cr_regnum
;
3107 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3109 return tdep
->ppc_acc_regnum
;
3111 return tdep
->ppc_mq_regnum
;
3113 return tdep
->ppc_xer_regnum
;
3115 return tdep
->ppc_lr_regnum
;
3117 return tdep
->ppc_ctr_regnum
;
3119 return tdep
->ppc_vrsave_regnum
;
3121 return tdep
->ppc_spefscr_regnum
;
3127 /* Translate a .eh_frame register to DWARF register, or adjust a
3128 .debug_frame register. */
3131 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3133 /* GCC releases before 3.4 use GCC internal register numbering in
3134 .debug_frame (and .debug_info, et cetera). The numbering is
3135 different from the standard SysV numbering for everything except
3136 for GPRs and FPRs. We can not detect this problem in most cases
3137 - to get accurate debug info for variables living in lr, ctr, v0,
3138 et cetera, use a newer version of GCC. But we must detect
3139 one important case - lr is in column 65 in .debug_frame output,
3142 GCC 3.4, and the "hammer" branch, have a related problem. They
3143 record lr register saves in .debug_frame as 108, but still record
3144 the return column as 65. We fix that up too.
3146 We can do this because 65 is assigned to fpsr, and GCC never
3147 generates debug info referring to it. To add support for
3148 handwritten debug info that restores fpsr, we would need to add a
3149 producer version check to this. */
3158 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3159 internal register numbering; translate that to the standard DWARF2
3160 register numbering. */
3161 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3163 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3164 return num
- 68 + 86;
3165 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3166 return num
- 77 + 1124;
3178 case 109: /* vrsave */
3180 case 110: /* vscr */
3182 case 111: /* spe_acc */
3184 case 112: /* spefscr */
3192 /* Handling the various POWER/PowerPC variants. */
3194 /* Information about a particular processor variant. */
3198 /* Name of this variant. */
3201 /* English description of the variant. */
3202 const char *description
;
3204 /* bfd_arch_info.arch corresponding to variant. */
3205 enum bfd_architecture arch
;
3207 /* bfd_arch_info.mach corresponding to variant. */
3210 /* Target description for this variant. */
3211 struct target_desc
**tdesc
;
3214 static struct variant variants
[] =
3216 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3217 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3218 {"power", "POWER user-level", bfd_arch_rs6000
,
3219 bfd_mach_rs6k
, &tdesc_rs6000
},
3220 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3221 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3222 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3223 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3224 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3225 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3226 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3227 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3228 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3229 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3230 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3231 604, &tdesc_powerpc_604
},
3232 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3233 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3234 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3235 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3236 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3237 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3238 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3239 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3240 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3241 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3242 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3243 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3246 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3247 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3248 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3249 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3250 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3251 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3252 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3253 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3254 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3255 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3256 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3257 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3259 /* FIXME: I haven't checked the register sets of the following. */
3260 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3261 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3262 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3263 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3264 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3265 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3267 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3270 /* Return the variant corresponding to architecture ARCH and machine number
3271 MACH. If no such variant exists, return null. */
3273 static const struct variant
*
3274 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3276 const struct variant
*v
;
3278 for (v
= variants
; v
->name
; v
++)
3279 if (arch
== v
->arch
&& mach
== v
->mach
)
3287 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3289 return frame_unwind_register_unsigned (next_frame
,
3290 gdbarch_pc_regnum (gdbarch
));
3293 static struct frame_id
3294 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3296 return frame_id_build (get_frame_register_unsigned
3297 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3298 get_frame_pc (this_frame
));
3301 struct rs6000_frame_cache
3304 CORE_ADDR initial_sp
;
3305 struct trad_frame_saved_reg
*saved_regs
;
3307 /* Set BASE_P to true if this frame cache is properly initialized.
3308 Otherwise set to false because some registers or memory cannot
3311 /* Cache PC for building unavailable frame. */
3315 static struct rs6000_frame_cache
*
3316 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3318 struct rs6000_frame_cache
*cache
;
3319 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3320 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3321 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3322 struct rs6000_framedata fdata
;
3323 int wordsize
= tdep
->wordsize
;
3324 CORE_ADDR func
= 0, pc
= 0;
3326 if ((*this_cache
) != NULL
)
3327 return (struct rs6000_frame_cache
*) (*this_cache
);
3328 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3329 (*this_cache
) = cache
;
3331 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3335 func
= get_frame_func (this_frame
);
3337 pc
= get_frame_pc (this_frame
);
3338 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3340 /* Figure out the parent's stack pointer. */
3342 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3343 address of the current frame. Things might be easier if the
3344 ->frame pointed to the outer-most address of the frame. In
3345 the mean time, the address of the prev frame is used as the
3346 base address of this frame. */
3347 cache
->base
= get_frame_register_unsigned
3348 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3350 CATCH (ex
, RETURN_MASK_ERROR
)
3352 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3353 throw_exception (ex
);
3354 return (struct rs6000_frame_cache
*) (*this_cache
);
3358 /* If the function appears to be frameless, check a couple of likely
3359 indicators that we have simply failed to find the frame setup.
3360 Two common cases of this are missing symbols (i.e.
3361 get_frame_func returns the wrong address or 0), and assembly
3362 stubs which have a fast exit path but set up a frame on the slow
3365 If the LR appears to return to this function, then presume that
3366 we have an ABI compliant frame that we failed to find. */
3367 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3372 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3373 if (func
== 0 && saved_lr
== pc
)
3377 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3378 if (func
== saved_func
)
3384 fdata
.frameless
= 0;
3385 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3389 if (!fdata
.frameless
)
3391 /* Frameless really means stackless. */
3394 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3395 byte_order
, &backchain
))
3396 cache
->base
= (CORE_ADDR
) backchain
;
3399 trad_frame_set_value (cache
->saved_regs
,
3400 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3402 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3403 All fpr's from saved_fpr to fp31 are saved. */
3405 if (fdata
.saved_fpr
>= 0)
3408 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3410 /* If skip_prologue says floating-point registers were saved,
3411 but the current architecture has no floating-point registers,
3412 then that's strange. But we have no indices to even record
3413 the addresses under, so we just ignore it. */
3414 if (ppc_floating_point_unit_p (gdbarch
))
3415 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3417 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3422 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3423 All gpr's from saved_gpr to gpr31 are saved (except during the
3426 if (fdata
.saved_gpr
>= 0)
3429 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3430 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3432 if (fdata
.gpr_mask
& (1U << i
))
3433 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3434 gpr_addr
+= wordsize
;
3438 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3439 All vr's from saved_vr to vr31 are saved. */
3440 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3442 if (fdata
.saved_vr
>= 0)
3445 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3446 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3448 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3449 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3454 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3455 All vr's from saved_ev to ev31 are saved. ????? */
3456 if (tdep
->ppc_ev0_regnum
!= -1)
3458 if (fdata
.saved_ev
>= 0)
3461 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3462 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3464 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3466 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3467 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3468 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3473 /* If != 0, fdata.cr_offset is the offset from the frame that
3475 if (fdata
.cr_offset
!= 0)
3476 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3477 = cache
->base
+ fdata
.cr_offset
;
3479 /* If != 0, fdata.lr_offset is the offset from the frame that
3481 if (fdata
.lr_offset
!= 0)
3482 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3483 = cache
->base
+ fdata
.lr_offset
;
3484 else if (fdata
.lr_register
!= -1)
3485 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3486 /* The PC is found in the link register. */
3487 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3488 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3490 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3491 holds the VRSAVE. */
3492 if (fdata
.vrsave_offset
!= 0)
3493 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3494 = cache
->base
+ fdata
.vrsave_offset
;
3496 if (fdata
.alloca_reg
< 0)
3497 /* If no alloca register used, then fi->frame is the value of the
3498 %sp for this frame, and it is good enough. */
3500 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3503 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3510 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3511 struct frame_id
*this_id
)
3513 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3518 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3522 /* This marks the outermost frame. */
3523 if (info
->base
== 0)
3526 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3529 static struct value
*
3530 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3531 void **this_cache
, int regnum
)
3533 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3535 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3538 static const struct frame_unwind rs6000_frame_unwind
=
3541 default_frame_unwind_stop_reason
,
3542 rs6000_frame_this_id
,
3543 rs6000_frame_prev_register
,
3545 default_frame_sniffer
3548 /* Allocate and initialize a frame cache for an epilogue frame.
3549 SP is restored and prev-PC is stored in LR. */
3551 static struct rs6000_frame_cache
*
3552 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3554 struct rs6000_frame_cache
*cache
;
3555 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3556 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3559 return (struct rs6000_frame_cache
*) *this_cache
;
3561 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3562 (*this_cache
) = cache
;
3563 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3567 /* At this point the stack looks as if we just entered the
3568 function, and the return address is stored in LR. */
3571 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3572 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3575 cache
->initial_sp
= sp
;
3577 trad_frame_set_value (cache
->saved_regs
,
3578 gdbarch_pc_regnum (gdbarch
), lr
);
3580 CATCH (ex
, RETURN_MASK_ERROR
)
3582 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3583 throw_exception (ex
);
3590 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3591 Return the frame ID of an epilogue frame. */
3594 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3595 void **this_cache
, struct frame_id
*this_id
)
3598 struct rs6000_frame_cache
*info
=
3599 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3601 pc
= get_frame_func (this_frame
);
3602 if (info
->base
== 0)
3603 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3605 (*this_id
) = frame_id_build (info
->base
, pc
);
3608 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3609 Return the register value of REGNUM in previous frame. */
3611 static struct value
*
3612 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3613 void **this_cache
, int regnum
)
3615 struct rs6000_frame_cache
*info
=
3616 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3617 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3620 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3621 Check whether this an epilogue frame. */
3624 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3625 struct frame_info
*this_frame
,
3626 void **this_prologue_cache
)
3628 if (frame_relative_level (this_frame
) == 0)
3629 return rs6000_in_function_epilogue_frame_p (this_frame
,
3630 get_frame_arch (this_frame
),
3631 get_frame_pc (this_frame
));
3636 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3637 a function without debug information. */
3639 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3642 default_frame_unwind_stop_reason
,
3643 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3645 rs6000_epilogue_frame_sniffer
3650 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3652 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3654 return info
->initial_sp
;
3657 static const struct frame_base rs6000_frame_base
= {
3658 &rs6000_frame_unwind
,
3659 rs6000_frame_base_address
,
3660 rs6000_frame_base_address
,
3661 rs6000_frame_base_address
3664 static const struct frame_base
*
3665 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3667 return &rs6000_frame_base
;
3670 /* DWARF-2 frame support. Used to handle the detection of
3671 clobbered registers during function calls. */
3674 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3675 struct dwarf2_frame_state_reg
*reg
,
3676 struct frame_info
*this_frame
)
3678 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3680 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3681 non-volatile registers. We will use the same code for both. */
3683 /* Call-saved GP registers. */
3684 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3685 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3686 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3687 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3689 /* Call-clobbered GP registers. */
3690 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3691 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3692 || (regnum
== tdep
->ppc_gp0_regnum
))
3693 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3695 /* Deal with FP registers, if supported. */
3696 if (tdep
->ppc_fp0_regnum
>= 0)
3698 /* Call-saved FP registers. */
3699 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3700 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3701 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3703 /* Call-clobbered FP registers. */
3704 if ((regnum
>= tdep
->ppc_fp0_regnum
3705 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3706 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3709 /* Deal with ALTIVEC registers, if supported. */
3710 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3712 /* Call-saved Altivec registers. */
3713 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3714 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3715 || regnum
== tdep
->ppc_vrsave_regnum
)
3716 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3718 /* Call-clobbered Altivec registers. */
3719 if ((regnum
>= tdep
->ppc_vr0_regnum
3720 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3721 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3724 /* Handle PC register and Stack Pointer correctly. */
3725 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3726 reg
->how
= DWARF2_FRAME_REG_RA
;
3727 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3728 reg
->how
= DWARF2_FRAME_REG_CFA
;
3732 /* Return true if a .gnu_attributes section exists in BFD and it
3733 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3734 section exists in BFD and it indicates that SPE extensions are in
3735 use. Check the .gnu.attributes section first, as the binary might be
3736 compiled for SPE, but not actually using SPE instructions. */
3739 bfd_uses_spe_extensions (bfd
*abfd
)
3742 gdb_byte
*contents
= NULL
;
3752 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3753 could be using the SPE vector abi without actually using any spe
3754 bits whatsoever. But it's close enough for now. */
3755 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3756 Tag_GNU_Power_ABI_Vector
);
3757 if (vector_abi
== 3)
3761 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3765 size
= bfd_get_section_size (sect
);
3766 contents
= (gdb_byte
*) xmalloc (size
);
3767 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3773 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3779 char name[name_len rounded up to 4-byte alignment];
3780 char data[data_len];
3783 Technically, there's only supposed to be one such structure in a
3784 given apuinfo section, but the linker is not always vigilant about
3785 merging apuinfo sections from input files. Just go ahead and parse
3786 them all, exiting early when we discover the binary uses SPE
3789 It's not specified in what endianness the information in this
3790 section is stored. Assume that it's the endianness of the BFD. */
3794 unsigned int name_len
;
3795 unsigned int data_len
;
3798 /* If we can't read the first three fields, we're done. */
3802 name_len
= bfd_get_32 (abfd
, ptr
);
3803 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3804 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3805 type
= bfd_get_32 (abfd
, ptr
+ 8);
3808 /* The name must be "APUinfo\0". */
3810 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3814 /* The type must be 2. */
3818 /* The data is stored as a series of uint32. The upper half of
3819 each uint32 indicates the particular APU used and the lower
3820 half indicates the revision of that APU. We just care about
3823 /* Not 4-byte quantities. */
3829 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3830 unsigned int apu
= apuinfo
>> 16;
3834 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3836 if (apu
== 0x100 || apu
== 0x101)
3851 /* These are macros for parsing instruction fields (I.1.6.28) */
3853 #define PPC_FIELD(value, from, len) \
3854 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3855 #define PPC_SEXT(v, bs) \
3856 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3857 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3858 - ((CORE_ADDR) 1 << ((bs) - 1)))
3859 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3860 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3861 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3862 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3863 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3864 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3865 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3866 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3867 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3868 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3869 | (PPC_FIELD (insn, 16, 5) << 5))
3870 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3871 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3872 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3873 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3874 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3875 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3876 #define PPC_OE(insn) PPC_BIT (insn, 21)
3877 #define PPC_RC(insn) PPC_BIT (insn, 31)
3878 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3879 #define PPC_LK(insn) PPC_BIT (insn, 31)
3880 #define PPC_TX(insn) PPC_BIT (insn, 31)
3881 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3883 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3884 #define PPC_XER_NB(xer) (xer & 0x7f)
3886 /* Record Vector-Scalar Registers.
3887 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3888 Otherwise, it's just a VR register. Record them accordingly. */
3891 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3893 if (vsr
< 0 || vsr
>= 64)
3898 if (tdep
->ppc_vr0_regnum
>= 0)
3899 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3903 if (tdep
->ppc_fp0_regnum
>= 0)
3904 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3905 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3906 record_full_arch_list_add_reg (regcache
,
3907 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3913 /* Parse and record instructions primary opcode-4 at ADDR.
3914 Return 0 if successful. */
3917 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3918 CORE_ADDR addr
, uint32_t insn
)
3920 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3921 int ext
= PPC_FIELD (insn
, 21, 11);
3922 int vra
= PPC_FIELD (insn
, 11, 5);
3926 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3927 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3928 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3929 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3930 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3932 case 42: /* Vector Select */
3933 case 43: /* Vector Permute */
3934 case 59: /* Vector Permute Right-indexed */
3935 case 44: /* Vector Shift Left Double by Octet Immediate */
3936 case 45: /* Vector Permute and Exclusive-OR */
3937 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3938 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3939 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3940 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3941 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3942 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3943 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3944 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3945 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3946 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3947 case 46: /* Vector Multiply-Add Single-Precision */
3948 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3949 record_full_arch_list_add_reg (regcache
,
3950 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3953 case 48: /* Multiply-Add High Doubleword */
3954 case 49: /* Multiply-Add High Doubleword Unsigned */
3955 case 51: /* Multiply-Add Low Doubleword */
3956 record_full_arch_list_add_reg (regcache
,
3957 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3961 switch ((ext
& 0x1ff))
3964 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3965 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3966 && vra
!= 4 /* Decimal Convert To Zoned */
3967 && vra
!= 5 /* Decimal Convert To National */
3968 && vra
!= 6 /* Decimal Convert From Zoned */
3969 && vra
!= 7 /* Decimal Convert From National */
3970 && vra
!= 31) /* Decimal Set Sign */
3972 /* 5.16 Decimal Integer Arithmetic Instructions */
3973 case 1: /* Decimal Add Modulo */
3974 case 65: /* Decimal Subtract Modulo */
3976 case 193: /* Decimal Shift */
3977 case 129: /* Decimal Unsigned Shift */
3978 case 449: /* Decimal Shift and Round */
3980 case 257: /* Decimal Truncate */
3981 case 321: /* Decimal Unsigned Truncate */
3983 /* Bit-21 should be set. */
3984 if (!PPC_BIT (insn
, 21))
3987 record_full_arch_list_add_reg (regcache
,
3988 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3989 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3993 /* Bit-21 is used for RC */
3994 switch (ext
& 0x3ff)
3996 case 6: /* Vector Compare Equal To Unsigned Byte */
3997 case 70: /* Vector Compare Equal To Unsigned Halfword */
3998 case 134: /* Vector Compare Equal To Unsigned Word */
3999 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4000 case 774: /* Vector Compare Greater Than Signed Byte */
4001 case 838: /* Vector Compare Greater Than Signed Halfword */
4002 case 902: /* Vector Compare Greater Than Signed Word */
4003 case 967: /* Vector Compare Greater Than Signed Doubleword */
4004 case 518: /* Vector Compare Greater Than Unsigned Byte */
4005 case 646: /* Vector Compare Greater Than Unsigned Word */
4006 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4007 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4008 case 966: /* Vector Compare Bounds Single-Precision */
4009 case 198: /* Vector Compare Equal To Single-Precision */
4010 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4011 case 710: /* Vector Compare Greater Than Single-Precision */
4012 case 7: /* Vector Compare Not Equal Byte */
4013 case 71: /* Vector Compare Not Equal Halfword */
4014 case 135: /* Vector Compare Not Equal Word */
4015 case 263: /* Vector Compare Not Equal or Zero Byte */
4016 case 327: /* Vector Compare Not Equal or Zero Halfword */
4017 case 391: /* Vector Compare Not Equal or Zero Word */
4019 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4020 record_full_arch_list_add_reg (regcache
,
4021 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4029 case 0: /* Vector Count Leading Zero Least-Significant Bits
4031 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4033 record_full_arch_list_add_reg (regcache
,
4034 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4037 case 6: /* Vector Negate Word */
4038 case 7: /* Vector Negate Doubleword */
4039 case 8: /* Vector Parity Byte Word */
4040 case 9: /* Vector Parity Byte Doubleword */
4041 case 10: /* Vector Parity Byte Quadword */
4042 case 16: /* Vector Extend Sign Byte To Word */
4043 case 17: /* Vector Extend Sign Halfword To Word */
4044 case 24: /* Vector Extend Sign Byte To Doubleword */
4045 case 25: /* Vector Extend Sign Halfword To Doubleword */
4046 case 26: /* Vector Extend Sign Word To Doubleword */
4047 case 28: /* Vector Count Trailing Zeros Byte */
4048 case 29: /* Vector Count Trailing Zeros Halfword */
4049 case 30: /* Vector Count Trailing Zeros Word */
4050 case 31: /* Vector Count Trailing Zeros Doubleword */
4051 record_full_arch_list_add_reg (regcache
,
4052 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4059 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4060 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4061 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4062 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4063 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4064 case 462: /* Vector Pack Signed Word Signed Saturate */
4065 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4066 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4067 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4068 case 512: /* Vector Add Unsigned Byte Saturate */
4069 case 576: /* Vector Add Unsigned Halfword Saturate */
4070 case 640: /* Vector Add Unsigned Word Saturate */
4071 case 768: /* Vector Add Signed Byte Saturate */
4072 case 832: /* Vector Add Signed Halfword Saturate */
4073 case 896: /* Vector Add Signed Word Saturate */
4074 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4075 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4076 case 1664: /* Vector Subtract Unsigned Word Saturate */
4077 case 1792: /* Vector Subtract Signed Byte Saturate */
4078 case 1856: /* Vector Subtract Signed Halfword Saturate */
4079 case 1920: /* Vector Subtract Signed Word Saturate */
4081 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4082 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4083 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4084 case 1672: /* Vector Sum across Half Signed Word Saturate */
4085 case 1928: /* Vector Sum across Signed Word Saturate */
4086 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4087 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4088 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4090 case 12: /* Vector Merge High Byte */
4091 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4092 case 76: /* Vector Merge High Halfword */
4093 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4094 case 140: /* Vector Merge High Word */
4095 case 268: /* Vector Merge Low Byte */
4096 case 332: /* Vector Merge Low Halfword */
4097 case 396: /* Vector Merge Low Word */
4098 case 526: /* Vector Unpack High Signed Byte */
4099 case 590: /* Vector Unpack High Signed Halfword */
4100 case 654: /* Vector Unpack Low Signed Byte */
4101 case 718: /* Vector Unpack Low Signed Halfword */
4102 case 782: /* Vector Pack Pixel */
4103 case 846: /* Vector Unpack High Pixel */
4104 case 974: /* Vector Unpack Low Pixel */
4105 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4106 case 1614: /* Vector Unpack High Signed Word */
4107 case 1676: /* Vector Merge Odd Word */
4108 case 1742: /* Vector Unpack Low Signed Word */
4109 case 1932: /* Vector Merge Even Word */
4110 case 524: /* Vector Splat Byte */
4111 case 588: /* Vector Splat Halfword */
4112 case 652: /* Vector Splat Word */
4113 case 780: /* Vector Splat Immediate Signed Byte */
4114 case 844: /* Vector Splat Immediate Signed Halfword */
4115 case 908: /* Vector Splat Immediate Signed Word */
4116 case 452: /* Vector Shift Left */
4117 case 708: /* Vector Shift Right */
4118 case 1036: /* Vector Shift Left by Octet */
4119 case 1100: /* Vector Shift Right by Octet */
4120 case 0: /* Vector Add Unsigned Byte Modulo */
4121 case 64: /* Vector Add Unsigned Halfword Modulo */
4122 case 128: /* Vector Add Unsigned Word Modulo */
4123 case 192: /* Vector Add Unsigned Doubleword Modulo */
4124 case 256: /* Vector Add Unsigned Quadword Modulo */
4125 case 320: /* Vector Add & write Carry Unsigned Quadword */
4126 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4127 case 8: /* Vector Multiply Odd Unsigned Byte */
4128 case 72: /* Vector Multiply Odd Unsigned Halfword */
4129 case 136: /* Vector Multiply Odd Unsigned Word */
4130 case 264: /* Vector Multiply Odd Signed Byte */
4131 case 328: /* Vector Multiply Odd Signed Halfword */
4132 case 392: /* Vector Multiply Odd Signed Word */
4133 case 520: /* Vector Multiply Even Unsigned Byte */
4134 case 584: /* Vector Multiply Even Unsigned Halfword */
4135 case 648: /* Vector Multiply Even Unsigned Word */
4136 case 776: /* Vector Multiply Even Signed Byte */
4137 case 840: /* Vector Multiply Even Signed Halfword */
4138 case 904: /* Vector Multiply Even Signed Word */
4139 case 137: /* Vector Multiply Unsigned Word Modulo */
4140 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4141 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4142 case 1152: /* Vector Subtract Unsigned Word Modulo */
4143 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4144 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4145 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4146 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4147 case 1282: /* Vector Average Signed Byte */
4148 case 1346: /* Vector Average Signed Halfword */
4149 case 1410: /* Vector Average Signed Word */
4150 case 1026: /* Vector Average Unsigned Byte */
4151 case 1090: /* Vector Average Unsigned Halfword */
4152 case 1154: /* Vector Average Unsigned Word */
4153 case 258: /* Vector Maximum Signed Byte */
4154 case 322: /* Vector Maximum Signed Halfword */
4155 case 386: /* Vector Maximum Signed Word */
4156 case 450: /* Vector Maximum Signed Doubleword */
4157 case 2: /* Vector Maximum Unsigned Byte */
4158 case 66: /* Vector Maximum Unsigned Halfword */
4159 case 130: /* Vector Maximum Unsigned Word */
4160 case 194: /* Vector Maximum Unsigned Doubleword */
4161 case 770: /* Vector Minimum Signed Byte */
4162 case 834: /* Vector Minimum Signed Halfword */
4163 case 898: /* Vector Minimum Signed Word */
4164 case 962: /* Vector Minimum Signed Doubleword */
4165 case 514: /* Vector Minimum Unsigned Byte */
4166 case 578: /* Vector Minimum Unsigned Halfword */
4167 case 642: /* Vector Minimum Unsigned Word */
4168 case 706: /* Vector Minimum Unsigned Doubleword */
4169 case 1028: /* Vector Logical AND */
4170 case 1668: /* Vector Logical Equivalent */
4171 case 1092: /* Vector Logical AND with Complement */
4172 case 1412: /* Vector Logical NAND */
4173 case 1348: /* Vector Logical OR with Complement */
4174 case 1156: /* Vector Logical OR */
4175 case 1284: /* Vector Logical NOR */
4176 case 1220: /* Vector Logical XOR */
4177 case 4: /* Vector Rotate Left Byte */
4178 case 132: /* Vector Rotate Left Word VX-form */
4179 case 68: /* Vector Rotate Left Halfword */
4180 case 196: /* Vector Rotate Left Doubleword */
4181 case 260: /* Vector Shift Left Byte */
4182 case 388: /* Vector Shift Left Word */
4183 case 324: /* Vector Shift Left Halfword */
4184 case 1476: /* Vector Shift Left Doubleword */
4185 case 516: /* Vector Shift Right Byte */
4186 case 644: /* Vector Shift Right Word */
4187 case 580: /* Vector Shift Right Halfword */
4188 case 1732: /* Vector Shift Right Doubleword */
4189 case 772: /* Vector Shift Right Algebraic Byte */
4190 case 900: /* Vector Shift Right Algebraic Word */
4191 case 836: /* Vector Shift Right Algebraic Halfword */
4192 case 964: /* Vector Shift Right Algebraic Doubleword */
4193 case 10: /* Vector Add Single-Precision */
4194 case 74: /* Vector Subtract Single-Precision */
4195 case 1034: /* Vector Maximum Single-Precision */
4196 case 1098: /* Vector Minimum Single-Precision */
4197 case 842: /* Vector Convert From Signed Fixed-Point Word */
4198 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4199 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4200 case 522: /* Vector Round to Single-Precision Integer Nearest */
4201 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4202 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4203 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4204 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4205 case 266: /* Vector Reciprocal Estimate Single-Precision */
4206 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4207 case 1288: /* Vector AES Cipher */
4208 case 1289: /* Vector AES Cipher Last */
4209 case 1352: /* Vector AES Inverse Cipher */
4210 case 1353: /* Vector AES Inverse Cipher Last */
4211 case 1480: /* Vector AES SubBytes */
4212 case 1730: /* Vector SHA-512 Sigma Doubleword */
4213 case 1666: /* Vector SHA-256 Sigma Word */
4214 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4215 case 1160: /* Vector Polynomial Multiply-Sum Word */
4216 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4217 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4218 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4219 case 1794: /* Vector Count Leading Zeros Byte */
4220 case 1858: /* Vector Count Leading Zeros Halfword */
4221 case 1922: /* Vector Count Leading Zeros Word */
4222 case 1986: /* Vector Count Leading Zeros Doubleword */
4223 case 1795: /* Vector Population Count Byte */
4224 case 1859: /* Vector Population Count Halfword */
4225 case 1923: /* Vector Population Count Word */
4226 case 1987: /* Vector Population Count Doubleword */
4227 case 1356: /* Vector Bit Permute Quadword */
4228 case 1484: /* Vector Bit Permute Doubleword */
4229 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4230 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4232 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4233 case 65: /* Vector Multiply-by-10 Extended & write Carry
4234 Unsigned Quadword */
4235 case 1027: /* Vector Absolute Difference Unsigned Byte */
4236 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4237 case 1155: /* Vector Absolute Difference Unsigned Word */
4238 case 1796: /* Vector Shift Right Variable */
4239 case 1860: /* Vector Shift Left Variable */
4240 case 133: /* Vector Rotate Left Word then Mask Insert */
4241 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4242 case 389: /* Vector Rotate Left Word then AND with Mask */
4243 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4244 case 525: /* Vector Extract Unsigned Byte */
4245 case 589: /* Vector Extract Unsigned Halfword */
4246 case 653: /* Vector Extract Unsigned Word */
4247 case 717: /* Vector Extract Doubleword */
4248 case 781: /* Vector Insert Byte */
4249 case 845: /* Vector Insert Halfword */
4250 case 909: /* Vector Insert Word */
4251 case 973: /* Vector Insert Doubleword */
4252 record_full_arch_list_add_reg (regcache
,
4253 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4256 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4257 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4258 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4259 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4260 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4261 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4262 record_full_arch_list_add_reg (regcache
,
4263 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4266 case 1604: /* Move To Vector Status and Control Register */
4267 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4269 case 1540: /* Move From Vector Status and Control Register */
4270 record_full_arch_list_add_reg (regcache
,
4271 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4273 case 833: /* Decimal Copy Sign */
4274 record_full_arch_list_add_reg (regcache
,
4275 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4276 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4280 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4281 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4285 /* Parse and record instructions of primary opcode-19 at ADDR.
4286 Return 0 if successful. */
4289 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4290 CORE_ADDR addr
, uint32_t insn
)
4292 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4293 int ext
= PPC_EXTOP (insn
);
4295 switch (ext
& 0x01f)
4297 case 2: /* Add PC Immediate Shifted */
4298 record_full_arch_list_add_reg (regcache
,
4299 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4305 case 0: /* Move Condition Register Field */
4306 case 33: /* Condition Register NOR */
4307 case 129: /* Condition Register AND with Complement */
4308 case 193: /* Condition Register XOR */
4309 case 225: /* Condition Register NAND */
4310 case 257: /* Condition Register AND */
4311 case 289: /* Condition Register Equivalent */
4312 case 417: /* Condition Register OR with Complement */
4313 case 449: /* Condition Register OR */
4314 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4317 case 16: /* Branch Conditional */
4318 case 560: /* Branch Conditional to Branch Target Address Register */
4319 if ((PPC_BO (insn
) & 0x4) == 0)
4320 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4322 case 528: /* Branch Conditional to Count Register */
4324 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4327 case 150: /* Instruction Synchronize */
4332 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4333 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4337 /* Parse and record instructions of primary opcode-31 at ADDR.
4338 Return 0 if successful. */
4341 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4342 CORE_ADDR addr
, uint32_t insn
)
4344 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4345 int ext
= PPC_EXTOP (insn
);
4347 CORE_ADDR at_dcsz
, ea
= 0;
4348 ULONGEST rb
, ra
, xer
;
4351 /* These instructions have OE bit. */
4352 switch (ext
& 0x1ff)
4354 /* These write RT and XER. Update CR if RC is set. */
4355 case 8: /* Subtract from carrying */
4356 case 10: /* Add carrying */
4357 case 136: /* Subtract from extended */
4358 case 138: /* Add extended */
4359 case 200: /* Subtract from zero extended */
4360 case 202: /* Add to zero extended */
4361 case 232: /* Subtract from minus one extended */
4362 case 234: /* Add to minus one extended */
4363 /* CA is always altered, but SO/OV are only altered when OE=1.
4364 In any case, XER is always altered. */
4365 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4367 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4368 record_full_arch_list_add_reg (regcache
,
4369 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4372 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4373 case 40: /* Subtract from */
4374 case 104: /* Negate */
4375 case 233: /* Multiply low doubleword */
4376 case 235: /* Multiply low word */
4378 case 393: /* Divide Doubleword Extended Unsigned */
4379 case 395: /* Divide Word Extended Unsigned */
4380 case 425: /* Divide Doubleword Extended */
4381 case 427: /* Divide Word Extended */
4382 case 457: /* Divide Doubleword Unsigned */
4383 case 459: /* Divide Word Unsigned */
4384 case 489: /* Divide Doubleword */
4385 case 491: /* Divide Word */
4387 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4389 case 9: /* Multiply High Doubleword Unsigned */
4390 case 11: /* Multiply High Word Unsigned */
4391 case 73: /* Multiply High Doubleword */
4392 case 75: /* Multiply High Word */
4394 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4395 record_full_arch_list_add_reg (regcache
,
4396 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4400 if ((ext
& 0x1f) == 15)
4402 /* Integer Select. bit[16:20] is used for BC. */
4403 record_full_arch_list_add_reg (regcache
,
4404 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4408 if ((ext
& 0xff) == 170)
4410 /* Add Extended using alternate carry bits */
4411 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4412 record_full_arch_list_add_reg (regcache
,
4413 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4419 case 78: /* Determine Leftmost Zero Byte */
4421 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4422 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4423 record_full_arch_list_add_reg (regcache
,
4424 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4427 /* These only write RT. */
4428 case 19: /* Move from condition register */
4429 /* Move From One Condition Register Field */
4430 case 74: /* Add and Generate Sixes */
4431 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4432 case 302: /* Move From Branch History Rolling Buffer */
4433 case 339: /* Move From Special Purpose Register */
4434 case 371: /* Move From Time Base [Phased-Out] */
4435 case 309: /* Load Doubleword Monitored Indexed */
4436 case 128: /* Set Boolean */
4437 case 755: /* Deliver A Random Number */
4438 record_full_arch_list_add_reg (regcache
,
4439 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4442 /* These only write to RA. */
4443 case 51: /* Move From VSR Doubleword */
4444 case 115: /* Move From VSR Word and Zero */
4445 case 122: /* Population count bytes */
4446 case 378: /* Population count words */
4447 case 506: /* Population count doublewords */
4448 case 154: /* Parity Word */
4449 case 186: /* Parity Doubleword */
4450 case 252: /* Bit Permute Doubleword */
4451 case 282: /* Convert Declets To Binary Coded Decimal */
4452 case 314: /* Convert Binary Coded Decimal To Declets */
4453 case 508: /* Compare bytes */
4454 case 307: /* Move From VSR Lower Doubleword */
4455 record_full_arch_list_add_reg (regcache
,
4456 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4459 /* These write CR and optional RA. */
4460 case 792: /* Shift Right Algebraic Word */
4461 case 794: /* Shift Right Algebraic Doubleword */
4462 case 824: /* Shift Right Algebraic Word Immediate */
4463 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4464 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4465 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4466 record_full_arch_list_add_reg (regcache
,
4467 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4469 case 0: /* Compare */
4470 case 32: /* Compare logical */
4471 case 144: /* Move To Condition Register Fields */
4472 /* Move To One Condition Register Field */
4473 case 192: /* Compare Ranged Byte */
4474 case 224: /* Compare Equal Byte */
4475 case 576: /* Move XER to CR Extended */
4476 case 902: /* Paste (should always fail due to single-stepping and
4477 the memory location might not be accessible, so
4479 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4482 /* These write to RT. Update RA if 'update indexed.' */
4483 case 53: /* Load Doubleword with Update Indexed */
4484 case 119: /* Load Byte and Zero with Update Indexed */
4485 case 311: /* Load Halfword and Zero with Update Indexed */
4486 case 55: /* Load Word and Zero with Update Indexed */
4487 case 375: /* Load Halfword Algebraic with Update Indexed */
4488 case 373: /* Load Word Algebraic with Update Indexed */
4489 record_full_arch_list_add_reg (regcache
,
4490 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4492 case 21: /* Load Doubleword Indexed */
4493 case 52: /* Load Byte And Reserve Indexed */
4494 case 116: /* Load Halfword And Reserve Indexed */
4495 case 20: /* Load Word And Reserve Indexed */
4496 case 84: /* Load Doubleword And Reserve Indexed */
4497 case 87: /* Load Byte and Zero Indexed */
4498 case 279: /* Load Halfword and Zero Indexed */
4499 case 23: /* Load Word and Zero Indexed */
4500 case 343: /* Load Halfword Algebraic Indexed */
4501 case 341: /* Load Word Algebraic Indexed */
4502 case 790: /* Load Halfword Byte-Reverse Indexed */
4503 case 534: /* Load Word Byte-Reverse Indexed */
4504 case 532: /* Load Doubleword Byte-Reverse Indexed */
4505 case 582: /* Load Word Atomic */
4506 case 614: /* Load Doubleword Atomic */
4507 case 265: /* Modulo Unsigned Doubleword */
4508 case 777: /* Modulo Signed Doubleword */
4509 case 267: /* Modulo Unsigned Word */
4510 case 779: /* Modulo Signed Word */
4511 record_full_arch_list_add_reg (regcache
,
4512 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4515 case 597: /* Load String Word Immediate */
4516 case 533: /* Load String Word Indexed */
4525 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4526 nr
= PPC_XER_NB (xer
);
4531 /* If n=0, the contents of register RT are undefined. */
4535 for (i
= 0; i
< nr
; i
++)
4536 record_full_arch_list_add_reg (regcache
,
4537 tdep
->ppc_gp0_regnum
4538 + ((PPC_RT (insn
) + i
) & 0x1f));
4541 case 276: /* Load Quadword And Reserve Indexed */
4542 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4543 record_full_arch_list_add_reg (regcache
, tmp
);
4544 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4547 /* These write VRT. */
4548 case 6: /* Load Vector for Shift Left Indexed */
4549 case 38: /* Load Vector for Shift Right Indexed */
4550 case 7: /* Load Vector Element Byte Indexed */
4551 case 39: /* Load Vector Element Halfword Indexed */
4552 case 71: /* Load Vector Element Word Indexed */
4553 case 103: /* Load Vector Indexed */
4554 case 359: /* Load Vector Indexed LRU */
4555 record_full_arch_list_add_reg (regcache
,
4556 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4559 /* These write FRT. Update RA if 'update indexed.' */
4560 case 567: /* Load Floating-Point Single with Update Indexed */
4561 case 631: /* Load Floating-Point Double with Update Indexed */
4562 record_full_arch_list_add_reg (regcache
,
4563 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4565 case 535: /* Load Floating-Point Single Indexed */
4566 case 599: /* Load Floating-Point Double Indexed */
4567 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4568 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4569 record_full_arch_list_add_reg (regcache
,
4570 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4573 case 791: /* Load Floating-Point Double Pair Indexed */
4574 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4575 record_full_arch_list_add_reg (regcache
, tmp
);
4576 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4579 case 179: /* Move To VSR Doubleword */
4580 case 211: /* Move To VSR Word Algebraic */
4581 case 243: /* Move To VSR Word and Zero */
4582 case 588: /* Load VSX Scalar Doubleword Indexed */
4583 case 524: /* Load VSX Scalar Single-Precision Indexed */
4584 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4585 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4586 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4587 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4588 case 780: /* Load VSX Vector Word*4 Indexed */
4589 case 268: /* Load VSX Vector Indexed */
4590 case 364: /* Load VSX Vector Word & Splat Indexed */
4591 case 812: /* Load VSX Vector Halfword*8 Indexed */
4592 case 876: /* Load VSX Vector Byte*16 Indexed */
4593 case 269: /* Load VSX Vector with Length */
4594 case 301: /* Load VSX Vector Left-justified with Length */
4595 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4596 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4597 case 403: /* Move To VSR Word & Splat */
4598 case 435: /* Move To VSR Double Doubleword */
4599 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4602 /* These write RA. Update CR if RC is set. */
4603 case 24: /* Shift Left Word */
4604 case 26: /* Count Leading Zeros Word */
4605 case 27: /* Shift Left Doubleword */
4607 case 58: /* Count Leading Zeros Doubleword */
4608 case 60: /* AND with Complement */
4610 case 284: /* Equivalent */
4612 case 476: /* NAND */
4613 case 412: /* OR with Complement */
4615 case 536: /* Shift Right Word */
4616 case 539: /* Shift Right Doubleword */
4617 case 922: /* Extend Sign Halfword */
4618 case 954: /* Extend Sign Byte */
4619 case 986: /* Extend Sign Word */
4620 case 538: /* Count Trailing Zeros Word */
4621 case 570: /* Count Trailing Zeros Doubleword */
4622 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4623 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4625 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4626 record_full_arch_list_add_reg (regcache
,
4627 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4631 case 181: /* Store Doubleword with Update Indexed */
4632 case 183: /* Store Word with Update Indexed */
4633 case 247: /* Store Byte with Update Indexed */
4634 case 439: /* Store Half Word with Update Indexed */
4635 case 695: /* Store Floating-Point Single with Update Indexed */
4636 case 759: /* Store Floating-Point Double with Update Indexed */
4637 record_full_arch_list_add_reg (regcache
,
4638 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4640 case 135: /* Store Vector Element Byte Indexed */
4641 case 167: /* Store Vector Element Halfword Indexed */
4642 case 199: /* Store Vector Element Word Indexed */
4643 case 231: /* Store Vector Indexed */
4644 case 487: /* Store Vector Indexed LRU */
4645 case 716: /* Store VSX Scalar Doubleword Indexed */
4646 case 140: /* Store VSX Scalar as Integer Word Indexed */
4647 case 652: /* Store VSX Scalar Single-Precision Indexed */
4648 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4649 case 908: /* Store VSX Vector Word*4 Indexed */
4650 case 149: /* Store Doubleword Indexed */
4651 case 151: /* Store Word Indexed */
4652 case 215: /* Store Byte Indexed */
4653 case 407: /* Store Half Word Indexed */
4654 case 694: /* Store Byte Conditional Indexed */
4655 case 726: /* Store Halfword Conditional Indexed */
4656 case 150: /* Store Word Conditional Indexed */
4657 case 214: /* Store Doubleword Conditional Indexed */
4658 case 182: /* Store Quadword Conditional Indexed */
4659 case 662: /* Store Word Byte-Reverse Indexed */
4660 case 918: /* Store Halfword Byte-Reverse Indexed */
4661 case 660: /* Store Doubleword Byte-Reverse Indexed */
4662 case 663: /* Store Floating-Point Single Indexed */
4663 case 727: /* Store Floating-Point Double Indexed */
4664 case 919: /* Store Floating-Point Double Pair Indexed */
4665 case 983: /* Store Floating-Point as Integer Word Indexed */
4666 case 396: /* Store VSX Vector Indexed */
4667 case 940: /* Store VSX Vector Halfword*8 Indexed */
4668 case 1004: /* Store VSX Vector Byte*16 Indexed */
4669 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4670 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4671 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4672 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4675 if (PPC_RA (insn
) != 0)
4676 regcache_raw_read_unsigned (regcache
,
4677 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4678 regcache_raw_read_unsigned (regcache
,
4679 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4684 case 183: /* Store Word with Update Indexed */
4685 case 199: /* Store Vector Element Word Indexed */
4686 case 140: /* Store VSX Scalar as Integer Word Indexed */
4687 case 652: /* Store VSX Scalar Single-Precision Indexed */
4688 case 151: /* Store Word Indexed */
4689 case 150: /* Store Word Conditional Indexed */
4690 case 662: /* Store Word Byte-Reverse Indexed */
4691 case 663: /* Store Floating-Point Single Indexed */
4692 case 695: /* Store Floating-Point Single with Update Indexed */
4693 case 983: /* Store Floating-Point as Integer Word Indexed */
4696 case 247: /* Store Byte with Update Indexed */
4697 case 135: /* Store Vector Element Byte Indexed */
4698 case 215: /* Store Byte Indexed */
4699 case 694: /* Store Byte Conditional Indexed */
4700 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4703 case 439: /* Store Halfword with Update Indexed */
4704 case 167: /* Store Vector Element Halfword Indexed */
4705 case 407: /* Store Halfword Indexed */
4706 case 726: /* Store Halfword Conditional Indexed */
4707 case 918: /* Store Halfword Byte-Reverse Indexed */
4708 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4711 case 181: /* Store Doubleword with Update Indexed */
4712 case 716: /* Store VSX Scalar Doubleword Indexed */
4713 case 149: /* Store Doubleword Indexed */
4714 case 214: /* Store Doubleword Conditional Indexed */
4715 case 660: /* Store Doubleword Byte-Reverse Indexed */
4716 case 727: /* Store Floating-Point Double Indexed */
4717 case 759: /* Store Floating-Point Double with Update Indexed */
4720 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4721 case 908: /* Store VSX Vector Word*4 Indexed */
4722 case 182: /* Store Quadword Conditional Indexed */
4723 case 231: /* Store Vector Indexed */
4724 case 487: /* Store Vector Indexed LRU */
4725 case 919: /* Store Floating-Point Double Pair Indexed */
4726 case 396: /* Store VSX Vector Indexed */
4727 case 940: /* Store VSX Vector Halfword*8 Indexed */
4728 case 1004: /* Store VSX Vector Byte*16 Indexed */
4735 /* Align address for Store Vector instructions. */
4738 case 167: /* Store Vector Element Halfword Indexed */
4739 addr
= addr
& ~0x1ULL
;
4742 case 199: /* Store Vector Element Word Indexed */
4743 addr
= addr
& ~0x3ULL
;
4746 case 231: /* Store Vector Indexed */
4747 case 487: /* Store Vector Indexed LRU */
4748 addr
= addr
& ~0xfULL
;
4752 record_full_arch_list_add_mem (addr
, size
);
4755 case 397: /* Store VSX Vector with Length */
4756 case 429: /* Store VSX Vector Left-justified with Length */
4758 if (PPC_RA (insn
) != 0)
4759 regcache_raw_read_unsigned (regcache
,
4760 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4762 regcache_raw_read_unsigned (regcache
,
4763 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4764 /* Store up to 16 bytes. */
4765 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4767 record_full_arch_list_add_mem (ea
, nb
);
4770 case 710: /* Store Word Atomic */
4771 case 742: /* Store Doubleword Atomic */
4773 if (PPC_RA (insn
) != 0)
4774 regcache_raw_read_unsigned (regcache
,
4775 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4779 case 710: /* Store Word Atomic */
4782 case 742: /* Store Doubleword Atomic */
4788 record_full_arch_list_add_mem (ea
, size
);
4791 case 725: /* Store String Word Immediate */
4793 if (PPC_RA (insn
) != 0)
4794 regcache_raw_read_unsigned (regcache
,
4795 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4802 record_full_arch_list_add_mem (ea
, nb
);
4806 case 661: /* Store String Word Indexed */
4808 if (PPC_RA (insn
) != 0)
4809 regcache_raw_read_unsigned (regcache
,
4810 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4813 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4814 nb
= PPC_XER_NB (xer
);
4818 regcache_raw_read_unsigned (regcache
,
4819 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4822 record_full_arch_list_add_mem (ea
, nb
);
4827 case 467: /* Move To Special Purpose Register */
4828 switch (PPC_SPR (insn
))
4831 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4834 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4837 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4839 case 256: /* VRSAVE */
4840 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4846 case 147: /* Move To Split Little Endian */
4847 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4850 case 512: /* Move to Condition Register from XER */
4851 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4852 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4855 case 4: /* Trap Word */
4856 case 68: /* Trap Doubleword */
4857 case 430: /* Clear BHRB */
4858 case 598: /* Synchronize */
4859 case 62: /* Wait for Interrupt */
4861 case 22: /* Instruction Cache Block Touch */
4862 case 854: /* Enforce In-order Execution of I/O */
4863 case 246: /* Data Cache Block Touch for Store */
4864 case 54: /* Data Cache Block Store */
4865 case 86: /* Data Cache Block Flush */
4866 case 278: /* Data Cache Block Touch */
4867 case 758: /* Data Cache Block Allocate */
4868 case 982: /* Instruction Cache Block Invalidate */
4869 case 774: /* Copy */
4870 case 838: /* CP_Abort */
4873 case 654: /* Transaction Begin */
4874 case 686: /* Transaction End */
4875 case 750: /* Transaction Suspend or Resume */
4876 case 782: /* Transaction Abort Word Conditional */
4877 case 814: /* Transaction Abort Doubleword Conditional */
4878 case 846: /* Transaction Abort Word Conditional Immediate */
4879 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4880 case 910: /* Transaction Abort */
4881 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4883 case 718: /* Transaction Check */
4884 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4887 case 1014: /* Data Cache Block set to Zero */
4888 if (target_auxv_search (target_stack
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4890 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4893 if (PPC_RA (insn
) != 0)
4894 regcache_raw_read_unsigned (regcache
,
4895 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4896 regcache_raw_read_unsigned (regcache
,
4897 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4898 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4899 record_full_arch_list_add_mem (ea
, at_dcsz
);
4904 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4905 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4909 /* Parse and record instructions of primary opcode-59 at ADDR.
4910 Return 0 if successful. */
4913 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4914 CORE_ADDR addr
, uint32_t insn
)
4916 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4917 int ext
= PPC_EXTOP (insn
);
4921 case 18: /* Floating Divide */
4922 case 20: /* Floating Subtract */
4923 case 21: /* Floating Add */
4924 case 22: /* Floating Square Root */
4925 case 24: /* Floating Reciprocal Estimate */
4926 case 25: /* Floating Multiply */
4927 case 26: /* Floating Reciprocal Square Root Estimate */
4928 case 28: /* Floating Multiply-Subtract */
4929 case 29: /* Floating Multiply-Add */
4930 case 30: /* Floating Negative Multiply-Subtract */
4931 case 31: /* Floating Negative Multiply-Add */
4932 record_full_arch_list_add_reg (regcache
,
4933 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4935 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4936 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4943 case 2: /* DFP Add */
4944 case 3: /* DFP Quantize */
4945 case 34: /* DFP Multiply */
4946 case 35: /* DFP Reround */
4947 case 67: /* DFP Quantize Immediate */
4948 case 99: /* DFP Round To FP Integer With Inexact */
4949 case 227: /* DFP Round To FP Integer Without Inexact */
4950 case 258: /* DFP Convert To DFP Long! */
4951 case 290: /* DFP Convert To Fixed */
4952 case 514: /* DFP Subtract */
4953 case 546: /* DFP Divide */
4954 case 770: /* DFP Round To DFP Short! */
4955 case 802: /* DFP Convert From Fixed */
4956 case 834: /* DFP Encode BCD To DPD */
4958 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4959 record_full_arch_list_add_reg (regcache
,
4960 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4961 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4964 case 130: /* DFP Compare Ordered */
4965 case 162: /* DFP Test Exponent */
4966 case 194: /* DFP Test Data Class */
4967 case 226: /* DFP Test Data Group */
4968 case 642: /* DFP Compare Unordered */
4969 case 674: /* DFP Test Significance */
4970 case 675: /* DFP Test Significance Immediate */
4971 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4972 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4975 case 66: /* DFP Shift Significand Left Immediate */
4976 case 98: /* DFP Shift Significand Right Immediate */
4977 case 322: /* DFP Decode DPD To BCD */
4978 case 354: /* DFP Extract Biased Exponent */
4979 case 866: /* DFP Insert Biased Exponent */
4980 record_full_arch_list_add_reg (regcache
,
4981 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4983 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4986 case 846: /* Floating Convert From Integer Doubleword Single */
4987 case 974: /* Floating Convert From Integer Doubleword Unsigned
4989 record_full_arch_list_add_reg (regcache
,
4990 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4992 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4993 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4998 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4999 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5003 /* Parse and record instructions of primary opcode-60 at ADDR.
5004 Return 0 if successful. */
5007 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5008 CORE_ADDR addr
, uint32_t insn
)
5010 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5011 int ext
= PPC_EXTOP (insn
);
5015 case 0: /* VSX Scalar Add Single-Precision */
5016 case 32: /* VSX Scalar Add Double-Precision */
5017 case 24: /* VSX Scalar Divide Single-Precision */
5018 case 56: /* VSX Scalar Divide Double-Precision */
5019 case 176: /* VSX Scalar Copy Sign Double-Precision */
5020 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5021 case 41: /* ditto */
5022 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5024 case 160: /* VSX Scalar Maximum Double-Precision */
5025 case 168: /* VSX Scalar Minimum Double-Precision */
5026 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5027 case 57: /* ditto */
5028 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5029 case 25: /* ditto */
5030 case 48: /* VSX Scalar Multiply Double-Precision */
5031 case 16: /* VSX Scalar Multiply Single-Precision */
5032 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5033 case 169: /* ditto */
5034 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5035 case 137: /* ditto */
5036 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5037 case 185: /* ditto */
5038 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5039 case 153: /* ditto */
5040 case 40: /* VSX Scalar Subtract Double-Precision */
5041 case 8: /* VSX Scalar Subtract Single-Precision */
5042 case 96: /* VSX Vector Add Double-Precision */
5043 case 64: /* VSX Vector Add Single-Precision */
5044 case 120: /* VSX Vector Divide Double-Precision */
5045 case 88: /* VSX Vector Divide Single-Precision */
5046 case 97: /* VSX Vector Multiply-Add Double-Precision */
5047 case 105: /* ditto */
5048 case 65: /* VSX Vector Multiply-Add Single-Precision */
5049 case 73: /* ditto */
5050 case 224: /* VSX Vector Maximum Double-Precision */
5051 case 192: /* VSX Vector Maximum Single-Precision */
5052 case 232: /* VSX Vector Minimum Double-Precision */
5053 case 200: /* VSX Vector Minimum Single-Precision */
5054 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5055 case 121: /* ditto */
5056 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5057 case 89: /* ditto */
5058 case 112: /* VSX Vector Multiply Double-Precision */
5059 case 80: /* VSX Vector Multiply Single-Precision */
5060 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5061 case 233: /* ditto */
5062 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5063 case 201: /* ditto */
5064 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5065 case 249: /* ditto */
5066 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5067 case 217: /* ditto */
5068 case 104: /* VSX Vector Subtract Double-Precision */
5069 case 72: /* VSX Vector Subtract Single-Precision */
5070 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5071 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5072 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5073 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5074 case 3: /* VSX Scalar Compare Equal Double-Precision */
5075 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5076 case 19: /* VSX Scalar Compare Greater Than or Equal
5078 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5080 case 240: /* VSX Vector Copy Sign Double-Precision */
5081 case 208: /* VSX Vector Copy Sign Single-Precision */
5082 case 130: /* VSX Logical AND */
5083 case 138: /* VSX Logical AND with Complement */
5084 case 186: /* VSX Logical Equivalence */
5085 case 178: /* VSX Logical NAND */
5086 case 170: /* VSX Logical OR with Complement */
5087 case 162: /* VSX Logical NOR */
5088 case 146: /* VSX Logical OR */
5089 case 154: /* VSX Logical XOR */
5090 case 18: /* VSX Merge High Word */
5091 case 50: /* VSX Merge Low Word */
5092 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5093 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5094 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5095 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5096 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5097 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5098 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5099 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5100 case 216: /* VSX Vector Insert Exponent Single-Precision */
5101 case 248: /* VSX Vector Insert Exponent Double-Precision */
5102 case 26: /* VSX Vector Permute */
5103 case 58: /* VSX Vector Permute Right-indexed */
5104 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5105 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5106 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5107 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5108 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5111 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5112 case 125: /* VSX Vector Test for software Divide Double-Precision */
5113 case 93: /* VSX Vector Test for software Divide Single-Precision */
5114 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5117 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5118 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5119 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5120 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5121 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5125 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5127 case 99: /* VSX Vector Compare Equal To Double-Precision */
5128 case 67: /* VSX Vector Compare Equal To Single-Precision */
5129 case 115: /* VSX Vector Compare Greater Than or
5130 Equal To Double-Precision */
5131 case 83: /* VSX Vector Compare Greater Than or
5132 Equal To Single-Precision */
5133 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5134 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5136 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5137 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5138 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5144 case 265: /* VSX Scalar round Double-Precision to
5145 Single-Precision and Convert to
5146 Single-Precision format */
5147 case 344: /* VSX Scalar truncate Double-Precision to
5148 Integer and Convert to Signed Integer
5149 Doubleword format with Saturate */
5150 case 88: /* VSX Scalar truncate Double-Precision to
5151 Integer and Convert to Signed Integer Word
5152 Format with Saturate */
5153 case 328: /* VSX Scalar truncate Double-Precision integer
5154 and Convert to Unsigned Integer Doubleword
5155 Format with Saturate */
5156 case 72: /* VSX Scalar truncate Double-Precision to
5157 Integer and Convert to Unsigned Integer Word
5158 Format with Saturate */
5159 case 329: /* VSX Scalar Convert Single-Precision to
5160 Double-Precision format */
5161 case 376: /* VSX Scalar Convert Signed Integer
5162 Doubleword to floating-point format and
5163 Round to Double-Precision format */
5164 case 312: /* VSX Scalar Convert Signed Integer
5165 Doubleword to floating-point format and
5166 round to Single-Precision */
5167 case 360: /* VSX Scalar Convert Unsigned Integer
5168 Doubleword to floating-point format and
5169 Round to Double-Precision format */
5170 case 296: /* VSX Scalar Convert Unsigned Integer
5171 Doubleword to floating-point format and
5172 Round to Single-Precision */
5173 case 73: /* VSX Scalar Round to Double-Precision Integer
5174 Using Round to Nearest Away */
5175 case 107: /* VSX Scalar Round to Double-Precision Integer
5176 Exact using Current rounding mode */
5177 case 121: /* VSX Scalar Round to Double-Precision Integer
5178 Using Round toward -Infinity */
5179 case 105: /* VSX Scalar Round to Double-Precision Integer
5180 Using Round toward +Infinity */
5181 case 89: /* VSX Scalar Round to Double-Precision Integer
5182 Using Round toward Zero */
5183 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5184 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5185 case 281: /* VSX Scalar Round to Single-Precision */
5186 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5188 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5190 case 75: /* VSX Scalar Square Root Double-Precision */
5191 case 11: /* VSX Scalar Square Root Single-Precision */
5192 case 393: /* VSX Vector round Double-Precision to
5193 Single-Precision and Convert to
5194 Single-Precision format */
5195 case 472: /* VSX Vector truncate Double-Precision to
5196 Integer and Convert to Signed Integer
5197 Doubleword format with Saturate */
5198 case 216: /* VSX Vector truncate Double-Precision to
5199 Integer and Convert to Signed Integer Word
5200 Format with Saturate */
5201 case 456: /* VSX Vector truncate Double-Precision to
5202 Integer and Convert to Unsigned Integer
5203 Doubleword format with Saturate */
5204 case 200: /* VSX Vector truncate Double-Precision to
5205 Integer and Convert to Unsigned Integer Word
5206 Format with Saturate */
5207 case 457: /* VSX Vector Convert Single-Precision to
5208 Double-Precision format */
5209 case 408: /* VSX Vector truncate Single-Precision to
5210 Integer and Convert to Signed Integer
5211 Doubleword format with Saturate */
5212 case 152: /* VSX Vector truncate Single-Precision to
5213 Integer and Convert to Signed Integer Word
5214 Format with Saturate */
5215 case 392: /* VSX Vector truncate Single-Precision to
5216 Integer and Convert to Unsigned Integer
5217 Doubleword format with Saturate */
5218 case 136: /* VSX Vector truncate Single-Precision to
5219 Integer and Convert to Unsigned Integer Word
5220 Format with Saturate */
5221 case 504: /* VSX Vector Convert and round Signed Integer
5222 Doubleword to Double-Precision format */
5223 case 440: /* VSX Vector Convert and round Signed Integer
5224 Doubleword to Single-Precision format */
5225 case 248: /* VSX Vector Convert Signed Integer Word to
5226 Double-Precision format */
5227 case 184: /* VSX Vector Convert and round Signed Integer
5228 Word to Single-Precision format */
5229 case 488: /* VSX Vector Convert and round Unsigned
5230 Integer Doubleword to Double-Precision format */
5231 case 424: /* VSX Vector Convert and round Unsigned
5232 Integer Doubleword to Single-Precision format */
5233 case 232: /* VSX Vector Convert and round Unsigned
5234 Integer Word to Double-Precision format */
5235 case 168: /* VSX Vector Convert and round Unsigned
5236 Integer Word to Single-Precision format */
5237 case 201: /* VSX Vector Round to Double-Precision
5238 Integer using round to Nearest Away */
5239 case 235: /* VSX Vector Round to Double-Precision
5240 Integer Exact using Current rounding mode */
5241 case 249: /* VSX Vector Round to Double-Precision
5242 Integer using round toward -Infinity */
5243 case 233: /* VSX Vector Round to Double-Precision
5244 Integer using round toward +Infinity */
5245 case 217: /* VSX Vector Round to Double-Precision
5246 Integer using round toward Zero */
5247 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5248 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5249 case 137: /* VSX Vector Round to Single-Precision Integer
5250 Using Round to Nearest Away */
5251 case 171: /* VSX Vector Round to Single-Precision Integer
5252 Exact Using Current rounding mode */
5253 case 185: /* VSX Vector Round to Single-Precision Integer
5254 Using Round toward -Infinity */
5255 case 169: /* VSX Vector Round to Single-Precision Integer
5256 Using Round toward +Infinity */
5257 case 153: /* VSX Vector Round to Single-Precision Integer
5258 Using round toward Zero */
5259 case 202: /* VSX Vector Reciprocal Square Root Estimate
5261 case 138: /* VSX Vector Reciprocal Square Root Estimate
5263 case 203: /* VSX Vector Square Root Double-Precision */
5264 case 139: /* VSX Vector Square Root Single-Precision */
5265 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5267 case 345: /* VSX Scalar Absolute Value Double-Precision */
5268 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5269 Vector Single-Precision format Non-signalling */
5270 case 331: /* VSX Scalar Convert Single-Precision to
5271 Double-Precision format Non-signalling */
5272 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5273 case 377: /* VSX Scalar Negate Double-Precision */
5274 case 473: /* VSX Vector Absolute Value Double-Precision */
5275 case 409: /* VSX Vector Absolute Value Single-Precision */
5276 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5277 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5278 case 505: /* VSX Vector Negate Double-Precision */
5279 case 441: /* VSX Vector Negate Single-Precision */
5280 case 164: /* VSX Splat Word */
5281 case 165: /* VSX Vector Extract Unsigned Word */
5282 case 181: /* VSX Vector Insert Word */
5283 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5286 case 298: /* VSX Scalar Test Data Class Single-Precision */
5287 case 362: /* VSX Scalar Test Data Class Double-Precision */
5288 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5290 case 106: /* VSX Scalar Test for software Square Root
5292 case 234: /* VSX Vector Test for software Square Root
5294 case 170: /* VSX Vector Test for software Square Root
5296 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5300 switch (PPC_FIELD (insn
, 11, 5))
5302 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5303 case 1: /* VSX Scalar Extract Significand Double-Precision */
5304 record_full_arch_list_add_reg (regcache
,
5305 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5307 case 16: /* VSX Scalar Convert Half-Precision format to
5308 Double-Precision format */
5309 case 17: /* VSX Scalar round & Convert Double-Precision format
5310 to Half-Precision format */
5311 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5312 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5318 switch (PPC_FIELD (insn
, 11, 5))
5320 case 24: /* VSX Vector Convert Half-Precision format to
5321 Single-Precision format */
5322 case 25: /* VSX Vector round and Convert Single-Precision format
5323 to Half-Precision format */
5324 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5326 case 0: /* VSX Vector Extract Exponent Double-Precision */
5327 case 1: /* VSX Vector Extract Significand Double-Precision */
5328 case 7: /* VSX Vector Byte-Reverse Halfword */
5329 case 8: /* VSX Vector Extract Exponent Single-Precision */
5330 case 9: /* VSX Vector Extract Significand Single-Precision */
5331 case 15: /* VSX Vector Byte-Reverse Word */
5332 case 23: /* VSX Vector Byte-Reverse Doubleword */
5333 case 31: /* VSX Vector Byte-Reverse Quadword */
5334 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5342 case 360: /* VSX Vector Splat Immediate Byte */
5343 if (PPC_FIELD (insn
, 11, 2) == 0)
5345 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5349 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5350 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5354 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5356 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5360 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5361 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5365 /* Parse and record instructions of primary opcode-61 at ADDR.
5366 Return 0 if successful. */
5369 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5370 CORE_ADDR addr
, uint32_t insn
)
5372 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5378 case 0: /* Store Floating-Point Double Pair */
5379 case 2: /* Store VSX Scalar Doubleword */
5380 case 3: /* Store VSX Scalar Single */
5381 if (PPC_RA (insn
) != 0)
5382 regcache_raw_read_unsigned (regcache
,
5383 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5385 ea
+= PPC_DS (insn
) << 2;
5388 case 0: /* Store Floating-Point Double Pair */
5391 case 2: /* Store VSX Scalar Doubleword */
5394 case 3: /* Store VSX Scalar Single */
5400 record_full_arch_list_add_mem (ea
, size
);
5406 case 1: /* Load VSX Vector */
5407 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5409 case 5: /* Store VSX Vector */
5410 if (PPC_RA (insn
) != 0)
5411 regcache_raw_read_unsigned (regcache
,
5412 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5414 ea
+= PPC_DQ (insn
) << 4;
5415 record_full_arch_list_add_mem (ea
, 16);
5419 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5420 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5424 /* Parse and record instructions of primary opcode-63 at ADDR.
5425 Return 0 if successful. */
5428 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5429 CORE_ADDR addr
, uint32_t insn
)
5431 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5432 int ext
= PPC_EXTOP (insn
);
5437 case 18: /* Floating Divide */
5438 case 20: /* Floating Subtract */
5439 case 21: /* Floating Add */
5440 case 22: /* Floating Square Root */
5441 case 24: /* Floating Reciprocal Estimate */
5442 case 25: /* Floating Multiply */
5443 case 26: /* Floating Reciprocal Square Root Estimate */
5444 case 28: /* Floating Multiply-Subtract */
5445 case 29: /* Floating Multiply-Add */
5446 case 30: /* Floating Negative Multiply-Subtract */
5447 case 31: /* Floating Negative Multiply-Add */
5448 record_full_arch_list_add_reg (regcache
,
5449 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5451 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5452 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5455 case 23: /* Floating Select */
5456 record_full_arch_list_add_reg (regcache
,
5457 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5459 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5465 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5466 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5468 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5469 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5475 case 2: /* DFP Add Quad */
5476 case 3: /* DFP Quantize Quad */
5477 case 34: /* DFP Multiply Quad */
5478 case 35: /* DFP Reround Quad */
5479 case 67: /* DFP Quantize Immediate Quad */
5480 case 99: /* DFP Round To FP Integer With Inexact Quad */
5481 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5482 case 258: /* DFP Convert To DFP Extended Quad */
5483 case 514: /* DFP Subtract Quad */
5484 case 546: /* DFP Divide Quad */
5485 case 770: /* DFP Round To DFP Long Quad */
5486 case 802: /* DFP Convert From Fixed Quad */
5487 case 834: /* DFP Encode BCD To DPD Quad */
5489 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5490 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5491 record_full_arch_list_add_reg (regcache
, tmp
);
5492 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5493 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5496 case 130: /* DFP Compare Ordered Quad */
5497 case 162: /* DFP Test Exponent Quad */
5498 case 194: /* DFP Test Data Class Quad */
5499 case 226: /* DFP Test Data Group Quad */
5500 case 642: /* DFP Compare Unordered Quad */
5501 case 674: /* DFP Test Significance Quad */
5502 case 675: /* DFP Test Significance Immediate Quad */
5503 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5504 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5507 case 66: /* DFP Shift Significand Left Immediate Quad */
5508 case 98: /* DFP Shift Significand Right Immediate Quad */
5509 case 322: /* DFP Decode DPD To BCD Quad */
5510 case 866: /* DFP Insert Biased Exponent Quad */
5511 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5512 record_full_arch_list_add_reg (regcache
, tmp
);
5513 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5515 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5518 case 290: /* DFP Convert To Fixed Quad */
5519 record_full_arch_list_add_reg (regcache
,
5520 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5522 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5523 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5526 case 354: /* DFP Extract Biased Exponent Quad */
5527 record_full_arch_list_add_reg (regcache
,
5528 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5530 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5533 case 12: /* Floating Round to Single-Precision */
5534 case 14: /* Floating Convert To Integer Word */
5535 case 15: /* Floating Convert To Integer Word
5536 with round toward Zero */
5537 case 142: /* Floating Convert To Integer Word Unsigned */
5538 case 143: /* Floating Convert To Integer Word Unsigned
5539 with round toward Zero */
5540 case 392: /* Floating Round to Integer Nearest */
5541 case 424: /* Floating Round to Integer Toward Zero */
5542 case 456: /* Floating Round to Integer Plus */
5543 case 488: /* Floating Round to Integer Minus */
5544 case 814: /* Floating Convert To Integer Doubleword */
5545 case 815: /* Floating Convert To Integer Doubleword
5546 with round toward Zero */
5547 case 846: /* Floating Convert From Integer Doubleword */
5548 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5549 case 943: /* Floating Convert To Integer Doubleword Unsigned
5550 with round toward Zero */
5551 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5552 record_full_arch_list_add_reg (regcache
,
5553 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5555 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5556 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5560 switch (PPC_FIELD (insn
, 11, 5))
5562 case 1: /* Move From FPSCR & Clear Enables */
5563 case 20: /* Move From FPSCR Control & set DRN */
5564 case 21: /* Move From FPSCR Control & set DRN Immediate */
5565 case 22: /* Move From FPSCR Control & set RN */
5566 case 23: /* Move From FPSCR Control & set RN Immediate */
5567 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5568 case 0: /* Move From FPSCR */
5569 case 24: /* Move From FPSCR Lightweight */
5570 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5571 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5572 record_full_arch_list_add_reg (regcache
,
5573 tdep
->ppc_fp0_regnum
5579 case 8: /* Floating Copy Sign */
5580 case 40: /* Floating Negate */
5581 case 72: /* Floating Move Register */
5582 case 136: /* Floating Negative Absolute Value */
5583 case 264: /* Floating Absolute Value */
5584 record_full_arch_list_add_reg (regcache
,
5585 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5587 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5590 case 838: /* Floating Merge Odd Word */
5591 case 966: /* Floating Merge Even Word */
5592 record_full_arch_list_add_reg (regcache
,
5593 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5596 case 38: /* Move To FPSCR Bit 1 */
5597 case 70: /* Move To FPSCR Bit 0 */
5598 case 134: /* Move To FPSCR Field Immediate */
5599 case 711: /* Move To FPSCR Fields */
5601 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5602 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5605 case 0: /* Floating Compare Unordered */
5606 case 32: /* Floating Compare Ordered */
5607 case 64: /* Move to Condition Register from FPSCR */
5608 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5609 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5610 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5611 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5612 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5614 case 128: /* Floating Test for software Divide */
5615 case 160: /* Floating Test for software Square Root */
5616 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5619 case 4: /* VSX Scalar Add Quad-Precision */
5620 case 36: /* VSX Scalar Multiply Quad-Precision */
5621 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5622 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5623 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5624 case 484: /* VSX Scalar Negative Multiply-Subtract
5626 case 516: /* VSX Scalar Subtract Quad-Precision */
5627 case 548: /* VSX Scalar Divide Quad-Precision */
5628 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5630 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5631 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5632 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5636 switch (PPC_FIELD (insn
, 11, 5))
5638 case 27: /* VSX Scalar Square Root Quad-Precision */
5639 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5641 case 0: /* VSX Scalar Absolute Quad-Precision */
5642 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5643 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5644 case 16: /* VSX Scalar Negate Quad-Precision */
5645 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5646 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5652 switch (PPC_FIELD (insn
, 11, 5))
5654 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5655 to Unsigned Word format */
5656 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5657 Quad-Precision format */
5658 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5659 to Signed Word format */
5660 case 10: /* VSX Scalar Convert Signed Doubleword format to
5661 Quad-Precision format */
5662 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5663 to Unsigned Doubleword format */
5664 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5665 Double-Precision format */
5666 case 22: /* VSX Scalar Convert Double-Precision format to
5667 Quad-Precision format */
5668 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5669 to Signed Doubleword format */
5670 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5671 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5676 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5677 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5681 /* Parse the current instruction and record the values of the registers and
5682 memory that will be changed in current instruction to "record_arch_list".
5683 Return -1 if something wrong. */
5686 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5689 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5690 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5694 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5695 op6
= PPC_OP6 (insn
);
5699 case 2: /* Trap Doubleword Immediate */
5700 case 3: /* Trap Word Immediate */
5705 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5709 case 17: /* System call */
5710 if (PPC_LEV (insn
) != 0)
5713 if (tdep
->ppc_syscall_record
!= NULL
)
5715 if (tdep
->ppc_syscall_record (regcache
) != 0)
5720 printf_unfiltered (_("no syscall record support\n"));
5725 case 7: /* Multiply Low Immediate */
5726 record_full_arch_list_add_reg (regcache
,
5727 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5730 case 8: /* Subtract From Immediate Carrying */
5731 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5732 record_full_arch_list_add_reg (regcache
,
5733 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5736 case 10: /* Compare Logical Immediate */
5737 case 11: /* Compare Immediate */
5738 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5741 case 13: /* Add Immediate Carrying and Record */
5742 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5744 case 12: /* Add Immediate Carrying */
5745 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5747 case 14: /* Add Immediate */
5748 case 15: /* Add Immediate Shifted */
5749 record_full_arch_list_add_reg (regcache
,
5750 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5753 case 16: /* Branch Conditional */
5754 if ((PPC_BO (insn
) & 0x4) == 0)
5755 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5757 case 18: /* Branch */
5759 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5763 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5767 case 20: /* Rotate Left Word Immediate then Mask Insert */
5768 case 21: /* Rotate Left Word Immediate then AND with Mask */
5769 case 23: /* Rotate Left Word then AND with Mask */
5770 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5771 /* Rotate Left Doubleword Immediate then Clear Right */
5772 /* Rotate Left Doubleword Immediate then Clear */
5773 /* Rotate Left Doubleword then Clear Left */
5774 /* Rotate Left Doubleword then Clear Right */
5775 /* Rotate Left Doubleword Immediate then Mask Insert */
5777 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5778 record_full_arch_list_add_reg (regcache
,
5779 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5782 case 28: /* AND Immediate */
5783 case 29: /* AND Immediate Shifted */
5784 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5786 case 24: /* OR Immediate */
5787 case 25: /* OR Immediate Shifted */
5788 case 26: /* XOR Immediate */
5789 case 27: /* XOR Immediate Shifted */
5790 record_full_arch_list_add_reg (regcache
,
5791 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5795 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5799 case 33: /* Load Word and Zero with Update */
5800 case 35: /* Load Byte and Zero with Update */
5801 case 41: /* Load Halfword and Zero with Update */
5802 case 43: /* Load Halfword Algebraic with Update */
5803 record_full_arch_list_add_reg (regcache
,
5804 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5806 case 32: /* Load Word and Zero */
5807 case 34: /* Load Byte and Zero */
5808 case 40: /* Load Halfword and Zero */
5809 case 42: /* Load Halfword Algebraic */
5810 record_full_arch_list_add_reg (regcache
,
5811 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5814 case 46: /* Load Multiple Word */
5815 for (i
= PPC_RT (insn
); i
< 32; i
++)
5816 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5819 case 56: /* Load Quadword */
5820 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5821 record_full_arch_list_add_reg (regcache
, tmp
);
5822 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5825 case 49: /* Load Floating-Point Single with Update */
5826 case 51: /* Load Floating-Point Double with Update */
5827 record_full_arch_list_add_reg (regcache
,
5828 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5830 case 48: /* Load Floating-Point Single */
5831 case 50: /* Load Floating-Point Double */
5832 record_full_arch_list_add_reg (regcache
,
5833 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5836 case 47: /* Store Multiple Word */
5840 if (PPC_RA (insn
) != 0)
5841 regcache_raw_read_unsigned (regcache
,
5842 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5845 addr
+= PPC_D (insn
);
5846 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5850 case 37: /* Store Word with Update */
5851 case 39: /* Store Byte with Update */
5852 case 45: /* Store Halfword with Update */
5853 case 53: /* Store Floating-Point Single with Update */
5854 case 55: /* Store Floating-Point Double with Update */
5855 record_full_arch_list_add_reg (regcache
,
5856 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5858 case 36: /* Store Word */
5859 case 38: /* Store Byte */
5860 case 44: /* Store Halfword */
5861 case 52: /* Store Floating-Point Single */
5862 case 54: /* Store Floating-Point Double */
5867 if (PPC_RA (insn
) != 0)
5868 regcache_raw_read_unsigned (regcache
,
5869 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5871 addr
+= PPC_D (insn
);
5873 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5875 else if (op6
== 54 || op6
== 55)
5877 else if (op6
== 44 || op6
== 45)
5879 else if (op6
== 38 || op6
== 39)
5884 record_full_arch_list_add_mem (addr
, size
);
5891 case 0: /* Load Floating-Point Double Pair */
5892 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5893 record_full_arch_list_add_reg (regcache
, tmp
);
5894 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5896 case 2: /* Load VSX Scalar Doubleword */
5897 case 3: /* Load VSX Scalar Single */
5898 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5905 case 58: /* Load Doubleword */
5906 /* Load Doubleword with Update */
5907 /* Load Word Algebraic */
5908 if (PPC_FIELD (insn
, 30, 2) > 2)
5911 record_full_arch_list_add_reg (regcache
,
5912 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5913 if (PPC_BIT (insn
, 31))
5914 record_full_arch_list_add_reg (regcache
,
5915 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5919 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5924 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5929 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5933 case 62: /* Store Doubleword */
5934 /* Store Doubleword with Update */
5935 /* Store Quadword with Update */
5939 int sub2
= PPC_FIELD (insn
, 30, 2);
5944 if (PPC_RA (insn
) != 0)
5945 regcache_raw_read_unsigned (regcache
,
5946 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5949 size
= (sub2
== 2) ? 16 : 8;
5951 addr
+= PPC_DS (insn
) << 2;
5952 record_full_arch_list_add_mem (addr
, size
);
5954 if (op6
== 62 && sub2
== 1)
5955 record_full_arch_list_add_reg (regcache
,
5956 tdep
->ppc_gp0_regnum
+
5963 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5969 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5970 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5974 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5976 if (record_full_arch_list_add_end ())
5981 /* Initialize the current architecture based on INFO. If possible, re-use an
5982 architecture from ARCHES, which is a list of architectures already created
5983 during this debugging session.
5985 Called e.g. at program startup, when reading a core file, and when reading
5988 static struct gdbarch
*
5989 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5991 struct gdbarch
*gdbarch
;
5992 struct gdbarch_tdep
*tdep
;
5993 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5994 enum bfd_architecture arch
;
5997 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5999 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
6000 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
6001 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
6002 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
6004 int tdesc_wordsize
= -1;
6005 const struct target_desc
*tdesc
= info
.target_desc
;
6006 struct tdesc_arch_data
*tdesc_data
= NULL
;
6007 int num_pseudoregs
= 0;
6010 /* INFO may refer to a binary that is not of the PowerPC architecture,
6011 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
6012 In this case, we must not attempt to infer properties of the (PowerPC
6013 side) of the target system from properties of that executable. Trust
6014 the target description instead. */
6016 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
6017 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
6020 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6021 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
6023 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6024 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
6026 /* Check word size. If INFO is from a binary file, infer it from
6027 that, else choose a likely default. */
6028 if (from_xcoff_exec
)
6030 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
6035 else if (from_elf_exec
)
6037 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6042 else if (tdesc_has_registers (tdesc
))
6046 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6047 wordsize
= (info
.bfd_arch_info
->bits_per_word
6048 / info
.bfd_arch_info
->bits_per_byte
);
6053 /* Get the architecture and machine from the BFD. */
6054 arch
= info
.bfd_arch_info
->arch
;
6055 mach
= info
.bfd_arch_info
->mach
;
6057 /* For e500 executables, the apuinfo section is of help here. Such
6058 section contains the identifier and revision number of each
6059 Application-specific Processing Unit that is present on the
6060 chip. The content of the section is determined by the assembler
6061 which looks at each instruction and determines which unit (and
6062 which version of it) can execute it. Grovel through the section
6063 looking for relevant e500 APUs. */
6065 if (bfd_uses_spe_extensions (info
.abfd
))
6067 arch
= info
.bfd_arch_info
->arch
;
6068 mach
= bfd_mach_ppc_e500
;
6069 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6070 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6073 /* Find a default target description which describes our register
6074 layout, if we do not already have one. */
6075 if (! tdesc_has_registers (tdesc
))
6077 const struct variant
*v
;
6079 /* Choose variant. */
6080 v
= find_variant_by_arch (arch
, mach
);
6087 gdb_assert (tdesc_has_registers (tdesc
));
6089 /* Check any target description for validity. */
6090 if (tdesc_has_registers (tdesc
))
6092 static const char *const gprs
[] = {
6093 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6094 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6095 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6096 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6098 const struct tdesc_feature
*feature
;
6100 static const char *const msr_names
[] = { "msr", "ps" };
6101 static const char *const cr_names
[] = { "cr", "cnd" };
6102 static const char *const ctr_names
[] = { "ctr", "cnt" };
6104 feature
= tdesc_find_feature (tdesc
,
6105 "org.gnu.gdb.power.core");
6106 if (feature
== NULL
)
6109 tdesc_data
= tdesc_data_alloc ();
6112 for (i
= 0; i
< ppc_num_gprs
; i
++)
6113 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
6114 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
6116 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
6118 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
6121 /* Allow alternate names for these registers, to accomodate GDB's
6123 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6124 PPC_MSR_REGNUM
, msr_names
);
6125 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6126 PPC_CR_REGNUM
, cr_names
);
6127 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6128 PPC_CTR_REGNUM
, ctr_names
);
6132 tdesc_data_cleanup (tdesc_data
);
6136 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
6139 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
6141 wordsize
= tdesc_wordsize
;
6143 feature
= tdesc_find_feature (tdesc
,
6144 "org.gnu.gdb.power.fpu");
6145 if (feature
!= NULL
)
6147 static const char *const fprs
[] = {
6148 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6149 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6150 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6151 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6154 for (i
= 0; i
< ppc_num_fprs
; i
++)
6155 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6156 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6157 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6158 PPC_FPSCR_REGNUM
, "fpscr");
6162 tdesc_data_cleanup (tdesc_data
);
6170 /* The DFP pseudo-registers will be available when there are floating
6172 have_dfp
= have_fpu
;
6174 feature
= tdesc_find_feature (tdesc
,
6175 "org.gnu.gdb.power.altivec");
6176 if (feature
!= NULL
)
6178 static const char *const vector_regs
[] = {
6179 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6180 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6181 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6182 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6186 for (i
= 0; i
< ppc_num_gprs
; i
++)
6187 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6190 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6191 PPC_VSCR_REGNUM
, "vscr");
6192 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6193 PPC_VRSAVE_REGNUM
, "vrsave");
6195 if (have_spe
|| !valid_p
)
6197 tdesc_data_cleanup (tdesc_data
);
6205 /* Check for POWER7 VSX registers support. */
6206 feature
= tdesc_find_feature (tdesc
,
6207 "org.gnu.gdb.power.vsx");
6209 if (feature
!= NULL
)
6211 static const char *const vsx_regs
[] = {
6212 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6213 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6214 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6215 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6216 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6222 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6223 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6224 PPC_VSR0_UPPER_REGNUM
+ i
,
6228 tdesc_data_cleanup (tdesc_data
);
6237 /* On machines supporting the SPE APU, the general-purpose registers
6238 are 64 bits long. There are SIMD vector instructions to treat them
6239 as pairs of floats, but the rest of the instruction set treats them
6240 as 32-bit registers, and only operates on their lower halves.
6242 In the GDB regcache, we treat their high and low halves as separate
6243 registers. The low halves we present as the general-purpose
6244 registers, and then we have pseudo-registers that stitch together
6245 the upper and lower halves and present them as pseudo-registers.
6247 Thus, the target description is expected to supply the upper
6248 halves separately. */
6250 feature
= tdesc_find_feature (tdesc
,
6251 "org.gnu.gdb.power.spe");
6252 if (feature
!= NULL
)
6254 static const char *const upper_spe
[] = {
6255 "ev0h", "ev1h", "ev2h", "ev3h",
6256 "ev4h", "ev5h", "ev6h", "ev7h",
6257 "ev8h", "ev9h", "ev10h", "ev11h",
6258 "ev12h", "ev13h", "ev14h", "ev15h",
6259 "ev16h", "ev17h", "ev18h", "ev19h",
6260 "ev20h", "ev21h", "ev22h", "ev23h",
6261 "ev24h", "ev25h", "ev26h", "ev27h",
6262 "ev28h", "ev29h", "ev30h", "ev31h"
6266 for (i
= 0; i
< ppc_num_gprs
; i
++)
6267 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6268 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6270 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6271 PPC_SPE_ACC_REGNUM
, "acc");
6272 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6273 PPC_SPE_FSCR_REGNUM
, "spefscr");
6275 if (have_mq
|| have_fpu
|| !valid_p
)
6277 tdesc_data_cleanup (tdesc_data
);
6286 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6287 complain for a 32-bit binary on a 64-bit target; we do not yet
6288 support that. For instance, the 32-bit ABI routines expect
6291 As long as there isn't an explicit target description, we'll
6292 choose one based on the BFD architecture and get a word size
6293 matching the binary (probably powerpc:common or
6294 powerpc:common64). So there is only trouble if a 64-bit target
6295 supplies a 64-bit description while debugging a 32-bit
6297 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6299 tdesc_data_cleanup (tdesc_data
);
6306 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6309 elf_abi
= POWERPC_ELF_V1
;
6312 elf_abi
= POWERPC_ELF_V2
;
6319 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6321 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6322 Tag_GNU_Power_ABI_FP
) & 3)
6325 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6328 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6335 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6337 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6338 Tag_GNU_Power_ABI_FP
) >> 2)
6341 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6344 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6351 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6353 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6354 Tag_GNU_Power_ABI_Vector
))
6357 vector_abi
= POWERPC_VEC_GENERIC
;
6360 vector_abi
= POWERPC_VEC_ALTIVEC
;
6363 vector_abi
= POWERPC_VEC_SPE
;
6371 /* At this point, the only supported ELF-based 64-bit little-endian
6372 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6373 default. All other supported ELF-based operating systems use the
6374 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6375 e.g. because we run a legacy binary, or have attached to a process
6376 and have not found any associated binary file, set the default
6377 according to this heuristic. */
6378 if (elf_abi
== POWERPC_ELF_AUTO
)
6380 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6381 elf_abi
= POWERPC_ELF_V2
;
6383 elf_abi
= POWERPC_ELF_V1
;
6386 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6388 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6391 soft_float
= !have_fpu
;
6393 /* If we have a hard float binary or setting but no floating point
6394 registers, downgrade to soft float anyway. We're still somewhat
6395 useful in this scenario. */
6396 if (!soft_float
&& !have_fpu
)
6399 /* Similarly for vector registers. */
6400 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6401 vector_abi
= POWERPC_VEC_GENERIC
;
6403 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6404 vector_abi
= POWERPC_VEC_GENERIC
;
6406 if (vector_abi
== POWERPC_VEC_AUTO
)
6409 vector_abi
= POWERPC_VEC_ALTIVEC
;
6411 vector_abi
= POWERPC_VEC_SPE
;
6413 vector_abi
= POWERPC_VEC_GENERIC
;
6416 /* Do not limit the vector ABI based on available hardware, since we
6417 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6419 /* Find a candidate among extant architectures. */
6420 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6422 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6424 /* Word size in the various PowerPC bfd_arch_info structs isn't
6425 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6426 separate word size check. */
6427 tdep
= gdbarch_tdep (arches
->gdbarch
);
6428 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6430 if (tdep
&& tdep
->soft_float
!= soft_float
)
6432 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6434 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6436 if (tdep
&& tdep
->wordsize
== wordsize
)
6438 if (tdesc_data
!= NULL
)
6439 tdesc_data_cleanup (tdesc_data
);
6440 return arches
->gdbarch
;
6444 /* None found, create a new architecture from INFO, whose bfd_arch_info
6445 validity depends on the source:
6446 - executable useless
6447 - rs6000_host_arch() good
6449 - "set arch" trust blindly
6450 - GDB startup useless but harmless */
6452 tdep
= XCNEW (struct gdbarch_tdep
);
6453 tdep
->wordsize
= wordsize
;
6454 tdep
->elf_abi
= elf_abi
;
6455 tdep
->soft_float
= soft_float
;
6456 tdep
->long_double_abi
= long_double_abi
;
6457 tdep
->vector_abi
= vector_abi
;
6459 gdbarch
= gdbarch_alloc (&info
, tdep
);
6461 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6462 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6463 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6464 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6465 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6466 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6467 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6468 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6470 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6471 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6472 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6473 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6474 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6475 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6476 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6477 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6479 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6480 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6481 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6482 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6484 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6485 GDB traditionally called it "ps", though, so let GDB add an
6487 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6490 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6492 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6494 /* Set lr_frame_offset. */
6496 tdep
->lr_frame_offset
= 16;
6498 tdep
->lr_frame_offset
= 4;
6500 if (have_spe
|| have_dfp
|| have_vsx
)
6502 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6503 set_gdbarch_pseudo_register_write (gdbarch
,
6504 rs6000_pseudo_register_write
);
6505 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6506 rs6000_ax_pseudo_register_collect
);
6509 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6511 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6513 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6516 num_pseudoregs
+= 32;
6518 num_pseudoregs
+= 16;
6520 /* Include both VSX and Extended FP registers. */
6521 num_pseudoregs
+= 96;
6523 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6525 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6526 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6527 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6528 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6529 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6530 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6531 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6532 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6533 set_gdbarch_char_signed (gdbarch
, 0);
6535 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6538 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6540 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6541 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6542 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6544 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6545 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6548 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6549 else if (wordsize
== 8)
6550 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6552 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6553 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6554 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6556 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6558 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6559 rs6000_breakpoint::kind_from_pc
);
6560 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6561 rs6000_breakpoint::bp_from_kind
);
6563 /* The value of symbols of type N_SO and N_FUN maybe null when
6565 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6567 /* Handles single stepping of atomic sequences. */
6568 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6570 /* Not sure on this. FIXMEmgo */
6571 set_gdbarch_frame_args_skip (gdbarch
, 8);
6573 /* Helpers for function argument information. */
6574 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6577 set_gdbarch_in_solib_return_trampoline
6578 (gdbarch
, rs6000_in_solib_return_trampoline
);
6579 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6581 /* Hook in the DWARF CFI frame unwinder. */
6582 dwarf2_append_unwinders (gdbarch
);
6583 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6585 /* Frame handling. */
6586 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6588 /* Setup displaced stepping. */
6589 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6590 ppc_displaced_step_copy_insn
);
6591 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6592 ppc_displaced_step_hw_singlestep
);
6593 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6594 set_gdbarch_displaced_step_location (gdbarch
,
6595 displaced_step_at_entry_point
);
6597 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6599 /* Hook in ABI-specific overrides, if they have been registered. */
6600 info
.target_desc
= tdesc
;
6601 info
.tdesc_data
= tdesc_data
;
6602 gdbarch_init_osabi (info
, gdbarch
);
6606 case GDB_OSABI_LINUX
:
6607 case GDB_OSABI_NETBSD
:
6608 case GDB_OSABI_UNKNOWN
:
6609 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6610 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6611 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6612 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6613 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6616 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6618 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6619 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6620 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6621 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6622 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6625 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6626 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6627 rs6000_pseudo_register_reggroup_p
);
6628 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6630 /* Override the normal target description method to make the SPE upper
6631 halves anonymous. */
6632 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6634 /* Choose register numbers for all supported pseudo-registers. */
6635 tdep
->ppc_ev0_regnum
= -1;
6636 tdep
->ppc_dl0_regnum
= -1;
6637 tdep
->ppc_vsr0_regnum
= -1;
6638 tdep
->ppc_efpr0_regnum
= -1;
6640 cur_reg
= gdbarch_num_regs (gdbarch
);
6644 tdep
->ppc_ev0_regnum
= cur_reg
;
6649 tdep
->ppc_dl0_regnum
= cur_reg
;
6654 tdep
->ppc_vsr0_regnum
= cur_reg
;
6656 tdep
->ppc_efpr0_regnum
= cur_reg
;
6660 gdb_assert (gdbarch_num_regs (gdbarch
)
6661 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6663 /* Register the ravenscar_arch_ops. */
6664 if (mach
== bfd_mach_ppc_e500
)
6665 register_e500_ravenscar_ops (gdbarch
);
6667 register_ppc_ravenscar_ops (gdbarch
);
6669 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
6670 set_gdbarch_valid_disassembler_options (gdbarch
,
6671 disassembler_options_powerpc ());
6677 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6679 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6684 /* FIXME: Dump gdbarch_tdep. */
6687 /* PowerPC-specific commands. */
6690 set_powerpc_command (const char *args
, int from_tty
)
6692 printf_unfiltered (_("\
6693 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6694 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6698 show_powerpc_command (const char *args
, int from_tty
)
6700 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6704 powerpc_set_soft_float (const char *args
, int from_tty
,
6705 struct cmd_list_element
*c
)
6707 struct gdbarch_info info
;
6709 /* Update the architecture. */
6710 gdbarch_info_init (&info
);
6711 if (!gdbarch_update_p (info
))
6712 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6716 powerpc_set_vector_abi (const char *args
, int from_tty
,
6717 struct cmd_list_element
*c
)
6719 struct gdbarch_info info
;
6722 for (vector_abi
= POWERPC_VEC_AUTO
;
6723 vector_abi
!= POWERPC_VEC_LAST
;
6725 if (strcmp (powerpc_vector_abi_string
,
6726 powerpc_vector_strings
[vector_abi
]) == 0)
6728 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6732 if (vector_abi
== POWERPC_VEC_LAST
)
6733 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6734 powerpc_vector_abi_string
);
6736 /* Update the architecture. */
6737 gdbarch_info_init (&info
);
6738 if (!gdbarch_update_p (info
))
6739 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6742 /* Show the current setting of the exact watchpoints flag. */
6745 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6746 struct cmd_list_element
*c
,
6749 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6752 /* Read a PPC instruction from memory. */
6755 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6757 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6758 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6760 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6763 /* Return non-zero if the instructions at PC match the series
6764 described in PATTERN, or zero otherwise. PATTERN is an array of
6765 'struct ppc_insn_pattern' objects, terminated by an entry whose
6768 When the match is successful, fill INSNS[i] with what PATTERN[i]
6769 matched. If PATTERN[i] is optional, and the instruction wasn't
6770 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
6771 INSNS should have as many elements as PATTERN, minus the terminator.
6772 Note that, if PATTERN contains optional instructions which aren't
6773 present in memory, then INSNS will have holes, so INSNS[i] isn't
6774 necessarily the i'th instruction in memory. */
6777 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6778 const struct ppc_insn_pattern
*pattern
,
6779 unsigned int *insns
)
6784 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6787 insn
= read_insn (frame
, pc
);
6789 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6795 else if (!pattern
[i
].optional
)
6802 /* Return the 'd' field of the d-form instruction INSN, properly
6806 ppc_insn_d_field (unsigned int insn
)
6808 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6811 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6812 zero bits concatenated at the right, and properly
6816 ppc_insn_ds_field (unsigned int insn
)
6818 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6821 /* Initialization code. */
6824 _initialize_rs6000_tdep (void)
6826 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6827 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6829 /* Initialize the standard target descriptions. */
6830 initialize_tdesc_powerpc_32 ();
6831 initialize_tdesc_powerpc_altivec32 ();
6832 initialize_tdesc_powerpc_vsx32 ();
6833 initialize_tdesc_powerpc_403 ();
6834 initialize_tdesc_powerpc_403gc ();
6835 initialize_tdesc_powerpc_405 ();
6836 initialize_tdesc_powerpc_505 ();
6837 initialize_tdesc_powerpc_601 ();
6838 initialize_tdesc_powerpc_602 ();
6839 initialize_tdesc_powerpc_603 ();
6840 initialize_tdesc_powerpc_604 ();
6841 initialize_tdesc_powerpc_64 ();
6842 initialize_tdesc_powerpc_altivec64 ();
6843 initialize_tdesc_powerpc_vsx64 ();
6844 initialize_tdesc_powerpc_7400 ();
6845 initialize_tdesc_powerpc_750 ();
6846 initialize_tdesc_powerpc_860 ();
6847 initialize_tdesc_powerpc_e500 ();
6848 initialize_tdesc_rs6000 ();
6850 /* Add root prefix command for all "set powerpc"/"show powerpc"
6852 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6853 _("Various PowerPC-specific commands."),
6854 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6856 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6857 _("Various PowerPC-specific commands."),
6858 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6860 /* Add a command to allow the user to force the ABI. */
6861 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6862 &powerpc_soft_float_global
,
6863 _("Set whether to use a soft-float ABI."),
6864 _("Show whether to use a soft-float ABI."),
6866 powerpc_set_soft_float
, NULL
,
6867 &setpowerpccmdlist
, &showpowerpccmdlist
);
6869 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6870 &powerpc_vector_abi_string
,
6871 _("Set the vector ABI."),
6872 _("Show the vector ABI."),
6873 NULL
, powerpc_set_vector_abi
, NULL
,
6874 &setpowerpccmdlist
, &showpowerpccmdlist
);
6876 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6877 &target_exact_watchpoints
,
6879 Set whether to use just one debug register for watchpoints on scalars."),
6881 Show whether to use just one debug register for watchpoints on scalars."),
6883 If true, GDB will use only one debug register when watching a variable of\n\
6884 scalar type, thus assuming that the variable is accessed through the address\n\
6885 of its first byte."),
6886 NULL
, show_powerpc_exact_watchpoints
,
6887 &setpowerpccmdlist
, &showpowerpccmdlist
);